1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
50
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
52 {
53 struct ixgbe_mac_info *mac = &hw->mac;
54
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
56
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
64
65 } else {
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
69 }
70
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
74 } else {
75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
76 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
77 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
80 } else {
81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
82 }
83 }
84 }
85
86 /**
87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
88 * @hw: pointer to hardware structure
89 *
90 * Initialize any function pointers that were not able to be
91 * set during init_shared_code because the PHY/SFP type was
92 * not known. Perform the SFP init if necessary.
93 *
94 **/
95 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
96 {
97 struct ixgbe_mac_info *mac = &hw->mac;
98 struct ixgbe_phy_info *phy = &hw->phy;
99 s32 ret_val = IXGBE_SUCCESS;
100
101 DEBUGFUNC("ixgbe_init_phy_ops_82599");
102
103 /* Identify the PHY or SFP module */
104 ret_val = phy->ops.identify(hw);
105 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
106 goto init_phy_ops_out;
107
108 /* Setup function pointers based on detected SFP module and speeds */
109 ixgbe_init_mac_link_ops_82599(hw);
110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
111 hw->phy.ops.reset = NULL;
112
113 /* If copper media, overwrite with copper function pointers */
114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_generic;
118 }
119
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
122 case ixgbe_phy_tn:
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
127 break;
128 default:
129 break;
130 }
131 init_phy_ops_out:
132 return ret_val;
133 }
134
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
136 {
137 s32 ret_val = IXGBE_SUCCESS;
138 u32 reg_anlp1 = 0;
139 u32 i = 0;
140 u16 list_offset, data_offset, data_value;
141
142 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143
144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
145 ixgbe_init_mac_link_ops_82599(hw);
146
147 hw->phy.ops.reset = NULL;
148
149 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 &data_offset);
151 if (ret_val != IXGBE_SUCCESS)
152 goto setup_sfp_out;
153
154 /* PHY config will finish before releasing the semaphore */
155 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
156 IXGBE_GSSR_MAC_CSR_SM);
157 if (ret_val != IXGBE_SUCCESS) {
158 ret_val = IXGBE_ERR_SWFW_SYNC;
159 goto setup_sfp_out;
160 }
161
162 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
163 while (data_value != 0xffff) {
164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
165 IXGBE_WRITE_FLUSH(hw);
166 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
167 }
168
169 /* Release the semaphore */
170 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
171 /* Delay obtaining semaphore again to allow FW access */
172 msec_delay(hw->eeprom.semaphore_delay);
173
174 /* Now restart DSP by setting Restart_AN and clearing LMS */
175 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
176 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
177 IXGBE_AUTOC_AN_RESTART));
178
179 /* Wait for AN to leave state 0 */
180 for (i = 0; i < 10; i++) {
181 msec_delay(4);
182 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
183 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
184 break;
185 }
186 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
187 DEBUGOUT("sfp module setup not complete\n");
188 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
189 goto setup_sfp_out;
190 }
191
192 /* Restart DSP by setting Restart_AN and return to SFI mode */
193 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
194 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
195 IXGBE_AUTOC_AN_RESTART));
196 }
197
198 setup_sfp_out:
199 return ret_val;
200 }
201
202 /**
203 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
204 * @hw: pointer to hardware structure
205 *
206 * Initialize the function pointers and assign the MAC type for 82599.
207 * Does not touch the hardware.
208 **/
209
210 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
211 {
212 struct ixgbe_mac_info *mac = &hw->mac;
213 struct ixgbe_phy_info *phy = &hw->phy;
214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
215 s32 ret_val;
216
217 DEBUGFUNC("ixgbe_init_ops_82599");
218
219 ret_val = ixgbe_init_phy_ops_generic(hw);
220 ret_val = ixgbe_init_ops_generic(hw);
221
222 /* PHY */
223 phy->ops.identify = &ixgbe_identify_phy_82599;
224 phy->ops.init = &ixgbe_init_phy_ops_82599;
225
226 /* MAC */
227 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
228 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
229 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
230 mac->ops.get_supported_physical_layer =
231 &ixgbe_get_supported_physical_layer_82599;
232 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
233 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
234 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
235 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
236 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
237 mac->ops.start_hw = &ixgbe_start_hw_82599;
238 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
239 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
240 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
241 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
242 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
243
244 /* RAR, Multicast, VLAN */
245 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
246 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
247 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
248 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
249 mac->rar_highwater = 1;
250 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
251 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
252 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
253 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
254 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
255 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
256 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
257
258 /* Link */
259 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
260 mac->ops.check_link = &ixgbe_check_mac_link_generic;
261 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
262 ixgbe_init_mac_link_ops_82599(hw);
263
264 mac->mcft_size = 128;
265 mac->vft_size = 128;
266 mac->num_rar_entries = 128;
267 mac->rx_pb_size = 512;
268 mac->max_tx_queues = 128;
269 mac->max_rx_queues = 128;
270 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
271
272 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
273 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
274
275 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
276
277 /* EEPROM */
278 eeprom->ops.read = &ixgbe_read_eeprom_82599;
279 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
280
281 /* Manageability interface */
282 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
283
284
285 return ret_val;
286 }
287
288 /**
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
292 * @negotiation: TRUE when autoneg or autotry is enabled
293 *
294 * Determines the link capabilities by reading the AUTOC register.
295 **/
296 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
298 bool *negotiation)
299 {
300 s32 status = IXGBE_SUCCESS;
301 u32 autoc = 0;
302
303 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
304
305
306 /* Check if 1G SFP module. */
307 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
308 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
310 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
311 *speed = IXGBE_LINK_SPEED_1GB_FULL;
312 *negotiation = TRUE;
313 goto out;
314 }
315
316 /*
317 * Determine link capabilities based on the stored value of AUTOC,
318 * which represents EEPROM defaults. If AUTOC value has not
319 * been stored, use the current register values.
320 */
321 if (hw->mac.orig_link_settings_stored)
322 autoc = hw->mac.orig_autoc;
323 else
324 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
325
326 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
327 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
328 *speed = IXGBE_LINK_SPEED_1GB_FULL;
329 *negotiation = FALSE;
330 break;
331
332 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
333 *speed = IXGBE_LINK_SPEED_10GB_FULL;
334 *negotiation = FALSE;
335 break;
336
337 case IXGBE_AUTOC_LMS_1G_AN:
338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 *negotiation = TRUE;
340 break;
341
342 case IXGBE_AUTOC_LMS_10G_SERIAL:
343 *speed = IXGBE_LINK_SPEED_10GB_FULL;
344 *negotiation = FALSE;
345 break;
346
347 case IXGBE_AUTOC_LMS_KX4_KX_KR:
348 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
349 *speed = IXGBE_LINK_SPEED_UNKNOWN;
350 if (autoc & IXGBE_AUTOC_KR_SUPP)
351 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
352 if (autoc & IXGBE_AUTOC_KX4_SUPP)
353 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
354 if (autoc & IXGBE_AUTOC_KX_SUPP)
355 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
356 *negotiation = TRUE;
357 break;
358
359 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
360 *speed = IXGBE_LINK_SPEED_100_FULL;
361 if (autoc & IXGBE_AUTOC_KR_SUPP)
362 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
363 if (autoc & IXGBE_AUTOC_KX4_SUPP)
364 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
365 if (autoc & IXGBE_AUTOC_KX_SUPP)
366 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
367 *negotiation = TRUE;
368 break;
369
370 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
371 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
372 *negotiation = FALSE;
373 break;
374
375 default:
376 status = IXGBE_ERR_LINK_SETUP;
377 goto out;
378 }
379
380 if (hw->phy.multispeed_fiber) {
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
382 IXGBE_LINK_SPEED_1GB_FULL;
383 *negotiation = TRUE;
384 }
385
386 out:
387 return status;
388 }
389
390 /**
391 * ixgbe_get_media_type_82599 - Get media type
392 * @hw: pointer to hardware structure
393 *
394 * Returns the media type (fiber, copper, backplane)
395 **/
396 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
397 {
398 enum ixgbe_media_type media_type;
399
400 DEBUGFUNC("ixgbe_get_media_type_82599");
401
402 /* Detect if there is a copper PHY attached. */
403 switch (hw->phy.type) {
404 case ixgbe_phy_cu_unknown:
405 case ixgbe_phy_tn:
406 media_type = ixgbe_media_type_copper;
407 goto out;
408 default:
409 break;
410 }
411
412 switch (hw->device_id) {
413 case IXGBE_DEV_ID_82599_KX4:
414 case IXGBE_DEV_ID_82599_KX4_MEZZ:
415 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
416 case IXGBE_DEV_ID_82599_KR:
417 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
418 case IXGBE_DEV_ID_82599_XAUI_LOM:
419 /* Default device ID is mezzanine card KX/KX4 */
420 media_type = ixgbe_media_type_backplane;
421 break;
422 case IXGBE_DEV_ID_82599_SFP:
423 case IXGBE_DEV_ID_82599_SFP_FCOE:
424 case IXGBE_DEV_ID_82599_SFP_EM:
425 case IXGBE_DEV_ID_82599_SFP_SF2:
426 case IXGBE_DEV_ID_82599EN_SFP:
427 media_type = ixgbe_media_type_fiber;
428 break;
429 case IXGBE_DEV_ID_82599_CX4:
430 media_type = ixgbe_media_type_cx4;
431 break;
432 case IXGBE_DEV_ID_82599_T3_LOM:
433 media_type = ixgbe_media_type_copper;
434 break;
435 default:
436 media_type = ixgbe_media_type_unknown;
437 break;
438 }
439 out:
440 return media_type;
441 }
442
443 /**
444 * ixgbe_start_mac_link_82599 - Setup MAC link settings
445 * @hw: pointer to hardware structure
446 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
447 *
448 * Configures link settings based on values in the ixgbe_hw struct.
449 * Restarts the link. Performs autonegotiation if needed.
450 **/
451 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
452 bool autoneg_wait_to_complete)
453 {
454 u32 autoc_reg;
455 u32 links_reg;
456 u32 i;
457 s32 status = IXGBE_SUCCESS;
458
459 DEBUGFUNC("ixgbe_start_mac_link_82599");
460
461
462 /* Restart link */
463 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
464 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
465 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
466
467 /* Only poll for autoneg to complete if specified to do so */
468 if (autoneg_wait_to_complete) {
469 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
470 IXGBE_AUTOC_LMS_KX4_KX_KR ||
471 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
472 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
473 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
474 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
475 links_reg = 0; /* Just in case Autoneg time = 0 */
476 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
477 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
478 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
479 break;
480 msec_delay(100);
481 }
482 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
483 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
484 DEBUGOUT("Autoneg did not complete.\n");
485 }
486 }
487 }
488
489 /* Add delay to filter out noises during initial link setup */
490 msec_delay(50);
491
492 return status;
493 }
494
495 /**
496 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
497 * @hw: pointer to hardware structure
498 *
499 * The base drivers may require better control over SFP+ module
500 * PHY states. This includes selectively shutting down the Tx
501 * laser on the PHY, effectively halting physical link.
502 **/
503 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
504 {
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
506
507 /* Disable tx laser; allow 100us to go dark per spec */
508 esdp_reg |= IXGBE_ESDP_SDP3;
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
510 IXGBE_WRITE_FLUSH(hw);
511 usec_delay(100);
512 }
513
514 /**
515 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
516 * @hw: pointer to hardware structure
517 *
518 * The base drivers may require better control over SFP+ module
519 * PHY states. This includes selectively turning on the Tx
520 * laser on the PHY, effectively starting physical link.
521 **/
522 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
523 {
524 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
525
526 /* Enable tx laser; allow 100ms to light up */
527 esdp_reg &= ~IXGBE_ESDP_SDP3;
528 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
529 IXGBE_WRITE_FLUSH(hw);
530 msec_delay(100);
531 }
532
533 /**
534 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
535 * @hw: pointer to hardware structure
536 *
537 * When the driver changes the link speeds that it can support,
538 * it sets autotry_restart to TRUE to indicate that we need to
539 * initiate a new autotry session with the link partner. To do
540 * so, we set the speed then disable and re-enable the tx laser, to
541 * alert the link partner that it also needs to restart autotry on its
542 * end. This is consistent with TRUE clause 37 autoneg, which also
543 * involves a loss of signal.
544 **/
545 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
546 {
547 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
548
549 if (hw->mac.autotry_restart) {
550 ixgbe_disable_tx_laser_multispeed_fiber(hw);
551 ixgbe_enable_tx_laser_multispeed_fiber(hw);
552 hw->mac.autotry_restart = FALSE;
553 }
554 }
555
556 /**
557 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
558 * @hw: pointer to hardware structure
559 * @speed: new link speed
560 * @autoneg: TRUE if autonegotiation enabled
561 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
562 *
563 * Set the link speed in the AUTOC register and restarts link.
564 **/
565 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
566 ixgbe_link_speed speed, bool autoneg,
567 bool autoneg_wait_to_complete)
568 {
569 s32 status = IXGBE_SUCCESS;
570 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
571 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
572 u32 speedcnt = 0;
573 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
574 u32 i = 0;
575 bool link_up = FALSE;
576 bool negotiation;
577
578 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
579
580 /* Mask off requested but non-supported speeds */
581 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
582 if (status != IXGBE_SUCCESS)
583 return status;
584
585 speed &= link_speed;
586
587 /*
588 * Try each speed one by one, highest priority first. We do this in
589 * software because 10gb fiber doesn't support speed autonegotiation.
590 */
591 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
592 speedcnt++;
593 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
594
595 /* If we already have link at this speed, just jump out */
596 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
597 if (status != IXGBE_SUCCESS)
598 return status;
599
600 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
601 goto out;
602
603 /* Set the module link speed */
604 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
606 IXGBE_WRITE_FLUSH(hw);
607
608 /* Allow module to change analog characteristics (1G->10G) */
609 msec_delay(40);
610
611 status = ixgbe_setup_mac_link_82599(hw,
612 IXGBE_LINK_SPEED_10GB_FULL,
613 autoneg,
614 autoneg_wait_to_complete);
615 if (status != IXGBE_SUCCESS)
616 return status;
617
618 /* Flap the tx laser if it has not already been done */
619 ixgbe_flap_tx_laser(hw);
620
621 /*
622 * Wait for the controller to acquire link. Per IEEE 802.3ap,
623 * Section 73.10.2, we may have to wait up to 500ms if KR is
624 * attempted. 82599 uses the same timing for 10g SFI.
625 */
626 for (i = 0; i < 5; i++) {
627 /* Wait for the link partner to also set speed */
628 msec_delay(100);
629
630 /* If we have link, just jump out */
631 status = ixgbe_check_link(hw, &link_speed,
632 &link_up, FALSE);
633 if (status != IXGBE_SUCCESS)
634 return status;
635
636 if (link_up)
637 goto out;
638 }
639 }
640
641 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
642 speedcnt++;
643 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
644 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
645
646 /* If we already have link at this speed, just jump out */
647 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
648 if (status != IXGBE_SUCCESS)
649 return status;
650
651 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
652 goto out;
653
654 /* Set the module link speed */
655 esdp_reg &= ~IXGBE_ESDP_SDP5;
656 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
658 IXGBE_WRITE_FLUSH(hw);
659
660 /* Allow module to change analog characteristics (10G->1G) */
661 msec_delay(40);
662
663 status = ixgbe_setup_mac_link_82599(hw,
664 IXGBE_LINK_SPEED_1GB_FULL,
665 autoneg,
666 autoneg_wait_to_complete);
667 if (status != IXGBE_SUCCESS)
668 return status;
669
670 /* Flap the tx laser if it has not already been done */
671 ixgbe_flap_tx_laser(hw);
672
673 /* Wait for the link partner to also set speed */
674 msec_delay(100);
675
676 /* If we have link, just jump out */
677 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
678 if (status != IXGBE_SUCCESS)
679 return status;
680
681 if (link_up)
682 goto out;
683 }
684
685 /*
686 * We didn't get link. Configure back to the highest speed we tried,
687 * (if there was more than one). We call ourselves back with just the
688 * single highest speed that the user requested.
689 */
690 if (speedcnt > 1)
691 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
692 highest_link_speed, autoneg, autoneg_wait_to_complete);
693
694 out:
695 /* Set autoneg_advertised value based on input link speed */
696 hw->phy.autoneg_advertised = 0;
697
698 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
699 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
700
701 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
703
704 return status;
705 }
706
707 /**
708 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
709 * @hw: pointer to hardware structure
710 * @speed: new link speed
711 * @autoneg: TRUE if autonegotiation enabled
712 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
713 *
714 * Implements the Intel SmartSpeed algorithm.
715 **/
716 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
717 ixgbe_link_speed speed, bool autoneg,
718 bool autoneg_wait_to_complete)
719 {
720 s32 status = IXGBE_SUCCESS;
721 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
722 s32 i, j;
723 bool link_up = FALSE;
724 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
725
726 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
727
728 /* Set autoneg_advertised value based on input link speed */
729 hw->phy.autoneg_advertised = 0;
730
731 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
732 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
733
734 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
735 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
736
737 if (speed & IXGBE_LINK_SPEED_100_FULL)
738 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
739
740 /*
741 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
742 * autoneg advertisement if link is unable to be established at the
743 * highest negotiated rate. This can sometimes happen due to integrity
744 * issues with the physical media connection.
745 */
746
747 /* First, try to get link with full advertisement */
748 hw->phy.smart_speed_active = FALSE;
749 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
750 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
751 autoneg_wait_to_complete);
752 if (status != IXGBE_SUCCESS)
753 goto out;
754
755 /*
756 * Wait for the controller to acquire link. Per IEEE 802.3ap,
757 * Section 73.10.2, we may have to wait up to 500ms if KR is
758 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
759 * Table 9 in the AN MAS.
760 */
761 for (i = 0; i < 5; i++) {
762 msec_delay(100);
763
764 /* If we have link, just jump out */
765 status = ixgbe_check_link(hw, &link_speed, &link_up,
766 FALSE);
767 if (status != IXGBE_SUCCESS)
768 goto out;
769
770 if (link_up)
771 goto out;
772 }
773 }
774
775 /*
776 * We didn't get link. If we advertised KR plus one of KX4/KX
777 * (or BX4/BX), then disable KR and try again.
778 */
779 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
780 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
781 goto out;
782
783 /* Turn SmartSpeed on to disable KR support */
784 hw->phy.smart_speed_active = TRUE;
785 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
786 autoneg_wait_to_complete);
787 if (status != IXGBE_SUCCESS)
788 goto out;
789
790 /*
791 * Wait for the controller to acquire link. 600ms will allow for
792 * the AN link_fail_inhibit_timer as well for multiple cycles of
793 * parallel detect, both 10g and 1g. This allows for the maximum
794 * connect attempts as defined in the AN MAS table 73-7.
795 */
796 for (i = 0; i < 6; i++) {
797 msec_delay(100);
798
799 /* If we have link, just jump out */
800 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
801 if (status != IXGBE_SUCCESS)
802 goto out;
803
804 if (link_up)
805 goto out;
806 }
807
808 /* We didn't get link. Turn SmartSpeed back off. */
809 hw->phy.smart_speed_active = FALSE;
810 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
811 autoneg_wait_to_complete);
812
813 out:
814 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
815 DEBUGOUT("Smartspeed has downgraded the link speed "
816 "from the maximum advertised\n");
817 return status;
818 }
819
820 /**
821 * ixgbe_setup_mac_link_82599 - Set MAC link speed
822 * @hw: pointer to hardware structure
823 * @speed: new link speed
824 * @autoneg: TRUE if autonegotiation enabled
825 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
826 *
827 * Set the link speed in the AUTOC register and restarts link.
828 **/
829 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
830 ixgbe_link_speed speed, bool autoneg,
831 bool autoneg_wait_to_complete)
832 {
833 s32 status = IXGBE_SUCCESS;
834 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
835 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
836 u32 start_autoc = autoc;
837 u32 orig_autoc = 0;
838 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
839 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
840 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
841 u32 links_reg;
842 u32 i;
843 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
844
845 DEBUGFUNC("ixgbe_setup_mac_link_82599");
846
847 /* Check to see if speed passed in is supported. */
848 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
849 if (status != IXGBE_SUCCESS)
850 goto out;
851
852 speed &= link_capabilities;
853
854 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
855 status = IXGBE_ERR_LINK_SETUP;
856 goto out;
857 }
858
859 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
860 if (hw->mac.orig_link_settings_stored)
861 orig_autoc = hw->mac.orig_autoc;
862 else
863 orig_autoc = autoc;
864
865 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
866 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
867 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
868 /* Set KX4/KX/KR support according to speed requested */
869 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
870 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
871 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
872 autoc |= IXGBE_AUTOC_KX4_SUPP;
873 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
874 (hw->phy.smart_speed_active == FALSE))
875 autoc |= IXGBE_AUTOC_KR_SUPP;
876 }
877 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878 autoc |= IXGBE_AUTOC_KX_SUPP;
879 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
880 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
881 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
882 /* Switch from 1G SFI to 10G SFI if requested */
883 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
884 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
885 autoc &= ~IXGBE_AUTOC_LMS_MASK;
886 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
887 }
888 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
889 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
890 /* Switch from 10G SFI to 1G SFI if requested */
891 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
892 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
893 autoc &= ~IXGBE_AUTOC_LMS_MASK;
894 if (autoneg)
895 autoc |= IXGBE_AUTOC_LMS_1G_AN;
896 else
897 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
898 }
899 }
900
901 if (autoc != start_autoc) {
902 /* Restart link */
903 autoc |= IXGBE_AUTOC_AN_RESTART;
904 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
905
906 /* Only poll for autoneg to complete if specified to do so */
907 if (autoneg_wait_to_complete) {
908 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
909 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
910 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
911 links_reg = 0; /*Just in case Autoneg time=0*/
912 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
913 links_reg =
914 IXGBE_READ_REG(hw, IXGBE_LINKS);
915 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
916 break;
917 msec_delay(100);
918 }
919 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
920 status =
921 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
922 DEBUGOUT("Autoneg did not complete.\n");
923 }
924 }
925 }
926
927 /* Add delay to filter out noises during initial link setup */
928 msec_delay(50);
929 }
930
931 out:
932 return status;
933 }
934
935 /**
936 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
937 * @hw: pointer to hardware structure
938 * @speed: new link speed
939 * @autoneg: TRUE if autonegotiation enabled
940 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
941 *
942 * Restarts link on PHY and MAC based on settings passed in.
943 **/
944 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
945 ixgbe_link_speed speed,
946 bool autoneg,
947 bool autoneg_wait_to_complete)
948 {
949 s32 status;
950
951 DEBUGFUNC("ixgbe_setup_copper_link_82599");
952
953 /* Setup the PHY according to input speed */
954 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
955 autoneg_wait_to_complete);
956 if (status == IXGBE_SUCCESS) {
957 /* Set up MAC */
958 status =
959 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
960 }
961
962 return status;
963 }
964
965 /**
966 * ixgbe_reset_hw_82599 - Perform hardware reset
967 * @hw: pointer to hardware structure
968 *
969 * Resets the hardware by resetting the transmit and receive units, masks
970 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
971 * reset.
972 **/
973 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
974 {
975 ixgbe_link_speed link_speed;
976 s32 status;
977 u32 ctrl, i, autoc, autoc2;
978 bool link_up = FALSE;
979
980 DEBUGFUNC("ixgbe_reset_hw_82599");
981
982 /* Call adapter stop to disable tx/rx and clear interrupts */
983 status = hw->mac.ops.stop_adapter(hw);
984 if (status != IXGBE_SUCCESS)
985 goto reset_hw_out;
986
987 /* flush pending Tx transactions */
988 ixgbe_clear_tx_pending(hw);
989
990 /* PHY ops must be identified and initialized prior to reset */
991
992 /* Identify PHY and related function pointers */
993 status = hw->phy.ops.init(hw);
994
995 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
996 goto reset_hw_out;
997
998 /* Setup SFP module if there is one present. */
999 if (hw->phy.sfp_setup_needed) {
1000 status = hw->mac.ops.setup_sfp(hw);
1001 hw->phy.sfp_setup_needed = FALSE;
1002 }
1003
1004 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1005 goto reset_hw_out;
1006
1007 /* Reset PHY */
1008 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1009 hw->phy.ops.reset(hw);
1010
1011 mac_reset_top:
1012 /*
1013 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1014 * If link reset is used when link is up, it might reset the PHY when
1015 * mng is using it. If link is down or the flag to force full link
1016 * reset is set, then perform link reset.
1017 */
1018 ctrl = IXGBE_CTRL_LNK_RST;
1019 if (!hw->force_full_reset) {
1020 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1021 if (link_up)
1022 ctrl = IXGBE_CTRL_RST;
1023 }
1024
1025 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1026 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1027 IXGBE_WRITE_FLUSH(hw);
1028
1029 /* Poll for reset bit to self-clear indicating reset is complete */
1030 for (i = 0; i < 10; i++) {
1031 usec_delay(1);
1032 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1033 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1034 break;
1035 }
1036
1037 if (ctrl & IXGBE_CTRL_RST_MASK) {
1038 status = IXGBE_ERR_RESET_FAILED;
1039 DEBUGOUT("Reset polling failed to complete.\n");
1040 }
1041
1042 msec_delay(50);
1043
1044 /*
1045 * Double resets are required for recovery from certain error
1046 * conditions. Between resets, it is necessary to stall to allow time
1047 * for any pending HW events to complete.
1048 */
1049 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1050 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1051 goto mac_reset_top;
1052 }
1053
1054 /*
1055 * Store the original AUTOC/AUTOC2 values if they have not been
1056 * stored off yet. Otherwise restore the stored original
1057 * values since the reset operation sets back to defaults.
1058 */
1059 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1060 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1061 if (hw->mac.orig_link_settings_stored == FALSE) {
1062 hw->mac.orig_autoc = autoc;
1063 hw->mac.orig_autoc2 = autoc2;
1064 hw->mac.orig_link_settings_stored = TRUE;
1065 } else {
1066 if (autoc != hw->mac.orig_autoc)
1067 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1068 IXGBE_AUTOC_AN_RESTART));
1069
1070 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1071 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1072 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1073 autoc2 |= (hw->mac.orig_autoc2 &
1074 IXGBE_AUTOC2_UPPER_MASK);
1075 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1076 }
1077 }
1078
1079 /* Store the permanent mac address */
1080 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1081
1082 /*
1083 * Store MAC address from RAR0, clear receive address registers, and
1084 * clear the multicast table. Also reset num_rar_entries to 128,
1085 * since we modify this value when programming the SAN MAC address.
1086 */
1087 hw->mac.num_rar_entries = 128;
1088 hw->mac.ops.init_rx_addrs(hw);
1089
1090 /* Store the permanent SAN mac address */
1091 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1092
1093 /* Add the SAN MAC address to the RAR only if it's a valid address */
1094 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1095 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1096 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1097
1098 /* Save the SAN MAC RAR index */
1099 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1100
1101 /* Reserve the last RAR for the SAN MAC address */
1102 hw->mac.num_rar_entries--;
1103 }
1104
1105 /* Store the alternative WWNN/WWPN prefix */
1106 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1107 &hw->mac.wwpn_prefix);
1108
1109 reset_hw_out:
1110 return status;
1111 }
1112
1113 /**
1114 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1115 * @hw: pointer to hardware structure
1116 **/
1117 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1118 {
1119 int i;
1120 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1121 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1122
1123 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1124
1125 /*
1126 * Before starting reinitialization process,
1127 * FDIRCMD.CMD must be zero.
1128 */
1129 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1130 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1131 IXGBE_FDIRCMD_CMD_MASK))
1132 break;
1133 usec_delay(10);
1134 }
1135 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1136 DEBUGOUT("Flow Director previous command isn't complete, "
1137 "aborting table re-initialization.\n");
1138 return IXGBE_ERR_FDIR_REINIT_FAILED;
1139 }
1140
1141 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1142 IXGBE_WRITE_FLUSH(hw);
1143 /*
1144 * 82599 adapters flow director init flow cannot be restarted,
1145 * Workaround 82599 silicon errata by performing the following steps
1146 * before re-writing the FDIRCTRL control register with the same value.
1147 * - write 1 to bit 8 of FDIRCMD register &
1148 * - write 0 to bit 8 of FDIRCMD register
1149 */
1150 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1151 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1152 IXGBE_FDIRCMD_CLEARHT));
1153 IXGBE_WRITE_FLUSH(hw);
1154 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1155 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1156 ~IXGBE_FDIRCMD_CLEARHT));
1157 IXGBE_WRITE_FLUSH(hw);
1158 /*
1159 * Clear FDIR Hash register to clear any leftover hashes
1160 * waiting to be programmed.
1161 */
1162 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1163 IXGBE_WRITE_FLUSH(hw);
1164
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1166 IXGBE_WRITE_FLUSH(hw);
1167
1168 /* Poll init-done after we write FDIRCTRL register */
1169 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1170 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1171 IXGBE_FDIRCTRL_INIT_DONE)
1172 break;
1173 usec_delay(10);
1174 }
1175 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1176 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1177 return IXGBE_ERR_FDIR_REINIT_FAILED;
1178 }
1179
1180 /* Clear FDIR statistics registers (read to clear) */
1181 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1182 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1183 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1184 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1185 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1186
1187 return IXGBE_SUCCESS;
1188 }
1189
1190 /**
1191 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1192 * @hw: pointer to hardware structure
1193 * @fdirctrl: value to write to flow director control register
1194 **/
1195 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1196 {
1197 int i;
1198
1199 DEBUGFUNC("ixgbe_fdir_enable_82599");
1200
1201 /* Prime the keys for hashing */
1202 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1203 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1204
1205 /*
1206 * Poll init-done after we write the register. Estimated times:
1207 * 10G: PBALLOC = 11b, timing is 60us
1208 * 1G: PBALLOC = 11b, timing is 600us
1209 * 100M: PBALLOC = 11b, timing is 6ms
1210 *
1211 * Multiple these timings by 4 if under full Rx load
1212 *
1213 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1214 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1215 * this might not finish in our poll time, but we can live with that
1216 * for now.
1217 */
1218 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1219 IXGBE_WRITE_FLUSH(hw);
1220 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1221 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1222 IXGBE_FDIRCTRL_INIT_DONE)
1223 break;
1224 msec_delay(1);
1225 }
1226
1227 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1228 DEBUGOUT("Flow Director poll time exceeded!\n");
1229 }
1230
1231 /**
1232 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1233 * @hw: pointer to hardware structure
1234 * @fdirctrl: value to write to flow director control register, initially
1235 * contains just the value of the Rx packet buffer allocation
1236 **/
1237 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1238 {
1239 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1240
1241 /*
1242 * Continue setup of fdirctrl register bits:
1243 * Move the flexible bytes to use the ethertype - shift 6 words
1244 * Set the maximum length per hash bucket to 0xA filters
1245 * Send interrupt when 64 filters are left
1246 */
1247 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1248 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1249 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1250
1251 /* write hashes and fdirctrl register, poll for completion */
1252 ixgbe_fdir_enable_82599(hw, fdirctrl);
1253
1254 return IXGBE_SUCCESS;
1255 }
1256
1257 /**
1258 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1259 * @hw: pointer to hardware structure
1260 * @fdirctrl: value to write to flow director control register, initially
1261 * contains just the value of the Rx packet buffer allocation
1262 **/
1263 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1264 {
1265 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1266
1267 /*
1268 * Continue setup of fdirctrl register bits:
1269 * Turn perfect match filtering on
1270 * Report hash in RSS field of Rx wb descriptor
1271 * Initialize the drop queue
1272 * Move the flexible bytes to use the ethertype - shift 6 words
1273 * Set the maximum length per hash bucket to 0xA filters
1274 * Send interrupt when 64 (0x4 * 16) filters are left
1275 */
1276 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1277 IXGBE_FDIRCTRL_REPORT_STATUS |
1278 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1279 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1280 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1281 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1282
1283 /* write hashes and fdirctrl register, poll for completion */
1284 ixgbe_fdir_enable_82599(hw, fdirctrl);
1285
1286 return IXGBE_SUCCESS;
1287 }
1288
1289 /*
1290 * These defines allow us to quickly generate all of the necessary instructions
1291 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1292 * for values 0 through 15
1293 */
1294 #define IXGBE_ATR_COMMON_HASH_KEY \
1295 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1296 #ifdef lint
1297 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n)
1298 #else
1299 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1300 do { \
1301 u32 n = (_n); \
1302 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1303 common_hash ^= lo_hash_dword >> n; \
1304 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1305 bucket_hash ^= lo_hash_dword >> n; \
1306 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1307 sig_hash ^= lo_hash_dword << (16 - n); \
1308 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1309 common_hash ^= hi_hash_dword >> n; \
1310 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1311 bucket_hash ^= hi_hash_dword >> n; \
1312 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1313 sig_hash ^= hi_hash_dword << (16 - n); \
1314 } while (0);
1315 #endif
1316
1317 /**
1318 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1319 * @stream: input bitstream to compute the hash on
1320 *
1321 * This function is almost identical to the function above but contains
1322 * several optomizations such as unwinding all of the loops, letting the
1323 * compiler work out all of the conditional ifs since the keys are static
1324 * defines, and computing two keys at once since the hashed dword stream
1325 * will be the same for both keys.
1326 **/
1327 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1328 union ixgbe_atr_hash_dword common)
1329 {
1330 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1331 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1332
1333 /* record the flow_vm_vlan bits as they are a key part to the hash */
1334 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1335
1336 /* generate common hash dword */
1337 hi_hash_dword = IXGBE_NTOHL(common.dword);
1338
1339 /* low dword is word swapped version of common */
1340 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1341
1342 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1343 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1344
1345 /* Process bits 0 and 16 */
1346 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1347
1348 /*
1349 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1350 * delay this because bit 0 of the stream should not be processed
1351 * so we do not add the vlan until after bit 0 was processed
1352 */
1353 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1354
1355 /* Process remaining 30 bit of the key */
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1370 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1371
1372 /* combine common_hash result with signature and bucket hashes */
1373 bucket_hash ^= common_hash;
1374 bucket_hash &= IXGBE_ATR_HASH_MASK;
1375
1376 sig_hash ^= common_hash << 16;
1377 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1378
1379 /* return completed signature hash */
1380 return sig_hash ^ bucket_hash;
1381 }
1382
1383 /**
1384 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1385 * @hw: pointer to hardware structure
1386 * @input: unique input dword
1387 * @common: compressed common input dword
1388 * @queue: queue index to direct traffic to
1389 **/
1390 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1391 union ixgbe_atr_hash_dword input,
1392 union ixgbe_atr_hash_dword common,
1393 u8 queue)
1394 {
1395 u64 fdirhashcmd;
1396 u32 fdircmd;
1397
1398 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1399
1400 /*
1401 * Get the flow_type in order to program FDIRCMD properly
1402 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1403 */
1404 switch (input.formatted.flow_type) {
1405 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1406 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1407 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1408 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1409 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1410 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1411 break;
1412 default:
1413 DEBUGOUT(" Error on flow type input\n");
1414 return IXGBE_ERR_CONFIG;
1415 }
1416
1417 /* configure FDIRCMD register */
1418 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1419 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1420 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1421 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1422
1423 /*
1424 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1425 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1426 */
1427 fdirhashcmd = (u64)fdircmd << 32;
1428 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1429 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1430
1431 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1432
1433 return IXGBE_SUCCESS;
1434 }
1435
1436 #ifdef lint
1437 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n)
1438 #else
1439 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1440 do { \
1441 u32 n = (_n); \
1442 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1443 bucket_hash ^= lo_hash_dword >> n; \
1444 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1445 bucket_hash ^= hi_hash_dword >> n; \
1446 } while (0);
1447 #endif
1448 /**
1449 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1450 * @atr_input: input bitstream to compute the hash on
1451 * @input_mask: mask for the input bitstream
1452 *
1453 * This function serves two main purposes. First it applys the input_mask
1454 * to the atr_input resulting in a cleaned up atr_input data stream.
1455 * Secondly it computes the hash and stores it in the bkt_hash field at
1456 * the end of the input byte stream. This way it will be available for
1457 * future use without needing to recompute the hash.
1458 **/
1459 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1460 union ixgbe_atr_input *input_mask)
1461 {
1462
1463 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1464 u32 bucket_hash = 0;
1465
1466 /* Apply masks to input data */
1467 input->dword_stream[0] &= input_mask->dword_stream[0];
1468 input->dword_stream[1] &= input_mask->dword_stream[1];
1469 input->dword_stream[2] &= input_mask->dword_stream[2];
1470 input->dword_stream[3] &= input_mask->dword_stream[3];
1471 input->dword_stream[4] &= input_mask->dword_stream[4];
1472 input->dword_stream[5] &= input_mask->dword_stream[5];
1473 input->dword_stream[6] &= input_mask->dword_stream[6];
1474 input->dword_stream[7] &= input_mask->dword_stream[7];
1475 input->dword_stream[8] &= input_mask->dword_stream[8];
1476 input->dword_stream[9] &= input_mask->dword_stream[9];
1477 input->dword_stream[10] &= input_mask->dword_stream[10];
1478
1479 /* record the flow_vm_vlan bits as they are a key part to the hash */
1480 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1481
1482 /* generate common hash dword */
1483 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1484 input->dword_stream[2] ^
1485 input->dword_stream[3] ^
1486 input->dword_stream[4] ^
1487 input->dword_stream[5] ^
1488 input->dword_stream[6] ^
1489 input->dword_stream[7] ^
1490 input->dword_stream[8] ^
1491 input->dword_stream[9] ^
1492 input->dword_stream[10]);
1493
1494 /* low dword is word swapped version of common */
1495 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1496
1497 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1498 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1499
1500 /* Process bits 0 and 16 */
1501 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1502
1503 /*
1504 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1505 * delay this because bit 0 of the stream should not be processed
1506 * so we do not add the vlan until after bit 0 was processed
1507 */
1508 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1509
1510 /* Process remaining 30 bit of the key */
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1515 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1516 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1517 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1518 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1519 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1525 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1526
1527 /*
1528 * Limit hash to 13 bits since max bucket count is 8K.
1529 * Store result at the end of the input stream.
1530 */
1531 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1532 }
1533
1534 /**
1535 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1536 * @input_mask: mask to be bit swapped
1537 *
1538 * The source and destination port masks for flow director are bit swapped
1539 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1540 * generate a correctly swapped value we need to bit swap the mask and that
1541 * is what is accomplished by this function.
1542 **/
1543 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1544 {
1545 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1546 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1547 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1548 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1549 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1550 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1551 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1552 }
1553
1554 /*
1555 * These two macros are meant to address the fact that we have registers
1556 * that are either all or in part big-endian. As a result on big-endian
1557 * systems we will end up byte swapping the value to little-endian before
1558 * it is byte swapped again and written to the hardware in the original
1559 * big-endian format.
1560 */
1561 #define IXGBE_STORE_AS_BE32(_value) \
1562 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1563 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1564
1565 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1566 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1567
1568 #define IXGBE_STORE_AS_BE16(_value) \
1569 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1570
1571 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1572 union ixgbe_atr_input *input_mask)
1573 {
1574 /* mask IPv6 since it is currently not supported */
1575 u32 fdirm = IXGBE_FDIRM_DIPv6;
1576 u32 fdirtcpm;
1577
1578 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1579
1580 /*
1581 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1582 * are zero, then assume a full mask for that field. Also assume that
1583 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1584 * cannot be masked out in this implementation.
1585 *
1586 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1587 * point in time.
1588 */
1589
1590 /* verify bucket hash is cleared on hash generation */
1591 if (input_mask->formatted.bkt_hash)
1592 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1593
1594 /* Program FDIRM and verify partial masks */
1595 switch (input_mask->formatted.vm_pool & 0x7F) {
1596 case 0x0:
1597 fdirm |= IXGBE_FDIRM_POOL;
1598 /* FALLTHRU */
1599 case 0x7F:
1600 break;
1601 default:
1602 DEBUGOUT(" Error on vm pool mask\n");
1603 return IXGBE_ERR_CONFIG;
1604 }
1605
1606 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1607 case 0x0:
1608 fdirm |= IXGBE_FDIRM_L4P;
1609 if (input_mask->formatted.dst_port ||
1610 input_mask->formatted.src_port) {
1611 DEBUGOUT(" Error on src/dst port mask\n");
1612 return IXGBE_ERR_CONFIG;
1613 }
1614 /* FALLTHRU */
1615 case IXGBE_ATR_L4TYPE_MASK:
1616 break;
1617 default:
1618 DEBUGOUT(" Error on flow type mask\n");
1619 return IXGBE_ERR_CONFIG;
1620 }
1621
1622 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1623 case 0x0000:
1624 /* mask VLAN ID, fall through to mask VLAN priority */
1625 fdirm |= IXGBE_FDIRM_VLANID;
1626 /* FALLTHRU */
1627 case 0x0FFF:
1628 /* mask VLAN priority */
1629 fdirm |= IXGBE_FDIRM_VLANP;
1630 break;
1631 case 0xE000:
1632 /* mask VLAN ID only, fall through */
1633 fdirm |= IXGBE_FDIRM_VLANID;
1634 /* FALLTHRU */
1635 case 0xEFFF:
1636 /* no VLAN fields masked */
1637 break;
1638 default:
1639 DEBUGOUT(" Error on VLAN mask\n");
1640 return IXGBE_ERR_CONFIG;
1641 }
1642
1643 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1644 case 0x0000:
1645 /* Mask Flex Bytes, fall through */
1646 fdirm |= IXGBE_FDIRM_FLEX;
1647 /* FALLTHRU */
1648 case 0xFFFF:
1649 break;
1650 default:
1651 DEBUGOUT(" Error on flexible byte mask\n");
1652 return IXGBE_ERR_CONFIG;
1653 }
1654
1655 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1656 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1657
1658 /* store the TCP/UDP port masks, bit reversed from port layout */
1659 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1660
1661 /* write both the same so that UDP and TCP use the same mask */
1662 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1663 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1664
1665 /* store source and destination IP masks (big-enian) */
1666 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1667 ~input_mask->formatted.src_ip[0]);
1668 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1669 ~input_mask->formatted.dst_ip[0]);
1670
1671 return IXGBE_SUCCESS;
1672 }
1673
1674 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1675 union ixgbe_atr_input *input,
1676 u16 soft_id, u8 queue)
1677 {
1678 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1679
1680 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1681
1682 /* currently IPv6 is not supported, must be programmed with 0 */
1683 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1684 input->formatted.src_ip[0]);
1685 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1686 input->formatted.src_ip[1]);
1687 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1688 input->formatted.src_ip[2]);
1689
1690 /* record the source address (big-endian) */
1691 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1692
1693 /* record the first 32 bits of the destination address (big-endian) */
1694 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1695
1696 /* record source and destination port (little-endian)*/
1697 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1698 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1699 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1700 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1701
1702 /* record vlan (little-endian) and flex_bytes(big-endian) */
1703 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1704 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1705 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1706 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1707
1708 /* configure FDIRHASH register */
1709 fdirhash = input->formatted.bkt_hash;
1710 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1711 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1712
1713 /*
1714 * flush all previous writes to make certain registers are
1715 * programmed prior to issuing the command
1716 */
1717 IXGBE_WRITE_FLUSH(hw);
1718
1719 /* configure FDIRCMD register */
1720 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1721 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1722 if (queue == IXGBE_FDIR_DROP_QUEUE)
1723 fdircmd |= IXGBE_FDIRCMD_DROP;
1724 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1725 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1726 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1727
1728 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1729
1730 return IXGBE_SUCCESS;
1731 }
1732
1733 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1734 union ixgbe_atr_input *input,
1735 u16 soft_id)
1736 {
1737 u32 fdirhash;
1738 u32 fdircmd = 0;
1739 u32 retry_count;
1740 s32 err = IXGBE_SUCCESS;
1741
1742 /* configure FDIRHASH register */
1743 fdirhash = input->formatted.bkt_hash;
1744 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1745 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1746
1747 /* flush hash to HW */
1748 IXGBE_WRITE_FLUSH(hw);
1749
1750 /* Query if filter is present */
1751 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1752
1753 for (retry_count = 10; retry_count; retry_count--) {
1754 /* allow 10us for query to process */
1755 usec_delay(10);
1756 /* verify query completed successfully */
1757 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1758 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1759 break;
1760 }
1761
1762 if (!retry_count)
1763 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1764
1765 /* if filter exists in hardware then remove it */
1766 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1767 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1768 IXGBE_WRITE_FLUSH(hw);
1769 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1770 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1771 }
1772
1773 return err;
1774 }
1775
1776 /**
1777 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1778 * @hw: pointer to hardware structure
1779 * @input: input bitstream
1780 * @input_mask: mask for the input bitstream
1781 * @soft_id: software index for the filters
1782 * @queue: queue index to direct traffic to
1783 *
1784 * Note that the caller to this function must lock before calling, since the
1785 * hardware writes must be protected from one another.
1786 **/
1787 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1788 union ixgbe_atr_input *input,
1789 union ixgbe_atr_input *input_mask,
1790 u16 soft_id, u8 queue)
1791 {
1792 s32 err = IXGBE_ERR_CONFIG;
1793
1794 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1795
1796 /*
1797 * Check flow_type formatting, and bail out before we touch the hardware
1798 * if there's a configuration issue
1799 */
1800 switch (input->formatted.flow_type) {
1801 case IXGBE_ATR_FLOW_TYPE_IPV4:
1802 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1803 if (input->formatted.dst_port || input->formatted.src_port) {
1804 DEBUGOUT(" Error on src/dst port\n");
1805 return IXGBE_ERR_CONFIG;
1806 }
1807 break;
1808 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1809 if (input->formatted.dst_port || input->formatted.src_port) {
1810 DEBUGOUT(" Error on src/dst port\n");
1811 return IXGBE_ERR_CONFIG;
1812 }
1813 /* FALLTHRU */
1814 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1815 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1816 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1817 IXGBE_ATR_L4TYPE_MASK;
1818 break;
1819 default:
1820 DEBUGOUT(" Error on flow type input\n");
1821 return err;
1822 }
1823
1824 /* program input mask into the HW */
1825 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1826 if (err)
1827 return err;
1828
1829 /* apply mask and compute/store hash */
1830 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1831
1832 /* program filters to filter memory */
1833 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1834 soft_id, queue);
1835 }
1836
1837 /**
1838 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1839 * @hw: pointer to hardware structure
1840 * @reg: analog register to read
1841 * @val: read value
1842 *
1843 * Performs read operation to Omer analog register specified.
1844 **/
1845 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1846 {
1847 u32 core_ctl;
1848
1849 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1850
1851 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1852 (reg << 8));
1853 IXGBE_WRITE_FLUSH(hw);
1854 usec_delay(10);
1855 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1856 *val = (u8)core_ctl;
1857
1858 return IXGBE_SUCCESS;
1859 }
1860
1861 /**
1862 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1863 * @hw: pointer to hardware structure
1864 * @reg: atlas register to write
1865 * @val: value to write
1866 *
1867 * Performs write operation to Omer analog register specified.
1868 **/
1869 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1870 {
1871 u32 core_ctl;
1872
1873 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1874
1875 core_ctl = (reg << 8) | val;
1876 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1877 IXGBE_WRITE_FLUSH(hw);
1878 usec_delay(10);
1879
1880 return IXGBE_SUCCESS;
1881 }
1882
1883 /**
1884 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1885 * @hw: pointer to hardware structure
1886 *
1887 * Starts the hardware using the generic start_hw function
1888 * and the generation start_hw function.
1889 * Then performs revision-specific operations, if any.
1890 **/
1891 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1892 {
1893 s32 ret_val = IXGBE_SUCCESS;
1894
1895 DEBUGFUNC("ixgbe_start_hw_82599");
1896
1897 ret_val = ixgbe_start_hw_generic(hw);
1898 if (ret_val != IXGBE_SUCCESS)
1899 goto out;
1900
1901 ret_val = ixgbe_start_hw_gen2(hw);
1902 if (ret_val != IXGBE_SUCCESS)
1903 goto out;
1904
1905 /* We need to run link autotry after the driver loads */
1906 hw->mac.autotry_restart = TRUE;
1907
1908 if (ret_val == IXGBE_SUCCESS)
1909 ret_val = ixgbe_verify_fw_version_82599(hw);
1910 out:
1911 return ret_val;
1912 }
1913
1914 /**
1915 * ixgbe_identify_phy_82599 - Get physical layer module
1916 * @hw: pointer to hardware structure
1917 *
1918 * Determines the physical layer module found on the current adapter.
1919 * If PHY already detected, maintains current PHY type in hw struct,
1920 * otherwise executes the PHY detection routine.
1921 **/
1922 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1923 {
1924 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1925
1926 DEBUGFUNC("ixgbe_identify_phy_82599");
1927
1928 /* Detect PHY if not unknown - returns success if already detected. */
1929 status = ixgbe_identify_phy_generic(hw);
1930 if (status != IXGBE_SUCCESS) {
1931 /* 82599 10GBASE-T requires an external PHY */
1932 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1933 goto out;
1934 else
1935 status = ixgbe_identify_module_generic(hw);
1936 }
1937
1938 /* Set PHY type none if no PHY detected */
1939 if (hw->phy.type == ixgbe_phy_unknown) {
1940 hw->phy.type = ixgbe_phy_none;
1941 status = IXGBE_SUCCESS;
1942 }
1943
1944 /* Return error if SFP module has been detected but is not supported */
1945 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1946 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1947
1948 out:
1949 return status;
1950 }
1951
1952 /**
1953 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1954 * @hw: pointer to hardware structure
1955 *
1956 * Determines physical layer capabilities of the current configuration.
1957 **/
1958 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1959 {
1960 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1961 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1962 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1963 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1964 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1965 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1966 u16 ext_ability = 0;
1967 u8 comp_codes_10g = 0;
1968 u8 comp_codes_1g = 0;
1969
1970 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1971
1972 hw->phy.ops.identify(hw);
1973
1974 switch (hw->phy.type) {
1975 case ixgbe_phy_tn:
1976 case ixgbe_phy_cu_unknown:
1977 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1978 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1979 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1980 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1981 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1982 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1983 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1984 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1985 goto out;
1986 default:
1987 break;
1988 }
1989
1990 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1991 case IXGBE_AUTOC_LMS_1G_AN:
1992 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1993 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1994 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1995 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1996 goto out;
1997 }
1998 /* SFI mode so read SFP module */
1999 goto sfp_check;
2000 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2001 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2002 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2003 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2004 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2005 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2006 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2007 goto out;
2008 case IXGBE_AUTOC_LMS_10G_SERIAL:
2009 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2010 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2011 goto out;
2012 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2013 goto sfp_check;
2014 break;
2015 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2016 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2017 if (autoc & IXGBE_AUTOC_KX_SUPP)
2018 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2019 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2020 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2021 if (autoc & IXGBE_AUTOC_KR_SUPP)
2022 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2023 goto out;
2024 default:
2025 goto out;
2026 }
2027
2028 sfp_check:
2029 /* SFP check must be done last since DA modules are sometimes used to
2030 * test KR mode - we need to id KR mode correctly before SFP module.
2031 * Call identify_sfp because the pluggable module may have changed */
2032 hw->phy.ops.identify_sfp(hw);
2033 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2034 goto out;
2035
2036 switch (hw->phy.type) {
2037 case ixgbe_phy_sfp_passive_tyco:
2038 case ixgbe_phy_sfp_passive_unknown:
2039 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2040 break;
2041 case ixgbe_phy_sfp_ftl_active:
2042 case ixgbe_phy_sfp_active_unknown:
2043 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2044 break;
2045 case ixgbe_phy_sfp_avago:
2046 case ixgbe_phy_sfp_ftl:
2047 case ixgbe_phy_sfp_intel:
2048 case ixgbe_phy_sfp_unknown:
2049 hw->phy.ops.read_i2c_eeprom(hw,
2050 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2051 hw->phy.ops.read_i2c_eeprom(hw,
2052 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2053 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2054 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2055 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2056 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2057 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2058 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2059 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2060 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2061 break;
2062 default:
2063 break;
2064 }
2065
2066 out:
2067 return physical_layer;
2068 }
2069
2070 /**
2071 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2072 * @hw: pointer to hardware structure
2073 * @regval: register value to write to RXCTRL
2074 *
2075 * Enables the Rx DMA unit for 82599
2076 **/
2077 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2078 {
2079
2080 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2081
2082 /*
2083 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2084 * If traffic is incoming before we enable the Rx unit, it could hang
2085 * the Rx DMA unit. Therefore, make sure the security engine is
2086 * completely disabled prior to enabling the Rx unit.
2087 */
2088
2089 hw->mac.ops.disable_sec_rx_path(hw);
2090
2091 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2092
2093 hw->mac.ops.enable_sec_rx_path(hw);
2094
2095 return IXGBE_SUCCESS;
2096 }
2097
2098 /**
2099 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2100 * @hw: pointer to hardware structure
2101 *
2102 * Verifies that installed the firmware version is 0.6 or higher
2103 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2104 *
2105 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2106 * if the FW version is not supported.
2107 **/
2108 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2109 {
2110 s32 status = IXGBE_ERR_EEPROM_VERSION;
2111 u16 fw_offset, fw_ptp_cfg_offset;
2112 u16 fw_version = 0;
2113
2114 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2115
2116 /* firmware check is only necessary for SFI devices */
2117 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2118 status = IXGBE_SUCCESS;
2119 goto fw_version_out;
2120 }
2121
2122 /* get the offset to the Firmware Module block */
2123 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2124
2125 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2126 goto fw_version_out;
2127
2128 /* get the offset to the Pass Through Patch Configuration block */
2129 hw->eeprom.ops.read(hw, (fw_offset +
2130 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2131 &fw_ptp_cfg_offset);
2132
2133 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2134 goto fw_version_out;
2135
2136 /* get the firmware version */
2137 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2138 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2139
2140 if (fw_version > 0x5)
2141 status = IXGBE_SUCCESS;
2142
2143 fw_version_out:
2144 return status;
2145 }
2146
2147 /**
2148 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2149 * @hw: pointer to hardware structure
2150 *
2151 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2152 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2153 **/
2154 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2155 {
2156 bool lesm_enabled = FALSE;
2157 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2158 s32 status;
2159
2160 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2161
2162 /* get the offset to the Firmware Module block */
2163 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2164
2165 if ((status != IXGBE_SUCCESS) ||
2166 (fw_offset == 0) || (fw_offset == 0xFFFF))
2167 goto out;
2168
2169 /* get the offset to the LESM Parameters block */
2170 status = hw->eeprom.ops.read(hw, (fw_offset +
2171 IXGBE_FW_LESM_PARAMETERS_PTR),
2172 &fw_lesm_param_offset);
2173
2174 if ((status != IXGBE_SUCCESS) ||
2175 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2176 goto out;
2177
2178 /* get the lesm state word */
2179 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2180 IXGBE_FW_LESM_STATE_1),
2181 &fw_lesm_state);
2182
2183 if ((status == IXGBE_SUCCESS) &&
2184 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2185 lesm_enabled = TRUE;
2186
2187 out:
2188 return lesm_enabled;
2189 }
2190
2191 /**
2192 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2193 * fastest available method
2194 *
2195 * @hw: pointer to hardware structure
2196 * @offset: offset of word in EEPROM to read
2197 * @words: number of words
2198 * @data: word(s) read from the EEPROM
2199 *
2200 * Retrieves 16 bit word(s) read from EEPROM
2201 **/
2202 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2203 u16 words, u16 *data)
2204 {
2205 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2206 s32 ret_val = IXGBE_ERR_CONFIG;
2207
2208 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2209
2210 /*
2211 * If EEPROM is detected and can be addressed using 14 bits,
2212 * use EERD otherwise use bit bang
2213 */
2214 if ((eeprom->type == ixgbe_eeprom_spi) &&
2215 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2216 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2217 data);
2218 else
2219 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2220 words,
2221 data);
2222
2223 return ret_val;
2224 }
2225
2226 /**
2227 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2228 * fastest available method
2229 *
2230 * @hw: pointer to hardware structure
2231 * @offset: offset of word in the EEPROM to read
2232 * @data: word read from the EEPROM
2233 *
2234 * Reads a 16 bit word from the EEPROM
2235 **/
2236 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2237 u16 offset, u16 *data)
2238 {
2239 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2240 s32 ret_val = IXGBE_ERR_CONFIG;
2241
2242 DEBUGFUNC("ixgbe_read_eeprom_82599");
2243
2244 /*
2245 * If EEPROM is detected and can be addressed using 14 bits,
2246 * use EERD otherwise use bit bang
2247 */
2248 if ((eeprom->type == ixgbe_eeprom_spi) &&
2249 (offset <= IXGBE_EERD_MAX_ADDR))
2250 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2251 else
2252 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2253
2254 return ret_val;
2255 }
2256
2257