1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82598.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
59 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
60 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
61 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
62 u32 headroom, int strategy);
63
64 /**
65 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
66 * @hw: pointer to the HW structure
67 *
68 * The defaults for 82598 should be in the range of 50us to 50ms,
69 * however the hardware default for these parts is 500us to 1ms which is less
70 * than the 10ms recommended by the pci-e spec. To address this we need to
71 * increase the value to either 10ms to 250ms for capability version 1 config,
72 * or 16ms to 55ms for version 2.
73 **/
74 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
75 {
76 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
77 u16 pcie_devctl2;
78
79 /* only take action if timeout value is defaulted to 0 */
80 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
81 goto out;
82
83 /*
138 /* RAR, Multicast, VLAN */
139 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
140 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
141 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
142 mac->ops.set_vlvf = NULL;
143 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
144
145 /* Flow Control */
146 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
147
148 mac->mcft_size = 128;
149 mac->vft_size = 128;
150 mac->num_rar_entries = 16;
151 mac->rx_pb_size = 512;
152 mac->max_tx_queues = 32;
153 mac->max_rx_queues = 64;
154 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
155
156 /* SFP+ Module */
157 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
165
166 /* Manageability interface */
167 mac->ops.set_fw_drv_ver = NULL;
168
169 return ret_val;
170 }
171
172 /**
173 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
174 * @hw: pointer to hardware structure
175 *
176 * Initialize any function pointers that were not able to be
177 * set during init_shared_code because the PHY/SFP type was
700 *speed = IXGBE_LINK_SPEED_1GB_FULL;
701
702 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
703 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
704 *link_up = FALSE;
705
706 out:
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_setup_mac_link_82598 - Set MAC link speed
712 * @hw: pointer to hardware structure
713 * @speed: new link speed
714 * @autoneg: TRUE if autonegotiation enabled
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
720 ixgbe_link_speed speed, bool autoneg,
721 bool autoneg_wait_to_complete)
722 {
723 s32 status;
724 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
725 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
726 u32 autoc = curr_autoc;
727 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
728
729 DEBUGFUNC("ixgbe_setup_mac_link_82598");
730
731 /* Check to see if speed passed in is supported. */
732 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
733 if (status != IXGBE_SUCCESS)
734 return (status);
735 speed &= link_capabilities;
736
737 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
738 status = IXGBE_ERR_LINK_SETUP;
739
740 /* Set KX4/KX support according to speed requested */
741 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
742 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
750 }
751
752 if (status == IXGBE_SUCCESS) {
753 /*
754 * Setup and restart the link based on the new values in
755 * ixgbe_hw This will write the AUTOC register based on the new
756 * stored values
757 */
758 status = ixgbe_start_mac_link_82598(hw,
759 autoneg_wait_to_complete);
760 }
761
762 return status;
763 }
764
765
766 /**
767 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
768 * @hw: pointer to hardware structure
769 * @speed: new link speed
770 * @autoneg: TRUE if autonegotiation enabled
771 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
772 *
773 * Sets the link speed in the AUTOC register in the MAC and restarts link.
774 **/
775 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
776 ixgbe_link_speed speed,
777 bool autoneg,
778 bool autoneg_wait_to_complete)
779 {
780 s32 status;
781
782 DEBUGFUNC("ixgbe_setup_copper_link_82598");
783
784 /* Setup the PHY according to input speed */
785 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
786 autoneg_wait_to_complete);
787 if (status == IXGBE_SUCCESS) {
788 /* Set up MAC */
789 status =
790 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
791 }
792
793 return status;
794 }
795
796 /**
797 * ixgbe_reset_hw_82598 - Performs hardware reset
798 * @hw: pointer to hardware structure
799 *
800 * Resets the hardware by resetting the transmit and receive units, masks and
801 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
802 * reset.
803 **/
804 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
805 {
1089 * @reg: atlas register to write
1090 * @val: value to write
1091 *
1092 * Performs write operation to Atlas analog register specified.
1093 **/
1094 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1095 {
1096 u32 atlas_ctl;
1097
1098 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1099
1100 atlas_ctl = (reg << 8) | val;
1101 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1102 IXGBE_WRITE_FLUSH(hw);
1103 usec_delay(10);
1104
1105 return IXGBE_SUCCESS;
1106 }
1107
1108 /**
1109 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1110 * @hw: pointer to hardware structure
1111 * @byte_offset: EEPROM byte offset to read
1112 * @eeprom_data: value read
1113 *
1114 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1115 **/
1116 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1117 u8 *eeprom_data)
1118 {
1119 s32 status = IXGBE_SUCCESS;
1120 u16 sfp_addr = 0;
1121 u16 sfp_data = 0;
1122 u16 sfp_stat = 0;
1123 u32 i;
1124
1125 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1126
1127 if (hw->phy.type == ixgbe_phy_nl) {
1128 /*
1129 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1130 * 0xC30D. These registers are used to talk to the SFP+
1131 * module's EEPROM through the SDA/SCL (I2C) interface.
1132 */
1133 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1134 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1135 hw->phy.ops.write_reg(hw,
1136 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1137 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1138 sfp_addr);
1139
1140 /* Poll status */
1141 for (i = 0; i < 100; i++) {
1142 hw->phy.ops.read_reg(hw,
1143 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1144 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1145 &sfp_stat);
1146 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1147 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1148 break;
1149 msec_delay(10);
1150 }
1151
1152 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1153 DEBUGOUT("EEPROM read did not pass.\n");
1154 status = IXGBE_ERR_SFP_NOT_PRESENT;
1155 goto out;
1156 }
1157
1158 /* Read data */
1159 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1160 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1161
1162 *eeprom_data = (u8)(sfp_data >> 8);
1163 } else {
1164 status = IXGBE_ERR_PHY;
1165 goto out;
1166 }
1167
1168 out:
1169 return status;
1170 }
1171
1172 /**
1173 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1174 * @hw: pointer to hardware structure
1175 *
1176 * Determines physical layer capabilities of the current configuration.
1177 **/
1178 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1179 {
1180 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1181 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1182 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1183 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1184 u16 ext_ability = 0;
1185
1186 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1187
1188 hw->phy.ops.identify(hw);
1189
1190 /* Copper PHY must be checked before AUTOC LMS to determine correct
1191 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82598.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
57 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
58 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
59 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
60 u32 headroom, int strategy);
61 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
62 u8 *sff8472_data);
63 /**
64 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
65 * @hw: pointer to the HW structure
66 *
67 * The defaults for 82598 should be in the range of 50us to 50ms,
68 * however the hardware default for these parts is 500us to 1ms which is less
69 * than the 10ms recommended by the pci-e spec. To address this we need to
70 * increase the value to either 10ms to 250ms for capability version 1 config,
71 * or 16ms to 55ms for version 2.
72 **/
73 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
74 {
75 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
76 u16 pcie_devctl2;
77
78 /* only take action if timeout value is defaulted to 0 */
79 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
80 goto out;
81
82 /*
137 /* RAR, Multicast, VLAN */
138 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
139 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
140 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
141 mac->ops.set_vlvf = NULL;
142 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
143
144 /* Flow Control */
145 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
146
147 mac->mcft_size = 128;
148 mac->vft_size = 128;
149 mac->num_rar_entries = 16;
150 mac->rx_pb_size = 512;
151 mac->max_tx_queues = 32;
152 mac->max_rx_queues = 64;
153 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
154
155 /* SFP+ Module */
156 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
157 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598;
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
165
166 /* Manageability interface */
167 mac->ops.set_fw_drv_ver = NULL;
168
169 return ret_val;
170 }
171
172 /**
173 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
174 * @hw: pointer to hardware structure
175 *
176 * Initialize any function pointers that were not able to be
177 * set during init_shared_code because the PHY/SFP type was
700 *speed = IXGBE_LINK_SPEED_1GB_FULL;
701
702 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
703 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
704 *link_up = FALSE;
705
706 out:
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_setup_mac_link_82598 - Set MAC link speed
712 * @hw: pointer to hardware structure
713 * @speed: new link speed
714 * @autoneg: TRUE if autonegotiation enabled
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
720 ixgbe_link_speed speed,
721 bool autoneg_wait_to_complete)
722 {
723 bool autoneg = FALSE;
724 s32 status;
725 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
726 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 u32 autoc = curr_autoc;
728 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
729
730 DEBUGFUNC("ixgbe_setup_mac_link_82598");
731
732 /* Check to see if speed passed in is supported. */
733 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
734 if (status != IXGBE_SUCCESS)
735 return (status);
736 speed &= link_capabilities;
737
738 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
739 status = IXGBE_ERR_LINK_SETUP;
740
741 /* Set KX4/KX support according to speed requested */
742 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
743 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
751 }
752
753 if (status == IXGBE_SUCCESS) {
754 /*
755 * Setup and restart the link based on the new values in
756 * ixgbe_hw This will write the AUTOC register based on the new
757 * stored values
758 */
759 status = ixgbe_start_mac_link_82598(hw,
760 autoneg_wait_to_complete);
761 }
762
763 return status;
764 }
765
766
767 /**
768 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
769 * @hw: pointer to hardware structure
770 * @speed: new link speed
771 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
772 *
773 * Sets the link speed in the AUTOC register in the MAC and restarts link.
774 **/
775 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
776 ixgbe_link_speed speed,
777 bool autoneg_wait_to_complete)
778 {
779 s32 status;
780
781 DEBUGFUNC("ixgbe_setup_copper_link_82598");
782
783 /* Setup the PHY according to input speed */
784 status = hw->phy.ops.setup_link_speed(hw, speed,
785 autoneg_wait_to_complete);
786 if (status == IXGBE_SUCCESS) {
787 /* Set up MAC */
788 status =
789 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
790 }
791
792 return status;
793 }
794
795 /**
796 * ixgbe_reset_hw_82598 - Performs hardware reset
797 * @hw: pointer to hardware structure
798 *
799 * Resets the hardware by resetting the transmit and receive units, masks and
800 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
801 * reset.
802 **/
803 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
804 {
1088 * @reg: atlas register to write
1089 * @val: value to write
1090 *
1091 * Performs write operation to Atlas analog register specified.
1092 **/
1093 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1094 {
1095 u32 atlas_ctl;
1096
1097 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1098
1099 atlas_ctl = (reg << 8) | val;
1100 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1101 IXGBE_WRITE_FLUSH(hw);
1102 usec_delay(10);
1103
1104 return IXGBE_SUCCESS;
1105 }
1106
1107 /**
1108 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1109 * @hw: pointer to hardware structure
1110 * @dev_addr: address to read from
1111 * @byte_offset: byte offset to read from dev_addr
1112 * @eeprom_data: value read
1113 *
1114 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1115 **/
1116 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
1117 u8 byte_offset, u8 *eeprom_data)
1118 {
1119 s32 status = IXGBE_SUCCESS;
1120 u16 sfp_addr = 0;
1121 u16 sfp_data = 0;
1122 u16 sfp_stat = 0;
1123 u32 i;
1124
1125 DEBUGFUNC("ixgbe_read_i2c_phy_82598");
1126
1127 if (hw->phy.type == ixgbe_phy_nl) {
1128 /*
1129 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1130 * 0xC30D. These registers are used to talk to the SFP+
1131 * module's EEPROM through the SDA/SCL (I2C) interface.
1132 */
1133 sfp_addr = (dev_addr << 8) + byte_offset;
1134 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1135 hw->phy.ops.write_reg(hw,
1136 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1137 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1138 sfp_addr);
1139
1140 /* Poll status */
1141 for (i = 0; i < 100; i++) {
1142 hw->phy.ops.read_reg(hw,
1143 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1144 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1145 &sfp_stat);
1146 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1147 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1148 break;
1149 msec_delay(10);
1150 }
1151
1152 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1153 DEBUGOUT("EEPROM read did not pass.\n");
1154 status = IXGBE_ERR_SFP_NOT_PRESENT;
1155 goto out;
1156 }
1157
1158 /* Read data */
1159 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1160 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1161
1162 *eeprom_data = (u8)(sfp_data >> 8);
1163 } else {
1164 status = IXGBE_ERR_PHY;
1165 }
1166
1167 out:
1168 return status;
1169 }
1170
1171 /**
1172 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1173 * @hw: pointer to hardware structure
1174 * @byte_offset: EEPROM byte offset to read
1175 * @eeprom_data: value read
1176 *
1177 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1178 **/
1179 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1180 u8 *eeprom_data)
1181 {
1182 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1183 byte_offset, eeprom_data);
1184 }
1185
1186 /**
1187 * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1188 * @hw: pointer to hardware structure
1189 * @byte_offset: byte offset at address 0xA2
1190 * @eeprom_data: value read
1191 *
1192 * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1193 **/
1194 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1195 u8 *sff8472_data)
1196 {
1197 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1198 byte_offset, sff8472_data);
1199 }
1200
1201 /**
1202 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1203 * @hw: pointer to hardware structure
1204 *
1205 * Determines physical layer capabilities of the current configuration.
1206 **/
1207 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1208 {
1209 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1210 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1211 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1212 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1213 u16 ext_ability = 0;
1214
1215 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1216
1217 hw->phy.ops.identify(hw);
1218
1219 /* Copper PHY must be checked before AUTOC LMS to determine correct
1220 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
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