1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 /* All Rights Reserved */
27 /*
28 * Copyright 2015 Joyent, Inc.
29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 */
31
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/vmparam.h>
35 #include <sys/systm.h>
36 #include <sys/signal.h>
37 #include <sys/stack.h>
38 #include <sys/regset.h>
39 #include <sys/privregs.h>
40 #include <sys/frame.h>
41 #include <sys/proc.h>
42 #include <sys/psw.h>
43 #include <sys/siginfo.h>
44 #include <sys/cpuvar.h>
45 #include <sys/asm_linkage.h>
46 #include <sys/kmem.h>
47 #include <sys/errno.h>
48 #include <sys/bootconf.h>
49 #include <sys/archsystm.h>
50 #include <sys/debug.h>
51 #include <sys/elf.h>
52 #include <sys/spl.h>
53 #include <sys/time.h>
54 #include <sys/atomic.h>
55 #include <sys/sysmacros.h>
56 #include <sys/cmn_err.h>
57 #include <sys/modctl.h>
58 #include <sys/kobj.h>
59 #include <sys/panic.h>
60 #include <sys/reboot.h>
61 #include <sys/time.h>
62 #include <sys/fp.h>
63 #include <sys/x86_archext.h>
64 #include <sys/auxv.h>
65 #include <sys/auxv_386.h>
66 #include <sys/dtrace.h>
67 #include <sys/brand.h>
68 #include <sys/machbrand.h>
69 #include <sys/cmn_err.h>
70
71 extern const struct fnsave_state x87_initial;
72 extern const struct fxsave_state sse_initial;
73
74 /*
75 * Map an fnsave-formatted save area into an fxsave-formatted save area.
76 *
77 * Most fields are the same width, content and semantics. However
78 * the tag word is compressed.
79 */
80 static void
81 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
82 {
83 uint_t i, tagbits;
84
85 fx->fx_fcw = fn->f_fcw;
86 fx->fx_fsw = fn->f_fsw;
87
88 /*
89 * copy element by element (because of holes)
90 */
91 for (i = 0; i < 8; i++)
92 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
93 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
94
95 /*
96 * synthesize compressed tag bits
97 */
98 fx->fx_fctw = 0;
99 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
100 if ((tagbits & 3) != 3)
101 fx->fx_fctw |= (1 << i);
102
103 fx->fx_fop = fn->f_fop;
104
105 #if defined(__amd64)
106 fx->fx_rip = (uint64_t)fn->f_eip;
107 fx->fx_rdp = (uint64_t)fn->f_dp;
108 #else
109 fx->fx_eip = fn->f_eip;
110 fx->fx_cs = fn->f_cs;
111 fx->__fx_ign0 = 0;
112 fx->fx_dp = fn->f_dp;
113 fx->fx_ds = fn->f_ds;
114 fx->__fx_ign1 = 0;
115 #endif
116 }
117
118 /*
119 * Map from an fxsave-format save area to an fnsave-format save area.
120 */
121 static void
122 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
123 {
124 uint_t i, top, tagbits;
125
126 fn->f_fcw = fx->fx_fcw;
127 fn->__f_ign0 = 0;
128 fn->f_fsw = fx->fx_fsw;
129 fn->__f_ign1 = 0;
130
131 top = (fx->fx_fsw & FPS_TOP) >> 11;
132
133 /*
134 * copy element by element (because of holes)
135 */
136 for (i = 0; i < 8; i++)
137 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
138 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
139
140 /*
141 * synthesize uncompressed tag bits
142 */
143 fn->f_ftw = 0;
144 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
145 uint_t ibit, expo;
146 const uint16_t *fpp;
147 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
148
149 if ((tagbits & 1) == 0) {
150 fn->f_ftw |= 3 << (i << 1); /* empty */
151 continue;
152 }
153
154 /*
155 * (tags refer to *physical* registers)
156 */
157 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
158 ibit = fpp[3] >> 15;
159 expo = fpp[4] & 0x7fff;
160
161 if (ibit && expo != 0 && expo != 0x7fff)
162 continue; /* valid fp number */
163
164 if (bcmp(fpp, &zero, sizeof (zero)))
165 fn->f_ftw |= 2 << (i << 1); /* NaN */
166 else
167 fn->f_ftw |= 1 << (i << 1); /* fp zero */
168 }
169
170 fn->f_fop = fx->fx_fop;
171
172 fn->__f_ign2 = 0;
173 #if defined(__amd64)
174 fn->f_eip = (uint32_t)fx->fx_rip;
175 fn->f_cs = U32CS_SEL;
176 fn->f_dp = (uint32_t)fx->fx_rdp;
177 fn->f_ds = UDS_SEL;
178 #else
179 fn->f_eip = fx->fx_eip;
180 fn->f_cs = fx->fx_cs;
181 fn->f_dp = fx->fx_dp;
182 fn->f_ds = fx->fx_ds;
183 #endif
184 fn->__f_ign3 = 0;
185 }
186
187 /*
188 * Map from an fpregset_t into an fxsave-format save area
189 */
190 static void
191 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
192 {
193 #if defined(__amd64)
194 bcopy(fp, fx, sizeof (*fx));
195 #else
196 const struct _fpchip_state *fc = &fp->fp_reg_set.fpchip_state;
197
198 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
199 fx->fx_mxcsr = fc->mxcsr;
200 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
201 #endif
202 /*
203 * avoid useless #gp exceptions - mask reserved bits
204 */
205 fx->fx_mxcsr &= sse_mxcsr_mask;
206 }
207
208 /*
209 * Map from an fxsave-format save area into a fpregset_t
210 */
211 static void
212 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
213 {
214 #if defined(__amd64)
215 bcopy(fx, fp, sizeof (*fx));
216 #else
217 struct _fpchip_state *fc = &fp->fp_reg_set.fpchip_state;
218
219 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
220 fc->mxcsr = fx->fx_mxcsr;
221 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
222 #endif
223 }
224
225 #if defined(_SYSCALL32_IMPL)
226 static void
227 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
228 {
229 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
230
231 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
232 /*
233 * avoid useless #gp exceptions - mask reserved bits
234 */
235 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
236 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
237 }
238
239 static void
240 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
241 {
242 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
243
244 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
245 fc->mxcsr = fx->fx_mxcsr;
246 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
247 }
248
249 static void
250 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
251 {
252 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
253 dst->fp_reg_set.fpchip_state.status =
254 src->fp_reg_set.fpchip_state.status;
255 dst->fp_reg_set.fpchip_state.xstatus =
256 src->fp_reg_set.fpchip_state.xstatus;
257 }
258
259 static void
260 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
261 {
262 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
263 dst->fp_reg_set.fpchip_state.status =
264 src->fp_reg_set.fpchip_state.status;
265 dst->fp_reg_set.fpchip_state.xstatus =
266 src->fp_reg_set.fpchip_state.xstatus;
267 }
268 #endif
269
270 /*
271 * Set floating-point registers from a native fpregset_t.
272 */
273 void
274 setfpregs(klwp_t *lwp, fpregset_t *fp)
275 {
276 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
277
278 if (fpu->fpu_flags & FPU_EN) {
279 if (!(fpu->fpu_flags & FPU_VALID)) {
280 /*
281 * FPU context is still active, release the
282 * ownership.
283 */
284 fp_free(fpu, 0);
285 }
286 }
287 /*
288 * Else: if we are trying to change the FPU state of a thread which
289 * hasn't yet initialized floating point, store the state in
290 * the pcb and indicate that the state is valid. When the
291 * thread enables floating point, it will use this state instead
292 * of the default state.
293 */
294
295 switch (fp_save_mech) {
296 #if defined(__i386)
297 case FP_FNSAVE:
298 bcopy(fp, &fpu->fpu_regs.kfpu_u.kfpu_fn,
299 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn));
300 break;
301 #endif
302 case FP_FXSAVE:
303 fpregset_to_fxsave(fp, &fpu->fpu_regs.kfpu_u.kfpu_fx);
304 fpu->fpu_regs.kfpu_xstatus =
305 fp->fp_reg_set.fpchip_state.xstatus;
306 break;
307
308 case FP_XSAVE:
309 fpregset_to_fxsave(fp,
310 &fpu->fpu_regs.kfpu_u.kfpu_xs.xs_fxsave);
311 fpu->fpu_regs.kfpu_xstatus =
312 fp->fp_reg_set.fpchip_state.xstatus;
313 fpu->fpu_regs.kfpu_u.kfpu_xs.xs_xstate_bv |=
314 (XFEATURE_LEGACY_FP | XFEATURE_SSE);
315 break;
316 default:
317 panic("Invalid fp_save_mech");
318 /*NOTREACHED*/
319 }
320
321 fpu->fpu_regs.kfpu_status = fp->fp_reg_set.fpchip_state.status;
322 fpu->fpu_flags |= FPU_VALID;
323 }
324
325 /*
326 * Get floating-point registers into a native fpregset_t.
327 */
328 void
329 getfpregs(klwp_t *lwp, fpregset_t *fp)
330 {
331 struct fpu_ctx *fpu = &lwp->lwp_pcb.pcb_fpu;
332
333 kpreempt_disable();
334 if (fpu->fpu_flags & FPU_EN) {
335 /*
336 * If we have FPU hw and the thread's pcb doesn't have
337 * a valid FPU state then get the state from the hw.
338 */
339 if (fpu_exists && ttolwp(curthread) == lwp &&
340 !(fpu->fpu_flags & FPU_VALID))
341 fp_save(fpu); /* get the current FPU state */
342 }
343
344 /*
345 * There are 3 possible cases we have to be aware of here:
346 *
347 * 1. FPU is enabled. FPU state is stored in the current LWP.
348 *
349 * 2. FPU is not enabled, and there have been no intervening /proc
350 * modifications. Return initial FPU state.
351 *
352 * 3. FPU is not enabled, but a /proc consumer has modified FPU state.
353 * FPU state is stored in the current LWP.
354 */
355 if ((fpu->fpu_flags & FPU_EN) || (fpu->fpu_flags & FPU_VALID)) {
356 /*
357 * Cases 1 and 3.
358 */
359 switch (fp_save_mech) {
360 #if defined(__i386)
361 case FP_FNSAVE:
362 bcopy(&fpu->fpu_regs.kfpu_u.kfpu_fn, fp,
363 sizeof (fpu->fpu_regs.kfpu_u.kfpu_fn));
364 break;
365 #endif
366 case FP_FXSAVE:
367 fxsave_to_fpregset(&fpu->fpu_regs.kfpu_u.kfpu_fx, fp);
368 fp->fp_reg_set.fpchip_state.xstatus =
369 fpu->fpu_regs.kfpu_xstatus;
370 break;
371 case FP_XSAVE:
372 fxsave_to_fpregset(
373 &fpu->fpu_regs.kfpu_u.kfpu_xs.xs_fxsave, fp);
374 fp->fp_reg_set.fpchip_state.xstatus =
375 fpu->fpu_regs.kfpu_xstatus;
376 break;
377 default:
378 panic("Invalid fp_save_mech");
379 /*NOTREACHED*/
380 }
381 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
382 } else {
383 /*
384 * Case 2.
385 */
386 switch (fp_save_mech) {
387 #if defined(__i386)
388 case FP_FNSAVE:
389 bcopy(&x87_initial, fp, sizeof (x87_initial));
390 break;
391 #endif
392 case FP_FXSAVE:
393 case FP_XSAVE:
394 /*
395 * For now, we don't have any AVX specific field in ABI.
396 * If we add any in the future, we need to initial them
397 * as well.
398 */
399 fxsave_to_fpregset(&sse_initial, fp);
400 fp->fp_reg_set.fpchip_state.xstatus =
401 fpu->fpu_regs.kfpu_xstatus;
402 break;
403 default:
404 panic("Invalid fp_save_mech");
405 /*NOTREACHED*/
406 }
407 fp->fp_reg_set.fpchip_state.status = fpu->fpu_regs.kfpu_status;
408 }
409 kpreempt_enable();
410 }
411
412 #if defined(_SYSCALL32_IMPL)
413
414 /*
415 * Set floating-point registers from an fpregset32_t.
416 */
417 void
418 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
419 {
420 fpregset_t fpregs;
421
422 fpregset_32ton(fp, &fpregs);
423 setfpregs(lwp, &fpregs);
424 }
425
426 /*
427 * Get floating-point registers into an fpregset32_t.
428 */
429 void
430 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
431 {
432 fpregset_t fpregs;
433
434 getfpregs(lwp, &fpregs);
435 fpregset_nto32(&fpregs, fp);
436 }
437
438 #endif /* _SYSCALL32_IMPL */
439
440 /*
441 * Return the general registers
442 */
443 void
444 getgregs(klwp_t *lwp, gregset_t grp)
445 {
446 struct regs *rp = lwptoregs(lwp);
447 #if defined(__amd64)
448 struct pcb *pcb = &lwp->lwp_pcb;
449 int thisthread = lwptot(lwp) == curthread;
450
451 grp[REG_RDI] = rp->r_rdi;
452 grp[REG_RSI] = rp->r_rsi;
453 grp[REG_RDX] = rp->r_rdx;
454 grp[REG_RCX] = rp->r_rcx;
455 grp[REG_R8] = rp->r_r8;
456 grp[REG_R9] = rp->r_r9;
457 grp[REG_RAX] = rp->r_rax;
458 grp[REG_RBX] = rp->r_rbx;
459 grp[REG_RBP] = rp->r_rbp;
460 grp[REG_R10] = rp->r_r10;
461 grp[REG_R11] = rp->r_r11;
462 grp[REG_R12] = rp->r_r12;
463 grp[REG_R13] = rp->r_r13;
464 grp[REG_R14] = rp->r_r14;
465 grp[REG_R15] = rp->r_r15;
466 grp[REG_FSBASE] = pcb->pcb_fsbase;
467 grp[REG_GSBASE] = pcb->pcb_gsbase;
468 if (thisthread)
469 kpreempt_disable();
470 if (pcb->pcb_rupdate == 1) {
471 grp[REG_DS] = pcb->pcb_ds;
472 grp[REG_ES] = pcb->pcb_es;
473 grp[REG_FS] = pcb->pcb_fs;
474 grp[REG_GS] = pcb->pcb_gs;
475 } else {
476 grp[REG_DS] = rp->r_ds;
477 grp[REG_ES] = rp->r_es;
478 grp[REG_FS] = rp->r_fs;
479 grp[REG_GS] = rp->r_gs;
480 }
481 if (thisthread)
482 kpreempt_enable();
483 grp[REG_TRAPNO] = rp->r_trapno;
484 grp[REG_ERR] = rp->r_err;
485 grp[REG_RIP] = rp->r_rip;
486 grp[REG_CS] = rp->r_cs;
487 grp[REG_SS] = rp->r_ss;
488 grp[REG_RFL] = rp->r_rfl;
489 grp[REG_RSP] = rp->r_rsp;
490 #else
491 bcopy(&rp->r_gs, grp, sizeof (gregset_t));
492 #endif
493 }
494
495 #if defined(_SYSCALL32_IMPL)
496
497 void
498 getgregs32(klwp_t *lwp, gregset32_t grp)
499 {
500 struct regs *rp = lwptoregs(lwp);
501 struct pcb *pcb = &lwp->lwp_pcb;
502 int thisthread = lwptot(lwp) == curthread;
503
504 if (thisthread)
505 kpreempt_disable();
506 if (pcb->pcb_rupdate == 1) {
507 grp[GS] = (uint16_t)pcb->pcb_gs;
508 grp[FS] = (uint16_t)pcb->pcb_fs;
509 grp[DS] = (uint16_t)pcb->pcb_ds;
510 grp[ES] = (uint16_t)pcb->pcb_es;
511 } else {
512 grp[GS] = (uint16_t)rp->r_gs;
513 grp[FS] = (uint16_t)rp->r_fs;
514 grp[DS] = (uint16_t)rp->r_ds;
515 grp[ES] = (uint16_t)rp->r_es;
516 }
517 if (thisthread)
518 kpreempt_enable();
519 grp[EDI] = (greg32_t)rp->r_rdi;
520 grp[ESI] = (greg32_t)rp->r_rsi;
521 grp[EBP] = (greg32_t)rp->r_rbp;
522 grp[ESP] = 0;
523 grp[EBX] = (greg32_t)rp->r_rbx;
524 grp[EDX] = (greg32_t)rp->r_rdx;
525 grp[ECX] = (greg32_t)rp->r_rcx;
526 grp[EAX] = (greg32_t)rp->r_rax;
527 grp[TRAPNO] = (greg32_t)rp->r_trapno;
528 grp[ERR] = (greg32_t)rp->r_err;
529 grp[EIP] = (greg32_t)rp->r_rip;
530 grp[CS] = (uint16_t)rp->r_cs;
531 grp[EFL] = (greg32_t)rp->r_rfl;
532 grp[UESP] = (greg32_t)rp->r_rsp;
533 grp[SS] = (uint16_t)rp->r_ss;
534 }
535
536 void
537 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
538 {
539 mcontext_t *dmc = &dst->uc_mcontext;
540 const mcontext32_t *smc = &src->uc_mcontext;
541
542 bzero(dst, sizeof (*dst));
543 dst->uc_flags = src->uc_flags;
544 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
545
546 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
547
548 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
549 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
550 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
551
552 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
553 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
554 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
555 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
556 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
557 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
558 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
559 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
560 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
561 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
562 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
563 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
564 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
565 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
566 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
567 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
568 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
569 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
570
571 /*
572 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
573 * otherwise there is no guarantee that anything in fpregs is valid.
574 */
575 if (src->uc_flags & UC_FPU)
576 fpregset_32ton(&src->uc_mcontext.fpregs,
577 &dst->uc_mcontext.fpregs);
578
579 /*
580 * Copy the brand-private data:
581 */
582 dst->uc_brand_data[0] = (void *)(uintptr_t)src->uc_brand_data[0];
583 dst->uc_brand_data[1] = (void *)(uintptr_t)src->uc_brand_data[1];
584 dst->uc_brand_data[2] = (void *)(uintptr_t)src->uc_brand_data[2];
585 }
586
587 #endif /* _SYSCALL32_IMPL */
588
589 /*
590 * Return the user-level PC.
591 * If in a system call, return the address of the syscall trap.
592 */
593 greg_t
594 getuserpc()
595 {
596 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
597 uint32_t insn;
598
599 if (curthread->t_sysnum == 0)
600 return (upc);
601
602 /*
603 * We might've gotten here from sysenter (0xf 0x34),
604 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
605 *
606 * Go peek at the binary to figure it out..
607 */
608 if (fuword32((void *)(upc - 2), &insn) != -1 &&
609 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
610 return (upc - 2);
611 return (upc - 7);
612 }
613
614 /*
615 * Protect segment registers from non-user privilege levels and GDT selectors
616 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
617 * selector is non-null and not USER_CS/USER_DS, we make sure that the
618 * TI bit is set to point into the LDT and that the RPL is set to 3.
619 *
620 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
621 * also explicitly zero the top 16 bits since they may be coming from the
622 * user's address space via setcontext(2) or /proc.
623 *
624 * Note about null selector. When running on the hypervisor if we allow a
625 * process to set its %cs to null selector with RPL of 0 the hypervisor will
626 * crash the domain. If running on bare metal we would get a #gp fault and
627 * be able to kill the process and continue on. Therefore we make sure to
628 * force RPL to SEL_UPL even for null selector when setting %cs.
629 */
630
631 #if defined(IS_CS) || defined(IS_NOT_CS)
632 #error "IS_CS and IS_NOT_CS already defined"
633 #endif
634
635 #define IS_CS 1
636 #define IS_NOT_CS 0
637
638 /*ARGSUSED*/
639 greg_t
640 fix_segreg(greg_t sr, int iscs, model_t datamodel)
641 {
642 kthread_t *t = curthread;
643
644 switch (sr &= 0xffff) {
645
646 case 0:
647 if (iscs == IS_CS)
648 return (0 | SEL_UPL);
649 else
650 return (0);
651
652 #if defined(__amd64)
653 /*
654 * If lwp attempts to switch data model then force their
655 * code selector to be null selector.
656 */
657 case U32CS_SEL:
658 if (datamodel == DATAMODEL_NATIVE)
659 return (0 | SEL_UPL);
660 else
661 return (sr);
662
663 case UCS_SEL:
664 if (datamodel == DATAMODEL_ILP32)
665 return (0 | SEL_UPL);
666 #elif defined(__i386)
667 case UCS_SEL:
668 #endif
669 /*FALLTHROUGH*/
670 case UDS_SEL:
671 case LWPFS_SEL:
672 case LWPGS_SEL:
673 case SEL_UPL:
674 return (sr);
675 default:
676 break;
677 }
678
679 /*
680 * Allow this process's brand to do any necessary segment register
681 * manipulation.
682 */
683 if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) {
684 greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel);
685
686 if (bsr == 0 && iscs == IS_CS)
687 return (0 | SEL_UPL);
688 else
689 return (bsr);
690 }
691
692 /*
693 * Force it into the LDT in ring 3 for 32-bit processes, which by
694 * default do not have an LDT, so that any attempt to use an invalid
695 * selector will reference the (non-existant) LDT, and cause a #gp
696 * fault for the process.
697 *
698 * 64-bit processes get the null gdt selector since they
699 * are not allowed to have a private LDT.
700 */
701 #if defined(__amd64)
702 if (datamodel == DATAMODEL_ILP32) {
703 return (sr | SEL_TI_LDT | SEL_UPL);
704 } else {
705 if (iscs == IS_CS)
706 return (0 | SEL_UPL);
707 else
708 return (0);
709 }
710
711 #elif defined(__i386)
712 return (sr | SEL_TI_LDT | SEL_UPL);
713 #endif
714 }
715
716 /*
717 * Set general registers.
718 */
719 void
720 setgregs(klwp_t *lwp, gregset_t grp)
721 {
722 struct regs *rp = lwptoregs(lwp);
723 model_t datamodel = lwp_getdatamodel(lwp);
724
725 #if defined(__amd64)
726 struct pcb *pcb = &lwp->lwp_pcb;
727 int thisthread = lwptot(lwp) == curthread;
728
729 if (datamodel == DATAMODEL_NATIVE) {
730
731 if (thisthread)
732 (void) save_syscall_args(); /* copy the args */
733
734 rp->r_rdi = grp[REG_RDI];
735 rp->r_rsi = grp[REG_RSI];
736 rp->r_rdx = grp[REG_RDX];
737 rp->r_rcx = grp[REG_RCX];
738 rp->r_r8 = grp[REG_R8];
739 rp->r_r9 = grp[REG_R9];
740 rp->r_rax = grp[REG_RAX];
741 rp->r_rbx = grp[REG_RBX];
742 rp->r_rbp = grp[REG_RBP];
743 rp->r_r10 = grp[REG_R10];
744 rp->r_r11 = grp[REG_R11];
745 rp->r_r12 = grp[REG_R12];
746 rp->r_r13 = grp[REG_R13];
747 rp->r_r14 = grp[REG_R14];
748 rp->r_r15 = grp[REG_R15];
749 rp->r_trapno = grp[REG_TRAPNO];
750 rp->r_err = grp[REG_ERR];
751 rp->r_rip = grp[REG_RIP];
752 /*
753 * Setting %cs or %ss to anything else is quietly but
754 * quite definitely forbidden!
755 */
756 rp->r_cs = UCS_SEL;
757 rp->r_ss = UDS_SEL;
758 rp->r_rsp = grp[REG_RSP];
759
760 if (thisthread)
761 kpreempt_disable();
762
763 pcb->pcb_ds = UDS_SEL;
764 pcb->pcb_es = UDS_SEL;
765
766 /*
767 * 64-bit processes -are- allowed to set their fsbase/gsbase
768 * values directly, but only if they're using the segment
769 * selectors that allow that semantic.
770 *
771 * (32-bit processes must use lwp_set_private().)
772 */
773 pcb->pcb_fsbase = grp[REG_FSBASE];
774 pcb->pcb_gsbase = grp[REG_GSBASE];
775 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
776 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
777
778 /*
779 * Ensure that we go out via update_sregs
780 */
781 pcb->pcb_rupdate = 1;
782 lwptot(lwp)->t_post_sys = 1;
783 if (thisthread)
784 kpreempt_enable();
785 #if defined(_SYSCALL32_IMPL)
786 } else {
787 rp->r_rdi = (uint32_t)grp[REG_RDI];
788 rp->r_rsi = (uint32_t)grp[REG_RSI];
789 rp->r_rdx = (uint32_t)grp[REG_RDX];
790 rp->r_rcx = (uint32_t)grp[REG_RCX];
791 rp->r_rax = (uint32_t)grp[REG_RAX];
792 rp->r_rbx = (uint32_t)grp[REG_RBX];
793 rp->r_rbp = (uint32_t)grp[REG_RBP];
794 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
795 rp->r_err = (uint32_t)grp[REG_ERR];
796 rp->r_rip = (uint32_t)grp[REG_RIP];
797
798 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
799 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
800
801 rp->r_rsp = (uint32_t)grp[REG_RSP];
802
803 if (thisthread)
804 kpreempt_disable();
805
806 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
807 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
808
809 /*
810 * (See fsbase/gsbase commentary above)
811 */
812 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
813 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
814
815 /*
816 * Ensure that we go out via update_sregs
817 */
818 pcb->pcb_rupdate = 1;
819 lwptot(lwp)->t_post_sys = 1;
820 if (thisthread)
821 kpreempt_enable();
822 #endif
823 }
824
825 /*
826 * Only certain bits of the flags register can be modified.
827 */
828 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
829 (grp[REG_RFL] & PSL_USERMASK);
830
831 #elif defined(__i386)
832
833 /*
834 * Only certain bits of the flags register can be modified.
835 */
836 grp[EFL] = (rp->r_efl & ~PSL_USERMASK) | (grp[EFL] & PSL_USERMASK);
837
838 /*
839 * Copy saved registers from user stack.
840 */
841 bcopy(grp, &rp->r_gs, sizeof (gregset_t));
842
843 rp->r_cs = fix_segreg(rp->r_cs, IS_CS, datamodel);
844 rp->r_ss = fix_segreg(rp->r_ss, IS_NOT_CS, datamodel);
845 rp->r_ds = fix_segreg(rp->r_ds, IS_NOT_CS, datamodel);
846 rp->r_es = fix_segreg(rp->r_es, IS_NOT_CS, datamodel);
847 rp->r_fs = fix_segreg(rp->r_fs, IS_NOT_CS, datamodel);
848 rp->r_gs = fix_segreg(rp->r_gs, IS_NOT_CS, datamodel);
849
850 #endif /* __i386 */
851 }
852
853 /*
854 * Determine whether eip is likely to have an interrupt frame
855 * on the stack. We do this by comparing the address to the
856 * range of addresses spanned by several well-known routines.
857 */
858 extern void _interrupt();
859 extern void _allsyscalls();
860 extern void _cmntrap();
861 extern void fakesoftint();
862
863 extern size_t _interrupt_size;
864 extern size_t _allsyscalls_size;
865 extern size_t _cmntrap_size;
866 extern size_t _fakesoftint_size;
867
868 /*
869 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
870 * Returns MIN(current stack depth, pcstack_limit).
871 */
872 int
873 getpcstack(pc_t *pcstack, int pcstack_limit)
874 {
875 struct frame *fp = (struct frame *)getfp();
876 struct frame *nextfp, *minfp, *stacktop;
877 int depth = 0;
878 int on_intr;
879 uintptr_t pc;
880
881 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
882 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
883 else
884 stacktop = (struct frame *)curthread->t_stk;
885 minfp = fp;
886
887 pc = ((struct regs *)fp)->r_pc;
888
889 while (depth < pcstack_limit) {
890 nextfp = (struct frame *)fp->fr_savfp;
891 pc = fp->fr_savpc;
892 if (nextfp <= minfp || nextfp >= stacktop) {
893 if (on_intr) {
894 /*
895 * Hop from interrupt stack to thread stack.
896 */
897 stacktop = (struct frame *)curthread->t_stk;
898 minfp = (struct frame *)curthread->t_stkbase;
899 on_intr = 0;
900 continue;
901 }
902 break;
903 }
904 pcstack[depth++] = (pc_t)pc;
905 fp = nextfp;
906 minfp = fp;
907 }
908 return (depth);
909 }
910
911 /*
912 * The following ELF header fields are defined as processor-specific
913 * in the V8 ABI:
914 *
915 * e_ident[EI_DATA] encoding of the processor-specific
916 * data in the object file
917 * e_machine processor identification
918 * e_flags processor-specific flags associated
919 * with the file
920 */
921
922 /*
923 * The value of at_flags reflects a platform's cpu module support.
924 * at_flags is used to check for allowing a binary to execute and
925 * is passed as the value of the AT_FLAGS auxiliary vector.
926 */
927 int at_flags = 0;
928
929 /*
930 * Check the processor-specific fields of an ELF header.
931 *
932 * returns 1 if the fields are valid, 0 otherwise
933 */
934 /*ARGSUSED2*/
935 int
936 elfheadcheck(
937 unsigned char e_data,
938 Elf32_Half e_machine,
939 Elf32_Word e_flags)
940 {
941 if (e_data != ELFDATA2LSB)
942 return (0);
943 #if defined(__amd64)
944 if (e_machine == EM_AMD64)
945 return (1);
946 #endif
947 return (e_machine == EM_386);
948 }
949
950 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
951 uint_t auxv_hwcap_include_2 = 0; /* second word */
952 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
953 uint_t auxv_hwcap_exclude_2 = 0; /* second word */
954 #if defined(_SYSCALL32_IMPL)
955 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
956 uint_t auxv_hwcap32_include_2 = 0; /* ditto for 32-bit apps */
957 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
958 uint_t auxv_hwcap32_exclude_2 = 0; /* ditto for 32-bit apps */
959 #endif
960
961 /*
962 * Gather information about the processor and place it into auxv_hwcap
963 * so that it can be exported to the linker via the aux vector.
964 *
965 * We use this seemingly complicated mechanism so that we can ensure
966 * that /etc/system can be used to override what the system can or
967 * cannot discover for itself.
968 */
969 void
970 bind_hwcap(void)
971 {
972 uint_t cpu_hwcap_flags[2];
973 cpuid_pass4(NULL, cpu_hwcap_flags);
974
975 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags[0]) &
976 ~auxv_hwcap_exclude;
977 auxv_hwcap_2 = (auxv_hwcap_include_2 | cpu_hwcap_flags[1]) &
978 ~auxv_hwcap_exclude_2;
979
980 #if defined(__amd64)
981 /*
982 * On AMD processors, sysenter just doesn't work at all
983 * when the kernel is in long mode. On IA-32e processors
984 * it does, but there's no real point in all the alternate
985 * mechanism when syscall works on both.
986 *
987 * Besides, the kernel's sysenter handler is expecting a
988 * 32-bit lwp ...
989 */
990 auxv_hwcap &= ~AV_386_SEP;
991 #else
992 /*
993 * 32-bit processes can -always- use the lahf/sahf instructions
994 */
995 auxv_hwcap |= AV_386_AHF;
996 #endif
997
998 if (auxv_hwcap_include || auxv_hwcap_exclude || auxv_hwcap_include_2 ||
999 auxv_hwcap_exclude_2) {
1000 /*
1001 * The below assignment is regrettably required to get lint
1002 * to accept the validity of our format string. The format
1003 * string is in fact valid, but whatever intelligence in lint
1004 * understands the cmn_err()-specific %b appears to have an
1005 * off-by-one error: it (mistakenly) complains about bit
1006 * number 32 (even though this is explicitly permitted).
1007 * Normally, one would will away such warnings with a "LINTED"
1008 * directive, but for reasons unclear and unknown, lint
1009 * refuses to be assuaged in this case. Fortunately, lint
1010 * doesn't pretend to have solved the Halting Problem --
1011 * and as soon as the format string is programmatic, it
1012 * knows enough to shut up.
1013 */
1014 char *fmt = "?user ABI extensions: %b\n";
1015 cmn_err(CE_CONT, fmt, auxv_hwcap, FMT_AV_386);
1016 fmt = "?user ABI extensions (word 2): %b\n";
1017 cmn_err(CE_CONT, fmt, auxv_hwcap_2, FMT_AV_386_2);
1018 }
1019
1020 #if defined(_SYSCALL32_IMPL)
1021 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags[0]) &
1022 ~auxv_hwcap32_exclude;
1023 auxv_hwcap32_2 = (auxv_hwcap32_include_2 | cpu_hwcap_flags[1]) &
1024 ~auxv_hwcap32_exclude_2;
1025
1026 #if defined(__amd64)
1027 /*
1028 * If this is an amd64 architecture machine from Intel, then
1029 * syscall -doesn't- work in compatibility mode, only sysenter does.
1030 *
1031 * Sigh.
1032 */
1033 if (!cpuid_syscall32_insn(NULL))
1034 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
1035
1036 /*
1037 * 32-bit processes can -always- use the lahf/sahf instructions
1038 */
1039 auxv_hwcap32 |= AV_386_AHF;
1040 #endif
1041
1042 if (auxv_hwcap32_include || auxv_hwcap32_exclude ||
1043 auxv_hwcap32_include_2 || auxv_hwcap32_exclude_2) {
1044 /*
1045 * See the block comment in the cmn_err() of auxv_hwcap, above.
1046 */
1047 char *fmt = "?32-bit user ABI extensions: %b\n";
1048 cmn_err(CE_CONT, fmt, auxv_hwcap32, FMT_AV_386);
1049 fmt = "?32-bit user ABI extensions (word 2): %b\n";
1050 cmn_err(CE_CONT, fmt, auxv_hwcap32_2, FMT_AV_386_2);
1051 }
1052 #endif
1053 }
1054
1055 /*
1056 * sync_icache() - this is called
1057 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
1058 * this is a nop.
1059 */
1060 /* ARGSUSED */
1061 void
1062 sync_icache(caddr_t addr, uint_t len)
1063 {
1064 /* Do nothing for now */
1065 }
1066
1067 /*ARGSUSED*/
1068 void
1069 sync_data_memory(caddr_t va, size_t len)
1070 {
1071 /* Not implemented for this platform */
1072 }
1073
1074 int
1075 __ipltospl(int ipl)
1076 {
1077 return (ipltospl(ipl));
1078 }
1079
1080 /*
1081 * The panic code invokes panic_saveregs() to record the contents of a
1082 * regs structure into the specified panic_data structure for debuggers.
1083 */
1084 void
1085 panic_saveregs(panic_data_t *pdp, struct regs *rp)
1086 {
1087 panic_nv_t *pnv = PANICNVGET(pdp);
1088
1089 struct cregs creg;
1090
1091 getcregs(&creg);
1092
1093 #if defined(__amd64)
1094 PANICNVADD(pnv, "rdi", rp->r_rdi);
1095 PANICNVADD(pnv, "rsi", rp->r_rsi);
1096 PANICNVADD(pnv, "rdx", rp->r_rdx);
1097 PANICNVADD(pnv, "rcx", rp->r_rcx);
1098 PANICNVADD(pnv, "r8", rp->r_r8);
1099 PANICNVADD(pnv, "r9", rp->r_r9);
1100 PANICNVADD(pnv, "rax", rp->r_rax);
1101 PANICNVADD(pnv, "rbx", rp->r_rbx);
1102 PANICNVADD(pnv, "rbp", rp->r_rbp);
1103 PANICNVADD(pnv, "r10", rp->r_r10);
1104 PANICNVADD(pnv, "r11", rp->r_r11);
1105 PANICNVADD(pnv, "r12", rp->r_r12);
1106 PANICNVADD(pnv, "r13", rp->r_r13);
1107 PANICNVADD(pnv, "r14", rp->r_r14);
1108 PANICNVADD(pnv, "r15", rp->r_r15);
1109 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
1110 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
1111 PANICNVADD(pnv, "ds", rp->r_ds);
1112 PANICNVADD(pnv, "es", rp->r_es);
1113 PANICNVADD(pnv, "fs", rp->r_fs);
1114 PANICNVADD(pnv, "gs", rp->r_gs);
1115 PANICNVADD(pnv, "trapno", rp->r_trapno);
1116 PANICNVADD(pnv, "err", rp->r_err);
1117 PANICNVADD(pnv, "rip", rp->r_rip);
1118 PANICNVADD(pnv, "cs", rp->r_cs);
1119 PANICNVADD(pnv, "rflags", rp->r_rfl);
1120 PANICNVADD(pnv, "rsp", rp->r_rsp);
1121 PANICNVADD(pnv, "ss", rp->r_ss);
1122 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
1123 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
1124 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
1125 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
1126 #elif defined(__i386)
1127 PANICNVADD(pnv, "gs", (uint32_t)rp->r_gs);
1128 PANICNVADD(pnv, "fs", (uint32_t)rp->r_fs);
1129 PANICNVADD(pnv, "es", (uint32_t)rp->r_es);
1130 PANICNVADD(pnv, "ds", (uint32_t)rp->r_ds);
1131 PANICNVADD(pnv, "edi", (uint32_t)rp->r_edi);
1132 PANICNVADD(pnv, "esi", (uint32_t)rp->r_esi);
1133 PANICNVADD(pnv, "ebp", (uint32_t)rp->r_ebp);
1134 PANICNVADD(pnv, "esp", (uint32_t)rp->r_esp);
1135 PANICNVADD(pnv, "ebx", (uint32_t)rp->r_ebx);
1136 PANICNVADD(pnv, "edx", (uint32_t)rp->r_edx);
1137 PANICNVADD(pnv, "ecx", (uint32_t)rp->r_ecx);
1138 PANICNVADD(pnv, "eax", (uint32_t)rp->r_eax);
1139 PANICNVADD(pnv, "trapno", (uint32_t)rp->r_trapno);
1140 PANICNVADD(pnv, "err", (uint32_t)rp->r_err);
1141 PANICNVADD(pnv, "eip", (uint32_t)rp->r_eip);
1142 PANICNVADD(pnv, "cs", (uint32_t)rp->r_cs);
1143 PANICNVADD(pnv, "eflags", (uint32_t)rp->r_efl);
1144 PANICNVADD(pnv, "uesp", (uint32_t)rp->r_uesp);
1145 PANICNVADD(pnv, "ss", (uint32_t)rp->r_ss);
1146 PANICNVADD(pnv, "gdt", creg.cr_gdt);
1147 PANICNVADD(pnv, "idt", creg.cr_idt);
1148 #endif /* __i386 */
1149
1150 PANICNVADD(pnv, "ldt", creg.cr_ldt);
1151 PANICNVADD(pnv, "task", creg.cr_task);
1152 PANICNVADD(pnv, "cr0", creg.cr_cr0);
1153 PANICNVADD(pnv, "cr2", creg.cr_cr2);
1154 PANICNVADD(pnv, "cr3", creg.cr_cr3);
1155 if (creg.cr_cr4)
1156 PANICNVADD(pnv, "cr4", creg.cr_cr4);
1157
1158 PANICNVSET(pdp, pnv);
1159 }
1160
1161 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
1162
1163 #if !defined(__amd64)
1164
1165 /*
1166 * Given a return address (%eip), determine the likely number of arguments
1167 * that were pushed on the stack prior to its execution. We do this by
1168 * expecting that a typical call sequence consists of pushing arguments on
1169 * the stack, executing a call instruction, and then performing an add
1170 * on %esp to restore it to the value prior to pushing the arguments for
1171 * the call. We attempt to detect such an add, and divide the addend
1172 * by the size of a word to determine the number of pushed arguments.
1173 *
1174 * If we do not find such an add, we punt and return TR_ARG_MAX. It is not
1175 * possible to reliably determine if a function took no arguments (i.e. was
1176 * void) because assembler routines do not reliably perform an add on %esp
1177 * immediately upon returning (eg. _sys_call()), so returning TR_ARG_MAX is
1178 * safer than returning 0.
1179 */
1180 static ulong_t
1181 argcount(uintptr_t eip)
1182 {
1183 const uint8_t *ins = (const uint8_t *)eip;
1184 ulong_t n;
1185
1186 enum {
1187 M_MODRM_ESP = 0xc4, /* Mod/RM byte indicates %esp */
1188 M_ADD_IMM32 = 0x81, /* ADD imm32 to r/m32 */
1189 M_ADD_IMM8 = 0x83 /* ADD imm8 to r/m32 */
1190 };
1191
1192 if (eip < KERNELBASE || ins[1] != M_MODRM_ESP)
1193 return (TR_ARG_MAX);
1194
1195 switch (ins[0]) {
1196 case M_ADD_IMM32:
1197 n = ins[2] + (ins[3] << 8) + (ins[4] << 16) + (ins[5] << 24);
1198 break;
1199
1200 case M_ADD_IMM8:
1201 n = ins[2];
1202 break;
1203
1204 default:
1205 return (TR_ARG_MAX);
1206 }
1207
1208 n /= sizeof (long);
1209 return (MIN(n, TR_ARG_MAX));
1210 }
1211
1212 #endif /* !__amd64 */
1213
1214 /*
1215 * Print a stack backtrace using the specified frame pointer. We delay two
1216 * seconds before continuing, unless this is the panic traceback.
1217 * If we are in the process of panicking, we also attempt to write the
1218 * stack backtrace to a staticly assigned buffer, to allow the panic
1219 * code to find it and write it in to uncompressed pages within the
1220 * system crash dump.
1221 * Note that the frame for the starting stack pointer value is omitted because
1222 * the corresponding %eip is not known.
1223 */
1224
1225 extern char *dump_stack_scratch;
1226
1227 #if defined(__amd64)
1228
1229 void
1230 traceback(caddr_t fpreg)
1231 {
1232 struct frame *fp = (struct frame *)fpreg;
1233 struct frame *nextfp;
1234 uintptr_t pc, nextpc;
1235 ulong_t off;
1236 char args[TR_ARG_MAX * 2 + 16], *sym;
1237 uint_t offset = 0;
1238 uint_t next_offset = 0;
1239 char stack_buffer[1024];
1240
1241 if (!panicstr)
1242 printf("traceback: %%fp = %p\n", (void *)fp);
1243
1244 if (panicstr && !dump_stack_scratch) {
1245 printf("Warning - stack not written to the dump buffer\n");
1246 }
1247
1248 fp = (struct frame *)plat_traceback(fpreg);
1249 if ((uintptr_t)fp < KERNELBASE)
1250 goto out;
1251
1252 pc = fp->fr_savpc;
1253 fp = (struct frame *)fp->fr_savfp;
1254
1255 while ((uintptr_t)fp >= KERNELBASE) {
1256 /*
1257 * XX64 Until port is complete tolerate 8-byte aligned
1258 * frame pointers but flag with a warning so they can
1259 * be fixed.
1260 */
1261 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
1262 if (((uintptr_t)fp & (8 - 1)) == 0) {
1263 printf(" >> warning! 8-byte"
1264 " aligned %%fp = %p\n", (void *)fp);
1265 } else {
1266 printf(
1267 " >> mis-aligned %%fp = %p\n", (void *)fp);
1268 break;
1269 }
1270 }
1271
1272 args[0] = '\0';
1273 nextpc = (uintptr_t)fp->fr_savpc;
1274 nextfp = (struct frame *)fp->fr_savfp;
1275 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1276 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1277 mod_containing_pc((caddr_t)pc), sym, off, args);
1278 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1279 "%s:%s+%lx (%s) | ",
1280 mod_containing_pc((caddr_t)pc), sym, off, args);
1281 } else {
1282 printf("%016lx %lx (%s)\n",
1283 (uintptr_t)fp, pc, args);
1284 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1285 "%lx (%s) | ", pc, args);
1286 }
1287
1288 if (panicstr && dump_stack_scratch) {
1289 next_offset = offset + strlen(stack_buffer);
1290 if (next_offset < STACK_BUF_SIZE) {
1291 bcopy(stack_buffer, dump_stack_scratch + offset,
1292 strlen(stack_buffer));
1293 offset = next_offset;
1294 } else {
1295 /*
1296 * In attempting to save the panic stack
1297 * to the dumpbuf we have overflowed that area.
1298 * Print a warning and continue to printf the
1299 * stack to the msgbuf
1300 */
1301 printf("Warning: stack in the dump buffer"
1302 " may be incomplete\n");
1303 offset = next_offset;
1304 }
1305 }
1306
1307 pc = nextpc;
1308 fp = nextfp;
1309 }
1310 out:
1311 if (!panicstr) {
1312 printf("end of traceback\n");
1313 DELAY(2 * MICROSEC);
1314 } else if (dump_stack_scratch) {
1315 dump_stack_scratch[offset] = '\0';
1316 }
1317 }
1318
1319 #elif defined(__i386)
1320
1321 void
1322 traceback(caddr_t fpreg)
1323 {
1324 struct frame *fp = (struct frame *)fpreg;
1325 struct frame *nextfp, *minfp, *stacktop;
1326 uintptr_t pc, nextpc;
1327 uint_t offset = 0;
1328 uint_t next_offset = 0;
1329 char stack_buffer[1024];
1330
1331 cpu_t *cpu;
1332
1333 /*
1334 * args[] holds TR_ARG_MAX hex long args, plus ", " or '\0'.
1335 */
1336 char args[TR_ARG_MAX * 2 + 8], *p;
1337
1338 int on_intr;
1339 ulong_t off;
1340 char *sym;
1341
1342 if (!panicstr)
1343 printf("traceback: %%fp = %p\n", (void *)fp);
1344
1345 if (panicstr && !dump_stack_scratch) {
1346 printf("Warning - stack not written to the dumpbuf\n");
1347 }
1348
1349 /*
1350 * If we are panicking, all high-level interrupt information in
1351 * CPU was overwritten. panic_cpu has the correct values.
1352 */
1353 kpreempt_disable(); /* prevent migration */
1354
1355 cpu = (panicstr && CPU->cpu_id == panic_cpu.cpu_id)? &panic_cpu : CPU;
1356
1357 if ((on_intr = CPU_ON_INTR(cpu)) != 0)
1358 stacktop = (struct frame *)(cpu->cpu_intr_stack + SA(MINFRAME));
1359 else
1360 stacktop = (struct frame *)curthread->t_stk;
1361
1362 kpreempt_enable();
1363
1364 fp = (struct frame *)plat_traceback(fpreg);
1365 if ((uintptr_t)fp < KERNELBASE)
1366 goto out;
1367
1368 minfp = fp; /* Baseline minimum frame pointer */
1369 pc = fp->fr_savpc;
1370 fp = (struct frame *)fp->fr_savfp;
1371
1372 while ((uintptr_t)fp >= KERNELBASE) {
1373 ulong_t argc;
1374 long *argv;
1375
1376 if (fp <= minfp || fp >= stacktop) {
1377 if (on_intr) {
1378 /*
1379 * Hop from interrupt stack to thread stack.
1380 */
1381 stacktop = (struct frame *)curthread->t_stk;
1382 minfp = (struct frame *)curthread->t_stkbase;
1383 on_intr = 0;
1384 continue;
1385 }
1386 break; /* we're outside of the expected range */
1387 }
1388
1389 if ((uintptr_t)fp & (STACK_ALIGN - 1)) {
1390 printf(" >> mis-aligned %%fp = %p\n", (void *)fp);
1391 break;
1392 }
1393
1394 nextpc = fp->fr_savpc;
1395 nextfp = (struct frame *)fp->fr_savfp;
1396 argc = argcount(nextpc);
1397 argv = (long *)((char *)fp + sizeof (struct frame));
1398
1399 args[0] = '\0';
1400 p = args;
1401 while (argc-- > 0 && argv < (long *)stacktop) {
1402 p += snprintf(p, args + sizeof (args) - p,
1403 "%s%lx", (p == args) ? "" : ", ", *argv++);
1404 }
1405
1406 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
1407 printf("%08lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
1408 mod_containing_pc((caddr_t)pc), sym, off, args);
1409 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1410 "%s:%s+%lx (%s) | ",
1411 mod_containing_pc((caddr_t)pc), sym, off, args);
1412
1413 } else {
1414 printf("%08lx %lx (%s)\n",
1415 (uintptr_t)fp, pc, args);
1416 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1417 "%lx (%s) | ", pc, args);
1418
1419 }
1420
1421 if (panicstr && dump_stack_scratch) {
1422 next_offset = offset + strlen(stack_buffer);
1423 if (next_offset < STACK_BUF_SIZE) {
1424 bcopy(stack_buffer, dump_stack_scratch + offset,
1425 strlen(stack_buffer));
1426 offset = next_offset;
1427 } else {
1428 /*
1429 * In attempting to save the panic stack
1430 * to the dumpbuf we have overflowed that area.
1431 * Print a warning and continue to printf the
1432 * stack to the msgbuf
1433 */
1434 printf("Warning: stack in the dumpbuf"
1435 " may be incomplete\n");
1436 offset = next_offset;
1437 }
1438 }
1439
1440 minfp = fp;
1441 pc = nextpc;
1442 fp = nextfp;
1443 }
1444 out:
1445 if (!panicstr) {
1446 printf("end of traceback\n");
1447 DELAY(2 * MICROSEC);
1448 } else if (dump_stack_scratch) {
1449 dump_stack_scratch[offset] = '\0';
1450 }
1451
1452 }
1453
1454 #endif /* __i386 */
1455
1456 /*
1457 * Generate a stack backtrace from a saved register set.
1458 */
1459 void
1460 traceregs(struct regs *rp)
1461 {
1462 traceback((caddr_t)rp->r_fp);
1463 }
1464
1465 void
1466 exec_set_sp(size_t stksize)
1467 {
1468 klwp_t *lwp = ttolwp(curthread);
1469
1470 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1471 }
1472
1473 hrtime_t
1474 gethrtime_waitfree(void)
1475 {
1476 return (dtrace_gethrtime());
1477 }
1478
1479 hrtime_t
1480 gethrtime(void)
1481 {
1482 return (gethrtimef());
1483 }
1484
1485 hrtime_t
1486 gethrtime_unscaled(void)
1487 {
1488 return (gethrtimeunscaledf());
1489 }
1490
1491 void
1492 scalehrtime(hrtime_t *hrt)
1493 {
1494 scalehrtimef(hrt);
1495 }
1496
1497 uint64_t
1498 unscalehrtime(hrtime_t nsecs)
1499 {
1500 return (unscalehrtimef(nsecs));
1501 }
1502
1503 void
1504 gethrestime(timespec_t *tp)
1505 {
1506 gethrestimef(tp);
1507 }
1508
1509 #if defined(__amd64)
1510 /*
1511 * Part of the implementation of hres_tick(); this routine is
1512 * easier in C than assembler .. called with the hres_lock held.
1513 *
1514 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1515 */
1516
1517 #include <sys/time.h>
1518 #include <sys/machlock.h>
1519
1520 extern int one_sec;
1521 extern int max_hres_adj;
1522
1523 void
1524 __adj_hrestime(void)
1525 {
1526 long long adj;
1527
1528 if (hrestime_adj == 0)
1529 adj = 0;
1530 else if (hrestime_adj > 0) {
1531 if (hrestime_adj < max_hres_adj)
1532 adj = hrestime_adj;
1533 else
1534 adj = max_hres_adj;
1535 } else {
1536 if (hrestime_adj < -max_hres_adj)
1537 adj = -max_hres_adj;
1538 else
1539 adj = hrestime_adj;
1540 }
1541
1542 timedelta -= adj;
1543 hrestime_adj = timedelta;
1544 hrestime.tv_nsec += adj;
1545
1546 while (hrestime.tv_nsec >= NANOSEC) {
1547 one_sec++;
1548 hrestime.tv_sec++;
1549 hrestime.tv_nsec -= NANOSEC;
1550 }
1551 }
1552 #endif
1553
1554 /*
1555 * Wrapper functions to maintain backwards compability
1556 */
1557 int
1558 xcopyin(const void *uaddr, void *kaddr, size_t count)
1559 {
1560 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1561 }
1562
1563 int
1564 xcopyout(const void *kaddr, void *uaddr, size_t count)
1565 {
1566 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1567 }