365 #define APIC_AVAIL_VECTOR       (APIC_MAX_VECTOR+1-APIC_BASE_VECT)
 366 #define APIC_VECTOR_PER_IPL     0x10    /* # of vectors before PRI changes */
 367 #define APIC_VECTOR(ipl)        (apic_ipltopri[ipl] | APIC_RESV_VECT)
 368 #define APIC_VECTOR_MASK        0x0f
 369 #define APIC_HI_PRI_VECTS       2       /* vects reserved for hi pri reqs */
 370 #define APIC_IPL_MASK           0xf0
 371 #define APIC_IPL_SHIFT          4       /* >> to get ipl part of vector */
 372 #define APIC_FIRST_FREE_IRQ     0x10
 373 #define APIC_MAX_ISA_IRQ        15
 374 #define APIC_IPL0               0x0f    /* let IDLE_IPL be the lowest */
 375 #define APIC_IDLE_IPL           0x00
 376 
 377 #define APIC_MASK_ALL           0xf0    /* Mask all interrupts */
 378 
 379 /* spurious interrupt vector                                            */
 380 #define APIC_SPUR_INTR          0xFF
 381 
 382 /* special or reserve vectors */
 383 #define APIC_CHECK_RESERVE_VECTORS(v) \
 384         (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
 385         ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET))
 386 
 387 /* cmos shutdown code for BIOS                                          */
 388 #define BIOS_SHUTDOWN           0x0a
 389 
 390 /* define the entry types for BIOS information tables as defined in PC+MP */
 391 #define APIC_CPU_ENTRY          0
 392 #define APIC_BUS_ENTRY          1
 393 #define APIC_IO_ENTRY           2
 394 #define APIC_IO_INTR_ENTRY      3
 395 #define APIC_LOCAL_INTR_ENTRY   4
 396 #define APIC_MPTBL_ADDR         (639 * 1024)
 397 /*
 398  * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
 399  * of system base memory or in ROM between 0xF0000 and 0xFFFFF
 400  */
 401 #define MPFPS_RAM_WIN_LEN       1024
 402 #define MPFPS_ROM_WIN_START     (uint32_t)0xf0000
 403 #define MPFPS_ROM_WIN_LEN       0x10000
 404 
 405 #define EISA_LEVEL_CNTL         0x4D0

 365 #define APIC_AVAIL_VECTOR       (APIC_MAX_VECTOR+1-APIC_BASE_VECT)
 366 #define APIC_VECTOR_PER_IPL     0x10    /* # of vectors before PRI changes */
 367 #define APIC_VECTOR(ipl)        (apic_ipltopri[ipl] | APIC_RESV_VECT)
 368 #define APIC_VECTOR_MASK        0x0f
 369 #define APIC_HI_PRI_VECTS       2       /* vects reserved for hi pri reqs */
 370 #define APIC_IPL_MASK           0xf0
 371 #define APIC_IPL_SHIFT          4       /* >> to get ipl part of vector */
 372 #define APIC_FIRST_FREE_IRQ     0x10
 373 #define APIC_MAX_ISA_IRQ        15
 374 #define APIC_IPL0               0x0f    /* let IDLE_IPL be the lowest */
 375 #define APIC_IDLE_IPL           0x00
 376 
 377 #define APIC_MASK_ALL           0xf0    /* Mask all interrupts */
 378 
 379 /* spurious interrupt vector                                            */
 380 #define APIC_SPUR_INTR          0xFF
 381 
 382 /* special or reserve vectors */
 383 #define APIC_CHECK_RESERVE_VECTORS(v) \
 384         (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
 385         ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == 0x80))
 386 
 387 /* cmos shutdown code for BIOS                                          */
 388 #define BIOS_SHUTDOWN           0x0a
 389 
 390 /* define the entry types for BIOS information tables as defined in PC+MP */
 391 #define APIC_CPU_ENTRY          0
 392 #define APIC_BUS_ENTRY          1
 393 #define APIC_IO_ENTRY           2
 394 #define APIC_IO_INTR_ENTRY      3
 395 #define APIC_LOCAL_INTR_ENTRY   4
 396 #define APIC_MPTBL_ADDR         (639 * 1024)
 397 /*
 398  * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
 399  * of system base memory or in ROM between 0xF0000 and 0xFFFFF
 400  */
 401 #define MPFPS_RAM_WIN_LEN       1024
 402 #define MPFPS_ROM_WIN_START     (uint32_t)0xf0000
 403 #define MPFPS_ROM_WIN_LEN       0x10000
 404 
 405 #define EISA_LEVEL_CNTL         0x4D0