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OS-5192 need faster clock_gettime
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Joshua M. Clulow <jmc@joyent.com>
Reviewed by: Ryan Zezeski <ryan@zinascii.com>
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--- old/usr/src/uts/i86pc/os/mp_startup.c
+++ new/usr/src/uts/i86pc/os/mp_startup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 - * Copyright 2015 Joyent, Inc.
30 + * Copyright 2016 Joyent, Inc.
31 31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 32 */
33 33
34 34 #include <sys/types.h>
35 35 #include <sys/thread.h>
36 36 #include <sys/cpuvar.h>
37 37 #include <sys/cpu.h>
38 38 #include <sys/t_lock.h>
39 39 #include <sys/param.h>
40 40 #include <sys/proc.h>
41 41 #include <sys/disp.h>
42 42 #include <sys/class.h>
43 43 #include <sys/cmn_err.h>
44 44 #include <sys/debug.h>
45 45 #include <sys/note.h>
46 46 #include <sys/asm_linkage.h>
47 47 #include <sys/x_call.h>
48 48 #include <sys/systm.h>
49 49 #include <sys/var.h>
50 50 #include <sys/vtrace.h>
51 51 #include <vm/hat.h>
52 52 #include <vm/as.h>
53 53 #include <vm/seg_kmem.h>
54 54 #include <vm/seg_kp.h>
55 55 #include <sys/segments.h>
56 56 #include <sys/kmem.h>
57 57 #include <sys/stack.h>
58 58 #include <sys/smp_impldefs.h>
59 59 #include <sys/x86_archext.h>
60 60 #include <sys/machsystm.h>
61 61 #include <sys/traptrace.h>
62 62 #include <sys/clock.h>
63 63 #include <sys/cpc_impl.h>
64 64 #include <sys/pg.h>
65 65 #include <sys/cmt.h>
66 66 #include <sys/dtrace.h>
67 67 #include <sys/archsystm.h>
68 68 #include <sys/fp.h>
69 69 #include <sys/reboot.h>
70 70 #include <sys/kdi_machimpl.h>
71 71 #include <vm/hat_i86.h>
72 72 #include <vm/vm_dep.h>
73 73 #include <sys/memnode.h>
74 74 #include <sys/pci_cfgspace.h>
75 75 #include <sys/mach_mmu.h>
76 76 #include <sys/sysmacros.h>
77 77 #if defined(__xpv)
78 78 #include <sys/hypervisor.h>
79 79 #endif
80 80 #include <sys/cpu_module.h>
81 81 #include <sys/ontrap.h>
82 82
83 83 struct cpu cpus[1]; /* CPU data */
84 84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
85 85 struct cpu *cpu_free_list; /* list for released CPUs */
86 86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
87 87
88 88 #define cpu_next_free cpu_prev
89 89
90 90 /*
91 91 * Useful for disabling MP bring-up on a MP capable system.
92 92 */
93 93 int use_mp = 1;
94 94
95 95 /*
96 96 * to be set by a PSM to indicate what cpus
97 97 * are sitting around on the system.
98 98 */
99 99 cpuset_t mp_cpus;
100 100
101 101 /*
102 102 * This variable is used by the hat layer to decide whether or not
103 103 * critical sections are needed to prevent race conditions. For sun4m,
104 104 * this variable is set once enough MP initialization has been done in
105 105 * order to allow cross calls.
106 106 */
107 107 int flushes_require_xcalls;
108 108
109 109 cpuset_t cpu_ready_set; /* initialized in startup() */
110 110
111 111 static void mp_startup_boot(void);
112 112 static void mp_startup_hotplug(void);
113 113
114 114 static void cpu_sep_enable(void);
115 115 static void cpu_sep_disable(void);
116 116 static void cpu_asysc_enable(void);
117 117 static void cpu_asysc_disable(void);
118 118
119 119 /*
120 120 * Init CPU info - get CPU type info for processor_info system call.
121 121 */
122 122 void
123 123 init_cpu_info(struct cpu *cp)
124 124 {
125 125 processor_info_t *pi = &cp->cpu_type_info;
126 126
127 127 /*
128 128 * Get clock-frequency property for the CPU.
129 129 */
130 130 pi->pi_clock = cpu_freq;
131 131
132 132 /*
133 133 * Current frequency in Hz.
134 134 */
135 135 cp->cpu_curr_clock = cpu_freq_hz;
136 136
137 137 /*
138 138 * Supported frequencies.
139 139 */
140 140 if (cp->cpu_supp_freqs == NULL) {
141 141 cpu_set_supp_freqs(cp, NULL);
142 142 }
143 143
144 144 (void) strcpy(pi->pi_processor_type, "i386");
145 145 if (fpu_exists)
146 146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
147 147
148 148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
149 149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150 150
151 151 /*
152 152 * If called for the BSP, cp is equal to current CPU.
153 153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 156 * has been invoked on target CPU.
157 157 */
158 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
159 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
160 160 }
161 161
162 162 /*
163 163 * Configure syscall support on this CPU.
164 164 */
165 165 /*ARGSUSED*/
166 166 void
167 167 init_cpu_syscall(struct cpu *cp)
168 168 {
169 169 kpreempt_disable();
170 170
171 171 #if defined(__amd64)
172 172 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
173 173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
174 174 uint64_t flags;
175 175
176 176 #if !defined(__lint)
177 177 /*
178 178 * The syscall instruction imposes a certain ordering on
179 179 * segment selectors, so we double-check that ordering
180 180 * here.
181 181 */
182 182 ASSERT(KDS_SEL == KCS_SEL + 8);
183 183 ASSERT(UDS_SEL == U32CS_SEL + 8);
184 184 ASSERT(UCS_SEL == U32CS_SEL + 16);
185 185 #endif
186 186 /*
187 187 * Turn syscall/sysret extensions on.
188 188 */
189 189 cpu_asysc_enable();
190 190
191 191 /*
192 192 * Program the magic registers ..
193 193 */
194 194 wrmsr(MSR_AMD_STAR,
195 195 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
196 196 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
197 197 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
198 198
199 199 /*
200 200 * This list of flags is masked off the incoming
201 201 * %rfl when we enter the kernel.
202 202 */
203 203 flags = PS_IE | PS_T;
204 204 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
205 205 flags |= PS_ACHK;
206 206 wrmsr(MSR_AMD_SFMASK, flags);
207 207 }
208 208 #endif
209 209
210 210 /*
211 211 * On 32-bit kernels, we use sysenter/sysexit because it's too
212 212 * hard to use syscall/sysret, and it is more portable anyway.
213 213 *
214 214 * On 64-bit kernels on Nocona machines, the 32-bit syscall
215 215 * variant isn't available to 32-bit applications, but sysenter is.
216 216 */
217 217 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
218 218 is_x86_feature(x86_featureset, X86FSET_SEP)) {
219 219
220 220 #if !defined(__lint)
221 221 /*
222 222 * The sysenter instruction imposes a certain ordering on
223 223 * segment selectors, so we double-check that ordering
224 224 * here. See "sysenter" in Intel document 245471-012, "IA-32
225 225 * Intel Architecture Software Developer's Manual Volume 2:
226 226 * Instruction Set Reference"
227 227 */
228 228 ASSERT(KDS_SEL == KCS_SEL + 8);
229 229
230 230 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
231 231 ASSERT32(UDS_SEL == UCS_SEL + 8);
232 232
233 233 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
234 234 ASSERT64(UDS_SEL == U32CS_SEL + 8);
235 235 #endif
236 236
237 237 cpu_sep_enable();
238 238
239 239 /*
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240 240 * resume() sets this value to the base of the threads stack
241 241 * via a context handler.
242 242 */
243 243 wrmsr(MSR_INTC_SEP_ESP, 0);
244 244 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
245 245 }
246 246
247 247 kpreempt_enable();
248 248 }
249 249
250 +#if !defined(__xpv)
250 251 /*
252 + * Configure per-cpu ID GDT
253 + */
254 +static void
255 +init_cpu_id_gdt(struct cpu *cp)
256 +{
257 + /* Write cpu_id into limit field of GDT for usermode retrieval */
258 +#if defined(__amd64)
259 + set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
260 + SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
261 +#elif defined(__i386)
262 + set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
263 + SEL_UPL, SDP_BYTES, SDP_OP32);
264 +#endif
265 +}
266 +#endif /* !defined(__xpv) */
267 +
268 +/*
251 269 * Multiprocessor initialization.
252 270 *
253 271 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
254 272 * startup and idle threads for the specified CPU.
255 273 * Parameter boot is true for boot time operations and is false for CPU
256 274 * DR operations.
257 275 */
258 276 static struct cpu *
259 277 mp_cpu_configure_common(int cpun, boolean_t boot)
260 278 {
261 279 struct cpu *cp;
262 280 kthread_id_t tp;
263 281 caddr_t sp;
264 282 proc_t *procp;
265 283 #if !defined(__xpv)
266 284 extern int idle_cpu_prefer_mwait;
267 285 extern void cpu_idle_mwait();
268 286 #endif
269 287 extern void idle();
270 288 extern void cpu_idle();
271 289
272 290 #ifdef TRAPTRACE
273 291 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
274 292 #endif
275 293
276 294 ASSERT(MUTEX_HELD(&cpu_lock));
277 295 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
278 296
279 297 if (cpu_free_list == NULL) {
280 298 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
281 299 } else {
282 300 cp = cpu_free_list;
283 301 cpu_free_list = cp->cpu_next_free;
284 302 }
285 303
286 304 cp->cpu_m.mcpu_istamp = cpun << 16;
287 305
288 306 /* Create per CPU specific threads in the process p0. */
289 307 procp = &p0;
290 308
291 309 /*
292 310 * Initialize the dispatcher first.
293 311 */
294 312 disp_cpu_init(cp);
295 313
296 314 cpu_vm_data_init(cp);
297 315
298 316 /*
299 317 * Allocate and initialize the startup thread for this CPU.
300 318 * Interrupt and process switch stacks get allocated later
301 319 * when the CPU starts running.
302 320 */
303 321 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
304 322 TS_STOPPED, maxclsyspri);
305 323
306 324 /*
307 325 * Set state to TS_ONPROC since this thread will start running
308 326 * as soon as the CPU comes online.
309 327 *
310 328 * All the other fields of the thread structure are setup by
311 329 * thread_create().
312 330 */
313 331 THREAD_ONPROC(tp, cp);
314 332 tp->t_preempt = 1;
315 333 tp->t_bound_cpu = cp;
316 334 tp->t_affinitycnt = 1;
317 335 tp->t_cpu = cp;
318 336 tp->t_disp_queue = cp->cpu_disp;
319 337
320 338 /*
321 339 * Setup thread to start in mp_startup_common.
322 340 */
323 341 sp = tp->t_stk;
324 342 tp->t_sp = (uintptr_t)(sp - MINFRAME);
325 343 #if defined(__amd64)
326 344 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
327 345 #endif
328 346 /*
329 347 * Setup thread start entry point for boot or hotplug.
330 348 */
331 349 if (boot) {
332 350 tp->t_pc = (uintptr_t)mp_startup_boot;
333 351 } else {
334 352 tp->t_pc = (uintptr_t)mp_startup_hotplug;
335 353 }
336 354
337 355 cp->cpu_id = cpun;
338 356 cp->cpu_self = cp;
339 357 cp->cpu_thread = tp;
340 358 cp->cpu_lwp = NULL;
341 359 cp->cpu_dispthread = tp;
342 360 cp->cpu_dispatch_pri = DISP_PRIO(tp);
343 361
344 362 /*
345 363 * cpu_base_spl must be set explicitly here to prevent any blocking
346 364 * operations in mp_startup_common from causing the spl of the cpu
347 365 * to drop to 0 (allowing device interrupts before we're ready) in
348 366 * resume().
349 367 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
350 368 * As an extra bit of security on DEBUG kernels, this is enforced with
351 369 * an assertion in mp_startup_common() -- before cpu_base_spl is set
352 370 * to its proper value.
353 371 */
354 372 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
355 373
356 374 /*
357 375 * Now, initialize per-CPU idle thread for this CPU.
358 376 */
359 377 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
360 378
361 379 cp->cpu_idle_thread = tp;
362 380
363 381 tp->t_preempt = 1;
364 382 tp->t_bound_cpu = cp;
365 383 tp->t_affinitycnt = 1;
366 384 tp->t_cpu = cp;
367 385 tp->t_disp_queue = cp->cpu_disp;
368 386
369 387 /*
370 388 * Bootstrap the CPU's PG data
371 389 */
372 390 pg_cpu_bootstrap(cp);
373 391
374 392 /*
375 393 * Perform CPC initialization on the new CPU.
376 394 */
377 395 kcpc_hw_init(cp);
378 396
379 397 /*
380 398 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
381 399 * for each CPU.
382 400 */
383 401 setup_vaddr_for_ppcopy(cp);
384 402
385 403 /*
386 404 * Allocate page for new GDT and initialize from current GDT.
387 405 */
388 406 #if !defined(__lint)
389 407 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
390 408 #endif
391 409 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
392 410 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
393 411
394 412 #if defined(__i386)
395 413 /*
396 414 * setup kernel %gs.
397 415 */
398 416 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
399 417 SEL_KPL, 0, 1);
400 418 #endif
401 419
402 420 /*
403 421 * If we have more than one node, each cpu gets a copy of IDT
404 422 * local to its node. If this is a Pentium box, we use cpu 0's
405 423 * IDT. cpu 0's IDT has been made read-only to workaround the
406 424 * cmpxchgl register bug
407 425 */
408 426 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
409 427 #if !defined(__lint)
410 428 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
411 429 #endif
412 430 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
413 431 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
414 432 } else {
415 433 cp->cpu_idt = CPU->cpu_idt;
416 434 }
417 435
418 436 /*
419 437 * alloc space for cpuid info
420 438 */
421 439 cpuid_alloc_space(cp);
422 440 #if !defined(__xpv)
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423 441 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
424 442 idle_cpu_prefer_mwait) {
425 443 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
426 444 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
427 445 } else
428 446 #endif
429 447 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
430 448
431 449 init_cpu_info(cp);
432 450
451 +#if !defined(__xpv)
452 + init_cpu_id_gdt(cp);
453 +#endif
454 +
433 455 /*
434 456 * alloc space for ucode_info
435 457 */
436 458 ucode_alloc_space(cp);
437 459 xc_init_cpu(cp);
438 460 hat_cpu_online(cp);
439 461
440 462 #ifdef TRAPTRACE
441 463 /*
442 464 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
443 465 */
444 466 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
445 467 ttc->ttc_next = ttc->ttc_first;
446 468 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
447 469 #endif
448 470
449 471 /*
450 472 * Record that we have another CPU.
451 473 */
452 474 /*
453 475 * Initialize the interrupt threads for this CPU
454 476 */
455 477 cpu_intr_alloc(cp, NINTR_THREADS);
456 478
457 479 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
458 480 cpu_set_state(cp);
459 481
460 482 /*
461 483 * Add CPU to list of available CPUs. It'll be on the active list
462 484 * after mp_startup_common().
463 485 */
464 486 cpu_add_unit(cp);
465 487
466 488 return (cp);
467 489 }
468 490
469 491 /*
470 492 * Undo what was done in mp_cpu_configure_common
471 493 */
472 494 static void
473 495 mp_cpu_unconfigure_common(struct cpu *cp, int error)
474 496 {
475 497 ASSERT(MUTEX_HELD(&cpu_lock));
476 498
477 499 /*
478 500 * Remove the CPU from the list of available CPUs.
479 501 */
480 502 cpu_del_unit(cp->cpu_id);
481 503
482 504 if (error == ETIMEDOUT) {
483 505 /*
484 506 * The cpu was started, but never *seemed* to run any
485 507 * code in the kernel; it's probably off spinning in its
486 508 * own private world, though with potential references to
487 509 * our kmem-allocated IDTs and GDTs (for example).
488 510 *
489 511 * Worse still, it may actually wake up some time later,
490 512 * so rather than guess what it might or might not do, we
491 513 * leave the fundamental data structures intact.
492 514 */
493 515 cp->cpu_flags = 0;
494 516 return;
495 517 }
496 518
497 519 /*
498 520 * At this point, the only threads bound to this CPU should
499 521 * special per-cpu threads: it's idle thread, it's pause threads,
500 522 * and it's interrupt threads. Clean these up.
501 523 */
502 524 cpu_destroy_bound_threads(cp);
503 525 cp->cpu_idle_thread = NULL;
504 526
505 527 /*
506 528 * Free the interrupt stack.
507 529 */
508 530 segkp_release(segkp,
509 531 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
510 532 cp->cpu_intr_stack = NULL;
511 533
512 534 #ifdef TRAPTRACE
513 535 /*
514 536 * Discard the trap trace buffer
515 537 */
516 538 {
517 539 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
518 540
519 541 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
520 542 ttc->ttc_first = NULL;
521 543 }
522 544 #endif
523 545
524 546 hat_cpu_offline(cp);
525 547
526 548 ucode_free_space(cp);
527 549
528 550 /* Free CPU ID string and brand string. */
529 551 if (cp->cpu_idstr) {
530 552 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
531 553 cp->cpu_idstr = NULL;
532 554 }
533 555 if (cp->cpu_brandstr) {
534 556 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
535 557 cp->cpu_brandstr = NULL;
536 558 }
537 559
538 560 #if !defined(__xpv)
539 561 if (cp->cpu_m.mcpu_mwait != NULL) {
540 562 cpuid_mwait_free(cp);
541 563 cp->cpu_m.mcpu_mwait = NULL;
542 564 }
543 565 #endif
544 566 cpuid_free_space(cp);
545 567
546 568 if (cp->cpu_idt != CPU->cpu_idt)
547 569 kmem_free(cp->cpu_idt, PAGESIZE);
548 570 cp->cpu_idt = NULL;
549 571
550 572 kmem_free(cp->cpu_gdt, PAGESIZE);
551 573 cp->cpu_gdt = NULL;
552 574
553 575 if (cp->cpu_supp_freqs != NULL) {
554 576 size_t len = strlen(cp->cpu_supp_freqs) + 1;
555 577 kmem_free(cp->cpu_supp_freqs, len);
556 578 cp->cpu_supp_freqs = NULL;
557 579 }
558 580
559 581 teardown_vaddr_for_ppcopy(cp);
560 582
561 583 kcpc_hw_fini(cp);
562 584
563 585 cp->cpu_dispthread = NULL;
564 586 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
565 587
566 588 cpu_vm_data_destroy(cp);
567 589
568 590 xc_fini_cpu(cp);
569 591 disp_cpu_fini(cp);
570 592
571 593 ASSERT(cp != CPU0);
572 594 bzero(cp, sizeof (*cp));
573 595 cp->cpu_next_free = cpu_free_list;
574 596 cpu_free_list = cp;
575 597 }
576 598
577 599 /*
578 600 * Apply workarounds for known errata, and warn about those that are absent.
579 601 *
580 602 * System vendors occasionally create configurations which contain different
581 603 * revisions of the CPUs that are almost but not exactly the same. At the
582 604 * time of writing, this meant that their clock rates were the same, their
583 605 * feature sets were the same, but the required workaround were -not-
584 606 * necessarily the same. So, this routine is invoked on -every- CPU soon
585 607 * after starting to make sure that the resulting system contains the most
586 608 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
587 609 * system.
588 610 *
589 611 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
590 612 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
591 613 * prior to acknowledging their readiness to the master, so this routine will
592 614 * never be executed by multiple CPUs in parallel, thus making updates to
593 615 * global data safe.
594 616 *
595 617 * These workarounds are based on Rev 3.57 of the Revision Guide for
596 618 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
597 619 */
598 620
599 621 #if defined(OPTERON_ERRATUM_88)
600 622 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
601 623 #endif
602 624
603 625 #if defined(OPTERON_ERRATUM_91)
604 626 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
605 627 #endif
606 628
607 629 #if defined(OPTERON_ERRATUM_93)
608 630 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
609 631 #endif
610 632
611 633 #if defined(OPTERON_ERRATUM_95)
612 634 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
613 635 #endif
614 636
615 637 #if defined(OPTERON_ERRATUM_100)
616 638 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
617 639 #endif
618 640
619 641 #if defined(OPTERON_ERRATUM_108)
620 642 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
621 643 #endif
622 644
623 645 #if defined(OPTERON_ERRATUM_109)
624 646 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
625 647 #endif
626 648
627 649 #if defined(OPTERON_ERRATUM_121)
628 650 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
629 651 #endif
630 652
631 653 #if defined(OPTERON_ERRATUM_122)
632 654 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
633 655 #endif
634 656
635 657 #if defined(OPTERON_ERRATUM_123)
636 658 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
637 659 #endif
638 660
639 661 #if defined(OPTERON_ERRATUM_131)
640 662 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
641 663 #endif
642 664
643 665 #if defined(OPTERON_WORKAROUND_6336786)
644 666 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
645 667 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
646 668 #endif
647 669
648 670 #if defined(OPTERON_WORKAROUND_6323525)
649 671 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
650 672 #endif
651 673
652 674 #if defined(OPTERON_ERRATUM_298)
653 675 int opteron_erratum_298;
654 676 #endif
655 677
656 678 #if defined(OPTERON_ERRATUM_721)
657 679 int opteron_erratum_721;
658 680 #endif
659 681
660 682 static void
661 683 workaround_warning(cpu_t *cp, uint_t erratum)
662 684 {
663 685 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
664 686 cp->cpu_id, erratum);
665 687 }
666 688
667 689 static void
668 690 workaround_applied(uint_t erratum)
669 691 {
670 692 if (erratum > 1000000)
671 693 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
672 694 erratum);
673 695 else
674 696 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
675 697 erratum);
676 698 }
677 699
678 700 static void
679 701 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
680 702 {
681 703 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
682 704 cp->cpu_id, rw, msr, error);
683 705 }
684 706
685 707 /*
686 708 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
687 709 * system.
688 710 */
689 711 static uint_t
690 712 opteron_get_nnodes(void)
691 713 {
692 714 static uint_t nnodes = 0;
693 715
694 716 if (nnodes == 0) {
695 717 #ifdef DEBUG
696 718 uint_t family;
697 719
698 720 /*
699 721 * This routine uses a PCI config space based mechanism
700 722 * for retrieving the number of nodes in the system.
701 723 * Device 24, function 0, offset 0x60 as used here is not
702 724 * AMD processor architectural, and may not work on processor
703 725 * families other than those listed below.
704 726 *
705 727 * Callers of this routine must ensure that we're running on
706 728 * a processor which supports this mechanism.
707 729 * The assertion below is meant to catch calls on unsupported
708 730 * processors.
709 731 */
710 732 family = cpuid_getfamily(CPU);
711 733 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
712 734 #endif /* DEBUG */
713 735
714 736 /*
715 737 * Obtain the number of nodes in the system from
716 738 * bits [6:4] of the Node ID register on node 0.
717 739 *
718 740 * The actual node count is NodeID[6:4] + 1
719 741 *
720 742 * The Node ID register is accessed via function 0,
721 743 * offset 0x60. Node 0 is device 24.
722 744 */
723 745 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
724 746 }
725 747 return (nnodes);
726 748 }
727 749
728 750 uint_t
729 751 do_erratum_298(struct cpu *cpu)
730 752 {
731 753 static int osvwrc = -3;
732 754 extern int osvw_opteron_erratum(cpu_t *, uint_t);
733 755
734 756 /*
735 757 * L2 Eviction May Occur During Processor Operation To Set
736 758 * Accessed or Dirty Bit.
737 759 */
738 760 if (osvwrc == -3) {
739 761 osvwrc = osvw_opteron_erratum(cpu, 298);
740 762 } else {
741 763 /* osvw return codes should be consistent for all cpus */
742 764 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
743 765 }
744 766
745 767 switch (osvwrc) {
746 768 case 0: /* erratum is not present: do nothing */
747 769 break;
748 770 case 1: /* erratum is present: BIOS workaround applied */
749 771 /*
750 772 * check if workaround is actually in place and issue warning
751 773 * if not.
752 774 */
753 775 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
754 776 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
755 777 #if defined(OPTERON_ERRATUM_298)
756 778 opteron_erratum_298++;
757 779 #else
758 780 workaround_warning(cpu, 298);
759 781 return (1);
760 782 #endif
761 783 }
762 784 break;
763 785 case -1: /* cannot determine via osvw: check cpuid */
764 786 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
765 787 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
766 788 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
767 789 #if defined(OPTERON_ERRATUM_298)
768 790 opteron_erratum_298++;
769 791 #else
770 792 workaround_warning(cpu, 298);
771 793 return (1);
772 794 #endif
773 795 }
774 796 break;
775 797 }
776 798 return (0);
777 799 }
778 800
779 801 uint_t
780 802 workaround_errata(struct cpu *cpu)
781 803 {
782 804 uint_t missing = 0;
783 805
784 806 ASSERT(cpu == CPU);
785 807
786 808 /*LINTED*/
787 809 if (cpuid_opteron_erratum(cpu, 88) > 0) {
788 810 /*
789 811 * SWAPGS May Fail To Read Correct GS Base
790 812 */
791 813 #if defined(OPTERON_ERRATUM_88)
792 814 /*
793 815 * The workaround is an mfence in the relevant assembler code
794 816 */
795 817 opteron_erratum_88++;
796 818 #else
797 819 workaround_warning(cpu, 88);
798 820 missing++;
799 821 #endif
800 822 }
801 823
802 824 if (cpuid_opteron_erratum(cpu, 91) > 0) {
803 825 /*
804 826 * Software Prefetches May Report A Page Fault
805 827 */
806 828 #if defined(OPTERON_ERRATUM_91)
807 829 /*
808 830 * fix is in trap.c
809 831 */
810 832 opteron_erratum_91++;
811 833 #else
812 834 workaround_warning(cpu, 91);
813 835 missing++;
814 836 #endif
815 837 }
816 838
817 839 if (cpuid_opteron_erratum(cpu, 93) > 0) {
818 840 /*
819 841 * RSM Auto-Halt Restart Returns to Incorrect RIP
820 842 */
821 843 #if defined(OPTERON_ERRATUM_93)
822 844 /*
823 845 * fix is in trap.c
824 846 */
825 847 opteron_erratum_93++;
826 848 #else
827 849 workaround_warning(cpu, 93);
828 850 missing++;
829 851 #endif
830 852 }
831 853
832 854 /*LINTED*/
833 855 if (cpuid_opteron_erratum(cpu, 95) > 0) {
834 856 /*
835 857 * RET Instruction May Return to Incorrect EIP
836 858 */
837 859 #if defined(OPTERON_ERRATUM_95)
838 860 #if defined(_LP64)
839 861 /*
840 862 * Workaround this by ensuring that 32-bit user code and
841 863 * 64-bit kernel code never occupy the same address
842 864 * range mod 4G.
843 865 */
844 866 if (_userlimit32 > 0xc0000000ul)
845 867 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
846 868
847 869 /*LINTED*/
848 870 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
849 871 opteron_erratum_95++;
850 872 #endif /* _LP64 */
851 873 #else
852 874 workaround_warning(cpu, 95);
853 875 missing++;
854 876 #endif
855 877 }
856 878
857 879 if (cpuid_opteron_erratum(cpu, 100) > 0) {
858 880 /*
859 881 * Compatibility Mode Branches Transfer to Illegal Address
860 882 */
861 883 #if defined(OPTERON_ERRATUM_100)
862 884 /*
863 885 * fix is in trap.c
864 886 */
865 887 opteron_erratum_100++;
866 888 #else
867 889 workaround_warning(cpu, 100);
868 890 missing++;
869 891 #endif
870 892 }
871 893
872 894 /*LINTED*/
873 895 if (cpuid_opteron_erratum(cpu, 108) > 0) {
874 896 /*
875 897 * CPUID Instruction May Return Incorrect Model Number In
876 898 * Some Processors
877 899 */
878 900 #if defined(OPTERON_ERRATUM_108)
879 901 /*
880 902 * (Our cpuid-handling code corrects the model number on
881 903 * those processors)
882 904 */
883 905 #else
884 906 workaround_warning(cpu, 108);
885 907 missing++;
886 908 #endif
887 909 }
888 910
889 911 /*LINTED*/
890 912 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
891 913 /*
892 914 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
893 915 */
894 916 #if defined(OPTERON_ERRATUM_109)
895 917 /*
896 918 * The "workaround" is to print a warning to upgrade the BIOS
897 919 */
898 920 uint64_t value;
899 921 const uint_t msr = MSR_AMD_PATCHLEVEL;
900 922 int err;
901 923
902 924 if ((err = checked_rdmsr(msr, &value)) != 0) {
903 925 msr_warning(cpu, "rd", msr, err);
904 926 workaround_warning(cpu, 109);
905 927 missing++;
906 928 }
907 929 if (value == 0)
908 930 opteron_erratum_109++;
909 931 #else
910 932 workaround_warning(cpu, 109);
911 933 missing++;
912 934 #endif
913 935 /*CONSTANTCONDITION*/
914 936 } while (0);
915 937
916 938 /*LINTED*/
917 939 if (cpuid_opteron_erratum(cpu, 121) > 0) {
918 940 /*
919 941 * Sequential Execution Across Non_Canonical Boundary Caused
920 942 * Processor Hang
921 943 */
922 944 #if defined(OPTERON_ERRATUM_121)
923 945 #if defined(_LP64)
924 946 /*
925 947 * Erratum 121 is only present in long (64 bit) mode.
926 948 * Workaround is to include the page immediately before the
927 949 * va hole to eliminate the possibility of system hangs due to
928 950 * sequential execution across the va hole boundary.
929 951 */
930 952 if (opteron_erratum_121)
931 953 opteron_erratum_121++;
932 954 else {
933 955 if (hole_start) {
934 956 hole_start -= PAGESIZE;
935 957 } else {
936 958 /*
937 959 * hole_start not yet initialized by
938 960 * mmu_init. Initialize hole_start
939 961 * with value to be subtracted.
940 962 */
941 963 hole_start = PAGESIZE;
942 964 }
943 965 opteron_erratum_121++;
944 966 }
945 967 #endif /* _LP64 */
946 968 #else
947 969 workaround_warning(cpu, 121);
948 970 missing++;
949 971 #endif
950 972 }
951 973
952 974 /*LINTED*/
953 975 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
954 976 /*
955 977 * TLB Flush Filter May Cause Coherency Problem in
956 978 * Multiprocessor Systems
957 979 */
958 980 #if defined(OPTERON_ERRATUM_122)
959 981 uint64_t value;
960 982 const uint_t msr = MSR_AMD_HWCR;
961 983 int error;
962 984
963 985 /*
964 986 * Erratum 122 is only present in MP configurations (multi-core
965 987 * or multi-processor).
966 988 */
967 989 #if defined(__xpv)
968 990 if (!DOMAIN_IS_INITDOMAIN(xen_info))
969 991 break;
970 992 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
971 993 break;
972 994 #else
973 995 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
974 996 cpuid_get_ncpu_per_chip(cpu) == 1)
975 997 break;
976 998 #endif
977 999 /* disable TLB Flush Filter */
978 1000
979 1001 if ((error = checked_rdmsr(msr, &value)) != 0) {
980 1002 msr_warning(cpu, "rd", msr, error);
981 1003 workaround_warning(cpu, 122);
982 1004 missing++;
983 1005 } else {
984 1006 value |= (uint64_t)AMD_HWCR_FFDIS;
985 1007 if ((error = checked_wrmsr(msr, value)) != 0) {
986 1008 msr_warning(cpu, "wr", msr, error);
987 1009 workaround_warning(cpu, 122);
988 1010 missing++;
989 1011 }
990 1012 }
991 1013 opteron_erratum_122++;
992 1014 #else
993 1015 workaround_warning(cpu, 122);
994 1016 missing++;
995 1017 #endif
996 1018 /*CONSTANTCONDITION*/
997 1019 } while (0);
998 1020
999 1021 /*LINTED*/
1000 1022 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1001 1023 /*
1002 1024 * Bypassed Reads May Cause Data Corruption of System Hang in
1003 1025 * Dual Core Processors
1004 1026 */
1005 1027 #if defined(OPTERON_ERRATUM_123)
1006 1028 uint64_t value;
1007 1029 const uint_t msr = MSR_AMD_PATCHLEVEL;
1008 1030 int err;
1009 1031
1010 1032 /*
1011 1033 * Erratum 123 applies only to multi-core cpus.
1012 1034 */
1013 1035 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1014 1036 break;
1015 1037 #if defined(__xpv)
1016 1038 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1017 1039 break;
1018 1040 #endif
1019 1041 /*
1020 1042 * The "workaround" is to print a warning to upgrade the BIOS
1021 1043 */
1022 1044 if ((err = checked_rdmsr(msr, &value)) != 0) {
1023 1045 msr_warning(cpu, "rd", msr, err);
1024 1046 workaround_warning(cpu, 123);
1025 1047 missing++;
1026 1048 }
1027 1049 if (value == 0)
1028 1050 opteron_erratum_123++;
1029 1051 #else
1030 1052 workaround_warning(cpu, 123);
1031 1053 missing++;
1032 1054
1033 1055 #endif
1034 1056 /*CONSTANTCONDITION*/
1035 1057 } while (0);
1036 1058
1037 1059 /*LINTED*/
1038 1060 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1039 1061 /*
1040 1062 * Multiprocessor Systems with Four or More Cores May Deadlock
1041 1063 * Waiting for a Probe Response
1042 1064 */
1043 1065 #if defined(OPTERON_ERRATUM_131)
1044 1066 uint64_t nbcfg;
1045 1067 const uint_t msr = MSR_AMD_NB_CFG;
1046 1068 const uint64_t wabits =
1047 1069 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1048 1070 int error;
1049 1071
1050 1072 /*
1051 1073 * Erratum 131 applies to any system with four or more cores.
1052 1074 */
1053 1075 if (opteron_erratum_131)
1054 1076 break;
1055 1077 #if defined(__xpv)
1056 1078 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1057 1079 break;
1058 1080 if (xpv_nr_phys_cpus() < 4)
1059 1081 break;
1060 1082 #else
1061 1083 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1062 1084 break;
1063 1085 #endif
1064 1086 /*
1065 1087 * Print a warning if neither of the workarounds for
1066 1088 * erratum 131 is present.
1067 1089 */
1068 1090 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1069 1091 msr_warning(cpu, "rd", msr, error);
1070 1092 workaround_warning(cpu, 131);
1071 1093 missing++;
1072 1094 } else if ((nbcfg & wabits) == 0) {
1073 1095 opteron_erratum_131++;
1074 1096 } else {
1075 1097 /* cannot have both workarounds set */
1076 1098 ASSERT((nbcfg & wabits) != wabits);
1077 1099 }
1078 1100 #else
1079 1101 workaround_warning(cpu, 131);
1080 1102 missing++;
1081 1103 #endif
1082 1104 /*CONSTANTCONDITION*/
1083 1105 } while (0);
1084 1106
1085 1107 /*
1086 1108 * This isn't really an erratum, but for convenience the
1087 1109 * detection/workaround code lives here and in cpuid_opteron_erratum.
1088 1110 */
1089 1111 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1090 1112 #if defined(OPTERON_WORKAROUND_6336786)
1091 1113 /*
1092 1114 * Disable C1-Clock ramping on multi-core/multi-processor
1093 1115 * K8 platforms to guard against TSC drift.
1094 1116 */
1095 1117 if (opteron_workaround_6336786) {
1096 1118 opteron_workaround_6336786++;
1097 1119 #if defined(__xpv)
1098 1120 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1099 1121 xpv_nr_phys_cpus() > 1) ||
1100 1122 opteron_workaround_6336786_UP) {
1101 1123 /*
1102 1124 * XXPV Hmm. We can't walk the Northbridges on
1103 1125 * the hypervisor; so just complain and drive
1104 1126 * on. This probably needs to be fixed in
1105 1127 * the hypervisor itself.
1106 1128 */
1107 1129 opteron_workaround_6336786++;
1108 1130 workaround_warning(cpu, 6336786);
1109 1131 #else /* __xpv */
1110 1132 } else if ((opteron_get_nnodes() *
1111 1133 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1112 1134 opteron_workaround_6336786_UP) {
1113 1135
1114 1136 uint_t node, nnodes;
1115 1137 uint8_t data;
1116 1138
1117 1139 nnodes = opteron_get_nnodes();
1118 1140 for (node = 0; node < nnodes; node++) {
1119 1141 /*
1120 1142 * Clear PMM7[1:0] (function 3, offset 0x87)
1121 1143 * Northbridge device is the node id + 24.
1122 1144 */
1123 1145 data = pci_getb_func(0, node + 24, 3, 0x87);
1124 1146 data &= 0xFC;
1125 1147 pci_putb_func(0, node + 24, 3, 0x87, data);
1126 1148 }
1127 1149 opteron_workaround_6336786++;
1128 1150 #endif /* __xpv */
1129 1151 }
1130 1152 #else
1131 1153 workaround_warning(cpu, 6336786);
1132 1154 missing++;
1133 1155 #endif
1134 1156 }
1135 1157
1136 1158 /*LINTED*/
1137 1159 /*
1138 1160 * Mutex primitives don't work as expected.
1139 1161 */
1140 1162 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1141 1163 #if defined(OPTERON_WORKAROUND_6323525)
1142 1164 /*
1143 1165 * This problem only occurs with 2 or more cores. If bit in
1144 1166 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1145 1167 * is to patch the semaphone routines with the lfence
1146 1168 * instruction to provide necessary load memory barrier with
1147 1169 * possible subsequent read-modify-write ops.
1148 1170 *
1149 1171 * It is too early in boot to call the patch routine so
1150 1172 * set erratum variable to be done in startup_end().
1151 1173 */
1152 1174 if (opteron_workaround_6323525) {
1153 1175 opteron_workaround_6323525++;
1154 1176 #if defined(__xpv)
1155 1177 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1156 1178 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1157 1179 /*
1158 1180 * XXPV Use dom0_msr here when extended
1159 1181 * operations are supported?
1160 1182 */
1161 1183 if (xpv_nr_phys_cpus() > 1)
1162 1184 opteron_workaround_6323525++;
1163 1185 } else {
1164 1186 /*
1165 1187 * We have no way to tell how many physical
1166 1188 * cpus there are, or even if this processor
1167 1189 * has the problem, so enable the workaround
1168 1190 * unconditionally (at some performance cost).
1169 1191 */
1170 1192 opteron_workaround_6323525++;
1171 1193 }
1172 1194 #else /* __xpv */
1173 1195 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1174 1196 ((opteron_get_nnodes() *
1175 1197 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1176 1198 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1177 1199 opteron_workaround_6323525++;
1178 1200 #endif /* __xpv */
1179 1201 }
1180 1202 #else
1181 1203 workaround_warning(cpu, 6323525);
1182 1204 missing++;
1183 1205 #endif
1184 1206 }
1185 1207
1186 1208 missing += do_erratum_298(cpu);
1187 1209
1188 1210 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1189 1211 #if defined(OPTERON_ERRATUM_721)
1190 1212 on_trap_data_t otd;
1191 1213
1192 1214 if (!on_trap(&otd, OT_DATA_ACCESS))
1193 1215 wrmsr(MSR_AMD_DE_CFG,
1194 1216 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1195 1217 no_trap();
1196 1218
1197 1219 opteron_erratum_721++;
1198 1220 #else
1199 1221 workaround_warning(cpu, 721);
1200 1222 missing++;
1201 1223 #endif
1202 1224 }
1203 1225
1204 1226 #ifdef __xpv
1205 1227 return (0);
1206 1228 #else
1207 1229 return (missing);
1208 1230 #endif
1209 1231 }
1210 1232
1211 1233 void
1212 1234 workaround_errata_end()
1213 1235 {
1214 1236 #if defined(OPTERON_ERRATUM_88)
1215 1237 if (opteron_erratum_88)
1216 1238 workaround_applied(88);
1217 1239 #endif
1218 1240 #if defined(OPTERON_ERRATUM_91)
1219 1241 if (opteron_erratum_91)
1220 1242 workaround_applied(91);
1221 1243 #endif
1222 1244 #if defined(OPTERON_ERRATUM_93)
1223 1245 if (opteron_erratum_93)
1224 1246 workaround_applied(93);
1225 1247 #endif
1226 1248 #if defined(OPTERON_ERRATUM_95)
1227 1249 if (opteron_erratum_95)
1228 1250 workaround_applied(95);
1229 1251 #endif
1230 1252 #if defined(OPTERON_ERRATUM_100)
1231 1253 if (opteron_erratum_100)
1232 1254 workaround_applied(100);
1233 1255 #endif
1234 1256 #if defined(OPTERON_ERRATUM_108)
1235 1257 if (opteron_erratum_108)
1236 1258 workaround_applied(108);
1237 1259 #endif
1238 1260 #if defined(OPTERON_ERRATUM_109)
1239 1261 if (opteron_erratum_109) {
1240 1262 cmn_err(CE_WARN,
1241 1263 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1242 1264 " processor\nerratum 109 was not detected; updating your"
1243 1265 " system's BIOS to a version\ncontaining this"
1244 1266 " microcode patch is HIGHLY recommended or erroneous"
1245 1267 " system\noperation may occur.\n");
1246 1268 }
1247 1269 #endif
1248 1270 #if defined(OPTERON_ERRATUM_121)
1249 1271 if (opteron_erratum_121)
1250 1272 workaround_applied(121);
1251 1273 #endif
1252 1274 #if defined(OPTERON_ERRATUM_122)
1253 1275 if (opteron_erratum_122)
1254 1276 workaround_applied(122);
1255 1277 #endif
1256 1278 #if defined(OPTERON_ERRATUM_123)
1257 1279 if (opteron_erratum_123) {
1258 1280 cmn_err(CE_WARN,
1259 1281 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1260 1282 " processor\nerratum 123 was not detected; updating your"
1261 1283 " system's BIOS to a version\ncontaining this"
1262 1284 " microcode patch is HIGHLY recommended or erroneous"
1263 1285 " system\noperation may occur.\n");
1264 1286 }
1265 1287 #endif
1266 1288 #if defined(OPTERON_ERRATUM_131)
1267 1289 if (opteron_erratum_131) {
1268 1290 cmn_err(CE_WARN,
1269 1291 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1270 1292 " processor\nerratum 131 was not detected; updating your"
1271 1293 " system's BIOS to a version\ncontaining this"
1272 1294 " microcode patch is HIGHLY recommended or erroneous"
1273 1295 " system\noperation may occur.\n");
1274 1296 }
1275 1297 #endif
1276 1298 #if defined(OPTERON_WORKAROUND_6336786)
1277 1299 if (opteron_workaround_6336786)
1278 1300 workaround_applied(6336786);
1279 1301 #endif
1280 1302 #if defined(OPTERON_WORKAROUND_6323525)
1281 1303 if (opteron_workaround_6323525)
1282 1304 workaround_applied(6323525);
1283 1305 #endif
1284 1306 #if defined(OPTERON_ERRATUM_298)
1285 1307 if (opteron_erratum_298) {
1286 1308 cmn_err(CE_WARN,
1287 1309 "BIOS microcode patch for AMD 64/Opteron(tm)"
1288 1310 " processor\nerratum 298 was not detected; updating your"
1289 1311 " system's BIOS to a version\ncontaining this"
1290 1312 " microcode patch is HIGHLY recommended or erroneous"
1291 1313 " system\noperation may occur.\n");
1292 1314 }
1293 1315 #endif
1294 1316 #if defined(OPTERON_ERRATUM_721)
1295 1317 if (opteron_erratum_721)
1296 1318 workaround_applied(721);
1297 1319 #endif
1298 1320 }
1299 1321
1300 1322 /*
1301 1323 * The procset_slave and procset_master are used to synchronize
1302 1324 * between the control CPU and the target CPU when starting CPUs.
1303 1325 */
1304 1326 static cpuset_t procset_slave, procset_master;
1305 1327
1306 1328 static void
1307 1329 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1308 1330 {
1309 1331 cpuset_t tempset;
1310 1332
1311 1333 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1312 1334 tempset = *(volatile cpuset_t *)sp) {
1313 1335 SMT_PAUSE();
1314 1336 }
1315 1337 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1316 1338 }
1317 1339
1318 1340 static void
1319 1341 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1320 1342 {
1321 1343 cpuset_t tempset;
1322 1344
1323 1345 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1324 1346 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1325 1347 tempset = *(volatile cpuset_t *)sp) {
1326 1348 SMT_PAUSE();
1327 1349 }
1328 1350 }
1329 1351
1330 1352 int
1331 1353 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1332 1354 {
1333 1355 _NOTE(ARGUNUSED(boot));
1334 1356
1335 1357 void *ctx;
1336 1358 int delays;
1337 1359 int error = 0;
1338 1360 cpuset_t tempset;
1339 1361 processorid_t cpuid;
1340 1362 #ifndef __xpv
1341 1363 extern void cpupm_init(cpu_t *);
1342 1364 #endif
1343 1365
1344 1366 ASSERT(cp != NULL);
1345 1367 cpuid = cp->cpu_id;
1346 1368 ctx = mach_cpucontext_alloc(cp);
1347 1369 if (ctx == NULL) {
1348 1370 cmn_err(CE_WARN,
1349 1371 "cpu%d: failed to allocate context", cp->cpu_id);
1350 1372 return (EAGAIN);
1351 1373 }
1352 1374 error = mach_cpu_start(cp, ctx);
1353 1375 if (error != 0) {
1354 1376 cmn_err(CE_WARN,
1355 1377 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1356 1378 mach_cpucontext_free(cp, ctx, error);
1357 1379 return (error);
1358 1380 }
1359 1381
1360 1382 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1361 1383 delays++) {
1362 1384 if (delays == 500) {
1363 1385 /*
1364 1386 * After five seconds, things are probably looking
1365 1387 * a bit bleak - explain the hang.
1366 1388 */
1367 1389 cmn_err(CE_NOTE, "cpu%d: started, "
1368 1390 "but not running in the kernel yet", cpuid);
1369 1391 } else if (delays > 2000) {
1370 1392 /*
1371 1393 * We waited at least 20 seconds, bail ..
1372 1394 */
1373 1395 error = ETIMEDOUT;
1374 1396 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1375 1397 mach_cpucontext_free(cp, ctx, error);
1376 1398 return (error);
1377 1399 }
1378 1400
1379 1401 /*
1380 1402 * wait at least 10ms, then check again..
1381 1403 */
1382 1404 delay(USEC_TO_TICK_ROUNDUP(10000));
1383 1405 tempset = *((volatile cpuset_t *)&procset_slave);
1384 1406 }
1385 1407 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1386 1408
1387 1409 mach_cpucontext_free(cp, ctx, 0);
1388 1410
1389 1411 #ifndef __xpv
1390 1412 if (tsc_gethrtime_enable)
1391 1413 tsc_sync_master(cpuid);
1392 1414 #endif
1393 1415
1394 1416 if (dtrace_cpu_init != NULL) {
1395 1417 (*dtrace_cpu_init)(cpuid);
1396 1418 }
1397 1419
1398 1420 /*
1399 1421 * During CPU DR operations, the cpu_lock is held by current
1400 1422 * (the control) thread. We can't release the cpu_lock here
1401 1423 * because that will break the CPU DR logic.
1402 1424 * On the other hand, CPUPM and processor group initialization
1403 1425 * routines need to access the cpu_lock. So we invoke those
1404 1426 * routines here on behalf of mp_startup_common().
1405 1427 *
1406 1428 * CPUPM and processor group initialization routines depend
1407 1429 * on the cpuid probing results. Wait for mp_startup_common()
1408 1430 * to signal that cpuid probing is done.
1409 1431 */
1410 1432 mp_startup_wait(&procset_slave, cpuid);
1411 1433 #ifndef __xpv
1412 1434 cpupm_init(cp);
1413 1435 #endif
1414 1436 (void) pg_cpu_init(cp, B_FALSE);
1415 1437 cpu_set_state(cp);
1416 1438 mp_startup_signal(&procset_master, cpuid);
1417 1439
1418 1440 return (0);
1419 1441 }
1420 1442
1421 1443 /*
1422 1444 * Start a single cpu, assuming that the kernel context is available
1423 1445 * to successfully start another cpu.
1424 1446 *
1425 1447 * (For example, real mode code is mapped into the right place
1426 1448 * in memory and is ready to be run.)
1427 1449 */
1428 1450 int
1429 1451 start_cpu(processorid_t who)
1430 1452 {
1431 1453 cpu_t *cp;
1432 1454 int error = 0;
1433 1455 cpuset_t tempset;
1434 1456
1435 1457 ASSERT(who != 0);
1436 1458
1437 1459 /*
1438 1460 * Check if there's at least a Mbyte of kmem available
1439 1461 * before attempting to start the cpu.
1440 1462 */
1441 1463 if (kmem_avail() < 1024 * 1024) {
1442 1464 /*
1443 1465 * Kick off a reap in case that helps us with
1444 1466 * later attempts ..
1445 1467 */
1446 1468 kmem_reap();
1447 1469 return (ENOMEM);
1448 1470 }
1449 1471
1450 1472 /*
1451 1473 * First configure cpu.
1452 1474 */
1453 1475 cp = mp_cpu_configure_common(who, B_TRUE);
1454 1476 ASSERT(cp != NULL);
1455 1477
1456 1478 /*
1457 1479 * Then start cpu.
1458 1480 */
1459 1481 error = mp_start_cpu_common(cp, B_TRUE);
1460 1482 if (error != 0) {
1461 1483 mp_cpu_unconfigure_common(cp, error);
1462 1484 return (error);
1463 1485 }
1464 1486
1465 1487 mutex_exit(&cpu_lock);
1466 1488 tempset = cpu_ready_set;
1467 1489 while (!CPU_IN_SET(tempset, who)) {
1468 1490 drv_usecwait(1);
1469 1491 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1470 1492 }
1471 1493 mutex_enter(&cpu_lock);
1472 1494
1473 1495 return (0);
1474 1496 }
1475 1497
1476 1498 void
1477 1499 start_other_cpus(int cprboot)
1478 1500 {
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1479 1501 _NOTE(ARGUNUSED(cprboot));
1480 1502
1481 1503 uint_t who;
1482 1504 uint_t bootcpuid = 0;
1483 1505
1484 1506 /*
1485 1507 * Initialize our own cpu_info.
1486 1508 */
1487 1509 init_cpu_info(CPU);
1488 1510
1511 +#if !defined(__xpv)
1512 + init_cpu_id_gdt(CPU);
1513 +#endif
1514 +
1489 1515 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1490 1516 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1491 1517
1492 1518 /*
1493 1519 * Initialize our syscall handlers
1494 1520 */
1495 1521 init_cpu_syscall(CPU);
1496 1522
1497 1523 /*
1498 1524 * Take the boot cpu out of the mp_cpus set because we know
1499 1525 * it's already running. Add it to the cpu_ready_set for
1500 1526 * precisely the same reason.
1501 1527 */
1502 1528 CPUSET_DEL(mp_cpus, bootcpuid);
1503 1529 CPUSET_ADD(cpu_ready_set, bootcpuid);
1504 1530
1505 1531 /*
1506 1532 * skip the rest of this if
1507 1533 * . only 1 cpu dectected and system isn't hotplug-capable
1508 1534 * . not using MP
1509 1535 */
1510 1536 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1511 1537 use_mp == 0) {
1512 1538 if (use_mp == 0)
1513 1539 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1514 1540 goto done;
1515 1541 }
1516 1542
1517 1543 /*
1518 1544 * perform such initialization as is needed
1519 1545 * to be able to take CPUs on- and off-line.
1520 1546 */
1521 1547 cpu_pause_init();
1522 1548
1523 1549 xc_init_cpu(CPU); /* initialize processor crosscalls */
1524 1550
1525 1551 if (mach_cpucontext_init() != 0)
1526 1552 goto done;
1527 1553
1528 1554 flushes_require_xcalls = 1;
1529 1555
1530 1556 /*
1531 1557 * We lock our affinity to the master CPU to ensure that all slave CPUs
1532 1558 * do their TSC syncs with the same CPU.
1533 1559 */
1534 1560 affinity_set(CPU_CURRENT);
1535 1561
1536 1562 for (who = 0; who < NCPU; who++) {
1537 1563 if (!CPU_IN_SET(mp_cpus, who))
1538 1564 continue;
1539 1565 ASSERT(who != bootcpuid);
1540 1566
1541 1567 mutex_enter(&cpu_lock);
1542 1568 if (start_cpu(who) != 0)
1543 1569 CPUSET_DEL(mp_cpus, who);
1544 1570 cpu_state_change_notify(who, CPU_SETUP);
1545 1571 mutex_exit(&cpu_lock);
1546 1572 }
1547 1573
1548 1574 /* Free the space allocated to hold the microcode file */
1549 1575 ucode_cleanup();
1550 1576
1551 1577 affinity_clear();
1552 1578
1553 1579 mach_cpucontext_fini();
1554 1580
1555 1581 done:
1556 1582 if (get_hwenv() == HW_NATIVE)
1557 1583 workaround_errata_end();
1558 1584 cmi_post_mpstartup();
1559 1585
1560 1586 if (use_mp && ncpus != boot_max_ncpus) {
1561 1587 cmn_err(CE_NOTE,
1562 1588 "System detected %d cpus, but "
1563 1589 "only %d cpu(s) were enabled during boot.",
1564 1590 boot_max_ncpus, ncpus);
1565 1591 cmn_err(CE_NOTE,
1566 1592 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1567 1593 "See eeprom(1M).");
1568 1594 }
1569 1595 }
1570 1596
1571 1597 int
1572 1598 mp_cpu_configure(int cpuid)
1573 1599 {
1574 1600 cpu_t *cp;
1575 1601
1576 1602 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1577 1603 return (ENOTSUP);
1578 1604 }
1579 1605
1580 1606 cp = cpu_get(cpuid);
1581 1607 if (cp != NULL) {
1582 1608 return (EALREADY);
1583 1609 }
1584 1610
1585 1611 /*
1586 1612 * Check if there's at least a Mbyte of kmem available
1587 1613 * before attempting to start the cpu.
1588 1614 */
1589 1615 if (kmem_avail() < 1024 * 1024) {
1590 1616 /*
1591 1617 * Kick off a reap in case that helps us with
1592 1618 * later attempts ..
1593 1619 */
1594 1620 kmem_reap();
1595 1621 return (ENOMEM);
1596 1622 }
1597 1623
1598 1624 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1599 1625 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1600 1626
1601 1627 return (cp != NULL ? 0 : EAGAIN);
1602 1628 }
1603 1629
1604 1630 int
1605 1631 mp_cpu_unconfigure(int cpuid)
1606 1632 {
1607 1633 cpu_t *cp;
1608 1634
1609 1635 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1610 1636 return (ENOTSUP);
1611 1637 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1612 1638 return (EINVAL);
1613 1639 }
1614 1640
1615 1641 cp = cpu_get(cpuid);
1616 1642 if (cp == NULL) {
1617 1643 return (ENODEV);
1618 1644 }
1619 1645 mp_cpu_unconfigure_common(cp, 0);
1620 1646
1621 1647 return (0);
1622 1648 }
1623 1649
1624 1650 /*
1625 1651 * Startup function for 'other' CPUs (besides boot cpu).
1626 1652 * Called from real_mode_start.
1627 1653 *
1628 1654 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1629 1655 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1630 1656 * hat_unload which requires CPU_READY to be set.
1631 1657 */
1632 1658 static void
1633 1659 mp_startup_common(boolean_t boot)
1634 1660 {
1635 1661 cpu_t *cp = CPU;
1636 1662 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1637 1663 extern void cpu_event_init_cpu(cpu_t *);
1638 1664
1639 1665 /*
1640 1666 * We need to get TSC on this proc synced (i.e., any delta
1641 1667 * from cpu0 accounted for) as soon as we can, because many
1642 1668 * many things use gethrtime/pc_gethrestime, including
1643 1669 * interrupts, cmn_err, etc. Before we can do that, we want to
1644 1670 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1645 1671 * right away.
1646 1672 */
1647 1673 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1648 1674 cpuid_pass1(cp, new_x86_featureset);
1649 1675
1650 1676 if (boot && get_hwenv() == HW_NATIVE &&
1651 1677 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1652 1678 cpuid_getfamily(CPU) == 6 &&
1653 1679 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1654 1680 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1655 1681 (void) wrmsr(REG_TSC, 0UL);
1656 1682 }
1657 1683
1658 1684 /* Let the control CPU continue into tsc_sync_master() */
1659 1685 mp_startup_signal(&procset_slave, cp->cpu_id);
1660 1686
1661 1687 #ifndef __xpv
1662 1688 if (tsc_gethrtime_enable)
1663 1689 tsc_sync_slave();
1664 1690 #endif
1665 1691
1666 1692 /*
1667 1693 * Once this was done from assembly, but it's safer here; if
1668 1694 * it blocks, we need to be able to swtch() to and from, and
1669 1695 * since we get here by calling t_pc, we need to do that call
1670 1696 * before swtch() overwrites it.
1671 1697 */
1672 1698 (void) (*ap_mlsetup)();
1673 1699
1674 1700 #ifndef __xpv
1675 1701 /*
1676 1702 * Program this cpu's PAT
1677 1703 */
1678 1704 pat_sync();
1679 1705 #endif
1680 1706
1681 1707 /*
1682 1708 * Set up TSC_AUX to contain the cpuid for this processor
1683 1709 * for the rdtscp instruction.
1684 1710 */
1685 1711 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1686 1712 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1687 1713
1688 1714 /*
1689 1715 * Initialize this CPU's syscall handlers
1690 1716 */
1691 1717 init_cpu_syscall(cp);
1692 1718
1693 1719 /*
1694 1720 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1695 1721 * highest level at which a routine is permitted to block on
1696 1722 * an adaptive mutex (allows for cpu poke interrupt in case
1697 1723 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1698 1724 * device interrupts that may end up in the hat layer issuing cross
1699 1725 * calls before CPU_READY is set.
1700 1726 */
1701 1727 splx(ipltospl(LOCK_LEVEL));
1702 1728 sti();
1703 1729
1704 1730 /*
1705 1731 * Do a sanity check to make sure this new CPU is a sane thing
1706 1732 * to add to the collection of processors running this system.
1707 1733 *
1708 1734 * XXX Clearly this needs to get more sophisticated, if x86
1709 1735 * systems start to get built out of heterogenous CPUs; as is
1710 1736 * likely to happen once the number of processors in a configuration
1711 1737 * gets large enough.
1712 1738 */
1713 1739 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1714 1740 B_FALSE) {
1715 1741 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1716 1742 print_x86_featureset(new_x86_featureset);
1717 1743 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1718 1744 }
1719 1745
1720 1746 /*
1721 1747 * We do not support cpus with mixed monitor/mwait support if the
1722 1748 * boot cpu supports monitor/mwait.
1723 1749 */
1724 1750 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1725 1751 is_x86_feature(new_x86_featureset, X86FSET_MWAIT))
1726 1752 panic("unsupported mixed cpu monitor/mwait support detected");
1727 1753
1728 1754 /*
1729 1755 * We could be more sophisticated here, and just mark the CPU
1730 1756 * as "faulted" but at this point we'll opt for the easier
1731 1757 * answer of dying horribly. Provided the boot cpu is ok,
1732 1758 * the system can be recovered by booting with use_mp set to zero.
1733 1759 */
1734 1760 if (workaround_errata(cp) != 0)
1735 1761 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1736 1762
1737 1763 /*
1738 1764 * We can touch cpu_flags here without acquiring the cpu_lock here
1739 1765 * because the cpu_lock is held by the control CPU which is running
1740 1766 * mp_start_cpu_common().
1741 1767 * Need to clear CPU_QUIESCED flag before calling any function which
1742 1768 * may cause thread context switching, such as kmem_alloc() etc.
1743 1769 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1744 1770 * it's set. So the startup thread may have no chance to switch back
1745 1771 * again if it's switched away with CPU_QUIESCED set.
1746 1772 */
1747 1773 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1748 1774
1749 1775 /*
1750 1776 * Setup this processor for XSAVE.
1751 1777 */
1752 1778 if (fp_save_mech == FP_XSAVE) {
1753 1779 xsave_setup_msr(cp);
1754 1780 }
1755 1781
1756 1782 cpuid_pass2(cp);
1757 1783 cpuid_pass3(cp);
1758 1784 cpuid_pass4(cp, NULL);
1759 1785
1760 1786 /*
1761 1787 * Correct cpu_idstr and cpu_brandstr on target CPU after
1762 1788 * cpuid_pass1() is done.
1763 1789 */
1764 1790 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1765 1791 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1766 1792
1767 1793 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1768 1794
1769 1795 post_startup_cpu_fixups();
1770 1796
1771 1797 cpu_event_init_cpu(cp);
1772 1798
1773 1799 /*
1774 1800 * Enable preemption here so that contention for any locks acquired
1775 1801 * later in mp_startup_common may be preempted if the thread owning
1776 1802 * those locks is continuously executing on other CPUs (for example,
1777 1803 * this CPU must be preemptible to allow other CPUs to pause it during
1778 1804 * their startup phases). It's safe to enable preemption here because
1779 1805 * the CPU state is pretty-much fully constructed.
1780 1806 */
1781 1807 curthread->t_preempt = 0;
1782 1808
1783 1809 /* The base spl should still be at LOCK LEVEL here */
1784 1810 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1785 1811 set_base_spl(); /* Restore the spl to its proper value */
1786 1812
1787 1813 pghw_physid_create(cp);
1788 1814 /*
1789 1815 * Delegate initialization tasks, which need to access the cpu_lock,
1790 1816 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1791 1817 * during CPU DR operations.
1792 1818 */
1793 1819 mp_startup_signal(&procset_slave, cp->cpu_id);
1794 1820 mp_startup_wait(&procset_master, cp->cpu_id);
1795 1821 pg_cmt_cpu_startup(cp);
1796 1822
1797 1823 if (boot) {
1798 1824 mutex_enter(&cpu_lock);
1799 1825 cp->cpu_flags &= ~CPU_OFFLINE;
1800 1826 cpu_enable_intr(cp);
1801 1827 cpu_add_active(cp);
1802 1828 mutex_exit(&cpu_lock);
1803 1829 }
1804 1830
1805 1831 /* Enable interrupts */
1806 1832 (void) spl0();
1807 1833
1808 1834 /*
1809 1835 * Fill out cpu_ucode_info. Update microcode if necessary.
1810 1836 */
1811 1837 ucode_check(cp);
1812 1838
1813 1839 #ifndef __xpv
1814 1840 {
1815 1841 /*
1816 1842 * Set up the CPU module for this CPU. This can't be done
1817 1843 * before this CPU is made CPU_READY, because we may (in
1818 1844 * heterogeneous systems) need to go load another CPU module.
1819 1845 * The act of attempting to load a module may trigger a
1820 1846 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1821 1847 */
1822 1848 cmi_hdl_t hdl;
1823 1849
1824 1850 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1825 1851 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1826 1852 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1827 1853 cmi_mca_init(hdl);
1828 1854 cp->cpu_m.mcpu_cmi_hdl = hdl;
1829 1855 }
1830 1856 }
1831 1857 #endif /* __xpv */
1832 1858
1833 1859 if (boothowto & RB_DEBUG)
1834 1860 kdi_cpu_init();
1835 1861
1836 1862 /*
1837 1863 * Setting the bit in cpu_ready_set must be the last operation in
1838 1864 * processor initialization; the boot CPU will continue to boot once
1839 1865 * it sees this bit set for all active CPUs.
1840 1866 */
1841 1867 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1842 1868
1843 1869 (void) mach_cpu_create_device_node(cp, NULL);
1844 1870
1845 1871 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1846 1872 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1847 1873 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1848 1874 cp->cpu_id);
1849 1875
1850 1876 /*
1851 1877 * Now we are done with the startup thread, so free it up.
1852 1878 */
1853 1879 thread_exit();
1854 1880 panic("mp_startup: cannot return");
1855 1881 /*NOTREACHED*/
1856 1882 }
1857 1883
1858 1884 /*
1859 1885 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1860 1886 */
1861 1887 static void
1862 1888 mp_startup_boot(void)
1863 1889 {
1864 1890 mp_startup_common(B_TRUE);
1865 1891 }
1866 1892
1867 1893 /*
1868 1894 * Startup function for hotplug CPUs at runtime.
1869 1895 */
1870 1896 void
1871 1897 mp_startup_hotplug(void)
1872 1898 {
1873 1899 mp_startup_common(B_FALSE);
1874 1900 }
1875 1901
1876 1902 /*
1877 1903 * Start CPU on user request.
1878 1904 */
1879 1905 /* ARGSUSED */
1880 1906 int
1881 1907 mp_cpu_start(struct cpu *cp)
1882 1908 {
1883 1909 ASSERT(MUTEX_HELD(&cpu_lock));
1884 1910 return (0);
1885 1911 }
1886 1912
1887 1913 /*
1888 1914 * Stop CPU on user request.
1889 1915 */
1890 1916 int
1891 1917 mp_cpu_stop(struct cpu *cp)
1892 1918 {
1893 1919 extern int cbe_psm_timer_mode;
1894 1920 ASSERT(MUTEX_HELD(&cpu_lock));
1895 1921
1896 1922 #ifdef __xpv
1897 1923 /*
1898 1924 * We can't offline vcpu0.
1899 1925 */
1900 1926 if (cp->cpu_id == 0)
1901 1927 return (EBUSY);
1902 1928 #endif
1903 1929
1904 1930 /*
1905 1931 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1906 1932 * can't stop it. (This is true only for machines with no TSC.)
1907 1933 */
1908 1934
1909 1935 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1910 1936 return (EBUSY);
1911 1937
1912 1938 return (0);
1913 1939 }
1914 1940
1915 1941 /*
1916 1942 * Take the specified CPU out of participation in interrupts.
1917 1943 */
1918 1944 int
1919 1945 cpu_disable_intr(struct cpu *cp)
1920 1946 {
1921 1947 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1922 1948 return (EBUSY);
1923 1949
1924 1950 cp->cpu_flags &= ~CPU_ENABLE;
1925 1951 return (0);
1926 1952 }
1927 1953
1928 1954 /*
1929 1955 * Allow the specified CPU to participate in interrupts.
1930 1956 */
1931 1957 void
1932 1958 cpu_enable_intr(struct cpu *cp)
1933 1959 {
1934 1960 ASSERT(MUTEX_HELD(&cpu_lock));
1935 1961 cp->cpu_flags |= CPU_ENABLE;
1936 1962 psm_enable_intr(cp->cpu_id);
1937 1963 }
1938 1964
1939 1965 void
1940 1966 mp_cpu_faulted_enter(struct cpu *cp)
1941 1967 {
1942 1968 #ifdef __xpv
1943 1969 _NOTE(ARGUNUSED(cp));
1944 1970 #else
1945 1971 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1946 1972
1947 1973 if (hdl != NULL) {
1948 1974 cmi_hdl_hold(hdl);
1949 1975 } else {
1950 1976 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1951 1977 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1952 1978 }
1953 1979 if (hdl != NULL) {
1954 1980 cmi_faulted_enter(hdl);
1955 1981 cmi_hdl_rele(hdl);
1956 1982 }
1957 1983 #endif
1958 1984 }
1959 1985
1960 1986 void
1961 1987 mp_cpu_faulted_exit(struct cpu *cp)
1962 1988 {
1963 1989 #ifdef __xpv
1964 1990 _NOTE(ARGUNUSED(cp));
1965 1991 #else
1966 1992 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1967 1993
1968 1994 if (hdl != NULL) {
1969 1995 cmi_hdl_hold(hdl);
1970 1996 } else {
1971 1997 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1972 1998 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1973 1999 }
1974 2000 if (hdl != NULL) {
1975 2001 cmi_faulted_exit(hdl);
1976 2002 cmi_hdl_rele(hdl);
1977 2003 }
1978 2004 #endif
1979 2005 }
1980 2006
1981 2007 /*
1982 2008 * The following two routines are used as context operators on threads belonging
1983 2009 * to processes with a private LDT (see sysi86). Due to the rarity of such
1984 2010 * processes, these routines are currently written for best code readability and
1985 2011 * organization rather than speed. We could avoid checking x86_featureset at
1986 2012 * every context switch by installing different context ops, depending on
1987 2013 * x86_featureset, at LDT creation time -- one for each combination of fast
1988 2014 * syscall features.
1989 2015 */
1990 2016
1991 2017 /*ARGSUSED*/
1992 2018 void
1993 2019 cpu_fast_syscall_disable(void *arg)
1994 2020 {
1995 2021 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1996 2022 is_x86_feature(x86_featureset, X86FSET_SEP))
1997 2023 cpu_sep_disable();
1998 2024 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1999 2025 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2000 2026 cpu_asysc_disable();
2001 2027 }
2002 2028
2003 2029 /*ARGSUSED*/
2004 2030 void
2005 2031 cpu_fast_syscall_enable(void *arg)
2006 2032 {
2007 2033 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2008 2034 is_x86_feature(x86_featureset, X86FSET_SEP))
2009 2035 cpu_sep_enable();
2010 2036 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2011 2037 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2012 2038 cpu_asysc_enable();
2013 2039 }
2014 2040
2015 2041 static void
2016 2042 cpu_sep_enable(void)
2017 2043 {
2018 2044 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2019 2045 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2020 2046
2021 2047 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2022 2048 }
2023 2049
2024 2050 static void
2025 2051 cpu_sep_disable(void)
2026 2052 {
2027 2053 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2028 2054 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2029 2055
2030 2056 /*
2031 2057 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2032 2058 * the sysenter or sysexit instruction to trigger a #gp fault.
2033 2059 */
2034 2060 wrmsr(MSR_INTC_SEP_CS, 0);
2035 2061 }
2036 2062
2037 2063 static void
2038 2064 cpu_asysc_enable(void)
2039 2065 {
2040 2066 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2041 2067 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2042 2068
2043 2069 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2044 2070 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2045 2071 }
2046 2072
2047 2073 static void
2048 2074 cpu_asysc_disable(void)
2049 2075 {
2050 2076 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2051 2077 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2052 2078
2053 2079 /*
2054 2080 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2055 2081 * executing syscall or sysret with this bit off will incur a #ud trap.
2056 2082 */
2057 2083 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2058 2084 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2059 2085 }
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