1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2015 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 */
33
34 #include <sys/types.h>
35 #include <sys/thread.h>
36 #include <sys/cpuvar.h>
37 #include <sys/cpu.h>
38 #include <sys/t_lock.h>
39 #include <sys/param.h>
40 #include <sys/proc.h>
41 #include <sys/disp.h>
42 #include <sys/class.h>
43 #include <sys/cmn_err.h>
44 #include <sys/debug.h>
45 #include <sys/note.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/x_call.h>
48 #include <sys/systm.h>
49 #include <sys/var.h>
50 #include <sys/vtrace.h>
51 #include <vm/hat.h>
52 #include <vm/as.h>
53 #include <vm/seg_kmem.h>
54 #include <vm/seg_kp.h>
55 #include <sys/segments.h>
56 #include <sys/kmem.h>
57 #include <sys/stack.h>
58 #include <sys/smp_impldefs.h>
59 #include <sys/x86_archext.h>
60 #include <sys/machsystm.h>
61 #include <sys/traptrace.h>
62 #include <sys/clock.h>
63 #include <sys/cpc_impl.h>
64 #include <sys/pg.h>
65 #include <sys/cmt.h>
66 #include <sys/dtrace.h>
67 #include <sys/archsystm.h>
68 #include <sys/fp.h>
69 #include <sys/reboot.h>
70 #include <sys/kdi_machimpl.h>
71 #include <vm/hat_i86.h>
72 #include <vm/vm_dep.h>
73 #include <sys/memnode.h>
74 #include <sys/pci_cfgspace.h>
75 #include <sys/mach_mmu.h>
76 #include <sys/sysmacros.h>
77 #if defined(__xpv)
78 #include <sys/hypervisor.h>
79 #endif
80 #include <sys/cpu_module.h>
81 #include <sys/ontrap.h>
82
83 struct cpu cpus[1]; /* CPU data */
84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
85 struct cpu *cpu_free_list; /* list for released CPUs */
86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
87
88 #define cpu_next_free cpu_prev
89
90 /*
91 * Useful for disabling MP bring-up on a MP capable system.
92 */
93 int use_mp = 1;
94
95 /*
96 * to be set by a PSM to indicate what cpus
97 * are sitting around on the system.
98 */
99 cpuset_t mp_cpus;
100
101 /*
102 * This variable is used by the hat layer to decide whether or not
103 * critical sections are needed to prevent race conditions. For sun4m,
104 * this variable is set once enough MP initialization has been done in
105 * order to allow cross calls.
106 */
107 int flushes_require_xcalls;
108
109 cpuset_t cpu_ready_set; /* initialized in startup() */
110
111 static void mp_startup_boot(void);
112 static void mp_startup_hotplug(void);
113
114 static void cpu_sep_enable(void);
115 static void cpu_sep_disable(void);
116 static void cpu_asysc_enable(void);
117 static void cpu_asysc_disable(void);
118
119 /*
120 * Init CPU info - get CPU type info for processor_info system call.
121 */
122 void
123 init_cpu_info(struct cpu *cp)
124 {
125 processor_info_t *pi = &cp->cpu_type_info;
126
127 /*
128 * Get clock-frequency property for the CPU.
129 */
130 pi->pi_clock = cpu_freq;
131
132 /*
133 * Current frequency in Hz.
134 */
135 cp->cpu_curr_clock = cpu_freq_hz;
136
137 /*
138 * Supported frequencies.
139 */
140 if (cp->cpu_supp_freqs == NULL) {
141 cpu_set_supp_freqs(cp, NULL);
142 }
143
144 (void) strcpy(pi->pi_processor_type, "i386");
145 if (fpu_exists)
146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
147
148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150
151 /*
152 * If called for the BSP, cp is equal to current CPU.
153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 * has been invoked on target CPU.
157 */
158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
160 }
161
162 /*
163 * Configure syscall support on this CPU.
164 */
165 /*ARGSUSED*/
166 void
167 init_cpu_syscall(struct cpu *cp)
168 {
169 kpreempt_disable();
170
171 #if defined(__amd64)
172 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
174 uint64_t flags;
175
176 #if !defined(__lint)
177 /*
178 * The syscall instruction imposes a certain ordering on
179 * segment selectors, so we double-check that ordering
180 * here.
181 */
182 ASSERT(KDS_SEL == KCS_SEL + 8);
183 ASSERT(UDS_SEL == U32CS_SEL + 8);
184 ASSERT(UCS_SEL == U32CS_SEL + 16);
185 #endif
186 /*
187 * Turn syscall/sysret extensions on.
188 */
189 cpu_asysc_enable();
190
191 /*
192 * Program the magic registers ..
193 */
194 wrmsr(MSR_AMD_STAR,
195 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
196 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
197 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
198
199 /*
200 * This list of flags is masked off the incoming
201 * %rfl when we enter the kernel.
202 */
203 flags = PS_IE | PS_T;
204 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
205 flags |= PS_ACHK;
206 wrmsr(MSR_AMD_SFMASK, flags);
207 }
208 #endif
209
210 /*
211 * On 32-bit kernels, we use sysenter/sysexit because it's too
212 * hard to use syscall/sysret, and it is more portable anyway.
213 *
214 * On 64-bit kernels on Nocona machines, the 32-bit syscall
215 * variant isn't available to 32-bit applications, but sysenter is.
216 */
217 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
218 is_x86_feature(x86_featureset, X86FSET_SEP)) {
219
220 #if !defined(__lint)
221 /*
222 * The sysenter instruction imposes a certain ordering on
223 * segment selectors, so we double-check that ordering
224 * here. See "sysenter" in Intel document 245471-012, "IA-32
225 * Intel Architecture Software Developer's Manual Volume 2:
226 * Instruction Set Reference"
227 */
228 ASSERT(KDS_SEL == KCS_SEL + 8);
229
230 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
231 ASSERT32(UDS_SEL == UCS_SEL + 8);
232
233 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
234 ASSERT64(UDS_SEL == U32CS_SEL + 8);
235 #endif
236
237 cpu_sep_enable();
238
239 /*
240 * resume() sets this value to the base of the threads stack
241 * via a context handler.
242 */
243 wrmsr(MSR_INTC_SEP_ESP, 0);
244 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
245 }
246
247 kpreempt_enable();
248 }
249
250 /*
251 * Multiprocessor initialization.
252 *
253 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
254 * startup and idle threads for the specified CPU.
255 * Parameter boot is true for boot time operations and is false for CPU
256 * DR operations.
257 */
258 static struct cpu *
259 mp_cpu_configure_common(int cpun, boolean_t boot)
260 {
261 struct cpu *cp;
262 kthread_id_t tp;
263 caddr_t sp;
264 proc_t *procp;
265 #if !defined(__xpv)
266 extern int idle_cpu_prefer_mwait;
267 extern void cpu_idle_mwait();
268 #endif
269 extern void idle();
270 extern void cpu_idle();
271
272 #ifdef TRAPTRACE
273 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
274 #endif
275
276 ASSERT(MUTEX_HELD(&cpu_lock));
277 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
278
279 if (cpu_free_list == NULL) {
280 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
281 } else {
282 cp = cpu_free_list;
283 cpu_free_list = cp->cpu_next_free;
284 }
285
286 cp->cpu_m.mcpu_istamp = cpun << 16;
287
288 /* Create per CPU specific threads in the process p0. */
289 procp = &p0;
290
291 /*
292 * Initialize the dispatcher first.
293 */
294 disp_cpu_init(cp);
295
296 cpu_vm_data_init(cp);
297
298 /*
299 * Allocate and initialize the startup thread for this CPU.
300 * Interrupt and process switch stacks get allocated later
301 * when the CPU starts running.
302 */
303 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
304 TS_STOPPED, maxclsyspri);
305
306 /*
307 * Set state to TS_ONPROC since this thread will start running
308 * as soon as the CPU comes online.
309 *
310 * All the other fields of the thread structure are setup by
311 * thread_create().
312 */
313 THREAD_ONPROC(tp, cp);
314 tp->t_preempt = 1;
315 tp->t_bound_cpu = cp;
316 tp->t_affinitycnt = 1;
317 tp->t_cpu = cp;
318 tp->t_disp_queue = cp->cpu_disp;
319
320 /*
321 * Setup thread to start in mp_startup_common.
322 */
323 sp = tp->t_stk;
324 tp->t_sp = (uintptr_t)(sp - MINFRAME);
325 #if defined(__amd64)
326 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
327 #endif
328 /*
329 * Setup thread start entry point for boot or hotplug.
330 */
331 if (boot) {
332 tp->t_pc = (uintptr_t)mp_startup_boot;
333 } else {
334 tp->t_pc = (uintptr_t)mp_startup_hotplug;
335 }
336
337 cp->cpu_id = cpun;
338 cp->cpu_self = cp;
339 cp->cpu_thread = tp;
340 cp->cpu_lwp = NULL;
341 cp->cpu_dispthread = tp;
342 cp->cpu_dispatch_pri = DISP_PRIO(tp);
343
344 /*
345 * cpu_base_spl must be set explicitly here to prevent any blocking
346 * operations in mp_startup_common from causing the spl of the cpu
347 * to drop to 0 (allowing device interrupts before we're ready) in
348 * resume().
349 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
350 * As an extra bit of security on DEBUG kernels, this is enforced with
351 * an assertion in mp_startup_common() -- before cpu_base_spl is set
352 * to its proper value.
353 */
354 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
355
356 /*
357 * Now, initialize per-CPU idle thread for this CPU.
358 */
359 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
360
361 cp->cpu_idle_thread = tp;
362
363 tp->t_preempt = 1;
364 tp->t_bound_cpu = cp;
365 tp->t_affinitycnt = 1;
366 tp->t_cpu = cp;
367 tp->t_disp_queue = cp->cpu_disp;
368
369 /*
370 * Bootstrap the CPU's PG data
371 */
372 pg_cpu_bootstrap(cp);
373
374 /*
375 * Perform CPC initialization on the new CPU.
376 */
377 kcpc_hw_init(cp);
378
379 /*
380 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
381 * for each CPU.
382 */
383 setup_vaddr_for_ppcopy(cp);
384
385 /*
386 * Allocate page for new GDT and initialize from current GDT.
387 */
388 #if !defined(__lint)
389 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
390 #endif
391 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
392 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
393
394 #if defined(__i386)
395 /*
396 * setup kernel %gs.
397 */
398 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
399 SEL_KPL, 0, 1);
400 #endif
401
402 /*
403 * If we have more than one node, each cpu gets a copy of IDT
404 * local to its node. If this is a Pentium box, we use cpu 0's
405 * IDT. cpu 0's IDT has been made read-only to workaround the
406 * cmpxchgl register bug
407 */
408 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
409 #if !defined(__lint)
410 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
411 #endif
412 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
413 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
414 } else {
415 cp->cpu_idt = CPU->cpu_idt;
416 }
417
418 /*
419 * alloc space for cpuid info
420 */
421 cpuid_alloc_space(cp);
422 #if !defined(__xpv)
423 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
424 idle_cpu_prefer_mwait) {
425 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
426 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
427 } else
428 #endif
429 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
430
431 init_cpu_info(cp);
432
433 /*
434 * alloc space for ucode_info
435 */
436 ucode_alloc_space(cp);
437 xc_init_cpu(cp);
438 hat_cpu_online(cp);
439
440 #ifdef TRAPTRACE
441 /*
442 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
443 */
444 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
445 ttc->ttc_next = ttc->ttc_first;
446 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
447 #endif
448
449 /*
450 * Record that we have another CPU.
451 */
452 /*
453 * Initialize the interrupt threads for this CPU
454 */
455 cpu_intr_alloc(cp, NINTR_THREADS);
456
457 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
458 cpu_set_state(cp);
459
460 /*
461 * Add CPU to list of available CPUs. It'll be on the active list
462 * after mp_startup_common().
463 */
464 cpu_add_unit(cp);
465
466 return (cp);
467 }
468
469 /*
470 * Undo what was done in mp_cpu_configure_common
471 */
472 static void
473 mp_cpu_unconfigure_common(struct cpu *cp, int error)
474 {
475 ASSERT(MUTEX_HELD(&cpu_lock));
476
477 /*
478 * Remove the CPU from the list of available CPUs.
479 */
480 cpu_del_unit(cp->cpu_id);
481
482 if (error == ETIMEDOUT) {
483 /*
484 * The cpu was started, but never *seemed* to run any
485 * code in the kernel; it's probably off spinning in its
486 * own private world, though with potential references to
487 * our kmem-allocated IDTs and GDTs (for example).
488 *
489 * Worse still, it may actually wake up some time later,
490 * so rather than guess what it might or might not do, we
491 * leave the fundamental data structures intact.
492 */
493 cp->cpu_flags = 0;
494 return;
495 }
496
497 /*
498 * At this point, the only threads bound to this CPU should
499 * special per-cpu threads: it's idle thread, it's pause threads,
500 * and it's interrupt threads. Clean these up.
501 */
502 cpu_destroy_bound_threads(cp);
503 cp->cpu_idle_thread = NULL;
504
505 /*
506 * Free the interrupt stack.
507 */
508 segkp_release(segkp,
509 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
510 cp->cpu_intr_stack = NULL;
511
512 #ifdef TRAPTRACE
513 /*
514 * Discard the trap trace buffer
515 */
516 {
517 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
518
519 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
520 ttc->ttc_first = NULL;
521 }
522 #endif
523
524 hat_cpu_offline(cp);
525
526 ucode_free_space(cp);
527
528 /* Free CPU ID string and brand string. */
529 if (cp->cpu_idstr) {
530 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
531 cp->cpu_idstr = NULL;
532 }
533 if (cp->cpu_brandstr) {
534 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
535 cp->cpu_brandstr = NULL;
536 }
537
538 #if !defined(__xpv)
539 if (cp->cpu_m.mcpu_mwait != NULL) {
540 cpuid_mwait_free(cp);
541 cp->cpu_m.mcpu_mwait = NULL;
542 }
543 #endif
544 cpuid_free_space(cp);
545
546 if (cp->cpu_idt != CPU->cpu_idt)
547 kmem_free(cp->cpu_idt, PAGESIZE);
548 cp->cpu_idt = NULL;
549
550 kmem_free(cp->cpu_gdt, PAGESIZE);
551 cp->cpu_gdt = NULL;
552
553 if (cp->cpu_supp_freqs != NULL) {
554 size_t len = strlen(cp->cpu_supp_freqs) + 1;
555 kmem_free(cp->cpu_supp_freqs, len);
556 cp->cpu_supp_freqs = NULL;
557 }
558
559 teardown_vaddr_for_ppcopy(cp);
560
561 kcpc_hw_fini(cp);
562
563 cp->cpu_dispthread = NULL;
564 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
565
566 cpu_vm_data_destroy(cp);
567
568 xc_fini_cpu(cp);
569 disp_cpu_fini(cp);
570
571 ASSERT(cp != CPU0);
572 bzero(cp, sizeof (*cp));
573 cp->cpu_next_free = cpu_free_list;
574 cpu_free_list = cp;
575 }
576
577 /*
578 * Apply workarounds for known errata, and warn about those that are absent.
579 *
580 * System vendors occasionally create configurations which contain different
581 * revisions of the CPUs that are almost but not exactly the same. At the
582 * time of writing, this meant that their clock rates were the same, their
583 * feature sets were the same, but the required workaround were -not-
584 * necessarily the same. So, this routine is invoked on -every- CPU soon
585 * after starting to make sure that the resulting system contains the most
586 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
587 * system.
588 *
589 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
590 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
591 * prior to acknowledging their readiness to the master, so this routine will
592 * never be executed by multiple CPUs in parallel, thus making updates to
593 * global data safe.
594 *
595 * These workarounds are based on Rev 3.57 of the Revision Guide for
596 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
597 */
598
599 #if defined(OPTERON_ERRATUM_88)
600 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
601 #endif
602
603 #if defined(OPTERON_ERRATUM_91)
604 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
605 #endif
606
607 #if defined(OPTERON_ERRATUM_93)
608 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
609 #endif
610
611 #if defined(OPTERON_ERRATUM_95)
612 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
613 #endif
614
615 #if defined(OPTERON_ERRATUM_100)
616 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
617 #endif
618
619 #if defined(OPTERON_ERRATUM_108)
620 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
621 #endif
622
623 #if defined(OPTERON_ERRATUM_109)
624 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
625 #endif
626
627 #if defined(OPTERON_ERRATUM_121)
628 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
629 #endif
630
631 #if defined(OPTERON_ERRATUM_122)
632 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
633 #endif
634
635 #if defined(OPTERON_ERRATUM_123)
636 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
637 #endif
638
639 #if defined(OPTERON_ERRATUM_131)
640 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
641 #endif
642
643 #if defined(OPTERON_WORKAROUND_6336786)
644 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
645 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
646 #endif
647
648 #if defined(OPTERON_WORKAROUND_6323525)
649 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
650 #endif
651
652 #if defined(OPTERON_ERRATUM_298)
653 int opteron_erratum_298;
654 #endif
655
656 #if defined(OPTERON_ERRATUM_721)
657 int opteron_erratum_721;
658 #endif
659
660 static void
661 workaround_warning(cpu_t *cp, uint_t erratum)
662 {
663 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
664 cp->cpu_id, erratum);
665 }
666
667 static void
668 workaround_applied(uint_t erratum)
669 {
670 if (erratum > 1000000)
671 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
672 erratum);
673 else
674 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
675 erratum);
676 }
677
678 static void
679 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
680 {
681 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
682 cp->cpu_id, rw, msr, error);
683 }
684
685 /*
686 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
687 * system.
688 */
689 static uint_t
690 opteron_get_nnodes(void)
691 {
692 static uint_t nnodes = 0;
693
694 if (nnodes == 0) {
695 #ifdef DEBUG
696 uint_t family;
697
698 /*
699 * This routine uses a PCI config space based mechanism
700 * for retrieving the number of nodes in the system.
701 * Device 24, function 0, offset 0x60 as used here is not
702 * AMD processor architectural, and may not work on processor
703 * families other than those listed below.
704 *
705 * Callers of this routine must ensure that we're running on
706 * a processor which supports this mechanism.
707 * The assertion below is meant to catch calls on unsupported
708 * processors.
709 */
710 family = cpuid_getfamily(CPU);
711 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
712 #endif /* DEBUG */
713
714 /*
715 * Obtain the number of nodes in the system from
716 * bits [6:4] of the Node ID register on node 0.
717 *
718 * The actual node count is NodeID[6:4] + 1
719 *
720 * The Node ID register is accessed via function 0,
721 * offset 0x60. Node 0 is device 24.
722 */
723 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
724 }
725 return (nnodes);
726 }
727
728 uint_t
729 do_erratum_298(struct cpu *cpu)
730 {
731 static int osvwrc = -3;
732 extern int osvw_opteron_erratum(cpu_t *, uint_t);
733
734 /*
735 * L2 Eviction May Occur During Processor Operation To Set
736 * Accessed or Dirty Bit.
737 */
738 if (osvwrc == -3) {
739 osvwrc = osvw_opteron_erratum(cpu, 298);
740 } else {
741 /* osvw return codes should be consistent for all cpus */
742 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
743 }
744
745 switch (osvwrc) {
746 case 0: /* erratum is not present: do nothing */
747 break;
748 case 1: /* erratum is present: BIOS workaround applied */
749 /*
750 * check if workaround is actually in place and issue warning
751 * if not.
752 */
753 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
754 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
755 #if defined(OPTERON_ERRATUM_298)
756 opteron_erratum_298++;
757 #else
758 workaround_warning(cpu, 298);
759 return (1);
760 #endif
761 }
762 break;
763 case -1: /* cannot determine via osvw: check cpuid */
764 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
765 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
766 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
767 #if defined(OPTERON_ERRATUM_298)
768 opteron_erratum_298++;
769 #else
770 workaround_warning(cpu, 298);
771 return (1);
772 #endif
773 }
774 break;
775 }
776 return (0);
777 }
778
779 uint_t
780 workaround_errata(struct cpu *cpu)
781 {
782 uint_t missing = 0;
783
784 ASSERT(cpu == CPU);
785
786 /*LINTED*/
787 if (cpuid_opteron_erratum(cpu, 88) > 0) {
788 /*
789 * SWAPGS May Fail To Read Correct GS Base
790 */
791 #if defined(OPTERON_ERRATUM_88)
792 /*
793 * The workaround is an mfence in the relevant assembler code
794 */
795 opteron_erratum_88++;
796 #else
797 workaround_warning(cpu, 88);
798 missing++;
799 #endif
800 }
801
802 if (cpuid_opteron_erratum(cpu, 91) > 0) {
803 /*
804 * Software Prefetches May Report A Page Fault
805 */
806 #if defined(OPTERON_ERRATUM_91)
807 /*
808 * fix is in trap.c
809 */
810 opteron_erratum_91++;
811 #else
812 workaround_warning(cpu, 91);
813 missing++;
814 #endif
815 }
816
817 if (cpuid_opteron_erratum(cpu, 93) > 0) {
818 /*
819 * RSM Auto-Halt Restart Returns to Incorrect RIP
820 */
821 #if defined(OPTERON_ERRATUM_93)
822 /*
823 * fix is in trap.c
824 */
825 opteron_erratum_93++;
826 #else
827 workaround_warning(cpu, 93);
828 missing++;
829 #endif
830 }
831
832 /*LINTED*/
833 if (cpuid_opteron_erratum(cpu, 95) > 0) {
834 /*
835 * RET Instruction May Return to Incorrect EIP
836 */
837 #if defined(OPTERON_ERRATUM_95)
838 #if defined(_LP64)
839 /*
840 * Workaround this by ensuring that 32-bit user code and
841 * 64-bit kernel code never occupy the same address
842 * range mod 4G.
843 */
844 if (_userlimit32 > 0xc0000000ul)
845 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
846
847 /*LINTED*/
848 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
849 opteron_erratum_95++;
850 #endif /* _LP64 */
851 #else
852 workaround_warning(cpu, 95);
853 missing++;
854 #endif
855 }
856
857 if (cpuid_opteron_erratum(cpu, 100) > 0) {
858 /*
859 * Compatibility Mode Branches Transfer to Illegal Address
860 */
861 #if defined(OPTERON_ERRATUM_100)
862 /*
863 * fix is in trap.c
864 */
865 opteron_erratum_100++;
866 #else
867 workaround_warning(cpu, 100);
868 missing++;
869 #endif
870 }
871
872 /*LINTED*/
873 if (cpuid_opteron_erratum(cpu, 108) > 0) {
874 /*
875 * CPUID Instruction May Return Incorrect Model Number In
876 * Some Processors
877 */
878 #if defined(OPTERON_ERRATUM_108)
879 /*
880 * (Our cpuid-handling code corrects the model number on
881 * those processors)
882 */
883 #else
884 workaround_warning(cpu, 108);
885 missing++;
886 #endif
887 }
888
889 /*LINTED*/
890 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
891 /*
892 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
893 */
894 #if defined(OPTERON_ERRATUM_109)
895 /*
896 * The "workaround" is to print a warning to upgrade the BIOS
897 */
898 uint64_t value;
899 const uint_t msr = MSR_AMD_PATCHLEVEL;
900 int err;
901
902 if ((err = checked_rdmsr(msr, &value)) != 0) {
903 msr_warning(cpu, "rd", msr, err);
904 workaround_warning(cpu, 109);
905 missing++;
906 }
907 if (value == 0)
908 opteron_erratum_109++;
909 #else
910 workaround_warning(cpu, 109);
911 missing++;
912 #endif
913 /*CONSTANTCONDITION*/
914 } while (0);
915
916 /*LINTED*/
917 if (cpuid_opteron_erratum(cpu, 121) > 0) {
918 /*
919 * Sequential Execution Across Non_Canonical Boundary Caused
920 * Processor Hang
921 */
922 #if defined(OPTERON_ERRATUM_121)
923 #if defined(_LP64)
924 /*
925 * Erratum 121 is only present in long (64 bit) mode.
926 * Workaround is to include the page immediately before the
927 * va hole to eliminate the possibility of system hangs due to
928 * sequential execution across the va hole boundary.
929 */
930 if (opteron_erratum_121)
931 opteron_erratum_121++;
932 else {
933 if (hole_start) {
934 hole_start -= PAGESIZE;
935 } else {
936 /*
937 * hole_start not yet initialized by
938 * mmu_init. Initialize hole_start
939 * with value to be subtracted.
940 */
941 hole_start = PAGESIZE;
942 }
943 opteron_erratum_121++;
944 }
945 #endif /* _LP64 */
946 #else
947 workaround_warning(cpu, 121);
948 missing++;
949 #endif
950 }
951
952 /*LINTED*/
953 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
954 /*
955 * TLB Flush Filter May Cause Coherency Problem in
956 * Multiprocessor Systems
957 */
958 #if defined(OPTERON_ERRATUM_122)
959 uint64_t value;
960 const uint_t msr = MSR_AMD_HWCR;
961 int error;
962
963 /*
964 * Erratum 122 is only present in MP configurations (multi-core
965 * or multi-processor).
966 */
967 #if defined(__xpv)
968 if (!DOMAIN_IS_INITDOMAIN(xen_info))
969 break;
970 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
971 break;
972 #else
973 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
974 cpuid_get_ncpu_per_chip(cpu) == 1)
975 break;
976 #endif
977 /* disable TLB Flush Filter */
978
979 if ((error = checked_rdmsr(msr, &value)) != 0) {
980 msr_warning(cpu, "rd", msr, error);
981 workaround_warning(cpu, 122);
982 missing++;
983 } else {
984 value |= (uint64_t)AMD_HWCR_FFDIS;
985 if ((error = checked_wrmsr(msr, value)) != 0) {
986 msr_warning(cpu, "wr", msr, error);
987 workaround_warning(cpu, 122);
988 missing++;
989 }
990 }
991 opteron_erratum_122++;
992 #else
993 workaround_warning(cpu, 122);
994 missing++;
995 #endif
996 /*CONSTANTCONDITION*/
997 } while (0);
998
999 /*LINTED*/
1000 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1001 /*
1002 * Bypassed Reads May Cause Data Corruption of System Hang in
1003 * Dual Core Processors
1004 */
1005 #if defined(OPTERON_ERRATUM_123)
1006 uint64_t value;
1007 const uint_t msr = MSR_AMD_PATCHLEVEL;
1008 int err;
1009
1010 /*
1011 * Erratum 123 applies only to multi-core cpus.
1012 */
1013 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1014 break;
1015 #if defined(__xpv)
1016 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1017 break;
1018 #endif
1019 /*
1020 * The "workaround" is to print a warning to upgrade the BIOS
1021 */
1022 if ((err = checked_rdmsr(msr, &value)) != 0) {
1023 msr_warning(cpu, "rd", msr, err);
1024 workaround_warning(cpu, 123);
1025 missing++;
1026 }
1027 if (value == 0)
1028 opteron_erratum_123++;
1029 #else
1030 workaround_warning(cpu, 123);
1031 missing++;
1032
1033 #endif
1034 /*CONSTANTCONDITION*/
1035 } while (0);
1036
1037 /*LINTED*/
1038 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1039 /*
1040 * Multiprocessor Systems with Four or More Cores May Deadlock
1041 * Waiting for a Probe Response
1042 */
1043 #if defined(OPTERON_ERRATUM_131)
1044 uint64_t nbcfg;
1045 const uint_t msr = MSR_AMD_NB_CFG;
1046 const uint64_t wabits =
1047 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1048 int error;
1049
1050 /*
1051 * Erratum 131 applies to any system with four or more cores.
1052 */
1053 if (opteron_erratum_131)
1054 break;
1055 #if defined(__xpv)
1056 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1057 break;
1058 if (xpv_nr_phys_cpus() < 4)
1059 break;
1060 #else
1061 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1062 break;
1063 #endif
1064 /*
1065 * Print a warning if neither of the workarounds for
1066 * erratum 131 is present.
1067 */
1068 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1069 msr_warning(cpu, "rd", msr, error);
1070 workaround_warning(cpu, 131);
1071 missing++;
1072 } else if ((nbcfg & wabits) == 0) {
1073 opteron_erratum_131++;
1074 } else {
1075 /* cannot have both workarounds set */
1076 ASSERT((nbcfg & wabits) != wabits);
1077 }
1078 #else
1079 workaround_warning(cpu, 131);
1080 missing++;
1081 #endif
1082 /*CONSTANTCONDITION*/
1083 } while (0);
1084
1085 /*
1086 * This isn't really an erratum, but for convenience the
1087 * detection/workaround code lives here and in cpuid_opteron_erratum.
1088 */
1089 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1090 #if defined(OPTERON_WORKAROUND_6336786)
1091 /*
1092 * Disable C1-Clock ramping on multi-core/multi-processor
1093 * K8 platforms to guard against TSC drift.
1094 */
1095 if (opteron_workaround_6336786) {
1096 opteron_workaround_6336786++;
1097 #if defined(__xpv)
1098 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1099 xpv_nr_phys_cpus() > 1) ||
1100 opteron_workaround_6336786_UP) {
1101 /*
1102 * XXPV Hmm. We can't walk the Northbridges on
1103 * the hypervisor; so just complain and drive
1104 * on. This probably needs to be fixed in
1105 * the hypervisor itself.
1106 */
1107 opteron_workaround_6336786++;
1108 workaround_warning(cpu, 6336786);
1109 #else /* __xpv */
1110 } else if ((opteron_get_nnodes() *
1111 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1112 opteron_workaround_6336786_UP) {
1113
1114 uint_t node, nnodes;
1115 uint8_t data;
1116
1117 nnodes = opteron_get_nnodes();
1118 for (node = 0; node < nnodes; node++) {
1119 /*
1120 * Clear PMM7[1:0] (function 3, offset 0x87)
1121 * Northbridge device is the node id + 24.
1122 */
1123 data = pci_getb_func(0, node + 24, 3, 0x87);
1124 data &= 0xFC;
1125 pci_putb_func(0, node + 24, 3, 0x87, data);
1126 }
1127 opteron_workaround_6336786++;
1128 #endif /* __xpv */
1129 }
1130 #else
1131 workaround_warning(cpu, 6336786);
1132 missing++;
1133 #endif
1134 }
1135
1136 /*LINTED*/
1137 /*
1138 * Mutex primitives don't work as expected.
1139 */
1140 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1141 #if defined(OPTERON_WORKAROUND_6323525)
1142 /*
1143 * This problem only occurs with 2 or more cores. If bit in
1144 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1145 * is to patch the semaphone routines with the lfence
1146 * instruction to provide necessary load memory barrier with
1147 * possible subsequent read-modify-write ops.
1148 *
1149 * It is too early in boot to call the patch routine so
1150 * set erratum variable to be done in startup_end().
1151 */
1152 if (opteron_workaround_6323525) {
1153 opteron_workaround_6323525++;
1154 #if defined(__xpv)
1155 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1156 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1157 /*
1158 * XXPV Use dom0_msr here when extended
1159 * operations are supported?
1160 */
1161 if (xpv_nr_phys_cpus() > 1)
1162 opteron_workaround_6323525++;
1163 } else {
1164 /*
1165 * We have no way to tell how many physical
1166 * cpus there are, or even if this processor
1167 * has the problem, so enable the workaround
1168 * unconditionally (at some performance cost).
1169 */
1170 opteron_workaround_6323525++;
1171 }
1172 #else /* __xpv */
1173 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1174 ((opteron_get_nnodes() *
1175 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1176 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1177 opteron_workaround_6323525++;
1178 #endif /* __xpv */
1179 }
1180 #else
1181 workaround_warning(cpu, 6323525);
1182 missing++;
1183 #endif
1184 }
1185
1186 missing += do_erratum_298(cpu);
1187
1188 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1189 #if defined(OPTERON_ERRATUM_721)
1190 on_trap_data_t otd;
1191
1192 if (!on_trap(&otd, OT_DATA_ACCESS))
1193 wrmsr(MSR_AMD_DE_CFG,
1194 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1195 no_trap();
1196
1197 opteron_erratum_721++;
1198 #else
1199 workaround_warning(cpu, 721);
1200 missing++;
1201 #endif
1202 }
1203
1204 #ifdef __xpv
1205 return (0);
1206 #else
1207 return (missing);
1208 #endif
1209 }
1210
1211 void
1212 workaround_errata_end()
1213 {
1214 #if defined(OPTERON_ERRATUM_88)
1215 if (opteron_erratum_88)
1216 workaround_applied(88);
1217 #endif
1218 #if defined(OPTERON_ERRATUM_91)
1219 if (opteron_erratum_91)
1220 workaround_applied(91);
1221 #endif
1222 #if defined(OPTERON_ERRATUM_93)
1223 if (opteron_erratum_93)
1224 workaround_applied(93);
1225 #endif
1226 #if defined(OPTERON_ERRATUM_95)
1227 if (opteron_erratum_95)
1228 workaround_applied(95);
1229 #endif
1230 #if defined(OPTERON_ERRATUM_100)
1231 if (opteron_erratum_100)
1232 workaround_applied(100);
1233 #endif
1234 #if defined(OPTERON_ERRATUM_108)
1235 if (opteron_erratum_108)
1236 workaround_applied(108);
1237 #endif
1238 #if defined(OPTERON_ERRATUM_109)
1239 if (opteron_erratum_109) {
1240 cmn_err(CE_WARN,
1241 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1242 " processor\nerratum 109 was not detected; updating your"
1243 " system's BIOS to a version\ncontaining this"
1244 " microcode patch is HIGHLY recommended or erroneous"
1245 " system\noperation may occur.\n");
1246 }
1247 #endif
1248 #if defined(OPTERON_ERRATUM_121)
1249 if (opteron_erratum_121)
1250 workaround_applied(121);
1251 #endif
1252 #if defined(OPTERON_ERRATUM_122)
1253 if (opteron_erratum_122)
1254 workaround_applied(122);
1255 #endif
1256 #if defined(OPTERON_ERRATUM_123)
1257 if (opteron_erratum_123) {
1258 cmn_err(CE_WARN,
1259 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1260 " processor\nerratum 123 was not detected; updating your"
1261 " system's BIOS to a version\ncontaining this"
1262 " microcode patch is HIGHLY recommended or erroneous"
1263 " system\noperation may occur.\n");
1264 }
1265 #endif
1266 #if defined(OPTERON_ERRATUM_131)
1267 if (opteron_erratum_131) {
1268 cmn_err(CE_WARN,
1269 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1270 " processor\nerratum 131 was not detected; updating your"
1271 " system's BIOS to a version\ncontaining this"
1272 " microcode patch is HIGHLY recommended or erroneous"
1273 " system\noperation may occur.\n");
1274 }
1275 #endif
1276 #if defined(OPTERON_WORKAROUND_6336786)
1277 if (opteron_workaround_6336786)
1278 workaround_applied(6336786);
1279 #endif
1280 #if defined(OPTERON_WORKAROUND_6323525)
1281 if (opteron_workaround_6323525)
1282 workaround_applied(6323525);
1283 #endif
1284 #if defined(OPTERON_ERRATUM_298)
1285 if (opteron_erratum_298) {
1286 cmn_err(CE_WARN,
1287 "BIOS microcode patch for AMD 64/Opteron(tm)"
1288 " processor\nerratum 298 was not detected; updating your"
1289 " system's BIOS to a version\ncontaining this"
1290 " microcode patch is HIGHLY recommended or erroneous"
1291 " system\noperation may occur.\n");
1292 }
1293 #endif
1294 #if defined(OPTERON_ERRATUM_721)
1295 if (opteron_erratum_721)
1296 workaround_applied(721);
1297 #endif
1298 }
1299
1300 /*
1301 * The procset_slave and procset_master are used to synchronize
1302 * between the control CPU and the target CPU when starting CPUs.
1303 */
1304 static cpuset_t procset_slave, procset_master;
1305
1306 static void
1307 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1308 {
1309 cpuset_t tempset;
1310
1311 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1312 tempset = *(volatile cpuset_t *)sp) {
1313 SMT_PAUSE();
1314 }
1315 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1316 }
1317
1318 static void
1319 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1320 {
1321 cpuset_t tempset;
1322
1323 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1324 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1325 tempset = *(volatile cpuset_t *)sp) {
1326 SMT_PAUSE();
1327 }
1328 }
1329
1330 int
1331 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1332 {
1333 _NOTE(ARGUNUSED(boot));
1334
1335 void *ctx;
1336 int delays;
1337 int error = 0;
1338 cpuset_t tempset;
1339 processorid_t cpuid;
1340 #ifndef __xpv
1341 extern void cpupm_init(cpu_t *);
1342 #endif
1343
1344 ASSERT(cp != NULL);
1345 cpuid = cp->cpu_id;
1346 ctx = mach_cpucontext_alloc(cp);
1347 if (ctx == NULL) {
1348 cmn_err(CE_WARN,
1349 "cpu%d: failed to allocate context", cp->cpu_id);
1350 return (EAGAIN);
1351 }
1352 error = mach_cpu_start(cp, ctx);
1353 if (error != 0) {
1354 cmn_err(CE_WARN,
1355 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1356 mach_cpucontext_free(cp, ctx, error);
1357 return (error);
1358 }
1359
1360 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1361 delays++) {
1362 if (delays == 500) {
1363 /*
1364 * After five seconds, things are probably looking
1365 * a bit bleak - explain the hang.
1366 */
1367 cmn_err(CE_NOTE, "cpu%d: started, "
1368 "but not running in the kernel yet", cpuid);
1369 } else if (delays > 2000) {
1370 /*
1371 * We waited at least 20 seconds, bail ..
1372 */
1373 error = ETIMEDOUT;
1374 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1375 mach_cpucontext_free(cp, ctx, error);
1376 return (error);
1377 }
1378
1379 /*
1380 * wait at least 10ms, then check again..
1381 */
1382 delay(USEC_TO_TICK_ROUNDUP(10000));
1383 tempset = *((volatile cpuset_t *)&procset_slave);
1384 }
1385 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1386
1387 mach_cpucontext_free(cp, ctx, 0);
1388
1389 #ifndef __xpv
1390 if (tsc_gethrtime_enable)
1391 tsc_sync_master(cpuid);
1392 #endif
1393
1394 if (dtrace_cpu_init != NULL) {
1395 (*dtrace_cpu_init)(cpuid);
1396 }
1397
1398 /*
1399 * During CPU DR operations, the cpu_lock is held by current
1400 * (the control) thread. We can't release the cpu_lock here
1401 * because that will break the CPU DR logic.
1402 * On the other hand, CPUPM and processor group initialization
1403 * routines need to access the cpu_lock. So we invoke those
1404 * routines here on behalf of mp_startup_common().
1405 *
1406 * CPUPM and processor group initialization routines depend
1407 * on the cpuid probing results. Wait for mp_startup_common()
1408 * to signal that cpuid probing is done.
1409 */
1410 mp_startup_wait(&procset_slave, cpuid);
1411 #ifndef __xpv
1412 cpupm_init(cp);
1413 #endif
1414 (void) pg_cpu_init(cp, B_FALSE);
1415 cpu_set_state(cp);
1416 mp_startup_signal(&procset_master, cpuid);
1417
1418 return (0);
1419 }
1420
1421 /*
1422 * Start a single cpu, assuming that the kernel context is available
1423 * to successfully start another cpu.
1424 *
1425 * (For example, real mode code is mapped into the right place
1426 * in memory and is ready to be run.)
1427 */
1428 int
1429 start_cpu(processorid_t who)
1430 {
1431 cpu_t *cp;
1432 int error = 0;
1433 cpuset_t tempset;
1434
1435 ASSERT(who != 0);
1436
1437 /*
1438 * Check if there's at least a Mbyte of kmem available
1439 * before attempting to start the cpu.
1440 */
1441 if (kmem_avail() < 1024 * 1024) {
1442 /*
1443 * Kick off a reap in case that helps us with
1444 * later attempts ..
1445 */
1446 kmem_reap();
1447 return (ENOMEM);
1448 }
1449
1450 /*
1451 * First configure cpu.
1452 */
1453 cp = mp_cpu_configure_common(who, B_TRUE);
1454 ASSERT(cp != NULL);
1455
1456 /*
1457 * Then start cpu.
1458 */
1459 error = mp_start_cpu_common(cp, B_TRUE);
1460 if (error != 0) {
1461 mp_cpu_unconfigure_common(cp, error);
1462 return (error);
1463 }
1464
1465 mutex_exit(&cpu_lock);
1466 tempset = cpu_ready_set;
1467 while (!CPU_IN_SET(tempset, who)) {
1468 drv_usecwait(1);
1469 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1470 }
1471 mutex_enter(&cpu_lock);
1472
1473 return (0);
1474 }
1475
1476 void
1477 start_other_cpus(int cprboot)
1478 {
1479 _NOTE(ARGUNUSED(cprboot));
1480
1481 uint_t who;
1482 uint_t bootcpuid = 0;
1483
1484 /*
1485 * Initialize our own cpu_info.
1486 */
1487 init_cpu_info(CPU);
1488
1489 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1490 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1491
1492 /*
1493 * Initialize our syscall handlers
1494 */
1495 init_cpu_syscall(CPU);
1496
1497 /*
1498 * Take the boot cpu out of the mp_cpus set because we know
1499 * it's already running. Add it to the cpu_ready_set for
1500 * precisely the same reason.
1501 */
1502 CPUSET_DEL(mp_cpus, bootcpuid);
1503 CPUSET_ADD(cpu_ready_set, bootcpuid);
1504
1505 /*
1506 * skip the rest of this if
1507 * . only 1 cpu dectected and system isn't hotplug-capable
1508 * . not using MP
1509 */
1510 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1511 use_mp == 0) {
1512 if (use_mp == 0)
1513 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1514 goto done;
1515 }
1516
1517 /*
1518 * perform such initialization as is needed
1519 * to be able to take CPUs on- and off-line.
1520 */
1521 cpu_pause_init();
1522
1523 xc_init_cpu(CPU); /* initialize processor crosscalls */
1524
1525 if (mach_cpucontext_init() != 0)
1526 goto done;
1527
1528 flushes_require_xcalls = 1;
1529
1530 /*
1531 * We lock our affinity to the master CPU to ensure that all slave CPUs
1532 * do their TSC syncs with the same CPU.
1533 */
1534 affinity_set(CPU_CURRENT);
1535
1536 for (who = 0; who < NCPU; who++) {
1537 if (!CPU_IN_SET(mp_cpus, who))
1538 continue;
1539 ASSERT(who != bootcpuid);
1540
1541 mutex_enter(&cpu_lock);
1542 if (start_cpu(who) != 0)
1543 CPUSET_DEL(mp_cpus, who);
1544 cpu_state_change_notify(who, CPU_SETUP);
1545 mutex_exit(&cpu_lock);
1546 }
1547
1548 /* Free the space allocated to hold the microcode file */
1549 ucode_cleanup();
1550
1551 affinity_clear();
1552
1553 mach_cpucontext_fini();
1554
1555 done:
1556 if (get_hwenv() == HW_NATIVE)
1557 workaround_errata_end();
1558 cmi_post_mpstartup();
1559
1560 if (use_mp && ncpus != boot_max_ncpus) {
1561 cmn_err(CE_NOTE,
1562 "System detected %d cpus, but "
1563 "only %d cpu(s) were enabled during boot.",
1564 boot_max_ncpus, ncpus);
1565 cmn_err(CE_NOTE,
1566 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1567 "See eeprom(1M).");
1568 }
1569 }
1570
1571 int
1572 mp_cpu_configure(int cpuid)
1573 {
1574 cpu_t *cp;
1575
1576 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1577 return (ENOTSUP);
1578 }
1579
1580 cp = cpu_get(cpuid);
1581 if (cp != NULL) {
1582 return (EALREADY);
1583 }
1584
1585 /*
1586 * Check if there's at least a Mbyte of kmem available
1587 * before attempting to start the cpu.
1588 */
1589 if (kmem_avail() < 1024 * 1024) {
1590 /*
1591 * Kick off a reap in case that helps us with
1592 * later attempts ..
1593 */
1594 kmem_reap();
1595 return (ENOMEM);
1596 }
1597
1598 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1599 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1600
1601 return (cp != NULL ? 0 : EAGAIN);
1602 }
1603
1604 int
1605 mp_cpu_unconfigure(int cpuid)
1606 {
1607 cpu_t *cp;
1608
1609 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1610 return (ENOTSUP);
1611 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1612 return (EINVAL);
1613 }
1614
1615 cp = cpu_get(cpuid);
1616 if (cp == NULL) {
1617 return (ENODEV);
1618 }
1619 mp_cpu_unconfigure_common(cp, 0);
1620
1621 return (0);
1622 }
1623
1624 /*
1625 * Startup function for 'other' CPUs (besides boot cpu).
1626 * Called from real_mode_start.
1627 *
1628 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1629 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1630 * hat_unload which requires CPU_READY to be set.
1631 */
1632 static void
1633 mp_startup_common(boolean_t boot)
1634 {
1635 cpu_t *cp = CPU;
1636 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1637 extern void cpu_event_init_cpu(cpu_t *);
1638
1639 /*
1640 * We need to get TSC on this proc synced (i.e., any delta
1641 * from cpu0 accounted for) as soon as we can, because many
1642 * many things use gethrtime/pc_gethrestime, including
1643 * interrupts, cmn_err, etc. Before we can do that, we want to
1644 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1645 * right away.
1646 */
1647 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1648 cpuid_pass1(cp, new_x86_featureset);
1649
1650 if (boot && get_hwenv() == HW_NATIVE &&
1651 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1652 cpuid_getfamily(CPU) == 6 &&
1653 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1654 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1655 (void) wrmsr(REG_TSC, 0UL);
1656 }
1657
1658 /* Let the control CPU continue into tsc_sync_master() */
1659 mp_startup_signal(&procset_slave, cp->cpu_id);
1660
1661 #ifndef __xpv
1662 if (tsc_gethrtime_enable)
1663 tsc_sync_slave();
1664 #endif
1665
1666 /*
1667 * Once this was done from assembly, but it's safer here; if
1668 * it blocks, we need to be able to swtch() to and from, and
1669 * since we get here by calling t_pc, we need to do that call
1670 * before swtch() overwrites it.
1671 */
1672 (void) (*ap_mlsetup)();
1673
1674 #ifndef __xpv
1675 /*
1676 * Program this cpu's PAT
1677 */
1678 pat_sync();
1679 #endif
1680
1681 /*
1682 * Set up TSC_AUX to contain the cpuid for this processor
1683 * for the rdtscp instruction.
1684 */
1685 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1686 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1687
1688 /*
1689 * Initialize this CPU's syscall handlers
1690 */
1691 init_cpu_syscall(cp);
1692
1693 /*
1694 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1695 * highest level at which a routine is permitted to block on
1696 * an adaptive mutex (allows for cpu poke interrupt in case
1697 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1698 * device interrupts that may end up in the hat layer issuing cross
1699 * calls before CPU_READY is set.
1700 */
1701 splx(ipltospl(LOCK_LEVEL));
1702 sti();
1703
1704 /*
1705 * Do a sanity check to make sure this new CPU is a sane thing
1706 * to add to the collection of processors running this system.
1707 *
1708 * XXX Clearly this needs to get more sophisticated, if x86
1709 * systems start to get built out of heterogenous CPUs; as is
1710 * likely to happen once the number of processors in a configuration
1711 * gets large enough.
1712 */
1713 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1714 B_FALSE) {
1715 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1716 print_x86_featureset(new_x86_featureset);
1717 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1718 }
1719
1720 /*
1721 * We do not support cpus with mixed monitor/mwait support if the
1722 * boot cpu supports monitor/mwait.
1723 */
1724 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1725 is_x86_feature(new_x86_featureset, X86FSET_MWAIT))
1726 panic("unsupported mixed cpu monitor/mwait support detected");
1727
1728 /*
1729 * We could be more sophisticated here, and just mark the CPU
1730 * as "faulted" but at this point we'll opt for the easier
1731 * answer of dying horribly. Provided the boot cpu is ok,
1732 * the system can be recovered by booting with use_mp set to zero.
1733 */
1734 if (workaround_errata(cp) != 0)
1735 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1736
1737 /*
1738 * We can touch cpu_flags here without acquiring the cpu_lock here
1739 * because the cpu_lock is held by the control CPU which is running
1740 * mp_start_cpu_common().
1741 * Need to clear CPU_QUIESCED flag before calling any function which
1742 * may cause thread context switching, such as kmem_alloc() etc.
1743 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1744 * it's set. So the startup thread may have no chance to switch back
1745 * again if it's switched away with CPU_QUIESCED set.
1746 */
1747 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1748
1749 /*
1750 * Setup this processor for XSAVE.
1751 */
1752 if (fp_save_mech == FP_XSAVE) {
1753 xsave_setup_msr(cp);
1754 }
1755
1756 cpuid_pass2(cp);
1757 cpuid_pass3(cp);
1758 cpuid_pass4(cp, NULL);
1759
1760 /*
1761 * Correct cpu_idstr and cpu_brandstr on target CPU after
1762 * cpuid_pass1() is done.
1763 */
1764 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1765 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1766
1767 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1768
1769 post_startup_cpu_fixups();
1770
1771 cpu_event_init_cpu(cp);
1772
1773 /*
1774 * Enable preemption here so that contention for any locks acquired
1775 * later in mp_startup_common may be preempted if the thread owning
1776 * those locks is continuously executing on other CPUs (for example,
1777 * this CPU must be preemptible to allow other CPUs to pause it during
1778 * their startup phases). It's safe to enable preemption here because
1779 * the CPU state is pretty-much fully constructed.
1780 */
1781 curthread->t_preempt = 0;
1782
1783 /* The base spl should still be at LOCK LEVEL here */
1784 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1785 set_base_spl(); /* Restore the spl to its proper value */
1786
1787 pghw_physid_create(cp);
1788 /*
1789 * Delegate initialization tasks, which need to access the cpu_lock,
1790 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1791 * during CPU DR operations.
1792 */
1793 mp_startup_signal(&procset_slave, cp->cpu_id);
1794 mp_startup_wait(&procset_master, cp->cpu_id);
1795 pg_cmt_cpu_startup(cp);
1796
1797 if (boot) {
1798 mutex_enter(&cpu_lock);
1799 cp->cpu_flags &= ~CPU_OFFLINE;
1800 cpu_enable_intr(cp);
1801 cpu_add_active(cp);
1802 mutex_exit(&cpu_lock);
1803 }
1804
1805 /* Enable interrupts */
1806 (void) spl0();
1807
1808 /*
1809 * Fill out cpu_ucode_info. Update microcode if necessary.
1810 */
1811 ucode_check(cp);
1812
1813 #ifndef __xpv
1814 {
1815 /*
1816 * Set up the CPU module for this CPU. This can't be done
1817 * before this CPU is made CPU_READY, because we may (in
1818 * heterogeneous systems) need to go load another CPU module.
1819 * The act of attempting to load a module may trigger a
1820 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1821 */
1822 cmi_hdl_t hdl;
1823
1824 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1825 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1826 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1827 cmi_mca_init(hdl);
1828 cp->cpu_m.mcpu_cmi_hdl = hdl;
1829 }
1830 }
1831 #endif /* __xpv */
1832
1833 if (boothowto & RB_DEBUG)
1834 kdi_cpu_init();
1835
1836 /*
1837 * Setting the bit in cpu_ready_set must be the last operation in
1838 * processor initialization; the boot CPU will continue to boot once
1839 * it sees this bit set for all active CPUs.
1840 */
1841 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1842
1843 (void) mach_cpu_create_device_node(cp, NULL);
1844
1845 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1846 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1847 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1848 cp->cpu_id);
1849
1850 /*
1851 * Now we are done with the startup thread, so free it up.
1852 */
1853 thread_exit();
1854 panic("mp_startup: cannot return");
1855 /*NOTREACHED*/
1856 }
1857
1858 /*
1859 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1860 */
1861 static void
1862 mp_startup_boot(void)
1863 {
1864 mp_startup_common(B_TRUE);
1865 }
1866
1867 /*
1868 * Startup function for hotplug CPUs at runtime.
1869 */
1870 void
1871 mp_startup_hotplug(void)
1872 {
1873 mp_startup_common(B_FALSE);
1874 }
1875
1876 /*
1877 * Start CPU on user request.
1878 */
1879 /* ARGSUSED */
1880 int
1881 mp_cpu_start(struct cpu *cp)
1882 {
1883 ASSERT(MUTEX_HELD(&cpu_lock));
1884 return (0);
1885 }
1886
1887 /*
1888 * Stop CPU on user request.
1889 */
1890 int
1891 mp_cpu_stop(struct cpu *cp)
1892 {
1893 extern int cbe_psm_timer_mode;
1894 ASSERT(MUTEX_HELD(&cpu_lock));
1895
1896 #ifdef __xpv
1897 /*
1898 * We can't offline vcpu0.
1899 */
1900 if (cp->cpu_id == 0)
1901 return (EBUSY);
1902 #endif
1903
1904 /*
1905 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1906 * can't stop it. (This is true only for machines with no TSC.)
1907 */
1908
1909 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1910 return (EBUSY);
1911
1912 return (0);
1913 }
1914
1915 /*
1916 * Take the specified CPU out of participation in interrupts.
1917 */
1918 int
1919 cpu_disable_intr(struct cpu *cp)
1920 {
1921 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1922 return (EBUSY);
1923
1924 cp->cpu_flags &= ~CPU_ENABLE;
1925 return (0);
1926 }
1927
1928 /*
1929 * Allow the specified CPU to participate in interrupts.
1930 */
1931 void
1932 cpu_enable_intr(struct cpu *cp)
1933 {
1934 ASSERT(MUTEX_HELD(&cpu_lock));
1935 cp->cpu_flags |= CPU_ENABLE;
1936 psm_enable_intr(cp->cpu_id);
1937 }
1938
1939 void
1940 mp_cpu_faulted_enter(struct cpu *cp)
1941 {
1942 #ifdef __xpv
1943 _NOTE(ARGUNUSED(cp));
1944 #else
1945 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1946
1947 if (hdl != NULL) {
1948 cmi_hdl_hold(hdl);
1949 } else {
1950 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1951 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1952 }
1953 if (hdl != NULL) {
1954 cmi_faulted_enter(hdl);
1955 cmi_hdl_rele(hdl);
1956 }
1957 #endif
1958 }
1959
1960 void
1961 mp_cpu_faulted_exit(struct cpu *cp)
1962 {
1963 #ifdef __xpv
1964 _NOTE(ARGUNUSED(cp));
1965 #else
1966 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1967
1968 if (hdl != NULL) {
1969 cmi_hdl_hold(hdl);
1970 } else {
1971 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1972 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1973 }
1974 if (hdl != NULL) {
1975 cmi_faulted_exit(hdl);
1976 cmi_hdl_rele(hdl);
1977 }
1978 #endif
1979 }
1980
1981 /*
1982 * The following two routines are used as context operators on threads belonging
1983 * to processes with a private LDT (see sysi86). Due to the rarity of such
1984 * processes, these routines are currently written for best code readability and
1985 * organization rather than speed. We could avoid checking x86_featureset at
1986 * every context switch by installing different context ops, depending on
1987 * x86_featureset, at LDT creation time -- one for each combination of fast
1988 * syscall features.
1989 */
1990
1991 /*ARGSUSED*/
1992 void
1993 cpu_fast_syscall_disable(void *arg)
1994 {
1995 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1996 is_x86_feature(x86_featureset, X86FSET_SEP))
1997 cpu_sep_disable();
1998 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
1999 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2000 cpu_asysc_disable();
2001 }
2002
2003 /*ARGSUSED*/
2004 void
2005 cpu_fast_syscall_enable(void *arg)
2006 {
2007 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2008 is_x86_feature(x86_featureset, X86FSET_SEP))
2009 cpu_sep_enable();
2010 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2011 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2012 cpu_asysc_enable();
2013 }
2014
2015 static void
2016 cpu_sep_enable(void)
2017 {
2018 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2019 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2020
2021 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2022 }
2023
2024 static void
2025 cpu_sep_disable(void)
2026 {
2027 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2028 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2029
2030 /*
2031 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2032 * the sysenter or sysexit instruction to trigger a #gp fault.
2033 */
2034 wrmsr(MSR_INTC_SEP_CS, 0);
2035 }
2036
2037 static void
2038 cpu_asysc_enable(void)
2039 {
2040 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2041 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2042
2043 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2044 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2045 }
2046
2047 static void
2048 cpu_asysc_disable(void)
2049 {
2050 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2051 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2052
2053 /*
2054 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2055 * executing syscall or sysret with this bit off will incur a #ud trap.
2056 */
2057 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2058 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2059 }