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OS-4391 Want Broadwell Instruction support
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
OS-5192 need faster clock_gettime
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Joshua M. Clulow <jmc@joyent.com>
Reviewed by: Ryan Zezeski <ryan@zinascii.com>
OS-4368 lxbrand glibc abhors CPUID limits
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--- old/usr/src/uts/i86pc/os/cpuid.c
+++ new/usr/src/uts/i86pc/os/cpuid.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
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25 25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31 /*
32 32 * Portions Copyright 2009 Advanced Micro Devices, Inc.
33 33 */
34 34 /*
35 - * Copyright (c) 2015, Joyent, Inc. All rights reserved.
35 + * Copyright 2016 Joyent, Inc.
36 36 */
37 37 /*
38 38 * Various routines to handle identification
39 39 * and classification of x86 processors.
40 40 */
41 41
42 42 #include <sys/types.h>
43 43 #include <sys/archsystm.h>
44 44 #include <sys/x86_archext.h>
45 45 #include <sys/kmem.h>
46 46 #include <sys/systm.h>
47 47 #include <sys/cmn_err.h>
48 48 #include <sys/sunddi.h>
49 49 #include <sys/sunndi.h>
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50 50 #include <sys/cpuvar.h>
51 51 #include <sys/processor.h>
52 52 #include <sys/sysmacros.h>
53 53 #include <sys/pg.h>
54 54 #include <sys/fp.h>
55 55 #include <sys/controlregs.h>
56 56 #include <sys/bitmap.h>
57 57 #include <sys/auxv_386.h>
58 58 #include <sys/memnode.h>
59 59 #include <sys/pci_cfgspace.h>
60 +#include <sys/comm_page.h>
61 +#include <sys/tsc.h>
60 62
61 63 #ifdef __xpv
62 64 #include <sys/hypervisor.h>
63 65 #else
64 66 #include <sys/ontrap.h>
65 67 #endif
66 68
67 69 /*
68 70 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
69 71 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
70 72 * them accordingly. For most modern processors, feature detection occurs here
71 73 * in pass 1.
72 74 *
73 75 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
74 76 * for the boot CPU and does the basic analysis that the early kernel needs.
75 77 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
76 78 * CPU.
77 79 *
78 80 * Pass 1 includes:
79 81 *
80 82 * o Determining vendor/model/family/stepping and setting x86_type and
81 83 * x86_vendor accordingly.
82 84 * o Processing the feature flags returned by the cpuid instruction while
83 85 * applying any workarounds or tricks for the specific processor.
84 86 * o Mapping the feature flags into Solaris feature bits (X86_*).
85 87 * o Processing extended feature flags if supported by the processor,
86 88 * again while applying specific processor knowledge.
87 89 * o Determining the CMT characteristics of the system.
88 90 *
89 91 * Pass 1 is done on non-boot CPUs during their initialization and the results
90 92 * are used only as a meager attempt at ensuring that all processors within the
91 93 * system support the same features.
92 94 *
93 95 * Pass 2 of cpuid feature analysis happens just at the beginning
94 96 * of startup(). It just copies in and corrects the remainder
95 97 * of the cpuid data we depend on: standard cpuid functions that we didn't
96 98 * need for pass1 feature analysis, and extended cpuid functions beyond the
97 99 * simple feature processing done in pass1.
98 100 *
99 101 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
100 102 * particular kernel memory allocation has been made available. It creates a
101 103 * readable brand string based on the data collected in the first two passes.
102 104 *
103 105 * Pass 4 of cpuid analysis is invoked after post_startup() when all
104 106 * the support infrastructure for various hardware features has been
105 107 * initialized. It determines which processor features will be reported
106 108 * to userland via the aux vector.
107 109 *
108 110 * All passes are executed on all CPUs, but only the boot CPU determines what
109 111 * features the kernel will use.
110 112 *
111 113 * Much of the worst junk in this file is for the support of processors
112 114 * that didn't really implement the cpuid instruction properly.
113 115 *
114 116 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
115 117 * the pass numbers. Accordingly, changes to the pass code may require changes
116 118 * to the accessor code.
117 119 */
118 120
119 121 uint_t x86_vendor = X86_VENDOR_IntelClone;
120 122 uint_t x86_type = X86_TYPE_OTHER;
121 123 uint_t x86_clflush_size = 0;
122 124
123 125 uint_t pentiumpro_bug4046376;
124 126
125 127 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
126 128
127 129 static char *x86_feature_names[NUM_X86_FEATURES] = {
128 130 "lgpg",
129 131 "tsc",
130 132 "msr",
131 133 "mtrr",
132 134 "pge",
133 135 "de",
134 136 "cmov",
135 137 "mmx",
136 138 "mca",
137 139 "pae",
138 140 "cv8",
139 141 "pat",
140 142 "sep",
141 143 "sse",
142 144 "sse2",
143 145 "htt",
144 146 "asysc",
145 147 "nx",
146 148 "sse3",
147 149 "cx16",
148 150 "cmp",
149 151 "tscp",
150 152 "mwait",
151 153 "sse4a",
152 154 "cpuid",
153 155 "ssse3",
154 156 "sse4_1",
155 157 "sse4_2",
156 158 "1gpg",
157 159 "clfsh",
158 160 "64",
159 161 "aes",
160 162 "pclmulqdq",
161 163 "xsave",
162 164 "avx",
163 165 "vmx",
164 166 "svm",
165 167 "topoext",
166 168 "f16c",
167 169 "rdrand",
168 170 "x2apic",
169 171 "avx2",
170 172 "bmi1",
171 173 "bmi2",
172 174 "fma",
173 175 "smep",
174 176 "smap",
175 177 "adx",
176 178 "rdseed"
177 179 };
178 180
179 181 boolean_t
180 182 is_x86_feature(void *featureset, uint_t feature)
181 183 {
182 184 ASSERT(feature < NUM_X86_FEATURES);
183 185 return (BT_TEST((ulong_t *)featureset, feature));
184 186 }
185 187
186 188 void
187 189 add_x86_feature(void *featureset, uint_t feature)
188 190 {
189 191 ASSERT(feature < NUM_X86_FEATURES);
190 192 BT_SET((ulong_t *)featureset, feature);
191 193 }
192 194
193 195 void
194 196 remove_x86_feature(void *featureset, uint_t feature)
195 197 {
196 198 ASSERT(feature < NUM_X86_FEATURES);
197 199 BT_CLEAR((ulong_t *)featureset, feature);
198 200 }
199 201
200 202 boolean_t
201 203 compare_x86_featureset(void *setA, void *setB)
202 204 {
203 205 /*
204 206 * We assume that the unused bits of the bitmap are always zero.
205 207 */
206 208 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
207 209 return (B_TRUE);
208 210 } else {
209 211 return (B_FALSE);
210 212 }
211 213 }
212 214
213 215 void
214 216 print_x86_featureset(void *featureset)
215 217 {
216 218 uint_t i;
217 219
218 220 for (i = 0; i < NUM_X86_FEATURES; i++) {
219 221 if (is_x86_feature(featureset, i)) {
220 222 cmn_err(CE_CONT, "?x86_feature: %s\n",
221 223 x86_feature_names[i]);
222 224 }
223 225 }
224 226 }
225 227
226 228 static size_t xsave_state_size = 0;
227 229 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE);
228 230 boolean_t xsave_force_disable = B_FALSE;
229 231 extern int disable_smap;
230 232
231 233 /*
232 234 * This is set to platform type we are running on.
233 235 */
234 236 static int platform_type = -1;
235 237
236 238 #if !defined(__xpv)
237 239 /*
238 240 * Variable to patch if hypervisor platform detection needs to be
239 241 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
240 242 */
241 243 int enable_platform_detection = 1;
242 244 #endif
243 245
244 246 /*
245 247 * monitor/mwait info.
246 248 *
247 249 * size_actual and buf_actual are the real address and size allocated to get
248 250 * proper mwait_buf alignement. buf_actual and size_actual should be passed
249 251 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
250 252 * processor cache-line alignment, but this is not guarantied in the furture.
251 253 */
252 254 struct mwait_info {
253 255 size_t mon_min; /* min size to avoid missed wakeups */
254 256 size_t mon_max; /* size to avoid false wakeups */
255 257 size_t size_actual; /* size actually allocated */
256 258 void *buf_actual; /* memory actually allocated */
257 259 uint32_t support; /* processor support of monitor/mwait */
258 260 };
259 261
260 262 /*
261 263 * xsave/xrestor info.
262 264 *
263 265 * This structure contains HW feature bits and size of the xsave save area.
264 266 * Note: the kernel will use the maximum size required for all hardware
265 267 * features. It is not optimize for potential memory savings if features at
266 268 * the end of the save area are not enabled.
267 269 */
268 270 struct xsave_info {
269 271 uint32_t xsav_hw_features_low; /* Supported HW features */
270 272 uint32_t xsav_hw_features_high; /* Supported HW features */
271 273 size_t xsav_max_size; /* max size save area for HW features */
272 274 size_t ymm_size; /* AVX: size of ymm save area */
273 275 size_t ymm_offset; /* AVX: offset for ymm save area */
274 276 };
275 277
276 278
277 279 /*
278 280 * These constants determine how many of the elements of the
279 281 * cpuid we cache in the cpuid_info data structure; the
280 282 * remaining elements are accessible via the cpuid instruction.
281 283 */
282 284
283 285 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */
284 286 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
285 287
286 288 /*
287 289 * Some terminology needs to be explained:
288 290 * - Socket: Something that can be plugged into a motherboard.
289 291 * - Package: Same as socket
290 292 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
291 293 * differently: there, chip is the same as processor node (below)
292 294 * - Processor node: Some AMD processors have more than one
293 295 * "subprocessor" embedded in a package. These subprocessors (nodes)
294 296 * are fully-functional processors themselves with cores, caches,
295 297 * memory controllers, PCI configuration spaces. They are connected
296 298 * inside the package with Hypertransport links. On single-node
297 299 * processors, processor node is equivalent to chip/socket/package.
298 300 * - Compute Unit: Some AMD processors pair cores in "compute units" that
299 301 * share the FPU and the I$ and L2 caches.
300 302 */
301 303
302 304 struct cpuid_info {
303 305 uint_t cpi_pass; /* last pass completed */
304 306 /*
305 307 * standard function information
306 308 */
307 309 uint_t cpi_maxeax; /* fn 0: %eax */
308 310 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
309 311 uint_t cpi_vendor; /* enum of cpi_vendorstr */
310 312
311 313 uint_t cpi_family; /* fn 1: extended family */
312 314 uint_t cpi_model; /* fn 1: extended model */
313 315 uint_t cpi_step; /* fn 1: stepping */
314 316 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
315 317 /* AMD: package/socket # */
316 318 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
317 319 int cpi_clogid; /* fn 1: %ebx: thread # */
318 320 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
319 321 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
320 322 uint_t cpi_ncache; /* fn 2: number of elements */
321 323 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
322 324 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
323 325 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
324 326 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
325 327 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */
326 328 /*
327 329 * extended function information
328 330 */
329 331 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
330 332 char cpi_brandstr[49]; /* fn 0x8000000[234] */
331 333 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
332 334 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
333 335 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
334 336
335 337 id_t cpi_coreid; /* same coreid => strands share core */
336 338 int cpi_pkgcoreid; /* core number within single package */
337 339 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
338 340 /* Intel: fn 4: %eax[31-26] */
339 341 /*
340 342 * supported feature information
341 343 */
342 344 uint32_t cpi_support[6];
343 345 #define STD_EDX_FEATURES 0
344 346 #define AMD_EDX_FEATURES 1
345 347 #define TM_EDX_FEATURES 2
346 348 #define STD_ECX_FEATURES 3
347 349 #define AMD_ECX_FEATURES 4
348 350 #define STD_EBX_FEATURES 5
349 351 /*
350 352 * Synthesized information, where known.
351 353 */
352 354 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
353 355 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
354 356 uint32_t cpi_socket; /* Chip package/socket type */
355 357
356 358 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
357 359 uint32_t cpi_apicid;
358 360 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
359 361 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
360 362 /* Intel: 1 */
361 363 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
362 364 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
363 365
364 366 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
365 367 };
366 368
367 369
368 370 static struct cpuid_info cpuid_info0;
369 371
370 372 /*
371 373 * These bit fields are defined by the Intel Application Note AP-485
372 374 * "Intel Processor Identification and the CPUID Instruction"
373 375 */
374 376 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
375 377 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
376 378 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
377 379 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
378 380 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
379 381 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
380 382
381 383 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
382 384 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
383 385 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
384 386 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
385 387 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx)
386 388
387 389 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
388 390 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
389 391 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
390 392 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
391 393
392 394 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
393 395 #define CPI_XMAXEAX_MAX 0x80000100
394 396 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
395 397 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
396 398
397 399 /*
398 400 * Function 4 (Deterministic Cache Parameters) macros
399 401 * Defined by Intel Application Note AP-485
400 402 */
401 403 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
402 404 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
403 405 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
404 406 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
405 407 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
406 408 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
407 409 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
408 410
409 411 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
410 412 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
411 413 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
412 414
413 415 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
414 416
415 417 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
416 418
417 419
418 420 /*
419 421 * A couple of shorthand macros to identify "later" P6-family chips
420 422 * like the Pentium M and Core. First, the "older" P6-based stuff
421 423 * (loosely defined as "pre-Pentium-4"):
422 424 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
423 425 */
424 426
425 427 #define IS_LEGACY_P6(cpi) ( \
426 428 cpi->cpi_family == 6 && \
427 429 (cpi->cpi_model == 1 || \
428 430 cpi->cpi_model == 3 || \
429 431 cpi->cpi_model == 5 || \
430 432 cpi->cpi_model == 6 || \
431 433 cpi->cpi_model == 7 || \
432 434 cpi->cpi_model == 8 || \
433 435 cpi->cpi_model == 0xA || \
434 436 cpi->cpi_model == 0xB) \
435 437 )
436 438
437 439 /* A "new F6" is everything with family 6 that's not the above */
438 440 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
439 441
440 442 /* Extended family/model support */
441 443 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
442 444 cpi->cpi_family >= 0xf)
443 445
444 446 /*
445 447 * Info for monitor/mwait idle loop.
446 448 *
447 449 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
448 450 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
449 451 * 2006.
450 452 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
451 453 * Documentation Updates" #33633, Rev 2.05, December 2006.
452 454 */
453 455 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
454 456 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
455 457 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
456 458 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
457 459 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
458 460 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
459 461 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
460 462 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
461 463 /*
462 464 * Number of sub-cstates for a given c-state.
463 465 */
464 466 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
465 467 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
466 468
467 469 /*
468 470 * XSAVE leaf 0xD enumeration
469 471 */
470 472 #define CPUID_LEAFD_2_YMM_OFFSET 576
471 473 #define CPUID_LEAFD_2_YMM_SIZE 256
472 474
473 475 /*
474 476 * Functions we consune from cpuid_subr.c; don't publish these in a header
475 477 * file to try and keep people using the expected cpuid_* interfaces.
476 478 */
477 479 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
478 480 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
479 481 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
480 482 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
481 483 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
482 484
483 485 /*
484 486 * Apply up various platform-dependent restrictions where the
485 487 * underlying platform restrictions mean the CPU can be marked
486 488 * as less capable than its cpuid instruction would imply.
487 489 */
488 490 #if defined(__xpv)
489 491 static void
490 492 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
491 493 {
492 494 switch (eax) {
493 495 case 1: {
494 496 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
495 497 0 : CPUID_INTC_EDX_MCA;
496 498 cp->cp_edx &=
497 499 ~(mcamask |
498 500 CPUID_INTC_EDX_PSE |
499 501 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
500 502 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
501 503 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
502 504 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
503 505 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
504 506 break;
505 507 }
506 508
507 509 case 0x80000001:
508 510 cp->cp_edx &=
509 511 ~(CPUID_AMD_EDX_PSE |
510 512 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
511 513 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
512 514 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
513 515 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
514 516 CPUID_AMD_EDX_TSCP);
515 517 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
516 518 break;
517 519 default:
518 520 break;
519 521 }
520 522
521 523 switch (vendor) {
522 524 case X86_VENDOR_Intel:
523 525 switch (eax) {
524 526 case 4:
525 527 /*
526 528 * Zero out the (ncores-per-chip - 1) field
527 529 */
528 530 cp->cp_eax &= 0x03fffffff;
529 531 break;
530 532 default:
531 533 break;
532 534 }
533 535 break;
534 536 case X86_VENDOR_AMD:
535 537 switch (eax) {
536 538
537 539 case 0x80000001:
538 540 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
539 541 break;
540 542
541 543 case 0x80000008:
542 544 /*
543 545 * Zero out the (ncores-per-chip - 1) field
544 546 */
545 547 cp->cp_ecx &= 0xffffff00;
546 548 break;
547 549 default:
548 550 break;
549 551 }
550 552 break;
551 553 default:
552 554 break;
553 555 }
554 556 }
555 557 #else
556 558 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
557 559 #endif
558 560
559 561 /*
560 562 * Some undocumented ways of patching the results of the cpuid
561 563 * instruction to permit running Solaris 10 on future cpus that
562 564 * we don't currently support. Could be set to non-zero values
563 565 * via settings in eeprom.
564 566 */
565 567
566 568 uint32_t cpuid_feature_ecx_include;
567 569 uint32_t cpuid_feature_ecx_exclude;
568 570 uint32_t cpuid_feature_edx_include;
569 571 uint32_t cpuid_feature_edx_exclude;
570 572
571 573 /*
572 574 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
573 575 */
574 576 void
575 577 cpuid_alloc_space(cpu_t *cpu)
576 578 {
577 579 /*
578 580 * By convention, cpu0 is the boot cpu, which is set up
579 581 * before memory allocation is available. All other cpus get
580 582 * their cpuid_info struct allocated here.
581 583 */
582 584 ASSERT(cpu->cpu_id != 0);
583 585 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
584 586 cpu->cpu_m.mcpu_cpi =
585 587 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
586 588 }
587 589
588 590 void
589 591 cpuid_free_space(cpu_t *cpu)
590 592 {
591 593 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
592 594 int i;
593 595
594 596 ASSERT(cpi != NULL);
595 597 ASSERT(cpi != &cpuid_info0);
596 598
597 599 /*
598 600 * Free up any function 4 related dynamic storage
599 601 */
600 602 for (i = 1; i < cpi->cpi_std_4_size; i++)
601 603 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
602 604 if (cpi->cpi_std_4_size > 0)
603 605 kmem_free(cpi->cpi_std_4,
604 606 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
605 607
606 608 kmem_free(cpi, sizeof (*cpi));
607 609 cpu->cpu_m.mcpu_cpi = NULL;
608 610 }
609 611
610 612 #if !defined(__xpv)
611 613 /*
612 614 * Determine the type of the underlying platform. This is used to customize
613 615 * initialization of various subsystems (e.g. TSC). determine_platform() must
614 616 * only ever be called once to prevent two processors from seeing different
615 617 * values of platform_type. Must be called before cpuid_pass1(), the earliest
616 618 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
617 619 */
618 620 void
619 621 determine_platform(void)
620 622 {
621 623 struct cpuid_regs cp;
622 624 uint32_t base;
623 625 uint32_t regs[4];
624 626 char *hvstr = (char *)regs;
625 627
626 628 ASSERT(platform_type == -1);
627 629
628 630 platform_type = HW_NATIVE;
629 631
630 632 if (!enable_platform_detection)
631 633 return;
632 634
633 635 /*
634 636 * If Hypervisor CPUID bit is set, try to determine hypervisor
635 637 * vendor signature, and set platform type accordingly.
636 638 *
637 639 * References:
638 640 * http://lkml.org/lkml/2008/10/1/246
639 641 * http://kb.vmware.com/kb/1009458
640 642 */
641 643 cp.cp_eax = 0x1;
642 644 (void) __cpuid_insn(&cp);
643 645 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
644 646 cp.cp_eax = 0x40000000;
645 647 (void) __cpuid_insn(&cp);
646 648 regs[0] = cp.cp_ebx;
647 649 regs[1] = cp.cp_ecx;
648 650 regs[2] = cp.cp_edx;
649 651 regs[3] = 0;
650 652 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
651 653 platform_type = HW_XEN_HVM;
652 654 return;
653 655 }
654 656 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
655 657 platform_type = HW_VMWARE;
656 658 return;
657 659 }
658 660 if (strcmp(hvstr, HVSIG_KVM) == 0) {
659 661 platform_type = HW_KVM;
660 662 return;
661 663 }
662 664 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
663 665 platform_type = HW_MICROSOFT;
664 666 } else {
665 667 /*
666 668 * Check older VMware hardware versions. VMware hypervisor is
667 669 * detected by performing an IN operation to VMware hypervisor
668 670 * port and checking that value returned in %ebx is VMware
669 671 * hypervisor magic value.
670 672 *
671 673 * References: http://kb.vmware.com/kb/1009458
672 674 */
673 675 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
674 676 if (regs[1] == VMWARE_HVMAGIC) {
675 677 platform_type = HW_VMWARE;
676 678 return;
677 679 }
678 680 }
679 681
680 682 /*
681 683 * Check Xen hypervisor. In a fully virtualized domain,
682 684 * Xen's pseudo-cpuid function returns a string representing the
683 685 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
684 686 * supported cpuid function. We need at least a (base + 2) leaf value
685 687 * to do what we want to do. Try different base values, since the
686 688 * hypervisor might use a different one depending on whether Hyper-V
687 689 * emulation is switched on by default or not.
688 690 */
689 691 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
690 692 cp.cp_eax = base;
691 693 (void) __cpuid_insn(&cp);
692 694 regs[0] = cp.cp_ebx;
693 695 regs[1] = cp.cp_ecx;
694 696 regs[2] = cp.cp_edx;
695 697 regs[3] = 0;
696 698 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
697 699 cp.cp_eax >= (base + 2)) {
698 700 platform_type &= ~HW_NATIVE;
699 701 platform_type |= HW_XEN_HVM;
700 702 return;
701 703 }
702 704 }
703 705 }
704 706
705 707 int
706 708 get_hwenv(void)
707 709 {
708 710 ASSERT(platform_type != -1);
709 711 return (platform_type);
710 712 }
711 713
712 714 int
713 715 is_controldom(void)
714 716 {
715 717 return (0);
716 718 }
717 719
718 720 #else
719 721
720 722 int
721 723 get_hwenv(void)
722 724 {
723 725 return (HW_XEN_PV);
724 726 }
725 727
726 728 int
727 729 is_controldom(void)
728 730 {
729 731 return (DOMAIN_IS_INITDOMAIN(xen_info));
730 732 }
731 733
732 734 #endif /* __xpv */
733 735
734 736 static void
735 737 cpuid_intel_getids(cpu_t *cpu, void *feature)
736 738 {
737 739 uint_t i;
738 740 uint_t chipid_shift = 0;
739 741 uint_t coreid_shift = 0;
740 742 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
741 743
742 744 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
743 745 chipid_shift++;
744 746
745 747 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
746 748 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
747 749
748 750 if (is_x86_feature(feature, X86FSET_CMP)) {
749 751 /*
750 752 * Multi-core (and possibly multi-threaded)
751 753 * processors.
752 754 */
753 755 uint_t ncpu_per_core;
754 756 if (cpi->cpi_ncore_per_chip == 1)
755 757 ncpu_per_core = cpi->cpi_ncpu_per_chip;
756 758 else if (cpi->cpi_ncore_per_chip > 1)
757 759 ncpu_per_core = cpi->cpi_ncpu_per_chip /
758 760 cpi->cpi_ncore_per_chip;
759 761 /*
760 762 * 8bit APIC IDs on dual core Pentiums
761 763 * look like this:
762 764 *
763 765 * +-----------------------+------+------+
764 766 * | Physical Package ID | MC | HT |
765 767 * +-----------------------+------+------+
766 768 * <------- chipid -------->
767 769 * <------- coreid --------------->
768 770 * <--- clogid -->
769 771 * <------>
770 772 * pkgcoreid
771 773 *
772 774 * Where the number of bits necessary to
773 775 * represent MC and HT fields together equals
774 776 * to the minimum number of bits necessary to
775 777 * store the value of cpi->cpi_ncpu_per_chip.
776 778 * Of those bits, the MC part uses the number
777 779 * of bits necessary to store the value of
778 780 * cpi->cpi_ncore_per_chip.
779 781 */
780 782 for (i = 1; i < ncpu_per_core; i <<= 1)
781 783 coreid_shift++;
782 784 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
783 785 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
784 786 } else if (is_x86_feature(feature, X86FSET_HTT)) {
785 787 /*
786 788 * Single-core multi-threaded processors.
787 789 */
788 790 cpi->cpi_coreid = cpi->cpi_chipid;
789 791 cpi->cpi_pkgcoreid = 0;
790 792 }
791 793 cpi->cpi_procnodeid = cpi->cpi_chipid;
792 794 cpi->cpi_compunitid = cpi->cpi_coreid;
793 795 }
794 796
795 797 static void
796 798 cpuid_amd_getids(cpu_t *cpu)
797 799 {
798 800 int i, first_half, coreidsz;
799 801 uint32_t nb_caps_reg;
800 802 uint_t node2_1;
801 803 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
802 804 struct cpuid_regs *cp;
803 805
804 806 /*
805 807 * AMD CMP chips currently have a single thread per core.
806 808 *
807 809 * Since no two cpus share a core we must assign a distinct coreid
808 810 * per cpu, and we do this by using the cpu_id. This scheme does not,
809 811 * however, guarantee that sibling cores of a chip will have sequential
810 812 * coreids starting at a multiple of the number of cores per chip -
811 813 * that is usually the case, but if the ACPI MADT table is presented
812 814 * in a different order then we need to perform a few more gymnastics
813 815 * for the pkgcoreid.
814 816 *
815 817 * All processors in the system have the same number of enabled
816 818 * cores. Cores within a processor are always numbered sequentially
817 819 * from 0 regardless of how many or which are disabled, and there
818 820 * is no way for operating system to discover the real core id when some
819 821 * are disabled.
820 822 *
821 823 * In family 0x15, the cores come in pairs called compute units. They
822 824 * share I$ and L2 caches and the FPU. Enumeration of this feature is
823 825 * simplified by the new topology extensions CPUID leaf, indicated by
824 826 * the X86 feature X86FSET_TOPOEXT.
825 827 */
826 828
827 829 cpi->cpi_coreid = cpu->cpu_id;
828 830 cpi->cpi_compunitid = cpu->cpu_id;
829 831
830 832 if (cpi->cpi_xmaxeax >= 0x80000008) {
831 833
832 834 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
833 835
834 836 /*
835 837 * In AMD parlance chip is really a node while Solaris
836 838 * sees chip as equivalent to socket/package.
837 839 */
838 840 cpi->cpi_ncore_per_chip =
839 841 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
840 842 if (coreidsz == 0) {
841 843 /* Use legacy method */
842 844 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
843 845 coreidsz++;
844 846 if (coreidsz == 0)
845 847 coreidsz = 1;
846 848 }
847 849 } else {
848 850 /* Assume single-core part */
849 851 cpi->cpi_ncore_per_chip = 1;
850 852 coreidsz = 1;
851 853 }
852 854
853 855 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
854 856 cpi->cpi_apicid & ((1<<coreidsz) - 1);
855 857 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
856 858
857 859 /* Get node ID, compute unit ID */
858 860 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
859 861 cpi->cpi_xmaxeax >= 0x8000001e) {
860 862 cp = &cpi->cpi_extd[0x1e];
861 863 cp->cp_eax = 0x8000001e;
862 864 (void) __cpuid_insn(cp);
863 865
864 866 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
865 867 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
866 868 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
867 869 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
868 870 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
869 871 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
870 872 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
871 873 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
872 874 } else if (cpi->cpi_family == 0x10) {
873 875 /*
874 876 * See if we are a multi-node processor.
875 877 * All processors in the system have the same number of nodes
876 878 */
877 879 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
878 880 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
879 881 /* Single-node */
880 882 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
881 883 coreidsz);
882 884 } else {
883 885
884 886 /*
885 887 * Multi-node revision D (2 nodes per package
886 888 * are supported)
887 889 */
888 890 cpi->cpi_procnodes_per_pkg = 2;
889 891
890 892 first_half = (cpi->cpi_pkgcoreid <=
891 893 (cpi->cpi_ncore_per_chip/2 - 1));
892 894
893 895 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
894 896 /* We are BSP */
895 897 cpi->cpi_procnodeid = (first_half ? 0 : 1);
896 898 } else {
897 899
898 900 /* We are AP */
899 901 /* NodeId[2:1] bits to use for reading F3xe8 */
900 902 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
901 903
902 904 nb_caps_reg =
903 905 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
904 906
905 907 /*
906 908 * Check IntNodeNum bit (31:30, but bit 31 is
907 909 * always 0 on dual-node processors)
908 910 */
909 911 if (BITX(nb_caps_reg, 30, 30) == 0)
910 912 cpi->cpi_procnodeid = node2_1 +
911 913 !first_half;
912 914 else
913 915 cpi->cpi_procnodeid = node2_1 +
914 916 first_half;
915 917 }
916 918 }
917 919 } else {
918 920 cpi->cpi_procnodeid = 0;
919 921 }
920 922
921 923 cpi->cpi_chipid =
922 924 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
923 925 }
924 926
925 927 /*
926 928 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
927 929 */
928 930 void
929 931 setup_xfem(void)
930 932 {
931 933 uint64_t flags = XFEATURE_LEGACY_FP;
932 934
933 935 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
934 936
935 937 if (is_x86_feature(x86_featureset, X86FSET_SSE))
936 938 flags |= XFEATURE_SSE;
937 939
938 940 if (is_x86_feature(x86_featureset, X86FSET_AVX))
939 941 flags |= XFEATURE_AVX;
940 942
941 943 set_xcr(XFEATURE_ENABLED_MASK, flags);
942 944
943 945 xsave_bv_all = flags;
944 946 }
945 947
946 948 void
947 949 cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
948 950 {
949 951 uint32_t mask_ecx, mask_edx;
950 952 struct cpuid_info *cpi;
951 953 struct cpuid_regs *cp;
952 954 int xcpuid;
953 955 #if !defined(__xpv)
954 956 extern int idle_cpu_prefer_mwait;
955 957 #endif
956 958
957 959 /*
958 960 * Space statically allocated for BSP, ensure pointer is set
959 961 */
960 962 if (cpu->cpu_id == 0) {
961 963 if (cpu->cpu_m.mcpu_cpi == NULL)
962 964 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
963 965 }
964 966
965 967 add_x86_feature(featureset, X86FSET_CPUID);
966 968
967 969 cpi = cpu->cpu_m.mcpu_cpi;
968 970 ASSERT(cpi != NULL);
969 971 cp = &cpi->cpi_std[0];
970 972 cp->cp_eax = 0;
971 973 cpi->cpi_maxeax = __cpuid_insn(cp);
972 974 {
973 975 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
974 976 *iptr++ = cp->cp_ebx;
975 977 *iptr++ = cp->cp_edx;
976 978 *iptr++ = cp->cp_ecx;
977 979 *(char *)&cpi->cpi_vendorstr[12] = '\0';
978 980 }
979 981
980 982 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
981 983 x86_vendor = cpi->cpi_vendor; /* for compatibility */
982 984
983 985 /*
984 986 * Limit the range in case of weird hardware
985 987 */
986 988 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
987 989 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
988 990 if (cpi->cpi_maxeax < 1)
989 991 goto pass1_done;
990 992
991 993 cp = &cpi->cpi_std[1];
992 994 cp->cp_eax = 1;
993 995 (void) __cpuid_insn(cp);
994 996
995 997 /*
996 998 * Extract identifying constants for easy access.
997 999 */
998 1000 cpi->cpi_model = CPI_MODEL(cpi);
999 1001 cpi->cpi_family = CPI_FAMILY(cpi);
1000 1002
1001 1003 if (cpi->cpi_family == 0xf)
1002 1004 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1003 1005
1004 1006 /*
1005 1007 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
1006 1008 * Intel, and presumably everyone else, uses model == 0xf, as
1007 1009 * one would expect (max value means possible overflow). Sigh.
1008 1010 */
1009 1011
1010 1012 switch (cpi->cpi_vendor) {
1011 1013 case X86_VENDOR_Intel:
1012 1014 if (IS_EXTENDED_MODEL_INTEL(cpi))
1013 1015 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1014 1016 break;
1015 1017 case X86_VENDOR_AMD:
1016 1018 if (CPI_FAMILY(cpi) == 0xf)
1017 1019 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1018 1020 break;
1019 1021 default:
1020 1022 if (cpi->cpi_model == 0xf)
1021 1023 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1022 1024 break;
1023 1025 }
1024 1026
1025 1027 cpi->cpi_step = CPI_STEP(cpi);
1026 1028 cpi->cpi_brandid = CPI_BRANDID(cpi);
1027 1029
1028 1030 /*
1029 1031 * *default* assumptions:
1030 1032 * - believe %edx feature word
1031 1033 * - ignore %ecx feature word
1032 1034 * - 32-bit virtual and physical addressing
1033 1035 */
1034 1036 mask_edx = 0xffffffff;
1035 1037 mask_ecx = 0;
1036 1038
1037 1039 cpi->cpi_pabits = cpi->cpi_vabits = 32;
1038 1040
1039 1041 switch (cpi->cpi_vendor) {
1040 1042 case X86_VENDOR_Intel:
1041 1043 if (cpi->cpi_family == 5)
1042 1044 x86_type = X86_TYPE_P5;
1043 1045 else if (IS_LEGACY_P6(cpi)) {
1044 1046 x86_type = X86_TYPE_P6;
1045 1047 pentiumpro_bug4046376 = 1;
1046 1048 /*
1047 1049 * Clear the SEP bit when it was set erroneously
1048 1050 */
1049 1051 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
1050 1052 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1051 1053 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
1052 1054 x86_type = X86_TYPE_P4;
1053 1055 /*
1054 1056 * We don't currently depend on any of the %ecx
1055 1057 * features until Prescott, so we'll only check
1056 1058 * this from P4 onwards. We might want to revisit
1057 1059 * that idea later.
1058 1060 */
1059 1061 mask_ecx = 0xffffffff;
1060 1062 } else if (cpi->cpi_family > 0xf)
1061 1063 mask_ecx = 0xffffffff;
1062 1064 /*
1063 1065 * We don't support MONITOR/MWAIT if leaf 5 is not available
1064 1066 * to obtain the monitor linesize.
1065 1067 */
1066 1068 if (cpi->cpi_maxeax < 5)
1067 1069 mask_ecx &= ~CPUID_INTC_ECX_MON;
1068 1070 break;
1069 1071 case X86_VENDOR_IntelClone:
1070 1072 default:
1071 1073 break;
1072 1074 case X86_VENDOR_AMD:
1073 1075 #if defined(OPTERON_ERRATUM_108)
1074 1076 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
1075 1077 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
1076 1078 cpi->cpi_model = 0xc;
1077 1079 } else
1078 1080 #endif
1079 1081 if (cpi->cpi_family == 5) {
1080 1082 /*
1081 1083 * AMD K5 and K6
1082 1084 *
1083 1085 * These CPUs have an incomplete implementation
1084 1086 * of MCA/MCE which we mask away.
1085 1087 */
1086 1088 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
1087 1089
1088 1090 /*
1089 1091 * Model 0 uses the wrong (APIC) bit
1090 1092 * to indicate PGE. Fix it here.
1091 1093 */
1092 1094 if (cpi->cpi_model == 0) {
1093 1095 if (cp->cp_edx & 0x200) {
1094 1096 cp->cp_edx &= ~0x200;
1095 1097 cp->cp_edx |= CPUID_INTC_EDX_PGE;
1096 1098 }
1097 1099 }
1098 1100
1099 1101 /*
1100 1102 * Early models had problems w/ MMX; disable.
1101 1103 */
1102 1104 if (cpi->cpi_model < 6)
1103 1105 mask_edx &= ~CPUID_INTC_EDX_MMX;
1104 1106 }
1105 1107
1106 1108 /*
1107 1109 * For newer families, SSE3 and CX16, at least, are valid;
1108 1110 * enable all
1109 1111 */
1110 1112 if (cpi->cpi_family >= 0xf)
1111 1113 mask_ecx = 0xffffffff;
1112 1114 /*
1113 1115 * We don't support MONITOR/MWAIT if leaf 5 is not available
1114 1116 * to obtain the monitor linesize.
1115 1117 */
1116 1118 if (cpi->cpi_maxeax < 5)
1117 1119 mask_ecx &= ~CPUID_INTC_ECX_MON;
1118 1120
1119 1121 #if !defined(__xpv)
1120 1122 /*
1121 1123 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
1122 1124 * processors. AMD does not intend MWAIT to be used in the cpu
1123 1125 * idle loop on current and future processors. 10h and future
1124 1126 * AMD processors use more power in MWAIT than HLT.
1125 1127 * Pre-family-10h Opterons do not have the MWAIT instruction.
1126 1128 */
1127 1129 idle_cpu_prefer_mwait = 0;
1128 1130 #endif
1129 1131
1130 1132 break;
1131 1133 case X86_VENDOR_TM:
1132 1134 /*
1133 1135 * workaround the NT workaround in CMS 4.1
1134 1136 */
1135 1137 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
1136 1138 (cpi->cpi_step == 2 || cpi->cpi_step == 3))
1137 1139 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1138 1140 break;
1139 1141 case X86_VENDOR_Centaur:
1140 1142 /*
1141 1143 * workaround the NT workarounds again
1142 1144 */
1143 1145 if (cpi->cpi_family == 6)
1144 1146 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1145 1147 break;
1146 1148 case X86_VENDOR_Cyrix:
1147 1149 /*
1148 1150 * We rely heavily on the probing in locore
1149 1151 * to actually figure out what parts, if any,
1150 1152 * of the Cyrix cpuid instruction to believe.
1151 1153 */
1152 1154 switch (x86_type) {
1153 1155 case X86_TYPE_CYRIX_486:
1154 1156 mask_edx = 0;
1155 1157 break;
1156 1158 case X86_TYPE_CYRIX_6x86:
1157 1159 mask_edx = 0;
1158 1160 break;
1159 1161 case X86_TYPE_CYRIX_6x86L:
1160 1162 mask_edx =
1161 1163 CPUID_INTC_EDX_DE |
1162 1164 CPUID_INTC_EDX_CX8;
1163 1165 break;
1164 1166 case X86_TYPE_CYRIX_6x86MX:
1165 1167 mask_edx =
1166 1168 CPUID_INTC_EDX_DE |
1167 1169 CPUID_INTC_EDX_MSR |
1168 1170 CPUID_INTC_EDX_CX8 |
1169 1171 CPUID_INTC_EDX_PGE |
1170 1172 CPUID_INTC_EDX_CMOV |
1171 1173 CPUID_INTC_EDX_MMX;
1172 1174 break;
1173 1175 case X86_TYPE_CYRIX_GXm:
1174 1176 mask_edx =
1175 1177 CPUID_INTC_EDX_MSR |
1176 1178 CPUID_INTC_EDX_CX8 |
1177 1179 CPUID_INTC_EDX_CMOV |
1178 1180 CPUID_INTC_EDX_MMX;
1179 1181 break;
1180 1182 case X86_TYPE_CYRIX_MediaGX:
1181 1183 break;
1182 1184 case X86_TYPE_CYRIX_MII:
1183 1185 case X86_TYPE_VIA_CYRIX_III:
1184 1186 mask_edx =
1185 1187 CPUID_INTC_EDX_DE |
1186 1188 CPUID_INTC_EDX_TSC |
1187 1189 CPUID_INTC_EDX_MSR |
1188 1190 CPUID_INTC_EDX_CX8 |
1189 1191 CPUID_INTC_EDX_PGE |
1190 1192 CPUID_INTC_EDX_CMOV |
1191 1193 CPUID_INTC_EDX_MMX;
1192 1194 break;
1193 1195 default:
1194 1196 break;
1195 1197 }
1196 1198 break;
1197 1199 }
1198 1200
1199 1201 #if defined(__xpv)
1200 1202 /*
1201 1203 * Do not support MONITOR/MWAIT under a hypervisor
1202 1204 */
1203 1205 mask_ecx &= ~CPUID_INTC_ECX_MON;
1204 1206 /*
1205 1207 * Do not support XSAVE under a hypervisor for now
1206 1208 */
1207 1209 xsave_force_disable = B_TRUE;
1208 1210
1209 1211 #endif /* __xpv */
1210 1212
1211 1213 if (xsave_force_disable) {
1212 1214 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
1213 1215 mask_ecx &= ~CPUID_INTC_ECX_AVX;
1214 1216 mask_ecx &= ~CPUID_INTC_ECX_F16C;
1215 1217 mask_ecx &= ~CPUID_INTC_ECX_FMA;
1216 1218 }
1217 1219
1218 1220 /*
1219 1221 * Now we've figured out the masks that determine
1220 1222 * which bits we choose to believe, apply the masks
1221 1223 * to the feature words, then map the kernel's view
1222 1224 * of these feature words into its feature word.
1223 1225 */
1224 1226 cp->cp_edx &= mask_edx;
1225 1227 cp->cp_ecx &= mask_ecx;
1226 1228
1227 1229 /*
1228 1230 * apply any platform restrictions (we don't call this
1229 1231 * immediately after __cpuid_insn here, because we need the
1230 1232 * workarounds applied above first)
1231 1233 */
1232 1234 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
1233 1235
1234 1236 /*
1235 1237 * In addition to ecx and edx, Intel is storing a bunch of instruction
1236 1238 * set extensions in leaf 7's ebx.
1237 1239 */
1238 1240 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) {
1239 1241 struct cpuid_regs *ecp;
1240 1242 ecp = &cpi->cpi_std[7];
1241 1243 ecp->cp_eax = 7;
1242 1244 ecp->cp_ecx = 0;
1243 1245 (void) __cpuid_insn(ecp);
1244 1246 /*
1245 1247 * If XSAVE has been disabled, just ignore all of the AVX
1246 1248 * dependent flags here.
1247 1249 */
1248 1250 if (xsave_force_disable) {
1249 1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
1250 1252 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
1251 1253 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
1252 1254 }
1253 1255
1254 1256 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
1255 1257 add_x86_feature(featureset, X86FSET_SMEP);
1256 1258
1257 1259 /*
1258 1260 * We check disable_smap here in addition to in startup_smap()
1259 1261 * to ensure CPUs that aren't the boot CPU don't accidentally
1260 1262 * include it in the feature set and thus generate a mismatched
1261 1263 * x86 feature set across CPUs. Note that at this time we only
1262 1264 * enable SMAP for the 64-bit kernel.
1263 1265 */
1264 1266 #if defined(__amd64)
1265 1267 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMAP &&
1266 1268 disable_smap == 0)
1267 1269 add_x86_feature(featureset, X86FSET_SMAP);
1268 1270 #endif
1269 1271 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED)
1270 1272 add_x86_feature(featureset, X86FSET_RDSEED);
1271 1273
1272 1274 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX)
1273 1275 add_x86_feature(featureset, X86FSET_ADX);
1274 1276 }
1275 1277
1276 1278 /*
1277 1279 * fold in overrides from the "eeprom" mechanism
1278 1280 */
1279 1281 cp->cp_edx |= cpuid_feature_edx_include;
1280 1282 cp->cp_edx &= ~cpuid_feature_edx_exclude;
1281 1283
1282 1284 cp->cp_ecx |= cpuid_feature_ecx_include;
1283 1285 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
1284 1286
1285 1287 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
1286 1288 add_x86_feature(featureset, X86FSET_LARGEPAGE);
1287 1289 }
1288 1290 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
1289 1291 add_x86_feature(featureset, X86FSET_TSC);
1290 1292 }
1291 1293 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
1292 1294 add_x86_feature(featureset, X86FSET_MSR);
1293 1295 }
1294 1296 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
1295 1297 add_x86_feature(featureset, X86FSET_MTRR);
1296 1298 }
1297 1299 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
1298 1300 add_x86_feature(featureset, X86FSET_PGE);
1299 1301 }
1300 1302 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
1301 1303 add_x86_feature(featureset, X86FSET_CMOV);
1302 1304 }
1303 1305 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
1304 1306 add_x86_feature(featureset, X86FSET_MMX);
1305 1307 }
1306 1308 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
1307 1309 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
1308 1310 add_x86_feature(featureset, X86FSET_MCA);
1309 1311 }
1310 1312 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
1311 1313 add_x86_feature(featureset, X86FSET_PAE);
1312 1314 }
1313 1315 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
1314 1316 add_x86_feature(featureset, X86FSET_CX8);
1315 1317 }
1316 1318 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
1317 1319 add_x86_feature(featureset, X86FSET_CX16);
1318 1320 }
1319 1321 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
1320 1322 add_x86_feature(featureset, X86FSET_PAT);
1321 1323 }
1322 1324 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
1323 1325 add_x86_feature(featureset, X86FSET_SEP);
1324 1326 }
1325 1327 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
1326 1328 /*
1327 1329 * In our implementation, fxsave/fxrstor
1328 1330 * are prerequisites before we'll even
1329 1331 * try and do SSE things.
1330 1332 */
1331 1333 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
1332 1334 add_x86_feature(featureset, X86FSET_SSE);
1333 1335 }
1334 1336 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
1335 1337 add_x86_feature(featureset, X86FSET_SSE2);
1336 1338 }
1337 1339 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
1338 1340 add_x86_feature(featureset, X86FSET_SSE3);
1339 1341 }
1340 1342 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
1341 1343 add_x86_feature(featureset, X86FSET_SSSE3);
1342 1344 }
1343 1345 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
1344 1346 add_x86_feature(featureset, X86FSET_SSE4_1);
1345 1347 }
1346 1348 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
1347 1349 add_x86_feature(featureset, X86FSET_SSE4_2);
1348 1350 }
1349 1351 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
1350 1352 add_x86_feature(featureset, X86FSET_AES);
1351 1353 }
1352 1354 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
1353 1355 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
1354 1356 }
1355 1357
1356 1358 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
1357 1359 add_x86_feature(featureset, X86FSET_XSAVE);
1358 1360
1359 1361 /* We only test AVX when there is XSAVE */
1360 1362 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
1361 1363 add_x86_feature(featureset,
1362 1364 X86FSET_AVX);
1363 1365
1364 1366 /*
1365 1367 * Intel says we can't check these without also
1366 1368 * checking AVX.
1367 1369 */
1368 1370 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
1369 1371 add_x86_feature(featureset,
1370 1372 X86FSET_F16C);
1371 1373
1372 1374 if (cp->cp_ecx & CPUID_INTC_ECX_FMA)
1373 1375 add_x86_feature(featureset,
1374 1376 X86FSET_FMA);
1375 1377
1376 1378 if (cpi->cpi_std[7].cp_ebx &
1377 1379 CPUID_INTC_EBX_7_0_BMI1)
1378 1380 add_x86_feature(featureset,
1379 1381 X86FSET_BMI1);
1380 1382
1381 1383 if (cpi->cpi_std[7].cp_ebx &
1382 1384 CPUID_INTC_EBX_7_0_BMI2)
1383 1385 add_x86_feature(featureset,
1384 1386 X86FSET_BMI2);
1385 1387
1386 1388 if (cpi->cpi_std[7].cp_ebx &
1387 1389 CPUID_INTC_EBX_7_0_AVX2)
1388 1390 add_x86_feature(featureset,
1389 1391 X86FSET_AVX2);
1390 1392 }
1391 1393 }
1392 1394 }
1393 1395 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
1394 1396 add_x86_feature(featureset, X86FSET_X2APIC);
1395 1397 }
1396 1398 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
1397 1399 add_x86_feature(featureset, X86FSET_DE);
1398 1400 }
1399 1401 #if !defined(__xpv)
1400 1402 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
1401 1403
1402 1404 /*
1403 1405 * We require the CLFLUSH instruction for erratum workaround
1404 1406 * to use MONITOR/MWAIT.
1405 1407 */
1406 1408 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1407 1409 cpi->cpi_mwait.support |= MWAIT_SUPPORT;
1408 1410 add_x86_feature(featureset, X86FSET_MWAIT);
1409 1411 } else {
1410 1412 extern int idle_cpu_assert_cflush_monitor;
1411 1413
1412 1414 /*
1413 1415 * All processors we are aware of which have
1414 1416 * MONITOR/MWAIT also have CLFLUSH.
1415 1417 */
1416 1418 if (idle_cpu_assert_cflush_monitor) {
1417 1419 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
1418 1420 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
1419 1421 }
1420 1422 }
1421 1423 }
1422 1424 #endif /* __xpv */
1423 1425
1424 1426 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
1425 1427 add_x86_feature(featureset, X86FSET_VMX);
1426 1428 }
1427 1429
1428 1430 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
1429 1431 add_x86_feature(featureset, X86FSET_RDRAND);
1430 1432
1431 1433 /*
1432 1434 * Only need it first time, rest of the cpus would follow suit.
1433 1435 * we only capture this for the bootcpu.
1434 1436 */
1435 1437 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1436 1438 add_x86_feature(featureset, X86FSET_CLFSH);
1437 1439 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
1438 1440 }
1439 1441 if (is_x86_feature(featureset, X86FSET_PAE))
1440 1442 cpi->cpi_pabits = 36;
1441 1443
1442 1444 /*
1443 1445 * Hyperthreading configuration is slightly tricky on Intel
1444 1446 * and pure clones, and even trickier on AMD.
1445 1447 *
1446 1448 * (AMD chose to set the HTT bit on their CMP processors,
1447 1449 * even though they're not actually hyperthreaded. Thus it
1448 1450 * takes a bit more work to figure out what's really going
1449 1451 * on ... see the handling of the CMP_LGCY bit below)
1450 1452 */
1451 1453 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
1452 1454 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
1453 1455 if (cpi->cpi_ncpu_per_chip > 1)
1454 1456 add_x86_feature(featureset, X86FSET_HTT);
1455 1457 } else {
1456 1458 cpi->cpi_ncpu_per_chip = 1;
1457 1459 }
1458 1460
1459 1461 /*
1460 1462 * Work on the "extended" feature information, doing
1461 1463 * some basic initialization for cpuid_pass2()
1462 1464 */
1463 1465 xcpuid = 0;
1464 1466 switch (cpi->cpi_vendor) {
1465 1467 case X86_VENDOR_Intel:
1466 1468 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
1467 1469 xcpuid++;
1468 1470 break;
1469 1471 case X86_VENDOR_AMD:
1470 1472 if (cpi->cpi_family > 5 ||
1471 1473 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
1472 1474 xcpuid++;
1473 1475 break;
1474 1476 case X86_VENDOR_Cyrix:
1475 1477 /*
1476 1478 * Only these Cyrix CPUs are -known- to support
1477 1479 * extended cpuid operations.
1478 1480 */
1479 1481 if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1480 1482 x86_type == X86_TYPE_CYRIX_GXm)
1481 1483 xcpuid++;
1482 1484 break;
1483 1485 case X86_VENDOR_Centaur:
1484 1486 case X86_VENDOR_TM:
1485 1487 default:
1486 1488 xcpuid++;
1487 1489 break;
1488 1490 }
1489 1491
1490 1492 if (xcpuid) {
1491 1493 cp = &cpi->cpi_extd[0];
1492 1494 cp->cp_eax = 0x80000000;
1493 1495 cpi->cpi_xmaxeax = __cpuid_insn(cp);
1494 1496 }
1495 1497
1496 1498 if (cpi->cpi_xmaxeax & 0x80000000) {
1497 1499
1498 1500 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1499 1501 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1500 1502
1501 1503 switch (cpi->cpi_vendor) {
1502 1504 case X86_VENDOR_Intel:
1503 1505 case X86_VENDOR_AMD:
1504 1506 if (cpi->cpi_xmaxeax < 0x80000001)
1505 1507 break;
1506 1508 cp = &cpi->cpi_extd[1];
1507 1509 cp->cp_eax = 0x80000001;
1508 1510 (void) __cpuid_insn(cp);
1509 1511
1510 1512 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1511 1513 cpi->cpi_family == 5 &&
1512 1514 cpi->cpi_model == 6 &&
1513 1515 cpi->cpi_step == 6) {
1514 1516 /*
1515 1517 * K6 model 6 uses bit 10 to indicate SYSC
1516 1518 * Later models use bit 11. Fix it here.
1517 1519 */
1518 1520 if (cp->cp_edx & 0x400) {
1519 1521 cp->cp_edx &= ~0x400;
1520 1522 cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1521 1523 }
1522 1524 }
1523 1525
1524 1526 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1525 1527
1526 1528 /*
1527 1529 * Compute the additions to the kernel's feature word.
1528 1530 */
1529 1531 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
1530 1532 add_x86_feature(featureset, X86FSET_NX);
1531 1533 }
1532 1534
1533 1535 /*
1534 1536 * Regardless whether or not we boot 64-bit,
1535 1537 * we should have a way to identify whether
1536 1538 * the CPU is capable of running 64-bit.
1537 1539 */
1538 1540 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
1539 1541 add_x86_feature(featureset, X86FSET_64);
1540 1542 }
1541 1543
1542 1544 #if defined(__amd64)
1543 1545 /* 1 GB large page - enable only for 64 bit kernel */
1544 1546 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
1545 1547 add_x86_feature(featureset, X86FSET_1GPG);
1546 1548 }
1547 1549 #endif
1548 1550
1549 1551 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1550 1552 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1551 1553 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
1552 1554 add_x86_feature(featureset, X86FSET_SSE4A);
1553 1555 }
1554 1556
1555 1557 /*
1556 1558 * If both the HTT and CMP_LGCY bits are set,
1557 1559 * then we're not actually HyperThreaded. Read
1558 1560 * "AMD CPUID Specification" for more details.
1559 1561 */
1560 1562 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1561 1563 is_x86_feature(featureset, X86FSET_HTT) &&
1562 1564 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1563 1565 remove_x86_feature(featureset, X86FSET_HTT);
1564 1566 add_x86_feature(featureset, X86FSET_CMP);
1565 1567 }
1566 1568 #if defined(__amd64)
1567 1569 /*
1568 1570 * It's really tricky to support syscall/sysret in
1569 1571 * the i386 kernel; we rely on sysenter/sysexit
1570 1572 * instead. In the amd64 kernel, things are -way-
1571 1573 * better.
1572 1574 */
1573 1575 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1574 1576 add_x86_feature(featureset, X86FSET_ASYSC);
1575 1577 }
1576 1578
1577 1579 /*
1578 1580 * While we're thinking about system calls, note
1579 1581 * that AMD processors don't support sysenter
1580 1582 * in long mode at all, so don't try to program them.
1581 1583 */
1582 1584 if (x86_vendor == X86_VENDOR_AMD) {
1583 1585 remove_x86_feature(featureset, X86FSET_SEP);
1584 1586 }
1585 1587 #endif
1586 1588 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1587 1589 add_x86_feature(featureset, X86FSET_TSCP);
1588 1590 }
1589 1591
1590 1592 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1591 1593 add_x86_feature(featureset, X86FSET_SVM);
1592 1594 }
1593 1595
1594 1596 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1595 1597 add_x86_feature(featureset, X86FSET_TOPOEXT);
1596 1598 }
1597 1599 break;
1598 1600 default:
1599 1601 break;
1600 1602 }
1601 1603
1602 1604 /*
1603 1605 * Get CPUID data about processor cores and hyperthreads.
1604 1606 */
1605 1607 switch (cpi->cpi_vendor) {
1606 1608 case X86_VENDOR_Intel:
1607 1609 if (cpi->cpi_maxeax >= 4) {
1608 1610 cp = &cpi->cpi_std[4];
1609 1611 cp->cp_eax = 4;
1610 1612 cp->cp_ecx = 0;
1611 1613 (void) __cpuid_insn(cp);
1612 1614 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1613 1615 }
1614 1616 /*FALLTHROUGH*/
1615 1617 case X86_VENDOR_AMD:
1616 1618 if (cpi->cpi_xmaxeax < 0x80000008)
1617 1619 break;
1618 1620 cp = &cpi->cpi_extd[8];
1619 1621 cp->cp_eax = 0x80000008;
1620 1622 (void) __cpuid_insn(cp);
1621 1623 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1622 1624
1623 1625 /*
1624 1626 * Virtual and physical address limits from
1625 1627 * cpuid override previously guessed values.
1626 1628 */
1627 1629 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1628 1630 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1629 1631 break;
1630 1632 default:
1631 1633 break;
1632 1634 }
1633 1635
1634 1636 /*
1635 1637 * Derive the number of cores per chip
1636 1638 */
1637 1639 switch (cpi->cpi_vendor) {
1638 1640 case X86_VENDOR_Intel:
1639 1641 if (cpi->cpi_maxeax < 4) {
1640 1642 cpi->cpi_ncore_per_chip = 1;
1641 1643 break;
1642 1644 } else {
1643 1645 cpi->cpi_ncore_per_chip =
1644 1646 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1645 1647 }
1646 1648 break;
1647 1649 case X86_VENDOR_AMD:
1648 1650 if (cpi->cpi_xmaxeax < 0x80000008) {
1649 1651 cpi->cpi_ncore_per_chip = 1;
1650 1652 break;
1651 1653 } else {
1652 1654 /*
1653 1655 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1654 1656 * 1 less than the number of physical cores on
1655 1657 * the chip. In family 0x10 this value can
1656 1658 * be affected by "downcoring" - it reflects
1657 1659 * 1 less than the number of cores actually
1658 1660 * enabled on this node.
1659 1661 */
1660 1662 cpi->cpi_ncore_per_chip =
1661 1663 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1662 1664 }
1663 1665 break;
1664 1666 default:
1665 1667 cpi->cpi_ncore_per_chip = 1;
1666 1668 break;
1667 1669 }
1668 1670
1669 1671 /*
1670 1672 * Get CPUID data about TSC Invariance in Deep C-State.
1671 1673 */
1672 1674 switch (cpi->cpi_vendor) {
1673 1675 case X86_VENDOR_Intel:
1674 1676 if (cpi->cpi_maxeax >= 7) {
1675 1677 cp = &cpi->cpi_extd[7];
1676 1678 cp->cp_eax = 0x80000007;
1677 1679 cp->cp_ecx = 0;
1678 1680 (void) __cpuid_insn(cp);
1679 1681 }
1680 1682 break;
1681 1683 default:
1682 1684 break;
1683 1685 }
1684 1686 } else {
1685 1687 cpi->cpi_ncore_per_chip = 1;
1686 1688 }
1687 1689
1688 1690 /*
1689 1691 * If more than one core, then this processor is CMP.
1690 1692 */
1691 1693 if (cpi->cpi_ncore_per_chip > 1) {
1692 1694 add_x86_feature(featureset, X86FSET_CMP);
1693 1695 }
1694 1696
1695 1697 /*
1696 1698 * If the number of cores is the same as the number
1697 1699 * of CPUs, then we cannot have HyperThreading.
1698 1700 */
1699 1701 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1700 1702 remove_x86_feature(featureset, X86FSET_HTT);
1701 1703 }
1702 1704
1703 1705 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1704 1706 cpi->cpi_procnodes_per_pkg = 1;
1705 1707 cpi->cpi_cores_per_compunit = 1;
1706 1708 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1707 1709 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1708 1710 /*
1709 1711 * Single-core single-threaded processors.
1710 1712 */
1711 1713 cpi->cpi_chipid = -1;
1712 1714 cpi->cpi_clogid = 0;
1713 1715 cpi->cpi_coreid = cpu->cpu_id;
1714 1716 cpi->cpi_pkgcoreid = 0;
1715 1717 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1716 1718 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1717 1719 else
1718 1720 cpi->cpi_procnodeid = cpi->cpi_chipid;
1719 1721 } else if (cpi->cpi_ncpu_per_chip > 1) {
1720 1722 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1721 1723 cpuid_intel_getids(cpu, featureset);
1722 1724 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1723 1725 cpuid_amd_getids(cpu);
1724 1726 else {
1725 1727 /*
1726 1728 * All other processors are currently
1727 1729 * assumed to have single cores.
1728 1730 */
1729 1731 cpi->cpi_coreid = cpi->cpi_chipid;
1730 1732 cpi->cpi_pkgcoreid = 0;
1731 1733 cpi->cpi_procnodeid = cpi->cpi_chipid;
1732 1734 cpi->cpi_compunitid = cpi->cpi_chipid;
1733 1735 }
1734 1736 }
1735 1737
1736 1738 /*
1737 1739 * Synthesize chip "revision" and socket type
1738 1740 */
1739 1741 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1740 1742 cpi->cpi_model, cpi->cpi_step);
1741 1743 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1742 1744 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1743 1745 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1744 1746 cpi->cpi_model, cpi->cpi_step);
1745 1747
1746 1748 pass1_done:
1747 1749 cpi->cpi_pass = 1;
1748 1750 }
1749 1751
1750 1752 /*
1751 1753 * Make copies of the cpuid table entries we depend on, in
1752 1754 * part for ease of parsing now, in part so that we have only
1753 1755 * one place to correct any of it, in part for ease of
1754 1756 * later export to userland, and in part so we can look at
1755 1757 * this stuff in a crash dump.
1756 1758 */
1757 1759
1758 1760 /*ARGSUSED*/
1759 1761 void
1760 1762 cpuid_pass2(cpu_t *cpu)
1761 1763 {
1762 1764 uint_t n, nmax;
1763 1765 int i;
1764 1766 struct cpuid_regs *cp;
1765 1767 uint8_t *dp;
1766 1768 uint32_t *iptr;
1767 1769 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1768 1770
1769 1771 ASSERT(cpi->cpi_pass == 1);
1770 1772
1771 1773 if (cpi->cpi_maxeax < 1)
1772 1774 goto pass2_done;
1773 1775
1774 1776 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1775 1777 nmax = NMAX_CPI_STD;
1776 1778 /*
1777 1779 * (We already handled n == 0 and n == 1 in pass 1)
1778 1780 */
1779 1781 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1780 1782 cp->cp_eax = n;
1781 1783
1782 1784 /*
1783 1785 * CPUID function 4 expects %ecx to be initialized
1784 1786 * with an index which indicates which cache to return
1785 1787 * information about. The OS is expected to call function 4
1786 1788 * with %ecx set to 0, 1, 2, ... until it returns with
1787 1789 * EAX[4:0] set to 0, which indicates there are no more
1788 1790 * caches.
1789 1791 *
1790 1792 * Here, populate cpi_std[4] with the information returned by
1791 1793 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1792 1794 * when dynamic memory allocation becomes available.
1793 1795 *
1794 1796 * Note: we need to explicitly initialize %ecx here, since
1795 1797 * function 4 may have been previously invoked.
1796 1798 */
1797 1799 if (n == 4)
1798 1800 cp->cp_ecx = 0;
1799 1801
1800 1802 (void) __cpuid_insn(cp);
1801 1803 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1802 1804 switch (n) {
1803 1805 case 2:
1804 1806 /*
1805 1807 * "the lower 8 bits of the %eax register
1806 1808 * contain a value that identifies the number
1807 1809 * of times the cpuid [instruction] has to be
1808 1810 * executed to obtain a complete image of the
1809 1811 * processor's caching systems."
1810 1812 *
1811 1813 * How *do* they make this stuff up?
1812 1814 */
1813 1815 cpi->cpi_ncache = sizeof (*cp) *
1814 1816 BITX(cp->cp_eax, 7, 0);
1815 1817 if (cpi->cpi_ncache == 0)
1816 1818 break;
1817 1819 cpi->cpi_ncache--; /* skip count byte */
1818 1820
1819 1821 /*
1820 1822 * Well, for now, rather than attempt to implement
1821 1823 * this slightly dubious algorithm, we just look
1822 1824 * at the first 15 ..
1823 1825 */
1824 1826 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1825 1827 cpi->cpi_ncache = sizeof (*cp) - 1;
1826 1828
1827 1829 dp = cpi->cpi_cacheinfo;
1828 1830 if (BITX(cp->cp_eax, 31, 31) == 0) {
1829 1831 uint8_t *p = (void *)&cp->cp_eax;
1830 1832 for (i = 1; i < 4; i++)
1831 1833 if (p[i] != 0)
1832 1834 *dp++ = p[i];
1833 1835 }
1834 1836 if (BITX(cp->cp_ebx, 31, 31) == 0) {
1835 1837 uint8_t *p = (void *)&cp->cp_ebx;
1836 1838 for (i = 0; i < 4; i++)
1837 1839 if (p[i] != 0)
1838 1840 *dp++ = p[i];
1839 1841 }
1840 1842 if (BITX(cp->cp_ecx, 31, 31) == 0) {
1841 1843 uint8_t *p = (void *)&cp->cp_ecx;
1842 1844 for (i = 0; i < 4; i++)
1843 1845 if (p[i] != 0)
1844 1846 *dp++ = p[i];
1845 1847 }
1846 1848 if (BITX(cp->cp_edx, 31, 31) == 0) {
1847 1849 uint8_t *p = (void *)&cp->cp_edx;
1848 1850 for (i = 0; i < 4; i++)
1849 1851 if (p[i] != 0)
1850 1852 *dp++ = p[i];
1851 1853 }
1852 1854 break;
1853 1855
1854 1856 case 3: /* Processor serial number, if PSN supported */
1855 1857 break;
1856 1858
1857 1859 case 4: /* Deterministic cache parameters */
1858 1860 break;
1859 1861
1860 1862 case 5: /* Monitor/Mwait parameters */
1861 1863 {
1862 1864 size_t mwait_size;
1863 1865
1864 1866 /*
1865 1867 * check cpi_mwait.support which was set in cpuid_pass1
1866 1868 */
1867 1869 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
1868 1870 break;
1869 1871
1870 1872 /*
1871 1873 * Protect ourself from insane mwait line size.
1872 1874 * Workaround for incomplete hardware emulator(s).
1873 1875 */
1874 1876 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
1875 1877 if (mwait_size < sizeof (uint32_t) ||
1876 1878 !ISP2(mwait_size)) {
1877 1879 #if DEBUG
1878 1880 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
1879 1881 "size %ld", cpu->cpu_id, (long)mwait_size);
1880 1882 #endif
1881 1883 break;
1882 1884 }
1883 1885
1884 1886 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
1885 1887 cpi->cpi_mwait.mon_max = mwait_size;
1886 1888 if (MWAIT_EXTENSION(cpi)) {
1887 1889 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
1888 1890 if (MWAIT_INT_ENABLE(cpi))
1889 1891 cpi->cpi_mwait.support |=
1890 1892 MWAIT_ECX_INT_ENABLE;
1891 1893 }
1892 1894 break;
1893 1895 }
1894 1896 default:
1895 1897 break;
1896 1898 }
1897 1899 }
1898 1900
1899 1901 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
1900 1902 struct cpuid_regs regs;
1901 1903
1902 1904 cp = ®s;
1903 1905 cp->cp_eax = 0xB;
1904 1906 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1905 1907
1906 1908 (void) __cpuid_insn(cp);
1907 1909
1908 1910 /*
1909 1911 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
1910 1912 * indicates that the extended topology enumeration leaf is
1911 1913 * available.
1912 1914 */
1913 1915 if (cp->cp_ebx) {
1914 1916 uint32_t x2apic_id;
1915 1917 uint_t coreid_shift = 0;
1916 1918 uint_t ncpu_per_core = 1;
1917 1919 uint_t chipid_shift = 0;
1918 1920 uint_t ncpu_per_chip = 1;
1919 1921 uint_t i;
1920 1922 uint_t level;
1921 1923
1922 1924 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
1923 1925 cp->cp_eax = 0xB;
1924 1926 cp->cp_ecx = i;
1925 1927
1926 1928 (void) __cpuid_insn(cp);
1927 1929 level = CPI_CPU_LEVEL_TYPE(cp);
1928 1930
1929 1931 if (level == 1) {
1930 1932 x2apic_id = cp->cp_edx;
1931 1933 coreid_shift = BITX(cp->cp_eax, 4, 0);
1932 1934 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
1933 1935 } else if (level == 2) {
1934 1936 x2apic_id = cp->cp_edx;
1935 1937 chipid_shift = BITX(cp->cp_eax, 4, 0);
1936 1938 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
1937 1939 }
1938 1940 }
1939 1941
1940 1942 cpi->cpi_apicid = x2apic_id;
1941 1943 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
1942 1944 cpi->cpi_ncore_per_chip = ncpu_per_chip /
1943 1945 ncpu_per_core;
1944 1946 cpi->cpi_chipid = x2apic_id >> chipid_shift;
1945 1947 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
1946 1948 cpi->cpi_coreid = x2apic_id >> coreid_shift;
1947 1949 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
1948 1950 }
1949 1951
1950 1952 /* Make cp NULL so that we don't stumble on others */
1951 1953 cp = NULL;
1952 1954 }
1953 1955
1954 1956 /*
1955 1957 * XSAVE enumeration
1956 1958 */
1957 1959 if (cpi->cpi_maxeax >= 0xD) {
1958 1960 struct cpuid_regs regs;
1959 1961 boolean_t cpuid_d_valid = B_TRUE;
1960 1962
1961 1963 cp = ®s;
1962 1964 cp->cp_eax = 0xD;
1963 1965 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1964 1966
1965 1967 (void) __cpuid_insn(cp);
1966 1968
1967 1969 /*
1968 1970 * Sanity checks for debug
1969 1971 */
1970 1972 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 ||
1971 1973 (cp->cp_eax & XFEATURE_SSE) == 0) {
1972 1974 cpuid_d_valid = B_FALSE;
1973 1975 }
1974 1976
1975 1977 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
1976 1978 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
1977 1979 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
1978 1980
1979 1981 /*
1980 1982 * If the hw supports AVX, get the size and offset in the save
1981 1983 * area for the ymm state.
1982 1984 */
1983 1985 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
1984 1986 cp->cp_eax = 0xD;
1985 1987 cp->cp_ecx = 2;
1986 1988 cp->cp_edx = cp->cp_ebx = 0;
1987 1989
1988 1990 (void) __cpuid_insn(cp);
1989 1991
1990 1992 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET ||
1991 1993 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
1992 1994 cpuid_d_valid = B_FALSE;
1993 1995 }
1994 1996
1995 1997 cpi->cpi_xsave.ymm_size = cp->cp_eax;
1996 1998 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
1997 1999 }
1998 2000
1999 2001 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
2000 2002 xsave_state_size = 0;
2001 2003 } else if (cpuid_d_valid) {
2002 2004 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
2003 2005 } else {
2004 2006 /* Broken CPUID 0xD, probably in HVM */
2005 2007 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
2006 2008 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
2007 2009 ", ymm_size = %d, ymm_offset = %d\n",
2008 2010 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
2009 2011 cpi->cpi_xsave.xsav_hw_features_high,
2010 2012 (int)cpi->cpi_xsave.xsav_max_size,
2011 2013 (int)cpi->cpi_xsave.ymm_size,
2012 2014 (int)cpi->cpi_xsave.ymm_offset);
2013 2015
2014 2016 if (xsave_state_size != 0) {
2015 2017 /*
2016 2018 * This must be a non-boot CPU. We cannot
2017 2019 * continue, because boot cpu has already
2018 2020 * enabled XSAVE.
2019 2021 */
2020 2022 ASSERT(cpu->cpu_id != 0);
2021 2023 cmn_err(CE_PANIC, "cpu%d: we have already "
2022 2024 "enabled XSAVE on boot cpu, cannot "
2023 2025 "continue.", cpu->cpu_id);
2024 2026 } else {
2025 2027 /*
2026 2028 * If we reached here on the boot CPU, it's also
2027 2029 * almost certain that we'll reach here on the
2028 2030 * non-boot CPUs. When we're here on a boot CPU
2029 2031 * we should disable the feature, on a non-boot
2030 2032 * CPU we need to confirm that we have.
2031 2033 */
2032 2034 if (cpu->cpu_id == 0) {
2033 2035 remove_x86_feature(x86_featureset,
2034 2036 X86FSET_XSAVE);
2035 2037 remove_x86_feature(x86_featureset,
2036 2038 X86FSET_AVX);
2037 2039 remove_x86_feature(x86_featureset,
2038 2040 X86FSET_F16C);
2039 2041 remove_x86_feature(x86_featureset,
2040 2042 X86FSET_BMI1);
2041 2043 remove_x86_feature(x86_featureset,
2042 2044 X86FSET_BMI2);
2043 2045 remove_x86_feature(x86_featureset,
2044 2046 X86FSET_FMA);
2045 2047 remove_x86_feature(x86_featureset,
2046 2048 X86FSET_AVX2);
2047 2049 CPI_FEATURES_ECX(cpi) &=
2048 2050 ~CPUID_INTC_ECX_XSAVE;
2049 2051 CPI_FEATURES_ECX(cpi) &=
2050 2052 ~CPUID_INTC_ECX_AVX;
2051 2053 CPI_FEATURES_ECX(cpi) &=
2052 2054 ~CPUID_INTC_ECX_F16C;
2053 2055 CPI_FEATURES_ECX(cpi) &=
2054 2056 ~CPUID_INTC_ECX_FMA;
2055 2057 CPI_FEATURES_7_0_EBX(cpi) &=
2056 2058 ~CPUID_INTC_EBX_7_0_BMI1;
2057 2059 CPI_FEATURES_7_0_EBX(cpi) &=
2058 2060 ~CPUID_INTC_EBX_7_0_BMI2;
2059 2061 CPI_FEATURES_7_0_EBX(cpi) &=
2060 2062 ~CPUID_INTC_EBX_7_0_AVX2;
2061 2063 xsave_force_disable = B_TRUE;
2062 2064 } else {
2063 2065 VERIFY(is_x86_feature(x86_featureset,
2064 2066 X86FSET_XSAVE) == B_FALSE);
2065 2067 }
2066 2068 }
2067 2069 }
2068 2070 }
2069 2071
2070 2072
2071 2073 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
2072 2074 goto pass2_done;
2073 2075
2074 2076 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
2075 2077 nmax = NMAX_CPI_EXTD;
2076 2078 /*
2077 2079 * Copy the extended properties, fixing them as we go.
2078 2080 * (We already handled n == 0 and n == 1 in pass 1)
2079 2081 */
2080 2082 iptr = (void *)cpi->cpi_brandstr;
2081 2083 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
2082 2084 cp->cp_eax = 0x80000000 + n;
2083 2085 (void) __cpuid_insn(cp);
2084 2086 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
2085 2087 switch (n) {
2086 2088 case 2:
2087 2089 case 3:
2088 2090 case 4:
2089 2091 /*
2090 2092 * Extract the brand string
2091 2093 */
2092 2094 *iptr++ = cp->cp_eax;
2093 2095 *iptr++ = cp->cp_ebx;
2094 2096 *iptr++ = cp->cp_ecx;
2095 2097 *iptr++ = cp->cp_edx;
2096 2098 break;
2097 2099 case 5:
2098 2100 switch (cpi->cpi_vendor) {
2099 2101 case X86_VENDOR_AMD:
2100 2102 /*
2101 2103 * The Athlon and Duron were the first
2102 2104 * parts to report the sizes of the
2103 2105 * TLB for large pages. Before then,
2104 2106 * we don't trust the data.
2105 2107 */
2106 2108 if (cpi->cpi_family < 6 ||
2107 2109 (cpi->cpi_family == 6 &&
2108 2110 cpi->cpi_model < 1))
2109 2111 cp->cp_eax = 0;
2110 2112 break;
2111 2113 default:
2112 2114 break;
2113 2115 }
2114 2116 break;
2115 2117 case 6:
2116 2118 switch (cpi->cpi_vendor) {
2117 2119 case X86_VENDOR_AMD:
2118 2120 /*
2119 2121 * The Athlon and Duron were the first
2120 2122 * AMD parts with L2 TLB's.
2121 2123 * Before then, don't trust the data.
2122 2124 */
2123 2125 if (cpi->cpi_family < 6 ||
2124 2126 cpi->cpi_family == 6 &&
2125 2127 cpi->cpi_model < 1)
2126 2128 cp->cp_eax = cp->cp_ebx = 0;
2127 2129 /*
2128 2130 * AMD Duron rev A0 reports L2
2129 2131 * cache size incorrectly as 1K
2130 2132 * when it is really 64K
2131 2133 */
2132 2134 if (cpi->cpi_family == 6 &&
2133 2135 cpi->cpi_model == 3 &&
2134 2136 cpi->cpi_step == 0) {
2135 2137 cp->cp_ecx &= 0xffff;
2136 2138 cp->cp_ecx |= 0x400000;
2137 2139 }
2138 2140 break;
2139 2141 case X86_VENDOR_Cyrix: /* VIA C3 */
2140 2142 /*
2141 2143 * VIA C3 processors are a bit messed
2142 2144 * up w.r.t. encoding cache sizes in %ecx
2143 2145 */
2144 2146 if (cpi->cpi_family != 6)
2145 2147 break;
2146 2148 /*
2147 2149 * model 7 and 8 were incorrectly encoded
2148 2150 *
2149 2151 * xxx is model 8 really broken?
2150 2152 */
2151 2153 if (cpi->cpi_model == 7 ||
2152 2154 cpi->cpi_model == 8)
2153 2155 cp->cp_ecx =
2154 2156 BITX(cp->cp_ecx, 31, 24) << 16 |
2155 2157 BITX(cp->cp_ecx, 23, 16) << 12 |
2156 2158 BITX(cp->cp_ecx, 15, 8) << 8 |
2157 2159 BITX(cp->cp_ecx, 7, 0);
2158 2160 /*
2159 2161 * model 9 stepping 1 has wrong associativity
2160 2162 */
2161 2163 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
2162 2164 cp->cp_ecx |= 8 << 12;
2163 2165 break;
2164 2166 case X86_VENDOR_Intel:
2165 2167 /*
2166 2168 * Extended L2 Cache features function.
2167 2169 * First appeared on Prescott.
2168 2170 */
2169 2171 default:
2170 2172 break;
2171 2173 }
2172 2174 break;
2173 2175 default:
2174 2176 break;
2175 2177 }
2176 2178 }
2177 2179
2178 2180 pass2_done:
2179 2181 cpi->cpi_pass = 2;
2180 2182 }
2181 2183
2182 2184 static const char *
2183 2185 intel_cpubrand(const struct cpuid_info *cpi)
2184 2186 {
2185 2187 int i;
2186 2188
2187 2189 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2188 2190 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2189 2191 return ("i486");
2190 2192
2191 2193 switch (cpi->cpi_family) {
2192 2194 case 5:
2193 2195 return ("Intel Pentium(r)");
2194 2196 case 6:
2195 2197 switch (cpi->cpi_model) {
2196 2198 uint_t celeron, xeon;
2197 2199 const struct cpuid_regs *cp;
2198 2200 case 0:
2199 2201 case 1:
2200 2202 case 2:
2201 2203 return ("Intel Pentium(r) Pro");
2202 2204 case 3:
2203 2205 case 4:
2204 2206 return ("Intel Pentium(r) II");
2205 2207 case 6:
2206 2208 return ("Intel Celeron(r)");
2207 2209 case 5:
2208 2210 case 7:
2209 2211 celeron = xeon = 0;
2210 2212 cp = &cpi->cpi_std[2]; /* cache info */
2211 2213
2212 2214 for (i = 1; i < 4; i++) {
2213 2215 uint_t tmp;
2214 2216
2215 2217 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
2216 2218 if (tmp == 0x40)
2217 2219 celeron++;
2218 2220 if (tmp >= 0x44 && tmp <= 0x45)
2219 2221 xeon++;
2220 2222 }
2221 2223
2222 2224 for (i = 0; i < 2; i++) {
2223 2225 uint_t tmp;
2224 2226
2225 2227 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
2226 2228 if (tmp == 0x40)
2227 2229 celeron++;
2228 2230 else if (tmp >= 0x44 && tmp <= 0x45)
2229 2231 xeon++;
2230 2232 }
2231 2233
2232 2234 for (i = 0; i < 4; i++) {
2233 2235 uint_t tmp;
2234 2236
2235 2237 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
2236 2238 if (tmp == 0x40)
2237 2239 celeron++;
2238 2240 else if (tmp >= 0x44 && tmp <= 0x45)
2239 2241 xeon++;
2240 2242 }
2241 2243
2242 2244 for (i = 0; i < 4; i++) {
2243 2245 uint_t tmp;
2244 2246
2245 2247 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
2246 2248 if (tmp == 0x40)
2247 2249 celeron++;
2248 2250 else if (tmp >= 0x44 && tmp <= 0x45)
2249 2251 xeon++;
2250 2252 }
2251 2253
2252 2254 if (celeron)
2253 2255 return ("Intel Celeron(r)");
2254 2256 if (xeon)
2255 2257 return (cpi->cpi_model == 5 ?
2256 2258 "Intel Pentium(r) II Xeon(tm)" :
2257 2259 "Intel Pentium(r) III Xeon(tm)");
2258 2260 return (cpi->cpi_model == 5 ?
2259 2261 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
2260 2262 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
2261 2263 default:
2262 2264 break;
2263 2265 }
2264 2266 default:
2265 2267 break;
2266 2268 }
2267 2269
2268 2270 /* BrandID is present if the field is nonzero */
2269 2271 if (cpi->cpi_brandid != 0) {
2270 2272 static const struct {
2271 2273 uint_t bt_bid;
2272 2274 const char *bt_str;
2273 2275 } brand_tbl[] = {
2274 2276 { 0x1, "Intel(r) Celeron(r)" },
2275 2277 { 0x2, "Intel(r) Pentium(r) III" },
2276 2278 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
2277 2279 { 0x4, "Intel(r) Pentium(r) III" },
2278 2280 { 0x6, "Mobile Intel(r) Pentium(r) III" },
2279 2281 { 0x7, "Mobile Intel(r) Celeron(r)" },
2280 2282 { 0x8, "Intel(r) Pentium(r) 4" },
2281 2283 { 0x9, "Intel(r) Pentium(r) 4" },
2282 2284 { 0xa, "Intel(r) Celeron(r)" },
2283 2285 { 0xb, "Intel(r) Xeon(tm)" },
2284 2286 { 0xc, "Intel(r) Xeon(tm) MP" },
2285 2287 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
2286 2288 { 0xf, "Mobile Intel(r) Celeron(r)" },
2287 2289 { 0x11, "Mobile Genuine Intel(r)" },
2288 2290 { 0x12, "Intel(r) Celeron(r) M" },
2289 2291 { 0x13, "Mobile Intel(r) Celeron(r)" },
2290 2292 { 0x14, "Intel(r) Celeron(r)" },
2291 2293 { 0x15, "Mobile Genuine Intel(r)" },
2292 2294 { 0x16, "Intel(r) Pentium(r) M" },
2293 2295 { 0x17, "Mobile Intel(r) Celeron(r)" }
2294 2296 };
2295 2297 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
2296 2298 uint_t sgn;
2297 2299
2298 2300 sgn = (cpi->cpi_family << 8) |
2299 2301 (cpi->cpi_model << 4) | cpi->cpi_step;
2300 2302
2301 2303 for (i = 0; i < btblmax; i++)
2302 2304 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
2303 2305 break;
2304 2306 if (i < btblmax) {
2305 2307 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
2306 2308 return ("Intel(r) Celeron(r)");
2307 2309 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
2308 2310 return ("Intel(r) Xeon(tm) MP");
2309 2311 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
2310 2312 return ("Intel(r) Xeon(tm)");
2311 2313 return (brand_tbl[i].bt_str);
2312 2314 }
2313 2315 }
2314 2316
2315 2317 return (NULL);
2316 2318 }
2317 2319
2318 2320 static const char *
2319 2321 amd_cpubrand(const struct cpuid_info *cpi)
2320 2322 {
2321 2323 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2322 2324 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2323 2325 return ("i486 compatible");
2324 2326
2325 2327 switch (cpi->cpi_family) {
2326 2328 case 5:
2327 2329 switch (cpi->cpi_model) {
2328 2330 case 0:
2329 2331 case 1:
2330 2332 case 2:
2331 2333 case 3:
2332 2334 case 4:
2333 2335 case 5:
2334 2336 return ("AMD-K5(r)");
2335 2337 case 6:
2336 2338 case 7:
2337 2339 return ("AMD-K6(r)");
2338 2340 case 8:
2339 2341 return ("AMD-K6(r)-2");
2340 2342 case 9:
2341 2343 return ("AMD-K6(r)-III");
2342 2344 default:
2343 2345 return ("AMD (family 5)");
2344 2346 }
2345 2347 case 6:
2346 2348 switch (cpi->cpi_model) {
2347 2349 case 1:
2348 2350 return ("AMD-K7(tm)");
2349 2351 case 0:
2350 2352 case 2:
2351 2353 case 4:
2352 2354 return ("AMD Athlon(tm)");
2353 2355 case 3:
2354 2356 case 7:
2355 2357 return ("AMD Duron(tm)");
2356 2358 case 6:
2357 2359 case 8:
2358 2360 case 10:
2359 2361 /*
2360 2362 * Use the L2 cache size to distinguish
2361 2363 */
2362 2364 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
2363 2365 "AMD Athlon(tm)" : "AMD Duron(tm)");
2364 2366 default:
2365 2367 return ("AMD (family 6)");
2366 2368 }
2367 2369 default:
2368 2370 break;
2369 2371 }
2370 2372
2371 2373 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
2372 2374 cpi->cpi_brandid != 0) {
2373 2375 switch (BITX(cpi->cpi_brandid, 7, 5)) {
2374 2376 case 3:
2375 2377 return ("AMD Opteron(tm) UP 1xx");
2376 2378 case 4:
2377 2379 return ("AMD Opteron(tm) DP 2xx");
2378 2380 case 5:
2379 2381 return ("AMD Opteron(tm) MP 8xx");
2380 2382 default:
2381 2383 return ("AMD Opteron(tm)");
2382 2384 }
2383 2385 }
2384 2386
2385 2387 return (NULL);
2386 2388 }
2387 2389
2388 2390 static const char *
2389 2391 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
2390 2392 {
2391 2393 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2392 2394 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
2393 2395 type == X86_TYPE_CYRIX_486)
2394 2396 return ("i486 compatible");
2395 2397
2396 2398 switch (type) {
2397 2399 case X86_TYPE_CYRIX_6x86:
2398 2400 return ("Cyrix 6x86");
2399 2401 case X86_TYPE_CYRIX_6x86L:
2400 2402 return ("Cyrix 6x86L");
2401 2403 case X86_TYPE_CYRIX_6x86MX:
2402 2404 return ("Cyrix 6x86MX");
2403 2405 case X86_TYPE_CYRIX_GXm:
2404 2406 return ("Cyrix GXm");
2405 2407 case X86_TYPE_CYRIX_MediaGX:
2406 2408 return ("Cyrix MediaGX");
2407 2409 case X86_TYPE_CYRIX_MII:
2408 2410 return ("Cyrix M2");
2409 2411 case X86_TYPE_VIA_CYRIX_III:
2410 2412 return ("VIA Cyrix M3");
2411 2413 default:
2412 2414 /*
2413 2415 * Have another wild guess ..
2414 2416 */
2415 2417 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
2416 2418 return ("Cyrix 5x86");
2417 2419 else if (cpi->cpi_family == 5) {
2418 2420 switch (cpi->cpi_model) {
2419 2421 case 2:
2420 2422 return ("Cyrix 6x86"); /* Cyrix M1 */
2421 2423 case 4:
2422 2424 return ("Cyrix MediaGX");
2423 2425 default:
2424 2426 break;
2425 2427 }
2426 2428 } else if (cpi->cpi_family == 6) {
2427 2429 switch (cpi->cpi_model) {
2428 2430 case 0:
2429 2431 return ("Cyrix 6x86MX"); /* Cyrix M2? */
2430 2432 case 5:
2431 2433 case 6:
2432 2434 case 7:
2433 2435 case 8:
2434 2436 case 9:
2435 2437 return ("VIA C3");
2436 2438 default:
2437 2439 break;
2438 2440 }
2439 2441 }
2440 2442 break;
2441 2443 }
2442 2444 return (NULL);
2443 2445 }
2444 2446
2445 2447 /*
2446 2448 * This only gets called in the case that the CPU extended
2447 2449 * feature brand string (0x80000002, 0x80000003, 0x80000004)
2448 2450 * aren't available, or contain null bytes for some reason.
2449 2451 */
2450 2452 static void
2451 2453 fabricate_brandstr(struct cpuid_info *cpi)
2452 2454 {
2453 2455 const char *brand = NULL;
2454 2456
2455 2457 switch (cpi->cpi_vendor) {
2456 2458 case X86_VENDOR_Intel:
2457 2459 brand = intel_cpubrand(cpi);
2458 2460 break;
2459 2461 case X86_VENDOR_AMD:
2460 2462 brand = amd_cpubrand(cpi);
2461 2463 break;
2462 2464 case X86_VENDOR_Cyrix:
2463 2465 brand = cyrix_cpubrand(cpi, x86_type);
2464 2466 break;
2465 2467 case X86_VENDOR_NexGen:
2466 2468 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2467 2469 brand = "NexGen Nx586";
2468 2470 break;
2469 2471 case X86_VENDOR_Centaur:
2470 2472 if (cpi->cpi_family == 5)
2471 2473 switch (cpi->cpi_model) {
2472 2474 case 4:
2473 2475 brand = "Centaur C6";
2474 2476 break;
2475 2477 case 8:
2476 2478 brand = "Centaur C2";
2477 2479 break;
2478 2480 case 9:
2479 2481 brand = "Centaur C3";
2480 2482 break;
2481 2483 default:
2482 2484 break;
2483 2485 }
2484 2486 break;
2485 2487 case X86_VENDOR_Rise:
2486 2488 if (cpi->cpi_family == 5 &&
2487 2489 (cpi->cpi_model == 0 || cpi->cpi_model == 2))
2488 2490 brand = "Rise mP6";
2489 2491 break;
2490 2492 case X86_VENDOR_SiS:
2491 2493 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2492 2494 brand = "SiS 55x";
2493 2495 break;
2494 2496 case X86_VENDOR_TM:
2495 2497 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
2496 2498 brand = "Transmeta Crusoe TM3x00 or TM5x00";
2497 2499 break;
2498 2500 case X86_VENDOR_NSC:
2499 2501 case X86_VENDOR_UMC:
2500 2502 default:
2501 2503 break;
2502 2504 }
2503 2505 if (brand) {
2504 2506 (void) strcpy((char *)cpi->cpi_brandstr, brand);
2505 2507 return;
2506 2508 }
2507 2509
2508 2510 /*
2509 2511 * If all else fails ...
2510 2512 */
2511 2513 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
2512 2514 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
2513 2515 cpi->cpi_model, cpi->cpi_step);
2514 2516 }
2515 2517
2516 2518 /*
2517 2519 * This routine is called just after kernel memory allocation
2518 2520 * becomes available on cpu0, and as part of mp_startup() on
2519 2521 * the other cpus.
2520 2522 *
2521 2523 * Fixup the brand string, and collect any information from cpuid
2522 2524 * that requires dynamically allocated storage to represent.
2523 2525 */
2524 2526 /*ARGSUSED*/
2525 2527 void
2526 2528 cpuid_pass3(cpu_t *cpu)
2527 2529 {
2528 2530 int i, max, shft, level, size;
2529 2531 struct cpuid_regs regs;
2530 2532 struct cpuid_regs *cp;
2531 2533 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2532 2534
2533 2535 ASSERT(cpi->cpi_pass == 2);
2534 2536
2535 2537 /*
2536 2538 * Function 4: Deterministic cache parameters
2537 2539 *
2538 2540 * Take this opportunity to detect the number of threads
2539 2541 * sharing the last level cache, and construct a corresponding
2540 2542 * cache id. The respective cpuid_info members are initialized
2541 2543 * to the default case of "no last level cache sharing".
2542 2544 */
2543 2545 cpi->cpi_ncpu_shr_last_cache = 1;
2544 2546 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
2545 2547
2546 2548 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
2547 2549
2548 2550 /*
2549 2551 * Find the # of elements (size) returned by fn 4, and along
2550 2552 * the way detect last level cache sharing details.
2551 2553 */
2552 2554 bzero(®s, sizeof (regs));
2553 2555 cp = ®s;
2554 2556 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
2555 2557 cp->cp_eax = 4;
2556 2558 cp->cp_ecx = i;
2557 2559
2558 2560 (void) __cpuid_insn(cp);
2559 2561
2560 2562 if (CPI_CACHE_TYPE(cp) == 0)
2561 2563 break;
2562 2564 level = CPI_CACHE_LVL(cp);
2563 2565 if (level > max) {
2564 2566 max = level;
2565 2567 cpi->cpi_ncpu_shr_last_cache =
2566 2568 CPI_NTHR_SHR_CACHE(cp) + 1;
2567 2569 }
2568 2570 }
2569 2571 cpi->cpi_std_4_size = size = i;
2570 2572
2571 2573 /*
2572 2574 * Allocate the cpi_std_4 array. The first element
2573 2575 * references the regs for fn 4, %ecx == 0, which
2574 2576 * cpuid_pass2() stashed in cpi->cpi_std[4].
2575 2577 */
2576 2578 if (size > 0) {
2577 2579 cpi->cpi_std_4 =
2578 2580 kmem_alloc(size * sizeof (cp), KM_SLEEP);
2579 2581 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
2580 2582
2581 2583 /*
2582 2584 * Allocate storage to hold the additional regs
2583 2585 * for function 4, %ecx == 1 .. cpi_std_4_size.
2584 2586 *
2585 2587 * The regs for fn 4, %ecx == 0 has already
2586 2588 * been allocated as indicated above.
2587 2589 */
2588 2590 for (i = 1; i < size; i++) {
2589 2591 cp = cpi->cpi_std_4[i] =
2590 2592 kmem_zalloc(sizeof (regs), KM_SLEEP);
2591 2593 cp->cp_eax = 4;
2592 2594 cp->cp_ecx = i;
2593 2595
2594 2596 (void) __cpuid_insn(cp);
2595 2597 }
2596 2598 }
2597 2599 /*
2598 2600 * Determine the number of bits needed to represent
2599 2601 * the number of CPUs sharing the last level cache.
2600 2602 *
2601 2603 * Shift off that number of bits from the APIC id to
2602 2604 * derive the cache id.
2603 2605 */
2604 2606 shft = 0;
2605 2607 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
2606 2608 shft++;
2607 2609 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
2608 2610 }
2609 2611
2610 2612 /*
2611 2613 * Now fixup the brand string
2612 2614 */
2613 2615 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2614 2616 fabricate_brandstr(cpi);
2615 2617 } else {
2616 2618
2617 2619 /*
2618 2620 * If we successfully extracted a brand string from the cpuid
2619 2621 * instruction, clean it up by removing leading spaces and
2620 2622 * similar junk.
2621 2623 */
2622 2624 if (cpi->cpi_brandstr[0]) {
2623 2625 size_t maxlen = sizeof (cpi->cpi_brandstr);
2624 2626 char *src, *dst;
2625 2627
2626 2628 dst = src = (char *)cpi->cpi_brandstr;
2627 2629 src[maxlen - 1] = '\0';
2628 2630 /*
2629 2631 * strip leading spaces
2630 2632 */
2631 2633 while (*src == ' ')
2632 2634 src++;
2633 2635 /*
2634 2636 * Remove any 'Genuine' or "Authentic" prefixes
2635 2637 */
2636 2638 if (strncmp(src, "Genuine ", 8) == 0)
2637 2639 src += 8;
2638 2640 if (strncmp(src, "Authentic ", 10) == 0)
2639 2641 src += 10;
2640 2642
2641 2643 /*
2642 2644 * Now do an in-place copy.
2643 2645 * Map (R) to (r) and (TM) to (tm).
2644 2646 * The era of teletypes is long gone, and there's
2645 2647 * -really- no need to shout.
2646 2648 */
2647 2649 while (*src != '\0') {
2648 2650 if (src[0] == '(') {
2649 2651 if (strncmp(src + 1, "R)", 2) == 0) {
2650 2652 (void) strncpy(dst, "(r)", 3);
2651 2653 src += 3;
2652 2654 dst += 3;
2653 2655 continue;
2654 2656 }
2655 2657 if (strncmp(src + 1, "TM)", 3) == 0) {
2656 2658 (void) strncpy(dst, "(tm)", 4);
2657 2659 src += 4;
2658 2660 dst += 4;
2659 2661 continue;
2660 2662 }
2661 2663 }
2662 2664 *dst++ = *src++;
2663 2665 }
2664 2666 *dst = '\0';
2665 2667
2666 2668 /*
2667 2669 * Finally, remove any trailing spaces
2668 2670 */
2669 2671 while (--dst > cpi->cpi_brandstr)
2670 2672 if (*dst == ' ')
2671 2673 *dst = '\0';
2672 2674 else
2673 2675 break;
2674 2676 } else
2675 2677 fabricate_brandstr(cpi);
2676 2678 }
2677 2679 cpi->cpi_pass = 3;
2678 2680 }
2679 2681
2680 2682 /*
2681 2683 * This routine is called out of bind_hwcap() much later in the life
2682 2684 * of the kernel (post_startup()). The job of this routine is to resolve
2683 2685 * the hardware feature support and kernel support for those features into
2684 2686 * what we're actually going to tell applications via the aux vector.
2685 2687 */
2686 2688 void
2687 2689 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
2688 2690 {
2689 2691 struct cpuid_info *cpi;
2690 2692 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
2691 2693
2692 2694 if (cpu == NULL)
2693 2695 cpu = CPU;
2694 2696 cpi = cpu->cpu_m.mcpu_cpi;
2695 2697
2696 2698 ASSERT(cpi->cpi_pass == 3);
2697 2699
2698 2700 if (cpi->cpi_maxeax >= 1) {
2699 2701 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
2700 2702 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2701 2703 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES];
2702 2704
2703 2705 *edx = CPI_FEATURES_EDX(cpi);
2704 2706 *ecx = CPI_FEATURES_ECX(cpi);
2705 2707 *ebx = CPI_FEATURES_7_0_EBX(cpi);
2706 2708
2707 2709 /*
2708 2710 * [these require explicit kernel support]
2709 2711 */
2710 2712 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
2711 2713 *edx &= ~CPUID_INTC_EDX_SEP;
2712 2714
2713 2715 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
2714 2716 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
2715 2717 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
2716 2718 *edx &= ~CPUID_INTC_EDX_SSE2;
2717 2719
2718 2720 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
2719 2721 *edx &= ~CPUID_INTC_EDX_HTT;
2720 2722
2721 2723 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
2722 2724 *ecx &= ~CPUID_INTC_ECX_SSE3;
2723 2725
2724 2726 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
2725 2727 *ecx &= ~CPUID_INTC_ECX_SSSE3;
2726 2728 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
2727 2729 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
2728 2730 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
2729 2731 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
2730 2732 if (!is_x86_feature(x86_featureset, X86FSET_AES))
2731 2733 *ecx &= ~CPUID_INTC_ECX_AES;
2732 2734 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
2733 2735 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
2734 2736 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
2735 2737 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
2736 2738 CPUID_INTC_ECX_OSXSAVE);
2737 2739 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
2738 2740 *ecx &= ~CPUID_INTC_ECX_AVX;
2739 2741 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
2740 2742 *ecx &= ~CPUID_INTC_ECX_F16C;
2741 2743 if (!is_x86_feature(x86_featureset, X86FSET_FMA))
2742 2744 *ecx &= ~CPUID_INTC_ECX_FMA;
2743 2745 if (!is_x86_feature(x86_featureset, X86FSET_BMI1))
2744 2746 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
2745 2747 if (!is_x86_feature(x86_featureset, X86FSET_BMI2))
2746 2748 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
2747 2749 if (!is_x86_feature(x86_featureset, X86FSET_AVX2))
2748 2750 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
2749 2751 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED))
2750 2752 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED;
2751 2753 if (!is_x86_feature(x86_featureset, X86FSET_ADX))
2752 2754 *ebx &= ~CPUID_INTC_EBX_7_0_ADX;
2753 2755
2754 2756 /*
2755 2757 * [no explicit support required beyond x87 fp context]
2756 2758 */
2757 2759 if (!fpu_exists)
2758 2760 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
2759 2761
2760 2762 /*
2761 2763 * Now map the supported feature vector to things that we
2762 2764 * think userland will care about.
2763 2765 */
2764 2766 if (*edx & CPUID_INTC_EDX_SEP)
2765 2767 hwcap_flags |= AV_386_SEP;
2766 2768 if (*edx & CPUID_INTC_EDX_SSE)
2767 2769 hwcap_flags |= AV_386_FXSR | AV_386_SSE;
2768 2770 if (*edx & CPUID_INTC_EDX_SSE2)
2769 2771 hwcap_flags |= AV_386_SSE2;
2770 2772 if (*ecx & CPUID_INTC_ECX_SSE3)
2771 2773 hwcap_flags |= AV_386_SSE3;
2772 2774 if (*ecx & CPUID_INTC_ECX_SSSE3)
2773 2775 hwcap_flags |= AV_386_SSSE3;
2774 2776 if (*ecx & CPUID_INTC_ECX_SSE4_1)
2775 2777 hwcap_flags |= AV_386_SSE4_1;
2776 2778 if (*ecx & CPUID_INTC_ECX_SSE4_2)
2777 2779 hwcap_flags |= AV_386_SSE4_2;
2778 2780 if (*ecx & CPUID_INTC_ECX_MOVBE)
2779 2781 hwcap_flags |= AV_386_MOVBE;
2780 2782 if (*ecx & CPUID_INTC_ECX_AES)
2781 2783 hwcap_flags |= AV_386_AES;
2782 2784 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
2783 2785 hwcap_flags |= AV_386_PCLMULQDQ;
2784 2786 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
2785 2787 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
2786 2788 hwcap_flags |= AV_386_XSAVE;
2787 2789
2788 2790 if (*ecx & CPUID_INTC_ECX_AVX) {
2789 2791 hwcap_flags |= AV_386_AVX;
2790 2792 if (*ecx & CPUID_INTC_ECX_F16C)
2791 2793 hwcap_flags_2 |= AV_386_2_F16C;
2792 2794 if (*ecx & CPUID_INTC_ECX_FMA)
2793 2795 hwcap_flags_2 |= AV_386_2_FMA;
2794 2796 if (*ebx & CPUID_INTC_EBX_7_0_BMI1)
2795 2797 hwcap_flags_2 |= AV_386_2_BMI1;
2796 2798 if (*ebx & CPUID_INTC_EBX_7_0_BMI2)
2797 2799 hwcap_flags_2 |= AV_386_2_BMI2;
2798 2800 if (*ebx & CPUID_INTC_EBX_7_0_AVX2)
2799 2801 hwcap_flags_2 |= AV_386_2_AVX2;
2800 2802 }
2801 2803 }
2802 2804 if (*ecx & CPUID_INTC_ECX_VMX)
2803 2805 hwcap_flags |= AV_386_VMX;
2804 2806 if (*ecx & CPUID_INTC_ECX_POPCNT)
2805 2807 hwcap_flags |= AV_386_POPCNT;
2806 2808 if (*edx & CPUID_INTC_EDX_FPU)
2807 2809 hwcap_flags |= AV_386_FPU;
2808 2810 if (*edx & CPUID_INTC_EDX_MMX)
2809 2811 hwcap_flags |= AV_386_MMX;
2810 2812
2811 2813 if (*edx & CPUID_INTC_EDX_TSC)
2812 2814 hwcap_flags |= AV_386_TSC;
2813 2815 if (*edx & CPUID_INTC_EDX_CX8)
2814 2816 hwcap_flags |= AV_386_CX8;
2815 2817 if (*edx & CPUID_INTC_EDX_CMOV)
2816 2818 hwcap_flags |= AV_386_CMOV;
2817 2819 if (*ecx & CPUID_INTC_ECX_CX16)
2818 2820 hwcap_flags |= AV_386_CX16;
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2819 2821
2820 2822 if (*ecx & CPUID_INTC_ECX_RDRAND)
2821 2823 hwcap_flags_2 |= AV_386_2_RDRAND;
2822 2824 if (*ebx & CPUID_INTC_EBX_7_0_ADX)
2823 2825 hwcap_flags_2 |= AV_386_2_ADX;
2824 2826 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED)
2825 2827 hwcap_flags_2 |= AV_386_2_RDSEED;
2826 2828
2827 2829 }
2828 2830
2831 + /* Detect systems with a potential CPUID limit */
2832 + if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax < 4) {
2833 + cmn_err(CE_NOTE, "CPUID limit detected, "
2834 + "see the CPUID(7D) man page for details\n");
2835 + }
2836 +
2837 +
2829 2838 if (cpi->cpi_xmaxeax < 0x80000001)
2830 2839 goto pass4_done;
2831 2840
2832 2841 switch (cpi->cpi_vendor) {
2833 2842 struct cpuid_regs cp;
2834 2843 uint32_t *edx, *ecx;
2835 2844
2836 2845 case X86_VENDOR_Intel:
2837 2846 /*
2838 2847 * Seems like Intel duplicated what we necessary
2839 2848 * here to make the initial crop of 64-bit OS's work.
2840 2849 * Hopefully, those are the only "extended" bits
2841 2850 * they'll add.
2842 2851 */
2843 2852 /*FALLTHROUGH*/
2844 2853
2845 2854 case X86_VENDOR_AMD:
2846 2855 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
2847 2856 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2848 2857
2849 2858 *edx = CPI_FEATURES_XTD_EDX(cpi);
2850 2859 *ecx = CPI_FEATURES_XTD_ECX(cpi);
2851 2860
2852 2861 /*
2853 2862 * [these features require explicit kernel support]
2854 2863 */
2855 2864 switch (cpi->cpi_vendor) {
2856 2865 case X86_VENDOR_Intel:
2857 2866 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2858 2867 *edx &= ~CPUID_AMD_EDX_TSCP;
2859 2868 break;
2860 2869
2861 2870 case X86_VENDOR_AMD:
2862 2871 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2863 2872 *edx &= ~CPUID_AMD_EDX_TSCP;
2864 2873 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
2865 2874 *ecx &= ~CPUID_AMD_ECX_SSE4A;
2866 2875 break;
2867 2876
2868 2877 default:
2869 2878 break;
2870 2879 }
2871 2880
2872 2881 /*
2873 2882 * [no explicit support required beyond
2874 2883 * x87 fp context and exception handlers]
2875 2884 */
2876 2885 if (!fpu_exists)
2877 2886 *edx &= ~(CPUID_AMD_EDX_MMXamd |
2878 2887 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
2879 2888
2880 2889 if (!is_x86_feature(x86_featureset, X86FSET_NX))
2881 2890 *edx &= ~CPUID_AMD_EDX_NX;
2882 2891 #if !defined(__amd64)
2883 2892 *edx &= ~CPUID_AMD_EDX_LM;
2884 2893 #endif
2885 2894 /*
2886 2895 * Now map the supported feature vector to
2887 2896 * things that we think userland will care about.
2888 2897 */
2889 2898 #if defined(__amd64)
2890 2899 if (*edx & CPUID_AMD_EDX_SYSC)
2891 2900 hwcap_flags |= AV_386_AMD_SYSC;
2892 2901 #endif
2893 2902 if (*edx & CPUID_AMD_EDX_MMXamd)
2894 2903 hwcap_flags |= AV_386_AMD_MMX;
2895 2904 if (*edx & CPUID_AMD_EDX_3DNow)
2896 2905 hwcap_flags |= AV_386_AMD_3DNow;
2897 2906 if (*edx & CPUID_AMD_EDX_3DNowx)
2898 2907 hwcap_flags |= AV_386_AMD_3DNowx;
2899 2908 if (*ecx & CPUID_AMD_ECX_SVM)
2900 2909 hwcap_flags |= AV_386_AMD_SVM;
2901 2910
2902 2911 switch (cpi->cpi_vendor) {
2903 2912 case X86_VENDOR_AMD:
2904 2913 if (*edx & CPUID_AMD_EDX_TSCP)
2905 2914 hwcap_flags |= AV_386_TSCP;
2906 2915 if (*ecx & CPUID_AMD_ECX_AHF64)
2907 2916 hwcap_flags |= AV_386_AHF;
2908 2917 if (*ecx & CPUID_AMD_ECX_SSE4A)
2909 2918 hwcap_flags |= AV_386_AMD_SSE4A;
2910 2919 if (*ecx & CPUID_AMD_ECX_LZCNT)
2911 2920 hwcap_flags |= AV_386_AMD_LZCNT;
2912 2921 break;
2913 2922
2914 2923 case X86_VENDOR_Intel:
2915 2924 if (*edx & CPUID_AMD_EDX_TSCP)
2916 2925 hwcap_flags |= AV_386_TSCP;
2917 2926 /*
2918 2927 * Aarrgh.
2919 2928 * Intel uses a different bit in the same word.
2920 2929 */
2921 2930 if (*ecx & CPUID_INTC_ECX_AHF64)
2922 2931 hwcap_flags |= AV_386_AHF;
2923 2932 break;
2924 2933
2925 2934 default:
2926 2935 break;
2927 2936 }
2928 2937 break;
2929 2938
2930 2939 case X86_VENDOR_TM:
2931 2940 cp.cp_eax = 0x80860001;
2932 2941 (void) __cpuid_insn(&cp);
2933 2942 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
2934 2943 break;
2935 2944
2936 2945 default:
2937 2946 break;
2938 2947 }
2939 2948
2940 2949 pass4_done:
2941 2950 cpi->cpi_pass = 4;
2942 2951 if (hwcap_out != NULL) {
2943 2952 hwcap_out[0] = hwcap_flags;
2944 2953 hwcap_out[1] = hwcap_flags_2;
2945 2954 }
2946 2955 }
2947 2956
2948 2957
2949 2958 /*
2950 2959 * Simulate the cpuid instruction using the data we previously
2951 2960 * captured about this CPU. We try our best to return the truth
2952 2961 * about the hardware, independently of kernel support.
2953 2962 */
2954 2963 uint32_t
2955 2964 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
2956 2965 {
2957 2966 struct cpuid_info *cpi;
2958 2967 struct cpuid_regs *xcp;
2959 2968
2960 2969 if (cpu == NULL)
2961 2970 cpu = CPU;
2962 2971 cpi = cpu->cpu_m.mcpu_cpi;
2963 2972
2964 2973 ASSERT(cpuid_checkpass(cpu, 3));
2965 2974
2966 2975 /*
2967 2976 * CPUID data is cached in two separate places: cpi_std for standard
2968 2977 * CPUID functions, and cpi_extd for extended CPUID functions.
2969 2978 */
2970 2979 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
2971 2980 xcp = &cpi->cpi_std[cp->cp_eax];
2972 2981 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
2973 2982 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
2974 2983 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
2975 2984 else
2976 2985 /*
2977 2986 * The caller is asking for data from an input parameter which
2978 2987 * the kernel has not cached. In this case we go fetch from
2979 2988 * the hardware and return the data directly to the user.
2980 2989 */
2981 2990 return (__cpuid_insn(cp));
2982 2991
2983 2992 cp->cp_eax = xcp->cp_eax;
2984 2993 cp->cp_ebx = xcp->cp_ebx;
2985 2994 cp->cp_ecx = xcp->cp_ecx;
2986 2995 cp->cp_edx = xcp->cp_edx;
2987 2996 return (cp->cp_eax);
2988 2997 }
2989 2998
2990 2999 int
2991 3000 cpuid_checkpass(cpu_t *cpu, int pass)
2992 3001 {
2993 3002 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
2994 3003 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
2995 3004 }
2996 3005
2997 3006 int
2998 3007 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
2999 3008 {
3000 3009 ASSERT(cpuid_checkpass(cpu, 3));
3001 3010
3002 3011 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
3003 3012 }
3004 3013
3005 3014 int
3006 3015 cpuid_is_cmt(cpu_t *cpu)
3007 3016 {
3008 3017 if (cpu == NULL)
3009 3018 cpu = CPU;
3010 3019
3011 3020 ASSERT(cpuid_checkpass(cpu, 1));
3012 3021
3013 3022 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
3014 3023 }
3015 3024
3016 3025 /*
3017 3026 * AMD and Intel both implement the 64-bit variant of the syscall
3018 3027 * instruction (syscallq), so if there's -any- support for syscall,
3019 3028 * cpuid currently says "yes, we support this".
3020 3029 *
3021 3030 * However, Intel decided to -not- implement the 32-bit variant of the
3022 3031 * syscall instruction, so we provide a predicate to allow our caller
3023 3032 * to test that subtlety here.
3024 3033 *
3025 3034 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
3026 3035 * even in the case where the hardware would in fact support it.
3027 3036 */
3028 3037 /*ARGSUSED*/
3029 3038 int
3030 3039 cpuid_syscall32_insn(cpu_t *cpu)
3031 3040 {
3032 3041 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
3033 3042
3034 3043 #if !defined(__xpv)
3035 3044 if (cpu == NULL)
3036 3045 cpu = CPU;
3037 3046
3038 3047 /*CSTYLED*/
3039 3048 {
3040 3049 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3041 3050
3042 3051 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
3043 3052 cpi->cpi_xmaxeax >= 0x80000001 &&
3044 3053 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
3045 3054 return (1);
3046 3055 }
3047 3056 #endif
3048 3057 return (0);
3049 3058 }
3050 3059
3051 3060 int
3052 3061 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
3053 3062 {
3054 3063 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3055 3064
3056 3065 static const char fmt[] =
3057 3066 "x86 (%s %X family %d model %d step %d clock %d MHz)";
3058 3067 static const char fmt_ht[] =
3059 3068 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
3060 3069
3061 3070 ASSERT(cpuid_checkpass(cpu, 1));
3062 3071
3063 3072 if (cpuid_is_cmt(cpu))
3064 3073 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3065 3074 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3066 3075 cpi->cpi_family, cpi->cpi_model,
3067 3076 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3068 3077 return (snprintf(s, n, fmt,
3069 3078 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3070 3079 cpi->cpi_family, cpi->cpi_model,
3071 3080 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3072 3081 }
3073 3082
3074 3083 const char *
3075 3084 cpuid_getvendorstr(cpu_t *cpu)
3076 3085 {
3077 3086 ASSERT(cpuid_checkpass(cpu, 1));
3078 3087 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
3079 3088 }
3080 3089
3081 3090 uint_t
3082 3091 cpuid_getvendor(cpu_t *cpu)
3083 3092 {
3084 3093 ASSERT(cpuid_checkpass(cpu, 1));
3085 3094 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
3086 3095 }
3087 3096
3088 3097 uint_t
3089 3098 cpuid_getfamily(cpu_t *cpu)
3090 3099 {
3091 3100 ASSERT(cpuid_checkpass(cpu, 1));
3092 3101 return (cpu->cpu_m.mcpu_cpi->cpi_family);
3093 3102 }
3094 3103
3095 3104 uint_t
3096 3105 cpuid_getmodel(cpu_t *cpu)
3097 3106 {
3098 3107 ASSERT(cpuid_checkpass(cpu, 1));
3099 3108 return (cpu->cpu_m.mcpu_cpi->cpi_model);
3100 3109 }
3101 3110
3102 3111 uint_t
3103 3112 cpuid_get_ncpu_per_chip(cpu_t *cpu)
3104 3113 {
3105 3114 ASSERT(cpuid_checkpass(cpu, 1));
3106 3115 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
3107 3116 }
3108 3117
3109 3118 uint_t
3110 3119 cpuid_get_ncore_per_chip(cpu_t *cpu)
3111 3120 {
3112 3121 ASSERT(cpuid_checkpass(cpu, 1));
3113 3122 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
3114 3123 }
3115 3124
3116 3125 uint_t
3117 3126 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
3118 3127 {
3119 3128 ASSERT(cpuid_checkpass(cpu, 2));
3120 3129 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
3121 3130 }
3122 3131
3123 3132 id_t
3124 3133 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
3125 3134 {
3126 3135 ASSERT(cpuid_checkpass(cpu, 2));
3127 3136 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3128 3137 }
3129 3138
3130 3139 uint_t
3131 3140 cpuid_getstep(cpu_t *cpu)
3132 3141 {
3133 3142 ASSERT(cpuid_checkpass(cpu, 1));
3134 3143 return (cpu->cpu_m.mcpu_cpi->cpi_step);
3135 3144 }
3136 3145
3137 3146 uint_t
3138 3147 cpuid_getsig(struct cpu *cpu)
3139 3148 {
3140 3149 ASSERT(cpuid_checkpass(cpu, 1));
3141 3150 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
3142 3151 }
3143 3152
3144 3153 uint32_t
3145 3154 cpuid_getchiprev(struct cpu *cpu)
3146 3155 {
3147 3156 ASSERT(cpuid_checkpass(cpu, 1));
3148 3157 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
3149 3158 }
3150 3159
3151 3160 const char *
3152 3161 cpuid_getchiprevstr(struct cpu *cpu)
3153 3162 {
3154 3163 ASSERT(cpuid_checkpass(cpu, 1));
3155 3164 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
3156 3165 }
3157 3166
3158 3167 uint32_t
3159 3168 cpuid_getsockettype(struct cpu *cpu)
3160 3169 {
3161 3170 ASSERT(cpuid_checkpass(cpu, 1));
3162 3171 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
3163 3172 }
3164 3173
3165 3174 const char *
3166 3175 cpuid_getsocketstr(cpu_t *cpu)
3167 3176 {
3168 3177 static const char *socketstr = NULL;
3169 3178 struct cpuid_info *cpi;
3170 3179
3171 3180 ASSERT(cpuid_checkpass(cpu, 1));
3172 3181 cpi = cpu->cpu_m.mcpu_cpi;
3173 3182
3174 3183 /* Assume that socket types are the same across the system */
3175 3184 if (socketstr == NULL)
3176 3185 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
3177 3186 cpi->cpi_model, cpi->cpi_step);
3178 3187
3179 3188
3180 3189 return (socketstr);
3181 3190 }
3182 3191
3183 3192 int
3184 3193 cpuid_get_chipid(cpu_t *cpu)
3185 3194 {
3186 3195 ASSERT(cpuid_checkpass(cpu, 1));
3187 3196
3188 3197 if (cpuid_is_cmt(cpu))
3189 3198 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
3190 3199 return (cpu->cpu_id);
3191 3200 }
3192 3201
3193 3202 id_t
3194 3203 cpuid_get_coreid(cpu_t *cpu)
3195 3204 {
3196 3205 ASSERT(cpuid_checkpass(cpu, 1));
3197 3206 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
3198 3207 }
3199 3208
3200 3209 int
3201 3210 cpuid_get_pkgcoreid(cpu_t *cpu)
3202 3211 {
3203 3212 ASSERT(cpuid_checkpass(cpu, 1));
3204 3213 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
3205 3214 }
3206 3215
3207 3216 int
3208 3217 cpuid_get_clogid(cpu_t *cpu)
3209 3218 {
3210 3219 ASSERT(cpuid_checkpass(cpu, 1));
3211 3220 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
3212 3221 }
3213 3222
3214 3223 int
3215 3224 cpuid_get_cacheid(cpu_t *cpu)
3216 3225 {
3217 3226 ASSERT(cpuid_checkpass(cpu, 1));
3218 3227 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3219 3228 }
3220 3229
3221 3230 uint_t
3222 3231 cpuid_get_procnodeid(cpu_t *cpu)
3223 3232 {
3224 3233 ASSERT(cpuid_checkpass(cpu, 1));
3225 3234 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3226 3235 }
3227 3236
3228 3237 uint_t
3229 3238 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3230 3239 {
3231 3240 ASSERT(cpuid_checkpass(cpu, 1));
3232 3241 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3233 3242 }
3234 3243
3235 3244 uint_t
3236 3245 cpuid_get_compunitid(cpu_t *cpu)
3237 3246 {
3238 3247 ASSERT(cpuid_checkpass(cpu, 1));
3239 3248 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3240 3249 }
3241 3250
3242 3251 uint_t
3243 3252 cpuid_get_cores_per_compunit(cpu_t *cpu)
3244 3253 {
3245 3254 ASSERT(cpuid_checkpass(cpu, 1));
3246 3255 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3247 3256 }
3248 3257
3249 3258 /*ARGSUSED*/
3250 3259 int
3251 3260 cpuid_have_cr8access(cpu_t *cpu)
3252 3261 {
3253 3262 #if defined(__amd64)
3254 3263 return (1);
3255 3264 #else
3256 3265 struct cpuid_info *cpi;
3257 3266
3258 3267 ASSERT(cpu != NULL);
3259 3268 cpi = cpu->cpu_m.mcpu_cpi;
3260 3269 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3261 3270 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3262 3271 return (1);
3263 3272 return (0);
3264 3273 #endif
3265 3274 }
3266 3275
3267 3276 uint32_t
3268 3277 cpuid_get_apicid(cpu_t *cpu)
3269 3278 {
3270 3279 ASSERT(cpuid_checkpass(cpu, 1));
3271 3280 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
3272 3281 return (UINT32_MAX);
3273 3282 } else {
3274 3283 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
3275 3284 }
3276 3285 }
3277 3286
3278 3287 void
3279 3288 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
3280 3289 {
3281 3290 struct cpuid_info *cpi;
3282 3291
3283 3292 if (cpu == NULL)
3284 3293 cpu = CPU;
3285 3294 cpi = cpu->cpu_m.mcpu_cpi;
3286 3295
3287 3296 ASSERT(cpuid_checkpass(cpu, 1));
3288 3297
3289 3298 if (pabits)
3290 3299 *pabits = cpi->cpi_pabits;
3291 3300 if (vabits)
3292 3301 *vabits = cpi->cpi_vabits;
3293 3302 }
3294 3303
3295 3304 /*
3296 3305 * Returns the number of data TLB entries for a corresponding
3297 3306 * pagesize. If it can't be computed, or isn't known, the
3298 3307 * routine returns zero. If you ask about an architecturally
3299 3308 * impossible pagesize, the routine will panic (so that the
3300 3309 * hat implementor knows that things are inconsistent.)
3301 3310 */
3302 3311 uint_t
3303 3312 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
3304 3313 {
3305 3314 struct cpuid_info *cpi;
3306 3315 uint_t dtlb_nent = 0;
3307 3316
3308 3317 if (cpu == NULL)
3309 3318 cpu = CPU;
3310 3319 cpi = cpu->cpu_m.mcpu_cpi;
3311 3320
3312 3321 ASSERT(cpuid_checkpass(cpu, 1));
3313 3322
3314 3323 /*
3315 3324 * Check the L2 TLB info
3316 3325 */
3317 3326 if (cpi->cpi_xmaxeax >= 0x80000006) {
3318 3327 struct cpuid_regs *cp = &cpi->cpi_extd[6];
3319 3328
3320 3329 switch (pagesize) {
3321 3330
3322 3331 case 4 * 1024:
3323 3332 /*
3324 3333 * All zero in the top 16 bits of the register
3325 3334 * indicates a unified TLB. Size is in low 16 bits.
3326 3335 */
3327 3336 if ((cp->cp_ebx & 0xffff0000) == 0)
3328 3337 dtlb_nent = cp->cp_ebx & 0x0000ffff;
3329 3338 else
3330 3339 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
3331 3340 break;
3332 3341
3333 3342 case 2 * 1024 * 1024:
3334 3343 if ((cp->cp_eax & 0xffff0000) == 0)
3335 3344 dtlb_nent = cp->cp_eax & 0x0000ffff;
3336 3345 else
3337 3346 dtlb_nent = BITX(cp->cp_eax, 27, 16);
3338 3347 break;
3339 3348
3340 3349 default:
3341 3350 panic("unknown L2 pagesize");
3342 3351 /*NOTREACHED*/
3343 3352 }
3344 3353 }
3345 3354
3346 3355 if (dtlb_nent != 0)
3347 3356 return (dtlb_nent);
3348 3357
3349 3358 /*
3350 3359 * No L2 TLB support for this size, try L1.
3351 3360 */
3352 3361 if (cpi->cpi_xmaxeax >= 0x80000005) {
3353 3362 struct cpuid_regs *cp = &cpi->cpi_extd[5];
3354 3363
3355 3364 switch (pagesize) {
3356 3365 case 4 * 1024:
3357 3366 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
3358 3367 break;
3359 3368 case 2 * 1024 * 1024:
3360 3369 dtlb_nent = BITX(cp->cp_eax, 23, 16);
3361 3370 break;
3362 3371 default:
3363 3372 panic("unknown L1 d-TLB pagesize");
3364 3373 /*NOTREACHED*/
3365 3374 }
3366 3375 }
3367 3376
3368 3377 return (dtlb_nent);
3369 3378 }
3370 3379
3371 3380 /*
3372 3381 * Return 0 if the erratum is not present or not applicable, positive
3373 3382 * if it is, and negative if the status of the erratum is unknown.
3374 3383 *
3375 3384 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
3376 3385 * Processors" #25759, Rev 3.57, August 2005
3377 3386 */
3378 3387 int
3379 3388 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
3380 3389 {
3381 3390 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3382 3391 uint_t eax;
3383 3392
3384 3393 /*
3385 3394 * Bail out if this CPU isn't an AMD CPU, or if it's
3386 3395 * a legacy (32-bit) AMD CPU.
3387 3396 */
3388 3397 if (cpi->cpi_vendor != X86_VENDOR_AMD ||
3389 3398 cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
3390 3399 cpi->cpi_family == 6)
3391 3400
3392 3401 return (0);
3393 3402
3394 3403 eax = cpi->cpi_std[1].cp_eax;
3395 3404
3396 3405 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
3397 3406 #define SH_B3(eax) (eax == 0xf51)
3398 3407 #define B(eax) (SH_B0(eax) || SH_B3(eax))
3399 3408
3400 3409 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
3401 3410
3402 3411 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
3403 3412 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
3404 3413 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
3405 3414 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
3406 3415
3407 3416 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
3408 3417 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
3409 3418 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
3410 3419 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
3411 3420
3412 3421 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
3413 3422 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
3414 3423 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
3415 3424 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
3416 3425 #define BH_E4(eax) (eax == 0x20fb1)
3417 3426 #define SH_E5(eax) (eax == 0x20f42)
3418 3427 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
3419 3428 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
3420 3429 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
3421 3430 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
3422 3431 DH_E6(eax) || JH_E6(eax))
3423 3432
3424 3433 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02)
3425 3434 #define DR_B0(eax) (eax == 0x100f20)
3426 3435 #define DR_B1(eax) (eax == 0x100f21)
3427 3436 #define DR_BA(eax) (eax == 0x100f2a)
3428 3437 #define DR_B2(eax) (eax == 0x100f22)
3429 3438 #define DR_B3(eax) (eax == 0x100f23)
3430 3439 #define RB_C0(eax) (eax == 0x100f40)
3431 3440
3432 3441 switch (erratum) {
3433 3442 case 1:
3434 3443 return (cpi->cpi_family < 0x10);
3435 3444 case 51: /* what does the asterisk mean? */
3436 3445 return (B(eax) || SH_C0(eax) || CG(eax));
3437 3446 case 52:
3438 3447 return (B(eax));
3439 3448 case 57:
3440 3449 return (cpi->cpi_family <= 0x11);
3441 3450 case 58:
3442 3451 return (B(eax));
3443 3452 case 60:
3444 3453 return (cpi->cpi_family <= 0x11);
3445 3454 case 61:
3446 3455 case 62:
3447 3456 case 63:
3448 3457 case 64:
3449 3458 case 65:
3450 3459 case 66:
3451 3460 case 68:
3452 3461 case 69:
3453 3462 case 70:
3454 3463 case 71:
3455 3464 return (B(eax));
3456 3465 case 72:
3457 3466 return (SH_B0(eax));
3458 3467 case 74:
3459 3468 return (B(eax));
3460 3469 case 75:
3461 3470 return (cpi->cpi_family < 0x10);
3462 3471 case 76:
3463 3472 return (B(eax));
3464 3473 case 77:
3465 3474 return (cpi->cpi_family <= 0x11);
3466 3475 case 78:
3467 3476 return (B(eax) || SH_C0(eax));
3468 3477 case 79:
3469 3478 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3470 3479 case 80:
3471 3480 case 81:
3472 3481 case 82:
3473 3482 return (B(eax));
3474 3483 case 83:
3475 3484 return (B(eax) || SH_C0(eax) || CG(eax));
3476 3485 case 85:
3477 3486 return (cpi->cpi_family < 0x10);
3478 3487 case 86:
3479 3488 return (SH_C0(eax) || CG(eax));
3480 3489 case 88:
3481 3490 #if !defined(__amd64)
3482 3491 return (0);
3483 3492 #else
3484 3493 return (B(eax) || SH_C0(eax));
3485 3494 #endif
3486 3495 case 89:
3487 3496 return (cpi->cpi_family < 0x10);
3488 3497 case 90:
3489 3498 return (B(eax) || SH_C0(eax) || CG(eax));
3490 3499 case 91:
3491 3500 case 92:
3492 3501 return (B(eax) || SH_C0(eax));
3493 3502 case 93:
3494 3503 return (SH_C0(eax));
3495 3504 case 94:
3496 3505 return (B(eax) || SH_C0(eax) || CG(eax));
3497 3506 case 95:
3498 3507 #if !defined(__amd64)
3499 3508 return (0);
3500 3509 #else
3501 3510 return (B(eax) || SH_C0(eax));
3502 3511 #endif
3503 3512 case 96:
3504 3513 return (B(eax) || SH_C0(eax) || CG(eax));
3505 3514 case 97:
3506 3515 case 98:
3507 3516 return (SH_C0(eax) || CG(eax));
3508 3517 case 99:
3509 3518 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3510 3519 case 100:
3511 3520 return (B(eax) || SH_C0(eax));
3512 3521 case 101:
3513 3522 case 103:
3514 3523 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3515 3524 case 104:
3516 3525 return (SH_C0(eax) || CG(eax) || D0(eax));
3517 3526 case 105:
3518 3527 case 106:
3519 3528 case 107:
3520 3529 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3521 3530 case 108:
3522 3531 return (DH_CG(eax));
3523 3532 case 109:
3524 3533 return (SH_C0(eax) || CG(eax) || D0(eax));
3525 3534 case 110:
3526 3535 return (D0(eax) || EX(eax));
3527 3536 case 111:
3528 3537 return (CG(eax));
3529 3538 case 112:
3530 3539 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3531 3540 case 113:
3532 3541 return (eax == 0x20fc0);
3533 3542 case 114:
3534 3543 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3535 3544 case 115:
3536 3545 return (SH_E0(eax) || JH_E1(eax));
3537 3546 case 116:
3538 3547 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3539 3548 case 117:
3540 3549 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3541 3550 case 118:
3542 3551 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
3543 3552 JH_E6(eax));
3544 3553 case 121:
3545 3554 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3546 3555 case 122:
3547 3556 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11);
3548 3557 case 123:
3549 3558 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
3550 3559 case 131:
3551 3560 return (cpi->cpi_family < 0x10);
3552 3561 case 6336786:
3553 3562 /*
3554 3563 * Test for AdvPowerMgmtInfo.TscPStateInvariant
3555 3564 * if this is a K8 family or newer processor
3556 3565 */
3557 3566 if (CPI_FAMILY(cpi) == 0xf) {
3558 3567 struct cpuid_regs regs;
3559 3568 regs.cp_eax = 0x80000007;
3560 3569 (void) __cpuid_insn(®s);
3561 3570 return (!(regs.cp_edx & 0x100));
3562 3571 }
3563 3572 return (0);
3564 3573 case 6323525:
3565 3574 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
3566 3575 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
3567 3576
3568 3577 case 6671130:
3569 3578 /*
3570 3579 * check for processors (pre-Shanghai) that do not provide
3571 3580 * optimal management of 1gb ptes in its tlb.
3572 3581 */
3573 3582 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
3574 3583
3575 3584 case 298:
3576 3585 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
3577 3586 DR_B2(eax) || RB_C0(eax));
3578 3587
3579 3588 case 721:
3580 3589 #if defined(__amd64)
3581 3590 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
3582 3591 #else
3583 3592 return (0);
3584 3593 #endif
3585 3594
3586 3595 default:
3587 3596 return (-1);
3588 3597
3589 3598 }
3590 3599 }
3591 3600
3592 3601 /*
3593 3602 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
3594 3603 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
3595 3604 */
3596 3605 int
3597 3606 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
3598 3607 {
3599 3608 struct cpuid_info *cpi;
3600 3609 uint_t osvwid;
3601 3610 static int osvwfeature = -1;
3602 3611 uint64_t osvwlength;
3603 3612
3604 3613
3605 3614 cpi = cpu->cpu_m.mcpu_cpi;
3606 3615
3607 3616 /* confirm OSVW supported */
3608 3617 if (osvwfeature == -1) {
3609 3618 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
3610 3619 } else {
3611 3620 /* assert that osvw feature setting is consistent on all cpus */
3612 3621 ASSERT(osvwfeature ==
3613 3622 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
3614 3623 }
3615 3624 if (!osvwfeature)
3616 3625 return (-1);
3617 3626
3618 3627 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
3619 3628
3620 3629 switch (erratum) {
3621 3630 case 298: /* osvwid is 0 */
3622 3631 osvwid = 0;
3623 3632 if (osvwlength <= (uint64_t)osvwid) {
3624 3633 /* osvwid 0 is unknown */
3625 3634 return (-1);
3626 3635 }
3627 3636
3628 3637 /*
3629 3638 * Check the OSVW STATUS MSR to determine the state
3630 3639 * of the erratum where:
3631 3640 * 0 - fixed by HW
3632 3641 * 1 - BIOS has applied the workaround when BIOS
3633 3642 * workaround is available. (Or for other errata,
3634 3643 * OS workaround is required.)
3635 3644 * For a value of 1, caller will confirm that the
3636 3645 * erratum 298 workaround has indeed been applied by BIOS.
3637 3646 *
3638 3647 * A 1 may be set in cpus that have a HW fix
3639 3648 * in a mixed cpu system. Regarding erratum 298:
3640 3649 * In a multiprocessor platform, the workaround above
3641 3650 * should be applied to all processors regardless of
3642 3651 * silicon revision when an affected processor is
3643 3652 * present.
3644 3653 */
3645 3654
3646 3655 return (rdmsr(MSR_AMD_OSVW_STATUS +
3647 3656 (osvwid / OSVW_ID_CNT_PER_MSR)) &
3648 3657 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
3649 3658
3650 3659 default:
3651 3660 return (-1);
3652 3661 }
3653 3662 }
3654 3663
3655 3664 static const char assoc_str[] = "associativity";
3656 3665 static const char line_str[] = "line-size";
3657 3666 static const char size_str[] = "size";
3658 3667
3659 3668 static void
3660 3669 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
3661 3670 uint32_t val)
3662 3671 {
3663 3672 char buf[128];
3664 3673
3665 3674 /*
3666 3675 * ndi_prop_update_int() is used because it is desirable for
3667 3676 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
3668 3677 */
3669 3678 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
3670 3679 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
3671 3680 }
3672 3681
3673 3682 /*
3674 3683 * Intel-style cache/tlb description
3675 3684 *
3676 3685 * Standard cpuid level 2 gives a randomly ordered
3677 3686 * selection of tags that index into a table that describes
3678 3687 * cache and tlb properties.
3679 3688 */
3680 3689
3681 3690 static const char l1_icache_str[] = "l1-icache";
3682 3691 static const char l1_dcache_str[] = "l1-dcache";
3683 3692 static const char l2_cache_str[] = "l2-cache";
3684 3693 static const char l3_cache_str[] = "l3-cache";
3685 3694 static const char itlb4k_str[] = "itlb-4K";
3686 3695 static const char dtlb4k_str[] = "dtlb-4K";
3687 3696 static const char itlb2M_str[] = "itlb-2M";
3688 3697 static const char itlb4M_str[] = "itlb-4M";
3689 3698 static const char dtlb4M_str[] = "dtlb-4M";
3690 3699 static const char dtlb24_str[] = "dtlb0-2M-4M";
3691 3700 static const char itlb424_str[] = "itlb-4K-2M-4M";
3692 3701 static const char itlb24_str[] = "itlb-2M-4M";
3693 3702 static const char dtlb44_str[] = "dtlb-4K-4M";
3694 3703 static const char sl1_dcache_str[] = "sectored-l1-dcache";
3695 3704 static const char sl2_cache_str[] = "sectored-l2-cache";
3696 3705 static const char itrace_str[] = "itrace-cache";
3697 3706 static const char sl3_cache_str[] = "sectored-l3-cache";
3698 3707 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
3699 3708
3700 3709 static const struct cachetab {
3701 3710 uint8_t ct_code;
3702 3711 uint8_t ct_assoc;
3703 3712 uint16_t ct_line_size;
3704 3713 size_t ct_size;
3705 3714 const char *ct_label;
3706 3715 } intel_ctab[] = {
3707 3716 /*
3708 3717 * maintain descending order!
3709 3718 *
3710 3719 * Codes ignored - Reason
3711 3720 * ----------------------
3712 3721 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3713 3722 * f0H/f1H - Currently we do not interpret prefetch size by design
3714 3723 */
3715 3724 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str},
3716 3725 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str},
3717 3726 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str},
3718 3727 { 0xde, 12, 64, 6*1024*1024, l3_cache_str},
3719 3728 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str},
3720 3729 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str},
3721 3730 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str},
3722 3731 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str},
3723 3732 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str},
3724 3733 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str},
3725 3734 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str},
3726 3735 { 0xd0, 4, 64, 512*1024, l3_cache_str},
3727 3736 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
3728 3737 { 0xc0, 4, 0, 8, dtlb44_str },
3729 3738 { 0xba, 4, 0, 64, dtlb4k_str },
3730 3739 { 0xb4, 4, 0, 256, dtlb4k_str },
3731 3740 { 0xb3, 4, 0, 128, dtlb4k_str },
3732 3741 { 0xb2, 4, 0, 64, itlb4k_str },
3733 3742 { 0xb0, 4, 0, 128, itlb4k_str },
3734 3743 { 0x87, 8, 64, 1024*1024, l2_cache_str},
3735 3744 { 0x86, 4, 64, 512*1024, l2_cache_str},
3736 3745 { 0x85, 8, 32, 2*1024*1024, l2_cache_str},
3737 3746 { 0x84, 8, 32, 1024*1024, l2_cache_str},
3738 3747 { 0x83, 8, 32, 512*1024, l2_cache_str},
3739 3748 { 0x82, 8, 32, 256*1024, l2_cache_str},
3740 3749 { 0x80, 8, 64, 512*1024, l2_cache_str},
3741 3750 { 0x7f, 2, 64, 512*1024, l2_cache_str},
3742 3751 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
3743 3752 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
3744 3753 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
3745 3754 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
3746 3755 { 0x79, 8, 64, 128*1024, sl2_cache_str},
3747 3756 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3748 3757 { 0x73, 8, 0, 64*1024, itrace_str},
3749 3758 { 0x72, 8, 0, 32*1024, itrace_str},
3750 3759 { 0x71, 8, 0, 16*1024, itrace_str},
3751 3760 { 0x70, 8, 0, 12*1024, itrace_str},
3752 3761 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
3753 3762 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
3754 3763 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
3755 3764 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
3756 3765 { 0x5d, 0, 0, 256, dtlb44_str},
3757 3766 { 0x5c, 0, 0, 128, dtlb44_str},
3758 3767 { 0x5b, 0, 0, 64, dtlb44_str},
3759 3768 { 0x5a, 4, 0, 32, dtlb24_str},
3760 3769 { 0x59, 0, 0, 16, dtlb4k_str},
3761 3770 { 0x57, 4, 0, 16, dtlb4k_str},
3762 3771 { 0x56, 4, 0, 16, dtlb4M_str},
3763 3772 { 0x55, 0, 0, 7, itlb24_str},
3764 3773 { 0x52, 0, 0, 256, itlb424_str},
3765 3774 { 0x51, 0, 0, 128, itlb424_str},
3766 3775 { 0x50, 0, 0, 64, itlb424_str},
3767 3776 { 0x4f, 0, 0, 32, itlb4k_str},
3768 3777 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str},
3769 3778 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
3770 3779 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
3771 3780 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
3772 3781 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
3773 3782 { 0x49, 16, 64, 4*1024*1024, l3_cache_str},
3774 3783 { 0x48, 12, 64, 3*1024*1024, l2_cache_str},
3775 3784 { 0x47, 8, 64, 8*1024*1024, l3_cache_str},
3776 3785 { 0x46, 4, 64, 4*1024*1024, l3_cache_str},
3777 3786 { 0x45, 4, 32, 2*1024*1024, l2_cache_str},
3778 3787 { 0x44, 4, 32, 1024*1024, l2_cache_str},
3779 3788 { 0x43, 4, 32, 512*1024, l2_cache_str},
3780 3789 { 0x42, 4, 32, 256*1024, l2_cache_str},
3781 3790 { 0x41, 4, 32, 128*1024, l2_cache_str},
3782 3791 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
3783 3792 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
3784 3793 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
3785 3794 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3786 3795 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
3787 3796 { 0x39, 4, 64, 128*1024, sl2_cache_str},
3788 3797 { 0x30, 8, 64, 32*1024, l1_icache_str},
3789 3798 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
3790 3799 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
3791 3800 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
3792 3801 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
3793 3802 { 0x22, 4, 64, 512*1024, sl3_cache_str},
3794 3803 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
3795 3804 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
3796 3805 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3797 3806 { 0x0b, 4, 0, 4, itlb4M_str},
3798 3807 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
3799 3808 { 0x08, 4, 32, 16*1024, l1_icache_str},
3800 3809 { 0x06, 4, 32, 8*1024, l1_icache_str},
3801 3810 { 0x05, 4, 0, 32, dtlb4M_str},
3802 3811 { 0x04, 4, 0, 8, dtlb4M_str},
3803 3812 { 0x03, 4, 0, 64, dtlb4k_str},
3804 3813 { 0x02, 4, 0, 2, itlb4M_str},
3805 3814 { 0x01, 4, 0, 32, itlb4k_str},
3806 3815 { 0 }
3807 3816 };
3808 3817
3809 3818 static const struct cachetab cyrix_ctab[] = {
3810 3819 { 0x70, 4, 0, 32, "tlb-4K" },
3811 3820 { 0x80, 4, 16, 16*1024, "l1-cache" },
3812 3821 { 0 }
3813 3822 };
3814 3823
3815 3824 /*
3816 3825 * Search a cache table for a matching entry
3817 3826 */
3818 3827 static const struct cachetab *
3819 3828 find_cacheent(const struct cachetab *ct, uint_t code)
3820 3829 {
3821 3830 if (code != 0) {
3822 3831 for (; ct->ct_code != 0; ct++)
3823 3832 if (ct->ct_code <= code)
3824 3833 break;
3825 3834 if (ct->ct_code == code)
3826 3835 return (ct);
3827 3836 }
3828 3837 return (NULL);
3829 3838 }
3830 3839
3831 3840 /*
3832 3841 * Populate cachetab entry with L2 or L3 cache-information using
3833 3842 * cpuid function 4. This function is called from intel_walk_cacheinfo()
3834 3843 * when descriptor 0x49 is encountered. It returns 0 if no such cache
3835 3844 * information is found.
3836 3845 */
3837 3846 static int
3838 3847 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
3839 3848 {
3840 3849 uint32_t level, i;
3841 3850 int ret = 0;
3842 3851
3843 3852 for (i = 0; i < cpi->cpi_std_4_size; i++) {
3844 3853 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
3845 3854
3846 3855 if (level == 2 || level == 3) {
3847 3856 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
3848 3857 ct->ct_line_size =
3849 3858 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
3850 3859 ct->ct_size = ct->ct_assoc *
3851 3860 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
3852 3861 ct->ct_line_size *
3853 3862 (cpi->cpi_std_4[i]->cp_ecx + 1);
3854 3863
3855 3864 if (level == 2) {
3856 3865 ct->ct_label = l2_cache_str;
3857 3866 } else if (level == 3) {
3858 3867 ct->ct_label = l3_cache_str;
3859 3868 }
3860 3869 ret = 1;
3861 3870 }
3862 3871 }
3863 3872
3864 3873 return (ret);
3865 3874 }
3866 3875
3867 3876 /*
3868 3877 * Walk the cacheinfo descriptor, applying 'func' to every valid element
3869 3878 * The walk is terminated if the walker returns non-zero.
3870 3879 */
3871 3880 static void
3872 3881 intel_walk_cacheinfo(struct cpuid_info *cpi,
3873 3882 void *arg, int (*func)(void *, const struct cachetab *))
3874 3883 {
3875 3884 const struct cachetab *ct;
3876 3885 struct cachetab des_49_ct, des_b1_ct;
3877 3886 uint8_t *dp;
3878 3887 int i;
3879 3888
3880 3889 if ((dp = cpi->cpi_cacheinfo) == NULL)
3881 3890 return;
3882 3891 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3883 3892 /*
3884 3893 * For overloaded descriptor 0x49 we use cpuid function 4
3885 3894 * if supported by the current processor, to create
3886 3895 * cache information.
3887 3896 * For overloaded descriptor 0xb1 we use X86_PAE flag
3888 3897 * to disambiguate the cache information.
3889 3898 */
3890 3899 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
3891 3900 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
3892 3901 ct = &des_49_ct;
3893 3902 } else if (*dp == 0xb1) {
3894 3903 des_b1_ct.ct_code = 0xb1;
3895 3904 des_b1_ct.ct_assoc = 4;
3896 3905 des_b1_ct.ct_line_size = 0;
3897 3906 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
3898 3907 des_b1_ct.ct_size = 8;
3899 3908 des_b1_ct.ct_label = itlb2M_str;
3900 3909 } else {
3901 3910 des_b1_ct.ct_size = 4;
3902 3911 des_b1_ct.ct_label = itlb4M_str;
3903 3912 }
3904 3913 ct = &des_b1_ct;
3905 3914 } else {
3906 3915 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
3907 3916 continue;
3908 3917 }
3909 3918 }
3910 3919
3911 3920 if (func(arg, ct) != 0) {
3912 3921 break;
3913 3922 }
3914 3923 }
3915 3924 }
3916 3925
3917 3926 /*
3918 3927 * (Like the Intel one, except for Cyrix CPUs)
3919 3928 */
3920 3929 static void
3921 3930 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
3922 3931 void *arg, int (*func)(void *, const struct cachetab *))
3923 3932 {
3924 3933 const struct cachetab *ct;
3925 3934 uint8_t *dp;
3926 3935 int i;
3927 3936
3928 3937 if ((dp = cpi->cpi_cacheinfo) == NULL)
3929 3938 return;
3930 3939 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3931 3940 /*
3932 3941 * Search Cyrix-specific descriptor table first ..
3933 3942 */
3934 3943 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
3935 3944 if (func(arg, ct) != 0)
3936 3945 break;
3937 3946 continue;
3938 3947 }
3939 3948 /*
3940 3949 * .. else fall back to the Intel one
3941 3950 */
3942 3951 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
3943 3952 if (func(arg, ct) != 0)
3944 3953 break;
3945 3954 continue;
3946 3955 }
3947 3956 }
3948 3957 }
3949 3958
3950 3959 /*
3951 3960 * A cacheinfo walker that adds associativity, line-size, and size properties
3952 3961 * to the devinfo node it is passed as an argument.
3953 3962 */
3954 3963 static int
3955 3964 add_cacheent_props(void *arg, const struct cachetab *ct)
3956 3965 {
3957 3966 dev_info_t *devi = arg;
3958 3967
3959 3968 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
3960 3969 if (ct->ct_line_size != 0)
3961 3970 add_cache_prop(devi, ct->ct_label, line_str,
3962 3971 ct->ct_line_size);
3963 3972 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
3964 3973 return (0);
3965 3974 }
3966 3975
3967 3976
3968 3977 static const char fully_assoc[] = "fully-associative?";
3969 3978
3970 3979 /*
3971 3980 * AMD style cache/tlb description
3972 3981 *
3973 3982 * Extended functions 5 and 6 directly describe properties of
3974 3983 * tlbs and various cache levels.
3975 3984 */
3976 3985 static void
3977 3986 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3978 3987 {
3979 3988 switch (assoc) {
3980 3989 case 0: /* reserved; ignore */
3981 3990 break;
3982 3991 default:
3983 3992 add_cache_prop(devi, label, assoc_str, assoc);
3984 3993 break;
3985 3994 case 0xff:
3986 3995 add_cache_prop(devi, label, fully_assoc, 1);
3987 3996 break;
3988 3997 }
3989 3998 }
3990 3999
3991 4000 static void
3992 4001 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
3993 4002 {
3994 4003 if (size == 0)
3995 4004 return;
3996 4005 add_cache_prop(devi, label, size_str, size);
3997 4006 add_amd_assoc(devi, label, assoc);
3998 4007 }
3999 4008
4000 4009 static void
4001 4010 add_amd_cache(dev_info_t *devi, const char *label,
4002 4011 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4003 4012 {
4004 4013 if (size == 0 || line_size == 0)
4005 4014 return;
4006 4015 add_amd_assoc(devi, label, assoc);
4007 4016 /*
4008 4017 * Most AMD parts have a sectored cache. Multiple cache lines are
4009 4018 * associated with each tag. A sector consists of all cache lines
4010 4019 * associated with a tag. For example, the AMD K6-III has a sector
4011 4020 * size of 2 cache lines per tag.
4012 4021 */
4013 4022 if (lines_per_tag != 0)
4014 4023 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4015 4024 add_cache_prop(devi, label, line_str, line_size);
4016 4025 add_cache_prop(devi, label, size_str, size * 1024);
4017 4026 }
4018 4027
4019 4028 static void
4020 4029 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4021 4030 {
4022 4031 switch (assoc) {
4023 4032 case 0: /* off */
4024 4033 break;
4025 4034 case 1:
4026 4035 case 2:
4027 4036 case 4:
4028 4037 add_cache_prop(devi, label, assoc_str, assoc);
4029 4038 break;
4030 4039 case 6:
4031 4040 add_cache_prop(devi, label, assoc_str, 8);
4032 4041 break;
4033 4042 case 8:
4034 4043 add_cache_prop(devi, label, assoc_str, 16);
4035 4044 break;
4036 4045 case 0xf:
4037 4046 add_cache_prop(devi, label, fully_assoc, 1);
4038 4047 break;
4039 4048 default: /* reserved; ignore */
4040 4049 break;
4041 4050 }
4042 4051 }
4043 4052
4044 4053 static void
4045 4054 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4046 4055 {
4047 4056 if (size == 0 || assoc == 0)
4048 4057 return;
4049 4058 add_amd_l2_assoc(devi, label, assoc);
4050 4059 add_cache_prop(devi, label, size_str, size);
4051 4060 }
4052 4061
4053 4062 static void
4054 4063 add_amd_l2_cache(dev_info_t *devi, const char *label,
4055 4064 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4056 4065 {
4057 4066 if (size == 0 || assoc == 0 || line_size == 0)
4058 4067 return;
4059 4068 add_amd_l2_assoc(devi, label, assoc);
4060 4069 if (lines_per_tag != 0)
4061 4070 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4062 4071 add_cache_prop(devi, label, line_str, line_size);
4063 4072 add_cache_prop(devi, label, size_str, size * 1024);
4064 4073 }
4065 4074
4066 4075 static void
4067 4076 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
4068 4077 {
4069 4078 struct cpuid_regs *cp;
4070 4079
4071 4080 if (cpi->cpi_xmaxeax < 0x80000005)
4072 4081 return;
4073 4082 cp = &cpi->cpi_extd[5];
4074 4083
4075 4084 /*
4076 4085 * 4M/2M L1 TLB configuration
4077 4086 *
4078 4087 * We report the size for 2M pages because AMD uses two
4079 4088 * TLB entries for one 4M page.
4080 4089 */
4081 4090 add_amd_tlb(devi, "dtlb-2M",
4082 4091 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
4083 4092 add_amd_tlb(devi, "itlb-2M",
4084 4093 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
4085 4094
4086 4095 /*
4087 4096 * 4K L1 TLB configuration
4088 4097 */
4089 4098
4090 4099 switch (cpi->cpi_vendor) {
4091 4100 uint_t nentries;
4092 4101 case X86_VENDOR_TM:
4093 4102 if (cpi->cpi_family >= 5) {
4094 4103 /*
4095 4104 * Crusoe processors have 256 TLB entries, but
4096 4105 * cpuid data format constrains them to only
4097 4106 * reporting 255 of them.
4098 4107 */
4099 4108 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
4100 4109 nentries = 256;
4101 4110 /*
4102 4111 * Crusoe processors also have a unified TLB
4103 4112 */
4104 4113 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
4105 4114 nentries);
4106 4115 break;
4107 4116 }
4108 4117 /*FALLTHROUGH*/
4109 4118 default:
4110 4119 add_amd_tlb(devi, itlb4k_str,
4111 4120 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
4112 4121 add_amd_tlb(devi, dtlb4k_str,
4113 4122 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
4114 4123 break;
4115 4124 }
4116 4125
4117 4126 /*
4118 4127 * data L1 cache configuration
4119 4128 */
4120 4129
4121 4130 add_amd_cache(devi, l1_dcache_str,
4122 4131 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
4123 4132 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
4124 4133
4125 4134 /*
4126 4135 * code L1 cache configuration
4127 4136 */
4128 4137
4129 4138 add_amd_cache(devi, l1_icache_str,
4130 4139 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
4131 4140 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
4132 4141
4133 4142 if (cpi->cpi_xmaxeax < 0x80000006)
4134 4143 return;
4135 4144 cp = &cpi->cpi_extd[6];
4136 4145
4137 4146 /* Check for a unified L2 TLB for large pages */
4138 4147
4139 4148 if (BITX(cp->cp_eax, 31, 16) == 0)
4140 4149 add_amd_l2_tlb(devi, "l2-tlb-2M",
4141 4150 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4142 4151 else {
4143 4152 add_amd_l2_tlb(devi, "l2-dtlb-2M",
4144 4153 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4145 4154 add_amd_l2_tlb(devi, "l2-itlb-2M",
4146 4155 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4147 4156 }
4148 4157
4149 4158 /* Check for a unified L2 TLB for 4K pages */
4150 4159
4151 4160 if (BITX(cp->cp_ebx, 31, 16) == 0) {
4152 4161 add_amd_l2_tlb(devi, "l2-tlb-4K",
4153 4162 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4154 4163 } else {
4155 4164 add_amd_l2_tlb(devi, "l2-dtlb-4K",
4156 4165 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4157 4166 add_amd_l2_tlb(devi, "l2-itlb-4K",
4158 4167 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4159 4168 }
4160 4169
4161 4170 add_amd_l2_cache(devi, l2_cache_str,
4162 4171 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
4163 4172 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
4164 4173 }
4165 4174
4166 4175 /*
4167 4176 * There are two basic ways that the x86 world describes it cache
4168 4177 * and tlb architecture - Intel's way and AMD's way.
4169 4178 *
4170 4179 * Return which flavor of cache architecture we should use
4171 4180 */
4172 4181 static int
4173 4182 x86_which_cacheinfo(struct cpuid_info *cpi)
4174 4183 {
4175 4184 switch (cpi->cpi_vendor) {
4176 4185 case X86_VENDOR_Intel:
4177 4186 if (cpi->cpi_maxeax >= 2)
4178 4187 return (X86_VENDOR_Intel);
4179 4188 break;
4180 4189 case X86_VENDOR_AMD:
4181 4190 /*
4182 4191 * The K5 model 1 was the first part from AMD that reported
4183 4192 * cache sizes via extended cpuid functions.
4184 4193 */
4185 4194 if (cpi->cpi_family > 5 ||
4186 4195 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
4187 4196 return (X86_VENDOR_AMD);
4188 4197 break;
4189 4198 case X86_VENDOR_TM:
4190 4199 if (cpi->cpi_family >= 5)
4191 4200 return (X86_VENDOR_AMD);
4192 4201 /*FALLTHROUGH*/
4193 4202 default:
4194 4203 /*
4195 4204 * If they have extended CPU data for 0x80000005
4196 4205 * then we assume they have AMD-format cache
4197 4206 * information.
4198 4207 *
4199 4208 * If not, and the vendor happens to be Cyrix,
4200 4209 * then try our-Cyrix specific handler.
4201 4210 *
4202 4211 * If we're not Cyrix, then assume we're using Intel's
4203 4212 * table-driven format instead.
4204 4213 */
4205 4214 if (cpi->cpi_xmaxeax >= 0x80000005)
4206 4215 return (X86_VENDOR_AMD);
4207 4216 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
4208 4217 return (X86_VENDOR_Cyrix);
4209 4218 else if (cpi->cpi_maxeax >= 2)
4210 4219 return (X86_VENDOR_Intel);
4211 4220 break;
4212 4221 }
4213 4222 return (-1);
4214 4223 }
4215 4224
4216 4225 void
4217 4226 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
4218 4227 struct cpuid_info *cpi)
4219 4228 {
4220 4229 dev_info_t *cpu_devi;
4221 4230 int create;
4222 4231
4223 4232 cpu_devi = (dev_info_t *)dip;
4224 4233
4225 4234 /* device_type */
4226 4235 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4227 4236 "device_type", "cpu");
4228 4237
4229 4238 /* reg */
4230 4239 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4231 4240 "reg", cpu_id);
4232 4241
4233 4242 /* cpu-mhz, and clock-frequency */
4234 4243 if (cpu_freq > 0) {
4235 4244 long long mul;
4236 4245
4237 4246 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4238 4247 "cpu-mhz", cpu_freq);
4239 4248 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
4240 4249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4241 4250 "clock-frequency", (int)mul);
4242 4251 }
4243 4252
4244 4253 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
4245 4254 return;
4246 4255 }
4247 4256
4248 4257 /* vendor-id */
4249 4258 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4250 4259 "vendor-id", cpi->cpi_vendorstr);
4251 4260
4252 4261 if (cpi->cpi_maxeax == 0) {
4253 4262 return;
4254 4263 }
4255 4264
4256 4265 /*
4257 4266 * family, model, and step
4258 4267 */
4259 4268 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4260 4269 "family", CPI_FAMILY(cpi));
4261 4270 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4262 4271 "cpu-model", CPI_MODEL(cpi));
4263 4272 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4264 4273 "stepping-id", CPI_STEP(cpi));
4265 4274
4266 4275 /* type */
4267 4276 switch (cpi->cpi_vendor) {
4268 4277 case X86_VENDOR_Intel:
4269 4278 create = 1;
4270 4279 break;
4271 4280 default:
4272 4281 create = 0;
4273 4282 break;
4274 4283 }
4275 4284 if (create)
4276 4285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4277 4286 "type", CPI_TYPE(cpi));
4278 4287
4279 4288 /* ext-family */
4280 4289 switch (cpi->cpi_vendor) {
4281 4290 case X86_VENDOR_Intel:
4282 4291 case X86_VENDOR_AMD:
4283 4292 create = cpi->cpi_family >= 0xf;
4284 4293 break;
4285 4294 default:
4286 4295 create = 0;
4287 4296 break;
4288 4297 }
4289 4298 if (create)
4290 4299 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4291 4300 "ext-family", CPI_FAMILY_XTD(cpi));
4292 4301
4293 4302 /* ext-model */
4294 4303 switch (cpi->cpi_vendor) {
4295 4304 case X86_VENDOR_Intel:
4296 4305 create = IS_EXTENDED_MODEL_INTEL(cpi);
4297 4306 break;
4298 4307 case X86_VENDOR_AMD:
4299 4308 create = CPI_FAMILY(cpi) == 0xf;
4300 4309 break;
4301 4310 default:
4302 4311 create = 0;
4303 4312 break;
4304 4313 }
4305 4314 if (create)
4306 4315 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4307 4316 "ext-model", CPI_MODEL_XTD(cpi));
4308 4317
4309 4318 /* generation */
4310 4319 switch (cpi->cpi_vendor) {
4311 4320 case X86_VENDOR_AMD:
4312 4321 /*
4313 4322 * AMD K5 model 1 was the first part to support this
4314 4323 */
4315 4324 create = cpi->cpi_xmaxeax >= 0x80000001;
4316 4325 break;
4317 4326 default:
4318 4327 create = 0;
4319 4328 break;
4320 4329 }
4321 4330 if (create)
4322 4331 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4323 4332 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
4324 4333
4325 4334 /* brand-id */
4326 4335 switch (cpi->cpi_vendor) {
4327 4336 case X86_VENDOR_Intel:
4328 4337 /*
4329 4338 * brand id first appeared on Pentium III Xeon model 8,
4330 4339 * and Celeron model 8 processors and Opteron
4331 4340 */
4332 4341 create = cpi->cpi_family > 6 ||
4333 4342 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
4334 4343 break;
4335 4344 case X86_VENDOR_AMD:
4336 4345 create = cpi->cpi_family >= 0xf;
4337 4346 break;
4338 4347 default:
4339 4348 create = 0;
4340 4349 break;
4341 4350 }
4342 4351 if (create && cpi->cpi_brandid != 0) {
4343 4352 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4344 4353 "brand-id", cpi->cpi_brandid);
4345 4354 }
4346 4355
4347 4356 /* chunks, and apic-id */
4348 4357 switch (cpi->cpi_vendor) {
4349 4358 /*
4350 4359 * first available on Pentium IV and Opteron (K8)
4351 4360 */
4352 4361 case X86_VENDOR_Intel:
4353 4362 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4354 4363 break;
4355 4364 case X86_VENDOR_AMD:
4356 4365 create = cpi->cpi_family >= 0xf;
4357 4366 break;
4358 4367 default:
4359 4368 create = 0;
4360 4369 break;
4361 4370 }
4362 4371 if (create) {
4363 4372 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4364 4373 "chunks", CPI_CHUNKS(cpi));
4365 4374 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4366 4375 "apic-id", cpi->cpi_apicid);
4367 4376 if (cpi->cpi_chipid >= 0) {
4368 4377 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4369 4378 "chip#", cpi->cpi_chipid);
4370 4379 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4371 4380 "clog#", cpi->cpi_clogid);
4372 4381 }
4373 4382 }
4374 4383
4375 4384 /* cpuid-features */
4376 4385 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4377 4386 "cpuid-features", CPI_FEATURES_EDX(cpi));
4378 4387
4379 4388
4380 4389 /* cpuid-features-ecx */
4381 4390 switch (cpi->cpi_vendor) {
4382 4391 case X86_VENDOR_Intel:
4383 4392 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4384 4393 break;
4385 4394 case X86_VENDOR_AMD:
4386 4395 create = cpi->cpi_family >= 0xf;
4387 4396 break;
4388 4397 default:
4389 4398 create = 0;
4390 4399 break;
4391 4400 }
4392 4401 if (create)
4393 4402 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4394 4403 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4395 4404
4396 4405 /* ext-cpuid-features */
4397 4406 switch (cpi->cpi_vendor) {
4398 4407 case X86_VENDOR_Intel:
4399 4408 case X86_VENDOR_AMD:
4400 4409 case X86_VENDOR_Cyrix:
4401 4410 case X86_VENDOR_TM:
4402 4411 case X86_VENDOR_Centaur:
4403 4412 create = cpi->cpi_xmaxeax >= 0x80000001;
4404 4413 break;
4405 4414 default:
4406 4415 create = 0;
4407 4416 break;
4408 4417 }
4409 4418 if (create) {
4410 4419 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4411 4420 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
4412 4421 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4413 4422 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
4414 4423 }
4415 4424
4416 4425 /*
4417 4426 * Brand String first appeared in Intel Pentium IV, AMD K5
4418 4427 * model 1, and Cyrix GXm. On earlier models we try and
4419 4428 * simulate something similar .. so this string should always
4420 4429 * same -something- about the processor, however lame.
4421 4430 */
4422 4431 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4423 4432 "brand-string", cpi->cpi_brandstr);
4424 4433
4425 4434 /*
4426 4435 * Finally, cache and tlb information
4427 4436 */
4428 4437 switch (x86_which_cacheinfo(cpi)) {
4429 4438 case X86_VENDOR_Intel:
4430 4439 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4431 4440 break;
4432 4441 case X86_VENDOR_Cyrix:
4433 4442 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4434 4443 break;
4435 4444 case X86_VENDOR_AMD:
4436 4445 amd_cache_info(cpi, cpu_devi);
4437 4446 break;
4438 4447 default:
4439 4448 break;
4440 4449 }
4441 4450 }
4442 4451
4443 4452 struct l2info {
4444 4453 int *l2i_csz;
4445 4454 int *l2i_lsz;
4446 4455 int *l2i_assoc;
4447 4456 int l2i_ret;
4448 4457 };
4449 4458
4450 4459 /*
4451 4460 * A cacheinfo walker that fetches the size, line-size and associativity
4452 4461 * of the L2 cache
4453 4462 */
4454 4463 static int
4455 4464 intel_l2cinfo(void *arg, const struct cachetab *ct)
4456 4465 {
4457 4466 struct l2info *l2i = arg;
4458 4467 int *ip;
4459 4468
4460 4469 if (ct->ct_label != l2_cache_str &&
4461 4470 ct->ct_label != sl2_cache_str)
4462 4471 return (0); /* not an L2 -- keep walking */
4463 4472
4464 4473 if ((ip = l2i->l2i_csz) != NULL)
4465 4474 *ip = ct->ct_size;
4466 4475 if ((ip = l2i->l2i_lsz) != NULL)
4467 4476 *ip = ct->ct_line_size;
4468 4477 if ((ip = l2i->l2i_assoc) != NULL)
4469 4478 *ip = ct->ct_assoc;
4470 4479 l2i->l2i_ret = ct->ct_size;
4471 4480 return (1); /* was an L2 -- terminate walk */
4472 4481 }
4473 4482
4474 4483 /*
4475 4484 * AMD L2/L3 Cache and TLB Associativity Field Definition:
4476 4485 *
4477 4486 * Unlike the associativity for the L1 cache and tlb where the 8 bit
4478 4487 * value is the associativity, the associativity for the L2 cache and
4479 4488 * tlb is encoded in the following table. The 4 bit L2 value serves as
4480 4489 * an index into the amd_afd[] array to determine the associativity.
4481 4490 * -1 is undefined. 0 is fully associative.
4482 4491 */
4483 4492
4484 4493 static int amd_afd[] =
4485 4494 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
4486 4495
4487 4496 static void
4488 4497 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
4489 4498 {
4490 4499 struct cpuid_regs *cp;
4491 4500 uint_t size, assoc;
4492 4501 int i;
4493 4502 int *ip;
4494 4503
4495 4504 if (cpi->cpi_xmaxeax < 0x80000006)
4496 4505 return;
4497 4506 cp = &cpi->cpi_extd[6];
4498 4507
4499 4508 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
4500 4509 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
4501 4510 uint_t cachesz = size * 1024;
4502 4511 assoc = amd_afd[i];
4503 4512
4504 4513 ASSERT(assoc != -1);
4505 4514
4506 4515 if ((ip = l2i->l2i_csz) != NULL)
4507 4516 *ip = cachesz;
4508 4517 if ((ip = l2i->l2i_lsz) != NULL)
4509 4518 *ip = BITX(cp->cp_ecx, 7, 0);
4510 4519 if ((ip = l2i->l2i_assoc) != NULL)
4511 4520 *ip = assoc;
4512 4521 l2i->l2i_ret = cachesz;
4513 4522 }
4514 4523 }
4515 4524
4516 4525 int
4517 4526 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
4518 4527 {
4519 4528 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
4520 4529 struct l2info __l2info, *l2i = &__l2info;
4521 4530
4522 4531 l2i->l2i_csz = csz;
4523 4532 l2i->l2i_lsz = lsz;
4524 4533 l2i->l2i_assoc = assoc;
4525 4534 l2i->l2i_ret = -1;
4526 4535
4527 4536 switch (x86_which_cacheinfo(cpi)) {
4528 4537 case X86_VENDOR_Intel:
4529 4538 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4530 4539 break;
4531 4540 case X86_VENDOR_Cyrix:
4532 4541 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4533 4542 break;
4534 4543 case X86_VENDOR_AMD:
4535 4544 amd_l2cacheinfo(cpi, l2i);
4536 4545 break;
4537 4546 default:
4538 4547 break;
4539 4548 }
4540 4549 return (l2i->l2i_ret);
4541 4550 }
4542 4551
4543 4552 #if !defined(__xpv)
4544 4553
4545 4554 uint32_t *
4546 4555 cpuid_mwait_alloc(cpu_t *cpu)
4547 4556 {
4548 4557 uint32_t *ret;
4549 4558 size_t mwait_size;
4550 4559
4551 4560 ASSERT(cpuid_checkpass(CPU, 2));
4552 4561
4553 4562 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
4554 4563 if (mwait_size == 0)
4555 4564 return (NULL);
4556 4565
4557 4566 /*
4558 4567 * kmem_alloc() returns cache line size aligned data for mwait_size
4559 4568 * allocations. mwait_size is currently cache line sized. Neither
4560 4569 * of these implementation details are guarantied to be true in the
4561 4570 * future.
4562 4571 *
4563 4572 * First try allocating mwait_size as kmem_alloc() currently returns
4564 4573 * correctly aligned memory. If kmem_alloc() does not return
4565 4574 * mwait_size aligned memory, then use mwait_size ROUNDUP.
4566 4575 *
4567 4576 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
4568 4577 * decide to free this memory.
4569 4578 */
4570 4579 ret = kmem_zalloc(mwait_size, KM_SLEEP);
4571 4580 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
4572 4581 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4573 4582 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
4574 4583 *ret = MWAIT_RUNNING;
4575 4584 return (ret);
4576 4585 } else {
4577 4586 kmem_free(ret, mwait_size);
4578 4587 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
4579 4588 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4580 4589 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
4581 4590 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
4582 4591 *ret = MWAIT_RUNNING;
4583 4592 return (ret);
4584 4593 }
4585 4594 }
4586 4595
4587 4596 void
4588 4597 cpuid_mwait_free(cpu_t *cpu)
4589 4598 {
4590 4599 if (cpu->cpu_m.mcpu_cpi == NULL) {
4591 4600 return;
4592 4601 }
4593 4602
4594 4603 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
4595 4604 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
4596 4605 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
4597 4606 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
4598 4607 }
4599 4608
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4600 4609 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
4601 4610 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4602 4611 }
4603 4612
4604 4613 void
4605 4614 patch_tsc_read(int flag)
4606 4615 {
4607 4616 size_t cnt;
4608 4617
4609 4618 switch (flag) {
4610 - case X86_NO_TSC:
4619 + case TSC_NONE:
4611 4620 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
4612 4621 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
4613 4622 break;
4614 - case X86_HAVE_TSCP:
4615 - cnt = &_tscp_end - &_tscp_start;
4616 - (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
4617 - break;
4618 - case X86_TSC_MFENCE:
4623 + case TSC_RDTSC_MFENCE:
4619 4624 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
4620 4625 (void) memcpy((void *)tsc_read,
4621 4626 (void *)&_tsc_mfence_start, cnt);
4622 4627 break;
4623 - case X86_TSC_LFENCE:
4628 + case TSC_RDTSC_LFENCE:
4624 4629 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
4625 4630 (void) memcpy((void *)tsc_read,
4626 4631 (void *)&_tsc_lfence_start, cnt);
4627 4632 break;
4633 + case TSC_TSCP:
4634 + cnt = &_tscp_end - &_tscp_start;
4635 + (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
4636 + break;
4628 4637 default:
4638 + /* Bail for unexpected TSC types. (TSC_NONE covers 0) */
4639 + cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag);
4629 4640 break;
4630 4641 }
4642 + tsc_type = flag;
4631 4643 }
4632 4644
4633 4645 int
4634 4646 cpuid_deep_cstates_supported(void)
4635 4647 {
4636 4648 struct cpuid_info *cpi;
4637 4649 struct cpuid_regs regs;
4638 4650
4639 4651 ASSERT(cpuid_checkpass(CPU, 1));
4640 4652
4641 4653 cpi = CPU->cpu_m.mcpu_cpi;
4642 4654
4643 4655 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
4644 4656 return (0);
4645 4657
4646 4658 switch (cpi->cpi_vendor) {
4647 4659 case X86_VENDOR_Intel:
4648 4660 if (cpi->cpi_xmaxeax < 0x80000007)
4649 4661 return (0);
4650 4662
4651 4663 /*
4652 4664 * TSC run at a constant rate in all ACPI C-states?
4653 4665 */
4654 4666 regs.cp_eax = 0x80000007;
4655 4667 (void) __cpuid_insn(®s);
4656 4668 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
4657 4669
4658 4670 default:
4659 4671 return (0);
4660 4672 }
4661 4673 }
4662 4674
4663 4675 #endif /* !__xpv */
4664 4676
4665 4677 void
4666 4678 post_startup_cpu_fixups(void)
4667 4679 {
4668 4680 #ifndef __xpv
4669 4681 /*
4670 4682 * Some AMD processors support C1E state. Entering this state will
4671 4683 * cause the local APIC timer to stop, which we can't deal with at
4672 4684 * this time.
4673 4685 */
4674 4686 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
4675 4687 on_trap_data_t otd;
4676 4688 uint64_t reg;
4677 4689
4678 4690 if (!on_trap(&otd, OT_DATA_ACCESS)) {
4679 4691 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
4680 4692 /* Disable C1E state if it is enabled by BIOS */
4681 4693 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
4682 4694 AMD_ACTONCMPHALT_MASK) {
4683 4695 reg &= ~(AMD_ACTONCMPHALT_MASK <<
4684 4696 AMD_ACTONCMPHALT_SHIFT);
4685 4697 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
4686 4698 }
4687 4699 }
4688 4700 no_trap();
4689 4701 }
4690 4702 #endif /* !__xpv */
4691 4703 }
4692 4704
4693 4705 /*
4694 4706 * Setup necessary registers to enable XSAVE feature on this processor.
4695 4707 * This function needs to be called early enough, so that no xsave/xrstor
4696 4708 * ops will execute on the processor before the MSRs are properly set up.
4697 4709 *
4698 4710 * Current implementation has the following assumption:
4699 4711 * - cpuid_pass1() is done, so that X86 features are known.
4700 4712 * - fpu_probe() is done, so that fp_save_mech is chosen.
4701 4713 */
4702 4714 void
4703 4715 xsave_setup_msr(cpu_t *cpu)
4704 4716 {
4705 4717 ASSERT(fp_save_mech == FP_XSAVE);
4706 4718 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
4707 4719
4708 4720 /* Enable OSXSAVE in CR4. */
4709 4721 setcr4(getcr4() | CR4_OSXSAVE);
4710 4722 /*
4711 4723 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
4712 4724 * correct value.
4713 4725 */
4714 4726 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE;
4715 4727 setup_xfem();
4716 4728 }
4717 4729
4718 4730 /*
4719 4731 * Starting with the Westmere processor the local
4720 4732 * APIC timer will continue running in all C-states,
4721 4733 * including the deepest C-states.
4722 4734 */
4723 4735 int
4724 4736 cpuid_arat_supported(void)
4725 4737 {
4726 4738 struct cpuid_info *cpi;
4727 4739 struct cpuid_regs regs;
4728 4740
4729 4741 ASSERT(cpuid_checkpass(CPU, 1));
4730 4742 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4731 4743
4732 4744 cpi = CPU->cpu_m.mcpu_cpi;
4733 4745
4734 4746 switch (cpi->cpi_vendor) {
4735 4747 case X86_VENDOR_Intel:
4736 4748 /*
4737 4749 * Always-running Local APIC Timer is
4738 4750 * indicated by CPUID.6.EAX[2].
4739 4751 */
4740 4752 if (cpi->cpi_maxeax >= 6) {
4741 4753 regs.cp_eax = 6;
4742 4754 (void) cpuid_insn(NULL, ®s);
4743 4755 return (regs.cp_eax & CPUID_CSTATE_ARAT);
4744 4756 } else {
4745 4757 return (0);
4746 4758 }
4747 4759 default:
4748 4760 return (0);
4749 4761 }
4750 4762 }
4751 4763
4752 4764 /*
4753 4765 * Check support for Intel ENERGY_PERF_BIAS feature
4754 4766 */
4755 4767 int
4756 4768 cpuid_iepb_supported(struct cpu *cp)
4757 4769 {
4758 4770 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
4759 4771 struct cpuid_regs regs;
4760 4772
4761 4773 ASSERT(cpuid_checkpass(cp, 1));
4762 4774
4763 4775 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) ||
4764 4776 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
4765 4777 return (0);
4766 4778 }
4767 4779
4768 4780 /*
4769 4781 * Intel ENERGY_PERF_BIAS MSR is indicated by
4770 4782 * capability bit CPUID.6.ECX.3
4771 4783 */
4772 4784 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6))
4773 4785 return (0);
4774 4786
4775 4787 regs.cp_eax = 0x6;
4776 4788 (void) cpuid_insn(NULL, ®s);
4777 4789 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
4778 4790 }
4779 4791
4780 4792 /*
4781 4793 * Check support for TSC deadline timer
4782 4794 *
4783 4795 * TSC deadline timer provides a superior software programming
4784 4796 * model over local APIC timer that eliminates "time drifts".
4785 4797 * Instead of specifying a relative time, software specifies an
4786 4798 * absolute time as the target at which the processor should
4787 4799 * generate a timer event.
4788 4800 */
4789 4801 int
4790 4802 cpuid_deadline_tsc_supported(void)
4791 4803 {
4792 4804 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
4793 4805 struct cpuid_regs regs;
4794 4806
4795 4807 ASSERT(cpuid_checkpass(CPU, 1));
4796 4808 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4797 4809
4798 4810 switch (cpi->cpi_vendor) {
4799 4811 case X86_VENDOR_Intel:
4800 4812 if (cpi->cpi_maxeax >= 1) {
4801 4813 regs.cp_eax = 1;
4802 4814 (void) cpuid_insn(NULL, ®s);
4803 4815 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
4804 4816 } else {
4805 4817 return (0);
4806 4818 }
4807 4819 default:
4808 4820 return (0);
4809 4821 }
4810 4822 }
4811 4823
4812 4824 #if defined(__amd64) && !defined(__xpv)
4813 4825 /*
4814 4826 * Patch in versions of bcopy for high performance Intel Nhm processors
4815 4827 * and later...
4816 4828 */
4817 4829 void
4818 4830 patch_memops(uint_t vendor)
4819 4831 {
4820 4832 size_t cnt, i;
4821 4833 caddr_t to, from;
4822 4834
4823 4835 if ((vendor == X86_VENDOR_Intel) &&
4824 4836 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
4825 4837 cnt = &bcopy_patch_end - &bcopy_patch_start;
4826 4838 to = &bcopy_ck_size;
4827 4839 from = &bcopy_patch_start;
4828 4840 for (i = 0; i < cnt; i++) {
4829 4841 *to++ = *from++;
4830 4842 }
4831 4843 }
4832 4844 }
4833 4845 #endif /* __amd64 && !__xpv */
4834 4846
4835 4847 /*
4836 4848 * This function finds the number of bits to represent the number of cores per
4837 4849 * chip and the number of strands per core for the Intel platforms.
4838 4850 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
4839 4851 */
4840 4852 void
4841 4853 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits)
4842 4854 {
4843 4855 struct cpuid_regs regs;
4844 4856 struct cpuid_regs *cp = ®s;
4845 4857
4846 4858 if (vendor != X86_VENDOR_Intel) {
4847 4859 return;
4848 4860 }
4849 4861
4850 4862 /* if the cpuid level is 0xB, extended topo is available. */
4851 4863 cp->cp_eax = 0;
4852 4864 if (__cpuid_insn(cp) >= 0xB) {
4853 4865
4854 4866 cp->cp_eax = 0xB;
4855 4867 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
4856 4868 (void) __cpuid_insn(cp);
4857 4869
4858 4870 /*
4859 4871 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
4860 4872 * indicates that the extended topology enumeration leaf is
4861 4873 * available.
4862 4874 */
4863 4875 if (cp->cp_ebx) {
4864 4876 uint_t coreid_shift = 0;
4865 4877 uint_t chipid_shift = 0;
4866 4878 uint_t i;
4867 4879 uint_t level;
4868 4880
4869 4881 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
4870 4882 cp->cp_eax = 0xB;
4871 4883 cp->cp_ecx = i;
4872 4884
4873 4885 (void) __cpuid_insn(cp);
4874 4886 level = CPI_CPU_LEVEL_TYPE(cp);
4875 4887
4876 4888 if (level == 1) {
4877 4889 /*
4878 4890 * Thread level processor topology
4879 4891 * Number of bits shift right APIC ID
4880 4892 * to get the coreid.
4881 4893 */
4882 4894 coreid_shift = BITX(cp->cp_eax, 4, 0);
4883 4895 } else if (level == 2) {
4884 4896 /*
4885 4897 * Core level processor topology
4886 4898 * Number of bits shift right APIC ID
4887 4899 * to get the chipid.
4888 4900 */
4889 4901 chipid_shift = BITX(cp->cp_eax, 4, 0);
4890 4902 }
4891 4903 }
4892 4904
4893 4905 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
4894 4906 *strand_nbits = coreid_shift;
4895 4907 *core_nbits = chipid_shift - coreid_shift;
4896 4908 }
4897 4909 }
4898 4910 }
4899 4911 }
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