1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
26 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31 /*
32 * Portions Copyright 2009 Advanced Micro Devices, Inc.
33 */
34 /*
35 * Copyright (c) 2015, Joyent, Inc. All rights reserved.
36 */
37 /*
38 * Various routines to handle identification
39 * and classification of x86 processors.
40 */
41
42 #include <sys/types.h>
43 #include <sys/archsystm.h>
44 #include <sys/x86_archext.h>
45 #include <sys/kmem.h>
46 #include <sys/systm.h>
47 #include <sys/cmn_err.h>
48 #include <sys/sunddi.h>
49 #include <sys/sunndi.h>
50 #include <sys/cpuvar.h>
51 #include <sys/processor.h>
52 #include <sys/sysmacros.h>
53 #include <sys/pg.h>
54 #include <sys/fp.h>
55 #include <sys/controlregs.h>
56 #include <sys/bitmap.h>
57 #include <sys/auxv_386.h>
58 #include <sys/memnode.h>
59 #include <sys/pci_cfgspace.h>
60
61 #ifdef __xpv
62 #include <sys/hypervisor.h>
63 #else
64 #include <sys/ontrap.h>
65 #endif
66
67 /*
68 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
69 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
70 * them accordingly. For most modern processors, feature detection occurs here
71 * in pass 1.
72 *
73 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
74 * for the boot CPU and does the basic analysis that the early kernel needs.
75 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
76 * CPU.
77 *
78 * Pass 1 includes:
79 *
80 * o Determining vendor/model/family/stepping and setting x86_type and
81 * x86_vendor accordingly.
82 * o Processing the feature flags returned by the cpuid instruction while
83 * applying any workarounds or tricks for the specific processor.
84 * o Mapping the feature flags into Solaris feature bits (X86_*).
85 * o Processing extended feature flags if supported by the processor,
86 * again while applying specific processor knowledge.
87 * o Determining the CMT characteristics of the system.
88 *
89 * Pass 1 is done on non-boot CPUs during their initialization and the results
90 * are used only as a meager attempt at ensuring that all processors within the
91 * system support the same features.
92 *
93 * Pass 2 of cpuid feature analysis happens just at the beginning
94 * of startup(). It just copies in and corrects the remainder
95 * of the cpuid data we depend on: standard cpuid functions that we didn't
96 * need for pass1 feature analysis, and extended cpuid functions beyond the
97 * simple feature processing done in pass1.
98 *
99 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
100 * particular kernel memory allocation has been made available. It creates a
101 * readable brand string based on the data collected in the first two passes.
102 *
103 * Pass 4 of cpuid analysis is invoked after post_startup() when all
104 * the support infrastructure for various hardware features has been
105 * initialized. It determines which processor features will be reported
106 * to userland via the aux vector.
107 *
108 * All passes are executed on all CPUs, but only the boot CPU determines what
109 * features the kernel will use.
110 *
111 * Much of the worst junk in this file is for the support of processors
112 * that didn't really implement the cpuid instruction properly.
113 *
114 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
115 * the pass numbers. Accordingly, changes to the pass code may require changes
116 * to the accessor code.
117 */
118
119 uint_t x86_vendor = X86_VENDOR_IntelClone;
120 uint_t x86_type = X86_TYPE_OTHER;
121 uint_t x86_clflush_size = 0;
122
123 uint_t pentiumpro_bug4046376;
124
125 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
126
127 static char *x86_feature_names[NUM_X86_FEATURES] = {
128 "lgpg",
129 "tsc",
130 "msr",
131 "mtrr",
132 "pge",
133 "de",
134 "cmov",
135 "mmx",
136 "mca",
137 "pae",
138 "cv8",
139 "pat",
140 "sep",
141 "sse",
142 "sse2",
143 "htt",
144 "asysc",
145 "nx",
146 "sse3",
147 "cx16",
148 "cmp",
149 "tscp",
150 "mwait",
151 "sse4a",
152 "cpuid",
153 "ssse3",
154 "sse4_1",
155 "sse4_2",
156 "1gpg",
157 "clfsh",
158 "64",
159 "aes",
160 "pclmulqdq",
161 "xsave",
162 "avx",
163 "vmx",
164 "svm",
165 "topoext",
166 "f16c",
167 "rdrand",
168 "x2apic",
169 "avx2",
170 "bmi1",
171 "bmi2",
172 "fma",
173 "smep",
174 "smap",
175 "adx",
176 "rdseed"
177 };
178
179 boolean_t
180 is_x86_feature(void *featureset, uint_t feature)
181 {
182 ASSERT(feature < NUM_X86_FEATURES);
183 return (BT_TEST((ulong_t *)featureset, feature));
184 }
185
186 void
187 add_x86_feature(void *featureset, uint_t feature)
188 {
189 ASSERT(feature < NUM_X86_FEATURES);
190 BT_SET((ulong_t *)featureset, feature);
191 }
192
193 void
194 remove_x86_feature(void *featureset, uint_t feature)
195 {
196 ASSERT(feature < NUM_X86_FEATURES);
197 BT_CLEAR((ulong_t *)featureset, feature);
198 }
199
200 boolean_t
201 compare_x86_featureset(void *setA, void *setB)
202 {
203 /*
204 * We assume that the unused bits of the bitmap are always zero.
205 */
206 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
207 return (B_TRUE);
208 } else {
209 return (B_FALSE);
210 }
211 }
212
213 void
214 print_x86_featureset(void *featureset)
215 {
216 uint_t i;
217
218 for (i = 0; i < NUM_X86_FEATURES; i++) {
219 if (is_x86_feature(featureset, i)) {
220 cmn_err(CE_CONT, "?x86_feature: %s\n",
221 x86_feature_names[i]);
222 }
223 }
224 }
225
226 static size_t xsave_state_size = 0;
227 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE);
228 boolean_t xsave_force_disable = B_FALSE;
229 extern int disable_smap;
230
231 /*
232 * This is set to platform type we are running on.
233 */
234 static int platform_type = -1;
235
236 #if !defined(__xpv)
237 /*
238 * Variable to patch if hypervisor platform detection needs to be
239 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
240 */
241 int enable_platform_detection = 1;
242 #endif
243
244 /*
245 * monitor/mwait info.
246 *
247 * size_actual and buf_actual are the real address and size allocated to get
248 * proper mwait_buf alignement. buf_actual and size_actual should be passed
249 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
250 * processor cache-line alignment, but this is not guarantied in the furture.
251 */
252 struct mwait_info {
253 size_t mon_min; /* min size to avoid missed wakeups */
254 size_t mon_max; /* size to avoid false wakeups */
255 size_t size_actual; /* size actually allocated */
256 void *buf_actual; /* memory actually allocated */
257 uint32_t support; /* processor support of monitor/mwait */
258 };
259
260 /*
261 * xsave/xrestor info.
262 *
263 * This structure contains HW feature bits and size of the xsave save area.
264 * Note: the kernel will use the maximum size required for all hardware
265 * features. It is not optimize for potential memory savings if features at
266 * the end of the save area are not enabled.
267 */
268 struct xsave_info {
269 uint32_t xsav_hw_features_low; /* Supported HW features */
270 uint32_t xsav_hw_features_high; /* Supported HW features */
271 size_t xsav_max_size; /* max size save area for HW features */
272 size_t ymm_size; /* AVX: size of ymm save area */
273 size_t ymm_offset; /* AVX: offset for ymm save area */
274 };
275
276
277 /*
278 * These constants determine how many of the elements of the
279 * cpuid we cache in the cpuid_info data structure; the
280 * remaining elements are accessible via the cpuid instruction.
281 */
282
283 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */
284 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
285
286 /*
287 * Some terminology needs to be explained:
288 * - Socket: Something that can be plugged into a motherboard.
289 * - Package: Same as socket
290 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
291 * differently: there, chip is the same as processor node (below)
292 * - Processor node: Some AMD processors have more than one
293 * "subprocessor" embedded in a package. These subprocessors (nodes)
294 * are fully-functional processors themselves with cores, caches,
295 * memory controllers, PCI configuration spaces. They are connected
296 * inside the package with Hypertransport links. On single-node
297 * processors, processor node is equivalent to chip/socket/package.
298 * - Compute Unit: Some AMD processors pair cores in "compute units" that
299 * share the FPU and the I$ and L2 caches.
300 */
301
302 struct cpuid_info {
303 uint_t cpi_pass; /* last pass completed */
304 /*
305 * standard function information
306 */
307 uint_t cpi_maxeax; /* fn 0: %eax */
308 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
309 uint_t cpi_vendor; /* enum of cpi_vendorstr */
310
311 uint_t cpi_family; /* fn 1: extended family */
312 uint_t cpi_model; /* fn 1: extended model */
313 uint_t cpi_step; /* fn 1: stepping */
314 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
315 /* AMD: package/socket # */
316 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
317 int cpi_clogid; /* fn 1: %ebx: thread # */
318 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
319 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
320 uint_t cpi_ncache; /* fn 2: number of elements */
321 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
322 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
323 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
324 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
325 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */
326 /*
327 * extended function information
328 */
329 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
330 char cpi_brandstr[49]; /* fn 0x8000000[234] */
331 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
332 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
333 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
334
335 id_t cpi_coreid; /* same coreid => strands share core */
336 int cpi_pkgcoreid; /* core number within single package */
337 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
338 /* Intel: fn 4: %eax[31-26] */
339 /*
340 * supported feature information
341 */
342 uint32_t cpi_support[6];
343 #define STD_EDX_FEATURES 0
344 #define AMD_EDX_FEATURES 1
345 #define TM_EDX_FEATURES 2
346 #define STD_ECX_FEATURES 3
347 #define AMD_ECX_FEATURES 4
348 #define STD_EBX_FEATURES 5
349 /*
350 * Synthesized information, where known.
351 */
352 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
353 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
354 uint32_t cpi_socket; /* Chip package/socket type */
355
356 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
357 uint32_t cpi_apicid;
358 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
359 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
360 /* Intel: 1 */
361 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
362 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
363
364 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
365 };
366
367
368 static struct cpuid_info cpuid_info0;
369
370 /*
371 * These bit fields are defined by the Intel Application Note AP-485
372 * "Intel Processor Identification and the CPUID Instruction"
373 */
374 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
375 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
376 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
377 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
378 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
379 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
380
381 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
382 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
383 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
384 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
385 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx)
386
387 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
388 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
389 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
390 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
391
392 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
393 #define CPI_XMAXEAX_MAX 0x80000100
394 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
395 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
396
397 /*
398 * Function 4 (Deterministic Cache Parameters) macros
399 * Defined by Intel Application Note AP-485
400 */
401 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
402 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
403 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
404 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
405 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
406 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
407 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
408
409 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
410 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
411 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
412
413 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
414
415 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
416
417
418 /*
419 * A couple of shorthand macros to identify "later" P6-family chips
420 * like the Pentium M and Core. First, the "older" P6-based stuff
421 * (loosely defined as "pre-Pentium-4"):
422 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
423 */
424
425 #define IS_LEGACY_P6(cpi) ( \
426 cpi->cpi_family == 6 && \
427 (cpi->cpi_model == 1 || \
428 cpi->cpi_model == 3 || \
429 cpi->cpi_model == 5 || \
430 cpi->cpi_model == 6 || \
431 cpi->cpi_model == 7 || \
432 cpi->cpi_model == 8 || \
433 cpi->cpi_model == 0xA || \
434 cpi->cpi_model == 0xB) \
435 )
436
437 /* A "new F6" is everything with family 6 that's not the above */
438 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
439
440 /* Extended family/model support */
441 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
442 cpi->cpi_family >= 0xf)
443
444 /*
445 * Info for monitor/mwait idle loop.
446 *
447 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
448 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
449 * 2006.
450 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
451 * Documentation Updates" #33633, Rev 2.05, December 2006.
452 */
453 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
454 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
455 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
456 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
457 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
458 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
459 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
460 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
461 /*
462 * Number of sub-cstates for a given c-state.
463 */
464 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
465 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
466
467 /*
468 * XSAVE leaf 0xD enumeration
469 */
470 #define CPUID_LEAFD_2_YMM_OFFSET 576
471 #define CPUID_LEAFD_2_YMM_SIZE 256
472
473 /*
474 * Functions we consune from cpuid_subr.c; don't publish these in a header
475 * file to try and keep people using the expected cpuid_* interfaces.
476 */
477 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
478 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
479 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
480 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
481 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
482
483 /*
484 * Apply up various platform-dependent restrictions where the
485 * underlying platform restrictions mean the CPU can be marked
486 * as less capable than its cpuid instruction would imply.
487 */
488 #if defined(__xpv)
489 static void
490 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
491 {
492 switch (eax) {
493 case 1: {
494 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
495 0 : CPUID_INTC_EDX_MCA;
496 cp->cp_edx &=
497 ~(mcamask |
498 CPUID_INTC_EDX_PSE |
499 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
500 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
501 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
502 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
503 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
504 break;
505 }
506
507 case 0x80000001:
508 cp->cp_edx &=
509 ~(CPUID_AMD_EDX_PSE |
510 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
511 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
512 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
513 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
514 CPUID_AMD_EDX_TSCP);
515 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
516 break;
517 default:
518 break;
519 }
520
521 switch (vendor) {
522 case X86_VENDOR_Intel:
523 switch (eax) {
524 case 4:
525 /*
526 * Zero out the (ncores-per-chip - 1) field
527 */
528 cp->cp_eax &= 0x03fffffff;
529 break;
530 default:
531 break;
532 }
533 break;
534 case X86_VENDOR_AMD:
535 switch (eax) {
536
537 case 0x80000001:
538 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
539 break;
540
541 case 0x80000008:
542 /*
543 * Zero out the (ncores-per-chip - 1) field
544 */
545 cp->cp_ecx &= 0xffffff00;
546 break;
547 default:
548 break;
549 }
550 break;
551 default:
552 break;
553 }
554 }
555 #else
556 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
557 #endif
558
559 /*
560 * Some undocumented ways of patching the results of the cpuid
561 * instruction to permit running Solaris 10 on future cpus that
562 * we don't currently support. Could be set to non-zero values
563 * via settings in eeprom.
564 */
565
566 uint32_t cpuid_feature_ecx_include;
567 uint32_t cpuid_feature_ecx_exclude;
568 uint32_t cpuid_feature_edx_include;
569 uint32_t cpuid_feature_edx_exclude;
570
571 /*
572 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
573 */
574 void
575 cpuid_alloc_space(cpu_t *cpu)
576 {
577 /*
578 * By convention, cpu0 is the boot cpu, which is set up
579 * before memory allocation is available. All other cpus get
580 * their cpuid_info struct allocated here.
581 */
582 ASSERT(cpu->cpu_id != 0);
583 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
584 cpu->cpu_m.mcpu_cpi =
585 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
586 }
587
588 void
589 cpuid_free_space(cpu_t *cpu)
590 {
591 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
592 int i;
593
594 ASSERT(cpi != NULL);
595 ASSERT(cpi != &cpuid_info0);
596
597 /*
598 * Free up any function 4 related dynamic storage
599 */
600 for (i = 1; i < cpi->cpi_std_4_size; i++)
601 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
602 if (cpi->cpi_std_4_size > 0)
603 kmem_free(cpi->cpi_std_4,
604 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
605
606 kmem_free(cpi, sizeof (*cpi));
607 cpu->cpu_m.mcpu_cpi = NULL;
608 }
609
610 #if !defined(__xpv)
611 /*
612 * Determine the type of the underlying platform. This is used to customize
613 * initialization of various subsystems (e.g. TSC). determine_platform() must
614 * only ever be called once to prevent two processors from seeing different
615 * values of platform_type. Must be called before cpuid_pass1(), the earliest
616 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
617 */
618 void
619 determine_platform(void)
620 {
621 struct cpuid_regs cp;
622 uint32_t base;
623 uint32_t regs[4];
624 char *hvstr = (char *)regs;
625
626 ASSERT(platform_type == -1);
627
628 platform_type = HW_NATIVE;
629
630 if (!enable_platform_detection)
631 return;
632
633 /*
634 * If Hypervisor CPUID bit is set, try to determine hypervisor
635 * vendor signature, and set platform type accordingly.
636 *
637 * References:
638 * http://lkml.org/lkml/2008/10/1/246
639 * http://kb.vmware.com/kb/1009458
640 */
641 cp.cp_eax = 0x1;
642 (void) __cpuid_insn(&cp);
643 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
644 cp.cp_eax = 0x40000000;
645 (void) __cpuid_insn(&cp);
646 regs[0] = cp.cp_ebx;
647 regs[1] = cp.cp_ecx;
648 regs[2] = cp.cp_edx;
649 regs[3] = 0;
650 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
651 platform_type = HW_XEN_HVM;
652 return;
653 }
654 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
655 platform_type = HW_VMWARE;
656 return;
657 }
658 if (strcmp(hvstr, HVSIG_KVM) == 0) {
659 platform_type = HW_KVM;
660 return;
661 }
662 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
663 platform_type = HW_MICROSOFT;
664 } else {
665 /*
666 * Check older VMware hardware versions. VMware hypervisor is
667 * detected by performing an IN operation to VMware hypervisor
668 * port and checking that value returned in %ebx is VMware
669 * hypervisor magic value.
670 *
671 * References: http://kb.vmware.com/kb/1009458
672 */
673 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
674 if (regs[1] == VMWARE_HVMAGIC) {
675 platform_type = HW_VMWARE;
676 return;
677 }
678 }
679
680 /*
681 * Check Xen hypervisor. In a fully virtualized domain,
682 * Xen's pseudo-cpuid function returns a string representing the
683 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
684 * supported cpuid function. We need at least a (base + 2) leaf value
685 * to do what we want to do. Try different base values, since the
686 * hypervisor might use a different one depending on whether Hyper-V
687 * emulation is switched on by default or not.
688 */
689 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
690 cp.cp_eax = base;
691 (void) __cpuid_insn(&cp);
692 regs[0] = cp.cp_ebx;
693 regs[1] = cp.cp_ecx;
694 regs[2] = cp.cp_edx;
695 regs[3] = 0;
696 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
697 cp.cp_eax >= (base + 2)) {
698 platform_type &= ~HW_NATIVE;
699 platform_type |= HW_XEN_HVM;
700 return;
701 }
702 }
703 }
704
705 int
706 get_hwenv(void)
707 {
708 ASSERT(platform_type != -1);
709 return (platform_type);
710 }
711
712 int
713 is_controldom(void)
714 {
715 return (0);
716 }
717
718 #else
719
720 int
721 get_hwenv(void)
722 {
723 return (HW_XEN_PV);
724 }
725
726 int
727 is_controldom(void)
728 {
729 return (DOMAIN_IS_INITDOMAIN(xen_info));
730 }
731
732 #endif /* __xpv */
733
734 static void
735 cpuid_intel_getids(cpu_t *cpu, void *feature)
736 {
737 uint_t i;
738 uint_t chipid_shift = 0;
739 uint_t coreid_shift = 0;
740 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
741
742 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
743 chipid_shift++;
744
745 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
746 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
747
748 if (is_x86_feature(feature, X86FSET_CMP)) {
749 /*
750 * Multi-core (and possibly multi-threaded)
751 * processors.
752 */
753 uint_t ncpu_per_core;
754 if (cpi->cpi_ncore_per_chip == 1)
755 ncpu_per_core = cpi->cpi_ncpu_per_chip;
756 else if (cpi->cpi_ncore_per_chip > 1)
757 ncpu_per_core = cpi->cpi_ncpu_per_chip /
758 cpi->cpi_ncore_per_chip;
759 /*
760 * 8bit APIC IDs on dual core Pentiums
761 * look like this:
762 *
763 * +-----------------------+------+------+
764 * | Physical Package ID | MC | HT |
765 * +-----------------------+------+------+
766 * <------- chipid -------->
767 * <------- coreid --------------->
768 * <--- clogid -->
769 * <------>
770 * pkgcoreid
771 *
772 * Where the number of bits necessary to
773 * represent MC and HT fields together equals
774 * to the minimum number of bits necessary to
775 * store the value of cpi->cpi_ncpu_per_chip.
776 * Of those bits, the MC part uses the number
777 * of bits necessary to store the value of
778 * cpi->cpi_ncore_per_chip.
779 */
780 for (i = 1; i < ncpu_per_core; i <<= 1)
781 coreid_shift++;
782 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
783 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
784 } else if (is_x86_feature(feature, X86FSET_HTT)) {
785 /*
786 * Single-core multi-threaded processors.
787 */
788 cpi->cpi_coreid = cpi->cpi_chipid;
789 cpi->cpi_pkgcoreid = 0;
790 }
791 cpi->cpi_procnodeid = cpi->cpi_chipid;
792 cpi->cpi_compunitid = cpi->cpi_coreid;
793 }
794
795 static void
796 cpuid_amd_getids(cpu_t *cpu)
797 {
798 int i, first_half, coreidsz;
799 uint32_t nb_caps_reg;
800 uint_t node2_1;
801 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
802 struct cpuid_regs *cp;
803
804 /*
805 * AMD CMP chips currently have a single thread per core.
806 *
807 * Since no two cpus share a core we must assign a distinct coreid
808 * per cpu, and we do this by using the cpu_id. This scheme does not,
809 * however, guarantee that sibling cores of a chip will have sequential
810 * coreids starting at a multiple of the number of cores per chip -
811 * that is usually the case, but if the ACPI MADT table is presented
812 * in a different order then we need to perform a few more gymnastics
813 * for the pkgcoreid.
814 *
815 * All processors in the system have the same number of enabled
816 * cores. Cores within a processor are always numbered sequentially
817 * from 0 regardless of how many or which are disabled, and there
818 * is no way for operating system to discover the real core id when some
819 * are disabled.
820 *
821 * In family 0x15, the cores come in pairs called compute units. They
822 * share I$ and L2 caches and the FPU. Enumeration of this feature is
823 * simplified by the new topology extensions CPUID leaf, indicated by
824 * the X86 feature X86FSET_TOPOEXT.
825 */
826
827 cpi->cpi_coreid = cpu->cpu_id;
828 cpi->cpi_compunitid = cpu->cpu_id;
829
830 if (cpi->cpi_xmaxeax >= 0x80000008) {
831
832 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
833
834 /*
835 * In AMD parlance chip is really a node while Solaris
836 * sees chip as equivalent to socket/package.
837 */
838 cpi->cpi_ncore_per_chip =
839 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
840 if (coreidsz == 0) {
841 /* Use legacy method */
842 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
843 coreidsz++;
844 if (coreidsz == 0)
845 coreidsz = 1;
846 }
847 } else {
848 /* Assume single-core part */
849 cpi->cpi_ncore_per_chip = 1;
850 coreidsz = 1;
851 }
852
853 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
854 cpi->cpi_apicid & ((1<<coreidsz) - 1);
855 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
856
857 /* Get node ID, compute unit ID */
858 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
859 cpi->cpi_xmaxeax >= 0x8000001e) {
860 cp = &cpi->cpi_extd[0x1e];
861 cp->cp_eax = 0x8000001e;
862 (void) __cpuid_insn(cp);
863
864 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
865 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
866 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
867 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
868 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
869 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
870 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
871 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
872 } else if (cpi->cpi_family == 0x10) {
873 /*
874 * See if we are a multi-node processor.
875 * All processors in the system have the same number of nodes
876 */
877 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
878 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
879 /* Single-node */
880 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
881 coreidsz);
882 } else {
883
884 /*
885 * Multi-node revision D (2 nodes per package
886 * are supported)
887 */
888 cpi->cpi_procnodes_per_pkg = 2;
889
890 first_half = (cpi->cpi_pkgcoreid <=
891 (cpi->cpi_ncore_per_chip/2 - 1));
892
893 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
894 /* We are BSP */
895 cpi->cpi_procnodeid = (first_half ? 0 : 1);
896 } else {
897
898 /* We are AP */
899 /* NodeId[2:1] bits to use for reading F3xe8 */
900 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
901
902 nb_caps_reg =
903 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
904
905 /*
906 * Check IntNodeNum bit (31:30, but bit 31 is
907 * always 0 on dual-node processors)
908 */
909 if (BITX(nb_caps_reg, 30, 30) == 0)
910 cpi->cpi_procnodeid = node2_1 +
911 !first_half;
912 else
913 cpi->cpi_procnodeid = node2_1 +
914 first_half;
915 }
916 }
917 } else {
918 cpi->cpi_procnodeid = 0;
919 }
920
921 cpi->cpi_chipid =
922 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
923 }
924
925 /*
926 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
927 */
928 void
929 setup_xfem(void)
930 {
931 uint64_t flags = XFEATURE_LEGACY_FP;
932
933 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
934
935 if (is_x86_feature(x86_featureset, X86FSET_SSE))
936 flags |= XFEATURE_SSE;
937
938 if (is_x86_feature(x86_featureset, X86FSET_AVX))
939 flags |= XFEATURE_AVX;
940
941 set_xcr(XFEATURE_ENABLED_MASK, flags);
942
943 xsave_bv_all = flags;
944 }
945
946 void
947 cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
948 {
949 uint32_t mask_ecx, mask_edx;
950 struct cpuid_info *cpi;
951 struct cpuid_regs *cp;
952 int xcpuid;
953 #if !defined(__xpv)
954 extern int idle_cpu_prefer_mwait;
955 #endif
956
957 /*
958 * Space statically allocated for BSP, ensure pointer is set
959 */
960 if (cpu->cpu_id == 0) {
961 if (cpu->cpu_m.mcpu_cpi == NULL)
962 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
963 }
964
965 add_x86_feature(featureset, X86FSET_CPUID);
966
967 cpi = cpu->cpu_m.mcpu_cpi;
968 ASSERT(cpi != NULL);
969 cp = &cpi->cpi_std[0];
970 cp->cp_eax = 0;
971 cpi->cpi_maxeax = __cpuid_insn(cp);
972 {
973 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
974 *iptr++ = cp->cp_ebx;
975 *iptr++ = cp->cp_edx;
976 *iptr++ = cp->cp_ecx;
977 *(char *)&cpi->cpi_vendorstr[12] = '\0';
978 }
979
980 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
981 x86_vendor = cpi->cpi_vendor; /* for compatibility */
982
983 /*
984 * Limit the range in case of weird hardware
985 */
986 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
987 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
988 if (cpi->cpi_maxeax < 1)
989 goto pass1_done;
990
991 cp = &cpi->cpi_std[1];
992 cp->cp_eax = 1;
993 (void) __cpuid_insn(cp);
994
995 /*
996 * Extract identifying constants for easy access.
997 */
998 cpi->cpi_model = CPI_MODEL(cpi);
999 cpi->cpi_family = CPI_FAMILY(cpi);
1000
1001 if (cpi->cpi_family == 0xf)
1002 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1003
1004 /*
1005 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
1006 * Intel, and presumably everyone else, uses model == 0xf, as
1007 * one would expect (max value means possible overflow). Sigh.
1008 */
1009
1010 switch (cpi->cpi_vendor) {
1011 case X86_VENDOR_Intel:
1012 if (IS_EXTENDED_MODEL_INTEL(cpi))
1013 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1014 break;
1015 case X86_VENDOR_AMD:
1016 if (CPI_FAMILY(cpi) == 0xf)
1017 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1018 break;
1019 default:
1020 if (cpi->cpi_model == 0xf)
1021 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1022 break;
1023 }
1024
1025 cpi->cpi_step = CPI_STEP(cpi);
1026 cpi->cpi_brandid = CPI_BRANDID(cpi);
1027
1028 /*
1029 * *default* assumptions:
1030 * - believe %edx feature word
1031 * - ignore %ecx feature word
1032 * - 32-bit virtual and physical addressing
1033 */
1034 mask_edx = 0xffffffff;
1035 mask_ecx = 0;
1036
1037 cpi->cpi_pabits = cpi->cpi_vabits = 32;
1038
1039 switch (cpi->cpi_vendor) {
1040 case X86_VENDOR_Intel:
1041 if (cpi->cpi_family == 5)
1042 x86_type = X86_TYPE_P5;
1043 else if (IS_LEGACY_P6(cpi)) {
1044 x86_type = X86_TYPE_P6;
1045 pentiumpro_bug4046376 = 1;
1046 /*
1047 * Clear the SEP bit when it was set erroneously
1048 */
1049 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
1050 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1051 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
1052 x86_type = X86_TYPE_P4;
1053 /*
1054 * We don't currently depend on any of the %ecx
1055 * features until Prescott, so we'll only check
1056 * this from P4 onwards. We might want to revisit
1057 * that idea later.
1058 */
1059 mask_ecx = 0xffffffff;
1060 } else if (cpi->cpi_family > 0xf)
1061 mask_ecx = 0xffffffff;
1062 /*
1063 * We don't support MONITOR/MWAIT if leaf 5 is not available
1064 * to obtain the monitor linesize.
1065 */
1066 if (cpi->cpi_maxeax < 5)
1067 mask_ecx &= ~CPUID_INTC_ECX_MON;
1068 break;
1069 case X86_VENDOR_IntelClone:
1070 default:
1071 break;
1072 case X86_VENDOR_AMD:
1073 #if defined(OPTERON_ERRATUM_108)
1074 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
1075 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
1076 cpi->cpi_model = 0xc;
1077 } else
1078 #endif
1079 if (cpi->cpi_family == 5) {
1080 /*
1081 * AMD K5 and K6
1082 *
1083 * These CPUs have an incomplete implementation
1084 * of MCA/MCE which we mask away.
1085 */
1086 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
1087
1088 /*
1089 * Model 0 uses the wrong (APIC) bit
1090 * to indicate PGE. Fix it here.
1091 */
1092 if (cpi->cpi_model == 0) {
1093 if (cp->cp_edx & 0x200) {
1094 cp->cp_edx &= ~0x200;
1095 cp->cp_edx |= CPUID_INTC_EDX_PGE;
1096 }
1097 }
1098
1099 /*
1100 * Early models had problems w/ MMX; disable.
1101 */
1102 if (cpi->cpi_model < 6)
1103 mask_edx &= ~CPUID_INTC_EDX_MMX;
1104 }
1105
1106 /*
1107 * For newer families, SSE3 and CX16, at least, are valid;
1108 * enable all
1109 */
1110 if (cpi->cpi_family >= 0xf)
1111 mask_ecx = 0xffffffff;
1112 /*
1113 * We don't support MONITOR/MWAIT if leaf 5 is not available
1114 * to obtain the monitor linesize.
1115 */
1116 if (cpi->cpi_maxeax < 5)
1117 mask_ecx &= ~CPUID_INTC_ECX_MON;
1118
1119 #if !defined(__xpv)
1120 /*
1121 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
1122 * processors. AMD does not intend MWAIT to be used in the cpu
1123 * idle loop on current and future processors. 10h and future
1124 * AMD processors use more power in MWAIT than HLT.
1125 * Pre-family-10h Opterons do not have the MWAIT instruction.
1126 */
1127 idle_cpu_prefer_mwait = 0;
1128 #endif
1129
1130 break;
1131 case X86_VENDOR_TM:
1132 /*
1133 * workaround the NT workaround in CMS 4.1
1134 */
1135 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
1136 (cpi->cpi_step == 2 || cpi->cpi_step == 3))
1137 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1138 break;
1139 case X86_VENDOR_Centaur:
1140 /*
1141 * workaround the NT workarounds again
1142 */
1143 if (cpi->cpi_family == 6)
1144 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1145 break;
1146 case X86_VENDOR_Cyrix:
1147 /*
1148 * We rely heavily on the probing in locore
1149 * to actually figure out what parts, if any,
1150 * of the Cyrix cpuid instruction to believe.
1151 */
1152 switch (x86_type) {
1153 case X86_TYPE_CYRIX_486:
1154 mask_edx = 0;
1155 break;
1156 case X86_TYPE_CYRIX_6x86:
1157 mask_edx = 0;
1158 break;
1159 case X86_TYPE_CYRIX_6x86L:
1160 mask_edx =
1161 CPUID_INTC_EDX_DE |
1162 CPUID_INTC_EDX_CX8;
1163 break;
1164 case X86_TYPE_CYRIX_6x86MX:
1165 mask_edx =
1166 CPUID_INTC_EDX_DE |
1167 CPUID_INTC_EDX_MSR |
1168 CPUID_INTC_EDX_CX8 |
1169 CPUID_INTC_EDX_PGE |
1170 CPUID_INTC_EDX_CMOV |
1171 CPUID_INTC_EDX_MMX;
1172 break;
1173 case X86_TYPE_CYRIX_GXm:
1174 mask_edx =
1175 CPUID_INTC_EDX_MSR |
1176 CPUID_INTC_EDX_CX8 |
1177 CPUID_INTC_EDX_CMOV |
1178 CPUID_INTC_EDX_MMX;
1179 break;
1180 case X86_TYPE_CYRIX_MediaGX:
1181 break;
1182 case X86_TYPE_CYRIX_MII:
1183 case X86_TYPE_VIA_CYRIX_III:
1184 mask_edx =
1185 CPUID_INTC_EDX_DE |
1186 CPUID_INTC_EDX_TSC |
1187 CPUID_INTC_EDX_MSR |
1188 CPUID_INTC_EDX_CX8 |
1189 CPUID_INTC_EDX_PGE |
1190 CPUID_INTC_EDX_CMOV |
1191 CPUID_INTC_EDX_MMX;
1192 break;
1193 default:
1194 break;
1195 }
1196 break;
1197 }
1198
1199 #if defined(__xpv)
1200 /*
1201 * Do not support MONITOR/MWAIT under a hypervisor
1202 */
1203 mask_ecx &= ~CPUID_INTC_ECX_MON;
1204 /*
1205 * Do not support XSAVE under a hypervisor for now
1206 */
1207 xsave_force_disable = B_TRUE;
1208
1209 #endif /* __xpv */
1210
1211 if (xsave_force_disable) {
1212 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
1213 mask_ecx &= ~CPUID_INTC_ECX_AVX;
1214 mask_ecx &= ~CPUID_INTC_ECX_F16C;
1215 mask_ecx &= ~CPUID_INTC_ECX_FMA;
1216 }
1217
1218 /*
1219 * Now we've figured out the masks that determine
1220 * which bits we choose to believe, apply the masks
1221 * to the feature words, then map the kernel's view
1222 * of these feature words into its feature word.
1223 */
1224 cp->cp_edx &= mask_edx;
1225 cp->cp_ecx &= mask_ecx;
1226
1227 /*
1228 * apply any platform restrictions (we don't call this
1229 * immediately after __cpuid_insn here, because we need the
1230 * workarounds applied above first)
1231 */
1232 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
1233
1234 /*
1235 * In addition to ecx and edx, Intel is storing a bunch of instruction
1236 * set extensions in leaf 7's ebx.
1237 */
1238 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) {
1239 struct cpuid_regs *ecp;
1240 ecp = &cpi->cpi_std[7];
1241 ecp->cp_eax = 7;
1242 ecp->cp_ecx = 0;
1243 (void) __cpuid_insn(ecp);
1244 /*
1245 * If XSAVE has been disabled, just ignore all of the AVX
1246 * dependent flags here.
1247 */
1248 if (xsave_force_disable) {
1249 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
1250 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
1252 }
1253
1254 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
1255 add_x86_feature(featureset, X86FSET_SMEP);
1256
1257 /*
1258 * We check disable_smap here in addition to in startup_smap()
1259 * to ensure CPUs that aren't the boot CPU don't accidentally
1260 * include it in the feature set and thus generate a mismatched
1261 * x86 feature set across CPUs. Note that at this time we only
1262 * enable SMAP for the 64-bit kernel.
1263 */
1264 #if defined(__amd64)
1265 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMAP &&
1266 disable_smap == 0)
1267 add_x86_feature(featureset, X86FSET_SMAP);
1268 #endif
1269 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED)
1270 add_x86_feature(featureset, X86FSET_RDSEED);
1271
1272 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX)
1273 add_x86_feature(featureset, X86FSET_ADX);
1274 }
1275
1276 /*
1277 * fold in overrides from the "eeprom" mechanism
1278 */
1279 cp->cp_edx |= cpuid_feature_edx_include;
1280 cp->cp_edx &= ~cpuid_feature_edx_exclude;
1281
1282 cp->cp_ecx |= cpuid_feature_ecx_include;
1283 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
1284
1285 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
1286 add_x86_feature(featureset, X86FSET_LARGEPAGE);
1287 }
1288 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
1289 add_x86_feature(featureset, X86FSET_TSC);
1290 }
1291 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
1292 add_x86_feature(featureset, X86FSET_MSR);
1293 }
1294 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
1295 add_x86_feature(featureset, X86FSET_MTRR);
1296 }
1297 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
1298 add_x86_feature(featureset, X86FSET_PGE);
1299 }
1300 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
1301 add_x86_feature(featureset, X86FSET_CMOV);
1302 }
1303 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
1304 add_x86_feature(featureset, X86FSET_MMX);
1305 }
1306 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
1307 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
1308 add_x86_feature(featureset, X86FSET_MCA);
1309 }
1310 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
1311 add_x86_feature(featureset, X86FSET_PAE);
1312 }
1313 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
1314 add_x86_feature(featureset, X86FSET_CX8);
1315 }
1316 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
1317 add_x86_feature(featureset, X86FSET_CX16);
1318 }
1319 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
1320 add_x86_feature(featureset, X86FSET_PAT);
1321 }
1322 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
1323 add_x86_feature(featureset, X86FSET_SEP);
1324 }
1325 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
1326 /*
1327 * In our implementation, fxsave/fxrstor
1328 * are prerequisites before we'll even
1329 * try and do SSE things.
1330 */
1331 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
1332 add_x86_feature(featureset, X86FSET_SSE);
1333 }
1334 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
1335 add_x86_feature(featureset, X86FSET_SSE2);
1336 }
1337 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
1338 add_x86_feature(featureset, X86FSET_SSE3);
1339 }
1340 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
1341 add_x86_feature(featureset, X86FSET_SSSE3);
1342 }
1343 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
1344 add_x86_feature(featureset, X86FSET_SSE4_1);
1345 }
1346 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
1347 add_x86_feature(featureset, X86FSET_SSE4_2);
1348 }
1349 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
1350 add_x86_feature(featureset, X86FSET_AES);
1351 }
1352 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
1353 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
1354 }
1355
1356 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
1357 add_x86_feature(featureset, X86FSET_XSAVE);
1358
1359 /* We only test AVX when there is XSAVE */
1360 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
1361 add_x86_feature(featureset,
1362 X86FSET_AVX);
1363
1364 /*
1365 * Intel says we can't check these without also
1366 * checking AVX.
1367 */
1368 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
1369 add_x86_feature(featureset,
1370 X86FSET_F16C);
1371
1372 if (cp->cp_ecx & CPUID_INTC_ECX_FMA)
1373 add_x86_feature(featureset,
1374 X86FSET_FMA);
1375
1376 if (cpi->cpi_std[7].cp_ebx &
1377 CPUID_INTC_EBX_7_0_BMI1)
1378 add_x86_feature(featureset,
1379 X86FSET_BMI1);
1380
1381 if (cpi->cpi_std[7].cp_ebx &
1382 CPUID_INTC_EBX_7_0_BMI2)
1383 add_x86_feature(featureset,
1384 X86FSET_BMI2);
1385
1386 if (cpi->cpi_std[7].cp_ebx &
1387 CPUID_INTC_EBX_7_0_AVX2)
1388 add_x86_feature(featureset,
1389 X86FSET_AVX2);
1390 }
1391 }
1392 }
1393 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
1394 add_x86_feature(featureset, X86FSET_X2APIC);
1395 }
1396 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
1397 add_x86_feature(featureset, X86FSET_DE);
1398 }
1399 #if !defined(__xpv)
1400 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
1401
1402 /*
1403 * We require the CLFLUSH instruction for erratum workaround
1404 * to use MONITOR/MWAIT.
1405 */
1406 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1407 cpi->cpi_mwait.support |= MWAIT_SUPPORT;
1408 add_x86_feature(featureset, X86FSET_MWAIT);
1409 } else {
1410 extern int idle_cpu_assert_cflush_monitor;
1411
1412 /*
1413 * All processors we are aware of which have
1414 * MONITOR/MWAIT also have CLFLUSH.
1415 */
1416 if (idle_cpu_assert_cflush_monitor) {
1417 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
1418 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
1419 }
1420 }
1421 }
1422 #endif /* __xpv */
1423
1424 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
1425 add_x86_feature(featureset, X86FSET_VMX);
1426 }
1427
1428 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
1429 add_x86_feature(featureset, X86FSET_RDRAND);
1430
1431 /*
1432 * Only need it first time, rest of the cpus would follow suit.
1433 * we only capture this for the bootcpu.
1434 */
1435 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1436 add_x86_feature(featureset, X86FSET_CLFSH);
1437 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
1438 }
1439 if (is_x86_feature(featureset, X86FSET_PAE))
1440 cpi->cpi_pabits = 36;
1441
1442 /*
1443 * Hyperthreading configuration is slightly tricky on Intel
1444 * and pure clones, and even trickier on AMD.
1445 *
1446 * (AMD chose to set the HTT bit on their CMP processors,
1447 * even though they're not actually hyperthreaded. Thus it
1448 * takes a bit more work to figure out what's really going
1449 * on ... see the handling of the CMP_LGCY bit below)
1450 */
1451 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
1452 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
1453 if (cpi->cpi_ncpu_per_chip > 1)
1454 add_x86_feature(featureset, X86FSET_HTT);
1455 } else {
1456 cpi->cpi_ncpu_per_chip = 1;
1457 }
1458
1459 /*
1460 * Work on the "extended" feature information, doing
1461 * some basic initialization for cpuid_pass2()
1462 */
1463 xcpuid = 0;
1464 switch (cpi->cpi_vendor) {
1465 case X86_VENDOR_Intel:
1466 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
1467 xcpuid++;
1468 break;
1469 case X86_VENDOR_AMD:
1470 if (cpi->cpi_family > 5 ||
1471 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
1472 xcpuid++;
1473 break;
1474 case X86_VENDOR_Cyrix:
1475 /*
1476 * Only these Cyrix CPUs are -known- to support
1477 * extended cpuid operations.
1478 */
1479 if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1480 x86_type == X86_TYPE_CYRIX_GXm)
1481 xcpuid++;
1482 break;
1483 case X86_VENDOR_Centaur:
1484 case X86_VENDOR_TM:
1485 default:
1486 xcpuid++;
1487 break;
1488 }
1489
1490 if (xcpuid) {
1491 cp = &cpi->cpi_extd[0];
1492 cp->cp_eax = 0x80000000;
1493 cpi->cpi_xmaxeax = __cpuid_insn(cp);
1494 }
1495
1496 if (cpi->cpi_xmaxeax & 0x80000000) {
1497
1498 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1499 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1500
1501 switch (cpi->cpi_vendor) {
1502 case X86_VENDOR_Intel:
1503 case X86_VENDOR_AMD:
1504 if (cpi->cpi_xmaxeax < 0x80000001)
1505 break;
1506 cp = &cpi->cpi_extd[1];
1507 cp->cp_eax = 0x80000001;
1508 (void) __cpuid_insn(cp);
1509
1510 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1511 cpi->cpi_family == 5 &&
1512 cpi->cpi_model == 6 &&
1513 cpi->cpi_step == 6) {
1514 /*
1515 * K6 model 6 uses bit 10 to indicate SYSC
1516 * Later models use bit 11. Fix it here.
1517 */
1518 if (cp->cp_edx & 0x400) {
1519 cp->cp_edx &= ~0x400;
1520 cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1521 }
1522 }
1523
1524 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1525
1526 /*
1527 * Compute the additions to the kernel's feature word.
1528 */
1529 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
1530 add_x86_feature(featureset, X86FSET_NX);
1531 }
1532
1533 /*
1534 * Regardless whether or not we boot 64-bit,
1535 * we should have a way to identify whether
1536 * the CPU is capable of running 64-bit.
1537 */
1538 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
1539 add_x86_feature(featureset, X86FSET_64);
1540 }
1541
1542 #if defined(__amd64)
1543 /* 1 GB large page - enable only for 64 bit kernel */
1544 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
1545 add_x86_feature(featureset, X86FSET_1GPG);
1546 }
1547 #endif
1548
1549 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1550 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1551 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
1552 add_x86_feature(featureset, X86FSET_SSE4A);
1553 }
1554
1555 /*
1556 * If both the HTT and CMP_LGCY bits are set,
1557 * then we're not actually HyperThreaded. Read
1558 * "AMD CPUID Specification" for more details.
1559 */
1560 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1561 is_x86_feature(featureset, X86FSET_HTT) &&
1562 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1563 remove_x86_feature(featureset, X86FSET_HTT);
1564 add_x86_feature(featureset, X86FSET_CMP);
1565 }
1566 #if defined(__amd64)
1567 /*
1568 * It's really tricky to support syscall/sysret in
1569 * the i386 kernel; we rely on sysenter/sysexit
1570 * instead. In the amd64 kernel, things are -way-
1571 * better.
1572 */
1573 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1574 add_x86_feature(featureset, X86FSET_ASYSC);
1575 }
1576
1577 /*
1578 * While we're thinking about system calls, note
1579 * that AMD processors don't support sysenter
1580 * in long mode at all, so don't try to program them.
1581 */
1582 if (x86_vendor == X86_VENDOR_AMD) {
1583 remove_x86_feature(featureset, X86FSET_SEP);
1584 }
1585 #endif
1586 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1587 add_x86_feature(featureset, X86FSET_TSCP);
1588 }
1589
1590 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1591 add_x86_feature(featureset, X86FSET_SVM);
1592 }
1593
1594 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1595 add_x86_feature(featureset, X86FSET_TOPOEXT);
1596 }
1597 break;
1598 default:
1599 break;
1600 }
1601
1602 /*
1603 * Get CPUID data about processor cores and hyperthreads.
1604 */
1605 switch (cpi->cpi_vendor) {
1606 case X86_VENDOR_Intel:
1607 if (cpi->cpi_maxeax >= 4) {
1608 cp = &cpi->cpi_std[4];
1609 cp->cp_eax = 4;
1610 cp->cp_ecx = 0;
1611 (void) __cpuid_insn(cp);
1612 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1613 }
1614 /*FALLTHROUGH*/
1615 case X86_VENDOR_AMD:
1616 if (cpi->cpi_xmaxeax < 0x80000008)
1617 break;
1618 cp = &cpi->cpi_extd[8];
1619 cp->cp_eax = 0x80000008;
1620 (void) __cpuid_insn(cp);
1621 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1622
1623 /*
1624 * Virtual and physical address limits from
1625 * cpuid override previously guessed values.
1626 */
1627 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1628 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1629 break;
1630 default:
1631 break;
1632 }
1633
1634 /*
1635 * Derive the number of cores per chip
1636 */
1637 switch (cpi->cpi_vendor) {
1638 case X86_VENDOR_Intel:
1639 if (cpi->cpi_maxeax < 4) {
1640 cpi->cpi_ncore_per_chip = 1;
1641 break;
1642 } else {
1643 cpi->cpi_ncore_per_chip =
1644 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1645 }
1646 break;
1647 case X86_VENDOR_AMD:
1648 if (cpi->cpi_xmaxeax < 0x80000008) {
1649 cpi->cpi_ncore_per_chip = 1;
1650 break;
1651 } else {
1652 /*
1653 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1654 * 1 less than the number of physical cores on
1655 * the chip. In family 0x10 this value can
1656 * be affected by "downcoring" - it reflects
1657 * 1 less than the number of cores actually
1658 * enabled on this node.
1659 */
1660 cpi->cpi_ncore_per_chip =
1661 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1662 }
1663 break;
1664 default:
1665 cpi->cpi_ncore_per_chip = 1;
1666 break;
1667 }
1668
1669 /*
1670 * Get CPUID data about TSC Invariance in Deep C-State.
1671 */
1672 switch (cpi->cpi_vendor) {
1673 case X86_VENDOR_Intel:
1674 if (cpi->cpi_maxeax >= 7) {
1675 cp = &cpi->cpi_extd[7];
1676 cp->cp_eax = 0x80000007;
1677 cp->cp_ecx = 0;
1678 (void) __cpuid_insn(cp);
1679 }
1680 break;
1681 default:
1682 break;
1683 }
1684 } else {
1685 cpi->cpi_ncore_per_chip = 1;
1686 }
1687
1688 /*
1689 * If more than one core, then this processor is CMP.
1690 */
1691 if (cpi->cpi_ncore_per_chip > 1) {
1692 add_x86_feature(featureset, X86FSET_CMP);
1693 }
1694
1695 /*
1696 * If the number of cores is the same as the number
1697 * of CPUs, then we cannot have HyperThreading.
1698 */
1699 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1700 remove_x86_feature(featureset, X86FSET_HTT);
1701 }
1702
1703 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1704 cpi->cpi_procnodes_per_pkg = 1;
1705 cpi->cpi_cores_per_compunit = 1;
1706 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1707 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1708 /*
1709 * Single-core single-threaded processors.
1710 */
1711 cpi->cpi_chipid = -1;
1712 cpi->cpi_clogid = 0;
1713 cpi->cpi_coreid = cpu->cpu_id;
1714 cpi->cpi_pkgcoreid = 0;
1715 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1716 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1717 else
1718 cpi->cpi_procnodeid = cpi->cpi_chipid;
1719 } else if (cpi->cpi_ncpu_per_chip > 1) {
1720 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1721 cpuid_intel_getids(cpu, featureset);
1722 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1723 cpuid_amd_getids(cpu);
1724 else {
1725 /*
1726 * All other processors are currently
1727 * assumed to have single cores.
1728 */
1729 cpi->cpi_coreid = cpi->cpi_chipid;
1730 cpi->cpi_pkgcoreid = 0;
1731 cpi->cpi_procnodeid = cpi->cpi_chipid;
1732 cpi->cpi_compunitid = cpi->cpi_chipid;
1733 }
1734 }
1735
1736 /*
1737 * Synthesize chip "revision" and socket type
1738 */
1739 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1740 cpi->cpi_model, cpi->cpi_step);
1741 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1742 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1743 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1744 cpi->cpi_model, cpi->cpi_step);
1745
1746 pass1_done:
1747 cpi->cpi_pass = 1;
1748 }
1749
1750 /*
1751 * Make copies of the cpuid table entries we depend on, in
1752 * part for ease of parsing now, in part so that we have only
1753 * one place to correct any of it, in part for ease of
1754 * later export to userland, and in part so we can look at
1755 * this stuff in a crash dump.
1756 */
1757
1758 /*ARGSUSED*/
1759 void
1760 cpuid_pass2(cpu_t *cpu)
1761 {
1762 uint_t n, nmax;
1763 int i;
1764 struct cpuid_regs *cp;
1765 uint8_t *dp;
1766 uint32_t *iptr;
1767 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1768
1769 ASSERT(cpi->cpi_pass == 1);
1770
1771 if (cpi->cpi_maxeax < 1)
1772 goto pass2_done;
1773
1774 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1775 nmax = NMAX_CPI_STD;
1776 /*
1777 * (We already handled n == 0 and n == 1 in pass 1)
1778 */
1779 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1780 cp->cp_eax = n;
1781
1782 /*
1783 * CPUID function 4 expects %ecx to be initialized
1784 * with an index which indicates which cache to return
1785 * information about. The OS is expected to call function 4
1786 * with %ecx set to 0, 1, 2, ... until it returns with
1787 * EAX[4:0] set to 0, which indicates there are no more
1788 * caches.
1789 *
1790 * Here, populate cpi_std[4] with the information returned by
1791 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1792 * when dynamic memory allocation becomes available.
1793 *
1794 * Note: we need to explicitly initialize %ecx here, since
1795 * function 4 may have been previously invoked.
1796 */
1797 if (n == 4)
1798 cp->cp_ecx = 0;
1799
1800 (void) __cpuid_insn(cp);
1801 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1802 switch (n) {
1803 case 2:
1804 /*
1805 * "the lower 8 bits of the %eax register
1806 * contain a value that identifies the number
1807 * of times the cpuid [instruction] has to be
1808 * executed to obtain a complete image of the
1809 * processor's caching systems."
1810 *
1811 * How *do* they make this stuff up?
1812 */
1813 cpi->cpi_ncache = sizeof (*cp) *
1814 BITX(cp->cp_eax, 7, 0);
1815 if (cpi->cpi_ncache == 0)
1816 break;
1817 cpi->cpi_ncache--; /* skip count byte */
1818
1819 /*
1820 * Well, for now, rather than attempt to implement
1821 * this slightly dubious algorithm, we just look
1822 * at the first 15 ..
1823 */
1824 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1825 cpi->cpi_ncache = sizeof (*cp) - 1;
1826
1827 dp = cpi->cpi_cacheinfo;
1828 if (BITX(cp->cp_eax, 31, 31) == 0) {
1829 uint8_t *p = (void *)&cp->cp_eax;
1830 for (i = 1; i < 4; i++)
1831 if (p[i] != 0)
1832 *dp++ = p[i];
1833 }
1834 if (BITX(cp->cp_ebx, 31, 31) == 0) {
1835 uint8_t *p = (void *)&cp->cp_ebx;
1836 for (i = 0; i < 4; i++)
1837 if (p[i] != 0)
1838 *dp++ = p[i];
1839 }
1840 if (BITX(cp->cp_ecx, 31, 31) == 0) {
1841 uint8_t *p = (void *)&cp->cp_ecx;
1842 for (i = 0; i < 4; i++)
1843 if (p[i] != 0)
1844 *dp++ = p[i];
1845 }
1846 if (BITX(cp->cp_edx, 31, 31) == 0) {
1847 uint8_t *p = (void *)&cp->cp_edx;
1848 for (i = 0; i < 4; i++)
1849 if (p[i] != 0)
1850 *dp++ = p[i];
1851 }
1852 break;
1853
1854 case 3: /* Processor serial number, if PSN supported */
1855 break;
1856
1857 case 4: /* Deterministic cache parameters */
1858 break;
1859
1860 case 5: /* Monitor/Mwait parameters */
1861 {
1862 size_t mwait_size;
1863
1864 /*
1865 * check cpi_mwait.support which was set in cpuid_pass1
1866 */
1867 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
1868 break;
1869
1870 /*
1871 * Protect ourself from insane mwait line size.
1872 * Workaround for incomplete hardware emulator(s).
1873 */
1874 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
1875 if (mwait_size < sizeof (uint32_t) ||
1876 !ISP2(mwait_size)) {
1877 #if DEBUG
1878 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
1879 "size %ld", cpu->cpu_id, (long)mwait_size);
1880 #endif
1881 break;
1882 }
1883
1884 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
1885 cpi->cpi_mwait.mon_max = mwait_size;
1886 if (MWAIT_EXTENSION(cpi)) {
1887 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
1888 if (MWAIT_INT_ENABLE(cpi))
1889 cpi->cpi_mwait.support |=
1890 MWAIT_ECX_INT_ENABLE;
1891 }
1892 break;
1893 }
1894 default:
1895 break;
1896 }
1897 }
1898
1899 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
1900 struct cpuid_regs regs;
1901
1902 cp = ®s;
1903 cp->cp_eax = 0xB;
1904 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1905
1906 (void) __cpuid_insn(cp);
1907
1908 /*
1909 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
1910 * indicates that the extended topology enumeration leaf is
1911 * available.
1912 */
1913 if (cp->cp_ebx) {
1914 uint32_t x2apic_id;
1915 uint_t coreid_shift = 0;
1916 uint_t ncpu_per_core = 1;
1917 uint_t chipid_shift = 0;
1918 uint_t ncpu_per_chip = 1;
1919 uint_t i;
1920 uint_t level;
1921
1922 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
1923 cp->cp_eax = 0xB;
1924 cp->cp_ecx = i;
1925
1926 (void) __cpuid_insn(cp);
1927 level = CPI_CPU_LEVEL_TYPE(cp);
1928
1929 if (level == 1) {
1930 x2apic_id = cp->cp_edx;
1931 coreid_shift = BITX(cp->cp_eax, 4, 0);
1932 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
1933 } else if (level == 2) {
1934 x2apic_id = cp->cp_edx;
1935 chipid_shift = BITX(cp->cp_eax, 4, 0);
1936 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
1937 }
1938 }
1939
1940 cpi->cpi_apicid = x2apic_id;
1941 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
1942 cpi->cpi_ncore_per_chip = ncpu_per_chip /
1943 ncpu_per_core;
1944 cpi->cpi_chipid = x2apic_id >> chipid_shift;
1945 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
1946 cpi->cpi_coreid = x2apic_id >> coreid_shift;
1947 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
1948 }
1949
1950 /* Make cp NULL so that we don't stumble on others */
1951 cp = NULL;
1952 }
1953
1954 /*
1955 * XSAVE enumeration
1956 */
1957 if (cpi->cpi_maxeax >= 0xD) {
1958 struct cpuid_regs regs;
1959 boolean_t cpuid_d_valid = B_TRUE;
1960
1961 cp = ®s;
1962 cp->cp_eax = 0xD;
1963 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1964
1965 (void) __cpuid_insn(cp);
1966
1967 /*
1968 * Sanity checks for debug
1969 */
1970 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 ||
1971 (cp->cp_eax & XFEATURE_SSE) == 0) {
1972 cpuid_d_valid = B_FALSE;
1973 }
1974
1975 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
1976 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
1977 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
1978
1979 /*
1980 * If the hw supports AVX, get the size and offset in the save
1981 * area for the ymm state.
1982 */
1983 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
1984 cp->cp_eax = 0xD;
1985 cp->cp_ecx = 2;
1986 cp->cp_edx = cp->cp_ebx = 0;
1987
1988 (void) __cpuid_insn(cp);
1989
1990 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET ||
1991 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
1992 cpuid_d_valid = B_FALSE;
1993 }
1994
1995 cpi->cpi_xsave.ymm_size = cp->cp_eax;
1996 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
1997 }
1998
1999 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
2000 xsave_state_size = 0;
2001 } else if (cpuid_d_valid) {
2002 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
2003 } else {
2004 /* Broken CPUID 0xD, probably in HVM */
2005 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
2006 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
2007 ", ymm_size = %d, ymm_offset = %d\n",
2008 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
2009 cpi->cpi_xsave.xsav_hw_features_high,
2010 (int)cpi->cpi_xsave.xsav_max_size,
2011 (int)cpi->cpi_xsave.ymm_size,
2012 (int)cpi->cpi_xsave.ymm_offset);
2013
2014 if (xsave_state_size != 0) {
2015 /*
2016 * This must be a non-boot CPU. We cannot
2017 * continue, because boot cpu has already
2018 * enabled XSAVE.
2019 */
2020 ASSERT(cpu->cpu_id != 0);
2021 cmn_err(CE_PANIC, "cpu%d: we have already "
2022 "enabled XSAVE on boot cpu, cannot "
2023 "continue.", cpu->cpu_id);
2024 } else {
2025 /*
2026 * If we reached here on the boot CPU, it's also
2027 * almost certain that we'll reach here on the
2028 * non-boot CPUs. When we're here on a boot CPU
2029 * we should disable the feature, on a non-boot
2030 * CPU we need to confirm that we have.
2031 */
2032 if (cpu->cpu_id == 0) {
2033 remove_x86_feature(x86_featureset,
2034 X86FSET_XSAVE);
2035 remove_x86_feature(x86_featureset,
2036 X86FSET_AVX);
2037 remove_x86_feature(x86_featureset,
2038 X86FSET_F16C);
2039 remove_x86_feature(x86_featureset,
2040 X86FSET_BMI1);
2041 remove_x86_feature(x86_featureset,
2042 X86FSET_BMI2);
2043 remove_x86_feature(x86_featureset,
2044 X86FSET_FMA);
2045 remove_x86_feature(x86_featureset,
2046 X86FSET_AVX2);
2047 CPI_FEATURES_ECX(cpi) &=
2048 ~CPUID_INTC_ECX_XSAVE;
2049 CPI_FEATURES_ECX(cpi) &=
2050 ~CPUID_INTC_ECX_AVX;
2051 CPI_FEATURES_ECX(cpi) &=
2052 ~CPUID_INTC_ECX_F16C;
2053 CPI_FEATURES_ECX(cpi) &=
2054 ~CPUID_INTC_ECX_FMA;
2055 CPI_FEATURES_7_0_EBX(cpi) &=
2056 ~CPUID_INTC_EBX_7_0_BMI1;
2057 CPI_FEATURES_7_0_EBX(cpi) &=
2058 ~CPUID_INTC_EBX_7_0_BMI2;
2059 CPI_FEATURES_7_0_EBX(cpi) &=
2060 ~CPUID_INTC_EBX_7_0_AVX2;
2061 xsave_force_disable = B_TRUE;
2062 } else {
2063 VERIFY(is_x86_feature(x86_featureset,
2064 X86FSET_XSAVE) == B_FALSE);
2065 }
2066 }
2067 }
2068 }
2069
2070
2071 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
2072 goto pass2_done;
2073
2074 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
2075 nmax = NMAX_CPI_EXTD;
2076 /*
2077 * Copy the extended properties, fixing them as we go.
2078 * (We already handled n == 0 and n == 1 in pass 1)
2079 */
2080 iptr = (void *)cpi->cpi_brandstr;
2081 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
2082 cp->cp_eax = 0x80000000 + n;
2083 (void) __cpuid_insn(cp);
2084 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
2085 switch (n) {
2086 case 2:
2087 case 3:
2088 case 4:
2089 /*
2090 * Extract the brand string
2091 */
2092 *iptr++ = cp->cp_eax;
2093 *iptr++ = cp->cp_ebx;
2094 *iptr++ = cp->cp_ecx;
2095 *iptr++ = cp->cp_edx;
2096 break;
2097 case 5:
2098 switch (cpi->cpi_vendor) {
2099 case X86_VENDOR_AMD:
2100 /*
2101 * The Athlon and Duron were the first
2102 * parts to report the sizes of the
2103 * TLB for large pages. Before then,
2104 * we don't trust the data.
2105 */
2106 if (cpi->cpi_family < 6 ||
2107 (cpi->cpi_family == 6 &&
2108 cpi->cpi_model < 1))
2109 cp->cp_eax = 0;
2110 break;
2111 default:
2112 break;
2113 }
2114 break;
2115 case 6:
2116 switch (cpi->cpi_vendor) {
2117 case X86_VENDOR_AMD:
2118 /*
2119 * The Athlon and Duron were the first
2120 * AMD parts with L2 TLB's.
2121 * Before then, don't trust the data.
2122 */
2123 if (cpi->cpi_family < 6 ||
2124 cpi->cpi_family == 6 &&
2125 cpi->cpi_model < 1)
2126 cp->cp_eax = cp->cp_ebx = 0;
2127 /*
2128 * AMD Duron rev A0 reports L2
2129 * cache size incorrectly as 1K
2130 * when it is really 64K
2131 */
2132 if (cpi->cpi_family == 6 &&
2133 cpi->cpi_model == 3 &&
2134 cpi->cpi_step == 0) {
2135 cp->cp_ecx &= 0xffff;
2136 cp->cp_ecx |= 0x400000;
2137 }
2138 break;
2139 case X86_VENDOR_Cyrix: /* VIA C3 */
2140 /*
2141 * VIA C3 processors are a bit messed
2142 * up w.r.t. encoding cache sizes in %ecx
2143 */
2144 if (cpi->cpi_family != 6)
2145 break;
2146 /*
2147 * model 7 and 8 were incorrectly encoded
2148 *
2149 * xxx is model 8 really broken?
2150 */
2151 if (cpi->cpi_model == 7 ||
2152 cpi->cpi_model == 8)
2153 cp->cp_ecx =
2154 BITX(cp->cp_ecx, 31, 24) << 16 |
2155 BITX(cp->cp_ecx, 23, 16) << 12 |
2156 BITX(cp->cp_ecx, 15, 8) << 8 |
2157 BITX(cp->cp_ecx, 7, 0);
2158 /*
2159 * model 9 stepping 1 has wrong associativity
2160 */
2161 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
2162 cp->cp_ecx |= 8 << 12;
2163 break;
2164 case X86_VENDOR_Intel:
2165 /*
2166 * Extended L2 Cache features function.
2167 * First appeared on Prescott.
2168 */
2169 default:
2170 break;
2171 }
2172 break;
2173 default:
2174 break;
2175 }
2176 }
2177
2178 pass2_done:
2179 cpi->cpi_pass = 2;
2180 }
2181
2182 static const char *
2183 intel_cpubrand(const struct cpuid_info *cpi)
2184 {
2185 int i;
2186
2187 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2188 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2189 return ("i486");
2190
2191 switch (cpi->cpi_family) {
2192 case 5:
2193 return ("Intel Pentium(r)");
2194 case 6:
2195 switch (cpi->cpi_model) {
2196 uint_t celeron, xeon;
2197 const struct cpuid_regs *cp;
2198 case 0:
2199 case 1:
2200 case 2:
2201 return ("Intel Pentium(r) Pro");
2202 case 3:
2203 case 4:
2204 return ("Intel Pentium(r) II");
2205 case 6:
2206 return ("Intel Celeron(r)");
2207 case 5:
2208 case 7:
2209 celeron = xeon = 0;
2210 cp = &cpi->cpi_std[2]; /* cache info */
2211
2212 for (i = 1; i < 4; i++) {
2213 uint_t tmp;
2214
2215 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
2216 if (tmp == 0x40)
2217 celeron++;
2218 if (tmp >= 0x44 && tmp <= 0x45)
2219 xeon++;
2220 }
2221
2222 for (i = 0; i < 2; i++) {
2223 uint_t tmp;
2224
2225 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
2226 if (tmp == 0x40)
2227 celeron++;
2228 else if (tmp >= 0x44 && tmp <= 0x45)
2229 xeon++;
2230 }
2231
2232 for (i = 0; i < 4; i++) {
2233 uint_t tmp;
2234
2235 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
2236 if (tmp == 0x40)
2237 celeron++;
2238 else if (tmp >= 0x44 && tmp <= 0x45)
2239 xeon++;
2240 }
2241
2242 for (i = 0; i < 4; i++) {
2243 uint_t tmp;
2244
2245 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
2246 if (tmp == 0x40)
2247 celeron++;
2248 else if (tmp >= 0x44 && tmp <= 0x45)
2249 xeon++;
2250 }
2251
2252 if (celeron)
2253 return ("Intel Celeron(r)");
2254 if (xeon)
2255 return (cpi->cpi_model == 5 ?
2256 "Intel Pentium(r) II Xeon(tm)" :
2257 "Intel Pentium(r) III Xeon(tm)");
2258 return (cpi->cpi_model == 5 ?
2259 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
2260 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
2261 default:
2262 break;
2263 }
2264 default:
2265 break;
2266 }
2267
2268 /* BrandID is present if the field is nonzero */
2269 if (cpi->cpi_brandid != 0) {
2270 static const struct {
2271 uint_t bt_bid;
2272 const char *bt_str;
2273 } brand_tbl[] = {
2274 { 0x1, "Intel(r) Celeron(r)" },
2275 { 0x2, "Intel(r) Pentium(r) III" },
2276 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
2277 { 0x4, "Intel(r) Pentium(r) III" },
2278 { 0x6, "Mobile Intel(r) Pentium(r) III" },
2279 { 0x7, "Mobile Intel(r) Celeron(r)" },
2280 { 0x8, "Intel(r) Pentium(r) 4" },
2281 { 0x9, "Intel(r) Pentium(r) 4" },
2282 { 0xa, "Intel(r) Celeron(r)" },
2283 { 0xb, "Intel(r) Xeon(tm)" },
2284 { 0xc, "Intel(r) Xeon(tm) MP" },
2285 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
2286 { 0xf, "Mobile Intel(r) Celeron(r)" },
2287 { 0x11, "Mobile Genuine Intel(r)" },
2288 { 0x12, "Intel(r) Celeron(r) M" },
2289 { 0x13, "Mobile Intel(r) Celeron(r)" },
2290 { 0x14, "Intel(r) Celeron(r)" },
2291 { 0x15, "Mobile Genuine Intel(r)" },
2292 { 0x16, "Intel(r) Pentium(r) M" },
2293 { 0x17, "Mobile Intel(r) Celeron(r)" }
2294 };
2295 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
2296 uint_t sgn;
2297
2298 sgn = (cpi->cpi_family << 8) |
2299 (cpi->cpi_model << 4) | cpi->cpi_step;
2300
2301 for (i = 0; i < btblmax; i++)
2302 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
2303 break;
2304 if (i < btblmax) {
2305 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
2306 return ("Intel(r) Celeron(r)");
2307 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
2308 return ("Intel(r) Xeon(tm) MP");
2309 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
2310 return ("Intel(r) Xeon(tm)");
2311 return (brand_tbl[i].bt_str);
2312 }
2313 }
2314
2315 return (NULL);
2316 }
2317
2318 static const char *
2319 amd_cpubrand(const struct cpuid_info *cpi)
2320 {
2321 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2322 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2323 return ("i486 compatible");
2324
2325 switch (cpi->cpi_family) {
2326 case 5:
2327 switch (cpi->cpi_model) {
2328 case 0:
2329 case 1:
2330 case 2:
2331 case 3:
2332 case 4:
2333 case 5:
2334 return ("AMD-K5(r)");
2335 case 6:
2336 case 7:
2337 return ("AMD-K6(r)");
2338 case 8:
2339 return ("AMD-K6(r)-2");
2340 case 9:
2341 return ("AMD-K6(r)-III");
2342 default:
2343 return ("AMD (family 5)");
2344 }
2345 case 6:
2346 switch (cpi->cpi_model) {
2347 case 1:
2348 return ("AMD-K7(tm)");
2349 case 0:
2350 case 2:
2351 case 4:
2352 return ("AMD Athlon(tm)");
2353 case 3:
2354 case 7:
2355 return ("AMD Duron(tm)");
2356 case 6:
2357 case 8:
2358 case 10:
2359 /*
2360 * Use the L2 cache size to distinguish
2361 */
2362 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
2363 "AMD Athlon(tm)" : "AMD Duron(tm)");
2364 default:
2365 return ("AMD (family 6)");
2366 }
2367 default:
2368 break;
2369 }
2370
2371 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
2372 cpi->cpi_brandid != 0) {
2373 switch (BITX(cpi->cpi_brandid, 7, 5)) {
2374 case 3:
2375 return ("AMD Opteron(tm) UP 1xx");
2376 case 4:
2377 return ("AMD Opteron(tm) DP 2xx");
2378 case 5:
2379 return ("AMD Opteron(tm) MP 8xx");
2380 default:
2381 return ("AMD Opteron(tm)");
2382 }
2383 }
2384
2385 return (NULL);
2386 }
2387
2388 static const char *
2389 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
2390 {
2391 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2392 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
2393 type == X86_TYPE_CYRIX_486)
2394 return ("i486 compatible");
2395
2396 switch (type) {
2397 case X86_TYPE_CYRIX_6x86:
2398 return ("Cyrix 6x86");
2399 case X86_TYPE_CYRIX_6x86L:
2400 return ("Cyrix 6x86L");
2401 case X86_TYPE_CYRIX_6x86MX:
2402 return ("Cyrix 6x86MX");
2403 case X86_TYPE_CYRIX_GXm:
2404 return ("Cyrix GXm");
2405 case X86_TYPE_CYRIX_MediaGX:
2406 return ("Cyrix MediaGX");
2407 case X86_TYPE_CYRIX_MII:
2408 return ("Cyrix M2");
2409 case X86_TYPE_VIA_CYRIX_III:
2410 return ("VIA Cyrix M3");
2411 default:
2412 /*
2413 * Have another wild guess ..
2414 */
2415 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
2416 return ("Cyrix 5x86");
2417 else if (cpi->cpi_family == 5) {
2418 switch (cpi->cpi_model) {
2419 case 2:
2420 return ("Cyrix 6x86"); /* Cyrix M1 */
2421 case 4:
2422 return ("Cyrix MediaGX");
2423 default:
2424 break;
2425 }
2426 } else if (cpi->cpi_family == 6) {
2427 switch (cpi->cpi_model) {
2428 case 0:
2429 return ("Cyrix 6x86MX"); /* Cyrix M2? */
2430 case 5:
2431 case 6:
2432 case 7:
2433 case 8:
2434 case 9:
2435 return ("VIA C3");
2436 default:
2437 break;
2438 }
2439 }
2440 break;
2441 }
2442 return (NULL);
2443 }
2444
2445 /*
2446 * This only gets called in the case that the CPU extended
2447 * feature brand string (0x80000002, 0x80000003, 0x80000004)
2448 * aren't available, or contain null bytes for some reason.
2449 */
2450 static void
2451 fabricate_brandstr(struct cpuid_info *cpi)
2452 {
2453 const char *brand = NULL;
2454
2455 switch (cpi->cpi_vendor) {
2456 case X86_VENDOR_Intel:
2457 brand = intel_cpubrand(cpi);
2458 break;
2459 case X86_VENDOR_AMD:
2460 brand = amd_cpubrand(cpi);
2461 break;
2462 case X86_VENDOR_Cyrix:
2463 brand = cyrix_cpubrand(cpi, x86_type);
2464 break;
2465 case X86_VENDOR_NexGen:
2466 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2467 brand = "NexGen Nx586";
2468 break;
2469 case X86_VENDOR_Centaur:
2470 if (cpi->cpi_family == 5)
2471 switch (cpi->cpi_model) {
2472 case 4:
2473 brand = "Centaur C6";
2474 break;
2475 case 8:
2476 brand = "Centaur C2";
2477 break;
2478 case 9:
2479 brand = "Centaur C3";
2480 break;
2481 default:
2482 break;
2483 }
2484 break;
2485 case X86_VENDOR_Rise:
2486 if (cpi->cpi_family == 5 &&
2487 (cpi->cpi_model == 0 || cpi->cpi_model == 2))
2488 brand = "Rise mP6";
2489 break;
2490 case X86_VENDOR_SiS:
2491 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2492 brand = "SiS 55x";
2493 break;
2494 case X86_VENDOR_TM:
2495 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
2496 brand = "Transmeta Crusoe TM3x00 or TM5x00";
2497 break;
2498 case X86_VENDOR_NSC:
2499 case X86_VENDOR_UMC:
2500 default:
2501 break;
2502 }
2503 if (brand) {
2504 (void) strcpy((char *)cpi->cpi_brandstr, brand);
2505 return;
2506 }
2507
2508 /*
2509 * If all else fails ...
2510 */
2511 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
2512 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
2513 cpi->cpi_model, cpi->cpi_step);
2514 }
2515
2516 /*
2517 * This routine is called just after kernel memory allocation
2518 * becomes available on cpu0, and as part of mp_startup() on
2519 * the other cpus.
2520 *
2521 * Fixup the brand string, and collect any information from cpuid
2522 * that requires dynamically allocated storage to represent.
2523 */
2524 /*ARGSUSED*/
2525 void
2526 cpuid_pass3(cpu_t *cpu)
2527 {
2528 int i, max, shft, level, size;
2529 struct cpuid_regs regs;
2530 struct cpuid_regs *cp;
2531 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2532
2533 ASSERT(cpi->cpi_pass == 2);
2534
2535 /*
2536 * Function 4: Deterministic cache parameters
2537 *
2538 * Take this opportunity to detect the number of threads
2539 * sharing the last level cache, and construct a corresponding
2540 * cache id. The respective cpuid_info members are initialized
2541 * to the default case of "no last level cache sharing".
2542 */
2543 cpi->cpi_ncpu_shr_last_cache = 1;
2544 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
2545
2546 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
2547
2548 /*
2549 * Find the # of elements (size) returned by fn 4, and along
2550 * the way detect last level cache sharing details.
2551 */
2552 bzero(®s, sizeof (regs));
2553 cp = ®s;
2554 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
2555 cp->cp_eax = 4;
2556 cp->cp_ecx = i;
2557
2558 (void) __cpuid_insn(cp);
2559
2560 if (CPI_CACHE_TYPE(cp) == 0)
2561 break;
2562 level = CPI_CACHE_LVL(cp);
2563 if (level > max) {
2564 max = level;
2565 cpi->cpi_ncpu_shr_last_cache =
2566 CPI_NTHR_SHR_CACHE(cp) + 1;
2567 }
2568 }
2569 cpi->cpi_std_4_size = size = i;
2570
2571 /*
2572 * Allocate the cpi_std_4 array. The first element
2573 * references the regs for fn 4, %ecx == 0, which
2574 * cpuid_pass2() stashed in cpi->cpi_std[4].
2575 */
2576 if (size > 0) {
2577 cpi->cpi_std_4 =
2578 kmem_alloc(size * sizeof (cp), KM_SLEEP);
2579 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
2580
2581 /*
2582 * Allocate storage to hold the additional regs
2583 * for function 4, %ecx == 1 .. cpi_std_4_size.
2584 *
2585 * The regs for fn 4, %ecx == 0 has already
2586 * been allocated as indicated above.
2587 */
2588 for (i = 1; i < size; i++) {
2589 cp = cpi->cpi_std_4[i] =
2590 kmem_zalloc(sizeof (regs), KM_SLEEP);
2591 cp->cp_eax = 4;
2592 cp->cp_ecx = i;
2593
2594 (void) __cpuid_insn(cp);
2595 }
2596 }
2597 /*
2598 * Determine the number of bits needed to represent
2599 * the number of CPUs sharing the last level cache.
2600 *
2601 * Shift off that number of bits from the APIC id to
2602 * derive the cache id.
2603 */
2604 shft = 0;
2605 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
2606 shft++;
2607 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
2608 }
2609
2610 /*
2611 * Now fixup the brand string
2612 */
2613 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2614 fabricate_brandstr(cpi);
2615 } else {
2616
2617 /*
2618 * If we successfully extracted a brand string from the cpuid
2619 * instruction, clean it up by removing leading spaces and
2620 * similar junk.
2621 */
2622 if (cpi->cpi_brandstr[0]) {
2623 size_t maxlen = sizeof (cpi->cpi_brandstr);
2624 char *src, *dst;
2625
2626 dst = src = (char *)cpi->cpi_brandstr;
2627 src[maxlen - 1] = '\0';
2628 /*
2629 * strip leading spaces
2630 */
2631 while (*src == ' ')
2632 src++;
2633 /*
2634 * Remove any 'Genuine' or "Authentic" prefixes
2635 */
2636 if (strncmp(src, "Genuine ", 8) == 0)
2637 src += 8;
2638 if (strncmp(src, "Authentic ", 10) == 0)
2639 src += 10;
2640
2641 /*
2642 * Now do an in-place copy.
2643 * Map (R) to (r) and (TM) to (tm).
2644 * The era of teletypes is long gone, and there's
2645 * -really- no need to shout.
2646 */
2647 while (*src != '\0') {
2648 if (src[0] == '(') {
2649 if (strncmp(src + 1, "R)", 2) == 0) {
2650 (void) strncpy(dst, "(r)", 3);
2651 src += 3;
2652 dst += 3;
2653 continue;
2654 }
2655 if (strncmp(src + 1, "TM)", 3) == 0) {
2656 (void) strncpy(dst, "(tm)", 4);
2657 src += 4;
2658 dst += 4;
2659 continue;
2660 }
2661 }
2662 *dst++ = *src++;
2663 }
2664 *dst = '\0';
2665
2666 /*
2667 * Finally, remove any trailing spaces
2668 */
2669 while (--dst > cpi->cpi_brandstr)
2670 if (*dst == ' ')
2671 *dst = '\0';
2672 else
2673 break;
2674 } else
2675 fabricate_brandstr(cpi);
2676 }
2677 cpi->cpi_pass = 3;
2678 }
2679
2680 /*
2681 * This routine is called out of bind_hwcap() much later in the life
2682 * of the kernel (post_startup()). The job of this routine is to resolve
2683 * the hardware feature support and kernel support for those features into
2684 * what we're actually going to tell applications via the aux vector.
2685 */
2686 void
2687 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
2688 {
2689 struct cpuid_info *cpi;
2690 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
2691
2692 if (cpu == NULL)
2693 cpu = CPU;
2694 cpi = cpu->cpu_m.mcpu_cpi;
2695
2696 ASSERT(cpi->cpi_pass == 3);
2697
2698 if (cpi->cpi_maxeax >= 1) {
2699 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
2700 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2701 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES];
2702
2703 *edx = CPI_FEATURES_EDX(cpi);
2704 *ecx = CPI_FEATURES_ECX(cpi);
2705 *ebx = CPI_FEATURES_7_0_EBX(cpi);
2706
2707 /*
2708 * [these require explicit kernel support]
2709 */
2710 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
2711 *edx &= ~CPUID_INTC_EDX_SEP;
2712
2713 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
2714 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
2715 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
2716 *edx &= ~CPUID_INTC_EDX_SSE2;
2717
2718 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
2719 *edx &= ~CPUID_INTC_EDX_HTT;
2720
2721 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
2722 *ecx &= ~CPUID_INTC_ECX_SSE3;
2723
2724 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
2725 *ecx &= ~CPUID_INTC_ECX_SSSE3;
2726 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
2727 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
2728 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
2729 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
2730 if (!is_x86_feature(x86_featureset, X86FSET_AES))
2731 *ecx &= ~CPUID_INTC_ECX_AES;
2732 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
2733 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
2734 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
2735 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
2736 CPUID_INTC_ECX_OSXSAVE);
2737 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
2738 *ecx &= ~CPUID_INTC_ECX_AVX;
2739 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
2740 *ecx &= ~CPUID_INTC_ECX_F16C;
2741 if (!is_x86_feature(x86_featureset, X86FSET_FMA))
2742 *ecx &= ~CPUID_INTC_ECX_FMA;
2743 if (!is_x86_feature(x86_featureset, X86FSET_BMI1))
2744 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
2745 if (!is_x86_feature(x86_featureset, X86FSET_BMI2))
2746 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
2747 if (!is_x86_feature(x86_featureset, X86FSET_AVX2))
2748 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
2749 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED))
2750 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED;
2751 if (!is_x86_feature(x86_featureset, X86FSET_ADX))
2752 *ebx &= ~CPUID_INTC_EBX_7_0_ADX;
2753
2754 /*
2755 * [no explicit support required beyond x87 fp context]
2756 */
2757 if (!fpu_exists)
2758 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
2759
2760 /*
2761 * Now map the supported feature vector to things that we
2762 * think userland will care about.
2763 */
2764 if (*edx & CPUID_INTC_EDX_SEP)
2765 hwcap_flags |= AV_386_SEP;
2766 if (*edx & CPUID_INTC_EDX_SSE)
2767 hwcap_flags |= AV_386_FXSR | AV_386_SSE;
2768 if (*edx & CPUID_INTC_EDX_SSE2)
2769 hwcap_flags |= AV_386_SSE2;
2770 if (*ecx & CPUID_INTC_ECX_SSE3)
2771 hwcap_flags |= AV_386_SSE3;
2772 if (*ecx & CPUID_INTC_ECX_SSSE3)
2773 hwcap_flags |= AV_386_SSSE3;
2774 if (*ecx & CPUID_INTC_ECX_SSE4_1)
2775 hwcap_flags |= AV_386_SSE4_1;
2776 if (*ecx & CPUID_INTC_ECX_SSE4_2)
2777 hwcap_flags |= AV_386_SSE4_2;
2778 if (*ecx & CPUID_INTC_ECX_MOVBE)
2779 hwcap_flags |= AV_386_MOVBE;
2780 if (*ecx & CPUID_INTC_ECX_AES)
2781 hwcap_flags |= AV_386_AES;
2782 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
2783 hwcap_flags |= AV_386_PCLMULQDQ;
2784 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
2785 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
2786 hwcap_flags |= AV_386_XSAVE;
2787
2788 if (*ecx & CPUID_INTC_ECX_AVX) {
2789 hwcap_flags |= AV_386_AVX;
2790 if (*ecx & CPUID_INTC_ECX_F16C)
2791 hwcap_flags_2 |= AV_386_2_F16C;
2792 if (*ecx & CPUID_INTC_ECX_FMA)
2793 hwcap_flags_2 |= AV_386_2_FMA;
2794 if (*ebx & CPUID_INTC_EBX_7_0_BMI1)
2795 hwcap_flags_2 |= AV_386_2_BMI1;
2796 if (*ebx & CPUID_INTC_EBX_7_0_BMI2)
2797 hwcap_flags_2 |= AV_386_2_BMI2;
2798 if (*ebx & CPUID_INTC_EBX_7_0_AVX2)
2799 hwcap_flags_2 |= AV_386_2_AVX2;
2800 }
2801 }
2802 if (*ecx & CPUID_INTC_ECX_VMX)
2803 hwcap_flags |= AV_386_VMX;
2804 if (*ecx & CPUID_INTC_ECX_POPCNT)
2805 hwcap_flags |= AV_386_POPCNT;
2806 if (*edx & CPUID_INTC_EDX_FPU)
2807 hwcap_flags |= AV_386_FPU;
2808 if (*edx & CPUID_INTC_EDX_MMX)
2809 hwcap_flags |= AV_386_MMX;
2810
2811 if (*edx & CPUID_INTC_EDX_TSC)
2812 hwcap_flags |= AV_386_TSC;
2813 if (*edx & CPUID_INTC_EDX_CX8)
2814 hwcap_flags |= AV_386_CX8;
2815 if (*edx & CPUID_INTC_EDX_CMOV)
2816 hwcap_flags |= AV_386_CMOV;
2817 if (*ecx & CPUID_INTC_ECX_CX16)
2818 hwcap_flags |= AV_386_CX16;
2819
2820 if (*ecx & CPUID_INTC_ECX_RDRAND)
2821 hwcap_flags_2 |= AV_386_2_RDRAND;
2822 if (*ebx & CPUID_INTC_EBX_7_0_ADX)
2823 hwcap_flags_2 |= AV_386_2_ADX;
2824 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED)
2825 hwcap_flags_2 |= AV_386_2_RDSEED;
2826
2827 }
2828
2829 if (cpi->cpi_xmaxeax < 0x80000001)
2830 goto pass4_done;
2831
2832 switch (cpi->cpi_vendor) {
2833 struct cpuid_regs cp;
2834 uint32_t *edx, *ecx;
2835
2836 case X86_VENDOR_Intel:
2837 /*
2838 * Seems like Intel duplicated what we necessary
2839 * here to make the initial crop of 64-bit OS's work.
2840 * Hopefully, those are the only "extended" bits
2841 * they'll add.
2842 */
2843 /*FALLTHROUGH*/
2844
2845 case X86_VENDOR_AMD:
2846 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
2847 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2848
2849 *edx = CPI_FEATURES_XTD_EDX(cpi);
2850 *ecx = CPI_FEATURES_XTD_ECX(cpi);
2851
2852 /*
2853 * [these features require explicit kernel support]
2854 */
2855 switch (cpi->cpi_vendor) {
2856 case X86_VENDOR_Intel:
2857 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2858 *edx &= ~CPUID_AMD_EDX_TSCP;
2859 break;
2860
2861 case X86_VENDOR_AMD:
2862 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2863 *edx &= ~CPUID_AMD_EDX_TSCP;
2864 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
2865 *ecx &= ~CPUID_AMD_ECX_SSE4A;
2866 break;
2867
2868 default:
2869 break;
2870 }
2871
2872 /*
2873 * [no explicit support required beyond
2874 * x87 fp context and exception handlers]
2875 */
2876 if (!fpu_exists)
2877 *edx &= ~(CPUID_AMD_EDX_MMXamd |
2878 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
2879
2880 if (!is_x86_feature(x86_featureset, X86FSET_NX))
2881 *edx &= ~CPUID_AMD_EDX_NX;
2882 #if !defined(__amd64)
2883 *edx &= ~CPUID_AMD_EDX_LM;
2884 #endif
2885 /*
2886 * Now map the supported feature vector to
2887 * things that we think userland will care about.
2888 */
2889 #if defined(__amd64)
2890 if (*edx & CPUID_AMD_EDX_SYSC)
2891 hwcap_flags |= AV_386_AMD_SYSC;
2892 #endif
2893 if (*edx & CPUID_AMD_EDX_MMXamd)
2894 hwcap_flags |= AV_386_AMD_MMX;
2895 if (*edx & CPUID_AMD_EDX_3DNow)
2896 hwcap_flags |= AV_386_AMD_3DNow;
2897 if (*edx & CPUID_AMD_EDX_3DNowx)
2898 hwcap_flags |= AV_386_AMD_3DNowx;
2899 if (*ecx & CPUID_AMD_ECX_SVM)
2900 hwcap_flags |= AV_386_AMD_SVM;
2901
2902 switch (cpi->cpi_vendor) {
2903 case X86_VENDOR_AMD:
2904 if (*edx & CPUID_AMD_EDX_TSCP)
2905 hwcap_flags |= AV_386_TSCP;
2906 if (*ecx & CPUID_AMD_ECX_AHF64)
2907 hwcap_flags |= AV_386_AHF;
2908 if (*ecx & CPUID_AMD_ECX_SSE4A)
2909 hwcap_flags |= AV_386_AMD_SSE4A;
2910 if (*ecx & CPUID_AMD_ECX_LZCNT)
2911 hwcap_flags |= AV_386_AMD_LZCNT;
2912 break;
2913
2914 case X86_VENDOR_Intel:
2915 if (*edx & CPUID_AMD_EDX_TSCP)
2916 hwcap_flags |= AV_386_TSCP;
2917 /*
2918 * Aarrgh.
2919 * Intel uses a different bit in the same word.
2920 */
2921 if (*ecx & CPUID_INTC_ECX_AHF64)
2922 hwcap_flags |= AV_386_AHF;
2923 break;
2924
2925 default:
2926 break;
2927 }
2928 break;
2929
2930 case X86_VENDOR_TM:
2931 cp.cp_eax = 0x80860001;
2932 (void) __cpuid_insn(&cp);
2933 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
2934 break;
2935
2936 default:
2937 break;
2938 }
2939
2940 pass4_done:
2941 cpi->cpi_pass = 4;
2942 if (hwcap_out != NULL) {
2943 hwcap_out[0] = hwcap_flags;
2944 hwcap_out[1] = hwcap_flags_2;
2945 }
2946 }
2947
2948
2949 /*
2950 * Simulate the cpuid instruction using the data we previously
2951 * captured about this CPU. We try our best to return the truth
2952 * about the hardware, independently of kernel support.
2953 */
2954 uint32_t
2955 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
2956 {
2957 struct cpuid_info *cpi;
2958 struct cpuid_regs *xcp;
2959
2960 if (cpu == NULL)
2961 cpu = CPU;
2962 cpi = cpu->cpu_m.mcpu_cpi;
2963
2964 ASSERT(cpuid_checkpass(cpu, 3));
2965
2966 /*
2967 * CPUID data is cached in two separate places: cpi_std for standard
2968 * CPUID functions, and cpi_extd for extended CPUID functions.
2969 */
2970 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
2971 xcp = &cpi->cpi_std[cp->cp_eax];
2972 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
2973 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
2974 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
2975 else
2976 /*
2977 * The caller is asking for data from an input parameter which
2978 * the kernel has not cached. In this case we go fetch from
2979 * the hardware and return the data directly to the user.
2980 */
2981 return (__cpuid_insn(cp));
2982
2983 cp->cp_eax = xcp->cp_eax;
2984 cp->cp_ebx = xcp->cp_ebx;
2985 cp->cp_ecx = xcp->cp_ecx;
2986 cp->cp_edx = xcp->cp_edx;
2987 return (cp->cp_eax);
2988 }
2989
2990 int
2991 cpuid_checkpass(cpu_t *cpu, int pass)
2992 {
2993 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
2994 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
2995 }
2996
2997 int
2998 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
2999 {
3000 ASSERT(cpuid_checkpass(cpu, 3));
3001
3002 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
3003 }
3004
3005 int
3006 cpuid_is_cmt(cpu_t *cpu)
3007 {
3008 if (cpu == NULL)
3009 cpu = CPU;
3010
3011 ASSERT(cpuid_checkpass(cpu, 1));
3012
3013 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
3014 }
3015
3016 /*
3017 * AMD and Intel both implement the 64-bit variant of the syscall
3018 * instruction (syscallq), so if there's -any- support for syscall,
3019 * cpuid currently says "yes, we support this".
3020 *
3021 * However, Intel decided to -not- implement the 32-bit variant of the
3022 * syscall instruction, so we provide a predicate to allow our caller
3023 * to test that subtlety here.
3024 *
3025 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
3026 * even in the case where the hardware would in fact support it.
3027 */
3028 /*ARGSUSED*/
3029 int
3030 cpuid_syscall32_insn(cpu_t *cpu)
3031 {
3032 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
3033
3034 #if !defined(__xpv)
3035 if (cpu == NULL)
3036 cpu = CPU;
3037
3038 /*CSTYLED*/
3039 {
3040 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3041
3042 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
3043 cpi->cpi_xmaxeax >= 0x80000001 &&
3044 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
3045 return (1);
3046 }
3047 #endif
3048 return (0);
3049 }
3050
3051 int
3052 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
3053 {
3054 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3055
3056 static const char fmt[] =
3057 "x86 (%s %X family %d model %d step %d clock %d MHz)";
3058 static const char fmt_ht[] =
3059 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
3060
3061 ASSERT(cpuid_checkpass(cpu, 1));
3062
3063 if (cpuid_is_cmt(cpu))
3064 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3065 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3066 cpi->cpi_family, cpi->cpi_model,
3067 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3068 return (snprintf(s, n, fmt,
3069 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3070 cpi->cpi_family, cpi->cpi_model,
3071 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3072 }
3073
3074 const char *
3075 cpuid_getvendorstr(cpu_t *cpu)
3076 {
3077 ASSERT(cpuid_checkpass(cpu, 1));
3078 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
3079 }
3080
3081 uint_t
3082 cpuid_getvendor(cpu_t *cpu)
3083 {
3084 ASSERT(cpuid_checkpass(cpu, 1));
3085 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
3086 }
3087
3088 uint_t
3089 cpuid_getfamily(cpu_t *cpu)
3090 {
3091 ASSERT(cpuid_checkpass(cpu, 1));
3092 return (cpu->cpu_m.mcpu_cpi->cpi_family);
3093 }
3094
3095 uint_t
3096 cpuid_getmodel(cpu_t *cpu)
3097 {
3098 ASSERT(cpuid_checkpass(cpu, 1));
3099 return (cpu->cpu_m.mcpu_cpi->cpi_model);
3100 }
3101
3102 uint_t
3103 cpuid_get_ncpu_per_chip(cpu_t *cpu)
3104 {
3105 ASSERT(cpuid_checkpass(cpu, 1));
3106 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
3107 }
3108
3109 uint_t
3110 cpuid_get_ncore_per_chip(cpu_t *cpu)
3111 {
3112 ASSERT(cpuid_checkpass(cpu, 1));
3113 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
3114 }
3115
3116 uint_t
3117 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
3118 {
3119 ASSERT(cpuid_checkpass(cpu, 2));
3120 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
3121 }
3122
3123 id_t
3124 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
3125 {
3126 ASSERT(cpuid_checkpass(cpu, 2));
3127 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3128 }
3129
3130 uint_t
3131 cpuid_getstep(cpu_t *cpu)
3132 {
3133 ASSERT(cpuid_checkpass(cpu, 1));
3134 return (cpu->cpu_m.mcpu_cpi->cpi_step);
3135 }
3136
3137 uint_t
3138 cpuid_getsig(struct cpu *cpu)
3139 {
3140 ASSERT(cpuid_checkpass(cpu, 1));
3141 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
3142 }
3143
3144 uint32_t
3145 cpuid_getchiprev(struct cpu *cpu)
3146 {
3147 ASSERT(cpuid_checkpass(cpu, 1));
3148 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
3149 }
3150
3151 const char *
3152 cpuid_getchiprevstr(struct cpu *cpu)
3153 {
3154 ASSERT(cpuid_checkpass(cpu, 1));
3155 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
3156 }
3157
3158 uint32_t
3159 cpuid_getsockettype(struct cpu *cpu)
3160 {
3161 ASSERT(cpuid_checkpass(cpu, 1));
3162 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
3163 }
3164
3165 const char *
3166 cpuid_getsocketstr(cpu_t *cpu)
3167 {
3168 static const char *socketstr = NULL;
3169 struct cpuid_info *cpi;
3170
3171 ASSERT(cpuid_checkpass(cpu, 1));
3172 cpi = cpu->cpu_m.mcpu_cpi;
3173
3174 /* Assume that socket types are the same across the system */
3175 if (socketstr == NULL)
3176 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
3177 cpi->cpi_model, cpi->cpi_step);
3178
3179
3180 return (socketstr);
3181 }
3182
3183 int
3184 cpuid_get_chipid(cpu_t *cpu)
3185 {
3186 ASSERT(cpuid_checkpass(cpu, 1));
3187
3188 if (cpuid_is_cmt(cpu))
3189 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
3190 return (cpu->cpu_id);
3191 }
3192
3193 id_t
3194 cpuid_get_coreid(cpu_t *cpu)
3195 {
3196 ASSERT(cpuid_checkpass(cpu, 1));
3197 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
3198 }
3199
3200 int
3201 cpuid_get_pkgcoreid(cpu_t *cpu)
3202 {
3203 ASSERT(cpuid_checkpass(cpu, 1));
3204 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
3205 }
3206
3207 int
3208 cpuid_get_clogid(cpu_t *cpu)
3209 {
3210 ASSERT(cpuid_checkpass(cpu, 1));
3211 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
3212 }
3213
3214 int
3215 cpuid_get_cacheid(cpu_t *cpu)
3216 {
3217 ASSERT(cpuid_checkpass(cpu, 1));
3218 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3219 }
3220
3221 uint_t
3222 cpuid_get_procnodeid(cpu_t *cpu)
3223 {
3224 ASSERT(cpuid_checkpass(cpu, 1));
3225 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3226 }
3227
3228 uint_t
3229 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3230 {
3231 ASSERT(cpuid_checkpass(cpu, 1));
3232 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3233 }
3234
3235 uint_t
3236 cpuid_get_compunitid(cpu_t *cpu)
3237 {
3238 ASSERT(cpuid_checkpass(cpu, 1));
3239 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3240 }
3241
3242 uint_t
3243 cpuid_get_cores_per_compunit(cpu_t *cpu)
3244 {
3245 ASSERT(cpuid_checkpass(cpu, 1));
3246 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3247 }
3248
3249 /*ARGSUSED*/
3250 int
3251 cpuid_have_cr8access(cpu_t *cpu)
3252 {
3253 #if defined(__amd64)
3254 return (1);
3255 #else
3256 struct cpuid_info *cpi;
3257
3258 ASSERT(cpu != NULL);
3259 cpi = cpu->cpu_m.mcpu_cpi;
3260 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3261 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3262 return (1);
3263 return (0);
3264 #endif
3265 }
3266
3267 uint32_t
3268 cpuid_get_apicid(cpu_t *cpu)
3269 {
3270 ASSERT(cpuid_checkpass(cpu, 1));
3271 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
3272 return (UINT32_MAX);
3273 } else {
3274 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
3275 }
3276 }
3277
3278 void
3279 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
3280 {
3281 struct cpuid_info *cpi;
3282
3283 if (cpu == NULL)
3284 cpu = CPU;
3285 cpi = cpu->cpu_m.mcpu_cpi;
3286
3287 ASSERT(cpuid_checkpass(cpu, 1));
3288
3289 if (pabits)
3290 *pabits = cpi->cpi_pabits;
3291 if (vabits)
3292 *vabits = cpi->cpi_vabits;
3293 }
3294
3295 /*
3296 * Returns the number of data TLB entries for a corresponding
3297 * pagesize. If it can't be computed, or isn't known, the
3298 * routine returns zero. If you ask about an architecturally
3299 * impossible pagesize, the routine will panic (so that the
3300 * hat implementor knows that things are inconsistent.)
3301 */
3302 uint_t
3303 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
3304 {
3305 struct cpuid_info *cpi;
3306 uint_t dtlb_nent = 0;
3307
3308 if (cpu == NULL)
3309 cpu = CPU;
3310 cpi = cpu->cpu_m.mcpu_cpi;
3311
3312 ASSERT(cpuid_checkpass(cpu, 1));
3313
3314 /*
3315 * Check the L2 TLB info
3316 */
3317 if (cpi->cpi_xmaxeax >= 0x80000006) {
3318 struct cpuid_regs *cp = &cpi->cpi_extd[6];
3319
3320 switch (pagesize) {
3321
3322 case 4 * 1024:
3323 /*
3324 * All zero in the top 16 bits of the register
3325 * indicates a unified TLB. Size is in low 16 bits.
3326 */
3327 if ((cp->cp_ebx & 0xffff0000) == 0)
3328 dtlb_nent = cp->cp_ebx & 0x0000ffff;
3329 else
3330 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
3331 break;
3332
3333 case 2 * 1024 * 1024:
3334 if ((cp->cp_eax & 0xffff0000) == 0)
3335 dtlb_nent = cp->cp_eax & 0x0000ffff;
3336 else
3337 dtlb_nent = BITX(cp->cp_eax, 27, 16);
3338 break;
3339
3340 default:
3341 panic("unknown L2 pagesize");
3342 /*NOTREACHED*/
3343 }
3344 }
3345
3346 if (dtlb_nent != 0)
3347 return (dtlb_nent);
3348
3349 /*
3350 * No L2 TLB support for this size, try L1.
3351 */
3352 if (cpi->cpi_xmaxeax >= 0x80000005) {
3353 struct cpuid_regs *cp = &cpi->cpi_extd[5];
3354
3355 switch (pagesize) {
3356 case 4 * 1024:
3357 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
3358 break;
3359 case 2 * 1024 * 1024:
3360 dtlb_nent = BITX(cp->cp_eax, 23, 16);
3361 break;
3362 default:
3363 panic("unknown L1 d-TLB pagesize");
3364 /*NOTREACHED*/
3365 }
3366 }
3367
3368 return (dtlb_nent);
3369 }
3370
3371 /*
3372 * Return 0 if the erratum is not present or not applicable, positive
3373 * if it is, and negative if the status of the erratum is unknown.
3374 *
3375 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
3376 * Processors" #25759, Rev 3.57, August 2005
3377 */
3378 int
3379 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
3380 {
3381 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3382 uint_t eax;
3383
3384 /*
3385 * Bail out if this CPU isn't an AMD CPU, or if it's
3386 * a legacy (32-bit) AMD CPU.
3387 */
3388 if (cpi->cpi_vendor != X86_VENDOR_AMD ||
3389 cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
3390 cpi->cpi_family == 6)
3391
3392 return (0);
3393
3394 eax = cpi->cpi_std[1].cp_eax;
3395
3396 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
3397 #define SH_B3(eax) (eax == 0xf51)
3398 #define B(eax) (SH_B0(eax) || SH_B3(eax))
3399
3400 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
3401
3402 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
3403 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
3404 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
3405 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
3406
3407 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
3408 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
3409 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
3410 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
3411
3412 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
3413 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
3414 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
3415 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
3416 #define BH_E4(eax) (eax == 0x20fb1)
3417 #define SH_E5(eax) (eax == 0x20f42)
3418 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
3419 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
3420 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
3421 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
3422 DH_E6(eax) || JH_E6(eax))
3423
3424 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02)
3425 #define DR_B0(eax) (eax == 0x100f20)
3426 #define DR_B1(eax) (eax == 0x100f21)
3427 #define DR_BA(eax) (eax == 0x100f2a)
3428 #define DR_B2(eax) (eax == 0x100f22)
3429 #define DR_B3(eax) (eax == 0x100f23)
3430 #define RB_C0(eax) (eax == 0x100f40)
3431
3432 switch (erratum) {
3433 case 1:
3434 return (cpi->cpi_family < 0x10);
3435 case 51: /* what does the asterisk mean? */
3436 return (B(eax) || SH_C0(eax) || CG(eax));
3437 case 52:
3438 return (B(eax));
3439 case 57:
3440 return (cpi->cpi_family <= 0x11);
3441 case 58:
3442 return (B(eax));
3443 case 60:
3444 return (cpi->cpi_family <= 0x11);
3445 case 61:
3446 case 62:
3447 case 63:
3448 case 64:
3449 case 65:
3450 case 66:
3451 case 68:
3452 case 69:
3453 case 70:
3454 case 71:
3455 return (B(eax));
3456 case 72:
3457 return (SH_B0(eax));
3458 case 74:
3459 return (B(eax));
3460 case 75:
3461 return (cpi->cpi_family < 0x10);
3462 case 76:
3463 return (B(eax));
3464 case 77:
3465 return (cpi->cpi_family <= 0x11);
3466 case 78:
3467 return (B(eax) || SH_C0(eax));
3468 case 79:
3469 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3470 case 80:
3471 case 81:
3472 case 82:
3473 return (B(eax));
3474 case 83:
3475 return (B(eax) || SH_C0(eax) || CG(eax));
3476 case 85:
3477 return (cpi->cpi_family < 0x10);
3478 case 86:
3479 return (SH_C0(eax) || CG(eax));
3480 case 88:
3481 #if !defined(__amd64)
3482 return (0);
3483 #else
3484 return (B(eax) || SH_C0(eax));
3485 #endif
3486 case 89:
3487 return (cpi->cpi_family < 0x10);
3488 case 90:
3489 return (B(eax) || SH_C0(eax) || CG(eax));
3490 case 91:
3491 case 92:
3492 return (B(eax) || SH_C0(eax));
3493 case 93:
3494 return (SH_C0(eax));
3495 case 94:
3496 return (B(eax) || SH_C0(eax) || CG(eax));
3497 case 95:
3498 #if !defined(__amd64)
3499 return (0);
3500 #else
3501 return (B(eax) || SH_C0(eax));
3502 #endif
3503 case 96:
3504 return (B(eax) || SH_C0(eax) || CG(eax));
3505 case 97:
3506 case 98:
3507 return (SH_C0(eax) || CG(eax));
3508 case 99:
3509 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3510 case 100:
3511 return (B(eax) || SH_C0(eax));
3512 case 101:
3513 case 103:
3514 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3515 case 104:
3516 return (SH_C0(eax) || CG(eax) || D0(eax));
3517 case 105:
3518 case 106:
3519 case 107:
3520 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3521 case 108:
3522 return (DH_CG(eax));
3523 case 109:
3524 return (SH_C0(eax) || CG(eax) || D0(eax));
3525 case 110:
3526 return (D0(eax) || EX(eax));
3527 case 111:
3528 return (CG(eax));
3529 case 112:
3530 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3531 case 113:
3532 return (eax == 0x20fc0);
3533 case 114:
3534 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3535 case 115:
3536 return (SH_E0(eax) || JH_E1(eax));
3537 case 116:
3538 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3539 case 117:
3540 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3541 case 118:
3542 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
3543 JH_E6(eax));
3544 case 121:
3545 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3546 case 122:
3547 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11);
3548 case 123:
3549 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
3550 case 131:
3551 return (cpi->cpi_family < 0x10);
3552 case 6336786:
3553 /*
3554 * Test for AdvPowerMgmtInfo.TscPStateInvariant
3555 * if this is a K8 family or newer processor
3556 */
3557 if (CPI_FAMILY(cpi) == 0xf) {
3558 struct cpuid_regs regs;
3559 regs.cp_eax = 0x80000007;
3560 (void) __cpuid_insn(®s);
3561 return (!(regs.cp_edx & 0x100));
3562 }
3563 return (0);
3564 case 6323525:
3565 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
3566 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
3567
3568 case 6671130:
3569 /*
3570 * check for processors (pre-Shanghai) that do not provide
3571 * optimal management of 1gb ptes in its tlb.
3572 */
3573 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
3574
3575 case 298:
3576 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
3577 DR_B2(eax) || RB_C0(eax));
3578
3579 case 721:
3580 #if defined(__amd64)
3581 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
3582 #else
3583 return (0);
3584 #endif
3585
3586 default:
3587 return (-1);
3588
3589 }
3590 }
3591
3592 /*
3593 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
3594 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
3595 */
3596 int
3597 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
3598 {
3599 struct cpuid_info *cpi;
3600 uint_t osvwid;
3601 static int osvwfeature = -1;
3602 uint64_t osvwlength;
3603
3604
3605 cpi = cpu->cpu_m.mcpu_cpi;
3606
3607 /* confirm OSVW supported */
3608 if (osvwfeature == -1) {
3609 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
3610 } else {
3611 /* assert that osvw feature setting is consistent on all cpus */
3612 ASSERT(osvwfeature ==
3613 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
3614 }
3615 if (!osvwfeature)
3616 return (-1);
3617
3618 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
3619
3620 switch (erratum) {
3621 case 298: /* osvwid is 0 */
3622 osvwid = 0;
3623 if (osvwlength <= (uint64_t)osvwid) {
3624 /* osvwid 0 is unknown */
3625 return (-1);
3626 }
3627
3628 /*
3629 * Check the OSVW STATUS MSR to determine the state
3630 * of the erratum where:
3631 * 0 - fixed by HW
3632 * 1 - BIOS has applied the workaround when BIOS
3633 * workaround is available. (Or for other errata,
3634 * OS workaround is required.)
3635 * For a value of 1, caller will confirm that the
3636 * erratum 298 workaround has indeed been applied by BIOS.
3637 *
3638 * A 1 may be set in cpus that have a HW fix
3639 * in a mixed cpu system. Regarding erratum 298:
3640 * In a multiprocessor platform, the workaround above
3641 * should be applied to all processors regardless of
3642 * silicon revision when an affected processor is
3643 * present.
3644 */
3645
3646 return (rdmsr(MSR_AMD_OSVW_STATUS +
3647 (osvwid / OSVW_ID_CNT_PER_MSR)) &
3648 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
3649
3650 default:
3651 return (-1);
3652 }
3653 }
3654
3655 static const char assoc_str[] = "associativity";
3656 static const char line_str[] = "line-size";
3657 static const char size_str[] = "size";
3658
3659 static void
3660 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
3661 uint32_t val)
3662 {
3663 char buf[128];
3664
3665 /*
3666 * ndi_prop_update_int() is used because it is desirable for
3667 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
3668 */
3669 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
3670 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
3671 }
3672
3673 /*
3674 * Intel-style cache/tlb description
3675 *
3676 * Standard cpuid level 2 gives a randomly ordered
3677 * selection of tags that index into a table that describes
3678 * cache and tlb properties.
3679 */
3680
3681 static const char l1_icache_str[] = "l1-icache";
3682 static const char l1_dcache_str[] = "l1-dcache";
3683 static const char l2_cache_str[] = "l2-cache";
3684 static const char l3_cache_str[] = "l3-cache";
3685 static const char itlb4k_str[] = "itlb-4K";
3686 static const char dtlb4k_str[] = "dtlb-4K";
3687 static const char itlb2M_str[] = "itlb-2M";
3688 static const char itlb4M_str[] = "itlb-4M";
3689 static const char dtlb4M_str[] = "dtlb-4M";
3690 static const char dtlb24_str[] = "dtlb0-2M-4M";
3691 static const char itlb424_str[] = "itlb-4K-2M-4M";
3692 static const char itlb24_str[] = "itlb-2M-4M";
3693 static const char dtlb44_str[] = "dtlb-4K-4M";
3694 static const char sl1_dcache_str[] = "sectored-l1-dcache";
3695 static const char sl2_cache_str[] = "sectored-l2-cache";
3696 static const char itrace_str[] = "itrace-cache";
3697 static const char sl3_cache_str[] = "sectored-l3-cache";
3698 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
3699
3700 static const struct cachetab {
3701 uint8_t ct_code;
3702 uint8_t ct_assoc;
3703 uint16_t ct_line_size;
3704 size_t ct_size;
3705 const char *ct_label;
3706 } intel_ctab[] = {
3707 /*
3708 * maintain descending order!
3709 *
3710 * Codes ignored - Reason
3711 * ----------------------
3712 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3713 * f0H/f1H - Currently we do not interpret prefetch size by design
3714 */
3715 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str},
3716 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str},
3717 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str},
3718 { 0xde, 12, 64, 6*1024*1024, l3_cache_str},
3719 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str},
3720 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str},
3721 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str},
3722 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str},
3723 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str},
3724 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str},
3725 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str},
3726 { 0xd0, 4, 64, 512*1024, l3_cache_str},
3727 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
3728 { 0xc0, 4, 0, 8, dtlb44_str },
3729 { 0xba, 4, 0, 64, dtlb4k_str },
3730 { 0xb4, 4, 0, 256, dtlb4k_str },
3731 { 0xb3, 4, 0, 128, dtlb4k_str },
3732 { 0xb2, 4, 0, 64, itlb4k_str },
3733 { 0xb0, 4, 0, 128, itlb4k_str },
3734 { 0x87, 8, 64, 1024*1024, l2_cache_str},
3735 { 0x86, 4, 64, 512*1024, l2_cache_str},
3736 { 0x85, 8, 32, 2*1024*1024, l2_cache_str},
3737 { 0x84, 8, 32, 1024*1024, l2_cache_str},
3738 { 0x83, 8, 32, 512*1024, l2_cache_str},
3739 { 0x82, 8, 32, 256*1024, l2_cache_str},
3740 { 0x80, 8, 64, 512*1024, l2_cache_str},
3741 { 0x7f, 2, 64, 512*1024, l2_cache_str},
3742 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
3743 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
3744 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
3745 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
3746 { 0x79, 8, 64, 128*1024, sl2_cache_str},
3747 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3748 { 0x73, 8, 0, 64*1024, itrace_str},
3749 { 0x72, 8, 0, 32*1024, itrace_str},
3750 { 0x71, 8, 0, 16*1024, itrace_str},
3751 { 0x70, 8, 0, 12*1024, itrace_str},
3752 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
3753 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
3754 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
3755 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
3756 { 0x5d, 0, 0, 256, dtlb44_str},
3757 { 0x5c, 0, 0, 128, dtlb44_str},
3758 { 0x5b, 0, 0, 64, dtlb44_str},
3759 { 0x5a, 4, 0, 32, dtlb24_str},
3760 { 0x59, 0, 0, 16, dtlb4k_str},
3761 { 0x57, 4, 0, 16, dtlb4k_str},
3762 { 0x56, 4, 0, 16, dtlb4M_str},
3763 { 0x55, 0, 0, 7, itlb24_str},
3764 { 0x52, 0, 0, 256, itlb424_str},
3765 { 0x51, 0, 0, 128, itlb424_str},
3766 { 0x50, 0, 0, 64, itlb424_str},
3767 { 0x4f, 0, 0, 32, itlb4k_str},
3768 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str},
3769 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
3770 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
3771 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
3772 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
3773 { 0x49, 16, 64, 4*1024*1024, l3_cache_str},
3774 { 0x48, 12, 64, 3*1024*1024, l2_cache_str},
3775 { 0x47, 8, 64, 8*1024*1024, l3_cache_str},
3776 { 0x46, 4, 64, 4*1024*1024, l3_cache_str},
3777 { 0x45, 4, 32, 2*1024*1024, l2_cache_str},
3778 { 0x44, 4, 32, 1024*1024, l2_cache_str},
3779 { 0x43, 4, 32, 512*1024, l2_cache_str},
3780 { 0x42, 4, 32, 256*1024, l2_cache_str},
3781 { 0x41, 4, 32, 128*1024, l2_cache_str},
3782 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
3783 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
3784 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
3785 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3786 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
3787 { 0x39, 4, 64, 128*1024, sl2_cache_str},
3788 { 0x30, 8, 64, 32*1024, l1_icache_str},
3789 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
3790 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
3791 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
3792 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
3793 { 0x22, 4, 64, 512*1024, sl3_cache_str},
3794 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
3795 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
3796 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3797 { 0x0b, 4, 0, 4, itlb4M_str},
3798 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
3799 { 0x08, 4, 32, 16*1024, l1_icache_str},
3800 { 0x06, 4, 32, 8*1024, l1_icache_str},
3801 { 0x05, 4, 0, 32, dtlb4M_str},
3802 { 0x04, 4, 0, 8, dtlb4M_str},
3803 { 0x03, 4, 0, 64, dtlb4k_str},
3804 { 0x02, 4, 0, 2, itlb4M_str},
3805 { 0x01, 4, 0, 32, itlb4k_str},
3806 { 0 }
3807 };
3808
3809 static const struct cachetab cyrix_ctab[] = {
3810 { 0x70, 4, 0, 32, "tlb-4K" },
3811 { 0x80, 4, 16, 16*1024, "l1-cache" },
3812 { 0 }
3813 };
3814
3815 /*
3816 * Search a cache table for a matching entry
3817 */
3818 static const struct cachetab *
3819 find_cacheent(const struct cachetab *ct, uint_t code)
3820 {
3821 if (code != 0) {
3822 for (; ct->ct_code != 0; ct++)
3823 if (ct->ct_code <= code)
3824 break;
3825 if (ct->ct_code == code)
3826 return (ct);
3827 }
3828 return (NULL);
3829 }
3830
3831 /*
3832 * Populate cachetab entry with L2 or L3 cache-information using
3833 * cpuid function 4. This function is called from intel_walk_cacheinfo()
3834 * when descriptor 0x49 is encountered. It returns 0 if no such cache
3835 * information is found.
3836 */
3837 static int
3838 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
3839 {
3840 uint32_t level, i;
3841 int ret = 0;
3842
3843 for (i = 0; i < cpi->cpi_std_4_size; i++) {
3844 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
3845
3846 if (level == 2 || level == 3) {
3847 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
3848 ct->ct_line_size =
3849 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
3850 ct->ct_size = ct->ct_assoc *
3851 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
3852 ct->ct_line_size *
3853 (cpi->cpi_std_4[i]->cp_ecx + 1);
3854
3855 if (level == 2) {
3856 ct->ct_label = l2_cache_str;
3857 } else if (level == 3) {
3858 ct->ct_label = l3_cache_str;
3859 }
3860 ret = 1;
3861 }
3862 }
3863
3864 return (ret);
3865 }
3866
3867 /*
3868 * Walk the cacheinfo descriptor, applying 'func' to every valid element
3869 * The walk is terminated if the walker returns non-zero.
3870 */
3871 static void
3872 intel_walk_cacheinfo(struct cpuid_info *cpi,
3873 void *arg, int (*func)(void *, const struct cachetab *))
3874 {
3875 const struct cachetab *ct;
3876 struct cachetab des_49_ct, des_b1_ct;
3877 uint8_t *dp;
3878 int i;
3879
3880 if ((dp = cpi->cpi_cacheinfo) == NULL)
3881 return;
3882 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3883 /*
3884 * For overloaded descriptor 0x49 we use cpuid function 4
3885 * if supported by the current processor, to create
3886 * cache information.
3887 * For overloaded descriptor 0xb1 we use X86_PAE flag
3888 * to disambiguate the cache information.
3889 */
3890 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
3891 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
3892 ct = &des_49_ct;
3893 } else if (*dp == 0xb1) {
3894 des_b1_ct.ct_code = 0xb1;
3895 des_b1_ct.ct_assoc = 4;
3896 des_b1_ct.ct_line_size = 0;
3897 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
3898 des_b1_ct.ct_size = 8;
3899 des_b1_ct.ct_label = itlb2M_str;
3900 } else {
3901 des_b1_ct.ct_size = 4;
3902 des_b1_ct.ct_label = itlb4M_str;
3903 }
3904 ct = &des_b1_ct;
3905 } else {
3906 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
3907 continue;
3908 }
3909 }
3910
3911 if (func(arg, ct) != 0) {
3912 break;
3913 }
3914 }
3915 }
3916
3917 /*
3918 * (Like the Intel one, except for Cyrix CPUs)
3919 */
3920 static void
3921 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
3922 void *arg, int (*func)(void *, const struct cachetab *))
3923 {
3924 const struct cachetab *ct;
3925 uint8_t *dp;
3926 int i;
3927
3928 if ((dp = cpi->cpi_cacheinfo) == NULL)
3929 return;
3930 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3931 /*
3932 * Search Cyrix-specific descriptor table first ..
3933 */
3934 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
3935 if (func(arg, ct) != 0)
3936 break;
3937 continue;
3938 }
3939 /*
3940 * .. else fall back to the Intel one
3941 */
3942 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
3943 if (func(arg, ct) != 0)
3944 break;
3945 continue;
3946 }
3947 }
3948 }
3949
3950 /*
3951 * A cacheinfo walker that adds associativity, line-size, and size properties
3952 * to the devinfo node it is passed as an argument.
3953 */
3954 static int
3955 add_cacheent_props(void *arg, const struct cachetab *ct)
3956 {
3957 dev_info_t *devi = arg;
3958
3959 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
3960 if (ct->ct_line_size != 0)
3961 add_cache_prop(devi, ct->ct_label, line_str,
3962 ct->ct_line_size);
3963 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
3964 return (0);
3965 }
3966
3967
3968 static const char fully_assoc[] = "fully-associative?";
3969
3970 /*
3971 * AMD style cache/tlb description
3972 *
3973 * Extended functions 5 and 6 directly describe properties of
3974 * tlbs and various cache levels.
3975 */
3976 static void
3977 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3978 {
3979 switch (assoc) {
3980 case 0: /* reserved; ignore */
3981 break;
3982 default:
3983 add_cache_prop(devi, label, assoc_str, assoc);
3984 break;
3985 case 0xff:
3986 add_cache_prop(devi, label, fully_assoc, 1);
3987 break;
3988 }
3989 }
3990
3991 static void
3992 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
3993 {
3994 if (size == 0)
3995 return;
3996 add_cache_prop(devi, label, size_str, size);
3997 add_amd_assoc(devi, label, assoc);
3998 }
3999
4000 static void
4001 add_amd_cache(dev_info_t *devi, const char *label,
4002 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4003 {
4004 if (size == 0 || line_size == 0)
4005 return;
4006 add_amd_assoc(devi, label, assoc);
4007 /*
4008 * Most AMD parts have a sectored cache. Multiple cache lines are
4009 * associated with each tag. A sector consists of all cache lines
4010 * associated with a tag. For example, the AMD K6-III has a sector
4011 * size of 2 cache lines per tag.
4012 */
4013 if (lines_per_tag != 0)
4014 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4015 add_cache_prop(devi, label, line_str, line_size);
4016 add_cache_prop(devi, label, size_str, size * 1024);
4017 }
4018
4019 static void
4020 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4021 {
4022 switch (assoc) {
4023 case 0: /* off */
4024 break;
4025 case 1:
4026 case 2:
4027 case 4:
4028 add_cache_prop(devi, label, assoc_str, assoc);
4029 break;
4030 case 6:
4031 add_cache_prop(devi, label, assoc_str, 8);
4032 break;
4033 case 8:
4034 add_cache_prop(devi, label, assoc_str, 16);
4035 break;
4036 case 0xf:
4037 add_cache_prop(devi, label, fully_assoc, 1);
4038 break;
4039 default: /* reserved; ignore */
4040 break;
4041 }
4042 }
4043
4044 static void
4045 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4046 {
4047 if (size == 0 || assoc == 0)
4048 return;
4049 add_amd_l2_assoc(devi, label, assoc);
4050 add_cache_prop(devi, label, size_str, size);
4051 }
4052
4053 static void
4054 add_amd_l2_cache(dev_info_t *devi, const char *label,
4055 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4056 {
4057 if (size == 0 || assoc == 0 || line_size == 0)
4058 return;
4059 add_amd_l2_assoc(devi, label, assoc);
4060 if (lines_per_tag != 0)
4061 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4062 add_cache_prop(devi, label, line_str, line_size);
4063 add_cache_prop(devi, label, size_str, size * 1024);
4064 }
4065
4066 static void
4067 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
4068 {
4069 struct cpuid_regs *cp;
4070
4071 if (cpi->cpi_xmaxeax < 0x80000005)
4072 return;
4073 cp = &cpi->cpi_extd[5];
4074
4075 /*
4076 * 4M/2M L1 TLB configuration
4077 *
4078 * We report the size for 2M pages because AMD uses two
4079 * TLB entries for one 4M page.
4080 */
4081 add_amd_tlb(devi, "dtlb-2M",
4082 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
4083 add_amd_tlb(devi, "itlb-2M",
4084 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
4085
4086 /*
4087 * 4K L1 TLB configuration
4088 */
4089
4090 switch (cpi->cpi_vendor) {
4091 uint_t nentries;
4092 case X86_VENDOR_TM:
4093 if (cpi->cpi_family >= 5) {
4094 /*
4095 * Crusoe processors have 256 TLB entries, but
4096 * cpuid data format constrains them to only
4097 * reporting 255 of them.
4098 */
4099 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
4100 nentries = 256;
4101 /*
4102 * Crusoe processors also have a unified TLB
4103 */
4104 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
4105 nentries);
4106 break;
4107 }
4108 /*FALLTHROUGH*/
4109 default:
4110 add_amd_tlb(devi, itlb4k_str,
4111 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
4112 add_amd_tlb(devi, dtlb4k_str,
4113 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
4114 break;
4115 }
4116
4117 /*
4118 * data L1 cache configuration
4119 */
4120
4121 add_amd_cache(devi, l1_dcache_str,
4122 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
4123 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
4124
4125 /*
4126 * code L1 cache configuration
4127 */
4128
4129 add_amd_cache(devi, l1_icache_str,
4130 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
4131 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
4132
4133 if (cpi->cpi_xmaxeax < 0x80000006)
4134 return;
4135 cp = &cpi->cpi_extd[6];
4136
4137 /* Check for a unified L2 TLB for large pages */
4138
4139 if (BITX(cp->cp_eax, 31, 16) == 0)
4140 add_amd_l2_tlb(devi, "l2-tlb-2M",
4141 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4142 else {
4143 add_amd_l2_tlb(devi, "l2-dtlb-2M",
4144 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4145 add_amd_l2_tlb(devi, "l2-itlb-2M",
4146 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4147 }
4148
4149 /* Check for a unified L2 TLB for 4K pages */
4150
4151 if (BITX(cp->cp_ebx, 31, 16) == 0) {
4152 add_amd_l2_tlb(devi, "l2-tlb-4K",
4153 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4154 } else {
4155 add_amd_l2_tlb(devi, "l2-dtlb-4K",
4156 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4157 add_amd_l2_tlb(devi, "l2-itlb-4K",
4158 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4159 }
4160
4161 add_amd_l2_cache(devi, l2_cache_str,
4162 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
4163 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
4164 }
4165
4166 /*
4167 * There are two basic ways that the x86 world describes it cache
4168 * and tlb architecture - Intel's way and AMD's way.
4169 *
4170 * Return which flavor of cache architecture we should use
4171 */
4172 static int
4173 x86_which_cacheinfo(struct cpuid_info *cpi)
4174 {
4175 switch (cpi->cpi_vendor) {
4176 case X86_VENDOR_Intel:
4177 if (cpi->cpi_maxeax >= 2)
4178 return (X86_VENDOR_Intel);
4179 break;
4180 case X86_VENDOR_AMD:
4181 /*
4182 * The K5 model 1 was the first part from AMD that reported
4183 * cache sizes via extended cpuid functions.
4184 */
4185 if (cpi->cpi_family > 5 ||
4186 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
4187 return (X86_VENDOR_AMD);
4188 break;
4189 case X86_VENDOR_TM:
4190 if (cpi->cpi_family >= 5)
4191 return (X86_VENDOR_AMD);
4192 /*FALLTHROUGH*/
4193 default:
4194 /*
4195 * If they have extended CPU data for 0x80000005
4196 * then we assume they have AMD-format cache
4197 * information.
4198 *
4199 * If not, and the vendor happens to be Cyrix,
4200 * then try our-Cyrix specific handler.
4201 *
4202 * If we're not Cyrix, then assume we're using Intel's
4203 * table-driven format instead.
4204 */
4205 if (cpi->cpi_xmaxeax >= 0x80000005)
4206 return (X86_VENDOR_AMD);
4207 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
4208 return (X86_VENDOR_Cyrix);
4209 else if (cpi->cpi_maxeax >= 2)
4210 return (X86_VENDOR_Intel);
4211 break;
4212 }
4213 return (-1);
4214 }
4215
4216 void
4217 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
4218 struct cpuid_info *cpi)
4219 {
4220 dev_info_t *cpu_devi;
4221 int create;
4222
4223 cpu_devi = (dev_info_t *)dip;
4224
4225 /* device_type */
4226 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4227 "device_type", "cpu");
4228
4229 /* reg */
4230 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4231 "reg", cpu_id);
4232
4233 /* cpu-mhz, and clock-frequency */
4234 if (cpu_freq > 0) {
4235 long long mul;
4236
4237 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4238 "cpu-mhz", cpu_freq);
4239 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
4240 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4241 "clock-frequency", (int)mul);
4242 }
4243
4244 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
4245 return;
4246 }
4247
4248 /* vendor-id */
4249 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4250 "vendor-id", cpi->cpi_vendorstr);
4251
4252 if (cpi->cpi_maxeax == 0) {
4253 return;
4254 }
4255
4256 /*
4257 * family, model, and step
4258 */
4259 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4260 "family", CPI_FAMILY(cpi));
4261 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4262 "cpu-model", CPI_MODEL(cpi));
4263 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4264 "stepping-id", CPI_STEP(cpi));
4265
4266 /* type */
4267 switch (cpi->cpi_vendor) {
4268 case X86_VENDOR_Intel:
4269 create = 1;
4270 break;
4271 default:
4272 create = 0;
4273 break;
4274 }
4275 if (create)
4276 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4277 "type", CPI_TYPE(cpi));
4278
4279 /* ext-family */
4280 switch (cpi->cpi_vendor) {
4281 case X86_VENDOR_Intel:
4282 case X86_VENDOR_AMD:
4283 create = cpi->cpi_family >= 0xf;
4284 break;
4285 default:
4286 create = 0;
4287 break;
4288 }
4289 if (create)
4290 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4291 "ext-family", CPI_FAMILY_XTD(cpi));
4292
4293 /* ext-model */
4294 switch (cpi->cpi_vendor) {
4295 case X86_VENDOR_Intel:
4296 create = IS_EXTENDED_MODEL_INTEL(cpi);
4297 break;
4298 case X86_VENDOR_AMD:
4299 create = CPI_FAMILY(cpi) == 0xf;
4300 break;
4301 default:
4302 create = 0;
4303 break;
4304 }
4305 if (create)
4306 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4307 "ext-model", CPI_MODEL_XTD(cpi));
4308
4309 /* generation */
4310 switch (cpi->cpi_vendor) {
4311 case X86_VENDOR_AMD:
4312 /*
4313 * AMD K5 model 1 was the first part to support this
4314 */
4315 create = cpi->cpi_xmaxeax >= 0x80000001;
4316 break;
4317 default:
4318 create = 0;
4319 break;
4320 }
4321 if (create)
4322 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4323 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
4324
4325 /* brand-id */
4326 switch (cpi->cpi_vendor) {
4327 case X86_VENDOR_Intel:
4328 /*
4329 * brand id first appeared on Pentium III Xeon model 8,
4330 * and Celeron model 8 processors and Opteron
4331 */
4332 create = cpi->cpi_family > 6 ||
4333 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
4334 break;
4335 case X86_VENDOR_AMD:
4336 create = cpi->cpi_family >= 0xf;
4337 break;
4338 default:
4339 create = 0;
4340 break;
4341 }
4342 if (create && cpi->cpi_brandid != 0) {
4343 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4344 "brand-id", cpi->cpi_brandid);
4345 }
4346
4347 /* chunks, and apic-id */
4348 switch (cpi->cpi_vendor) {
4349 /*
4350 * first available on Pentium IV and Opteron (K8)
4351 */
4352 case X86_VENDOR_Intel:
4353 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4354 break;
4355 case X86_VENDOR_AMD:
4356 create = cpi->cpi_family >= 0xf;
4357 break;
4358 default:
4359 create = 0;
4360 break;
4361 }
4362 if (create) {
4363 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4364 "chunks", CPI_CHUNKS(cpi));
4365 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4366 "apic-id", cpi->cpi_apicid);
4367 if (cpi->cpi_chipid >= 0) {
4368 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4369 "chip#", cpi->cpi_chipid);
4370 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4371 "clog#", cpi->cpi_clogid);
4372 }
4373 }
4374
4375 /* cpuid-features */
4376 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4377 "cpuid-features", CPI_FEATURES_EDX(cpi));
4378
4379
4380 /* cpuid-features-ecx */
4381 switch (cpi->cpi_vendor) {
4382 case X86_VENDOR_Intel:
4383 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4384 break;
4385 case X86_VENDOR_AMD:
4386 create = cpi->cpi_family >= 0xf;
4387 break;
4388 default:
4389 create = 0;
4390 break;
4391 }
4392 if (create)
4393 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4394 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4395
4396 /* ext-cpuid-features */
4397 switch (cpi->cpi_vendor) {
4398 case X86_VENDOR_Intel:
4399 case X86_VENDOR_AMD:
4400 case X86_VENDOR_Cyrix:
4401 case X86_VENDOR_TM:
4402 case X86_VENDOR_Centaur:
4403 create = cpi->cpi_xmaxeax >= 0x80000001;
4404 break;
4405 default:
4406 create = 0;
4407 break;
4408 }
4409 if (create) {
4410 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4411 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
4412 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4413 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
4414 }
4415
4416 /*
4417 * Brand String first appeared in Intel Pentium IV, AMD K5
4418 * model 1, and Cyrix GXm. On earlier models we try and
4419 * simulate something similar .. so this string should always
4420 * same -something- about the processor, however lame.
4421 */
4422 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4423 "brand-string", cpi->cpi_brandstr);
4424
4425 /*
4426 * Finally, cache and tlb information
4427 */
4428 switch (x86_which_cacheinfo(cpi)) {
4429 case X86_VENDOR_Intel:
4430 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4431 break;
4432 case X86_VENDOR_Cyrix:
4433 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4434 break;
4435 case X86_VENDOR_AMD:
4436 amd_cache_info(cpi, cpu_devi);
4437 break;
4438 default:
4439 break;
4440 }
4441 }
4442
4443 struct l2info {
4444 int *l2i_csz;
4445 int *l2i_lsz;
4446 int *l2i_assoc;
4447 int l2i_ret;
4448 };
4449
4450 /*
4451 * A cacheinfo walker that fetches the size, line-size and associativity
4452 * of the L2 cache
4453 */
4454 static int
4455 intel_l2cinfo(void *arg, const struct cachetab *ct)
4456 {
4457 struct l2info *l2i = arg;
4458 int *ip;
4459
4460 if (ct->ct_label != l2_cache_str &&
4461 ct->ct_label != sl2_cache_str)
4462 return (0); /* not an L2 -- keep walking */
4463
4464 if ((ip = l2i->l2i_csz) != NULL)
4465 *ip = ct->ct_size;
4466 if ((ip = l2i->l2i_lsz) != NULL)
4467 *ip = ct->ct_line_size;
4468 if ((ip = l2i->l2i_assoc) != NULL)
4469 *ip = ct->ct_assoc;
4470 l2i->l2i_ret = ct->ct_size;
4471 return (1); /* was an L2 -- terminate walk */
4472 }
4473
4474 /*
4475 * AMD L2/L3 Cache and TLB Associativity Field Definition:
4476 *
4477 * Unlike the associativity for the L1 cache and tlb where the 8 bit
4478 * value is the associativity, the associativity for the L2 cache and
4479 * tlb is encoded in the following table. The 4 bit L2 value serves as
4480 * an index into the amd_afd[] array to determine the associativity.
4481 * -1 is undefined. 0 is fully associative.
4482 */
4483
4484 static int amd_afd[] =
4485 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
4486
4487 static void
4488 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
4489 {
4490 struct cpuid_regs *cp;
4491 uint_t size, assoc;
4492 int i;
4493 int *ip;
4494
4495 if (cpi->cpi_xmaxeax < 0x80000006)
4496 return;
4497 cp = &cpi->cpi_extd[6];
4498
4499 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
4500 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
4501 uint_t cachesz = size * 1024;
4502 assoc = amd_afd[i];
4503
4504 ASSERT(assoc != -1);
4505
4506 if ((ip = l2i->l2i_csz) != NULL)
4507 *ip = cachesz;
4508 if ((ip = l2i->l2i_lsz) != NULL)
4509 *ip = BITX(cp->cp_ecx, 7, 0);
4510 if ((ip = l2i->l2i_assoc) != NULL)
4511 *ip = assoc;
4512 l2i->l2i_ret = cachesz;
4513 }
4514 }
4515
4516 int
4517 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
4518 {
4519 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
4520 struct l2info __l2info, *l2i = &__l2info;
4521
4522 l2i->l2i_csz = csz;
4523 l2i->l2i_lsz = lsz;
4524 l2i->l2i_assoc = assoc;
4525 l2i->l2i_ret = -1;
4526
4527 switch (x86_which_cacheinfo(cpi)) {
4528 case X86_VENDOR_Intel:
4529 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4530 break;
4531 case X86_VENDOR_Cyrix:
4532 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4533 break;
4534 case X86_VENDOR_AMD:
4535 amd_l2cacheinfo(cpi, l2i);
4536 break;
4537 default:
4538 break;
4539 }
4540 return (l2i->l2i_ret);
4541 }
4542
4543 #if !defined(__xpv)
4544
4545 uint32_t *
4546 cpuid_mwait_alloc(cpu_t *cpu)
4547 {
4548 uint32_t *ret;
4549 size_t mwait_size;
4550
4551 ASSERT(cpuid_checkpass(CPU, 2));
4552
4553 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
4554 if (mwait_size == 0)
4555 return (NULL);
4556
4557 /*
4558 * kmem_alloc() returns cache line size aligned data for mwait_size
4559 * allocations. mwait_size is currently cache line sized. Neither
4560 * of these implementation details are guarantied to be true in the
4561 * future.
4562 *
4563 * First try allocating mwait_size as kmem_alloc() currently returns
4564 * correctly aligned memory. If kmem_alloc() does not return
4565 * mwait_size aligned memory, then use mwait_size ROUNDUP.
4566 *
4567 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
4568 * decide to free this memory.
4569 */
4570 ret = kmem_zalloc(mwait_size, KM_SLEEP);
4571 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
4572 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4573 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
4574 *ret = MWAIT_RUNNING;
4575 return (ret);
4576 } else {
4577 kmem_free(ret, mwait_size);
4578 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
4579 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4580 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
4581 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
4582 *ret = MWAIT_RUNNING;
4583 return (ret);
4584 }
4585 }
4586
4587 void
4588 cpuid_mwait_free(cpu_t *cpu)
4589 {
4590 if (cpu->cpu_m.mcpu_cpi == NULL) {
4591 return;
4592 }
4593
4594 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
4595 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
4596 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
4597 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
4598 }
4599
4600 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
4601 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4602 }
4603
4604 void
4605 patch_tsc_read(int flag)
4606 {
4607 size_t cnt;
4608
4609 switch (flag) {
4610 case X86_NO_TSC:
4611 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
4612 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
4613 break;
4614 case X86_HAVE_TSCP:
4615 cnt = &_tscp_end - &_tscp_start;
4616 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
4617 break;
4618 case X86_TSC_MFENCE:
4619 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
4620 (void) memcpy((void *)tsc_read,
4621 (void *)&_tsc_mfence_start, cnt);
4622 break;
4623 case X86_TSC_LFENCE:
4624 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
4625 (void) memcpy((void *)tsc_read,
4626 (void *)&_tsc_lfence_start, cnt);
4627 break;
4628 default:
4629 break;
4630 }
4631 }
4632
4633 int
4634 cpuid_deep_cstates_supported(void)
4635 {
4636 struct cpuid_info *cpi;
4637 struct cpuid_regs regs;
4638
4639 ASSERT(cpuid_checkpass(CPU, 1));
4640
4641 cpi = CPU->cpu_m.mcpu_cpi;
4642
4643 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
4644 return (0);
4645
4646 switch (cpi->cpi_vendor) {
4647 case X86_VENDOR_Intel:
4648 if (cpi->cpi_xmaxeax < 0x80000007)
4649 return (0);
4650
4651 /*
4652 * TSC run at a constant rate in all ACPI C-states?
4653 */
4654 regs.cp_eax = 0x80000007;
4655 (void) __cpuid_insn(®s);
4656 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
4657
4658 default:
4659 return (0);
4660 }
4661 }
4662
4663 #endif /* !__xpv */
4664
4665 void
4666 post_startup_cpu_fixups(void)
4667 {
4668 #ifndef __xpv
4669 /*
4670 * Some AMD processors support C1E state. Entering this state will
4671 * cause the local APIC timer to stop, which we can't deal with at
4672 * this time.
4673 */
4674 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
4675 on_trap_data_t otd;
4676 uint64_t reg;
4677
4678 if (!on_trap(&otd, OT_DATA_ACCESS)) {
4679 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
4680 /* Disable C1E state if it is enabled by BIOS */
4681 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
4682 AMD_ACTONCMPHALT_MASK) {
4683 reg &= ~(AMD_ACTONCMPHALT_MASK <<
4684 AMD_ACTONCMPHALT_SHIFT);
4685 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
4686 }
4687 }
4688 no_trap();
4689 }
4690 #endif /* !__xpv */
4691 }
4692
4693 /*
4694 * Setup necessary registers to enable XSAVE feature on this processor.
4695 * This function needs to be called early enough, so that no xsave/xrstor
4696 * ops will execute on the processor before the MSRs are properly set up.
4697 *
4698 * Current implementation has the following assumption:
4699 * - cpuid_pass1() is done, so that X86 features are known.
4700 * - fpu_probe() is done, so that fp_save_mech is chosen.
4701 */
4702 void
4703 xsave_setup_msr(cpu_t *cpu)
4704 {
4705 ASSERT(fp_save_mech == FP_XSAVE);
4706 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
4707
4708 /* Enable OSXSAVE in CR4. */
4709 setcr4(getcr4() | CR4_OSXSAVE);
4710 /*
4711 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
4712 * correct value.
4713 */
4714 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE;
4715 setup_xfem();
4716 }
4717
4718 /*
4719 * Starting with the Westmere processor the local
4720 * APIC timer will continue running in all C-states,
4721 * including the deepest C-states.
4722 */
4723 int
4724 cpuid_arat_supported(void)
4725 {
4726 struct cpuid_info *cpi;
4727 struct cpuid_regs regs;
4728
4729 ASSERT(cpuid_checkpass(CPU, 1));
4730 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4731
4732 cpi = CPU->cpu_m.mcpu_cpi;
4733
4734 switch (cpi->cpi_vendor) {
4735 case X86_VENDOR_Intel:
4736 /*
4737 * Always-running Local APIC Timer is
4738 * indicated by CPUID.6.EAX[2].
4739 */
4740 if (cpi->cpi_maxeax >= 6) {
4741 regs.cp_eax = 6;
4742 (void) cpuid_insn(NULL, ®s);
4743 return (regs.cp_eax & CPUID_CSTATE_ARAT);
4744 } else {
4745 return (0);
4746 }
4747 default:
4748 return (0);
4749 }
4750 }
4751
4752 /*
4753 * Check support for Intel ENERGY_PERF_BIAS feature
4754 */
4755 int
4756 cpuid_iepb_supported(struct cpu *cp)
4757 {
4758 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
4759 struct cpuid_regs regs;
4760
4761 ASSERT(cpuid_checkpass(cp, 1));
4762
4763 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) ||
4764 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
4765 return (0);
4766 }
4767
4768 /*
4769 * Intel ENERGY_PERF_BIAS MSR is indicated by
4770 * capability bit CPUID.6.ECX.3
4771 */
4772 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6))
4773 return (0);
4774
4775 regs.cp_eax = 0x6;
4776 (void) cpuid_insn(NULL, ®s);
4777 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
4778 }
4779
4780 /*
4781 * Check support for TSC deadline timer
4782 *
4783 * TSC deadline timer provides a superior software programming
4784 * model over local APIC timer that eliminates "time drifts".
4785 * Instead of specifying a relative time, software specifies an
4786 * absolute time as the target at which the processor should
4787 * generate a timer event.
4788 */
4789 int
4790 cpuid_deadline_tsc_supported(void)
4791 {
4792 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
4793 struct cpuid_regs regs;
4794
4795 ASSERT(cpuid_checkpass(CPU, 1));
4796 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4797
4798 switch (cpi->cpi_vendor) {
4799 case X86_VENDOR_Intel:
4800 if (cpi->cpi_maxeax >= 1) {
4801 regs.cp_eax = 1;
4802 (void) cpuid_insn(NULL, ®s);
4803 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
4804 } else {
4805 return (0);
4806 }
4807 default:
4808 return (0);
4809 }
4810 }
4811
4812 #if defined(__amd64) && !defined(__xpv)
4813 /*
4814 * Patch in versions of bcopy for high performance Intel Nhm processors
4815 * and later...
4816 */
4817 void
4818 patch_memops(uint_t vendor)
4819 {
4820 size_t cnt, i;
4821 caddr_t to, from;
4822
4823 if ((vendor == X86_VENDOR_Intel) &&
4824 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
4825 cnt = &bcopy_patch_end - &bcopy_patch_start;
4826 to = &bcopy_ck_size;
4827 from = &bcopy_patch_start;
4828 for (i = 0; i < cnt; i++) {
4829 *to++ = *from++;
4830 }
4831 }
4832 }
4833 #endif /* __amd64 && !__xpv */
4834
4835 /*
4836 * This function finds the number of bits to represent the number of cores per
4837 * chip and the number of strands per core for the Intel platforms.
4838 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
4839 */
4840 void
4841 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits)
4842 {
4843 struct cpuid_regs regs;
4844 struct cpuid_regs *cp = ®s;
4845
4846 if (vendor != X86_VENDOR_Intel) {
4847 return;
4848 }
4849
4850 /* if the cpuid level is 0xB, extended topo is available. */
4851 cp->cp_eax = 0;
4852 if (__cpuid_insn(cp) >= 0xB) {
4853
4854 cp->cp_eax = 0xB;
4855 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
4856 (void) __cpuid_insn(cp);
4857
4858 /*
4859 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
4860 * indicates that the extended topology enumeration leaf is
4861 * available.
4862 */
4863 if (cp->cp_ebx) {
4864 uint_t coreid_shift = 0;
4865 uint_t chipid_shift = 0;
4866 uint_t i;
4867 uint_t level;
4868
4869 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
4870 cp->cp_eax = 0xB;
4871 cp->cp_ecx = i;
4872
4873 (void) __cpuid_insn(cp);
4874 level = CPI_CPU_LEVEL_TYPE(cp);
4875
4876 if (level == 1) {
4877 /*
4878 * Thread level processor topology
4879 * Number of bits shift right APIC ID
4880 * to get the coreid.
4881 */
4882 coreid_shift = BITX(cp->cp_eax, 4, 0);
4883 } else if (level == 2) {
4884 /*
4885 * Core level processor topology
4886 * Number of bits shift right APIC ID
4887 * to get the chipid.
4888 */
4889 chipid_shift = BITX(cp->cp_eax, 4, 0);
4890 }
4891 }
4892
4893 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
4894 *strand_nbits = coreid_shift;
4895 *core_nbits = chipid_shift - coreid_shift;
4896 }
4897 }
4898 }
4899 }