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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 25 */
26 26 /*
27 27 * Copyright (c) 2010, Intel Corporation.
28 28 * All rights reserved.
29 29 */
30 30 /*
31 31 * Copyright 2016 Joyent, Inc.
32 32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 34 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124 124
125 125 /*
126 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 127 */
128 128
129 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 139 /* 0x00000400 - sysc on K6m6 */
140 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 148 /* 0x00040000 - reserved */
149 149 /* 0x00080000 - reserved */
150 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 151 /* 0x00200000 - reserved */
152 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 158 /* 0x10000000 - reserved */
159 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162 162
163 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 177 /* 0x00004000 - reserved */
178 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 180 /* 0x00020000 - reserved */
181 181 /* 0x00040000 - reserved */
182 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 183 /* 0x00100000 - reserved */
184 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186 186
187 187 /*
188 188 * Intel now seems to have claimed part of the "extended" function
189 189 * space that we previously for non-Intel implementors to use.
190 190 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
191 191 * is available in long mode i.e. what AMD indicate using bit 0.
192 192 * On the other hand, everything else is labelled as reserved.
193 193 */
194 194 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
195 195
196 196 /*
197 197 * Intel also uses cpuid leaf 7 to have additional instructions and features.
198 198 * Like some other leaves, but unlike the current ones we care about, it
199 199 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
200 200 * with the potential use of additional sub-leaves in the future, we now
201 201 * specifically label the EBX features with their leaf and sub-leaf.
202 202 */
203 203 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
204 204 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
205 205 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
206 206 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
207 207 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
208 208 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
209 209 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
210 210
211 211 #define P5_MCHADDR 0x0
212 212 #define P5_CESR 0x11
213 213 #define P5_CTR0 0x12
214 214 #define P5_CTR1 0x13
215 215
216 216 #define K5_MCHADDR 0x0
217 217 #define K5_MCHTYPE 0x01
218 218 #define K5_TSC 0x10
219 219 #define K5_TR12 0x12
220 220
221 221 #define REG_PAT 0x277
222 222
223 223 #define REG_MC0_CTL 0x400
224 224 #define REG_MC5_MISC 0x417
225 225 #define REG_PERFCTR0 0xc1
226 226 #define REG_PERFCTR1 0xc2
227 227
228 228 #define REG_PERFEVNT0 0x186
229 229 #define REG_PERFEVNT1 0x187
230 230
231 231 #define REG_TSC 0x10 /* timestamp counter */
232 232 #define REG_APIC_BASE_MSR 0x1b
233 233 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
234 234
235 235 #if !defined(__xpv)
236 236 /*
237 237 * AMD C1E
238 238 */
239 239 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
240 240 #define AMD_ACTONCMPHALT_SHIFT 27
241 241 #define AMD_ACTONCMPHALT_MASK 3
242 242 #endif
243 243
244 244 #define MSR_DEBUGCTL 0x1d9
245 245
246 246 #define DEBUGCTL_LBR 0x01
247 247 #define DEBUGCTL_BTF 0x02
248 248
249 249 /* Intel P6, AMD */
250 250 #define MSR_LBR_FROM 0x1db
251 251 #define MSR_LBR_TO 0x1dc
252 252 #define MSR_LEX_FROM 0x1dd
253 253 #define MSR_LEX_TO 0x1de
254 254
255 255 /* Intel P4 (pre-Prescott, non P4 M) */
256 256 #define MSR_P4_LBSTK_TOS 0x1da
257 257 #define MSR_P4_LBSTK_0 0x1db
258 258 #define MSR_P4_LBSTK_1 0x1dc
259 259 #define MSR_P4_LBSTK_2 0x1dd
260 260 #define MSR_P4_LBSTK_3 0x1de
261 261
262 262 /* Intel Pentium M */
263 263 #define MSR_P6M_LBSTK_TOS 0x1c9
264 264 #define MSR_P6M_LBSTK_0 0x040
265 265 #define MSR_P6M_LBSTK_1 0x041
266 266 #define MSR_P6M_LBSTK_2 0x042
267 267 #define MSR_P6M_LBSTK_3 0x043
268 268 #define MSR_P6M_LBSTK_4 0x044
269 269 #define MSR_P6M_LBSTK_5 0x045
270 270 #define MSR_P6M_LBSTK_6 0x046
271 271 #define MSR_P6M_LBSTK_7 0x047
272 272
273 273 /* Intel P4 (Prescott) */
274 274 #define MSR_PRP4_LBSTK_TOS 0x1da
275 275 #define MSR_PRP4_LBSTK_FROM_0 0x680
276 276 #define MSR_PRP4_LBSTK_FROM_1 0x681
277 277 #define MSR_PRP4_LBSTK_FROM_2 0x682
278 278 #define MSR_PRP4_LBSTK_FROM_3 0x683
279 279 #define MSR_PRP4_LBSTK_FROM_4 0x684
280 280 #define MSR_PRP4_LBSTK_FROM_5 0x685
281 281 #define MSR_PRP4_LBSTK_FROM_6 0x686
282 282 #define MSR_PRP4_LBSTK_FROM_7 0x687
283 283 #define MSR_PRP4_LBSTK_FROM_8 0x688
284 284 #define MSR_PRP4_LBSTK_FROM_9 0x689
285 285 #define MSR_PRP4_LBSTK_FROM_10 0x68a
286 286 #define MSR_PRP4_LBSTK_FROM_11 0x68b
287 287 #define MSR_PRP4_LBSTK_FROM_12 0x68c
288 288 #define MSR_PRP4_LBSTK_FROM_13 0x68d
289 289 #define MSR_PRP4_LBSTK_FROM_14 0x68e
290 290 #define MSR_PRP4_LBSTK_FROM_15 0x68f
291 291 #define MSR_PRP4_LBSTK_TO_0 0x6c0
292 292 #define MSR_PRP4_LBSTK_TO_1 0x6c1
293 293 #define MSR_PRP4_LBSTK_TO_2 0x6c2
294 294 #define MSR_PRP4_LBSTK_TO_3 0x6c3
295 295 #define MSR_PRP4_LBSTK_TO_4 0x6c4
296 296 #define MSR_PRP4_LBSTK_TO_5 0x6c5
297 297 #define MSR_PRP4_LBSTK_TO_6 0x6c6
298 298 #define MSR_PRP4_LBSTK_TO_7 0x6c7
299 299 #define MSR_PRP4_LBSTK_TO_8 0x6c8
300 300 #define MSR_PRP4_LBSTK_TO_9 0x6c9
301 301 #define MSR_PRP4_LBSTK_TO_10 0x6ca
302 302 #define MSR_PRP4_LBSTK_TO_11 0x6cb
303 303 #define MSR_PRP4_LBSTK_TO_12 0x6cc
304 304 #define MSR_PRP4_LBSTK_TO_13 0x6cd
305 305 #define MSR_PRP4_LBSTK_TO_14 0x6ce
306 306 #define MSR_PRP4_LBSTK_TO_15 0x6cf
307 307
308 308 #define MCI_CTL_VALUE 0xffffffff
309 309
310 310 #define MTRR_TYPE_UC 0
311 311 #define MTRR_TYPE_WC 1
312 312 #define MTRR_TYPE_WT 4
313 313 #define MTRR_TYPE_WP 5
314 314 #define MTRR_TYPE_WB 6
315 315 #define MTRR_TYPE_UC_ 7
316 316
317 317 /*
318 318 * For Solaris we set up the page attritubute table in the following way:
319 319 * PAT0 Write-Back
320 320 * PAT1 Write-Through
321 321 * PAT2 Unchacheable-
322 322 * PAT3 Uncacheable
323 323 * PAT4 Write-Back
324 324 * PAT5 Write-Through
325 325 * PAT6 Write-Combine
326 326 * PAT7 Uncacheable
327 327 * The only difference from h/w default is entry 6.
328 328 */
329 329 #define PAT_DEFAULT_ATTRIBUTE \
330 330 ((uint64_t)MTRR_TYPE_WB | \
331 331 ((uint64_t)MTRR_TYPE_WT << 8) | \
332 332 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
333 333 ((uint64_t)MTRR_TYPE_UC << 24) | \
334 334 ((uint64_t)MTRR_TYPE_WB << 32) | \
335 335 ((uint64_t)MTRR_TYPE_WT << 40) | \
336 336 ((uint64_t)MTRR_TYPE_WC << 48) | \
337 337 ((uint64_t)MTRR_TYPE_UC << 56))
338 338
339 339 #define X86FSET_LARGEPAGE 0
340 340 #define X86FSET_TSC 1
341 341 #define X86FSET_MSR 2
342 342 #define X86FSET_MTRR 3
343 343 #define X86FSET_PGE 4
344 344 #define X86FSET_DE 5
345 345 #define X86FSET_CMOV 6
346 346 #define X86FSET_MMX 7
347 347 #define X86FSET_MCA 8
348 348 #define X86FSET_PAE 9
349 349 #define X86FSET_CX8 10
350 350 #define X86FSET_PAT 11
351 351 #define X86FSET_SEP 12
352 352 #define X86FSET_SSE 13
353 353 #define X86FSET_SSE2 14
354 354 #define X86FSET_HTT 15
355 355 #define X86FSET_ASYSC 16
356 356 #define X86FSET_NX 17
357 357 #define X86FSET_SSE3 18
358 358 #define X86FSET_CX16 19
359 359 #define X86FSET_CMP 20
360 360 #define X86FSET_TSCP 21
361 361 #define X86FSET_MWAIT 22
362 362 #define X86FSET_SSE4A 23
363 363 #define X86FSET_CPUID 24
364 364 #define X86FSET_SSSE3 25
365 365 #define X86FSET_SSE4_1 26
366 366 #define X86FSET_SSE4_2 27
367 367 #define X86FSET_1GPG 28
368 368 #define X86FSET_CLFSH 29
369 369 #define X86FSET_64 30
370 370 #define X86FSET_AES 31
371 371 #define X86FSET_PCLMULQDQ 32
372 372 #define X86FSET_XSAVE 33
373 373 #define X86FSET_AVX 34
374 374 #define X86FSET_VMX 35
375 375 #define X86FSET_SVM 36
376 376 #define X86FSET_TOPOEXT 37
377 377 #define X86FSET_F16C 38
378 378 #define X86FSET_RDRAND 39
379 379 #define X86FSET_X2APIC 40
380 380 #define X86FSET_AVX2 41
381 381 #define X86FSET_BMI1 42
382 382 #define X86FSET_BMI2 43
383 383 #define X86FSET_FMA 44
384 384 #define X86FSET_SMEP 45
385 385 #define X86FSET_SMAP 46
386 386 #define X86FSET_ADX 47
387 387 #define X86FSET_RDSEED 48
388 388
389 389 /*
390 390 * flags to patch tsc_read routine.
391 391 */
392 392 #define X86_NO_TSC 0x0
393 393 #define X86_HAVE_TSCP 0x1
394 394 #define X86_TSC_MFENCE 0x2
395 395 #define X86_TSC_LFENCE 0x4
396 396
397 397 /*
398 398 * Intel Deep C-State invariant TSC in leaf 0x80000007.
399 399 */
400 400 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
401 401
402 402 /*
403 403 * Intel Deep C-state always-running local APIC timer
404 404 */
405 405 #define CPUID_CSTATE_ARAT (0x4)
406 406
407 407 /*
408 408 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
409 409 */
410 410 #define CPUID_EPB_SUPPORT (1 << 3)
411 411
412 412 /*
413 413 * Intel TSC deadline timer
414 414 */
415 415 #define CPUID_DEADLINE_TSC (1 << 24)
416 416
417 417 /*
418 418 * x86_type is a legacy concept; this is supplanted
419 419 * for most purposes by x86_featureset; modern CPUs
420 420 * should be X86_TYPE_OTHER
421 421 */
422 422 #define X86_TYPE_OTHER 0
423 423 #define X86_TYPE_486 1
424 424 #define X86_TYPE_P5 2
425 425 #define X86_TYPE_P6 3
426 426 #define X86_TYPE_CYRIX_486 4
427 427 #define X86_TYPE_CYRIX_6x86L 5
428 428 #define X86_TYPE_CYRIX_6x86 6
429 429 #define X86_TYPE_CYRIX_GXm 7
430 430 #define X86_TYPE_CYRIX_6x86MX 8
431 431 #define X86_TYPE_CYRIX_MediaGX 9
432 432 #define X86_TYPE_CYRIX_MII 10
433 433 #define X86_TYPE_VIA_CYRIX_III 11
434 434 #define X86_TYPE_P4 12
435 435
436 436 /*
437 437 * x86_vendor allows us to select between
438 438 * implementation features and helps guide
439 439 * the interpretation of the cpuid instruction.
440 440 */
441 441 #define X86_VENDOR_Intel 0
442 442 #define X86_VENDORSTR_Intel "GenuineIntel"
443 443
444 444 #define X86_VENDOR_IntelClone 1
445 445
446 446 #define X86_VENDOR_AMD 2
447 447 #define X86_VENDORSTR_AMD "AuthenticAMD"
448 448
449 449 #define X86_VENDOR_Cyrix 3
450 450 #define X86_VENDORSTR_CYRIX "CyrixInstead"
451 451
452 452 #define X86_VENDOR_UMC 4
453 453 #define X86_VENDORSTR_UMC "UMC UMC UMC "
454 454
455 455 #define X86_VENDOR_NexGen 5
456 456 #define X86_VENDORSTR_NexGen "NexGenDriven"
457 457
458 458 #define X86_VENDOR_Centaur 6
459 459 #define X86_VENDORSTR_Centaur "CentaurHauls"
460 460
461 461 #define X86_VENDOR_Rise 7
462 462 #define X86_VENDORSTR_Rise "RiseRiseRise"
463 463
464 464 #define X86_VENDOR_SiS 8
465 465 #define X86_VENDORSTR_SiS "SiS SiS SiS "
466 466
467 467 #define X86_VENDOR_TM 9
468 468 #define X86_VENDORSTR_TM "GenuineTMx86"
469 469
470 470 #define X86_VENDOR_NSC 10
471 471 #define X86_VENDORSTR_NSC "Geode by NSC"
472 472
473 473 /*
474 474 * Vendor string max len + \0
475 475 */
476 476 #define X86_VENDOR_STRLEN 13
477 477
478 478 /*
479 479 * Some vendor/family/model/stepping ranges are commonly grouped under
480 480 * a single identifying banner by the vendor. The following encode
481 481 * that "revision" in a uint32_t with the 8 most significant bits
482 482 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
483 483 * family, and the remaining 16 typically forming a bitmask of revisions
484 484 * within that family with more significant bits indicating "later" revisions.
485 485 */
486 486
487 487 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
488 488 #define _X86_CHIPREV_VENDOR_SHIFT 24
489 489 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
490 490 #define _X86_CHIPREV_FAMILY_SHIFT 16
491 491 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
492 492
493 493 #define _X86_CHIPREV_VENDOR(x) \
494 494 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
495 495 #define _X86_CHIPREV_FAMILY(x) \
496 496 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
497 497 #define _X86_CHIPREV_REV(x) \
498 498 ((x) & _X86_CHIPREV_REV_MASK)
499 499
500 500 /* True if x matches in vendor and family and if x matches the given rev mask */
501 501 #define X86_CHIPREV_MATCH(x, mask) \
502 502 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
503 503 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
504 504 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
505 505
506 506 /* True if x matches in vendor and family, and rev is at least minx */
507 507 #define X86_CHIPREV_ATLEAST(x, minx) \
508 508 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
509 509 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
510 510 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
511 511
512 512 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
513 513 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
514 514 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
515 515
516 516 /* True if x matches in vendor, and family is at least minx */
517 517 #define X86_CHIPFAM_ATLEAST(x, minx) \
518 518 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
519 519 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
520 520
521 521 /* Revision default */
522 522 #define X86_CHIPREV_UNKNOWN 0x0
523 523
524 524 /*
525 525 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
526 526 * sufficiently different that we will distinguish them; in all other
527 527 * case we will identify the major revision.
528 528 */
529 529 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
530 530 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
531 531 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
532 532 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
533 533 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
534 534 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
535 535 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
536 536
537 537 /*
538 538 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
539 539 */
540 540 #define X86_CHIPREV_AMD_10_REV_A \
541 541 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
542 542 #define X86_CHIPREV_AMD_10_REV_B \
543 543 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
544 544 #define X86_CHIPREV_AMD_10_REV_C2 \
545 545 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
546 546 #define X86_CHIPREV_AMD_10_REV_C3 \
547 547 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
548 548 #define X86_CHIPREV_AMD_10_REV_D0 \
549 549 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
550 550 #define X86_CHIPREV_AMD_10_REV_D1 \
551 551 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
552 552 #define X86_CHIPREV_AMD_10_REV_E \
553 553 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
554 554
555 555 /*
556 556 * Definitions for AMD Family 0x11.
557 557 */
558 558 #define X86_CHIPREV_AMD_11_REV_B \
559 559 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
560 560
561 561 /*
562 562 * Definitions for AMD Family 0x12.
563 563 */
564 564 #define X86_CHIPREV_AMD_12_REV_B \
565 565 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
566 566
567 567 /*
568 568 * Definitions for AMD Family 0x14.
569 569 */
570 570 #define X86_CHIPREV_AMD_14_REV_B \
571 571 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
572 572 #define X86_CHIPREV_AMD_14_REV_C \
573 573 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
574 574
575 575 /*
576 576 * Definitions for AMD Family 0x15
577 577 */
578 578 #define X86_CHIPREV_AMD_15OR_REV_B2 \
579 579 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
580 580
581 581 #define X86_CHIPREV_AMD_15TN_REV_A1 \
582 582 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
583 583
584 584 /*
585 585 * Various socket/package types, extended as the need to distinguish
586 586 * a new type arises. The top 8 byte identfies the vendor and the
587 587 * remaining 24 bits describe 24 socket types.
588 588 */
589 589
590 590 #define _X86_SOCKET_VENDOR_SHIFT 24
591 591 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
592 592 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
593 593 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
594 594
595 595 #define _X86_SOCKET_MKVAL(vendor, bitval) \
596 596 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
597 597
598 598 #define X86_SOCKET_MATCH(s, mask) \
599 599 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
600 600 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
601 601
602 602 #define X86_SOCKET_UNKNOWN 0x0
603 603 /*
604 604 * AMD socket types
605 605 */
606 606 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
607 607 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
608 608 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
609 609 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
610 610 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
611 611 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
612 612 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
613 613 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
614 614 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
615 615 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
616 616 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
617 617 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
618 618 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
619 619 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
620 620 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
621 621 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
622 622 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
623 623 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
624 624 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
625 625 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
626 626 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
627 627 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
628 628
629 629 /*
630 630 * xgetbv/xsetbv support
631 631 */
632 632
633 633 #define XFEATURE_ENABLED_MASK 0x0
634 634 /*
635 635 * XFEATURE_ENABLED_MASK values (eax)
636 636 */
637 637 #define XFEATURE_LEGACY_FP 0x1
638 638 #define XFEATURE_SSE 0x2
639 639 #define XFEATURE_AVX 0x4
640 640 #define XFEATURE_MAX XFEATURE_AVX
641 641 #define XFEATURE_FP_ALL \
642 642 (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX)
643 643
644 644 #if !defined(_ASM)
645 645
646 646 #if defined(_KERNEL) || defined(_KMEMUSER)
647 647
648 648 #define NUM_X86_FEATURES 49
649 649 extern uchar_t x86_featureset[];
650 650
651 651 extern void free_x86_featureset(void *featureset);
652 652 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
653 653 extern void add_x86_feature(void *featureset, uint_t feature);
654 654 extern void remove_x86_feature(void *featureset, uint_t feature);
655 655 extern boolean_t compare_x86_featureset(void *setA, void *setB);
656 656 extern void print_x86_featureset(void *featureset);
657 657
658 658
659 659 extern uint_t x86_type;
660 660 extern uint_t x86_vendor;
661 661 extern uint_t x86_clflush_size;
662 662
663 663 extern uint_t pentiumpro_bug4046376;
664 664
665 665 extern const char CyrixInstead[];
666 666
667 667 #endif
668 668
669 669 #if defined(_KERNEL)
670 670
671 671 /*
672 672 * This structure is used to pass arguments and get return values back
673 673 * from the CPUID instruction in __cpuid_insn() routine.
674 674 */
675 675 struct cpuid_regs {
676 676 uint32_t cp_eax;
677 677 uint32_t cp_ebx;
678 678 uint32_t cp_ecx;
679 679 uint32_t cp_edx;
680 680 };
681 681
682 682 /*
683 683 * Utility functions to get/set extended control registers (XCR)
684 684 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
685 685 */
686 686 extern uint64_t get_xcr(uint_t);
687 687 extern void set_xcr(uint_t, uint64_t);
688 688
689 689 extern uint64_t rdmsr(uint_t);
690 690 extern void wrmsr(uint_t, const uint64_t);
691 691 extern uint64_t xrdmsr(uint_t);
692 692 extern void xwrmsr(uint_t, const uint64_t);
693 693 extern int checked_rdmsr(uint_t, uint64_t *);
694 694 extern int checked_wrmsr(uint_t, uint64_t);
695 695
696 696 extern void invalidate_cache(void);
697 697 extern ulong_t getcr4(void);
698 698 extern void setcr4(ulong_t);
699 699
700 700 extern void mtrr_sync(void);
701 701
702 702 extern void cpu_fast_syscall_enable(void *);
703 703 extern void cpu_fast_syscall_disable(void *);
704 704
705 705 struct cpu;
706 706
707 707 extern int cpuid_checkpass(struct cpu *, int);
708 708 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
709 709 extern uint32_t __cpuid_insn(struct cpuid_regs *);
710 710 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
711 711 extern int cpuid_getidstr(struct cpu *, char *, size_t);
712 712 extern const char *cpuid_getvendorstr(struct cpu *);
713 713 extern uint_t cpuid_getvendor(struct cpu *);
714 714 extern uint_t cpuid_getfamily(struct cpu *);
715 715 extern uint_t cpuid_getmodel(struct cpu *);
716 716 extern uint_t cpuid_getstep(struct cpu *);
717 717 extern uint_t cpuid_getsig(struct cpu *);
718 718 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
719 719 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
720 720 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
721 721 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
722 722 extern int cpuid_get_chipid(struct cpu *);
723 723 extern id_t cpuid_get_coreid(struct cpu *);
724 724 extern int cpuid_get_pkgcoreid(struct cpu *);
725 725 extern int cpuid_get_clogid(struct cpu *);
726 726 extern int cpuid_get_cacheid(struct cpu *);
727 727 extern uint32_t cpuid_get_apicid(struct cpu *);
728 728 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
729 729 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
730 730 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
731 731 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
732 732 extern int cpuid_is_cmt(struct cpu *);
733 733 extern int cpuid_syscall32_insn(struct cpu *);
734 734 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
735 735
736 736 extern uint32_t cpuid_getchiprev(struct cpu *);
737 737 extern const char *cpuid_getchiprevstr(struct cpu *);
738 738 extern uint32_t cpuid_getsockettype(struct cpu *);
739 739 extern const char *cpuid_getsocketstr(struct cpu *);
740 740
741 741 extern int cpuid_have_cr8access(struct cpu *);
742 742
743 743 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
744 744
745 745 struct cpuid_info;
746 746
747 747 extern void setx86isalist(void);
748 748 extern void cpuid_alloc_space(struct cpu *);
749 749 extern void cpuid_free_space(struct cpu *);
750 750 extern void cpuid_pass1(struct cpu *, uchar_t *);
751 751 extern void cpuid_pass2(struct cpu *);
752 752 extern void cpuid_pass3(struct cpu *);
753 753 extern void cpuid_pass4(struct cpu *, uint_t *);
754 754 extern void cpuid_set_cpu_properties(void *, processorid_t,
755 755 struct cpuid_info *);
756 756
757 757 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
758 758 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
759 759
760 760 #if !defined(__xpv)
761 761 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
762 762 extern void cpuid_mwait_free(struct cpu *);
763 763 extern int cpuid_deep_cstates_supported(void);
764 764 extern int cpuid_arat_supported(void);
765 765 extern int cpuid_iepb_supported(struct cpu *);
766 766 extern int cpuid_deadline_tsc_supported(void);
767 767 extern void vmware_port(int, uint32_t *);
768 768 #endif
769 769
770 770 struct cpu_ucode_info;
771 771
772 772 extern void ucode_alloc_space(struct cpu *);
773 773 extern void ucode_free_space(struct cpu *);
774 774 extern void ucode_check(struct cpu *);
775 775 extern void ucode_cleanup();
776 776
777 777 #if !defined(__xpv)
778 778 extern char _tsc_mfence_start;
779 779 extern char _tsc_mfence_end;
780 780 extern char _tscp_start;
781 781 extern char _tscp_end;
782 782 extern char _no_rdtsc_start;
783 783 extern char _no_rdtsc_end;
784 784 extern char _tsc_lfence_start;
785 785 extern char _tsc_lfence_end;
786 786 #endif
787 787
788 788 #if !defined(__xpv)
789 789 extern char bcopy_patch_start;
790 790 extern char bcopy_patch_end;
791 791 extern char bcopy_ck_size;
792 792 #endif
793 793
794 794 extern void post_startup_cpu_fixups(void);
795 795
796 796 extern uint_t workaround_errata(struct cpu *);
797 797
798 798 #if defined(OPTERON_ERRATUM_93)
799 799 extern int opteron_erratum_93;
800 800 #endif
801 801
802 802 #if defined(OPTERON_ERRATUM_91)
803 803 extern int opteron_erratum_91;
804 804 #endif
805 805
806 806 #if defined(OPTERON_ERRATUM_100)
807 807 extern int opteron_erratum_100;
808 808 #endif
809 809
810 810 #if defined(OPTERON_ERRATUM_121)
811 811 extern int opteron_erratum_121;
812 812 #endif
813 813
814 814 #if defined(OPTERON_WORKAROUND_6323525)
815 815 extern int opteron_workaround_6323525;
816 816 extern void patch_workaround_6323525(void);
817 817 #endif
818 818
819 819 #if !defined(__xpv)
820 820 extern void determine_platform(void);
821 821 #endif
822 822 extern int get_hwenv(void);
823 823 extern int is_controldom(void);
824 824
825 825 extern void xsave_setup_msr(struct cpu *);
826 826
827 827 /*
828 828 * Hypervisor signatures
829 829 */
830 830 #define HVSIG_XEN_HVM "XenVMMXenVMM"
831 831 #define HVSIG_VMWARE "VMwareVMware"
832 832 #define HVSIG_KVM "KVMKVMKVM"
833 833 #define HVSIG_MICROSOFT "Microsoft Hv"
834 834
835 835 /*
836 836 * Defined hardware environments
837 837 */
838 838 #define HW_NATIVE (1 << 0) /* Running on bare metal */
839 839 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
840 840
841 841 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
842 842 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
843 843 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
844 844 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
845 845
846 846 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
847 847
848 848 #endif /* _KERNEL */
849 849
850 850 #endif /* !_ASM */
851 851
852 852 /*
853 853 * VMware hypervisor related defines
854 854 */
855 855 #define VMWARE_HVMAGIC 0x564d5868
856 856 #define VMWARE_HVPORT 0x5658
857 857 #define VMWARE_HVCMD_GETVERSION 0x0a
858 858 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
859 859
860 860 #ifdef __cplusplus
861 861 }
862 862 #endif
863 863
864 864 #endif /* _SYS_X86_ARCHEXT_H */
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