Print this page
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/intel/sys/machlock.h
+++ new/usr/src/uts/intel/sys/machlock.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 * Copyright 2016 Joyent, Inc.
25 25 */
26 26
27 27 #ifndef _SYS_MACHLOCK_H
28 28 #define _SYS_MACHLOCK_H
29 29
30 30 #ifndef _ASM
31 31 #include <sys/types.h>
32 32 #include <sys/time.h>
33 33 #endif /* _ASM */
34 34
35 35 #ifdef __cplusplus
36 36 extern "C" {
37 37 #endif
38 38
39 39 #ifndef _ASM
40 40
41 41 #ifdef _KERNEL
42 42
43 43 extern void lock_set(lock_t *lp);
44 44 extern int lock_try(lock_t *lp);
45 45 extern int lock_spin_try(lock_t *lp);
46 46 extern int ulock_try(lock_t *lp);
47 47 extern void lock_clear(lock_t *lp);
48 48 extern void ulock_clear(lock_t *lp);
49 49 extern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil);
50 50 extern void lock_clear_splx(lock_t *lp, int s);
51 51
52 52 #endif /* _KERNEL */
53 53
54 54 #define LOCK_HELD_VALUE 0xff
55 55 #define LOCK_INIT_CLEAR(lp) (*(lp) = 0)
56 56 #define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE)
57 57 #define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0)
58 58
59 59 typedef lock_t disp_lock_t; /* dispatcher lock type */
60 60
61 61 /*
62 62 * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or
63 63 * an adaptive mutex, depending on what interrupt levels use it.
64 64 */
65 65 #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL))
66 66
67 67 /*
68 68 * Macro to control loops which spin on a lock and then check state
69 69 * periodically. Its passed an integer, and returns a boolean value
70 70 * that if true indicates its a good time to get the scheduler lock and
71 71 * check the state of the current owner of the lock.
72 72 */
73 73 #define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0)
74 74
75 75 /*
76 76 * Externs for CLOCK_LOCK and clock resolution
77 77 */
78 78 extern volatile uint32_t hres_lock;
79 79 extern hrtime_t hrtime_base;
80 80 extern int clock_res;
81 81
82 82 #endif /* _ASM */
83 83
84 84 /*
85 85 * The definitions of the symbolic interrupt levels:
86 86 *
87 87 * CLOCK_LEVEL => The level at which one must be to block the clock.
88 88 *
89 89 * LOCK_LEVEL => The highest level at which one may block (and thus the
90 90 * highest level at which one may acquire adaptive locks)
91 91 * Also the highest level at which one may be preempted.
92 92 *
93 93 * DISP_LEVEL => The level at which one must be to perform dispatcher
94 94 * operations.
95 95 *
96 96 * The constraints on the platform:
97 97 *
98 98 * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL
99 99 * - LOCK_LEVEL must be less than DISP_LEVEL
100 100 * - DISP_LEVEL should be as close to LOCK_LEVEL as possible
101 101 *
102 102 * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal;
103 103 * changing this relationship is probably possible but not advised.
104 104 *
105 105 */
106 106
107 107 #define PIL_MAX 15
108 108
109 109 #define CLOCK_LEVEL 10
110 110 #define LOCK_LEVEL 10
111 111 #define DISP_LEVEL (LOCK_LEVEL + 1)
112 112
113 113 #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL)
114 114
115 115 /*
116 116 * The following mask is for the cpu_intr_actv bits corresponding to
117 117 * high-level PILs. It should equal:
118 118 * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1)
119 119 */
120 120 #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xF800
121 121
122 122 /*
123 123 * The semaphore code depends on being able to represent a lock plus
124 124 * owner in a single 32-bit word. (Mutexes used to have a similar
125 125 * dependency, but no longer.) Thus the owner must contain at most
126 126 * 24 significant bits. At present only threads and semaphores
127 127 * must be aware of this vile constraint. Different ISAs may handle this
128 128 * differently depending on their capabilities (e.g. compare-and-swap)
129 129 * and limitations (e.g. constraints on alignment and/or KERNELBASE).
130 130 */
131 131 #define PTR24_LSB 5 /* lower bits all zero */
132 132 #define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */
133 133 #define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */
134 134 #define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */
135 135
136 136 #ifdef __cplusplus
137 137 }
138 138 #endif
139 139
140 140 #endif /* _SYS_MACHLOCK_H */
|
↓ open down ↓ |
140 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX