Print this page
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/i86pc/os/mp_startup.c
+++ new/usr/src/uts/i86pc/os/mp_startup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright 2016 Joyent, Inc.
31 31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 32 */
33 33
34 34 #include <sys/types.h>
35 35 #include <sys/thread.h>
36 36 #include <sys/cpuvar.h>
37 37 #include <sys/cpu.h>
38 38 #include <sys/t_lock.h>
39 39 #include <sys/param.h>
40 40 #include <sys/proc.h>
41 41 #include <sys/disp.h>
42 42 #include <sys/class.h>
43 43 #include <sys/cmn_err.h>
44 44 #include <sys/debug.h>
45 45 #include <sys/note.h>
46 46 #include <sys/asm_linkage.h>
47 47 #include <sys/x_call.h>
48 48 #include <sys/systm.h>
49 49 #include <sys/var.h>
50 50 #include <sys/vtrace.h>
51 51 #include <vm/hat.h>
52 52 #include <vm/as.h>
53 53 #include <vm/seg_kmem.h>
54 54 #include <vm/seg_kp.h>
55 55 #include <sys/segments.h>
56 56 #include <sys/kmem.h>
57 57 #include <sys/stack.h>
58 58 #include <sys/smp_impldefs.h>
59 59 #include <sys/x86_archext.h>
60 60 #include <sys/machsystm.h>
61 61 #include <sys/traptrace.h>
62 62 #include <sys/clock.h>
63 63 #include <sys/cpc_impl.h>
64 64 #include <sys/pg.h>
65 65 #include <sys/cmt.h>
66 66 #include <sys/dtrace.h>
67 67 #include <sys/archsystm.h>
68 68 #include <sys/fp.h>
69 69 #include <sys/reboot.h>
70 70 #include <sys/kdi_machimpl.h>
71 71 #include <vm/hat_i86.h>
72 72 #include <vm/vm_dep.h>
73 73 #include <sys/memnode.h>
74 74 #include <sys/pci_cfgspace.h>
75 75 #include <sys/mach_mmu.h>
76 76 #include <sys/sysmacros.h>
77 77 #if defined(__xpv)
78 78 #include <sys/hypervisor.h>
79 79 #endif
80 80 #include <sys/cpu_module.h>
81 81 #include <sys/ontrap.h>
82 82
83 83 struct cpu cpus[1]; /* CPU data */
84 84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
85 85 struct cpu *cpu_free_list; /* list for released CPUs */
86 86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
87 87
88 88 #define cpu_next_free cpu_prev
89 89
90 90 /*
91 91 * Useful for disabling MP bring-up on a MP capable system.
92 92 */
93 93 int use_mp = 1;
94 94
95 95 /*
96 96 * to be set by a PSM to indicate what cpus
97 97 * are sitting around on the system.
98 98 */
99 99 cpuset_t mp_cpus;
100 100
101 101 /*
102 102 * This variable is used by the hat layer to decide whether or not
103 103 * critical sections are needed to prevent race conditions. For sun4m,
104 104 * this variable is set once enough MP initialization has been done in
105 105 * order to allow cross calls.
106 106 */
107 107 int flushes_require_xcalls;
108 108
109 109 cpuset_t cpu_ready_set; /* initialized in startup() */
110 110
111 111 static void mp_startup_boot(void);
112 112 static void mp_startup_hotplug(void);
113 113
114 114 static void cpu_sep_enable(void);
115 115 static void cpu_sep_disable(void);
116 116 static void cpu_asysc_enable(void);
117 117 static void cpu_asysc_disable(void);
118 118
119 119 /*
120 120 * Init CPU info - get CPU type info for processor_info system call.
121 121 */
122 122 void
123 123 init_cpu_info(struct cpu *cp)
124 124 {
125 125 processor_info_t *pi = &cp->cpu_type_info;
126 126
127 127 /*
128 128 * Get clock-frequency property for the CPU.
129 129 */
130 130 pi->pi_clock = cpu_freq;
131 131
132 132 /*
133 133 * Current frequency in Hz.
134 134 */
135 135 cp->cpu_curr_clock = cpu_freq_hz;
136 136
137 137 /*
138 138 * Supported frequencies.
139 139 */
140 140 if (cp->cpu_supp_freqs == NULL) {
141 141 cpu_set_supp_freqs(cp, NULL);
142 142 }
143 143
144 144 (void) strcpy(pi->pi_processor_type, "i386");
145 145 if (fpu_exists)
146 146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
147 147
148 148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
149 149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150 150
151 151 /*
152 152 * If called for the BSP, cp is equal to current CPU.
153 153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 156 * has been invoked on target CPU.
157 157 */
158 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
|
↓ open down ↓ |
158 lines elided |
↑ open up ↑ |
159 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
160 160 }
161 161
162 162 /*
163 163 * Configure syscall support on this CPU.
164 164 */
165 165 /*ARGSUSED*/
166 166 void
167 167 init_cpu_syscall(struct cpu *cp)
168 168 {
169 - uint64_t flags;
170 -
171 169 kpreempt_disable();
172 170
173 171 #if defined(__amd64)
174 172 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
175 173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
176 174 uint64_t flags;
177 175
178 176 #if !defined(__lint)
179 177 /*
180 178 * The syscall instruction imposes a certain ordering on
181 179 * segment selectors, so we double-check that ordering
182 180 * here.
183 181 */
184 182 ASSERT(KDS_SEL == KCS_SEL + 8);
185 183 ASSERT(UDS_SEL == U32CS_SEL + 8);
186 184 ASSERT(UCS_SEL == U32CS_SEL + 16);
187 185 #endif
188 186 /*
189 187 * Turn syscall/sysret extensions on.
190 188 */
191 189 cpu_asysc_enable();
192 190
193 191 /*
194 192 * Program the magic registers ..
195 193 */
196 194 wrmsr(MSR_AMD_STAR,
197 195 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
198 196 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
199 197 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
200 198
201 199 /*
202 200 * This list of flags is masked off the incoming
203 201 * %rfl when we enter the kernel.
204 202 */
205 203 flags = PS_IE | PS_T;
206 204 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
207 205 flags |= PS_ACHK;
208 206 wrmsr(MSR_AMD_SFMASK, flags);
209 207 }
210 208 #endif
211 209
212 210 /*
213 211 * On 32-bit kernels, we use sysenter/sysexit because it's too
214 212 * hard to use syscall/sysret, and it is more portable anyway.
215 213 *
216 214 * On 64-bit kernels on Nocona machines, the 32-bit syscall
217 215 * variant isn't available to 32-bit applications, but sysenter is.
218 216 */
219 217 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
220 218 is_x86_feature(x86_featureset, X86FSET_SEP)) {
221 219
222 220 #if !defined(__lint)
223 221 /*
224 222 * The sysenter instruction imposes a certain ordering on
225 223 * segment selectors, so we double-check that ordering
226 224 * here. See "sysenter" in Intel document 245471-012, "IA-32
227 225 * Intel Architecture Software Developer's Manual Volume 2:
228 226 * Instruction Set Reference"
229 227 */
230 228 ASSERT(KDS_SEL == KCS_SEL + 8);
231 229
232 230 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
233 231 ASSERT32(UDS_SEL == UCS_SEL + 8);
234 232
235 233 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
236 234 ASSERT64(UDS_SEL == U32CS_SEL + 8);
237 235 #endif
238 236
239 237 cpu_sep_enable();
240 238
241 239 /*
242 240 * resume() sets this value to the base of the threads stack
243 241 * via a context handler.
244 242 */
245 243 wrmsr(MSR_INTC_SEP_ESP, 0);
246 244 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
247 245 }
248 246
249 247 kpreempt_enable();
250 248 }
251 249
252 250 #if !defined(__xpv)
253 251 /*
254 252 * Configure per-cpu ID GDT
255 253 */
256 254 static void
257 255 init_cpu_id_gdt(struct cpu *cp)
258 256 {
259 257 /* Write cpu_id into limit field of GDT for usermode retrieval */
260 258 #if defined(__amd64)
261 259 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
262 260 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
263 261 #elif defined(__i386)
264 262 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
265 263 SEL_UPL, SDP_BYTES, SDP_OP32);
266 264 #endif
267 265 }
268 266 #endif /* !defined(__xpv) */
269 267
270 268 /*
271 269 * Multiprocessor initialization.
272 270 *
273 271 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
274 272 * startup and idle threads for the specified CPU.
275 273 * Parameter boot is true for boot time operations and is false for CPU
276 274 * DR operations.
277 275 */
278 276 static struct cpu *
279 277 mp_cpu_configure_common(int cpun, boolean_t boot)
280 278 {
281 279 struct cpu *cp;
282 280 kthread_id_t tp;
283 281 caddr_t sp;
284 282 proc_t *procp;
285 283 #if !defined(__xpv)
286 284 extern int idle_cpu_prefer_mwait;
287 285 extern void cpu_idle_mwait();
288 286 #endif
289 287 extern void idle();
290 288 extern void cpu_idle();
291 289
292 290 #ifdef TRAPTRACE
293 291 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
294 292 #endif
295 293
296 294 ASSERT(MUTEX_HELD(&cpu_lock));
297 295 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
298 296
299 297 if (cpu_free_list == NULL) {
300 298 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
301 299 } else {
302 300 cp = cpu_free_list;
303 301 cpu_free_list = cp->cpu_next_free;
304 302 }
305 303
306 304 cp->cpu_m.mcpu_istamp = cpun << 16;
307 305
308 306 /* Create per CPU specific threads in the process p0. */
309 307 procp = &p0;
310 308
311 309 /*
312 310 * Initialize the dispatcher first.
313 311 */
314 312 disp_cpu_init(cp);
315 313
316 314 cpu_vm_data_init(cp);
317 315
318 316 /*
319 317 * Allocate and initialize the startup thread for this CPU.
320 318 * Interrupt and process switch stacks get allocated later
321 319 * when the CPU starts running.
322 320 */
323 321 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
324 322 TS_STOPPED, maxclsyspri);
325 323
326 324 /*
327 325 * Set state to TS_ONPROC since this thread will start running
328 326 * as soon as the CPU comes online.
329 327 *
330 328 * All the other fields of the thread structure are setup by
331 329 * thread_create().
332 330 */
333 331 THREAD_ONPROC(tp, cp);
334 332 tp->t_preempt = 1;
335 333 tp->t_bound_cpu = cp;
336 334 tp->t_affinitycnt = 1;
337 335 tp->t_cpu = cp;
338 336 tp->t_disp_queue = cp->cpu_disp;
339 337
340 338 /*
341 339 * Setup thread to start in mp_startup_common.
342 340 */
343 341 sp = tp->t_stk;
344 342 tp->t_sp = (uintptr_t)(sp - MINFRAME);
345 343 #if defined(__amd64)
346 344 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
347 345 #endif
348 346 /*
349 347 * Setup thread start entry point for boot or hotplug.
350 348 */
351 349 if (boot) {
352 350 tp->t_pc = (uintptr_t)mp_startup_boot;
353 351 } else {
354 352 tp->t_pc = (uintptr_t)mp_startup_hotplug;
355 353 }
356 354
357 355 cp->cpu_id = cpun;
358 356 cp->cpu_self = cp;
359 357 cp->cpu_thread = tp;
360 358 cp->cpu_lwp = NULL;
361 359 cp->cpu_dispthread = tp;
362 360 cp->cpu_dispatch_pri = DISP_PRIO(tp);
363 361
364 362 /*
365 363 * cpu_base_spl must be set explicitly here to prevent any blocking
366 364 * operations in mp_startup_common from causing the spl of the cpu
367 365 * to drop to 0 (allowing device interrupts before we're ready) in
368 366 * resume().
369 367 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
370 368 * As an extra bit of security on DEBUG kernels, this is enforced with
371 369 * an assertion in mp_startup_common() -- before cpu_base_spl is set
372 370 * to its proper value.
373 371 */
374 372 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
375 373
376 374 /*
377 375 * Now, initialize per-CPU idle thread for this CPU.
378 376 */
379 377 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
380 378
381 379 cp->cpu_idle_thread = tp;
382 380
383 381 tp->t_preempt = 1;
384 382 tp->t_bound_cpu = cp;
385 383 tp->t_affinitycnt = 1;
386 384 tp->t_cpu = cp;
387 385 tp->t_disp_queue = cp->cpu_disp;
388 386
389 387 /*
390 388 * Bootstrap the CPU's PG data
391 389 */
392 390 pg_cpu_bootstrap(cp);
393 391
394 392 /*
395 393 * Perform CPC initialization on the new CPU.
396 394 */
397 395 kcpc_hw_init(cp);
398 396
399 397 /*
400 398 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
401 399 * for each CPU.
402 400 */
403 401 setup_vaddr_for_ppcopy(cp);
404 402
405 403 /*
406 404 * Allocate page for new GDT and initialize from current GDT.
407 405 */
408 406 #if !defined(__lint)
409 407 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
410 408 #endif
411 409 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
412 410 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
413 411
414 412 #if defined(__i386)
415 413 /*
416 414 * setup kernel %gs.
417 415 */
418 416 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
419 417 SEL_KPL, 0, 1);
420 418 #endif
421 419
422 420 /*
423 421 * If we have more than one node, each cpu gets a copy of IDT
424 422 * local to its node. If this is a Pentium box, we use cpu 0's
425 423 * IDT. cpu 0's IDT has been made read-only to workaround the
426 424 * cmpxchgl register bug
427 425 */
428 426 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
429 427 #if !defined(__lint)
430 428 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
431 429 #endif
432 430 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
433 431 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
434 432 } else {
435 433 cp->cpu_idt = CPU->cpu_idt;
436 434 }
437 435
438 436 /*
439 437 * alloc space for cpuid info
440 438 */
441 439 cpuid_alloc_space(cp);
442 440 #if !defined(__xpv)
443 441 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
444 442 idle_cpu_prefer_mwait) {
445 443 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
446 444 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
447 445 } else
448 446 #endif
449 447 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
450 448
451 449 init_cpu_info(cp);
452 450
453 451 #if !defined(__xpv)
454 452 init_cpu_id_gdt(cp);
455 453 #endif
456 454
457 455 /*
458 456 * alloc space for ucode_info
459 457 */
460 458 ucode_alloc_space(cp);
461 459 xc_init_cpu(cp);
462 460 hat_cpu_online(cp);
463 461
464 462 #ifdef TRAPTRACE
465 463 /*
466 464 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
467 465 */
468 466 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
469 467 ttc->ttc_next = ttc->ttc_first;
470 468 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
471 469 #endif
472 470
473 471 /*
474 472 * Record that we have another CPU.
475 473 */
476 474 /*
477 475 * Initialize the interrupt threads for this CPU
478 476 */
479 477 cpu_intr_alloc(cp, NINTR_THREADS);
480 478
481 479 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
482 480 cpu_set_state(cp);
483 481
484 482 /*
485 483 * Add CPU to list of available CPUs. It'll be on the active list
486 484 * after mp_startup_common().
487 485 */
488 486 cpu_add_unit(cp);
489 487
490 488 return (cp);
491 489 }
492 490
493 491 /*
494 492 * Undo what was done in mp_cpu_configure_common
495 493 */
496 494 static void
497 495 mp_cpu_unconfigure_common(struct cpu *cp, int error)
498 496 {
499 497 ASSERT(MUTEX_HELD(&cpu_lock));
500 498
501 499 /*
502 500 * Remove the CPU from the list of available CPUs.
503 501 */
504 502 cpu_del_unit(cp->cpu_id);
505 503
506 504 if (error == ETIMEDOUT) {
507 505 /*
508 506 * The cpu was started, but never *seemed* to run any
509 507 * code in the kernel; it's probably off spinning in its
510 508 * own private world, though with potential references to
511 509 * our kmem-allocated IDTs and GDTs (for example).
512 510 *
513 511 * Worse still, it may actually wake up some time later,
514 512 * so rather than guess what it might or might not do, we
515 513 * leave the fundamental data structures intact.
516 514 */
517 515 cp->cpu_flags = 0;
518 516 return;
519 517 }
520 518
521 519 /*
522 520 * At this point, the only threads bound to this CPU should
523 521 * special per-cpu threads: it's idle thread, it's pause threads,
524 522 * and it's interrupt threads. Clean these up.
525 523 */
526 524 cpu_destroy_bound_threads(cp);
527 525 cp->cpu_idle_thread = NULL;
528 526
529 527 /*
530 528 * Free the interrupt stack.
531 529 */
532 530 segkp_release(segkp,
533 531 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
534 532 cp->cpu_intr_stack = NULL;
535 533
536 534 #ifdef TRAPTRACE
537 535 /*
538 536 * Discard the trap trace buffer
539 537 */
540 538 {
541 539 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
542 540
543 541 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
544 542 ttc->ttc_first = NULL;
545 543 }
546 544 #endif
547 545
548 546 hat_cpu_offline(cp);
549 547
550 548 ucode_free_space(cp);
551 549
552 550 /* Free CPU ID string and brand string. */
553 551 if (cp->cpu_idstr) {
554 552 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
555 553 cp->cpu_idstr = NULL;
556 554 }
557 555 if (cp->cpu_brandstr) {
558 556 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
559 557 cp->cpu_brandstr = NULL;
560 558 }
561 559
562 560 #if !defined(__xpv)
563 561 if (cp->cpu_m.mcpu_mwait != NULL) {
564 562 cpuid_mwait_free(cp);
565 563 cp->cpu_m.mcpu_mwait = NULL;
566 564 }
567 565 #endif
568 566 cpuid_free_space(cp);
569 567
570 568 if (cp->cpu_idt != CPU->cpu_idt)
571 569 kmem_free(cp->cpu_idt, PAGESIZE);
572 570 cp->cpu_idt = NULL;
573 571
574 572 kmem_free(cp->cpu_gdt, PAGESIZE);
575 573 cp->cpu_gdt = NULL;
576 574
577 575 if (cp->cpu_supp_freqs != NULL) {
578 576 size_t len = strlen(cp->cpu_supp_freqs) + 1;
579 577 kmem_free(cp->cpu_supp_freqs, len);
580 578 cp->cpu_supp_freqs = NULL;
581 579 }
582 580
583 581 teardown_vaddr_for_ppcopy(cp);
584 582
585 583 kcpc_hw_fini(cp);
586 584
587 585 cp->cpu_dispthread = NULL;
588 586 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
589 587
590 588 cpu_vm_data_destroy(cp);
591 589
592 590 xc_fini_cpu(cp);
593 591 disp_cpu_fini(cp);
594 592
595 593 ASSERT(cp != CPU0);
596 594 bzero(cp, sizeof (*cp));
597 595 cp->cpu_next_free = cpu_free_list;
598 596 cpu_free_list = cp;
599 597 }
600 598
601 599 /*
602 600 * Apply workarounds for known errata, and warn about those that are absent.
603 601 *
604 602 * System vendors occasionally create configurations which contain different
605 603 * revisions of the CPUs that are almost but not exactly the same. At the
606 604 * time of writing, this meant that their clock rates were the same, their
607 605 * feature sets were the same, but the required workaround were -not-
608 606 * necessarily the same. So, this routine is invoked on -every- CPU soon
609 607 * after starting to make sure that the resulting system contains the most
610 608 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
611 609 * system.
612 610 *
613 611 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
614 612 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
615 613 * prior to acknowledging their readiness to the master, so this routine will
616 614 * never be executed by multiple CPUs in parallel, thus making updates to
617 615 * global data safe.
618 616 *
619 617 * These workarounds are based on Rev 3.57 of the Revision Guide for
620 618 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
621 619 */
622 620
623 621 #if defined(OPTERON_ERRATUM_88)
624 622 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
625 623 #endif
626 624
627 625 #if defined(OPTERON_ERRATUM_91)
628 626 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
629 627 #endif
630 628
631 629 #if defined(OPTERON_ERRATUM_93)
632 630 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
633 631 #endif
634 632
635 633 #if defined(OPTERON_ERRATUM_95)
636 634 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
637 635 #endif
638 636
639 637 #if defined(OPTERON_ERRATUM_100)
640 638 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
641 639 #endif
642 640
643 641 #if defined(OPTERON_ERRATUM_108)
644 642 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
645 643 #endif
646 644
647 645 #if defined(OPTERON_ERRATUM_109)
648 646 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
649 647 #endif
650 648
651 649 #if defined(OPTERON_ERRATUM_121)
652 650 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
653 651 #endif
654 652
655 653 #if defined(OPTERON_ERRATUM_122)
656 654 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
657 655 #endif
658 656
659 657 #if defined(OPTERON_ERRATUM_123)
660 658 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
661 659 #endif
662 660
663 661 #if defined(OPTERON_ERRATUM_131)
664 662 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
665 663 #endif
666 664
667 665 #if defined(OPTERON_WORKAROUND_6336786)
668 666 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
669 667 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
670 668 #endif
671 669
672 670 #if defined(OPTERON_WORKAROUND_6323525)
673 671 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
674 672 #endif
675 673
676 674 #if defined(OPTERON_ERRATUM_298)
677 675 int opteron_erratum_298;
678 676 #endif
679 677
680 678 #if defined(OPTERON_ERRATUM_721)
681 679 int opteron_erratum_721;
682 680 #endif
683 681
684 682 static void
685 683 workaround_warning(cpu_t *cp, uint_t erratum)
686 684 {
687 685 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
688 686 cp->cpu_id, erratum);
689 687 }
690 688
691 689 static void
692 690 workaround_applied(uint_t erratum)
693 691 {
694 692 if (erratum > 1000000)
695 693 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
696 694 erratum);
697 695 else
698 696 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
699 697 erratum);
700 698 }
701 699
702 700 static void
703 701 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
704 702 {
705 703 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
706 704 cp->cpu_id, rw, msr, error);
707 705 }
708 706
709 707 /*
710 708 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
711 709 * system.
712 710 */
713 711 static uint_t
714 712 opteron_get_nnodes(void)
715 713 {
716 714 static uint_t nnodes = 0;
717 715
718 716 if (nnodes == 0) {
719 717 #ifdef DEBUG
720 718 uint_t family;
721 719
722 720 /*
723 721 * This routine uses a PCI config space based mechanism
724 722 * for retrieving the number of nodes in the system.
725 723 * Device 24, function 0, offset 0x60 as used here is not
726 724 * AMD processor architectural, and may not work on processor
727 725 * families other than those listed below.
728 726 *
729 727 * Callers of this routine must ensure that we're running on
730 728 * a processor which supports this mechanism.
731 729 * The assertion below is meant to catch calls on unsupported
732 730 * processors.
733 731 */
734 732 family = cpuid_getfamily(CPU);
735 733 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
736 734 #endif /* DEBUG */
737 735
738 736 /*
739 737 * Obtain the number of nodes in the system from
740 738 * bits [6:4] of the Node ID register on node 0.
741 739 *
742 740 * The actual node count is NodeID[6:4] + 1
743 741 *
744 742 * The Node ID register is accessed via function 0,
745 743 * offset 0x60. Node 0 is device 24.
746 744 */
747 745 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
748 746 }
749 747 return (nnodes);
750 748 }
751 749
752 750 uint_t
753 751 do_erratum_298(struct cpu *cpu)
754 752 {
755 753 static int osvwrc = -3;
756 754 extern int osvw_opteron_erratum(cpu_t *, uint_t);
757 755
758 756 /*
759 757 * L2 Eviction May Occur During Processor Operation To Set
760 758 * Accessed or Dirty Bit.
761 759 */
762 760 if (osvwrc == -3) {
763 761 osvwrc = osvw_opteron_erratum(cpu, 298);
764 762 } else {
765 763 /* osvw return codes should be consistent for all cpus */
766 764 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
767 765 }
768 766
769 767 switch (osvwrc) {
770 768 case 0: /* erratum is not present: do nothing */
771 769 break;
772 770 case 1: /* erratum is present: BIOS workaround applied */
773 771 /*
774 772 * check if workaround is actually in place and issue warning
775 773 * if not.
776 774 */
777 775 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
778 776 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
779 777 #if defined(OPTERON_ERRATUM_298)
780 778 opteron_erratum_298++;
781 779 #else
782 780 workaround_warning(cpu, 298);
783 781 return (1);
784 782 #endif
785 783 }
786 784 break;
787 785 case -1: /* cannot determine via osvw: check cpuid */
788 786 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
789 787 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
790 788 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
791 789 #if defined(OPTERON_ERRATUM_298)
792 790 opteron_erratum_298++;
793 791 #else
794 792 workaround_warning(cpu, 298);
795 793 return (1);
796 794 #endif
797 795 }
798 796 break;
799 797 }
800 798 return (0);
801 799 }
802 800
803 801 uint_t
804 802 workaround_errata(struct cpu *cpu)
805 803 {
806 804 uint_t missing = 0;
807 805
808 806 ASSERT(cpu == CPU);
809 807
810 808 /*LINTED*/
811 809 if (cpuid_opteron_erratum(cpu, 88) > 0) {
812 810 /*
813 811 * SWAPGS May Fail To Read Correct GS Base
814 812 */
815 813 #if defined(OPTERON_ERRATUM_88)
816 814 /*
817 815 * The workaround is an mfence in the relevant assembler code
818 816 */
819 817 opteron_erratum_88++;
820 818 #else
821 819 workaround_warning(cpu, 88);
822 820 missing++;
823 821 #endif
824 822 }
825 823
826 824 if (cpuid_opteron_erratum(cpu, 91) > 0) {
827 825 /*
828 826 * Software Prefetches May Report A Page Fault
829 827 */
830 828 #if defined(OPTERON_ERRATUM_91)
831 829 /*
832 830 * fix is in trap.c
833 831 */
834 832 opteron_erratum_91++;
835 833 #else
836 834 workaround_warning(cpu, 91);
837 835 missing++;
838 836 #endif
839 837 }
840 838
841 839 if (cpuid_opteron_erratum(cpu, 93) > 0) {
842 840 /*
843 841 * RSM Auto-Halt Restart Returns to Incorrect RIP
844 842 */
845 843 #if defined(OPTERON_ERRATUM_93)
846 844 /*
847 845 * fix is in trap.c
848 846 */
849 847 opteron_erratum_93++;
850 848 #else
851 849 workaround_warning(cpu, 93);
852 850 missing++;
853 851 #endif
854 852 }
855 853
856 854 /*LINTED*/
857 855 if (cpuid_opteron_erratum(cpu, 95) > 0) {
858 856 /*
859 857 * RET Instruction May Return to Incorrect EIP
860 858 */
861 859 #if defined(OPTERON_ERRATUM_95)
862 860 #if defined(_LP64)
863 861 /*
864 862 * Workaround this by ensuring that 32-bit user code and
865 863 * 64-bit kernel code never occupy the same address
866 864 * range mod 4G.
867 865 */
868 866 if (_userlimit32 > 0xc0000000ul)
869 867 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
870 868
871 869 /*LINTED*/
872 870 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
873 871 opteron_erratum_95++;
874 872 #endif /* _LP64 */
875 873 #else
876 874 workaround_warning(cpu, 95);
877 875 missing++;
878 876 #endif
879 877 }
880 878
881 879 if (cpuid_opteron_erratum(cpu, 100) > 0) {
882 880 /*
883 881 * Compatibility Mode Branches Transfer to Illegal Address
884 882 */
885 883 #if defined(OPTERON_ERRATUM_100)
886 884 /*
887 885 * fix is in trap.c
888 886 */
889 887 opteron_erratum_100++;
890 888 #else
891 889 workaround_warning(cpu, 100);
892 890 missing++;
893 891 #endif
894 892 }
895 893
896 894 /*LINTED*/
897 895 if (cpuid_opteron_erratum(cpu, 108) > 0) {
898 896 /*
899 897 * CPUID Instruction May Return Incorrect Model Number In
900 898 * Some Processors
901 899 */
902 900 #if defined(OPTERON_ERRATUM_108)
903 901 /*
904 902 * (Our cpuid-handling code corrects the model number on
905 903 * those processors)
906 904 */
907 905 #else
908 906 workaround_warning(cpu, 108);
909 907 missing++;
910 908 #endif
911 909 }
912 910
913 911 /*LINTED*/
914 912 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
915 913 /*
916 914 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
917 915 */
918 916 #if defined(OPTERON_ERRATUM_109)
919 917 /*
920 918 * The "workaround" is to print a warning to upgrade the BIOS
921 919 */
922 920 uint64_t value;
923 921 const uint_t msr = MSR_AMD_PATCHLEVEL;
924 922 int err;
925 923
926 924 if ((err = checked_rdmsr(msr, &value)) != 0) {
927 925 msr_warning(cpu, "rd", msr, err);
928 926 workaround_warning(cpu, 109);
929 927 missing++;
930 928 }
931 929 if (value == 0)
932 930 opteron_erratum_109++;
933 931 #else
934 932 workaround_warning(cpu, 109);
935 933 missing++;
936 934 #endif
937 935 /*CONSTANTCONDITION*/
938 936 } while (0);
939 937
940 938 /*LINTED*/
941 939 if (cpuid_opteron_erratum(cpu, 121) > 0) {
942 940 /*
943 941 * Sequential Execution Across Non_Canonical Boundary Caused
944 942 * Processor Hang
945 943 */
946 944 #if defined(OPTERON_ERRATUM_121)
947 945 #if defined(_LP64)
948 946 /*
949 947 * Erratum 121 is only present in long (64 bit) mode.
950 948 * Workaround is to include the page immediately before the
951 949 * va hole to eliminate the possibility of system hangs due to
952 950 * sequential execution across the va hole boundary.
953 951 */
954 952 if (opteron_erratum_121)
955 953 opteron_erratum_121++;
956 954 else {
957 955 if (hole_start) {
958 956 hole_start -= PAGESIZE;
959 957 } else {
960 958 /*
961 959 * hole_start not yet initialized by
962 960 * mmu_init. Initialize hole_start
963 961 * with value to be subtracted.
964 962 */
965 963 hole_start = PAGESIZE;
966 964 }
967 965 opteron_erratum_121++;
968 966 }
969 967 #endif /* _LP64 */
970 968 #else
971 969 workaround_warning(cpu, 121);
972 970 missing++;
973 971 #endif
974 972 }
975 973
976 974 /*LINTED*/
977 975 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
978 976 /*
979 977 * TLB Flush Filter May Cause Coherency Problem in
980 978 * Multiprocessor Systems
981 979 */
982 980 #if defined(OPTERON_ERRATUM_122)
983 981 uint64_t value;
984 982 const uint_t msr = MSR_AMD_HWCR;
985 983 int error;
986 984
987 985 /*
988 986 * Erratum 122 is only present in MP configurations (multi-core
989 987 * or multi-processor).
990 988 */
991 989 #if defined(__xpv)
992 990 if (!DOMAIN_IS_INITDOMAIN(xen_info))
993 991 break;
994 992 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
995 993 break;
996 994 #else
997 995 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
998 996 cpuid_get_ncpu_per_chip(cpu) == 1)
999 997 break;
1000 998 #endif
1001 999 /* disable TLB Flush Filter */
1002 1000
1003 1001 if ((error = checked_rdmsr(msr, &value)) != 0) {
1004 1002 msr_warning(cpu, "rd", msr, error);
1005 1003 workaround_warning(cpu, 122);
1006 1004 missing++;
1007 1005 } else {
1008 1006 value |= (uint64_t)AMD_HWCR_FFDIS;
1009 1007 if ((error = checked_wrmsr(msr, value)) != 0) {
1010 1008 msr_warning(cpu, "wr", msr, error);
1011 1009 workaround_warning(cpu, 122);
1012 1010 missing++;
1013 1011 }
1014 1012 }
1015 1013 opteron_erratum_122++;
1016 1014 #else
1017 1015 workaround_warning(cpu, 122);
1018 1016 missing++;
1019 1017 #endif
1020 1018 /*CONSTANTCONDITION*/
1021 1019 } while (0);
1022 1020
1023 1021 /*LINTED*/
1024 1022 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1025 1023 /*
1026 1024 * Bypassed Reads May Cause Data Corruption of System Hang in
1027 1025 * Dual Core Processors
1028 1026 */
1029 1027 #if defined(OPTERON_ERRATUM_123)
1030 1028 uint64_t value;
1031 1029 const uint_t msr = MSR_AMD_PATCHLEVEL;
1032 1030 int err;
1033 1031
1034 1032 /*
1035 1033 * Erratum 123 applies only to multi-core cpus.
1036 1034 */
1037 1035 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1038 1036 break;
1039 1037 #if defined(__xpv)
1040 1038 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1041 1039 break;
1042 1040 #endif
1043 1041 /*
1044 1042 * The "workaround" is to print a warning to upgrade the BIOS
1045 1043 */
1046 1044 if ((err = checked_rdmsr(msr, &value)) != 0) {
1047 1045 msr_warning(cpu, "rd", msr, err);
1048 1046 workaround_warning(cpu, 123);
1049 1047 missing++;
1050 1048 }
1051 1049 if (value == 0)
1052 1050 opteron_erratum_123++;
1053 1051 #else
1054 1052 workaround_warning(cpu, 123);
1055 1053 missing++;
1056 1054
1057 1055 #endif
1058 1056 /*CONSTANTCONDITION*/
1059 1057 } while (0);
1060 1058
1061 1059 /*LINTED*/
1062 1060 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1063 1061 /*
1064 1062 * Multiprocessor Systems with Four or More Cores May Deadlock
1065 1063 * Waiting for a Probe Response
1066 1064 */
1067 1065 #if defined(OPTERON_ERRATUM_131)
1068 1066 uint64_t nbcfg;
1069 1067 const uint_t msr = MSR_AMD_NB_CFG;
1070 1068 const uint64_t wabits =
1071 1069 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1072 1070 int error;
1073 1071
1074 1072 /*
1075 1073 * Erratum 131 applies to any system with four or more cores.
1076 1074 */
1077 1075 if (opteron_erratum_131)
1078 1076 break;
1079 1077 #if defined(__xpv)
1080 1078 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1081 1079 break;
1082 1080 if (xpv_nr_phys_cpus() < 4)
1083 1081 break;
1084 1082 #else
1085 1083 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1086 1084 break;
1087 1085 #endif
1088 1086 /*
1089 1087 * Print a warning if neither of the workarounds for
1090 1088 * erratum 131 is present.
1091 1089 */
1092 1090 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1093 1091 msr_warning(cpu, "rd", msr, error);
1094 1092 workaround_warning(cpu, 131);
1095 1093 missing++;
1096 1094 } else if ((nbcfg & wabits) == 0) {
1097 1095 opteron_erratum_131++;
1098 1096 } else {
1099 1097 /* cannot have both workarounds set */
1100 1098 ASSERT((nbcfg & wabits) != wabits);
1101 1099 }
1102 1100 #else
1103 1101 workaround_warning(cpu, 131);
1104 1102 missing++;
1105 1103 #endif
1106 1104 /*CONSTANTCONDITION*/
1107 1105 } while (0);
1108 1106
1109 1107 /*
1110 1108 * This isn't really an erratum, but for convenience the
1111 1109 * detection/workaround code lives here and in cpuid_opteron_erratum.
1112 1110 */
1113 1111 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1114 1112 #if defined(OPTERON_WORKAROUND_6336786)
1115 1113 /*
1116 1114 * Disable C1-Clock ramping on multi-core/multi-processor
1117 1115 * K8 platforms to guard against TSC drift.
1118 1116 */
1119 1117 if (opteron_workaround_6336786) {
1120 1118 opteron_workaround_6336786++;
1121 1119 #if defined(__xpv)
1122 1120 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1123 1121 xpv_nr_phys_cpus() > 1) ||
1124 1122 opteron_workaround_6336786_UP) {
1125 1123 /*
1126 1124 * XXPV Hmm. We can't walk the Northbridges on
1127 1125 * the hypervisor; so just complain and drive
1128 1126 * on. This probably needs to be fixed in
1129 1127 * the hypervisor itself.
1130 1128 */
1131 1129 opteron_workaround_6336786++;
1132 1130 workaround_warning(cpu, 6336786);
1133 1131 #else /* __xpv */
1134 1132 } else if ((opteron_get_nnodes() *
1135 1133 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1136 1134 opteron_workaround_6336786_UP) {
1137 1135
1138 1136 uint_t node, nnodes;
1139 1137 uint8_t data;
1140 1138
1141 1139 nnodes = opteron_get_nnodes();
1142 1140 for (node = 0; node < nnodes; node++) {
1143 1141 /*
1144 1142 * Clear PMM7[1:0] (function 3, offset 0x87)
1145 1143 * Northbridge device is the node id + 24.
1146 1144 */
1147 1145 data = pci_getb_func(0, node + 24, 3, 0x87);
1148 1146 data &= 0xFC;
1149 1147 pci_putb_func(0, node + 24, 3, 0x87, data);
1150 1148 }
1151 1149 opteron_workaround_6336786++;
1152 1150 #endif /* __xpv */
1153 1151 }
1154 1152 #else
1155 1153 workaround_warning(cpu, 6336786);
1156 1154 missing++;
1157 1155 #endif
1158 1156 }
1159 1157
1160 1158 /*LINTED*/
1161 1159 /*
1162 1160 * Mutex primitives don't work as expected.
1163 1161 */
1164 1162 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1165 1163 #if defined(OPTERON_WORKAROUND_6323525)
1166 1164 /*
1167 1165 * This problem only occurs with 2 or more cores. If bit in
1168 1166 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1169 1167 * is to patch the semaphone routines with the lfence
1170 1168 * instruction to provide necessary load memory barrier with
1171 1169 * possible subsequent read-modify-write ops.
1172 1170 *
1173 1171 * It is too early in boot to call the patch routine so
1174 1172 * set erratum variable to be done in startup_end().
1175 1173 */
1176 1174 if (opteron_workaround_6323525) {
1177 1175 opteron_workaround_6323525++;
1178 1176 #if defined(__xpv)
1179 1177 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1180 1178 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1181 1179 /*
1182 1180 * XXPV Use dom0_msr here when extended
1183 1181 * operations are supported?
1184 1182 */
1185 1183 if (xpv_nr_phys_cpus() > 1)
1186 1184 opteron_workaround_6323525++;
1187 1185 } else {
1188 1186 /*
1189 1187 * We have no way to tell how many physical
1190 1188 * cpus there are, or even if this processor
1191 1189 * has the problem, so enable the workaround
1192 1190 * unconditionally (at some performance cost).
1193 1191 */
1194 1192 opteron_workaround_6323525++;
1195 1193 }
1196 1194 #else /* __xpv */
1197 1195 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1198 1196 ((opteron_get_nnodes() *
1199 1197 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1200 1198 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1201 1199 opteron_workaround_6323525++;
1202 1200 #endif /* __xpv */
1203 1201 }
1204 1202 #else
1205 1203 workaround_warning(cpu, 6323525);
1206 1204 missing++;
1207 1205 #endif
1208 1206 }
1209 1207
1210 1208 missing += do_erratum_298(cpu);
1211 1209
1212 1210 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1213 1211 #if defined(OPTERON_ERRATUM_721)
1214 1212 on_trap_data_t otd;
1215 1213
1216 1214 if (!on_trap(&otd, OT_DATA_ACCESS))
1217 1215 wrmsr(MSR_AMD_DE_CFG,
1218 1216 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1219 1217 no_trap();
1220 1218
1221 1219 opteron_erratum_721++;
1222 1220 #else
1223 1221 workaround_warning(cpu, 721);
1224 1222 missing++;
1225 1223 #endif
1226 1224 }
1227 1225
1228 1226 #ifdef __xpv
1229 1227 return (0);
1230 1228 #else
1231 1229 return (missing);
1232 1230 #endif
1233 1231 }
1234 1232
1235 1233 void
1236 1234 workaround_errata_end()
1237 1235 {
1238 1236 #if defined(OPTERON_ERRATUM_88)
1239 1237 if (opteron_erratum_88)
1240 1238 workaround_applied(88);
1241 1239 #endif
1242 1240 #if defined(OPTERON_ERRATUM_91)
1243 1241 if (opteron_erratum_91)
1244 1242 workaround_applied(91);
1245 1243 #endif
1246 1244 #if defined(OPTERON_ERRATUM_93)
1247 1245 if (opteron_erratum_93)
1248 1246 workaround_applied(93);
1249 1247 #endif
1250 1248 #if defined(OPTERON_ERRATUM_95)
1251 1249 if (opteron_erratum_95)
1252 1250 workaround_applied(95);
1253 1251 #endif
1254 1252 #if defined(OPTERON_ERRATUM_100)
1255 1253 if (opteron_erratum_100)
1256 1254 workaround_applied(100);
1257 1255 #endif
1258 1256 #if defined(OPTERON_ERRATUM_108)
1259 1257 if (opteron_erratum_108)
1260 1258 workaround_applied(108);
1261 1259 #endif
1262 1260 #if defined(OPTERON_ERRATUM_109)
1263 1261 if (opteron_erratum_109) {
1264 1262 cmn_err(CE_WARN,
1265 1263 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1266 1264 " processor\nerratum 109 was not detected; updating your"
1267 1265 " system's BIOS to a version\ncontaining this"
1268 1266 " microcode patch is HIGHLY recommended or erroneous"
1269 1267 " system\noperation may occur.\n");
1270 1268 }
1271 1269 #endif
1272 1270 #if defined(OPTERON_ERRATUM_121)
1273 1271 if (opteron_erratum_121)
1274 1272 workaround_applied(121);
1275 1273 #endif
1276 1274 #if defined(OPTERON_ERRATUM_122)
1277 1275 if (opteron_erratum_122)
1278 1276 workaround_applied(122);
1279 1277 #endif
1280 1278 #if defined(OPTERON_ERRATUM_123)
1281 1279 if (opteron_erratum_123) {
1282 1280 cmn_err(CE_WARN,
1283 1281 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1284 1282 " processor\nerratum 123 was not detected; updating your"
1285 1283 " system's BIOS to a version\ncontaining this"
1286 1284 " microcode patch is HIGHLY recommended or erroneous"
1287 1285 " system\noperation may occur.\n");
1288 1286 }
1289 1287 #endif
1290 1288 #if defined(OPTERON_ERRATUM_131)
1291 1289 if (opteron_erratum_131) {
1292 1290 cmn_err(CE_WARN,
1293 1291 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1294 1292 " processor\nerratum 131 was not detected; updating your"
1295 1293 " system's BIOS to a version\ncontaining this"
1296 1294 " microcode patch is HIGHLY recommended or erroneous"
1297 1295 " system\noperation may occur.\n");
1298 1296 }
1299 1297 #endif
1300 1298 #if defined(OPTERON_WORKAROUND_6336786)
1301 1299 if (opteron_workaround_6336786)
1302 1300 workaround_applied(6336786);
1303 1301 #endif
1304 1302 #if defined(OPTERON_WORKAROUND_6323525)
1305 1303 if (opteron_workaround_6323525)
1306 1304 workaround_applied(6323525);
1307 1305 #endif
1308 1306 #if defined(OPTERON_ERRATUM_298)
1309 1307 if (opteron_erratum_298) {
1310 1308 cmn_err(CE_WARN,
1311 1309 "BIOS microcode patch for AMD 64/Opteron(tm)"
1312 1310 " processor\nerratum 298 was not detected; updating your"
1313 1311 " system's BIOS to a version\ncontaining this"
1314 1312 " microcode patch is HIGHLY recommended or erroneous"
1315 1313 " system\noperation may occur.\n");
1316 1314 }
1317 1315 #endif
1318 1316 #if defined(OPTERON_ERRATUM_721)
1319 1317 if (opteron_erratum_721)
1320 1318 workaround_applied(721);
1321 1319 #endif
1322 1320 }
1323 1321
1324 1322 /*
1325 1323 * The procset_slave and procset_master are used to synchronize
1326 1324 * between the control CPU and the target CPU when starting CPUs.
1327 1325 */
1328 1326 static cpuset_t procset_slave, procset_master;
1329 1327
1330 1328 static void
1331 1329 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1332 1330 {
1333 1331 cpuset_t tempset;
1334 1332
1335 1333 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1336 1334 tempset = *(volatile cpuset_t *)sp) {
1337 1335 SMT_PAUSE();
1338 1336 }
1339 1337 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1340 1338 }
1341 1339
1342 1340 static void
1343 1341 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1344 1342 {
1345 1343 cpuset_t tempset;
1346 1344
1347 1345 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1348 1346 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1349 1347 tempset = *(volatile cpuset_t *)sp) {
1350 1348 SMT_PAUSE();
1351 1349 }
1352 1350 }
1353 1351
1354 1352 int
1355 1353 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1356 1354 {
1357 1355 _NOTE(ARGUNUSED(boot));
1358 1356
1359 1357 void *ctx;
1360 1358 int delays;
1361 1359 int error = 0;
1362 1360 cpuset_t tempset;
1363 1361 processorid_t cpuid;
1364 1362 #ifndef __xpv
1365 1363 extern void cpupm_init(cpu_t *);
1366 1364 #endif
1367 1365
1368 1366 ASSERT(cp != NULL);
1369 1367 cpuid = cp->cpu_id;
1370 1368 ctx = mach_cpucontext_alloc(cp);
1371 1369 if (ctx == NULL) {
1372 1370 cmn_err(CE_WARN,
1373 1371 "cpu%d: failed to allocate context", cp->cpu_id);
1374 1372 return (EAGAIN);
1375 1373 }
1376 1374 error = mach_cpu_start(cp, ctx);
1377 1375 if (error != 0) {
1378 1376 cmn_err(CE_WARN,
1379 1377 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1380 1378 mach_cpucontext_free(cp, ctx, error);
1381 1379 return (error);
1382 1380 }
1383 1381
1384 1382 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1385 1383 delays++) {
1386 1384 if (delays == 500) {
1387 1385 /*
1388 1386 * After five seconds, things are probably looking
1389 1387 * a bit bleak - explain the hang.
1390 1388 */
1391 1389 cmn_err(CE_NOTE, "cpu%d: started, "
1392 1390 "but not running in the kernel yet", cpuid);
1393 1391 } else if (delays > 2000) {
1394 1392 /*
1395 1393 * We waited at least 20 seconds, bail ..
1396 1394 */
1397 1395 error = ETIMEDOUT;
1398 1396 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1399 1397 mach_cpucontext_free(cp, ctx, error);
1400 1398 return (error);
1401 1399 }
1402 1400
1403 1401 /*
1404 1402 * wait at least 10ms, then check again..
1405 1403 */
1406 1404 delay(USEC_TO_TICK_ROUNDUP(10000));
1407 1405 tempset = *((volatile cpuset_t *)&procset_slave);
1408 1406 }
1409 1407 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1410 1408
1411 1409 mach_cpucontext_free(cp, ctx, 0);
1412 1410
1413 1411 #ifndef __xpv
1414 1412 if (tsc_gethrtime_enable)
1415 1413 tsc_sync_master(cpuid);
1416 1414 #endif
1417 1415
1418 1416 if (dtrace_cpu_init != NULL) {
1419 1417 (*dtrace_cpu_init)(cpuid);
1420 1418 }
1421 1419
1422 1420 /*
1423 1421 * During CPU DR operations, the cpu_lock is held by current
1424 1422 * (the control) thread. We can't release the cpu_lock here
1425 1423 * because that will break the CPU DR logic.
1426 1424 * On the other hand, CPUPM and processor group initialization
1427 1425 * routines need to access the cpu_lock. So we invoke those
1428 1426 * routines here on behalf of mp_startup_common().
1429 1427 *
1430 1428 * CPUPM and processor group initialization routines depend
1431 1429 * on the cpuid probing results. Wait for mp_startup_common()
1432 1430 * to signal that cpuid probing is done.
1433 1431 */
1434 1432 mp_startup_wait(&procset_slave, cpuid);
1435 1433 #ifndef __xpv
1436 1434 cpupm_init(cp);
1437 1435 #endif
1438 1436 (void) pg_cpu_init(cp, B_FALSE);
1439 1437 cpu_set_state(cp);
1440 1438 mp_startup_signal(&procset_master, cpuid);
1441 1439
1442 1440 return (0);
1443 1441 }
1444 1442
1445 1443 /*
1446 1444 * Start a single cpu, assuming that the kernel context is available
1447 1445 * to successfully start another cpu.
1448 1446 *
1449 1447 * (For example, real mode code is mapped into the right place
1450 1448 * in memory and is ready to be run.)
1451 1449 */
1452 1450 int
1453 1451 start_cpu(processorid_t who)
1454 1452 {
1455 1453 cpu_t *cp;
1456 1454 int error = 0;
1457 1455 cpuset_t tempset;
1458 1456
1459 1457 ASSERT(who != 0);
1460 1458
1461 1459 /*
1462 1460 * Check if there's at least a Mbyte of kmem available
1463 1461 * before attempting to start the cpu.
1464 1462 */
1465 1463 if (kmem_avail() < 1024 * 1024) {
1466 1464 /*
1467 1465 * Kick off a reap in case that helps us with
1468 1466 * later attempts ..
1469 1467 */
1470 1468 kmem_reap();
1471 1469 return (ENOMEM);
1472 1470 }
1473 1471
1474 1472 /*
1475 1473 * First configure cpu.
1476 1474 */
1477 1475 cp = mp_cpu_configure_common(who, B_TRUE);
1478 1476 ASSERT(cp != NULL);
1479 1477
1480 1478 /*
1481 1479 * Then start cpu.
1482 1480 */
1483 1481 error = mp_start_cpu_common(cp, B_TRUE);
1484 1482 if (error != 0) {
1485 1483 mp_cpu_unconfigure_common(cp, error);
1486 1484 return (error);
1487 1485 }
1488 1486
1489 1487 mutex_exit(&cpu_lock);
1490 1488 tempset = cpu_ready_set;
1491 1489 while (!CPU_IN_SET(tempset, who)) {
1492 1490 drv_usecwait(1);
1493 1491 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1494 1492 }
1495 1493 mutex_enter(&cpu_lock);
1496 1494
1497 1495 return (0);
1498 1496 }
1499 1497
1500 1498 void
1501 1499 start_other_cpus(int cprboot)
1502 1500 {
1503 1501 _NOTE(ARGUNUSED(cprboot));
1504 1502
1505 1503 uint_t who;
1506 1504 uint_t bootcpuid = 0;
1507 1505
1508 1506 /*
1509 1507 * Initialize our own cpu_info.
1510 1508 */
1511 1509 init_cpu_info(CPU);
1512 1510
1513 1511 #if !defined(__xpv)
1514 1512 init_cpu_id_gdt(CPU);
1515 1513 #endif
1516 1514
1517 1515 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1518 1516 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1519 1517
1520 1518 /*
1521 1519 * Initialize our syscall handlers
1522 1520 */
1523 1521 init_cpu_syscall(CPU);
1524 1522
1525 1523 /*
1526 1524 * Take the boot cpu out of the mp_cpus set because we know
1527 1525 * it's already running. Add it to the cpu_ready_set for
1528 1526 * precisely the same reason.
1529 1527 */
1530 1528 CPUSET_DEL(mp_cpus, bootcpuid);
1531 1529 CPUSET_ADD(cpu_ready_set, bootcpuid);
1532 1530
1533 1531 /*
1534 1532 * skip the rest of this if
1535 1533 * . only 1 cpu dectected and system isn't hotplug-capable
1536 1534 * . not using MP
1537 1535 */
1538 1536 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1539 1537 use_mp == 0) {
1540 1538 if (use_mp == 0)
1541 1539 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1542 1540 goto done;
1543 1541 }
1544 1542
1545 1543 /*
1546 1544 * perform such initialization as is needed
1547 1545 * to be able to take CPUs on- and off-line.
1548 1546 */
1549 1547 cpu_pause_init();
1550 1548
1551 1549 xc_init_cpu(CPU); /* initialize processor crosscalls */
1552 1550
1553 1551 if (mach_cpucontext_init() != 0)
1554 1552 goto done;
1555 1553
1556 1554 flushes_require_xcalls = 1;
1557 1555
1558 1556 /*
1559 1557 * We lock our affinity to the master CPU to ensure that all slave CPUs
1560 1558 * do their TSC syncs with the same CPU.
1561 1559 */
1562 1560 affinity_set(CPU_CURRENT);
1563 1561
1564 1562 for (who = 0; who < NCPU; who++) {
1565 1563 if (!CPU_IN_SET(mp_cpus, who))
1566 1564 continue;
1567 1565 ASSERT(who != bootcpuid);
1568 1566
1569 1567 mutex_enter(&cpu_lock);
1570 1568 if (start_cpu(who) != 0)
1571 1569 CPUSET_DEL(mp_cpus, who);
1572 1570 cpu_state_change_notify(who, CPU_SETUP);
1573 1571 mutex_exit(&cpu_lock);
1574 1572 }
1575 1573
1576 1574 /* Free the space allocated to hold the microcode file */
1577 1575 ucode_cleanup();
1578 1576
1579 1577 affinity_clear();
1580 1578
1581 1579 mach_cpucontext_fini();
1582 1580
1583 1581 done:
1584 1582 if (get_hwenv() == HW_NATIVE)
1585 1583 workaround_errata_end();
1586 1584 cmi_post_mpstartup();
1587 1585
1588 1586 if (use_mp && ncpus != boot_max_ncpus) {
1589 1587 cmn_err(CE_NOTE,
1590 1588 "System detected %d cpus, but "
1591 1589 "only %d cpu(s) were enabled during boot.",
1592 1590 boot_max_ncpus, ncpus);
1593 1591 cmn_err(CE_NOTE,
1594 1592 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1595 1593 "See eeprom(1M).");
1596 1594 }
1597 1595 }
1598 1596
1599 1597 int
1600 1598 mp_cpu_configure(int cpuid)
1601 1599 {
1602 1600 cpu_t *cp;
1603 1601
1604 1602 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1605 1603 return (ENOTSUP);
1606 1604 }
1607 1605
1608 1606 cp = cpu_get(cpuid);
1609 1607 if (cp != NULL) {
1610 1608 return (EALREADY);
1611 1609 }
1612 1610
1613 1611 /*
1614 1612 * Check if there's at least a Mbyte of kmem available
1615 1613 * before attempting to start the cpu.
1616 1614 */
1617 1615 if (kmem_avail() < 1024 * 1024) {
1618 1616 /*
1619 1617 * Kick off a reap in case that helps us with
1620 1618 * later attempts ..
1621 1619 */
1622 1620 kmem_reap();
1623 1621 return (ENOMEM);
1624 1622 }
1625 1623
1626 1624 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1627 1625 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1628 1626
1629 1627 return (cp != NULL ? 0 : EAGAIN);
1630 1628 }
1631 1629
1632 1630 int
1633 1631 mp_cpu_unconfigure(int cpuid)
1634 1632 {
1635 1633 cpu_t *cp;
1636 1634
1637 1635 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1638 1636 return (ENOTSUP);
1639 1637 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1640 1638 return (EINVAL);
1641 1639 }
1642 1640
1643 1641 cp = cpu_get(cpuid);
1644 1642 if (cp == NULL) {
1645 1643 return (ENODEV);
1646 1644 }
1647 1645 mp_cpu_unconfigure_common(cp, 0);
1648 1646
1649 1647 return (0);
1650 1648 }
1651 1649
1652 1650 /*
1653 1651 * Startup function for 'other' CPUs (besides boot cpu).
1654 1652 * Called from real_mode_start.
1655 1653 *
1656 1654 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1657 1655 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1658 1656 * hat_unload which requires CPU_READY to be set.
1659 1657 */
1660 1658 static void
1661 1659 mp_startup_common(boolean_t boot)
1662 1660 {
1663 1661 cpu_t *cp = CPU;
1664 1662 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1665 1663 extern void cpu_event_init_cpu(cpu_t *);
1666 1664
1667 1665 /*
1668 1666 * We need to get TSC on this proc synced (i.e., any delta
1669 1667 * from cpu0 accounted for) as soon as we can, because many
1670 1668 * many things use gethrtime/pc_gethrestime, including
1671 1669 * interrupts, cmn_err, etc. Before we can do that, we want to
1672 1670 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1673 1671 * right away.
1674 1672 */
1675 1673 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1676 1674 cpuid_pass1(cp, new_x86_featureset);
1677 1675
1678 1676 if (boot && get_hwenv() == HW_NATIVE &&
1679 1677 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1680 1678 cpuid_getfamily(CPU) == 6 &&
1681 1679 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1682 1680 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1683 1681 (void) wrmsr(REG_TSC, 0UL);
1684 1682 }
1685 1683
1686 1684 /* Let the control CPU continue into tsc_sync_master() */
1687 1685 mp_startup_signal(&procset_slave, cp->cpu_id);
1688 1686
1689 1687 #ifndef __xpv
1690 1688 if (tsc_gethrtime_enable)
1691 1689 tsc_sync_slave();
1692 1690 #endif
1693 1691
1694 1692 /*
1695 1693 * Once this was done from assembly, but it's safer here; if
1696 1694 * it blocks, we need to be able to swtch() to and from, and
1697 1695 * since we get here by calling t_pc, we need to do that call
1698 1696 * before swtch() overwrites it.
1699 1697 */
1700 1698 (void) (*ap_mlsetup)();
1701 1699
1702 1700 #ifndef __xpv
1703 1701 /*
1704 1702 * Program this cpu's PAT
1705 1703 */
1706 1704 pat_sync();
1707 1705 #endif
1708 1706
1709 1707 /*
1710 1708 * Set up TSC_AUX to contain the cpuid for this processor
1711 1709 * for the rdtscp instruction.
1712 1710 */
1713 1711 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1714 1712 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1715 1713
1716 1714 /*
1717 1715 * Initialize this CPU's syscall handlers
1718 1716 */
1719 1717 init_cpu_syscall(cp);
1720 1718
1721 1719 /*
1722 1720 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1723 1721 * highest level at which a routine is permitted to block on
1724 1722 * an adaptive mutex (allows for cpu poke interrupt in case
1725 1723 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1726 1724 * device interrupts that may end up in the hat layer issuing cross
1727 1725 * calls before CPU_READY is set.
1728 1726 */
1729 1727 splx(ipltospl(LOCK_LEVEL));
1730 1728 sti();
1731 1729
1732 1730 /*
1733 1731 * Do a sanity check to make sure this new CPU is a sane thing
1734 1732 * to add to the collection of processors running this system.
1735 1733 *
1736 1734 * XXX Clearly this needs to get more sophisticated, if x86
1737 1735 * systems start to get built out of heterogenous CPUs; as is
1738 1736 * likely to happen once the number of processors in a configuration
1739 1737 * gets large enough.
1740 1738 */
1741 1739 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1742 1740 B_FALSE) {
1743 1741 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1744 1742 print_x86_featureset(new_x86_featureset);
1745 1743 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1746 1744 }
1747 1745
1748 1746 /*
1749 1747 * We do not support cpus with mixed monitor/mwait support if the
1750 1748 * boot cpu supports monitor/mwait.
1751 1749 */
1752 1750 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1753 1751 is_x86_feature(new_x86_featureset, X86FSET_MWAIT))
1754 1752 panic("unsupported mixed cpu monitor/mwait support detected");
1755 1753
1756 1754 /*
1757 1755 * We could be more sophisticated here, and just mark the CPU
1758 1756 * as "faulted" but at this point we'll opt for the easier
1759 1757 * answer of dying horribly. Provided the boot cpu is ok,
1760 1758 * the system can be recovered by booting with use_mp set to zero.
1761 1759 */
1762 1760 if (workaround_errata(cp) != 0)
1763 1761 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1764 1762
1765 1763 /*
1766 1764 * We can touch cpu_flags here without acquiring the cpu_lock here
1767 1765 * because the cpu_lock is held by the control CPU which is running
1768 1766 * mp_start_cpu_common().
1769 1767 * Need to clear CPU_QUIESCED flag before calling any function which
1770 1768 * may cause thread context switching, such as kmem_alloc() etc.
1771 1769 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1772 1770 * it's set. So the startup thread may have no chance to switch back
1773 1771 * again if it's switched away with CPU_QUIESCED set.
1774 1772 */
1775 1773 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1776 1774
1777 1775 /*
1778 1776 * Setup this processor for XSAVE.
1779 1777 */
1780 1778 if (fp_save_mech == FP_XSAVE) {
1781 1779 xsave_setup_msr(cp);
1782 1780 }
1783 1781
1784 1782 cpuid_pass2(cp);
1785 1783 cpuid_pass3(cp);
1786 1784 cpuid_pass4(cp, NULL);
1787 1785
1788 1786 /*
1789 1787 * Correct cpu_idstr and cpu_brandstr on target CPU after
1790 1788 * cpuid_pass1() is done.
1791 1789 */
1792 1790 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1793 1791 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1794 1792
1795 1793 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1796 1794
1797 1795 post_startup_cpu_fixups();
1798 1796
1799 1797 cpu_event_init_cpu(cp);
1800 1798
1801 1799 /*
1802 1800 * Enable preemption here so that contention for any locks acquired
1803 1801 * later in mp_startup_common may be preempted if the thread owning
1804 1802 * those locks is continuously executing on other CPUs (for example,
1805 1803 * this CPU must be preemptible to allow other CPUs to pause it during
1806 1804 * their startup phases). It's safe to enable preemption here because
1807 1805 * the CPU state is pretty-much fully constructed.
1808 1806 */
1809 1807 curthread->t_preempt = 0;
1810 1808
1811 1809 /* The base spl should still be at LOCK LEVEL here */
1812 1810 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1813 1811 set_base_spl(); /* Restore the spl to its proper value */
1814 1812
1815 1813 pghw_physid_create(cp);
1816 1814 /*
1817 1815 * Delegate initialization tasks, which need to access the cpu_lock,
1818 1816 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1819 1817 * during CPU DR operations.
1820 1818 */
1821 1819 mp_startup_signal(&procset_slave, cp->cpu_id);
1822 1820 mp_startup_wait(&procset_master, cp->cpu_id);
1823 1821 pg_cmt_cpu_startup(cp);
1824 1822
1825 1823 if (boot) {
1826 1824 mutex_enter(&cpu_lock);
1827 1825 cp->cpu_flags &= ~CPU_OFFLINE;
1828 1826 cpu_enable_intr(cp);
1829 1827 cpu_add_active(cp);
1830 1828 mutex_exit(&cpu_lock);
1831 1829 }
1832 1830
1833 1831 /* Enable interrupts */
1834 1832 (void) spl0();
1835 1833
1836 1834 /*
1837 1835 * Fill out cpu_ucode_info. Update microcode if necessary.
1838 1836 */
1839 1837 ucode_check(cp);
1840 1838
1841 1839 #ifndef __xpv
1842 1840 {
1843 1841 /*
1844 1842 * Set up the CPU module for this CPU. This can't be done
1845 1843 * before this CPU is made CPU_READY, because we may (in
1846 1844 * heterogeneous systems) need to go load another CPU module.
1847 1845 * The act of attempting to load a module may trigger a
1848 1846 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1849 1847 */
1850 1848 cmi_hdl_t hdl;
1851 1849
1852 1850 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1853 1851 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1854 1852 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1855 1853 cmi_mca_init(hdl);
1856 1854 cp->cpu_m.mcpu_cmi_hdl = hdl;
1857 1855 }
1858 1856 }
1859 1857 #endif /* __xpv */
1860 1858
1861 1859 if (boothowto & RB_DEBUG)
1862 1860 kdi_cpu_init();
1863 1861
1864 1862 /*
1865 1863 * Setting the bit in cpu_ready_set must be the last operation in
1866 1864 * processor initialization; the boot CPU will continue to boot once
1867 1865 * it sees this bit set for all active CPUs.
1868 1866 */
1869 1867 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1870 1868
1871 1869 (void) mach_cpu_create_device_node(cp, NULL);
1872 1870
1873 1871 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1874 1872 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1875 1873 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1876 1874 cp->cpu_id);
1877 1875
1878 1876 /*
1879 1877 * Now we are done with the startup thread, so free it up.
1880 1878 */
1881 1879 thread_exit();
1882 1880 panic("mp_startup: cannot return");
1883 1881 /*NOTREACHED*/
1884 1882 }
1885 1883
1886 1884 /*
1887 1885 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1888 1886 */
1889 1887 static void
1890 1888 mp_startup_boot(void)
1891 1889 {
1892 1890 mp_startup_common(B_TRUE);
1893 1891 }
1894 1892
1895 1893 /*
1896 1894 * Startup function for hotplug CPUs at runtime.
1897 1895 */
1898 1896 void
1899 1897 mp_startup_hotplug(void)
1900 1898 {
1901 1899 mp_startup_common(B_FALSE);
1902 1900 }
1903 1901
1904 1902 /*
1905 1903 * Start CPU on user request.
1906 1904 */
1907 1905 /* ARGSUSED */
1908 1906 int
1909 1907 mp_cpu_start(struct cpu *cp)
1910 1908 {
1911 1909 ASSERT(MUTEX_HELD(&cpu_lock));
1912 1910 return (0);
1913 1911 }
1914 1912
1915 1913 /*
1916 1914 * Stop CPU on user request.
1917 1915 */
1918 1916 int
1919 1917 mp_cpu_stop(struct cpu *cp)
1920 1918 {
1921 1919 extern int cbe_psm_timer_mode;
1922 1920 ASSERT(MUTEX_HELD(&cpu_lock));
1923 1921
1924 1922 #ifdef __xpv
1925 1923 /*
1926 1924 * We can't offline vcpu0.
1927 1925 */
1928 1926 if (cp->cpu_id == 0)
1929 1927 return (EBUSY);
1930 1928 #endif
1931 1929
1932 1930 /*
1933 1931 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1934 1932 * can't stop it. (This is true only for machines with no TSC.)
1935 1933 */
1936 1934
1937 1935 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1938 1936 return (EBUSY);
1939 1937
1940 1938 return (0);
1941 1939 }
1942 1940
1943 1941 /*
1944 1942 * Take the specified CPU out of participation in interrupts.
1945 1943 */
1946 1944 int
1947 1945 cpu_disable_intr(struct cpu *cp)
1948 1946 {
1949 1947 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1950 1948 return (EBUSY);
1951 1949
1952 1950 cp->cpu_flags &= ~CPU_ENABLE;
1953 1951 return (0);
1954 1952 }
1955 1953
1956 1954 /*
1957 1955 * Allow the specified CPU to participate in interrupts.
1958 1956 */
1959 1957 void
1960 1958 cpu_enable_intr(struct cpu *cp)
1961 1959 {
1962 1960 ASSERT(MUTEX_HELD(&cpu_lock));
1963 1961 cp->cpu_flags |= CPU_ENABLE;
1964 1962 psm_enable_intr(cp->cpu_id);
1965 1963 }
1966 1964
1967 1965 void
1968 1966 mp_cpu_faulted_enter(struct cpu *cp)
1969 1967 {
1970 1968 #ifdef __xpv
1971 1969 _NOTE(ARGUNUSED(cp));
1972 1970 #else
1973 1971 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1974 1972
1975 1973 if (hdl != NULL) {
1976 1974 cmi_hdl_hold(hdl);
1977 1975 } else {
1978 1976 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1979 1977 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1980 1978 }
1981 1979 if (hdl != NULL) {
1982 1980 cmi_faulted_enter(hdl);
1983 1981 cmi_hdl_rele(hdl);
1984 1982 }
1985 1983 #endif
1986 1984 }
1987 1985
1988 1986 void
1989 1987 mp_cpu_faulted_exit(struct cpu *cp)
1990 1988 {
1991 1989 #ifdef __xpv
1992 1990 _NOTE(ARGUNUSED(cp));
1993 1991 #else
1994 1992 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1995 1993
1996 1994 if (hdl != NULL) {
1997 1995 cmi_hdl_hold(hdl);
1998 1996 } else {
1999 1997 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2000 1998 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2001 1999 }
2002 2000 if (hdl != NULL) {
2003 2001 cmi_faulted_exit(hdl);
2004 2002 cmi_hdl_rele(hdl);
2005 2003 }
2006 2004 #endif
2007 2005 }
2008 2006
2009 2007 /*
2010 2008 * The following two routines are used as context operators on threads belonging
2011 2009 * to processes with a private LDT (see sysi86). Due to the rarity of such
2012 2010 * processes, these routines are currently written for best code readability and
2013 2011 * organization rather than speed. We could avoid checking x86_featureset at
2014 2012 * every context switch by installing different context ops, depending on
2015 2013 * x86_featureset, at LDT creation time -- one for each combination of fast
2016 2014 * syscall features.
2017 2015 */
2018 2016
2019 2017 /*ARGSUSED*/
2020 2018 void
2021 2019 cpu_fast_syscall_disable(void *arg)
2022 2020 {
2023 2021 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2024 2022 is_x86_feature(x86_featureset, X86FSET_SEP))
2025 2023 cpu_sep_disable();
2026 2024 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2027 2025 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2028 2026 cpu_asysc_disable();
2029 2027 }
2030 2028
2031 2029 /*ARGSUSED*/
2032 2030 void
2033 2031 cpu_fast_syscall_enable(void *arg)
2034 2032 {
2035 2033 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2036 2034 is_x86_feature(x86_featureset, X86FSET_SEP))
2037 2035 cpu_sep_enable();
2038 2036 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2039 2037 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2040 2038 cpu_asysc_enable();
2041 2039 }
2042 2040
2043 2041 static void
2044 2042 cpu_sep_enable(void)
2045 2043 {
2046 2044 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2047 2045 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2048 2046
2049 2047 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2050 2048 }
2051 2049
2052 2050 static void
2053 2051 cpu_sep_disable(void)
2054 2052 {
2055 2053 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2056 2054 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2057 2055
2058 2056 /*
2059 2057 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2060 2058 * the sysenter or sysexit instruction to trigger a #gp fault.
2061 2059 */
2062 2060 wrmsr(MSR_INTC_SEP_CS, 0);
2063 2061 }
2064 2062
2065 2063 static void
2066 2064 cpu_asysc_enable(void)
2067 2065 {
2068 2066 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2069 2067 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2070 2068
2071 2069 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2072 2070 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2073 2071 }
2074 2072
2075 2073 static void
2076 2074 cpu_asysc_disable(void)
2077 2075 {
2078 2076 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2079 2077 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2080 2078
2081 2079 /*
2082 2080 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2083 2081 * executing syscall or sysret with this bit off will incur a #ud trap.
2084 2082 */
2085 2083 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2086 2084 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2087 2085 }
|
↓ open down ↓ |
1907 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX