1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2016 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 */
33
34 #include <sys/types.h>
35 #include <sys/thread.h>
36 #include <sys/cpuvar.h>
37 #include <sys/cpu.h>
38 #include <sys/t_lock.h>
39 #include <sys/param.h>
40 #include <sys/proc.h>
41 #include <sys/disp.h>
42 #include <sys/class.h>
43 #include <sys/cmn_err.h>
44 #include <sys/debug.h>
45 #include <sys/note.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/x_call.h>
48 #include <sys/systm.h>
49 #include <sys/var.h>
50 #include <sys/vtrace.h>
51 #include <vm/hat.h>
52 #include <vm/as.h>
53 #include <vm/seg_kmem.h>
54 #include <vm/seg_kp.h>
55 #include <sys/segments.h>
56 #include <sys/kmem.h>
57 #include <sys/stack.h>
58 #include <sys/smp_impldefs.h>
59 #include <sys/x86_archext.h>
60 #include <sys/machsystm.h>
61 #include <sys/traptrace.h>
62 #include <sys/clock.h>
63 #include <sys/cpc_impl.h>
64 #include <sys/pg.h>
65 #include <sys/cmt.h>
66 #include <sys/dtrace.h>
67 #include <sys/archsystm.h>
68 #include <sys/fp.h>
69 #include <sys/reboot.h>
70 #include <sys/kdi_machimpl.h>
71 #include <vm/hat_i86.h>
72 #include <vm/vm_dep.h>
73 #include <sys/memnode.h>
74 #include <sys/pci_cfgspace.h>
75 #include <sys/mach_mmu.h>
76 #include <sys/sysmacros.h>
77 #if defined(__xpv)
78 #include <sys/hypervisor.h>
79 #endif
80 #include <sys/cpu_module.h>
81 #include <sys/ontrap.h>
82
83 struct cpu cpus[1]; /* CPU data */
84 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
85 struct cpu *cpu_free_list; /* list for released CPUs */
86 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
87
88 #define cpu_next_free cpu_prev
89
90 /*
91 * Useful for disabling MP bring-up on a MP capable system.
92 */
93 int use_mp = 1;
94
95 /*
96 * to be set by a PSM to indicate what cpus
97 * are sitting around on the system.
98 */
99 cpuset_t mp_cpus;
100
101 /*
102 * This variable is used by the hat layer to decide whether or not
103 * critical sections are needed to prevent race conditions. For sun4m,
104 * this variable is set once enough MP initialization has been done in
105 * order to allow cross calls.
106 */
107 int flushes_require_xcalls;
108
109 cpuset_t cpu_ready_set; /* initialized in startup() */
110
111 static void mp_startup_boot(void);
112 static void mp_startup_hotplug(void);
113
114 static void cpu_sep_enable(void);
115 static void cpu_sep_disable(void);
116 static void cpu_asysc_enable(void);
117 static void cpu_asysc_disable(void);
118
119 /*
120 * Init CPU info - get CPU type info for processor_info system call.
121 */
122 void
123 init_cpu_info(struct cpu *cp)
124 {
125 processor_info_t *pi = &cp->cpu_type_info;
126
127 /*
128 * Get clock-frequency property for the CPU.
129 */
130 pi->pi_clock = cpu_freq;
131
132 /*
133 * Current frequency in Hz.
134 */
135 cp->cpu_curr_clock = cpu_freq_hz;
136
137 /*
138 * Supported frequencies.
139 */
140 if (cp->cpu_supp_freqs == NULL) {
141 cpu_set_supp_freqs(cp, NULL);
142 }
143
144 (void) strcpy(pi->pi_processor_type, "i386");
145 if (fpu_exists)
146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
147
148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150
151 /*
152 * If called for the BSP, cp is equal to current CPU.
153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 * has been invoked on target CPU.
157 */
158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
160 }
161
162 /*
163 * Configure syscall support on this CPU.
164 */
165 /*ARGSUSED*/
166 void
167 init_cpu_syscall(struct cpu *cp)
168 {
169 uint64_t flags;
170
171 kpreempt_disable();
172
173 #if defined(__amd64)
174 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
175 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
176 uint64_t flags;
177
178 #if !defined(__lint)
179 /*
180 * The syscall instruction imposes a certain ordering on
181 * segment selectors, so we double-check that ordering
182 * here.
183 */
184 ASSERT(KDS_SEL == KCS_SEL + 8);
185 ASSERT(UDS_SEL == U32CS_SEL + 8);
186 ASSERT(UCS_SEL == U32CS_SEL + 16);
187 #endif
188 /*
189 * Turn syscall/sysret extensions on.
190 */
191 cpu_asysc_enable();
192
193 /*
194 * Program the magic registers ..
195 */
196 wrmsr(MSR_AMD_STAR,
197 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
198 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
199 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
200
201 /*
202 * This list of flags is masked off the incoming
203 * %rfl when we enter the kernel.
204 */
205 flags = PS_IE | PS_T;
206 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
207 flags |= PS_ACHK;
208 wrmsr(MSR_AMD_SFMASK, flags);
209 }
210 #endif
211
212 /*
213 * On 32-bit kernels, we use sysenter/sysexit because it's too
214 * hard to use syscall/sysret, and it is more portable anyway.
215 *
216 * On 64-bit kernels on Nocona machines, the 32-bit syscall
217 * variant isn't available to 32-bit applications, but sysenter is.
218 */
219 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
220 is_x86_feature(x86_featureset, X86FSET_SEP)) {
221
222 #if !defined(__lint)
223 /*
224 * The sysenter instruction imposes a certain ordering on
225 * segment selectors, so we double-check that ordering
226 * here. See "sysenter" in Intel document 245471-012, "IA-32
227 * Intel Architecture Software Developer's Manual Volume 2:
228 * Instruction Set Reference"
229 */
230 ASSERT(KDS_SEL == KCS_SEL + 8);
231
232 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
233 ASSERT32(UDS_SEL == UCS_SEL + 8);
234
235 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
236 ASSERT64(UDS_SEL == U32CS_SEL + 8);
237 #endif
238
239 cpu_sep_enable();
240
241 /*
242 * resume() sets this value to the base of the threads stack
243 * via a context handler.
244 */
245 wrmsr(MSR_INTC_SEP_ESP, 0);
246 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
247 }
248
249 kpreempt_enable();
250 }
251
252 #if !defined(__xpv)
253 /*
254 * Configure per-cpu ID GDT
255 */
256 static void
257 init_cpu_id_gdt(struct cpu *cp)
258 {
259 /* Write cpu_id into limit field of GDT for usermode retrieval */
260 #if defined(__amd64)
261 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
262 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
263 #elif defined(__i386)
264 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
265 SEL_UPL, SDP_BYTES, SDP_OP32);
266 #endif
267 }
268 #endif /* !defined(__xpv) */
269
270 /*
271 * Multiprocessor initialization.
272 *
273 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
274 * startup and idle threads for the specified CPU.
275 * Parameter boot is true for boot time operations and is false for CPU
276 * DR operations.
277 */
278 static struct cpu *
279 mp_cpu_configure_common(int cpun, boolean_t boot)
280 {
281 struct cpu *cp;
282 kthread_id_t tp;
283 caddr_t sp;
284 proc_t *procp;
285 #if !defined(__xpv)
286 extern int idle_cpu_prefer_mwait;
287 extern void cpu_idle_mwait();
288 #endif
289 extern void idle();
290 extern void cpu_idle();
291
292 #ifdef TRAPTRACE
293 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
294 #endif
295
296 ASSERT(MUTEX_HELD(&cpu_lock));
297 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
298
299 if (cpu_free_list == NULL) {
300 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
301 } else {
302 cp = cpu_free_list;
303 cpu_free_list = cp->cpu_next_free;
304 }
305
306 cp->cpu_m.mcpu_istamp = cpun << 16;
307
308 /* Create per CPU specific threads in the process p0. */
309 procp = &p0;
310
311 /*
312 * Initialize the dispatcher first.
313 */
314 disp_cpu_init(cp);
315
316 cpu_vm_data_init(cp);
317
318 /*
319 * Allocate and initialize the startup thread for this CPU.
320 * Interrupt and process switch stacks get allocated later
321 * when the CPU starts running.
322 */
323 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
324 TS_STOPPED, maxclsyspri);
325
326 /*
327 * Set state to TS_ONPROC since this thread will start running
328 * as soon as the CPU comes online.
329 *
330 * All the other fields of the thread structure are setup by
331 * thread_create().
332 */
333 THREAD_ONPROC(tp, cp);
334 tp->t_preempt = 1;
335 tp->t_bound_cpu = cp;
336 tp->t_affinitycnt = 1;
337 tp->t_cpu = cp;
338 tp->t_disp_queue = cp->cpu_disp;
339
340 /*
341 * Setup thread to start in mp_startup_common.
342 */
343 sp = tp->t_stk;
344 tp->t_sp = (uintptr_t)(sp - MINFRAME);
345 #if defined(__amd64)
346 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
347 #endif
348 /*
349 * Setup thread start entry point for boot or hotplug.
350 */
351 if (boot) {
352 tp->t_pc = (uintptr_t)mp_startup_boot;
353 } else {
354 tp->t_pc = (uintptr_t)mp_startup_hotplug;
355 }
356
357 cp->cpu_id = cpun;
358 cp->cpu_self = cp;
359 cp->cpu_thread = tp;
360 cp->cpu_lwp = NULL;
361 cp->cpu_dispthread = tp;
362 cp->cpu_dispatch_pri = DISP_PRIO(tp);
363
364 /*
365 * cpu_base_spl must be set explicitly here to prevent any blocking
366 * operations in mp_startup_common from causing the spl of the cpu
367 * to drop to 0 (allowing device interrupts before we're ready) in
368 * resume().
369 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
370 * As an extra bit of security on DEBUG kernels, this is enforced with
371 * an assertion in mp_startup_common() -- before cpu_base_spl is set
372 * to its proper value.
373 */
374 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
375
376 /*
377 * Now, initialize per-CPU idle thread for this CPU.
378 */
379 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
380
381 cp->cpu_idle_thread = tp;
382
383 tp->t_preempt = 1;
384 tp->t_bound_cpu = cp;
385 tp->t_affinitycnt = 1;
386 tp->t_cpu = cp;
387 tp->t_disp_queue = cp->cpu_disp;
388
389 /*
390 * Bootstrap the CPU's PG data
391 */
392 pg_cpu_bootstrap(cp);
393
394 /*
395 * Perform CPC initialization on the new CPU.
396 */
397 kcpc_hw_init(cp);
398
399 /*
400 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
401 * for each CPU.
402 */
403 setup_vaddr_for_ppcopy(cp);
404
405 /*
406 * Allocate page for new GDT and initialize from current GDT.
407 */
408 #if !defined(__lint)
409 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
410 #endif
411 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
412 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
413
414 #if defined(__i386)
415 /*
416 * setup kernel %gs.
417 */
418 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
419 SEL_KPL, 0, 1);
420 #endif
421
422 /*
423 * If we have more than one node, each cpu gets a copy of IDT
424 * local to its node. If this is a Pentium box, we use cpu 0's
425 * IDT. cpu 0's IDT has been made read-only to workaround the
426 * cmpxchgl register bug
427 */
428 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
429 #if !defined(__lint)
430 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
431 #endif
432 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
433 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
434 } else {
435 cp->cpu_idt = CPU->cpu_idt;
436 }
437
438 /*
439 * alloc space for cpuid info
440 */
441 cpuid_alloc_space(cp);
442 #if !defined(__xpv)
443 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
444 idle_cpu_prefer_mwait) {
445 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
446 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
447 } else
448 #endif
449 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
450
451 init_cpu_info(cp);
452
453 #if !defined(__xpv)
454 init_cpu_id_gdt(cp);
455 #endif
456
457 /*
458 * alloc space for ucode_info
459 */
460 ucode_alloc_space(cp);
461 xc_init_cpu(cp);
462 hat_cpu_online(cp);
463
464 #ifdef TRAPTRACE
465 /*
466 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
467 */
468 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
469 ttc->ttc_next = ttc->ttc_first;
470 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
471 #endif
472
473 /*
474 * Record that we have another CPU.
475 */
476 /*
477 * Initialize the interrupt threads for this CPU
478 */
479 cpu_intr_alloc(cp, NINTR_THREADS);
480
481 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
482 cpu_set_state(cp);
483
484 /*
485 * Add CPU to list of available CPUs. It'll be on the active list
486 * after mp_startup_common().
487 */
488 cpu_add_unit(cp);
489
490 return (cp);
491 }
492
493 /*
494 * Undo what was done in mp_cpu_configure_common
495 */
496 static void
497 mp_cpu_unconfigure_common(struct cpu *cp, int error)
498 {
499 ASSERT(MUTEX_HELD(&cpu_lock));
500
501 /*
502 * Remove the CPU from the list of available CPUs.
503 */
504 cpu_del_unit(cp->cpu_id);
505
506 if (error == ETIMEDOUT) {
507 /*
508 * The cpu was started, but never *seemed* to run any
509 * code in the kernel; it's probably off spinning in its
510 * own private world, though with potential references to
511 * our kmem-allocated IDTs and GDTs (for example).
512 *
513 * Worse still, it may actually wake up some time later,
514 * so rather than guess what it might or might not do, we
515 * leave the fundamental data structures intact.
516 */
517 cp->cpu_flags = 0;
518 return;
519 }
520
521 /*
522 * At this point, the only threads bound to this CPU should
523 * special per-cpu threads: it's idle thread, it's pause threads,
524 * and it's interrupt threads. Clean these up.
525 */
526 cpu_destroy_bound_threads(cp);
527 cp->cpu_idle_thread = NULL;
528
529 /*
530 * Free the interrupt stack.
531 */
532 segkp_release(segkp,
533 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
534 cp->cpu_intr_stack = NULL;
535
536 #ifdef TRAPTRACE
537 /*
538 * Discard the trap trace buffer
539 */
540 {
541 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
542
543 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
544 ttc->ttc_first = NULL;
545 }
546 #endif
547
548 hat_cpu_offline(cp);
549
550 ucode_free_space(cp);
551
552 /* Free CPU ID string and brand string. */
553 if (cp->cpu_idstr) {
554 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
555 cp->cpu_idstr = NULL;
556 }
557 if (cp->cpu_brandstr) {
558 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
559 cp->cpu_brandstr = NULL;
560 }
561
562 #if !defined(__xpv)
563 if (cp->cpu_m.mcpu_mwait != NULL) {
564 cpuid_mwait_free(cp);
565 cp->cpu_m.mcpu_mwait = NULL;
566 }
567 #endif
568 cpuid_free_space(cp);
569
570 if (cp->cpu_idt != CPU->cpu_idt)
571 kmem_free(cp->cpu_idt, PAGESIZE);
572 cp->cpu_idt = NULL;
573
574 kmem_free(cp->cpu_gdt, PAGESIZE);
575 cp->cpu_gdt = NULL;
576
577 if (cp->cpu_supp_freqs != NULL) {
578 size_t len = strlen(cp->cpu_supp_freqs) + 1;
579 kmem_free(cp->cpu_supp_freqs, len);
580 cp->cpu_supp_freqs = NULL;
581 }
582
583 teardown_vaddr_for_ppcopy(cp);
584
585 kcpc_hw_fini(cp);
586
587 cp->cpu_dispthread = NULL;
588 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
589
590 cpu_vm_data_destroy(cp);
591
592 xc_fini_cpu(cp);
593 disp_cpu_fini(cp);
594
595 ASSERT(cp != CPU0);
596 bzero(cp, sizeof (*cp));
597 cp->cpu_next_free = cpu_free_list;
598 cpu_free_list = cp;
599 }
600
601 /*
602 * Apply workarounds for known errata, and warn about those that are absent.
603 *
604 * System vendors occasionally create configurations which contain different
605 * revisions of the CPUs that are almost but not exactly the same. At the
606 * time of writing, this meant that their clock rates were the same, their
607 * feature sets were the same, but the required workaround were -not-
608 * necessarily the same. So, this routine is invoked on -every- CPU soon
609 * after starting to make sure that the resulting system contains the most
610 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
611 * system.
612 *
613 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
614 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
615 * prior to acknowledging their readiness to the master, so this routine will
616 * never be executed by multiple CPUs in parallel, thus making updates to
617 * global data safe.
618 *
619 * These workarounds are based on Rev 3.57 of the Revision Guide for
620 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
621 */
622
623 #if defined(OPTERON_ERRATUM_88)
624 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
625 #endif
626
627 #if defined(OPTERON_ERRATUM_91)
628 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
629 #endif
630
631 #if defined(OPTERON_ERRATUM_93)
632 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
633 #endif
634
635 #if defined(OPTERON_ERRATUM_95)
636 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
637 #endif
638
639 #if defined(OPTERON_ERRATUM_100)
640 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
641 #endif
642
643 #if defined(OPTERON_ERRATUM_108)
644 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
645 #endif
646
647 #if defined(OPTERON_ERRATUM_109)
648 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
649 #endif
650
651 #if defined(OPTERON_ERRATUM_121)
652 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
653 #endif
654
655 #if defined(OPTERON_ERRATUM_122)
656 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
657 #endif
658
659 #if defined(OPTERON_ERRATUM_123)
660 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
661 #endif
662
663 #if defined(OPTERON_ERRATUM_131)
664 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
665 #endif
666
667 #if defined(OPTERON_WORKAROUND_6336786)
668 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
669 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
670 #endif
671
672 #if defined(OPTERON_WORKAROUND_6323525)
673 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
674 #endif
675
676 #if defined(OPTERON_ERRATUM_298)
677 int opteron_erratum_298;
678 #endif
679
680 #if defined(OPTERON_ERRATUM_721)
681 int opteron_erratum_721;
682 #endif
683
684 static void
685 workaround_warning(cpu_t *cp, uint_t erratum)
686 {
687 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
688 cp->cpu_id, erratum);
689 }
690
691 static void
692 workaround_applied(uint_t erratum)
693 {
694 if (erratum > 1000000)
695 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
696 erratum);
697 else
698 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
699 erratum);
700 }
701
702 static void
703 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
704 {
705 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
706 cp->cpu_id, rw, msr, error);
707 }
708
709 /*
710 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
711 * system.
712 */
713 static uint_t
714 opteron_get_nnodes(void)
715 {
716 static uint_t nnodes = 0;
717
718 if (nnodes == 0) {
719 #ifdef DEBUG
720 uint_t family;
721
722 /*
723 * This routine uses a PCI config space based mechanism
724 * for retrieving the number of nodes in the system.
725 * Device 24, function 0, offset 0x60 as used here is not
726 * AMD processor architectural, and may not work on processor
727 * families other than those listed below.
728 *
729 * Callers of this routine must ensure that we're running on
730 * a processor which supports this mechanism.
731 * The assertion below is meant to catch calls on unsupported
732 * processors.
733 */
734 family = cpuid_getfamily(CPU);
735 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
736 #endif /* DEBUG */
737
738 /*
739 * Obtain the number of nodes in the system from
740 * bits [6:4] of the Node ID register on node 0.
741 *
742 * The actual node count is NodeID[6:4] + 1
743 *
744 * The Node ID register is accessed via function 0,
745 * offset 0x60. Node 0 is device 24.
746 */
747 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
748 }
749 return (nnodes);
750 }
751
752 uint_t
753 do_erratum_298(struct cpu *cpu)
754 {
755 static int osvwrc = -3;
756 extern int osvw_opteron_erratum(cpu_t *, uint_t);
757
758 /*
759 * L2 Eviction May Occur During Processor Operation To Set
760 * Accessed or Dirty Bit.
761 */
762 if (osvwrc == -3) {
763 osvwrc = osvw_opteron_erratum(cpu, 298);
764 } else {
765 /* osvw return codes should be consistent for all cpus */
766 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
767 }
768
769 switch (osvwrc) {
770 case 0: /* erratum is not present: do nothing */
771 break;
772 case 1: /* erratum is present: BIOS workaround applied */
773 /*
774 * check if workaround is actually in place and issue warning
775 * if not.
776 */
777 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
778 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
779 #if defined(OPTERON_ERRATUM_298)
780 opteron_erratum_298++;
781 #else
782 workaround_warning(cpu, 298);
783 return (1);
784 #endif
785 }
786 break;
787 case -1: /* cannot determine via osvw: check cpuid */
788 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
789 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
790 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
791 #if defined(OPTERON_ERRATUM_298)
792 opteron_erratum_298++;
793 #else
794 workaround_warning(cpu, 298);
795 return (1);
796 #endif
797 }
798 break;
799 }
800 return (0);
801 }
802
803 uint_t
804 workaround_errata(struct cpu *cpu)
805 {
806 uint_t missing = 0;
807
808 ASSERT(cpu == CPU);
809
810 /*LINTED*/
811 if (cpuid_opteron_erratum(cpu, 88) > 0) {
812 /*
813 * SWAPGS May Fail To Read Correct GS Base
814 */
815 #if defined(OPTERON_ERRATUM_88)
816 /*
817 * The workaround is an mfence in the relevant assembler code
818 */
819 opteron_erratum_88++;
820 #else
821 workaround_warning(cpu, 88);
822 missing++;
823 #endif
824 }
825
826 if (cpuid_opteron_erratum(cpu, 91) > 0) {
827 /*
828 * Software Prefetches May Report A Page Fault
829 */
830 #if defined(OPTERON_ERRATUM_91)
831 /*
832 * fix is in trap.c
833 */
834 opteron_erratum_91++;
835 #else
836 workaround_warning(cpu, 91);
837 missing++;
838 #endif
839 }
840
841 if (cpuid_opteron_erratum(cpu, 93) > 0) {
842 /*
843 * RSM Auto-Halt Restart Returns to Incorrect RIP
844 */
845 #if defined(OPTERON_ERRATUM_93)
846 /*
847 * fix is in trap.c
848 */
849 opteron_erratum_93++;
850 #else
851 workaround_warning(cpu, 93);
852 missing++;
853 #endif
854 }
855
856 /*LINTED*/
857 if (cpuid_opteron_erratum(cpu, 95) > 0) {
858 /*
859 * RET Instruction May Return to Incorrect EIP
860 */
861 #if defined(OPTERON_ERRATUM_95)
862 #if defined(_LP64)
863 /*
864 * Workaround this by ensuring that 32-bit user code and
865 * 64-bit kernel code never occupy the same address
866 * range mod 4G.
867 */
868 if (_userlimit32 > 0xc0000000ul)
869 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
870
871 /*LINTED*/
872 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
873 opteron_erratum_95++;
874 #endif /* _LP64 */
875 #else
876 workaround_warning(cpu, 95);
877 missing++;
878 #endif
879 }
880
881 if (cpuid_opteron_erratum(cpu, 100) > 0) {
882 /*
883 * Compatibility Mode Branches Transfer to Illegal Address
884 */
885 #if defined(OPTERON_ERRATUM_100)
886 /*
887 * fix is in trap.c
888 */
889 opteron_erratum_100++;
890 #else
891 workaround_warning(cpu, 100);
892 missing++;
893 #endif
894 }
895
896 /*LINTED*/
897 if (cpuid_opteron_erratum(cpu, 108) > 0) {
898 /*
899 * CPUID Instruction May Return Incorrect Model Number In
900 * Some Processors
901 */
902 #if defined(OPTERON_ERRATUM_108)
903 /*
904 * (Our cpuid-handling code corrects the model number on
905 * those processors)
906 */
907 #else
908 workaround_warning(cpu, 108);
909 missing++;
910 #endif
911 }
912
913 /*LINTED*/
914 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
915 /*
916 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
917 */
918 #if defined(OPTERON_ERRATUM_109)
919 /*
920 * The "workaround" is to print a warning to upgrade the BIOS
921 */
922 uint64_t value;
923 const uint_t msr = MSR_AMD_PATCHLEVEL;
924 int err;
925
926 if ((err = checked_rdmsr(msr, &value)) != 0) {
927 msr_warning(cpu, "rd", msr, err);
928 workaround_warning(cpu, 109);
929 missing++;
930 }
931 if (value == 0)
932 opteron_erratum_109++;
933 #else
934 workaround_warning(cpu, 109);
935 missing++;
936 #endif
937 /*CONSTANTCONDITION*/
938 } while (0);
939
940 /*LINTED*/
941 if (cpuid_opteron_erratum(cpu, 121) > 0) {
942 /*
943 * Sequential Execution Across Non_Canonical Boundary Caused
944 * Processor Hang
945 */
946 #if defined(OPTERON_ERRATUM_121)
947 #if defined(_LP64)
948 /*
949 * Erratum 121 is only present in long (64 bit) mode.
950 * Workaround is to include the page immediately before the
951 * va hole to eliminate the possibility of system hangs due to
952 * sequential execution across the va hole boundary.
953 */
954 if (opteron_erratum_121)
955 opteron_erratum_121++;
956 else {
957 if (hole_start) {
958 hole_start -= PAGESIZE;
959 } else {
960 /*
961 * hole_start not yet initialized by
962 * mmu_init. Initialize hole_start
963 * with value to be subtracted.
964 */
965 hole_start = PAGESIZE;
966 }
967 opteron_erratum_121++;
968 }
969 #endif /* _LP64 */
970 #else
971 workaround_warning(cpu, 121);
972 missing++;
973 #endif
974 }
975
976 /*LINTED*/
977 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
978 /*
979 * TLB Flush Filter May Cause Coherency Problem in
980 * Multiprocessor Systems
981 */
982 #if defined(OPTERON_ERRATUM_122)
983 uint64_t value;
984 const uint_t msr = MSR_AMD_HWCR;
985 int error;
986
987 /*
988 * Erratum 122 is only present in MP configurations (multi-core
989 * or multi-processor).
990 */
991 #if defined(__xpv)
992 if (!DOMAIN_IS_INITDOMAIN(xen_info))
993 break;
994 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
995 break;
996 #else
997 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
998 cpuid_get_ncpu_per_chip(cpu) == 1)
999 break;
1000 #endif
1001 /* disable TLB Flush Filter */
1002
1003 if ((error = checked_rdmsr(msr, &value)) != 0) {
1004 msr_warning(cpu, "rd", msr, error);
1005 workaround_warning(cpu, 122);
1006 missing++;
1007 } else {
1008 value |= (uint64_t)AMD_HWCR_FFDIS;
1009 if ((error = checked_wrmsr(msr, value)) != 0) {
1010 msr_warning(cpu, "wr", msr, error);
1011 workaround_warning(cpu, 122);
1012 missing++;
1013 }
1014 }
1015 opteron_erratum_122++;
1016 #else
1017 workaround_warning(cpu, 122);
1018 missing++;
1019 #endif
1020 /*CONSTANTCONDITION*/
1021 } while (0);
1022
1023 /*LINTED*/
1024 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1025 /*
1026 * Bypassed Reads May Cause Data Corruption of System Hang in
1027 * Dual Core Processors
1028 */
1029 #if defined(OPTERON_ERRATUM_123)
1030 uint64_t value;
1031 const uint_t msr = MSR_AMD_PATCHLEVEL;
1032 int err;
1033
1034 /*
1035 * Erratum 123 applies only to multi-core cpus.
1036 */
1037 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1038 break;
1039 #if defined(__xpv)
1040 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1041 break;
1042 #endif
1043 /*
1044 * The "workaround" is to print a warning to upgrade the BIOS
1045 */
1046 if ((err = checked_rdmsr(msr, &value)) != 0) {
1047 msr_warning(cpu, "rd", msr, err);
1048 workaround_warning(cpu, 123);
1049 missing++;
1050 }
1051 if (value == 0)
1052 opteron_erratum_123++;
1053 #else
1054 workaround_warning(cpu, 123);
1055 missing++;
1056
1057 #endif
1058 /*CONSTANTCONDITION*/
1059 } while (0);
1060
1061 /*LINTED*/
1062 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1063 /*
1064 * Multiprocessor Systems with Four or More Cores May Deadlock
1065 * Waiting for a Probe Response
1066 */
1067 #if defined(OPTERON_ERRATUM_131)
1068 uint64_t nbcfg;
1069 const uint_t msr = MSR_AMD_NB_CFG;
1070 const uint64_t wabits =
1071 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1072 int error;
1073
1074 /*
1075 * Erratum 131 applies to any system with four or more cores.
1076 */
1077 if (opteron_erratum_131)
1078 break;
1079 #if defined(__xpv)
1080 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1081 break;
1082 if (xpv_nr_phys_cpus() < 4)
1083 break;
1084 #else
1085 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1086 break;
1087 #endif
1088 /*
1089 * Print a warning if neither of the workarounds for
1090 * erratum 131 is present.
1091 */
1092 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1093 msr_warning(cpu, "rd", msr, error);
1094 workaround_warning(cpu, 131);
1095 missing++;
1096 } else if ((nbcfg & wabits) == 0) {
1097 opteron_erratum_131++;
1098 } else {
1099 /* cannot have both workarounds set */
1100 ASSERT((nbcfg & wabits) != wabits);
1101 }
1102 #else
1103 workaround_warning(cpu, 131);
1104 missing++;
1105 #endif
1106 /*CONSTANTCONDITION*/
1107 } while (0);
1108
1109 /*
1110 * This isn't really an erratum, but for convenience the
1111 * detection/workaround code lives here and in cpuid_opteron_erratum.
1112 */
1113 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1114 #if defined(OPTERON_WORKAROUND_6336786)
1115 /*
1116 * Disable C1-Clock ramping on multi-core/multi-processor
1117 * K8 platforms to guard against TSC drift.
1118 */
1119 if (opteron_workaround_6336786) {
1120 opteron_workaround_6336786++;
1121 #if defined(__xpv)
1122 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1123 xpv_nr_phys_cpus() > 1) ||
1124 opteron_workaround_6336786_UP) {
1125 /*
1126 * XXPV Hmm. We can't walk the Northbridges on
1127 * the hypervisor; so just complain and drive
1128 * on. This probably needs to be fixed in
1129 * the hypervisor itself.
1130 */
1131 opteron_workaround_6336786++;
1132 workaround_warning(cpu, 6336786);
1133 #else /* __xpv */
1134 } else if ((opteron_get_nnodes() *
1135 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1136 opteron_workaround_6336786_UP) {
1137
1138 uint_t node, nnodes;
1139 uint8_t data;
1140
1141 nnodes = opteron_get_nnodes();
1142 for (node = 0; node < nnodes; node++) {
1143 /*
1144 * Clear PMM7[1:0] (function 3, offset 0x87)
1145 * Northbridge device is the node id + 24.
1146 */
1147 data = pci_getb_func(0, node + 24, 3, 0x87);
1148 data &= 0xFC;
1149 pci_putb_func(0, node + 24, 3, 0x87, data);
1150 }
1151 opteron_workaround_6336786++;
1152 #endif /* __xpv */
1153 }
1154 #else
1155 workaround_warning(cpu, 6336786);
1156 missing++;
1157 #endif
1158 }
1159
1160 /*LINTED*/
1161 /*
1162 * Mutex primitives don't work as expected.
1163 */
1164 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1165 #if defined(OPTERON_WORKAROUND_6323525)
1166 /*
1167 * This problem only occurs with 2 or more cores. If bit in
1168 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1169 * is to patch the semaphone routines with the lfence
1170 * instruction to provide necessary load memory barrier with
1171 * possible subsequent read-modify-write ops.
1172 *
1173 * It is too early in boot to call the patch routine so
1174 * set erratum variable to be done in startup_end().
1175 */
1176 if (opteron_workaround_6323525) {
1177 opteron_workaround_6323525++;
1178 #if defined(__xpv)
1179 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1180 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1181 /*
1182 * XXPV Use dom0_msr here when extended
1183 * operations are supported?
1184 */
1185 if (xpv_nr_phys_cpus() > 1)
1186 opteron_workaround_6323525++;
1187 } else {
1188 /*
1189 * We have no way to tell how many physical
1190 * cpus there are, or even if this processor
1191 * has the problem, so enable the workaround
1192 * unconditionally (at some performance cost).
1193 */
1194 opteron_workaround_6323525++;
1195 }
1196 #else /* __xpv */
1197 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1198 ((opteron_get_nnodes() *
1199 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1200 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1201 opteron_workaround_6323525++;
1202 #endif /* __xpv */
1203 }
1204 #else
1205 workaround_warning(cpu, 6323525);
1206 missing++;
1207 #endif
1208 }
1209
1210 missing += do_erratum_298(cpu);
1211
1212 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1213 #if defined(OPTERON_ERRATUM_721)
1214 on_trap_data_t otd;
1215
1216 if (!on_trap(&otd, OT_DATA_ACCESS))
1217 wrmsr(MSR_AMD_DE_CFG,
1218 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1219 no_trap();
1220
1221 opteron_erratum_721++;
1222 #else
1223 workaround_warning(cpu, 721);
1224 missing++;
1225 #endif
1226 }
1227
1228 #ifdef __xpv
1229 return (0);
1230 #else
1231 return (missing);
1232 #endif
1233 }
1234
1235 void
1236 workaround_errata_end()
1237 {
1238 #if defined(OPTERON_ERRATUM_88)
1239 if (opteron_erratum_88)
1240 workaround_applied(88);
1241 #endif
1242 #if defined(OPTERON_ERRATUM_91)
1243 if (opteron_erratum_91)
1244 workaround_applied(91);
1245 #endif
1246 #if defined(OPTERON_ERRATUM_93)
1247 if (opteron_erratum_93)
1248 workaround_applied(93);
1249 #endif
1250 #if defined(OPTERON_ERRATUM_95)
1251 if (opteron_erratum_95)
1252 workaround_applied(95);
1253 #endif
1254 #if defined(OPTERON_ERRATUM_100)
1255 if (opteron_erratum_100)
1256 workaround_applied(100);
1257 #endif
1258 #if defined(OPTERON_ERRATUM_108)
1259 if (opteron_erratum_108)
1260 workaround_applied(108);
1261 #endif
1262 #if defined(OPTERON_ERRATUM_109)
1263 if (opteron_erratum_109) {
1264 cmn_err(CE_WARN,
1265 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1266 " processor\nerratum 109 was not detected; updating your"
1267 " system's BIOS to a version\ncontaining this"
1268 " microcode patch is HIGHLY recommended or erroneous"
1269 " system\noperation may occur.\n");
1270 }
1271 #endif
1272 #if defined(OPTERON_ERRATUM_121)
1273 if (opteron_erratum_121)
1274 workaround_applied(121);
1275 #endif
1276 #if defined(OPTERON_ERRATUM_122)
1277 if (opteron_erratum_122)
1278 workaround_applied(122);
1279 #endif
1280 #if defined(OPTERON_ERRATUM_123)
1281 if (opteron_erratum_123) {
1282 cmn_err(CE_WARN,
1283 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1284 " processor\nerratum 123 was not detected; updating your"
1285 " system's BIOS to a version\ncontaining this"
1286 " microcode patch is HIGHLY recommended or erroneous"
1287 " system\noperation may occur.\n");
1288 }
1289 #endif
1290 #if defined(OPTERON_ERRATUM_131)
1291 if (opteron_erratum_131) {
1292 cmn_err(CE_WARN,
1293 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1294 " processor\nerratum 131 was not detected; updating your"
1295 " system's BIOS to a version\ncontaining this"
1296 " microcode patch is HIGHLY recommended or erroneous"
1297 " system\noperation may occur.\n");
1298 }
1299 #endif
1300 #if defined(OPTERON_WORKAROUND_6336786)
1301 if (opteron_workaround_6336786)
1302 workaround_applied(6336786);
1303 #endif
1304 #if defined(OPTERON_WORKAROUND_6323525)
1305 if (opteron_workaround_6323525)
1306 workaround_applied(6323525);
1307 #endif
1308 #if defined(OPTERON_ERRATUM_298)
1309 if (opteron_erratum_298) {
1310 cmn_err(CE_WARN,
1311 "BIOS microcode patch for AMD 64/Opteron(tm)"
1312 " processor\nerratum 298 was not detected; updating your"
1313 " system's BIOS to a version\ncontaining this"
1314 " microcode patch is HIGHLY recommended or erroneous"
1315 " system\noperation may occur.\n");
1316 }
1317 #endif
1318 #if defined(OPTERON_ERRATUM_721)
1319 if (opteron_erratum_721)
1320 workaround_applied(721);
1321 #endif
1322 }
1323
1324 /*
1325 * The procset_slave and procset_master are used to synchronize
1326 * between the control CPU and the target CPU when starting CPUs.
1327 */
1328 static cpuset_t procset_slave, procset_master;
1329
1330 static void
1331 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1332 {
1333 cpuset_t tempset;
1334
1335 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1336 tempset = *(volatile cpuset_t *)sp) {
1337 SMT_PAUSE();
1338 }
1339 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1340 }
1341
1342 static void
1343 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1344 {
1345 cpuset_t tempset;
1346
1347 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1348 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1349 tempset = *(volatile cpuset_t *)sp) {
1350 SMT_PAUSE();
1351 }
1352 }
1353
1354 int
1355 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1356 {
1357 _NOTE(ARGUNUSED(boot));
1358
1359 void *ctx;
1360 int delays;
1361 int error = 0;
1362 cpuset_t tempset;
1363 processorid_t cpuid;
1364 #ifndef __xpv
1365 extern void cpupm_init(cpu_t *);
1366 #endif
1367
1368 ASSERT(cp != NULL);
1369 cpuid = cp->cpu_id;
1370 ctx = mach_cpucontext_alloc(cp);
1371 if (ctx == NULL) {
1372 cmn_err(CE_WARN,
1373 "cpu%d: failed to allocate context", cp->cpu_id);
1374 return (EAGAIN);
1375 }
1376 error = mach_cpu_start(cp, ctx);
1377 if (error != 0) {
1378 cmn_err(CE_WARN,
1379 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1380 mach_cpucontext_free(cp, ctx, error);
1381 return (error);
1382 }
1383
1384 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1385 delays++) {
1386 if (delays == 500) {
1387 /*
1388 * After five seconds, things are probably looking
1389 * a bit bleak - explain the hang.
1390 */
1391 cmn_err(CE_NOTE, "cpu%d: started, "
1392 "but not running in the kernel yet", cpuid);
1393 } else if (delays > 2000) {
1394 /*
1395 * We waited at least 20 seconds, bail ..
1396 */
1397 error = ETIMEDOUT;
1398 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1399 mach_cpucontext_free(cp, ctx, error);
1400 return (error);
1401 }
1402
1403 /*
1404 * wait at least 10ms, then check again..
1405 */
1406 delay(USEC_TO_TICK_ROUNDUP(10000));
1407 tempset = *((volatile cpuset_t *)&procset_slave);
1408 }
1409 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1410
1411 mach_cpucontext_free(cp, ctx, 0);
1412
1413 #ifndef __xpv
1414 if (tsc_gethrtime_enable)
1415 tsc_sync_master(cpuid);
1416 #endif
1417
1418 if (dtrace_cpu_init != NULL) {
1419 (*dtrace_cpu_init)(cpuid);
1420 }
1421
1422 /*
1423 * During CPU DR operations, the cpu_lock is held by current
1424 * (the control) thread. We can't release the cpu_lock here
1425 * because that will break the CPU DR logic.
1426 * On the other hand, CPUPM and processor group initialization
1427 * routines need to access the cpu_lock. So we invoke those
1428 * routines here on behalf of mp_startup_common().
1429 *
1430 * CPUPM and processor group initialization routines depend
1431 * on the cpuid probing results. Wait for mp_startup_common()
1432 * to signal that cpuid probing is done.
1433 */
1434 mp_startup_wait(&procset_slave, cpuid);
1435 #ifndef __xpv
1436 cpupm_init(cp);
1437 #endif
1438 (void) pg_cpu_init(cp, B_FALSE);
1439 cpu_set_state(cp);
1440 mp_startup_signal(&procset_master, cpuid);
1441
1442 return (0);
1443 }
1444
1445 /*
1446 * Start a single cpu, assuming that the kernel context is available
1447 * to successfully start another cpu.
1448 *
1449 * (For example, real mode code is mapped into the right place
1450 * in memory and is ready to be run.)
1451 */
1452 int
1453 start_cpu(processorid_t who)
1454 {
1455 cpu_t *cp;
1456 int error = 0;
1457 cpuset_t tempset;
1458
1459 ASSERT(who != 0);
1460
1461 /*
1462 * Check if there's at least a Mbyte of kmem available
1463 * before attempting to start the cpu.
1464 */
1465 if (kmem_avail() < 1024 * 1024) {
1466 /*
1467 * Kick off a reap in case that helps us with
1468 * later attempts ..
1469 */
1470 kmem_reap();
1471 return (ENOMEM);
1472 }
1473
1474 /*
1475 * First configure cpu.
1476 */
1477 cp = mp_cpu_configure_common(who, B_TRUE);
1478 ASSERT(cp != NULL);
1479
1480 /*
1481 * Then start cpu.
1482 */
1483 error = mp_start_cpu_common(cp, B_TRUE);
1484 if (error != 0) {
1485 mp_cpu_unconfigure_common(cp, error);
1486 return (error);
1487 }
1488
1489 mutex_exit(&cpu_lock);
1490 tempset = cpu_ready_set;
1491 while (!CPU_IN_SET(tempset, who)) {
1492 drv_usecwait(1);
1493 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1494 }
1495 mutex_enter(&cpu_lock);
1496
1497 return (0);
1498 }
1499
1500 void
1501 start_other_cpus(int cprboot)
1502 {
1503 _NOTE(ARGUNUSED(cprboot));
1504
1505 uint_t who;
1506 uint_t bootcpuid = 0;
1507
1508 /*
1509 * Initialize our own cpu_info.
1510 */
1511 init_cpu_info(CPU);
1512
1513 #if !defined(__xpv)
1514 init_cpu_id_gdt(CPU);
1515 #endif
1516
1517 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1518 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1519
1520 /*
1521 * Initialize our syscall handlers
1522 */
1523 init_cpu_syscall(CPU);
1524
1525 /*
1526 * Take the boot cpu out of the mp_cpus set because we know
1527 * it's already running. Add it to the cpu_ready_set for
1528 * precisely the same reason.
1529 */
1530 CPUSET_DEL(mp_cpus, bootcpuid);
1531 CPUSET_ADD(cpu_ready_set, bootcpuid);
1532
1533 /*
1534 * skip the rest of this if
1535 * . only 1 cpu dectected and system isn't hotplug-capable
1536 * . not using MP
1537 */
1538 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1539 use_mp == 0) {
1540 if (use_mp == 0)
1541 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1542 goto done;
1543 }
1544
1545 /*
1546 * perform such initialization as is needed
1547 * to be able to take CPUs on- and off-line.
1548 */
1549 cpu_pause_init();
1550
1551 xc_init_cpu(CPU); /* initialize processor crosscalls */
1552
1553 if (mach_cpucontext_init() != 0)
1554 goto done;
1555
1556 flushes_require_xcalls = 1;
1557
1558 /*
1559 * We lock our affinity to the master CPU to ensure that all slave CPUs
1560 * do their TSC syncs with the same CPU.
1561 */
1562 affinity_set(CPU_CURRENT);
1563
1564 for (who = 0; who < NCPU; who++) {
1565 if (!CPU_IN_SET(mp_cpus, who))
1566 continue;
1567 ASSERT(who != bootcpuid);
1568
1569 mutex_enter(&cpu_lock);
1570 if (start_cpu(who) != 0)
1571 CPUSET_DEL(mp_cpus, who);
1572 cpu_state_change_notify(who, CPU_SETUP);
1573 mutex_exit(&cpu_lock);
1574 }
1575
1576 /* Free the space allocated to hold the microcode file */
1577 ucode_cleanup();
1578
1579 affinity_clear();
1580
1581 mach_cpucontext_fini();
1582
1583 done:
1584 if (get_hwenv() == HW_NATIVE)
1585 workaround_errata_end();
1586 cmi_post_mpstartup();
1587
1588 if (use_mp && ncpus != boot_max_ncpus) {
1589 cmn_err(CE_NOTE,
1590 "System detected %d cpus, but "
1591 "only %d cpu(s) were enabled during boot.",
1592 boot_max_ncpus, ncpus);
1593 cmn_err(CE_NOTE,
1594 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1595 "See eeprom(1M).");
1596 }
1597 }
1598
1599 int
1600 mp_cpu_configure(int cpuid)
1601 {
1602 cpu_t *cp;
1603
1604 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1605 return (ENOTSUP);
1606 }
1607
1608 cp = cpu_get(cpuid);
1609 if (cp != NULL) {
1610 return (EALREADY);
1611 }
1612
1613 /*
1614 * Check if there's at least a Mbyte of kmem available
1615 * before attempting to start the cpu.
1616 */
1617 if (kmem_avail() < 1024 * 1024) {
1618 /*
1619 * Kick off a reap in case that helps us with
1620 * later attempts ..
1621 */
1622 kmem_reap();
1623 return (ENOMEM);
1624 }
1625
1626 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1627 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1628
1629 return (cp != NULL ? 0 : EAGAIN);
1630 }
1631
1632 int
1633 mp_cpu_unconfigure(int cpuid)
1634 {
1635 cpu_t *cp;
1636
1637 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1638 return (ENOTSUP);
1639 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1640 return (EINVAL);
1641 }
1642
1643 cp = cpu_get(cpuid);
1644 if (cp == NULL) {
1645 return (ENODEV);
1646 }
1647 mp_cpu_unconfigure_common(cp, 0);
1648
1649 return (0);
1650 }
1651
1652 /*
1653 * Startup function for 'other' CPUs (besides boot cpu).
1654 * Called from real_mode_start.
1655 *
1656 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1657 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1658 * hat_unload which requires CPU_READY to be set.
1659 */
1660 static void
1661 mp_startup_common(boolean_t boot)
1662 {
1663 cpu_t *cp = CPU;
1664 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1665 extern void cpu_event_init_cpu(cpu_t *);
1666
1667 /*
1668 * We need to get TSC on this proc synced (i.e., any delta
1669 * from cpu0 accounted for) as soon as we can, because many
1670 * many things use gethrtime/pc_gethrestime, including
1671 * interrupts, cmn_err, etc. Before we can do that, we want to
1672 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1673 * right away.
1674 */
1675 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1676 cpuid_pass1(cp, new_x86_featureset);
1677
1678 if (boot && get_hwenv() == HW_NATIVE &&
1679 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1680 cpuid_getfamily(CPU) == 6 &&
1681 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1682 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1683 (void) wrmsr(REG_TSC, 0UL);
1684 }
1685
1686 /* Let the control CPU continue into tsc_sync_master() */
1687 mp_startup_signal(&procset_slave, cp->cpu_id);
1688
1689 #ifndef __xpv
1690 if (tsc_gethrtime_enable)
1691 tsc_sync_slave();
1692 #endif
1693
1694 /*
1695 * Once this was done from assembly, but it's safer here; if
1696 * it blocks, we need to be able to swtch() to and from, and
1697 * since we get here by calling t_pc, we need to do that call
1698 * before swtch() overwrites it.
1699 */
1700 (void) (*ap_mlsetup)();
1701
1702 #ifndef __xpv
1703 /*
1704 * Program this cpu's PAT
1705 */
1706 pat_sync();
1707 #endif
1708
1709 /*
1710 * Set up TSC_AUX to contain the cpuid for this processor
1711 * for the rdtscp instruction.
1712 */
1713 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1714 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1715
1716 /*
1717 * Initialize this CPU's syscall handlers
1718 */
1719 init_cpu_syscall(cp);
1720
1721 /*
1722 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1723 * highest level at which a routine is permitted to block on
1724 * an adaptive mutex (allows for cpu poke interrupt in case
1725 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1726 * device interrupts that may end up in the hat layer issuing cross
1727 * calls before CPU_READY is set.
1728 */
1729 splx(ipltospl(LOCK_LEVEL));
1730 sti();
1731
1732 /*
1733 * Do a sanity check to make sure this new CPU is a sane thing
1734 * to add to the collection of processors running this system.
1735 *
1736 * XXX Clearly this needs to get more sophisticated, if x86
1737 * systems start to get built out of heterogenous CPUs; as is
1738 * likely to happen once the number of processors in a configuration
1739 * gets large enough.
1740 */
1741 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1742 B_FALSE) {
1743 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1744 print_x86_featureset(new_x86_featureset);
1745 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1746 }
1747
1748 /*
1749 * We do not support cpus with mixed monitor/mwait support if the
1750 * boot cpu supports monitor/mwait.
1751 */
1752 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1753 is_x86_feature(new_x86_featureset, X86FSET_MWAIT))
1754 panic("unsupported mixed cpu monitor/mwait support detected");
1755
1756 /*
1757 * We could be more sophisticated here, and just mark the CPU
1758 * as "faulted" but at this point we'll opt for the easier
1759 * answer of dying horribly. Provided the boot cpu is ok,
1760 * the system can be recovered by booting with use_mp set to zero.
1761 */
1762 if (workaround_errata(cp) != 0)
1763 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1764
1765 /*
1766 * We can touch cpu_flags here without acquiring the cpu_lock here
1767 * because the cpu_lock is held by the control CPU which is running
1768 * mp_start_cpu_common().
1769 * Need to clear CPU_QUIESCED flag before calling any function which
1770 * may cause thread context switching, such as kmem_alloc() etc.
1771 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1772 * it's set. So the startup thread may have no chance to switch back
1773 * again if it's switched away with CPU_QUIESCED set.
1774 */
1775 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1776
1777 /*
1778 * Setup this processor for XSAVE.
1779 */
1780 if (fp_save_mech == FP_XSAVE) {
1781 xsave_setup_msr(cp);
1782 }
1783
1784 cpuid_pass2(cp);
1785 cpuid_pass3(cp);
1786 cpuid_pass4(cp, NULL);
1787
1788 /*
1789 * Correct cpu_idstr and cpu_brandstr on target CPU after
1790 * cpuid_pass1() is done.
1791 */
1792 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1793 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1794
1795 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1796
1797 post_startup_cpu_fixups();
1798
1799 cpu_event_init_cpu(cp);
1800
1801 /*
1802 * Enable preemption here so that contention for any locks acquired
1803 * later in mp_startup_common may be preempted if the thread owning
1804 * those locks is continuously executing on other CPUs (for example,
1805 * this CPU must be preemptible to allow other CPUs to pause it during
1806 * their startup phases). It's safe to enable preemption here because
1807 * the CPU state is pretty-much fully constructed.
1808 */
1809 curthread->t_preempt = 0;
1810
1811 /* The base spl should still be at LOCK LEVEL here */
1812 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1813 set_base_spl(); /* Restore the spl to its proper value */
1814
1815 pghw_physid_create(cp);
1816 /*
1817 * Delegate initialization tasks, which need to access the cpu_lock,
1818 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1819 * during CPU DR operations.
1820 */
1821 mp_startup_signal(&procset_slave, cp->cpu_id);
1822 mp_startup_wait(&procset_master, cp->cpu_id);
1823 pg_cmt_cpu_startup(cp);
1824
1825 if (boot) {
1826 mutex_enter(&cpu_lock);
1827 cp->cpu_flags &= ~CPU_OFFLINE;
1828 cpu_enable_intr(cp);
1829 cpu_add_active(cp);
1830 mutex_exit(&cpu_lock);
1831 }
1832
1833 /* Enable interrupts */
1834 (void) spl0();
1835
1836 /*
1837 * Fill out cpu_ucode_info. Update microcode if necessary.
1838 */
1839 ucode_check(cp);
1840
1841 #ifndef __xpv
1842 {
1843 /*
1844 * Set up the CPU module for this CPU. This can't be done
1845 * before this CPU is made CPU_READY, because we may (in
1846 * heterogeneous systems) need to go load another CPU module.
1847 * The act of attempting to load a module may trigger a
1848 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1849 */
1850 cmi_hdl_t hdl;
1851
1852 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1853 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1854 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1855 cmi_mca_init(hdl);
1856 cp->cpu_m.mcpu_cmi_hdl = hdl;
1857 }
1858 }
1859 #endif /* __xpv */
1860
1861 if (boothowto & RB_DEBUG)
1862 kdi_cpu_init();
1863
1864 /*
1865 * Setting the bit in cpu_ready_set must be the last operation in
1866 * processor initialization; the boot CPU will continue to boot once
1867 * it sees this bit set for all active CPUs.
1868 */
1869 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1870
1871 (void) mach_cpu_create_device_node(cp, NULL);
1872
1873 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1874 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1875 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1876 cp->cpu_id);
1877
1878 /*
1879 * Now we are done with the startup thread, so free it up.
1880 */
1881 thread_exit();
1882 panic("mp_startup: cannot return");
1883 /*NOTREACHED*/
1884 }
1885
1886 /*
1887 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1888 */
1889 static void
1890 mp_startup_boot(void)
1891 {
1892 mp_startup_common(B_TRUE);
1893 }
1894
1895 /*
1896 * Startup function for hotplug CPUs at runtime.
1897 */
1898 void
1899 mp_startup_hotplug(void)
1900 {
1901 mp_startup_common(B_FALSE);
1902 }
1903
1904 /*
1905 * Start CPU on user request.
1906 */
1907 /* ARGSUSED */
1908 int
1909 mp_cpu_start(struct cpu *cp)
1910 {
1911 ASSERT(MUTEX_HELD(&cpu_lock));
1912 return (0);
1913 }
1914
1915 /*
1916 * Stop CPU on user request.
1917 */
1918 int
1919 mp_cpu_stop(struct cpu *cp)
1920 {
1921 extern int cbe_psm_timer_mode;
1922 ASSERT(MUTEX_HELD(&cpu_lock));
1923
1924 #ifdef __xpv
1925 /*
1926 * We can't offline vcpu0.
1927 */
1928 if (cp->cpu_id == 0)
1929 return (EBUSY);
1930 #endif
1931
1932 /*
1933 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1934 * can't stop it. (This is true only for machines with no TSC.)
1935 */
1936
1937 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1938 return (EBUSY);
1939
1940 return (0);
1941 }
1942
1943 /*
1944 * Take the specified CPU out of participation in interrupts.
1945 */
1946 int
1947 cpu_disable_intr(struct cpu *cp)
1948 {
1949 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1950 return (EBUSY);
1951
1952 cp->cpu_flags &= ~CPU_ENABLE;
1953 return (0);
1954 }
1955
1956 /*
1957 * Allow the specified CPU to participate in interrupts.
1958 */
1959 void
1960 cpu_enable_intr(struct cpu *cp)
1961 {
1962 ASSERT(MUTEX_HELD(&cpu_lock));
1963 cp->cpu_flags |= CPU_ENABLE;
1964 psm_enable_intr(cp->cpu_id);
1965 }
1966
1967 void
1968 mp_cpu_faulted_enter(struct cpu *cp)
1969 {
1970 #ifdef __xpv
1971 _NOTE(ARGUNUSED(cp));
1972 #else
1973 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1974
1975 if (hdl != NULL) {
1976 cmi_hdl_hold(hdl);
1977 } else {
1978 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1979 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1980 }
1981 if (hdl != NULL) {
1982 cmi_faulted_enter(hdl);
1983 cmi_hdl_rele(hdl);
1984 }
1985 #endif
1986 }
1987
1988 void
1989 mp_cpu_faulted_exit(struct cpu *cp)
1990 {
1991 #ifdef __xpv
1992 _NOTE(ARGUNUSED(cp));
1993 #else
1994 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1995
1996 if (hdl != NULL) {
1997 cmi_hdl_hold(hdl);
1998 } else {
1999 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2000 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2001 }
2002 if (hdl != NULL) {
2003 cmi_faulted_exit(hdl);
2004 cmi_hdl_rele(hdl);
2005 }
2006 #endif
2007 }
2008
2009 /*
2010 * The following two routines are used as context operators on threads belonging
2011 * to processes with a private LDT (see sysi86). Due to the rarity of such
2012 * processes, these routines are currently written for best code readability and
2013 * organization rather than speed. We could avoid checking x86_featureset at
2014 * every context switch by installing different context ops, depending on
2015 * x86_featureset, at LDT creation time -- one for each combination of fast
2016 * syscall features.
2017 */
2018
2019 /*ARGSUSED*/
2020 void
2021 cpu_fast_syscall_disable(void *arg)
2022 {
2023 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2024 is_x86_feature(x86_featureset, X86FSET_SEP))
2025 cpu_sep_disable();
2026 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2027 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2028 cpu_asysc_disable();
2029 }
2030
2031 /*ARGSUSED*/
2032 void
2033 cpu_fast_syscall_enable(void *arg)
2034 {
2035 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2036 is_x86_feature(x86_featureset, X86FSET_SEP))
2037 cpu_sep_enable();
2038 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2039 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2040 cpu_asysc_enable();
2041 }
2042
2043 static void
2044 cpu_sep_enable(void)
2045 {
2046 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2047 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2048
2049 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2050 }
2051
2052 static void
2053 cpu_sep_disable(void)
2054 {
2055 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2056 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2057
2058 /*
2059 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2060 * the sysenter or sysexit instruction to trigger a #gp fault.
2061 */
2062 wrmsr(MSR_INTC_SEP_CS, 0);
2063 }
2064
2065 static void
2066 cpu_asysc_enable(void)
2067 {
2068 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2069 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2070
2071 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2072 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2073 }
2074
2075 static void
2076 cpu_asysc_disable(void)
2077 {
2078 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2079 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2080
2081 /*
2082 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2083 * executing syscall or sysret with this bit off will incur a #ud trap.
2084 */
2085 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2086 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2087 }