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--- old/usr/src/uts/i86pc/os/mlsetup.c
+++ new/usr/src/uts/i86pc/os/mlsetup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2012 Gary Mills
23 23 *
24 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 26 * Copyright 2016 Joyent, Inc.
27 27 */
28 28 /*
29 29 * Copyright (c) 2010, Intel Corporation.
30 30 * All rights reserved.
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/sysmacros.h>
35 35 #include <sys/disp.h>
36 36 #include <sys/promif.h>
37 37 #include <sys/clock.h>
38 38 #include <sys/cpuvar.h>
39 39 #include <sys/stack.h>
40 40 #include <vm/as.h>
41 41 #include <vm/hat.h>
42 42 #include <sys/reboot.h>
43 43 #include <sys/avintr.h>
44 44 #include <sys/vtrace.h>
45 45 #include <sys/proc.h>
46 46 #include <sys/thread.h>
47 47 #include <sys/cpupart.h>
48 48 #include <sys/pset.h>
49 49 #include <sys/copyops.h>
50 50 #include <sys/pg.h>
51 51 #include <sys/disp.h>
52 52 #include <sys/debug.h>
53 53 #include <sys/sunddi.h>
54 54 #include <sys/x86_archext.h>
55 55 #include <sys/privregs.h>
56 56 #include <sys/machsystm.h>
57 57 #include <sys/ontrap.h>
58 58 #include <sys/bootconf.h>
59 59 #include <sys/boot_console.h>
60 60 #include <sys/kdi_machimpl.h>
61 61 #include <sys/archsystm.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/pci_cfgspace.h>
64 64 #include <sys/bootvfs.h>
65 65 #include <sys/tsc.h>
66 66 #ifdef __xpv
67 67 #include <sys/hypervisor.h>
68 68 #else
69 69 #include <sys/xpv_support.h>
70 70 #endif
71 71
72 72 /*
73 73 * some globals for patching the result of cpuid
74 74 * to solve problems w/ creative cpu vendors
75 75 */
76 76
77 77 extern uint32_t cpuid_feature_ecx_include;
78 78 extern uint32_t cpuid_feature_ecx_exclude;
79 79 extern uint32_t cpuid_feature_edx_include;
80 80 extern uint32_t cpuid_feature_edx_exclude;
81 81
82 82 /*
83 83 * Set console mode
84 84 */
85 85 static void
86 86 set_console_mode(uint8_t val)
87 87 {
88 88 struct bop_regs rp = {0};
89 89
90 90 rp.eax.byte.ah = 0x0;
91 91 rp.eax.byte.al = val;
92 92 rp.ebx.word.bx = 0x0;
93 93
94 94 BOP_DOINT(bootops, 0x10, &rp);
95 95 }
96 96
97 97
98 98 /*
99 99 * Setup routine called right before main(). Interposing this function
100 100 * before main() allows us to call it in a machine-independent fashion.
101 101 */
102 102 void
103 103 mlsetup(struct regs *rp)
104 104 {
105 105 u_longlong_t prop_value;
106 106 extern struct classfuncs sys_classfuncs;
107 107 extern disp_t cpu0_disp;
108 108 extern char t0stack[];
109 109 extern int post_fastreboot;
110 110 extern uint64_t plat_dr_options;
111 111
112 112 ASSERT_STACK_ALIGNED();
113 113
114 114 /*
115 115 * initialize cpu_self
116 116 */
117 117 cpu[0]->cpu_self = cpu[0];
118 118
119 119 #if defined(__xpv)
120 120 /*
121 121 * Point at the hypervisor's virtual cpu structure
122 122 */
123 123 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
124 124 #endif
125 125
126 126 /*
127 127 * check if we've got special bits to clear or set
128 128 * when checking cpu features
129 129 */
130 130
131 131 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
132 132 cpuid_feature_ecx_include = 0;
133 133 else
134 134 cpuid_feature_ecx_include = (uint32_t)prop_value;
135 135
136 136 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
137 137 cpuid_feature_ecx_exclude = 0;
138 138 else
139 139 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
140 140
141 141 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
142 142 cpuid_feature_edx_include = 0;
143 143 else
144 144 cpuid_feature_edx_include = (uint32_t)prop_value;
145 145
146 146 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
147 147 cpuid_feature_edx_exclude = 0;
148 148 else
149 149 cpuid_feature_edx_exclude = (uint32_t)prop_value;
150 150
151 151 /*
152 152 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
153 153 */
154 154 init_desctbls();
155 155
156 156 /*
157 157 * lgrp_init() and possibly cpuid_pass1() need PCI config
158 158 * space access
159 159 */
160 160 #if defined(__xpv)
161 161 if (DOMAIN_IS_INITDOMAIN(xen_info))
162 162 pci_cfgspace_init();
163 163 #else
164 164 pci_cfgspace_init();
165 165 /*
166 166 * Initialize the platform type from CPU 0 to ensure that
167 167 * determine_platform() is only ever called once.
168 168 */
169 169 determine_platform();
170 170 #endif
171 171
172 172 /*
173 173 * The first lightweight pass (pass0) through the cpuid data
174 174 * was done in locore before mlsetup was called. Do the next
175 175 * pass in C code.
176 176 *
177 177 * The x86_featureset is initialized here based on the capabilities
178 178 * of the boot CPU. Note that if we choose to support CPUs that have
179 179 * different feature sets (at which point we would almost certainly
180 180 * want to set the feature bits to correspond to the feature
181 181 * minimum) this value may be altered.
182 182 */
183 183 cpuid_pass1(cpu[0], x86_featureset);
184 184
185 185 #if !defined(__xpv)
186 186 if ((get_hwenv() & HW_XEN_HVM) != 0)
187 187 xen_hvm_init();
188 188
189 189 /*
190 190 * Before we do anything with the TSCs, we need to work around
191 191 * Intel erratum BT81. On some CPUs, warm reset does not
192 192 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
193 193 * here. Other CPUs will clear it when we boot them later, and the
194 194 * resulting skew will be handled by tsc_sync_master()/_slave();
195 195 * note that such skew already exists and has to be handled anyway.
196 196 *
197 197 * We do this only on metal. This same problem can occur with a
198 198 * hypervisor that does not happen to virtualise a TSC that starts from
199 199 * zero, regardless of CPU type; however, we do not expect hypervisors
200 200 * that do not virtualise TSC that way to handle writes to TSC
201 201 * correctly, either.
202 202 */
203 203 if (get_hwenv() == HW_NATIVE &&
204 204 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
205 205 cpuid_getfamily(CPU) == 6 &&
206 206 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
207 207 is_x86_feature(x86_featureset, X86FSET_TSC)) {
208 208 (void) wrmsr(REG_TSC, 0UL);
209 209 }
210 210
211 211 /*
212 212 * Patch the tsc_read routine with appropriate set of instructions,
213 213 * depending on the processor family and architecure, to read the
214 214 * time-stamp counter while ensuring no out-of-order execution.
215 215 * Patch it while the kernel text is still writable.
216 216 *
217 217 * Note: tsc_read is not patched for intel processors whose family
218 218 * is >6 and for amd whose family >f (in case they don't support rdtscp
219 219 * instruction, unlikely). By default tsc_read will use cpuid for
220 220 * serialization in such cases. The following code needs to be
221 221 * revisited if intel processors of family >= f retains the
222 222 * instruction serialization nature of mfence instruction.
223 223 * Note: tsc_read is not patched for x86 processors which do
224 224 * not support "mfence". By default tsc_read will use cpuid for
225 225 * serialization in such cases.
226 226 *
227 227 * The Xen hypervisor does not correctly report whether rdtscp is
228 228 * supported or not, so we must assume that it is not.
229 229 */
230 230 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
231 231 is_x86_feature(x86_featureset, X86FSET_TSCP))
232 232 patch_tsc_read(TSC_TSCP);
233 233 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
234 234 cpuid_getfamily(CPU) <= 0xf &&
235 235 is_x86_feature(x86_featureset, X86FSET_SSE2))
236 236 patch_tsc_read(TSC_RDTSC_MFENCE);
237 237 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
238 238 cpuid_getfamily(CPU) <= 6 &&
239 239 is_x86_feature(x86_featureset, X86FSET_SSE2))
240 240 patch_tsc_read(TSC_RDTSC_LFENCE);
241 241
242 242 #endif /* !__xpv */
243 243
244 244 #if defined(__i386) && !defined(__xpv)
245 245 /*
246 246 * Some i386 processors do not implement the rdtsc instruction,
247 247 * or at least they do not implement it correctly. Patch them to
248 248 * return 0.
249 249 */
250 250 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
251 251 patch_tsc_read(TSC_NONE);
252 252 #endif /* __i386 && !__xpv */
253 253
254 254 #if defined(__amd64) && !defined(__xpv)
255 255 patch_memops(cpuid_getvendor(CPU));
256 256 #endif /* __amd64 && !__xpv */
257 257
258 258 #if !defined(__xpv)
259 259 /* XXPV what, if anything, should be dorked with here under xen? */
260 260
261 261 /*
262 262 * While we're thinking about the TSC, let's set up %cr4 so that
263 263 * userland can issue rdtsc, and initialize the TSC_AUX value
264 264 * (the cpuid) for the rdtscp instruction on appropriately
265 265 * capable hardware.
266 266 */
267 267 if (is_x86_feature(x86_featureset, X86FSET_TSC))
268 268 setcr4(getcr4() & ~CR4_TSD);
269 269
270 270 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
271 271 (void) wrmsr(MSR_AMD_TSCAUX, 0);
272 272
273 273 /*
274 274 * Let's get the other %cr4 stuff while we're here. Note, we defer
275 275 * enabling CR4_SMAP until startup_end(); however, that's importantly
276 276 * before we start other CPUs. That ensures that it will be synced out
277 277 * to other CPUs.
278 278 */
279 279 if (is_x86_feature(x86_featureset, X86FSET_DE))
280 280 setcr4(getcr4() | CR4_DE);
281 281
282 282 if (is_x86_feature(x86_featureset, X86FSET_SMEP))
283 283 setcr4(getcr4() | CR4_SMEP);
284 284 #endif /* __xpv */
285 285
286 286 /*
287 287 * initialize t0
288 288 */
289 289 t0.t_stk = (caddr_t)rp - MINFRAME;
290 290 t0.t_stkbase = t0stack;
291 291 t0.t_pri = maxclsyspri - 3;
292 292 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
293 293 t0.t_procp = &p0;
294 294 t0.t_plockp = &p0lock.pl_lock;
295 295 t0.t_lwp = &lwp0;
296 296 t0.t_forw = &t0;
297 297 t0.t_back = &t0;
298 298 t0.t_next = &t0;
299 299 t0.t_prev = &t0;
300 300 t0.t_cpu = cpu[0];
301 301 t0.t_disp_queue = &cpu0_disp;
302 302 t0.t_bind_cpu = PBIND_NONE;
303 303 t0.t_bind_pset = PS_NONE;
304 304 t0.t_bindflag = (uchar_t)default_binding_mode;
305 305 t0.t_cpupart = &cp_default;
306 306 t0.t_clfuncs = &sys_classfuncs.thread;
307 307 t0.t_copyops = NULL;
308 308 THREAD_ONPROC(&t0, CPU);
309 309
310 310 lwp0.lwp_thread = &t0;
311 311 lwp0.lwp_regs = (void *)rp;
312 312 lwp0.lwp_procp = &p0;
313 313 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
314 314
315 315 p0.p_exec = NULL;
316 316 p0.p_stat = SRUN;
317 317 p0.p_flag = SSYS;
318 318 p0.p_tlist = &t0;
319 319 p0.p_stksize = 2*PAGESIZE;
320 320 p0.p_stkpageszc = 0;
321 321 p0.p_as = &kas;
322 322 p0.p_lockp = &p0lock;
323 323 p0.p_brkpageszc = 0;
324 324 p0.p_t1_lgrpid = LGRP_NONE;
325 325 p0.p_tr_lgrpid = LGRP_NONE;
326 326 sigorset(&p0.p_ignore, &ignoredefault);
327 327
328 328 CPU->cpu_thread = &t0;
329 329 bzero(&cpu0_disp, sizeof (disp_t));
330 330 CPU->cpu_disp = &cpu0_disp;
331 331 CPU->cpu_disp->disp_cpu = CPU;
332 332 CPU->cpu_dispthread = &t0;
333 333 CPU->cpu_idle_thread = &t0;
334 334 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
335 335 CPU->cpu_dispatch_pri = t0.t_pri;
336 336
337 337 CPU->cpu_id = 0;
338 338
339 339 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
340 340
341 341 /*
342 342 * The kernel doesn't use LDTs unless a process explicitly requests one.
343 343 */
344 344 p0.p_ldt_desc = null_sdesc;
345 345
346 346 /*
347 347 * Initialize thread/cpu microstate accounting
348 348 */
349 349 init_mstate(&t0, LMS_SYSTEM);
350 350 init_cpu_mstate(CPU, CMS_SYSTEM);
351 351
352 352 /*
353 353 * Initialize lists of available and active CPUs.
354 354 */
355 355 cpu_list_init(CPU);
356 356
357 357 pg_cpu_bootstrap(CPU);
358 358
359 359 /*
360 360 * Now that we have taken over the GDT, IDT and have initialized
361 361 * active CPU list it's time to inform kmdb if present.
362 362 */
363 363 if (boothowto & RB_DEBUG)
364 364 kdi_idt_sync();
365 365
366 366 /*
367 367 * Explicitly set console to text mode (0x3) if this is a boot
368 368 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT.
369 369 */
370 370 if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT)
371 371 set_console_mode(0x3);
372 372
373 373 /*
374 374 * If requested (boot -d) drop into kmdb.
375 375 *
376 376 * This must be done after cpu_list_init() on the 64-bit kernel
377 377 * since taking a trap requires that we re-compute gsbase based
378 378 * on the cpu list.
379 379 */
380 380 if (boothowto & RB_DEBUGENTER)
381 381 kmdb_enter();
382 382
383 383 cpu_vm_data_init(CPU);
384 384
385 385 rp->r_fp = 0; /* terminate kernel stack traces! */
386 386
387 387 prom_init("kernel", (void *)NULL);
388 388
389 389 /* User-set option overrides firmware value. */
390 390 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
391 391 plat_dr_options = (uint64_t)prop_value;
392 392 }
393 393 #if defined(__xpv)
394 394 /* No support of DR operations on xpv */
395 395 plat_dr_options = 0;
396 396 #else /* __xpv */
397 397 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
398 398 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
399 399 #ifndef __amd64
400 400 /* Only enable CPU/memory DR on 64 bits kernel. */
401 401 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
402 402 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
403 403 #endif /* __amd64 */
404 404 #endif /* __xpv */
405 405
406 406 /*
407 407 * Get value of "plat_dr_physmax" boot option.
408 408 * It overrides values calculated from MSCT or SRAT table.
409 409 */
410 410 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
411 411 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
412 412 }
413 413
414 414 /* Get value of boot_ncpus. */
415 415 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
416 416 boot_ncpus = NCPU;
417 417 } else {
418 418 boot_ncpus = (int)prop_value;
419 419 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
420 420 boot_ncpus = NCPU;
421 421 }
422 422
423 423 /*
424 424 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
425 425 * support CPU DR operations.
426 426 */
427 427 if (plat_dr_support_cpu() == 0) {
428 428 max_ncpus = boot_max_ncpus = boot_ncpus;
429 429 } else {
430 430 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
431 431 max_ncpus = NCPU;
432 432 } else {
433 433 max_ncpus = (int)prop_value;
434 434 if (max_ncpus <= 0 || max_ncpus > NCPU) {
435 435 max_ncpus = NCPU;
436 436 }
437 437 if (boot_ncpus > max_ncpus) {
438 438 boot_ncpus = max_ncpus;
439 439 }
440 440 }
441 441
442 442 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
443 443 boot_max_ncpus = boot_ncpus;
444 444 } else {
445 445 boot_max_ncpus = (int)prop_value;
446 446 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
447 447 boot_max_ncpus = boot_ncpus;
448 448 } else if (boot_max_ncpus > max_ncpus) {
449 449 boot_max_ncpus = max_ncpus;
450 450 }
451 451 }
452 452 }
453 453
454 454 /*
455 455 * Initialize the lgrp framework
456 456 */
457 457 lgrp_init(LGRP_INIT_STAGE1);
458 458
459 459 if (boothowto & RB_HALT) {
460 460 prom_printf("unix: kernel halted by -h flag\n");
461 461 prom_enter_mon();
462 462 }
463 463
464 464 ASSERT_STACK_ALIGNED();
465 465
466 466 /*
467 467 * Fill out cpu_ucode_info. Update microcode if necessary.
468 468 */
469 469 ucode_check(CPU);
470 470
471 471 if (workaround_errata(CPU) != 0)
472 472 panic("critical workaround(s) missing for boot cpu");
473 473 }
474 474
475 475
476 476 void
477 477 mach_modpath(char *path, const char *filename)
478 478 {
479 479 /*
480 480 * Construct the directory path from the filename.
481 481 */
482 482
483 483 int len;
484 484 char *p;
485 485 const char isastr[] = "/amd64";
486 486 size_t isalen = strlen(isastr);
487 487
488 488 len = strlen(SYSTEM_BOOT_PATH "/kernel");
489 489 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
490 490 path += len + 1;
491 491
492 492 if ((p = strrchr(filename, '/')) == NULL)
493 493 return;
494 494
495 495 while (p > filename && *(p - 1) == '/')
496 496 p--; /* remove trailing '/' characters */
497 497 if (p == filename)
498 498 p++; /* so "/" -is- the modpath in this case */
499 499
500 500 /*
501 501 * Remove optional isa-dependent directory name - the module
502 502 * subsystem will put this back again (!)
503 503 */
504 504 len = p - filename;
505 505 if (len > isalen &&
506 506 strncmp(&filename[len - isalen], isastr, isalen) == 0)
507 507 p -= isalen;
508 508
509 509 /*
510 510 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
511 511 */
512 512 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
513 513 (void) strncpy(path, filename, p - filename);
514 514 }
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