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--- old/usr/src/uts/i86pc/os/cpuid.c
+++ new/usr/src/uts/i86pc/os/cpuid.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
26 26 */
27 27 /*
28 28 * Copyright (c) 2010, Intel Corporation.
29 29 * All rights reserved.
30 30 */
31 31 /*
32 32 * Portions Copyright 2009 Advanced Micro Devices, Inc.
33 33 */
34 34 /*
35 35 * Copyright 2016 Joyent, Inc.
36 36 */
37 37 /*
38 38 * Various routines to handle identification
39 39 * and classification of x86 processors.
40 40 */
41 41
42 42 #include <sys/types.h>
43 43 #include <sys/archsystm.h>
44 44 #include <sys/x86_archext.h>
45 45 #include <sys/kmem.h>
46 46 #include <sys/systm.h>
47 47 #include <sys/cmn_err.h>
48 48 #include <sys/sunddi.h>
49 49 #include <sys/sunndi.h>
50 50 #include <sys/cpuvar.h>
51 51 #include <sys/processor.h>
52 52 #include <sys/sysmacros.h>
53 53 #include <sys/pg.h>
54 54 #include <sys/fp.h>
55 55 #include <sys/controlregs.h>
56 56 #include <sys/bitmap.h>
57 57 #include <sys/auxv_386.h>
58 58 #include <sys/memnode.h>
59 59 #include <sys/pci_cfgspace.h>
60 60 #include <sys/comm_page.h>
61 61 #include <sys/tsc.h>
62 62
63 63 #ifdef __xpv
64 64 #include <sys/hypervisor.h>
65 65 #else
66 66 #include <sys/ontrap.h>
67 67 #endif
68 68
69 69 /*
70 70 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
71 71 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
72 72 * them accordingly. For most modern processors, feature detection occurs here
73 73 * in pass 1.
74 74 *
75 75 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
76 76 * for the boot CPU and does the basic analysis that the early kernel needs.
77 77 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
78 78 * CPU.
79 79 *
80 80 * Pass 1 includes:
81 81 *
82 82 * o Determining vendor/model/family/stepping and setting x86_type and
83 83 * x86_vendor accordingly.
84 84 * o Processing the feature flags returned by the cpuid instruction while
85 85 * applying any workarounds or tricks for the specific processor.
86 86 * o Mapping the feature flags into Solaris feature bits (X86_*).
87 87 * o Processing extended feature flags if supported by the processor,
88 88 * again while applying specific processor knowledge.
89 89 * o Determining the CMT characteristics of the system.
90 90 *
91 91 * Pass 1 is done on non-boot CPUs during their initialization and the results
92 92 * are used only as a meager attempt at ensuring that all processors within the
93 93 * system support the same features.
94 94 *
95 95 * Pass 2 of cpuid feature analysis happens just at the beginning
96 96 * of startup(). It just copies in and corrects the remainder
97 97 * of the cpuid data we depend on: standard cpuid functions that we didn't
98 98 * need for pass1 feature analysis, and extended cpuid functions beyond the
99 99 * simple feature processing done in pass1.
100 100 *
101 101 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
102 102 * particular kernel memory allocation has been made available. It creates a
103 103 * readable brand string based on the data collected in the first two passes.
104 104 *
105 105 * Pass 4 of cpuid analysis is invoked after post_startup() when all
106 106 * the support infrastructure for various hardware features has been
107 107 * initialized. It determines which processor features will be reported
108 108 * to userland via the aux vector.
109 109 *
110 110 * All passes are executed on all CPUs, but only the boot CPU determines what
111 111 * features the kernel will use.
112 112 *
113 113 * Much of the worst junk in this file is for the support of processors
114 114 * that didn't really implement the cpuid instruction properly.
115 115 *
116 116 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
117 117 * the pass numbers. Accordingly, changes to the pass code may require changes
118 118 * to the accessor code.
119 119 */
120 120
121 121 uint_t x86_vendor = X86_VENDOR_IntelClone;
122 122 uint_t x86_type = X86_TYPE_OTHER;
123 123 uint_t x86_clflush_size = 0;
124 124
125 125 uint_t pentiumpro_bug4046376;
126 126
127 127 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
128 128
129 129 static char *x86_feature_names[NUM_X86_FEATURES] = {
130 130 "lgpg",
131 131 "tsc",
132 132 "msr",
133 133 "mtrr",
134 134 "pge",
135 135 "de",
136 136 "cmov",
137 137 "mmx",
138 138 "mca",
139 139 "pae",
140 140 "cv8",
141 141 "pat",
142 142 "sep",
143 143 "sse",
144 144 "sse2",
145 145 "htt",
146 146 "asysc",
147 147 "nx",
148 148 "sse3",
149 149 "cx16",
150 150 "cmp",
151 151 "tscp",
152 152 "mwait",
153 153 "sse4a",
154 154 "cpuid",
155 155 "ssse3",
156 156 "sse4_1",
157 157 "sse4_2",
158 158 "1gpg",
159 159 "clfsh",
160 160 "64",
161 161 "aes",
162 162 "pclmulqdq",
163 163 "xsave",
164 164 "avx",
165 165 "vmx",
166 166 "svm",
167 167 "topoext",
168 168 "f16c",
169 169 "rdrand",
170 170 "x2apic",
171 171 "avx2",
172 172 "bmi1",
173 173 "bmi2",
174 174 "fma",
175 175 "smep",
176 176 "smap",
177 177 "adx",
178 178 "rdseed"
179 179 };
180 180
181 181 boolean_t
182 182 is_x86_feature(void *featureset, uint_t feature)
183 183 {
184 184 ASSERT(feature < NUM_X86_FEATURES);
185 185 return (BT_TEST((ulong_t *)featureset, feature));
186 186 }
187 187
188 188 void
189 189 add_x86_feature(void *featureset, uint_t feature)
190 190 {
191 191 ASSERT(feature < NUM_X86_FEATURES);
192 192 BT_SET((ulong_t *)featureset, feature);
193 193 }
194 194
195 195 void
196 196 remove_x86_feature(void *featureset, uint_t feature)
197 197 {
198 198 ASSERT(feature < NUM_X86_FEATURES);
199 199 BT_CLEAR((ulong_t *)featureset, feature);
200 200 }
201 201
202 202 boolean_t
203 203 compare_x86_featureset(void *setA, void *setB)
204 204 {
205 205 /*
206 206 * We assume that the unused bits of the bitmap are always zero.
207 207 */
208 208 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
209 209 return (B_TRUE);
210 210 } else {
211 211 return (B_FALSE);
212 212 }
213 213 }
214 214
215 215 void
216 216 print_x86_featureset(void *featureset)
217 217 {
218 218 uint_t i;
219 219
220 220 for (i = 0; i < NUM_X86_FEATURES; i++) {
221 221 if (is_x86_feature(featureset, i)) {
222 222 cmn_err(CE_CONT, "?x86_feature: %s\n",
223 223 x86_feature_names[i]);
224 224 }
225 225 }
226 226 }
227 227
228 228 static size_t xsave_state_size = 0;
229 229 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE);
230 230 boolean_t xsave_force_disable = B_FALSE;
231 231 extern int disable_smap;
232 232
233 233 /*
234 234 * This is set to platform type we are running on.
235 235 */
236 236 static int platform_type = -1;
237 237
238 238 #if !defined(__xpv)
239 239 /*
240 240 * Variable to patch if hypervisor platform detection needs to be
241 241 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
242 242 */
243 243 int enable_platform_detection = 1;
244 244 #endif
245 245
246 246 /*
247 247 * monitor/mwait info.
248 248 *
249 249 * size_actual and buf_actual are the real address and size allocated to get
250 250 * proper mwait_buf alignement. buf_actual and size_actual should be passed
251 251 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
252 252 * processor cache-line alignment, but this is not guarantied in the furture.
253 253 */
254 254 struct mwait_info {
255 255 size_t mon_min; /* min size to avoid missed wakeups */
256 256 size_t mon_max; /* size to avoid false wakeups */
257 257 size_t size_actual; /* size actually allocated */
258 258 void *buf_actual; /* memory actually allocated */
259 259 uint32_t support; /* processor support of monitor/mwait */
260 260 };
261 261
262 262 /*
263 263 * xsave/xrestor info.
264 264 *
265 265 * This structure contains HW feature bits and size of the xsave save area.
266 266 * Note: the kernel will use the maximum size required for all hardware
267 267 * features. It is not optimize for potential memory savings if features at
268 268 * the end of the save area are not enabled.
269 269 */
270 270 struct xsave_info {
271 271 uint32_t xsav_hw_features_low; /* Supported HW features */
272 272 uint32_t xsav_hw_features_high; /* Supported HW features */
273 273 size_t xsav_max_size; /* max size save area for HW features */
274 274 size_t ymm_size; /* AVX: size of ymm save area */
275 275 size_t ymm_offset; /* AVX: offset for ymm save area */
276 276 };
277 277
278 278
279 279 /*
280 280 * These constants determine how many of the elements of the
281 281 * cpuid we cache in the cpuid_info data structure; the
282 282 * remaining elements are accessible via the cpuid instruction.
283 283 */
284 284
285 285 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */
286 286 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
287 287
288 288 /*
289 289 * Some terminology needs to be explained:
290 290 * - Socket: Something that can be plugged into a motherboard.
291 291 * - Package: Same as socket
292 292 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
293 293 * differently: there, chip is the same as processor node (below)
294 294 * - Processor node: Some AMD processors have more than one
295 295 * "subprocessor" embedded in a package. These subprocessors (nodes)
296 296 * are fully-functional processors themselves with cores, caches,
297 297 * memory controllers, PCI configuration spaces. They are connected
298 298 * inside the package with Hypertransport links. On single-node
299 299 * processors, processor node is equivalent to chip/socket/package.
300 300 * - Compute Unit: Some AMD processors pair cores in "compute units" that
301 301 * share the FPU and the I$ and L2 caches.
302 302 */
303 303
304 304 struct cpuid_info {
305 305 uint_t cpi_pass; /* last pass completed */
306 306 /*
307 307 * standard function information
308 308 */
309 309 uint_t cpi_maxeax; /* fn 0: %eax */
310 310 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
311 311 uint_t cpi_vendor; /* enum of cpi_vendorstr */
312 312
313 313 uint_t cpi_family; /* fn 1: extended family */
314 314 uint_t cpi_model; /* fn 1: extended model */
315 315 uint_t cpi_step; /* fn 1: stepping */
316 316 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
317 317 /* AMD: package/socket # */
318 318 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
319 319 int cpi_clogid; /* fn 1: %ebx: thread # */
320 320 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
321 321 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
322 322 uint_t cpi_ncache; /* fn 2: number of elements */
323 323 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
324 324 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
325 325 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
326 326 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
327 327 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */
328 328 /*
329 329 * extended function information
330 330 */
331 331 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
332 332 char cpi_brandstr[49]; /* fn 0x8000000[234] */
333 333 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
334 334 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
335 335 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
336 336
337 337 id_t cpi_coreid; /* same coreid => strands share core */
338 338 int cpi_pkgcoreid; /* core number within single package */
339 339 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
340 340 /* Intel: fn 4: %eax[31-26] */
341 341 /*
342 342 * supported feature information
343 343 */
344 344 uint32_t cpi_support[6];
345 345 #define STD_EDX_FEATURES 0
346 346 #define AMD_EDX_FEATURES 1
347 347 #define TM_EDX_FEATURES 2
348 348 #define STD_ECX_FEATURES 3
349 349 #define AMD_ECX_FEATURES 4
350 350 #define STD_EBX_FEATURES 5
351 351 /*
352 352 * Synthesized information, where known.
353 353 */
354 354 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
355 355 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
356 356 uint32_t cpi_socket; /* Chip package/socket type */
357 357
358 358 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
359 359 uint32_t cpi_apicid;
360 360 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
361 361 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
362 362 /* Intel: 1 */
363 363 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
364 364 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
365 365
366 366 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
367 367 };
368 368
369 369
370 370 static struct cpuid_info cpuid_info0;
371 371
372 372 /*
373 373 * These bit fields are defined by the Intel Application Note AP-485
374 374 * "Intel Processor Identification and the CPUID Instruction"
375 375 */
376 376 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
377 377 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
378 378 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
379 379 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
380 380 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
381 381 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
382 382
383 383 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
384 384 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
385 385 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
386 386 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
387 387 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx)
388 388
389 389 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
390 390 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
391 391 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
392 392 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
393 393
394 394 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
395 395 #define CPI_XMAXEAX_MAX 0x80000100
396 396 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
397 397 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
398 398
399 399 /*
400 400 * Function 4 (Deterministic Cache Parameters) macros
401 401 * Defined by Intel Application Note AP-485
402 402 */
403 403 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
404 404 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
405 405 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
406 406 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
407 407 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
408 408 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
409 409 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
410 410
411 411 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
412 412 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
413 413 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
414 414
415 415 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
416 416
417 417 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
418 418
419 419
420 420 /*
421 421 * A couple of shorthand macros to identify "later" P6-family chips
422 422 * like the Pentium M and Core. First, the "older" P6-based stuff
423 423 * (loosely defined as "pre-Pentium-4"):
424 424 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
425 425 */
426 426
427 427 #define IS_LEGACY_P6(cpi) ( \
428 428 cpi->cpi_family == 6 && \
429 429 (cpi->cpi_model == 1 || \
430 430 cpi->cpi_model == 3 || \
431 431 cpi->cpi_model == 5 || \
432 432 cpi->cpi_model == 6 || \
433 433 cpi->cpi_model == 7 || \
434 434 cpi->cpi_model == 8 || \
435 435 cpi->cpi_model == 0xA || \
436 436 cpi->cpi_model == 0xB) \
437 437 )
438 438
439 439 /* A "new F6" is everything with family 6 that's not the above */
440 440 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
441 441
442 442 /* Extended family/model support */
443 443 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
444 444 cpi->cpi_family >= 0xf)
445 445
446 446 /*
447 447 * Info for monitor/mwait idle loop.
448 448 *
449 449 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
450 450 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
451 451 * 2006.
452 452 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
453 453 * Documentation Updates" #33633, Rev 2.05, December 2006.
454 454 */
455 455 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
456 456 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
457 457 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
458 458 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
459 459 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
460 460 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
461 461 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
462 462 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
463 463 /*
464 464 * Number of sub-cstates for a given c-state.
465 465 */
466 466 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
467 467 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
468 468
469 469 /*
470 470 * XSAVE leaf 0xD enumeration
471 471 */
472 472 #define CPUID_LEAFD_2_YMM_OFFSET 576
473 473 #define CPUID_LEAFD_2_YMM_SIZE 256
474 474
475 475 /*
476 476 * Functions we consune from cpuid_subr.c; don't publish these in a header
477 477 * file to try and keep people using the expected cpuid_* interfaces.
478 478 */
479 479 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
480 480 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
481 481 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
482 482 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
483 483 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
484 484
485 485 /*
486 486 * Apply up various platform-dependent restrictions where the
487 487 * underlying platform restrictions mean the CPU can be marked
488 488 * as less capable than its cpuid instruction would imply.
489 489 */
490 490 #if defined(__xpv)
491 491 static void
492 492 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
493 493 {
494 494 switch (eax) {
495 495 case 1: {
496 496 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
497 497 0 : CPUID_INTC_EDX_MCA;
498 498 cp->cp_edx &=
499 499 ~(mcamask |
500 500 CPUID_INTC_EDX_PSE |
501 501 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
502 502 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
503 503 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
504 504 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
505 505 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
506 506 break;
507 507 }
508 508
509 509 case 0x80000001:
510 510 cp->cp_edx &=
511 511 ~(CPUID_AMD_EDX_PSE |
512 512 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
513 513 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
514 514 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
515 515 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
516 516 CPUID_AMD_EDX_TSCP);
517 517 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
518 518 break;
519 519 default:
520 520 break;
521 521 }
522 522
523 523 switch (vendor) {
524 524 case X86_VENDOR_Intel:
525 525 switch (eax) {
526 526 case 4:
527 527 /*
528 528 * Zero out the (ncores-per-chip - 1) field
529 529 */
530 530 cp->cp_eax &= 0x03fffffff;
531 531 break;
532 532 default:
533 533 break;
534 534 }
535 535 break;
536 536 case X86_VENDOR_AMD:
537 537 switch (eax) {
538 538
539 539 case 0x80000001:
540 540 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
541 541 break;
542 542
543 543 case 0x80000008:
544 544 /*
545 545 * Zero out the (ncores-per-chip - 1) field
546 546 */
547 547 cp->cp_ecx &= 0xffffff00;
548 548 break;
549 549 default:
550 550 break;
551 551 }
552 552 break;
553 553 default:
554 554 break;
555 555 }
556 556 }
557 557 #else
558 558 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
559 559 #endif
560 560
561 561 /*
562 562 * Some undocumented ways of patching the results of the cpuid
563 563 * instruction to permit running Solaris 10 on future cpus that
564 564 * we don't currently support. Could be set to non-zero values
565 565 * via settings in eeprom.
566 566 */
567 567
568 568 uint32_t cpuid_feature_ecx_include;
569 569 uint32_t cpuid_feature_ecx_exclude;
570 570 uint32_t cpuid_feature_edx_include;
571 571 uint32_t cpuid_feature_edx_exclude;
572 572
573 573 /*
574 574 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
575 575 */
576 576 void
577 577 cpuid_alloc_space(cpu_t *cpu)
578 578 {
579 579 /*
580 580 * By convention, cpu0 is the boot cpu, which is set up
581 581 * before memory allocation is available. All other cpus get
582 582 * their cpuid_info struct allocated here.
583 583 */
584 584 ASSERT(cpu->cpu_id != 0);
585 585 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
586 586 cpu->cpu_m.mcpu_cpi =
587 587 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
588 588 }
589 589
590 590 void
591 591 cpuid_free_space(cpu_t *cpu)
592 592 {
593 593 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
594 594 int i;
595 595
596 596 ASSERT(cpi != NULL);
597 597 ASSERT(cpi != &cpuid_info0);
598 598
599 599 /*
600 600 * Free up any function 4 related dynamic storage
601 601 */
602 602 for (i = 1; i < cpi->cpi_std_4_size; i++)
603 603 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
604 604 if (cpi->cpi_std_4_size > 0)
605 605 kmem_free(cpi->cpi_std_4,
606 606 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
607 607
608 608 kmem_free(cpi, sizeof (*cpi));
609 609 cpu->cpu_m.mcpu_cpi = NULL;
610 610 }
611 611
612 612 #if !defined(__xpv)
613 613 /*
614 614 * Determine the type of the underlying platform. This is used to customize
615 615 * initialization of various subsystems (e.g. TSC). determine_platform() must
616 616 * only ever be called once to prevent two processors from seeing different
617 617 * values of platform_type. Must be called before cpuid_pass1(), the earliest
618 618 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
619 619 */
620 620 void
621 621 determine_platform(void)
622 622 {
623 623 struct cpuid_regs cp;
624 624 uint32_t base;
625 625 uint32_t regs[4];
626 626 char *hvstr = (char *)regs;
627 627
628 628 ASSERT(platform_type == -1);
629 629
630 630 platform_type = HW_NATIVE;
631 631
632 632 if (!enable_platform_detection)
633 633 return;
634 634
635 635 /*
636 636 * If Hypervisor CPUID bit is set, try to determine hypervisor
637 637 * vendor signature, and set platform type accordingly.
638 638 *
639 639 * References:
640 640 * http://lkml.org/lkml/2008/10/1/246
641 641 * http://kb.vmware.com/kb/1009458
642 642 */
643 643 cp.cp_eax = 0x1;
644 644 (void) __cpuid_insn(&cp);
645 645 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
646 646 cp.cp_eax = 0x40000000;
647 647 (void) __cpuid_insn(&cp);
648 648 regs[0] = cp.cp_ebx;
649 649 regs[1] = cp.cp_ecx;
650 650 regs[2] = cp.cp_edx;
651 651 regs[3] = 0;
652 652 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
653 653 platform_type = HW_XEN_HVM;
654 654 return;
655 655 }
656 656 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
657 657 platform_type = HW_VMWARE;
658 658 return;
659 659 }
660 660 if (strcmp(hvstr, HVSIG_KVM) == 0) {
661 661 platform_type = HW_KVM;
662 662 return;
663 663 }
664 664 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
665 665 platform_type = HW_MICROSOFT;
666 666 } else {
667 667 /*
668 668 * Check older VMware hardware versions. VMware hypervisor is
669 669 * detected by performing an IN operation to VMware hypervisor
670 670 * port and checking that value returned in %ebx is VMware
671 671 * hypervisor magic value.
672 672 *
673 673 * References: http://kb.vmware.com/kb/1009458
674 674 */
675 675 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
676 676 if (regs[1] == VMWARE_HVMAGIC) {
677 677 platform_type = HW_VMWARE;
678 678 return;
679 679 }
680 680 }
681 681
682 682 /*
683 683 * Check Xen hypervisor. In a fully virtualized domain,
684 684 * Xen's pseudo-cpuid function returns a string representing the
685 685 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
686 686 * supported cpuid function. We need at least a (base + 2) leaf value
687 687 * to do what we want to do. Try different base values, since the
688 688 * hypervisor might use a different one depending on whether Hyper-V
689 689 * emulation is switched on by default or not.
690 690 */
691 691 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
692 692 cp.cp_eax = base;
693 693 (void) __cpuid_insn(&cp);
694 694 regs[0] = cp.cp_ebx;
695 695 regs[1] = cp.cp_ecx;
696 696 regs[2] = cp.cp_edx;
697 697 regs[3] = 0;
698 698 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
699 699 cp.cp_eax >= (base + 2)) {
700 700 platform_type &= ~HW_NATIVE;
701 701 platform_type |= HW_XEN_HVM;
702 702 return;
703 703 }
704 704 }
705 705 }
706 706
707 707 int
708 708 get_hwenv(void)
709 709 {
710 710 ASSERT(platform_type != -1);
711 711 return (platform_type);
712 712 }
713 713
714 714 int
715 715 is_controldom(void)
716 716 {
717 717 return (0);
718 718 }
719 719
720 720 #else
721 721
722 722 int
723 723 get_hwenv(void)
724 724 {
725 725 return (HW_XEN_PV);
726 726 }
727 727
728 728 int
729 729 is_controldom(void)
730 730 {
731 731 return (DOMAIN_IS_INITDOMAIN(xen_info));
732 732 }
733 733
734 734 #endif /* __xpv */
735 735
736 736 static void
737 737 cpuid_intel_getids(cpu_t *cpu, void *feature)
738 738 {
739 739 uint_t i;
740 740 uint_t chipid_shift = 0;
741 741 uint_t coreid_shift = 0;
742 742 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
743 743
744 744 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
745 745 chipid_shift++;
746 746
747 747 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
748 748 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
749 749
750 750 if (is_x86_feature(feature, X86FSET_CMP)) {
751 751 /*
752 752 * Multi-core (and possibly multi-threaded)
753 753 * processors.
754 754 */
755 755 uint_t ncpu_per_core;
756 756 if (cpi->cpi_ncore_per_chip == 1)
757 757 ncpu_per_core = cpi->cpi_ncpu_per_chip;
758 758 else if (cpi->cpi_ncore_per_chip > 1)
759 759 ncpu_per_core = cpi->cpi_ncpu_per_chip /
760 760 cpi->cpi_ncore_per_chip;
761 761 /*
762 762 * 8bit APIC IDs on dual core Pentiums
763 763 * look like this:
764 764 *
765 765 * +-----------------------+------+------+
766 766 * | Physical Package ID | MC | HT |
767 767 * +-----------------------+------+------+
768 768 * <------- chipid -------->
769 769 * <------- coreid --------------->
770 770 * <--- clogid -->
771 771 * <------>
772 772 * pkgcoreid
773 773 *
774 774 * Where the number of bits necessary to
775 775 * represent MC and HT fields together equals
776 776 * to the minimum number of bits necessary to
777 777 * store the value of cpi->cpi_ncpu_per_chip.
778 778 * Of those bits, the MC part uses the number
779 779 * of bits necessary to store the value of
780 780 * cpi->cpi_ncore_per_chip.
781 781 */
782 782 for (i = 1; i < ncpu_per_core; i <<= 1)
783 783 coreid_shift++;
784 784 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
785 785 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
786 786 } else if (is_x86_feature(feature, X86FSET_HTT)) {
787 787 /*
788 788 * Single-core multi-threaded processors.
789 789 */
790 790 cpi->cpi_coreid = cpi->cpi_chipid;
791 791 cpi->cpi_pkgcoreid = 0;
792 792 }
793 793 cpi->cpi_procnodeid = cpi->cpi_chipid;
794 794 cpi->cpi_compunitid = cpi->cpi_coreid;
795 795 }
796 796
797 797 static void
798 798 cpuid_amd_getids(cpu_t *cpu)
799 799 {
800 800 int i, first_half, coreidsz;
801 801 uint32_t nb_caps_reg;
802 802 uint_t node2_1;
803 803 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
804 804 struct cpuid_regs *cp;
805 805
806 806 /*
807 807 * AMD CMP chips currently have a single thread per core.
808 808 *
809 809 * Since no two cpus share a core we must assign a distinct coreid
810 810 * per cpu, and we do this by using the cpu_id. This scheme does not,
811 811 * however, guarantee that sibling cores of a chip will have sequential
812 812 * coreids starting at a multiple of the number of cores per chip -
813 813 * that is usually the case, but if the ACPI MADT table is presented
814 814 * in a different order then we need to perform a few more gymnastics
815 815 * for the pkgcoreid.
816 816 *
817 817 * All processors in the system have the same number of enabled
818 818 * cores. Cores within a processor are always numbered sequentially
819 819 * from 0 regardless of how many or which are disabled, and there
820 820 * is no way for operating system to discover the real core id when some
821 821 * are disabled.
822 822 *
823 823 * In family 0x15, the cores come in pairs called compute units. They
824 824 * share I$ and L2 caches and the FPU. Enumeration of this feature is
825 825 * simplified by the new topology extensions CPUID leaf, indicated by
826 826 * the X86 feature X86FSET_TOPOEXT.
827 827 */
828 828
829 829 cpi->cpi_coreid = cpu->cpu_id;
830 830 cpi->cpi_compunitid = cpu->cpu_id;
831 831
832 832 if (cpi->cpi_xmaxeax >= 0x80000008) {
833 833
834 834 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
835 835
836 836 /*
837 837 * In AMD parlance chip is really a node while Solaris
838 838 * sees chip as equivalent to socket/package.
839 839 */
840 840 cpi->cpi_ncore_per_chip =
841 841 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
842 842 if (coreidsz == 0) {
843 843 /* Use legacy method */
844 844 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
845 845 coreidsz++;
846 846 if (coreidsz == 0)
847 847 coreidsz = 1;
848 848 }
849 849 } else {
850 850 /* Assume single-core part */
851 851 cpi->cpi_ncore_per_chip = 1;
852 852 coreidsz = 1;
853 853 }
854 854
855 855 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
856 856 cpi->cpi_apicid & ((1<<coreidsz) - 1);
857 857 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
858 858
859 859 /* Get node ID, compute unit ID */
860 860 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
861 861 cpi->cpi_xmaxeax >= 0x8000001e) {
862 862 cp = &cpi->cpi_extd[0x1e];
863 863 cp->cp_eax = 0x8000001e;
864 864 (void) __cpuid_insn(cp);
865 865
866 866 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
867 867 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
868 868 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
869 869 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
870 870 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
871 871 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
872 872 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
873 873 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
874 874 } else if (cpi->cpi_family == 0x10) {
875 875 /*
876 876 * See if we are a multi-node processor.
877 877 * All processors in the system have the same number of nodes
878 878 */
879 879 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
880 880 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
881 881 /* Single-node */
882 882 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
883 883 coreidsz);
884 884 } else {
885 885
886 886 /*
887 887 * Multi-node revision D (2 nodes per package
888 888 * are supported)
889 889 */
890 890 cpi->cpi_procnodes_per_pkg = 2;
891 891
892 892 first_half = (cpi->cpi_pkgcoreid <=
893 893 (cpi->cpi_ncore_per_chip/2 - 1));
894 894
895 895 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
896 896 /* We are BSP */
897 897 cpi->cpi_procnodeid = (first_half ? 0 : 1);
898 898 } else {
899 899
900 900 /* We are AP */
901 901 /* NodeId[2:1] bits to use for reading F3xe8 */
902 902 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
903 903
904 904 nb_caps_reg =
905 905 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
906 906
907 907 /*
908 908 * Check IntNodeNum bit (31:30, but bit 31 is
909 909 * always 0 on dual-node processors)
910 910 */
911 911 if (BITX(nb_caps_reg, 30, 30) == 0)
912 912 cpi->cpi_procnodeid = node2_1 +
913 913 !first_half;
914 914 else
915 915 cpi->cpi_procnodeid = node2_1 +
916 916 first_half;
917 917 }
918 918 }
919 919 } else {
920 920 cpi->cpi_procnodeid = 0;
921 921 }
922 922
923 923 cpi->cpi_chipid =
924 924 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
925 925 }
926 926
927 927 /*
928 928 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
929 929 */
930 930 void
931 931 setup_xfem(void)
932 932 {
933 933 uint64_t flags = XFEATURE_LEGACY_FP;
934 934
935 935 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
936 936
937 937 if (is_x86_feature(x86_featureset, X86FSET_SSE))
938 938 flags |= XFEATURE_SSE;
939 939
940 940 if (is_x86_feature(x86_featureset, X86FSET_AVX))
941 941 flags |= XFEATURE_AVX;
942 942
943 943 set_xcr(XFEATURE_ENABLED_MASK, flags);
944 944
945 945 xsave_bv_all = flags;
946 946 }
947 947
948 948 void
949 949 cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
950 950 {
951 951 uint32_t mask_ecx, mask_edx;
952 952 struct cpuid_info *cpi;
953 953 struct cpuid_regs *cp;
954 954 int xcpuid;
955 955 #if !defined(__xpv)
956 956 extern int idle_cpu_prefer_mwait;
957 957 #endif
958 958
959 959 /*
960 960 * Space statically allocated for BSP, ensure pointer is set
961 961 */
962 962 if (cpu->cpu_id == 0) {
963 963 if (cpu->cpu_m.mcpu_cpi == NULL)
964 964 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
965 965 }
966 966
967 967 add_x86_feature(featureset, X86FSET_CPUID);
968 968
969 969 cpi = cpu->cpu_m.mcpu_cpi;
970 970 ASSERT(cpi != NULL);
971 971 cp = &cpi->cpi_std[0];
972 972 cp->cp_eax = 0;
973 973 cpi->cpi_maxeax = __cpuid_insn(cp);
974 974 {
975 975 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
976 976 *iptr++ = cp->cp_ebx;
977 977 *iptr++ = cp->cp_edx;
978 978 *iptr++ = cp->cp_ecx;
979 979 *(char *)&cpi->cpi_vendorstr[12] = '\0';
980 980 }
981 981
982 982 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
983 983 x86_vendor = cpi->cpi_vendor; /* for compatibility */
984 984
985 985 /*
986 986 * Limit the range in case of weird hardware
987 987 */
988 988 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
989 989 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
990 990 if (cpi->cpi_maxeax < 1)
991 991 goto pass1_done;
992 992
993 993 cp = &cpi->cpi_std[1];
994 994 cp->cp_eax = 1;
995 995 (void) __cpuid_insn(cp);
996 996
997 997 /*
998 998 * Extract identifying constants for easy access.
999 999 */
1000 1000 cpi->cpi_model = CPI_MODEL(cpi);
1001 1001 cpi->cpi_family = CPI_FAMILY(cpi);
1002 1002
1003 1003 if (cpi->cpi_family == 0xf)
1004 1004 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1005 1005
1006 1006 /*
1007 1007 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
1008 1008 * Intel, and presumably everyone else, uses model == 0xf, as
1009 1009 * one would expect (max value means possible overflow). Sigh.
1010 1010 */
1011 1011
1012 1012 switch (cpi->cpi_vendor) {
1013 1013 case X86_VENDOR_Intel:
1014 1014 if (IS_EXTENDED_MODEL_INTEL(cpi))
1015 1015 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1016 1016 break;
1017 1017 case X86_VENDOR_AMD:
1018 1018 if (CPI_FAMILY(cpi) == 0xf)
1019 1019 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1020 1020 break;
1021 1021 default:
1022 1022 if (cpi->cpi_model == 0xf)
1023 1023 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1024 1024 break;
1025 1025 }
1026 1026
1027 1027 cpi->cpi_step = CPI_STEP(cpi);
1028 1028 cpi->cpi_brandid = CPI_BRANDID(cpi);
1029 1029
1030 1030 /*
1031 1031 * *default* assumptions:
1032 1032 * - believe %edx feature word
1033 1033 * - ignore %ecx feature word
1034 1034 * - 32-bit virtual and physical addressing
1035 1035 */
1036 1036 mask_edx = 0xffffffff;
1037 1037 mask_ecx = 0;
1038 1038
1039 1039 cpi->cpi_pabits = cpi->cpi_vabits = 32;
1040 1040
1041 1041 switch (cpi->cpi_vendor) {
1042 1042 case X86_VENDOR_Intel:
1043 1043 if (cpi->cpi_family == 5)
1044 1044 x86_type = X86_TYPE_P5;
1045 1045 else if (IS_LEGACY_P6(cpi)) {
1046 1046 x86_type = X86_TYPE_P6;
1047 1047 pentiumpro_bug4046376 = 1;
1048 1048 /*
1049 1049 * Clear the SEP bit when it was set erroneously
1050 1050 */
1051 1051 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
1052 1052 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1053 1053 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
1054 1054 x86_type = X86_TYPE_P4;
1055 1055 /*
1056 1056 * We don't currently depend on any of the %ecx
1057 1057 * features until Prescott, so we'll only check
1058 1058 * this from P4 onwards. We might want to revisit
1059 1059 * that idea later.
1060 1060 */
1061 1061 mask_ecx = 0xffffffff;
1062 1062 } else if (cpi->cpi_family > 0xf)
1063 1063 mask_ecx = 0xffffffff;
1064 1064 /*
1065 1065 * We don't support MONITOR/MWAIT if leaf 5 is not available
1066 1066 * to obtain the monitor linesize.
1067 1067 */
1068 1068 if (cpi->cpi_maxeax < 5)
1069 1069 mask_ecx &= ~CPUID_INTC_ECX_MON;
1070 1070 break;
1071 1071 case X86_VENDOR_IntelClone:
1072 1072 default:
1073 1073 break;
1074 1074 case X86_VENDOR_AMD:
1075 1075 #if defined(OPTERON_ERRATUM_108)
1076 1076 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
1077 1077 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
1078 1078 cpi->cpi_model = 0xc;
1079 1079 } else
1080 1080 #endif
1081 1081 if (cpi->cpi_family == 5) {
1082 1082 /*
1083 1083 * AMD K5 and K6
1084 1084 *
1085 1085 * These CPUs have an incomplete implementation
1086 1086 * of MCA/MCE which we mask away.
1087 1087 */
1088 1088 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
1089 1089
1090 1090 /*
1091 1091 * Model 0 uses the wrong (APIC) bit
1092 1092 * to indicate PGE. Fix it here.
1093 1093 */
1094 1094 if (cpi->cpi_model == 0) {
1095 1095 if (cp->cp_edx & 0x200) {
1096 1096 cp->cp_edx &= ~0x200;
1097 1097 cp->cp_edx |= CPUID_INTC_EDX_PGE;
1098 1098 }
1099 1099 }
1100 1100
1101 1101 /*
1102 1102 * Early models had problems w/ MMX; disable.
1103 1103 */
1104 1104 if (cpi->cpi_model < 6)
1105 1105 mask_edx &= ~CPUID_INTC_EDX_MMX;
1106 1106 }
1107 1107
1108 1108 /*
1109 1109 * For newer families, SSE3 and CX16, at least, are valid;
1110 1110 * enable all
1111 1111 */
1112 1112 if (cpi->cpi_family >= 0xf)
1113 1113 mask_ecx = 0xffffffff;
1114 1114 /*
1115 1115 * We don't support MONITOR/MWAIT if leaf 5 is not available
1116 1116 * to obtain the monitor linesize.
1117 1117 */
1118 1118 if (cpi->cpi_maxeax < 5)
1119 1119 mask_ecx &= ~CPUID_INTC_ECX_MON;
1120 1120
1121 1121 #if !defined(__xpv)
1122 1122 /*
1123 1123 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
1124 1124 * processors. AMD does not intend MWAIT to be used in the cpu
1125 1125 * idle loop on current and future processors. 10h and future
1126 1126 * AMD processors use more power in MWAIT than HLT.
1127 1127 * Pre-family-10h Opterons do not have the MWAIT instruction.
1128 1128 */
1129 1129 idle_cpu_prefer_mwait = 0;
1130 1130 #endif
1131 1131
1132 1132 break;
1133 1133 case X86_VENDOR_TM:
1134 1134 /*
1135 1135 * workaround the NT workaround in CMS 4.1
1136 1136 */
1137 1137 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
1138 1138 (cpi->cpi_step == 2 || cpi->cpi_step == 3))
1139 1139 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1140 1140 break;
1141 1141 case X86_VENDOR_Centaur:
1142 1142 /*
1143 1143 * workaround the NT workarounds again
1144 1144 */
1145 1145 if (cpi->cpi_family == 6)
1146 1146 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1147 1147 break;
1148 1148 case X86_VENDOR_Cyrix:
1149 1149 /*
1150 1150 * We rely heavily on the probing in locore
1151 1151 * to actually figure out what parts, if any,
1152 1152 * of the Cyrix cpuid instruction to believe.
1153 1153 */
1154 1154 switch (x86_type) {
1155 1155 case X86_TYPE_CYRIX_486:
1156 1156 mask_edx = 0;
1157 1157 break;
1158 1158 case X86_TYPE_CYRIX_6x86:
1159 1159 mask_edx = 0;
1160 1160 break;
1161 1161 case X86_TYPE_CYRIX_6x86L:
1162 1162 mask_edx =
1163 1163 CPUID_INTC_EDX_DE |
1164 1164 CPUID_INTC_EDX_CX8;
1165 1165 break;
1166 1166 case X86_TYPE_CYRIX_6x86MX:
1167 1167 mask_edx =
1168 1168 CPUID_INTC_EDX_DE |
1169 1169 CPUID_INTC_EDX_MSR |
1170 1170 CPUID_INTC_EDX_CX8 |
1171 1171 CPUID_INTC_EDX_PGE |
1172 1172 CPUID_INTC_EDX_CMOV |
1173 1173 CPUID_INTC_EDX_MMX;
1174 1174 break;
1175 1175 case X86_TYPE_CYRIX_GXm:
1176 1176 mask_edx =
1177 1177 CPUID_INTC_EDX_MSR |
1178 1178 CPUID_INTC_EDX_CX8 |
1179 1179 CPUID_INTC_EDX_CMOV |
1180 1180 CPUID_INTC_EDX_MMX;
1181 1181 break;
1182 1182 case X86_TYPE_CYRIX_MediaGX:
1183 1183 break;
1184 1184 case X86_TYPE_CYRIX_MII:
1185 1185 case X86_TYPE_VIA_CYRIX_III:
1186 1186 mask_edx =
1187 1187 CPUID_INTC_EDX_DE |
1188 1188 CPUID_INTC_EDX_TSC |
1189 1189 CPUID_INTC_EDX_MSR |
1190 1190 CPUID_INTC_EDX_CX8 |
1191 1191 CPUID_INTC_EDX_PGE |
1192 1192 CPUID_INTC_EDX_CMOV |
1193 1193 CPUID_INTC_EDX_MMX;
1194 1194 break;
1195 1195 default:
1196 1196 break;
1197 1197 }
1198 1198 break;
1199 1199 }
1200 1200
1201 1201 #if defined(__xpv)
1202 1202 /*
1203 1203 * Do not support MONITOR/MWAIT under a hypervisor
1204 1204 */
1205 1205 mask_ecx &= ~CPUID_INTC_ECX_MON;
1206 1206 /*
1207 1207 * Do not support XSAVE under a hypervisor for now
1208 1208 */
1209 1209 xsave_force_disable = B_TRUE;
1210 1210
1211 1211 #endif /* __xpv */
1212 1212
1213 1213 if (xsave_force_disable) {
1214 1214 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
1215 1215 mask_ecx &= ~CPUID_INTC_ECX_AVX;
1216 1216 mask_ecx &= ~CPUID_INTC_ECX_F16C;
1217 1217 mask_ecx &= ~CPUID_INTC_ECX_FMA;
1218 1218 }
1219 1219
1220 1220 /*
1221 1221 * Now we've figured out the masks that determine
1222 1222 * which bits we choose to believe, apply the masks
1223 1223 * to the feature words, then map the kernel's view
1224 1224 * of these feature words into its feature word.
1225 1225 */
1226 1226 cp->cp_edx &= mask_edx;
1227 1227 cp->cp_ecx &= mask_ecx;
1228 1228
1229 1229 /*
1230 1230 * apply any platform restrictions (we don't call this
1231 1231 * immediately after __cpuid_insn here, because we need the
1232 1232 * workarounds applied above first)
1233 1233 */
1234 1234 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
1235 1235
1236 1236 /*
1237 1237 * In addition to ecx and edx, Intel is storing a bunch of instruction
1238 1238 * set extensions in leaf 7's ebx.
1239 1239 */
1240 1240 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) {
1241 1241 struct cpuid_regs *ecp;
1242 1242 ecp = &cpi->cpi_std[7];
1243 1243 ecp->cp_eax = 7;
1244 1244 ecp->cp_ecx = 0;
1245 1245 (void) __cpuid_insn(ecp);
1246 1246 /*
1247 1247 * If XSAVE has been disabled, just ignore all of the AVX
1248 1248 * dependent flags here.
1249 1249 */
1250 1250 if (xsave_force_disable) {
1251 1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
1252 1252 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
1253 1253 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
1254 1254 }
1255 1255
1256 1256 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
1257 1257 add_x86_feature(featureset, X86FSET_SMEP);
1258 1258
1259 1259 /*
1260 1260 * We check disable_smap here in addition to in startup_smap()
1261 1261 * to ensure CPUs that aren't the boot CPU don't accidentally
1262 1262 * include it in the feature set and thus generate a mismatched
1263 1263 * x86 feature set across CPUs. Note that at this time we only
1264 1264 * enable SMAP for the 64-bit kernel.
1265 1265 */
1266 1266 #if defined(__amd64)
1267 1267 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMAP &&
1268 1268 disable_smap == 0)
1269 1269 add_x86_feature(featureset, X86FSET_SMAP);
1270 1270 #endif
1271 1271 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED)
1272 1272 add_x86_feature(featureset, X86FSET_RDSEED);
1273 1273
1274 1274 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX)
1275 1275 add_x86_feature(featureset, X86FSET_ADX);
1276 1276 }
1277 1277
1278 1278 /*
1279 1279 * fold in overrides from the "eeprom" mechanism
1280 1280 */
1281 1281 cp->cp_edx |= cpuid_feature_edx_include;
1282 1282 cp->cp_edx &= ~cpuid_feature_edx_exclude;
1283 1283
1284 1284 cp->cp_ecx |= cpuid_feature_ecx_include;
1285 1285 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
1286 1286
1287 1287 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
1288 1288 add_x86_feature(featureset, X86FSET_LARGEPAGE);
1289 1289 }
1290 1290 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
1291 1291 add_x86_feature(featureset, X86FSET_TSC);
1292 1292 }
1293 1293 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
1294 1294 add_x86_feature(featureset, X86FSET_MSR);
1295 1295 }
1296 1296 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
1297 1297 add_x86_feature(featureset, X86FSET_MTRR);
1298 1298 }
1299 1299 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
1300 1300 add_x86_feature(featureset, X86FSET_PGE);
1301 1301 }
1302 1302 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
1303 1303 add_x86_feature(featureset, X86FSET_CMOV);
1304 1304 }
1305 1305 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
1306 1306 add_x86_feature(featureset, X86FSET_MMX);
1307 1307 }
1308 1308 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
1309 1309 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
1310 1310 add_x86_feature(featureset, X86FSET_MCA);
1311 1311 }
1312 1312 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
1313 1313 add_x86_feature(featureset, X86FSET_PAE);
1314 1314 }
1315 1315 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
1316 1316 add_x86_feature(featureset, X86FSET_CX8);
1317 1317 }
1318 1318 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
1319 1319 add_x86_feature(featureset, X86FSET_CX16);
1320 1320 }
1321 1321 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
1322 1322 add_x86_feature(featureset, X86FSET_PAT);
1323 1323 }
1324 1324 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
1325 1325 add_x86_feature(featureset, X86FSET_SEP);
1326 1326 }
1327 1327 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
1328 1328 /*
1329 1329 * In our implementation, fxsave/fxrstor
1330 1330 * are prerequisites before we'll even
1331 1331 * try and do SSE things.
1332 1332 */
1333 1333 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
1334 1334 add_x86_feature(featureset, X86FSET_SSE);
1335 1335 }
1336 1336 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
1337 1337 add_x86_feature(featureset, X86FSET_SSE2);
1338 1338 }
1339 1339 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
1340 1340 add_x86_feature(featureset, X86FSET_SSE3);
1341 1341 }
1342 1342 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
1343 1343 add_x86_feature(featureset, X86FSET_SSSE3);
1344 1344 }
1345 1345 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
1346 1346 add_x86_feature(featureset, X86FSET_SSE4_1);
1347 1347 }
1348 1348 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
1349 1349 add_x86_feature(featureset, X86FSET_SSE4_2);
1350 1350 }
1351 1351 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
1352 1352 add_x86_feature(featureset, X86FSET_AES);
1353 1353 }
1354 1354 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
1355 1355 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
1356 1356 }
1357 1357
1358 1358 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
1359 1359 add_x86_feature(featureset, X86FSET_XSAVE);
1360 1360
1361 1361 /* We only test AVX when there is XSAVE */
1362 1362 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
1363 1363 add_x86_feature(featureset,
1364 1364 X86FSET_AVX);
1365 1365
1366 1366 /*
1367 1367 * Intel says we can't check these without also
1368 1368 * checking AVX.
1369 1369 */
1370 1370 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
1371 1371 add_x86_feature(featureset,
1372 1372 X86FSET_F16C);
1373 1373
1374 1374 if (cp->cp_ecx & CPUID_INTC_ECX_FMA)
1375 1375 add_x86_feature(featureset,
1376 1376 X86FSET_FMA);
1377 1377
1378 1378 if (cpi->cpi_std[7].cp_ebx &
1379 1379 CPUID_INTC_EBX_7_0_BMI1)
1380 1380 add_x86_feature(featureset,
1381 1381 X86FSET_BMI1);
1382 1382
1383 1383 if (cpi->cpi_std[7].cp_ebx &
1384 1384 CPUID_INTC_EBX_7_0_BMI2)
1385 1385 add_x86_feature(featureset,
1386 1386 X86FSET_BMI2);
1387 1387
1388 1388 if (cpi->cpi_std[7].cp_ebx &
1389 1389 CPUID_INTC_EBX_7_0_AVX2)
1390 1390 add_x86_feature(featureset,
1391 1391 X86FSET_AVX2);
1392 1392 }
1393 1393 }
1394 1394 }
1395 1395 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
1396 1396 add_x86_feature(featureset, X86FSET_X2APIC);
1397 1397 }
1398 1398 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
1399 1399 add_x86_feature(featureset, X86FSET_DE);
1400 1400 }
1401 1401 #if !defined(__xpv)
1402 1402 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
1403 1403
1404 1404 /*
1405 1405 * We require the CLFLUSH instruction for erratum workaround
1406 1406 * to use MONITOR/MWAIT.
1407 1407 */
1408 1408 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1409 1409 cpi->cpi_mwait.support |= MWAIT_SUPPORT;
1410 1410 add_x86_feature(featureset, X86FSET_MWAIT);
1411 1411 } else {
1412 1412 extern int idle_cpu_assert_cflush_monitor;
1413 1413
1414 1414 /*
1415 1415 * All processors we are aware of which have
1416 1416 * MONITOR/MWAIT also have CLFLUSH.
1417 1417 */
1418 1418 if (idle_cpu_assert_cflush_monitor) {
1419 1419 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
1420 1420 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
1421 1421 }
1422 1422 }
1423 1423 }
1424 1424 #endif /* __xpv */
1425 1425
1426 1426 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
1427 1427 add_x86_feature(featureset, X86FSET_VMX);
1428 1428 }
1429 1429
1430 1430 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
1431 1431 add_x86_feature(featureset, X86FSET_RDRAND);
1432 1432
1433 1433 /*
1434 1434 * Only need it first time, rest of the cpus would follow suit.
1435 1435 * we only capture this for the bootcpu.
1436 1436 */
1437 1437 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1438 1438 add_x86_feature(featureset, X86FSET_CLFSH);
1439 1439 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
1440 1440 }
1441 1441 if (is_x86_feature(featureset, X86FSET_PAE))
1442 1442 cpi->cpi_pabits = 36;
1443 1443
1444 1444 /*
1445 1445 * Hyperthreading configuration is slightly tricky on Intel
1446 1446 * and pure clones, and even trickier on AMD.
1447 1447 *
1448 1448 * (AMD chose to set the HTT bit on their CMP processors,
1449 1449 * even though they're not actually hyperthreaded. Thus it
1450 1450 * takes a bit more work to figure out what's really going
1451 1451 * on ... see the handling of the CMP_LGCY bit below)
1452 1452 */
1453 1453 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
1454 1454 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
1455 1455 if (cpi->cpi_ncpu_per_chip > 1)
1456 1456 add_x86_feature(featureset, X86FSET_HTT);
1457 1457 } else {
1458 1458 cpi->cpi_ncpu_per_chip = 1;
1459 1459 }
1460 1460
1461 1461 /*
1462 1462 * Work on the "extended" feature information, doing
1463 1463 * some basic initialization for cpuid_pass2()
1464 1464 */
1465 1465 xcpuid = 0;
1466 1466 switch (cpi->cpi_vendor) {
1467 1467 case X86_VENDOR_Intel:
1468 1468 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
1469 1469 xcpuid++;
1470 1470 break;
1471 1471 case X86_VENDOR_AMD:
1472 1472 if (cpi->cpi_family > 5 ||
1473 1473 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
1474 1474 xcpuid++;
1475 1475 break;
1476 1476 case X86_VENDOR_Cyrix:
1477 1477 /*
1478 1478 * Only these Cyrix CPUs are -known- to support
1479 1479 * extended cpuid operations.
1480 1480 */
1481 1481 if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1482 1482 x86_type == X86_TYPE_CYRIX_GXm)
1483 1483 xcpuid++;
1484 1484 break;
1485 1485 case X86_VENDOR_Centaur:
1486 1486 case X86_VENDOR_TM:
1487 1487 default:
1488 1488 xcpuid++;
1489 1489 break;
1490 1490 }
1491 1491
1492 1492 if (xcpuid) {
1493 1493 cp = &cpi->cpi_extd[0];
1494 1494 cp->cp_eax = 0x80000000;
1495 1495 cpi->cpi_xmaxeax = __cpuid_insn(cp);
1496 1496 }
1497 1497
1498 1498 if (cpi->cpi_xmaxeax & 0x80000000) {
1499 1499
1500 1500 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1501 1501 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1502 1502
1503 1503 switch (cpi->cpi_vendor) {
1504 1504 case X86_VENDOR_Intel:
1505 1505 case X86_VENDOR_AMD:
1506 1506 if (cpi->cpi_xmaxeax < 0x80000001)
1507 1507 break;
1508 1508 cp = &cpi->cpi_extd[1];
1509 1509 cp->cp_eax = 0x80000001;
1510 1510 (void) __cpuid_insn(cp);
1511 1511
1512 1512 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1513 1513 cpi->cpi_family == 5 &&
1514 1514 cpi->cpi_model == 6 &&
1515 1515 cpi->cpi_step == 6) {
1516 1516 /*
1517 1517 * K6 model 6 uses bit 10 to indicate SYSC
1518 1518 * Later models use bit 11. Fix it here.
1519 1519 */
1520 1520 if (cp->cp_edx & 0x400) {
1521 1521 cp->cp_edx &= ~0x400;
1522 1522 cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1523 1523 }
1524 1524 }
1525 1525
1526 1526 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1527 1527
1528 1528 /*
1529 1529 * Compute the additions to the kernel's feature word.
1530 1530 */
1531 1531 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
1532 1532 add_x86_feature(featureset, X86FSET_NX);
1533 1533 }
1534 1534
1535 1535 /*
1536 1536 * Regardless whether or not we boot 64-bit,
1537 1537 * we should have a way to identify whether
1538 1538 * the CPU is capable of running 64-bit.
1539 1539 */
1540 1540 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
1541 1541 add_x86_feature(featureset, X86FSET_64);
1542 1542 }
1543 1543
1544 1544 #if defined(__amd64)
1545 1545 /* 1 GB large page - enable only for 64 bit kernel */
1546 1546 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
1547 1547 add_x86_feature(featureset, X86FSET_1GPG);
1548 1548 }
1549 1549 #endif
1550 1550
1551 1551 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1552 1552 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1553 1553 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
1554 1554 add_x86_feature(featureset, X86FSET_SSE4A);
1555 1555 }
1556 1556
1557 1557 /*
1558 1558 * If both the HTT and CMP_LGCY bits are set,
1559 1559 * then we're not actually HyperThreaded. Read
1560 1560 * "AMD CPUID Specification" for more details.
1561 1561 */
1562 1562 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1563 1563 is_x86_feature(featureset, X86FSET_HTT) &&
1564 1564 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1565 1565 remove_x86_feature(featureset, X86FSET_HTT);
1566 1566 add_x86_feature(featureset, X86FSET_CMP);
1567 1567 }
1568 1568 #if defined(__amd64)
1569 1569 /*
1570 1570 * It's really tricky to support syscall/sysret in
1571 1571 * the i386 kernel; we rely on sysenter/sysexit
1572 1572 * instead. In the amd64 kernel, things are -way-
1573 1573 * better.
1574 1574 */
1575 1575 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1576 1576 add_x86_feature(featureset, X86FSET_ASYSC);
1577 1577 }
1578 1578
1579 1579 /*
1580 1580 * While we're thinking about system calls, note
1581 1581 * that AMD processors don't support sysenter
1582 1582 * in long mode at all, so don't try to program them.
1583 1583 */
1584 1584 if (x86_vendor == X86_VENDOR_AMD) {
1585 1585 remove_x86_feature(featureset, X86FSET_SEP);
1586 1586 }
1587 1587 #endif
1588 1588 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1589 1589 add_x86_feature(featureset, X86FSET_TSCP);
1590 1590 }
1591 1591
1592 1592 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1593 1593 add_x86_feature(featureset, X86FSET_SVM);
1594 1594 }
1595 1595
1596 1596 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1597 1597 add_x86_feature(featureset, X86FSET_TOPOEXT);
1598 1598 }
1599 1599 break;
1600 1600 default:
1601 1601 break;
1602 1602 }
1603 1603
1604 1604 /*
1605 1605 * Get CPUID data about processor cores and hyperthreads.
1606 1606 */
1607 1607 switch (cpi->cpi_vendor) {
1608 1608 case X86_VENDOR_Intel:
1609 1609 if (cpi->cpi_maxeax >= 4) {
1610 1610 cp = &cpi->cpi_std[4];
1611 1611 cp->cp_eax = 4;
1612 1612 cp->cp_ecx = 0;
1613 1613 (void) __cpuid_insn(cp);
1614 1614 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1615 1615 }
1616 1616 /*FALLTHROUGH*/
1617 1617 case X86_VENDOR_AMD:
1618 1618 if (cpi->cpi_xmaxeax < 0x80000008)
1619 1619 break;
1620 1620 cp = &cpi->cpi_extd[8];
1621 1621 cp->cp_eax = 0x80000008;
1622 1622 (void) __cpuid_insn(cp);
1623 1623 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1624 1624
1625 1625 /*
1626 1626 * Virtual and physical address limits from
1627 1627 * cpuid override previously guessed values.
1628 1628 */
1629 1629 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1630 1630 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1631 1631 break;
1632 1632 default:
1633 1633 break;
1634 1634 }
1635 1635
1636 1636 /*
1637 1637 * Derive the number of cores per chip
1638 1638 */
1639 1639 switch (cpi->cpi_vendor) {
1640 1640 case X86_VENDOR_Intel:
1641 1641 if (cpi->cpi_maxeax < 4) {
1642 1642 cpi->cpi_ncore_per_chip = 1;
1643 1643 break;
1644 1644 } else {
1645 1645 cpi->cpi_ncore_per_chip =
1646 1646 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1647 1647 }
1648 1648 break;
1649 1649 case X86_VENDOR_AMD:
1650 1650 if (cpi->cpi_xmaxeax < 0x80000008) {
1651 1651 cpi->cpi_ncore_per_chip = 1;
1652 1652 break;
1653 1653 } else {
1654 1654 /*
1655 1655 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1656 1656 * 1 less than the number of physical cores on
1657 1657 * the chip. In family 0x10 this value can
1658 1658 * be affected by "downcoring" - it reflects
1659 1659 * 1 less than the number of cores actually
1660 1660 * enabled on this node.
1661 1661 */
1662 1662 cpi->cpi_ncore_per_chip =
1663 1663 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1664 1664 }
1665 1665 break;
1666 1666 default:
1667 1667 cpi->cpi_ncore_per_chip = 1;
1668 1668 break;
1669 1669 }
1670 1670
1671 1671 /*
1672 1672 * Get CPUID data about TSC Invariance in Deep C-State.
1673 1673 */
1674 1674 switch (cpi->cpi_vendor) {
1675 1675 case X86_VENDOR_Intel:
1676 1676 if (cpi->cpi_maxeax >= 7) {
1677 1677 cp = &cpi->cpi_extd[7];
1678 1678 cp->cp_eax = 0x80000007;
1679 1679 cp->cp_ecx = 0;
1680 1680 (void) __cpuid_insn(cp);
1681 1681 }
1682 1682 break;
1683 1683 default:
1684 1684 break;
1685 1685 }
1686 1686 } else {
1687 1687 cpi->cpi_ncore_per_chip = 1;
1688 1688 }
1689 1689
1690 1690 /*
1691 1691 * If more than one core, then this processor is CMP.
1692 1692 */
1693 1693 if (cpi->cpi_ncore_per_chip > 1) {
1694 1694 add_x86_feature(featureset, X86FSET_CMP);
1695 1695 }
1696 1696
1697 1697 /*
1698 1698 * If the number of cores is the same as the number
1699 1699 * of CPUs, then we cannot have HyperThreading.
1700 1700 */
1701 1701 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1702 1702 remove_x86_feature(featureset, X86FSET_HTT);
1703 1703 }
1704 1704
1705 1705 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1706 1706 cpi->cpi_procnodes_per_pkg = 1;
1707 1707 cpi->cpi_cores_per_compunit = 1;
1708 1708 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1709 1709 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1710 1710 /*
1711 1711 * Single-core single-threaded processors.
1712 1712 */
1713 1713 cpi->cpi_chipid = -1;
1714 1714 cpi->cpi_clogid = 0;
1715 1715 cpi->cpi_coreid = cpu->cpu_id;
1716 1716 cpi->cpi_pkgcoreid = 0;
1717 1717 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1718 1718 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1719 1719 else
1720 1720 cpi->cpi_procnodeid = cpi->cpi_chipid;
1721 1721 } else if (cpi->cpi_ncpu_per_chip > 1) {
1722 1722 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1723 1723 cpuid_intel_getids(cpu, featureset);
1724 1724 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1725 1725 cpuid_amd_getids(cpu);
1726 1726 else {
1727 1727 /*
1728 1728 * All other processors are currently
1729 1729 * assumed to have single cores.
1730 1730 */
1731 1731 cpi->cpi_coreid = cpi->cpi_chipid;
1732 1732 cpi->cpi_pkgcoreid = 0;
1733 1733 cpi->cpi_procnodeid = cpi->cpi_chipid;
1734 1734 cpi->cpi_compunitid = cpi->cpi_chipid;
1735 1735 }
1736 1736 }
1737 1737
1738 1738 /*
1739 1739 * Synthesize chip "revision" and socket type
1740 1740 */
1741 1741 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1742 1742 cpi->cpi_model, cpi->cpi_step);
1743 1743 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1744 1744 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1745 1745 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1746 1746 cpi->cpi_model, cpi->cpi_step);
1747 1747
1748 1748 pass1_done:
1749 1749 cpi->cpi_pass = 1;
1750 1750 }
1751 1751
1752 1752 /*
1753 1753 * Make copies of the cpuid table entries we depend on, in
1754 1754 * part for ease of parsing now, in part so that we have only
1755 1755 * one place to correct any of it, in part for ease of
1756 1756 * later export to userland, and in part so we can look at
1757 1757 * this stuff in a crash dump.
1758 1758 */
1759 1759
1760 1760 /*ARGSUSED*/
1761 1761 void
1762 1762 cpuid_pass2(cpu_t *cpu)
1763 1763 {
1764 1764 uint_t n, nmax;
1765 1765 int i;
1766 1766 struct cpuid_regs *cp;
1767 1767 uint8_t *dp;
1768 1768 uint32_t *iptr;
1769 1769 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1770 1770
1771 1771 ASSERT(cpi->cpi_pass == 1);
1772 1772
1773 1773 if (cpi->cpi_maxeax < 1)
1774 1774 goto pass2_done;
1775 1775
1776 1776 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1777 1777 nmax = NMAX_CPI_STD;
1778 1778 /*
1779 1779 * (We already handled n == 0 and n == 1 in pass 1)
1780 1780 */
1781 1781 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1782 1782 cp->cp_eax = n;
1783 1783
1784 1784 /*
1785 1785 * CPUID function 4 expects %ecx to be initialized
1786 1786 * with an index which indicates which cache to return
1787 1787 * information about. The OS is expected to call function 4
1788 1788 * with %ecx set to 0, 1, 2, ... until it returns with
1789 1789 * EAX[4:0] set to 0, which indicates there are no more
1790 1790 * caches.
1791 1791 *
1792 1792 * Here, populate cpi_std[4] with the information returned by
1793 1793 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1794 1794 * when dynamic memory allocation becomes available.
1795 1795 *
1796 1796 * Note: we need to explicitly initialize %ecx here, since
1797 1797 * function 4 may have been previously invoked.
1798 1798 */
1799 1799 if (n == 4)
1800 1800 cp->cp_ecx = 0;
1801 1801
1802 1802 (void) __cpuid_insn(cp);
1803 1803 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1804 1804 switch (n) {
1805 1805 case 2:
1806 1806 /*
1807 1807 * "the lower 8 bits of the %eax register
1808 1808 * contain a value that identifies the number
1809 1809 * of times the cpuid [instruction] has to be
1810 1810 * executed to obtain a complete image of the
1811 1811 * processor's caching systems."
1812 1812 *
1813 1813 * How *do* they make this stuff up?
1814 1814 */
1815 1815 cpi->cpi_ncache = sizeof (*cp) *
1816 1816 BITX(cp->cp_eax, 7, 0);
1817 1817 if (cpi->cpi_ncache == 0)
1818 1818 break;
1819 1819 cpi->cpi_ncache--; /* skip count byte */
1820 1820
1821 1821 /*
1822 1822 * Well, for now, rather than attempt to implement
1823 1823 * this slightly dubious algorithm, we just look
1824 1824 * at the first 15 ..
1825 1825 */
1826 1826 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1827 1827 cpi->cpi_ncache = sizeof (*cp) - 1;
1828 1828
1829 1829 dp = cpi->cpi_cacheinfo;
1830 1830 if (BITX(cp->cp_eax, 31, 31) == 0) {
1831 1831 uint8_t *p = (void *)&cp->cp_eax;
1832 1832 for (i = 1; i < 4; i++)
1833 1833 if (p[i] != 0)
1834 1834 *dp++ = p[i];
1835 1835 }
1836 1836 if (BITX(cp->cp_ebx, 31, 31) == 0) {
1837 1837 uint8_t *p = (void *)&cp->cp_ebx;
1838 1838 for (i = 0; i < 4; i++)
1839 1839 if (p[i] != 0)
1840 1840 *dp++ = p[i];
1841 1841 }
1842 1842 if (BITX(cp->cp_ecx, 31, 31) == 0) {
1843 1843 uint8_t *p = (void *)&cp->cp_ecx;
1844 1844 for (i = 0; i < 4; i++)
1845 1845 if (p[i] != 0)
1846 1846 *dp++ = p[i];
1847 1847 }
1848 1848 if (BITX(cp->cp_edx, 31, 31) == 0) {
1849 1849 uint8_t *p = (void *)&cp->cp_edx;
1850 1850 for (i = 0; i < 4; i++)
1851 1851 if (p[i] != 0)
1852 1852 *dp++ = p[i];
1853 1853 }
1854 1854 break;
1855 1855
1856 1856 case 3: /* Processor serial number, if PSN supported */
1857 1857 break;
1858 1858
1859 1859 case 4: /* Deterministic cache parameters */
1860 1860 break;
1861 1861
1862 1862 case 5: /* Monitor/Mwait parameters */
1863 1863 {
1864 1864 size_t mwait_size;
1865 1865
1866 1866 /*
1867 1867 * check cpi_mwait.support which was set in cpuid_pass1
1868 1868 */
1869 1869 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
1870 1870 break;
1871 1871
1872 1872 /*
1873 1873 * Protect ourself from insane mwait line size.
1874 1874 * Workaround for incomplete hardware emulator(s).
1875 1875 */
1876 1876 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
1877 1877 if (mwait_size < sizeof (uint32_t) ||
1878 1878 !ISP2(mwait_size)) {
1879 1879 #if DEBUG
1880 1880 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
1881 1881 "size %ld", cpu->cpu_id, (long)mwait_size);
1882 1882 #endif
1883 1883 break;
1884 1884 }
1885 1885
1886 1886 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
1887 1887 cpi->cpi_mwait.mon_max = mwait_size;
1888 1888 if (MWAIT_EXTENSION(cpi)) {
1889 1889 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
1890 1890 if (MWAIT_INT_ENABLE(cpi))
1891 1891 cpi->cpi_mwait.support |=
1892 1892 MWAIT_ECX_INT_ENABLE;
1893 1893 }
1894 1894 break;
1895 1895 }
1896 1896 default:
1897 1897 break;
1898 1898 }
1899 1899 }
1900 1900
1901 1901 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
1902 1902 struct cpuid_regs regs;
1903 1903
1904 1904 cp = ®s;
1905 1905 cp->cp_eax = 0xB;
1906 1906 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1907 1907
1908 1908 (void) __cpuid_insn(cp);
1909 1909
1910 1910 /*
1911 1911 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
1912 1912 * indicates that the extended topology enumeration leaf is
1913 1913 * available.
1914 1914 */
1915 1915 if (cp->cp_ebx) {
1916 1916 uint32_t x2apic_id;
1917 1917 uint_t coreid_shift = 0;
1918 1918 uint_t ncpu_per_core = 1;
1919 1919 uint_t chipid_shift = 0;
1920 1920 uint_t ncpu_per_chip = 1;
1921 1921 uint_t i;
1922 1922 uint_t level;
1923 1923
1924 1924 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
1925 1925 cp->cp_eax = 0xB;
1926 1926 cp->cp_ecx = i;
1927 1927
1928 1928 (void) __cpuid_insn(cp);
1929 1929 level = CPI_CPU_LEVEL_TYPE(cp);
1930 1930
1931 1931 if (level == 1) {
1932 1932 x2apic_id = cp->cp_edx;
1933 1933 coreid_shift = BITX(cp->cp_eax, 4, 0);
1934 1934 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
1935 1935 } else if (level == 2) {
1936 1936 x2apic_id = cp->cp_edx;
1937 1937 chipid_shift = BITX(cp->cp_eax, 4, 0);
1938 1938 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
1939 1939 }
1940 1940 }
1941 1941
1942 1942 cpi->cpi_apicid = x2apic_id;
1943 1943 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
1944 1944 cpi->cpi_ncore_per_chip = ncpu_per_chip /
1945 1945 ncpu_per_core;
1946 1946 cpi->cpi_chipid = x2apic_id >> chipid_shift;
1947 1947 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
1948 1948 cpi->cpi_coreid = x2apic_id >> coreid_shift;
1949 1949 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
1950 1950 }
1951 1951
1952 1952 /* Make cp NULL so that we don't stumble on others */
1953 1953 cp = NULL;
1954 1954 }
1955 1955
1956 1956 /*
1957 1957 * XSAVE enumeration
1958 1958 */
1959 1959 if (cpi->cpi_maxeax >= 0xD) {
1960 1960 struct cpuid_regs regs;
1961 1961 boolean_t cpuid_d_valid = B_TRUE;
1962 1962
1963 1963 cp = ®s;
1964 1964 cp->cp_eax = 0xD;
1965 1965 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1966 1966
1967 1967 (void) __cpuid_insn(cp);
1968 1968
1969 1969 /*
1970 1970 * Sanity checks for debug
1971 1971 */
1972 1972 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 ||
1973 1973 (cp->cp_eax & XFEATURE_SSE) == 0) {
1974 1974 cpuid_d_valid = B_FALSE;
1975 1975 }
1976 1976
1977 1977 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
1978 1978 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
1979 1979 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
1980 1980
1981 1981 /*
1982 1982 * If the hw supports AVX, get the size and offset in the save
1983 1983 * area for the ymm state.
1984 1984 */
1985 1985 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
1986 1986 cp->cp_eax = 0xD;
1987 1987 cp->cp_ecx = 2;
1988 1988 cp->cp_edx = cp->cp_ebx = 0;
1989 1989
1990 1990 (void) __cpuid_insn(cp);
1991 1991
1992 1992 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET ||
1993 1993 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
1994 1994 cpuid_d_valid = B_FALSE;
1995 1995 }
1996 1996
1997 1997 cpi->cpi_xsave.ymm_size = cp->cp_eax;
1998 1998 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
1999 1999 }
2000 2000
2001 2001 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
2002 2002 xsave_state_size = 0;
2003 2003 } else if (cpuid_d_valid) {
2004 2004 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
2005 2005 } else {
2006 2006 /* Broken CPUID 0xD, probably in HVM */
2007 2007 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
2008 2008 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
2009 2009 ", ymm_size = %d, ymm_offset = %d\n",
2010 2010 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
2011 2011 cpi->cpi_xsave.xsav_hw_features_high,
2012 2012 (int)cpi->cpi_xsave.xsav_max_size,
2013 2013 (int)cpi->cpi_xsave.ymm_size,
2014 2014 (int)cpi->cpi_xsave.ymm_offset);
2015 2015
2016 2016 if (xsave_state_size != 0) {
2017 2017 /*
2018 2018 * This must be a non-boot CPU. We cannot
2019 2019 * continue, because boot cpu has already
2020 2020 * enabled XSAVE.
2021 2021 */
2022 2022 ASSERT(cpu->cpu_id != 0);
2023 2023 cmn_err(CE_PANIC, "cpu%d: we have already "
2024 2024 "enabled XSAVE on boot cpu, cannot "
2025 2025 "continue.", cpu->cpu_id);
2026 2026 } else {
2027 2027 /*
2028 2028 * If we reached here on the boot CPU, it's also
2029 2029 * almost certain that we'll reach here on the
2030 2030 * non-boot CPUs. When we're here on a boot CPU
2031 2031 * we should disable the feature, on a non-boot
2032 2032 * CPU we need to confirm that we have.
2033 2033 */
2034 2034 if (cpu->cpu_id == 0) {
2035 2035 remove_x86_feature(x86_featureset,
2036 2036 X86FSET_XSAVE);
2037 2037 remove_x86_feature(x86_featureset,
2038 2038 X86FSET_AVX);
2039 2039 remove_x86_feature(x86_featureset,
2040 2040 X86FSET_F16C);
2041 2041 remove_x86_feature(x86_featureset,
2042 2042 X86FSET_BMI1);
2043 2043 remove_x86_feature(x86_featureset,
2044 2044 X86FSET_BMI2);
2045 2045 remove_x86_feature(x86_featureset,
2046 2046 X86FSET_FMA);
2047 2047 remove_x86_feature(x86_featureset,
2048 2048 X86FSET_AVX2);
2049 2049 CPI_FEATURES_ECX(cpi) &=
2050 2050 ~CPUID_INTC_ECX_XSAVE;
2051 2051 CPI_FEATURES_ECX(cpi) &=
2052 2052 ~CPUID_INTC_ECX_AVX;
2053 2053 CPI_FEATURES_ECX(cpi) &=
2054 2054 ~CPUID_INTC_ECX_F16C;
2055 2055 CPI_FEATURES_ECX(cpi) &=
2056 2056 ~CPUID_INTC_ECX_FMA;
2057 2057 CPI_FEATURES_7_0_EBX(cpi) &=
2058 2058 ~CPUID_INTC_EBX_7_0_BMI1;
2059 2059 CPI_FEATURES_7_0_EBX(cpi) &=
2060 2060 ~CPUID_INTC_EBX_7_0_BMI2;
2061 2061 CPI_FEATURES_7_0_EBX(cpi) &=
2062 2062 ~CPUID_INTC_EBX_7_0_AVX2;
2063 2063 xsave_force_disable = B_TRUE;
2064 2064 } else {
2065 2065 VERIFY(is_x86_feature(x86_featureset,
2066 2066 X86FSET_XSAVE) == B_FALSE);
2067 2067 }
2068 2068 }
2069 2069 }
2070 2070 }
2071 2071
2072 2072
2073 2073 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
2074 2074 goto pass2_done;
2075 2075
2076 2076 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
2077 2077 nmax = NMAX_CPI_EXTD;
2078 2078 /*
2079 2079 * Copy the extended properties, fixing them as we go.
2080 2080 * (We already handled n == 0 and n == 1 in pass 1)
2081 2081 */
2082 2082 iptr = (void *)cpi->cpi_brandstr;
2083 2083 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
2084 2084 cp->cp_eax = 0x80000000 + n;
2085 2085 (void) __cpuid_insn(cp);
2086 2086 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
2087 2087 switch (n) {
2088 2088 case 2:
2089 2089 case 3:
2090 2090 case 4:
2091 2091 /*
2092 2092 * Extract the brand string
2093 2093 */
2094 2094 *iptr++ = cp->cp_eax;
2095 2095 *iptr++ = cp->cp_ebx;
2096 2096 *iptr++ = cp->cp_ecx;
2097 2097 *iptr++ = cp->cp_edx;
2098 2098 break;
2099 2099 case 5:
2100 2100 switch (cpi->cpi_vendor) {
2101 2101 case X86_VENDOR_AMD:
2102 2102 /*
2103 2103 * The Athlon and Duron were the first
2104 2104 * parts to report the sizes of the
2105 2105 * TLB for large pages. Before then,
2106 2106 * we don't trust the data.
2107 2107 */
2108 2108 if (cpi->cpi_family < 6 ||
2109 2109 (cpi->cpi_family == 6 &&
2110 2110 cpi->cpi_model < 1))
2111 2111 cp->cp_eax = 0;
2112 2112 break;
2113 2113 default:
2114 2114 break;
2115 2115 }
2116 2116 break;
2117 2117 case 6:
2118 2118 switch (cpi->cpi_vendor) {
2119 2119 case X86_VENDOR_AMD:
2120 2120 /*
2121 2121 * The Athlon and Duron were the first
2122 2122 * AMD parts with L2 TLB's.
2123 2123 * Before then, don't trust the data.
2124 2124 */
2125 2125 if (cpi->cpi_family < 6 ||
2126 2126 cpi->cpi_family == 6 &&
2127 2127 cpi->cpi_model < 1)
2128 2128 cp->cp_eax = cp->cp_ebx = 0;
2129 2129 /*
2130 2130 * AMD Duron rev A0 reports L2
2131 2131 * cache size incorrectly as 1K
2132 2132 * when it is really 64K
2133 2133 */
2134 2134 if (cpi->cpi_family == 6 &&
2135 2135 cpi->cpi_model == 3 &&
2136 2136 cpi->cpi_step == 0) {
2137 2137 cp->cp_ecx &= 0xffff;
2138 2138 cp->cp_ecx |= 0x400000;
2139 2139 }
2140 2140 break;
2141 2141 case X86_VENDOR_Cyrix: /* VIA C3 */
2142 2142 /*
2143 2143 * VIA C3 processors are a bit messed
2144 2144 * up w.r.t. encoding cache sizes in %ecx
2145 2145 */
2146 2146 if (cpi->cpi_family != 6)
2147 2147 break;
2148 2148 /*
2149 2149 * model 7 and 8 were incorrectly encoded
2150 2150 *
2151 2151 * xxx is model 8 really broken?
2152 2152 */
2153 2153 if (cpi->cpi_model == 7 ||
2154 2154 cpi->cpi_model == 8)
2155 2155 cp->cp_ecx =
2156 2156 BITX(cp->cp_ecx, 31, 24) << 16 |
2157 2157 BITX(cp->cp_ecx, 23, 16) << 12 |
2158 2158 BITX(cp->cp_ecx, 15, 8) << 8 |
2159 2159 BITX(cp->cp_ecx, 7, 0);
2160 2160 /*
2161 2161 * model 9 stepping 1 has wrong associativity
2162 2162 */
2163 2163 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
2164 2164 cp->cp_ecx |= 8 << 12;
2165 2165 break;
2166 2166 case X86_VENDOR_Intel:
2167 2167 /*
2168 2168 * Extended L2 Cache features function.
2169 2169 * First appeared on Prescott.
2170 2170 */
2171 2171 default:
2172 2172 break;
2173 2173 }
2174 2174 break;
2175 2175 default:
2176 2176 break;
2177 2177 }
2178 2178 }
2179 2179
2180 2180 pass2_done:
2181 2181 cpi->cpi_pass = 2;
2182 2182 }
2183 2183
2184 2184 static const char *
2185 2185 intel_cpubrand(const struct cpuid_info *cpi)
2186 2186 {
2187 2187 int i;
2188 2188
2189 2189 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2190 2190 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2191 2191 return ("i486");
2192 2192
2193 2193 switch (cpi->cpi_family) {
2194 2194 case 5:
2195 2195 return ("Intel Pentium(r)");
2196 2196 case 6:
2197 2197 switch (cpi->cpi_model) {
2198 2198 uint_t celeron, xeon;
2199 2199 const struct cpuid_regs *cp;
2200 2200 case 0:
2201 2201 case 1:
2202 2202 case 2:
2203 2203 return ("Intel Pentium(r) Pro");
2204 2204 case 3:
2205 2205 case 4:
2206 2206 return ("Intel Pentium(r) II");
2207 2207 case 6:
2208 2208 return ("Intel Celeron(r)");
2209 2209 case 5:
2210 2210 case 7:
2211 2211 celeron = xeon = 0;
2212 2212 cp = &cpi->cpi_std[2]; /* cache info */
2213 2213
2214 2214 for (i = 1; i < 4; i++) {
2215 2215 uint_t tmp;
2216 2216
2217 2217 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
2218 2218 if (tmp == 0x40)
2219 2219 celeron++;
2220 2220 if (tmp >= 0x44 && tmp <= 0x45)
2221 2221 xeon++;
2222 2222 }
2223 2223
2224 2224 for (i = 0; i < 2; i++) {
2225 2225 uint_t tmp;
2226 2226
2227 2227 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
2228 2228 if (tmp == 0x40)
2229 2229 celeron++;
2230 2230 else if (tmp >= 0x44 && tmp <= 0x45)
2231 2231 xeon++;
2232 2232 }
2233 2233
2234 2234 for (i = 0; i < 4; i++) {
2235 2235 uint_t tmp;
2236 2236
2237 2237 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
2238 2238 if (tmp == 0x40)
2239 2239 celeron++;
2240 2240 else if (tmp >= 0x44 && tmp <= 0x45)
2241 2241 xeon++;
2242 2242 }
2243 2243
2244 2244 for (i = 0; i < 4; i++) {
2245 2245 uint_t tmp;
2246 2246
2247 2247 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
2248 2248 if (tmp == 0x40)
2249 2249 celeron++;
2250 2250 else if (tmp >= 0x44 && tmp <= 0x45)
2251 2251 xeon++;
2252 2252 }
2253 2253
2254 2254 if (celeron)
2255 2255 return ("Intel Celeron(r)");
2256 2256 if (xeon)
2257 2257 return (cpi->cpi_model == 5 ?
2258 2258 "Intel Pentium(r) II Xeon(tm)" :
2259 2259 "Intel Pentium(r) III Xeon(tm)");
2260 2260 return (cpi->cpi_model == 5 ?
2261 2261 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
2262 2262 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
2263 2263 default:
2264 2264 break;
2265 2265 }
2266 2266 default:
2267 2267 break;
2268 2268 }
2269 2269
2270 2270 /* BrandID is present if the field is nonzero */
2271 2271 if (cpi->cpi_brandid != 0) {
2272 2272 static const struct {
2273 2273 uint_t bt_bid;
2274 2274 const char *bt_str;
2275 2275 } brand_tbl[] = {
2276 2276 { 0x1, "Intel(r) Celeron(r)" },
2277 2277 { 0x2, "Intel(r) Pentium(r) III" },
2278 2278 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
2279 2279 { 0x4, "Intel(r) Pentium(r) III" },
2280 2280 { 0x6, "Mobile Intel(r) Pentium(r) III" },
2281 2281 { 0x7, "Mobile Intel(r) Celeron(r)" },
2282 2282 { 0x8, "Intel(r) Pentium(r) 4" },
2283 2283 { 0x9, "Intel(r) Pentium(r) 4" },
2284 2284 { 0xa, "Intel(r) Celeron(r)" },
2285 2285 { 0xb, "Intel(r) Xeon(tm)" },
2286 2286 { 0xc, "Intel(r) Xeon(tm) MP" },
2287 2287 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
2288 2288 { 0xf, "Mobile Intel(r) Celeron(r)" },
2289 2289 { 0x11, "Mobile Genuine Intel(r)" },
2290 2290 { 0x12, "Intel(r) Celeron(r) M" },
2291 2291 { 0x13, "Mobile Intel(r) Celeron(r)" },
2292 2292 { 0x14, "Intel(r) Celeron(r)" },
2293 2293 { 0x15, "Mobile Genuine Intel(r)" },
2294 2294 { 0x16, "Intel(r) Pentium(r) M" },
2295 2295 { 0x17, "Mobile Intel(r) Celeron(r)" }
2296 2296 };
2297 2297 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
2298 2298 uint_t sgn;
2299 2299
2300 2300 sgn = (cpi->cpi_family << 8) |
2301 2301 (cpi->cpi_model << 4) | cpi->cpi_step;
2302 2302
2303 2303 for (i = 0; i < btblmax; i++)
2304 2304 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
2305 2305 break;
2306 2306 if (i < btblmax) {
2307 2307 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
2308 2308 return ("Intel(r) Celeron(r)");
2309 2309 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
2310 2310 return ("Intel(r) Xeon(tm) MP");
2311 2311 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
2312 2312 return ("Intel(r) Xeon(tm)");
2313 2313 return (brand_tbl[i].bt_str);
2314 2314 }
2315 2315 }
2316 2316
2317 2317 return (NULL);
2318 2318 }
2319 2319
2320 2320 static const char *
2321 2321 amd_cpubrand(const struct cpuid_info *cpi)
2322 2322 {
2323 2323 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2324 2324 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2325 2325 return ("i486 compatible");
2326 2326
2327 2327 switch (cpi->cpi_family) {
2328 2328 case 5:
2329 2329 switch (cpi->cpi_model) {
2330 2330 case 0:
2331 2331 case 1:
2332 2332 case 2:
2333 2333 case 3:
2334 2334 case 4:
2335 2335 case 5:
2336 2336 return ("AMD-K5(r)");
2337 2337 case 6:
2338 2338 case 7:
2339 2339 return ("AMD-K6(r)");
2340 2340 case 8:
2341 2341 return ("AMD-K6(r)-2");
2342 2342 case 9:
2343 2343 return ("AMD-K6(r)-III");
2344 2344 default:
2345 2345 return ("AMD (family 5)");
2346 2346 }
2347 2347 case 6:
2348 2348 switch (cpi->cpi_model) {
2349 2349 case 1:
2350 2350 return ("AMD-K7(tm)");
2351 2351 case 0:
2352 2352 case 2:
2353 2353 case 4:
2354 2354 return ("AMD Athlon(tm)");
2355 2355 case 3:
2356 2356 case 7:
2357 2357 return ("AMD Duron(tm)");
2358 2358 case 6:
2359 2359 case 8:
2360 2360 case 10:
2361 2361 /*
2362 2362 * Use the L2 cache size to distinguish
2363 2363 */
2364 2364 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
2365 2365 "AMD Athlon(tm)" : "AMD Duron(tm)");
2366 2366 default:
2367 2367 return ("AMD (family 6)");
2368 2368 }
2369 2369 default:
2370 2370 break;
2371 2371 }
2372 2372
2373 2373 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
2374 2374 cpi->cpi_brandid != 0) {
2375 2375 switch (BITX(cpi->cpi_brandid, 7, 5)) {
2376 2376 case 3:
2377 2377 return ("AMD Opteron(tm) UP 1xx");
2378 2378 case 4:
2379 2379 return ("AMD Opteron(tm) DP 2xx");
2380 2380 case 5:
2381 2381 return ("AMD Opteron(tm) MP 8xx");
2382 2382 default:
2383 2383 return ("AMD Opteron(tm)");
2384 2384 }
2385 2385 }
2386 2386
2387 2387 return (NULL);
2388 2388 }
2389 2389
2390 2390 static const char *
2391 2391 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
2392 2392 {
2393 2393 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2394 2394 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
2395 2395 type == X86_TYPE_CYRIX_486)
2396 2396 return ("i486 compatible");
2397 2397
2398 2398 switch (type) {
2399 2399 case X86_TYPE_CYRIX_6x86:
2400 2400 return ("Cyrix 6x86");
2401 2401 case X86_TYPE_CYRIX_6x86L:
2402 2402 return ("Cyrix 6x86L");
2403 2403 case X86_TYPE_CYRIX_6x86MX:
2404 2404 return ("Cyrix 6x86MX");
2405 2405 case X86_TYPE_CYRIX_GXm:
2406 2406 return ("Cyrix GXm");
2407 2407 case X86_TYPE_CYRIX_MediaGX:
2408 2408 return ("Cyrix MediaGX");
2409 2409 case X86_TYPE_CYRIX_MII:
2410 2410 return ("Cyrix M2");
2411 2411 case X86_TYPE_VIA_CYRIX_III:
2412 2412 return ("VIA Cyrix M3");
2413 2413 default:
2414 2414 /*
2415 2415 * Have another wild guess ..
2416 2416 */
2417 2417 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
2418 2418 return ("Cyrix 5x86");
2419 2419 else if (cpi->cpi_family == 5) {
2420 2420 switch (cpi->cpi_model) {
2421 2421 case 2:
2422 2422 return ("Cyrix 6x86"); /* Cyrix M1 */
2423 2423 case 4:
2424 2424 return ("Cyrix MediaGX");
2425 2425 default:
2426 2426 break;
2427 2427 }
2428 2428 } else if (cpi->cpi_family == 6) {
2429 2429 switch (cpi->cpi_model) {
2430 2430 case 0:
2431 2431 return ("Cyrix 6x86MX"); /* Cyrix M2? */
2432 2432 case 5:
2433 2433 case 6:
2434 2434 case 7:
2435 2435 case 8:
2436 2436 case 9:
2437 2437 return ("VIA C3");
2438 2438 default:
2439 2439 break;
2440 2440 }
2441 2441 }
2442 2442 break;
2443 2443 }
2444 2444 return (NULL);
2445 2445 }
2446 2446
2447 2447 /*
2448 2448 * This only gets called in the case that the CPU extended
2449 2449 * feature brand string (0x80000002, 0x80000003, 0x80000004)
2450 2450 * aren't available, or contain null bytes for some reason.
2451 2451 */
2452 2452 static void
2453 2453 fabricate_brandstr(struct cpuid_info *cpi)
2454 2454 {
2455 2455 const char *brand = NULL;
2456 2456
2457 2457 switch (cpi->cpi_vendor) {
2458 2458 case X86_VENDOR_Intel:
2459 2459 brand = intel_cpubrand(cpi);
2460 2460 break;
2461 2461 case X86_VENDOR_AMD:
2462 2462 brand = amd_cpubrand(cpi);
2463 2463 break;
2464 2464 case X86_VENDOR_Cyrix:
2465 2465 brand = cyrix_cpubrand(cpi, x86_type);
2466 2466 break;
2467 2467 case X86_VENDOR_NexGen:
2468 2468 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2469 2469 brand = "NexGen Nx586";
2470 2470 break;
2471 2471 case X86_VENDOR_Centaur:
2472 2472 if (cpi->cpi_family == 5)
2473 2473 switch (cpi->cpi_model) {
2474 2474 case 4:
2475 2475 brand = "Centaur C6";
2476 2476 break;
2477 2477 case 8:
2478 2478 brand = "Centaur C2";
2479 2479 break;
2480 2480 case 9:
2481 2481 brand = "Centaur C3";
2482 2482 break;
2483 2483 default:
2484 2484 break;
2485 2485 }
2486 2486 break;
2487 2487 case X86_VENDOR_Rise:
2488 2488 if (cpi->cpi_family == 5 &&
2489 2489 (cpi->cpi_model == 0 || cpi->cpi_model == 2))
2490 2490 brand = "Rise mP6";
2491 2491 break;
2492 2492 case X86_VENDOR_SiS:
2493 2493 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2494 2494 brand = "SiS 55x";
2495 2495 break;
2496 2496 case X86_VENDOR_TM:
2497 2497 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
2498 2498 brand = "Transmeta Crusoe TM3x00 or TM5x00";
2499 2499 break;
2500 2500 case X86_VENDOR_NSC:
2501 2501 case X86_VENDOR_UMC:
2502 2502 default:
2503 2503 break;
2504 2504 }
2505 2505 if (brand) {
2506 2506 (void) strcpy((char *)cpi->cpi_brandstr, brand);
2507 2507 return;
2508 2508 }
2509 2509
2510 2510 /*
2511 2511 * If all else fails ...
2512 2512 */
2513 2513 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
2514 2514 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
2515 2515 cpi->cpi_model, cpi->cpi_step);
2516 2516 }
2517 2517
2518 2518 /*
2519 2519 * This routine is called just after kernel memory allocation
2520 2520 * becomes available on cpu0, and as part of mp_startup() on
2521 2521 * the other cpus.
2522 2522 *
2523 2523 * Fixup the brand string, and collect any information from cpuid
2524 2524 * that requires dynamically allocated storage to represent.
2525 2525 */
2526 2526 /*ARGSUSED*/
2527 2527 void
2528 2528 cpuid_pass3(cpu_t *cpu)
2529 2529 {
2530 2530 int i, max, shft, level, size;
2531 2531 struct cpuid_regs regs;
2532 2532 struct cpuid_regs *cp;
2533 2533 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2534 2534
2535 2535 ASSERT(cpi->cpi_pass == 2);
2536 2536
2537 2537 /*
2538 2538 * Function 4: Deterministic cache parameters
2539 2539 *
2540 2540 * Take this opportunity to detect the number of threads
2541 2541 * sharing the last level cache, and construct a corresponding
2542 2542 * cache id. The respective cpuid_info members are initialized
2543 2543 * to the default case of "no last level cache sharing".
2544 2544 */
2545 2545 cpi->cpi_ncpu_shr_last_cache = 1;
2546 2546 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
2547 2547
2548 2548 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
2549 2549
2550 2550 /*
2551 2551 * Find the # of elements (size) returned by fn 4, and along
2552 2552 * the way detect last level cache sharing details.
2553 2553 */
2554 2554 bzero(®s, sizeof (regs));
2555 2555 cp = ®s;
2556 2556 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
2557 2557 cp->cp_eax = 4;
2558 2558 cp->cp_ecx = i;
2559 2559
2560 2560 (void) __cpuid_insn(cp);
2561 2561
2562 2562 if (CPI_CACHE_TYPE(cp) == 0)
2563 2563 break;
2564 2564 level = CPI_CACHE_LVL(cp);
2565 2565 if (level > max) {
2566 2566 max = level;
2567 2567 cpi->cpi_ncpu_shr_last_cache =
2568 2568 CPI_NTHR_SHR_CACHE(cp) + 1;
2569 2569 }
2570 2570 }
2571 2571 cpi->cpi_std_4_size = size = i;
2572 2572
2573 2573 /*
2574 2574 * Allocate the cpi_std_4 array. The first element
2575 2575 * references the regs for fn 4, %ecx == 0, which
2576 2576 * cpuid_pass2() stashed in cpi->cpi_std[4].
2577 2577 */
2578 2578 if (size > 0) {
2579 2579 cpi->cpi_std_4 =
2580 2580 kmem_alloc(size * sizeof (cp), KM_SLEEP);
2581 2581 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
2582 2582
2583 2583 /*
2584 2584 * Allocate storage to hold the additional regs
2585 2585 * for function 4, %ecx == 1 .. cpi_std_4_size.
2586 2586 *
2587 2587 * The regs for fn 4, %ecx == 0 has already
2588 2588 * been allocated as indicated above.
2589 2589 */
2590 2590 for (i = 1; i < size; i++) {
2591 2591 cp = cpi->cpi_std_4[i] =
2592 2592 kmem_zalloc(sizeof (regs), KM_SLEEP);
2593 2593 cp->cp_eax = 4;
2594 2594 cp->cp_ecx = i;
2595 2595
2596 2596 (void) __cpuid_insn(cp);
2597 2597 }
2598 2598 }
2599 2599 /*
2600 2600 * Determine the number of bits needed to represent
2601 2601 * the number of CPUs sharing the last level cache.
2602 2602 *
2603 2603 * Shift off that number of bits from the APIC id to
2604 2604 * derive the cache id.
2605 2605 */
2606 2606 shft = 0;
2607 2607 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
2608 2608 shft++;
2609 2609 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
2610 2610 }
2611 2611
2612 2612 /*
2613 2613 * Now fixup the brand string
2614 2614 */
2615 2615 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2616 2616 fabricate_brandstr(cpi);
2617 2617 } else {
2618 2618
2619 2619 /*
2620 2620 * If we successfully extracted a brand string from the cpuid
2621 2621 * instruction, clean it up by removing leading spaces and
2622 2622 * similar junk.
2623 2623 */
2624 2624 if (cpi->cpi_brandstr[0]) {
2625 2625 size_t maxlen = sizeof (cpi->cpi_brandstr);
2626 2626 char *src, *dst;
2627 2627
2628 2628 dst = src = (char *)cpi->cpi_brandstr;
2629 2629 src[maxlen - 1] = '\0';
2630 2630 /*
2631 2631 * strip leading spaces
2632 2632 */
2633 2633 while (*src == ' ')
2634 2634 src++;
2635 2635 /*
2636 2636 * Remove any 'Genuine' or "Authentic" prefixes
2637 2637 */
2638 2638 if (strncmp(src, "Genuine ", 8) == 0)
2639 2639 src += 8;
2640 2640 if (strncmp(src, "Authentic ", 10) == 0)
2641 2641 src += 10;
2642 2642
2643 2643 /*
2644 2644 * Now do an in-place copy.
2645 2645 * Map (R) to (r) and (TM) to (tm).
2646 2646 * The era of teletypes is long gone, and there's
2647 2647 * -really- no need to shout.
2648 2648 */
2649 2649 while (*src != '\0') {
2650 2650 if (src[0] == '(') {
2651 2651 if (strncmp(src + 1, "R)", 2) == 0) {
2652 2652 (void) strncpy(dst, "(r)", 3);
2653 2653 src += 3;
2654 2654 dst += 3;
2655 2655 continue;
2656 2656 }
2657 2657 if (strncmp(src + 1, "TM)", 3) == 0) {
2658 2658 (void) strncpy(dst, "(tm)", 4);
2659 2659 src += 4;
2660 2660 dst += 4;
2661 2661 continue;
2662 2662 }
2663 2663 }
2664 2664 *dst++ = *src++;
2665 2665 }
2666 2666 *dst = '\0';
2667 2667
2668 2668 /*
2669 2669 * Finally, remove any trailing spaces
2670 2670 */
2671 2671 while (--dst > cpi->cpi_brandstr)
2672 2672 if (*dst == ' ')
2673 2673 *dst = '\0';
2674 2674 else
2675 2675 break;
2676 2676 } else
2677 2677 fabricate_brandstr(cpi);
2678 2678 }
2679 2679 cpi->cpi_pass = 3;
2680 2680 }
2681 2681
2682 2682 /*
2683 2683 * This routine is called out of bind_hwcap() much later in the life
2684 2684 * of the kernel (post_startup()). The job of this routine is to resolve
2685 2685 * the hardware feature support and kernel support for those features into
2686 2686 * what we're actually going to tell applications via the aux vector.
2687 2687 */
2688 2688 void
2689 2689 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
2690 2690 {
2691 2691 struct cpuid_info *cpi;
2692 2692 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
2693 2693
2694 2694 if (cpu == NULL)
2695 2695 cpu = CPU;
2696 2696 cpi = cpu->cpu_m.mcpu_cpi;
2697 2697
2698 2698 ASSERT(cpi->cpi_pass == 3);
2699 2699
2700 2700 if (cpi->cpi_maxeax >= 1) {
2701 2701 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
2702 2702 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2703 2703 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES];
2704 2704
2705 2705 *edx = CPI_FEATURES_EDX(cpi);
2706 2706 *ecx = CPI_FEATURES_ECX(cpi);
2707 2707 *ebx = CPI_FEATURES_7_0_EBX(cpi);
2708 2708
2709 2709 /*
2710 2710 * [these require explicit kernel support]
2711 2711 */
2712 2712 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
2713 2713 *edx &= ~CPUID_INTC_EDX_SEP;
2714 2714
2715 2715 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
2716 2716 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
2717 2717 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
2718 2718 *edx &= ~CPUID_INTC_EDX_SSE2;
2719 2719
2720 2720 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
2721 2721 *edx &= ~CPUID_INTC_EDX_HTT;
2722 2722
2723 2723 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
2724 2724 *ecx &= ~CPUID_INTC_ECX_SSE3;
2725 2725
2726 2726 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
2727 2727 *ecx &= ~CPUID_INTC_ECX_SSSE3;
2728 2728 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
2729 2729 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
2730 2730 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
2731 2731 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
2732 2732 if (!is_x86_feature(x86_featureset, X86FSET_AES))
2733 2733 *ecx &= ~CPUID_INTC_ECX_AES;
2734 2734 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
2735 2735 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
2736 2736 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
2737 2737 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
2738 2738 CPUID_INTC_ECX_OSXSAVE);
2739 2739 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
2740 2740 *ecx &= ~CPUID_INTC_ECX_AVX;
2741 2741 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
2742 2742 *ecx &= ~CPUID_INTC_ECX_F16C;
2743 2743 if (!is_x86_feature(x86_featureset, X86FSET_FMA))
2744 2744 *ecx &= ~CPUID_INTC_ECX_FMA;
2745 2745 if (!is_x86_feature(x86_featureset, X86FSET_BMI1))
2746 2746 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
2747 2747 if (!is_x86_feature(x86_featureset, X86FSET_BMI2))
2748 2748 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
2749 2749 if (!is_x86_feature(x86_featureset, X86FSET_AVX2))
2750 2750 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
2751 2751 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED))
2752 2752 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED;
2753 2753 if (!is_x86_feature(x86_featureset, X86FSET_ADX))
2754 2754 *ebx &= ~CPUID_INTC_EBX_7_0_ADX;
2755 2755
2756 2756 /*
2757 2757 * [no explicit support required beyond x87 fp context]
2758 2758 */
2759 2759 if (!fpu_exists)
2760 2760 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
2761 2761
2762 2762 /*
2763 2763 * Now map the supported feature vector to things that we
2764 2764 * think userland will care about.
2765 2765 */
2766 2766 if (*edx & CPUID_INTC_EDX_SEP)
2767 2767 hwcap_flags |= AV_386_SEP;
2768 2768 if (*edx & CPUID_INTC_EDX_SSE)
2769 2769 hwcap_flags |= AV_386_FXSR | AV_386_SSE;
2770 2770 if (*edx & CPUID_INTC_EDX_SSE2)
2771 2771 hwcap_flags |= AV_386_SSE2;
2772 2772 if (*ecx & CPUID_INTC_ECX_SSE3)
2773 2773 hwcap_flags |= AV_386_SSE3;
2774 2774 if (*ecx & CPUID_INTC_ECX_SSSE3)
2775 2775 hwcap_flags |= AV_386_SSSE3;
2776 2776 if (*ecx & CPUID_INTC_ECX_SSE4_1)
2777 2777 hwcap_flags |= AV_386_SSE4_1;
2778 2778 if (*ecx & CPUID_INTC_ECX_SSE4_2)
2779 2779 hwcap_flags |= AV_386_SSE4_2;
2780 2780 if (*ecx & CPUID_INTC_ECX_MOVBE)
2781 2781 hwcap_flags |= AV_386_MOVBE;
2782 2782 if (*ecx & CPUID_INTC_ECX_AES)
2783 2783 hwcap_flags |= AV_386_AES;
2784 2784 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
2785 2785 hwcap_flags |= AV_386_PCLMULQDQ;
2786 2786 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
2787 2787 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
2788 2788 hwcap_flags |= AV_386_XSAVE;
2789 2789
2790 2790 if (*ecx & CPUID_INTC_ECX_AVX) {
2791 2791 hwcap_flags |= AV_386_AVX;
2792 2792 if (*ecx & CPUID_INTC_ECX_F16C)
2793 2793 hwcap_flags_2 |= AV_386_2_F16C;
2794 2794 if (*ecx & CPUID_INTC_ECX_FMA)
2795 2795 hwcap_flags_2 |= AV_386_2_FMA;
2796 2796 if (*ebx & CPUID_INTC_EBX_7_0_BMI1)
2797 2797 hwcap_flags_2 |= AV_386_2_BMI1;
2798 2798 if (*ebx & CPUID_INTC_EBX_7_0_BMI2)
2799 2799 hwcap_flags_2 |= AV_386_2_BMI2;
2800 2800 if (*ebx & CPUID_INTC_EBX_7_0_AVX2)
2801 2801 hwcap_flags_2 |= AV_386_2_AVX2;
2802 2802 }
2803 2803 }
2804 2804 if (*ecx & CPUID_INTC_ECX_VMX)
2805 2805 hwcap_flags |= AV_386_VMX;
2806 2806 if (*ecx & CPUID_INTC_ECX_POPCNT)
2807 2807 hwcap_flags |= AV_386_POPCNT;
2808 2808 if (*edx & CPUID_INTC_EDX_FPU)
2809 2809 hwcap_flags |= AV_386_FPU;
2810 2810 if (*edx & CPUID_INTC_EDX_MMX)
2811 2811 hwcap_flags |= AV_386_MMX;
2812 2812
2813 2813 if (*edx & CPUID_INTC_EDX_TSC)
2814 2814 hwcap_flags |= AV_386_TSC;
2815 2815 if (*edx & CPUID_INTC_EDX_CX8)
2816 2816 hwcap_flags |= AV_386_CX8;
2817 2817 if (*edx & CPUID_INTC_EDX_CMOV)
2818 2818 hwcap_flags |= AV_386_CMOV;
2819 2819 if (*ecx & CPUID_INTC_ECX_CX16)
2820 2820 hwcap_flags |= AV_386_CX16;
2821 2821
2822 2822 if (*ecx & CPUID_INTC_ECX_RDRAND)
2823 2823 hwcap_flags_2 |= AV_386_2_RDRAND;
2824 2824 if (*ebx & CPUID_INTC_EBX_7_0_ADX)
2825 2825 hwcap_flags_2 |= AV_386_2_ADX;
2826 2826 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED)
2827 2827 hwcap_flags_2 |= AV_386_2_RDSEED;
2828 2828
2829 2829 }
2830 2830
2831 2831 /* Detect systems with a potential CPUID limit */
2832 2832 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax < 4) {
2833 2833 cmn_err(CE_NOTE, "CPUID limit detected, "
2834 2834 "see the CPUID(7D) man page for details\n");
2835 2835 }
2836 2836
2837 2837
2838 2838 if (cpi->cpi_xmaxeax < 0x80000001)
2839 2839 goto pass4_done;
2840 2840
2841 2841 switch (cpi->cpi_vendor) {
2842 2842 struct cpuid_regs cp;
2843 2843 uint32_t *edx, *ecx;
2844 2844
2845 2845 case X86_VENDOR_Intel:
2846 2846 /*
2847 2847 * Seems like Intel duplicated what we necessary
2848 2848 * here to make the initial crop of 64-bit OS's work.
2849 2849 * Hopefully, those are the only "extended" bits
2850 2850 * they'll add.
2851 2851 */
2852 2852 /*FALLTHROUGH*/
2853 2853
2854 2854 case X86_VENDOR_AMD:
2855 2855 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
2856 2856 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2857 2857
2858 2858 *edx = CPI_FEATURES_XTD_EDX(cpi);
2859 2859 *ecx = CPI_FEATURES_XTD_ECX(cpi);
2860 2860
2861 2861 /*
2862 2862 * [these features require explicit kernel support]
2863 2863 */
2864 2864 switch (cpi->cpi_vendor) {
2865 2865 case X86_VENDOR_Intel:
2866 2866 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2867 2867 *edx &= ~CPUID_AMD_EDX_TSCP;
2868 2868 break;
2869 2869
2870 2870 case X86_VENDOR_AMD:
2871 2871 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2872 2872 *edx &= ~CPUID_AMD_EDX_TSCP;
2873 2873 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
2874 2874 *ecx &= ~CPUID_AMD_ECX_SSE4A;
2875 2875 break;
2876 2876
2877 2877 default:
2878 2878 break;
2879 2879 }
2880 2880
2881 2881 /*
2882 2882 * [no explicit support required beyond
2883 2883 * x87 fp context and exception handlers]
2884 2884 */
2885 2885 if (!fpu_exists)
2886 2886 *edx &= ~(CPUID_AMD_EDX_MMXamd |
2887 2887 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
2888 2888
2889 2889 if (!is_x86_feature(x86_featureset, X86FSET_NX))
2890 2890 *edx &= ~CPUID_AMD_EDX_NX;
2891 2891 #if !defined(__amd64)
2892 2892 *edx &= ~CPUID_AMD_EDX_LM;
2893 2893 #endif
2894 2894 /*
2895 2895 * Now map the supported feature vector to
2896 2896 * things that we think userland will care about.
2897 2897 */
2898 2898 #if defined(__amd64)
2899 2899 if (*edx & CPUID_AMD_EDX_SYSC)
2900 2900 hwcap_flags |= AV_386_AMD_SYSC;
2901 2901 #endif
2902 2902 if (*edx & CPUID_AMD_EDX_MMXamd)
2903 2903 hwcap_flags |= AV_386_AMD_MMX;
2904 2904 if (*edx & CPUID_AMD_EDX_3DNow)
2905 2905 hwcap_flags |= AV_386_AMD_3DNow;
2906 2906 if (*edx & CPUID_AMD_EDX_3DNowx)
2907 2907 hwcap_flags |= AV_386_AMD_3DNowx;
2908 2908 if (*ecx & CPUID_AMD_ECX_SVM)
2909 2909 hwcap_flags |= AV_386_AMD_SVM;
2910 2910
2911 2911 switch (cpi->cpi_vendor) {
2912 2912 case X86_VENDOR_AMD:
2913 2913 if (*edx & CPUID_AMD_EDX_TSCP)
2914 2914 hwcap_flags |= AV_386_TSCP;
2915 2915 if (*ecx & CPUID_AMD_ECX_AHF64)
2916 2916 hwcap_flags |= AV_386_AHF;
2917 2917 if (*ecx & CPUID_AMD_ECX_SSE4A)
2918 2918 hwcap_flags |= AV_386_AMD_SSE4A;
2919 2919 if (*ecx & CPUID_AMD_ECX_LZCNT)
2920 2920 hwcap_flags |= AV_386_AMD_LZCNT;
2921 2921 break;
2922 2922
2923 2923 case X86_VENDOR_Intel:
2924 2924 if (*edx & CPUID_AMD_EDX_TSCP)
2925 2925 hwcap_flags |= AV_386_TSCP;
2926 2926 /*
2927 2927 * Aarrgh.
2928 2928 * Intel uses a different bit in the same word.
2929 2929 */
2930 2930 if (*ecx & CPUID_INTC_ECX_AHF64)
2931 2931 hwcap_flags |= AV_386_AHF;
2932 2932 break;
2933 2933
2934 2934 default:
2935 2935 break;
2936 2936 }
2937 2937 break;
2938 2938
2939 2939 case X86_VENDOR_TM:
2940 2940 cp.cp_eax = 0x80860001;
2941 2941 (void) __cpuid_insn(&cp);
2942 2942 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
2943 2943 break;
2944 2944
2945 2945 default:
2946 2946 break;
2947 2947 }
2948 2948
2949 2949 pass4_done:
2950 2950 cpi->cpi_pass = 4;
2951 2951 if (hwcap_out != NULL) {
2952 2952 hwcap_out[0] = hwcap_flags;
2953 2953 hwcap_out[1] = hwcap_flags_2;
2954 2954 }
2955 2955 }
2956 2956
2957 2957
2958 2958 /*
2959 2959 * Simulate the cpuid instruction using the data we previously
2960 2960 * captured about this CPU. We try our best to return the truth
2961 2961 * about the hardware, independently of kernel support.
2962 2962 */
2963 2963 uint32_t
2964 2964 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
2965 2965 {
2966 2966 struct cpuid_info *cpi;
2967 2967 struct cpuid_regs *xcp;
2968 2968
2969 2969 if (cpu == NULL)
2970 2970 cpu = CPU;
2971 2971 cpi = cpu->cpu_m.mcpu_cpi;
2972 2972
2973 2973 ASSERT(cpuid_checkpass(cpu, 3));
2974 2974
2975 2975 /*
2976 2976 * CPUID data is cached in two separate places: cpi_std for standard
2977 2977 * CPUID functions, and cpi_extd for extended CPUID functions.
2978 2978 */
2979 2979 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
2980 2980 xcp = &cpi->cpi_std[cp->cp_eax];
2981 2981 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
2982 2982 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
2983 2983 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
2984 2984 else
2985 2985 /*
2986 2986 * The caller is asking for data from an input parameter which
2987 2987 * the kernel has not cached. In this case we go fetch from
2988 2988 * the hardware and return the data directly to the user.
2989 2989 */
2990 2990 return (__cpuid_insn(cp));
2991 2991
2992 2992 cp->cp_eax = xcp->cp_eax;
2993 2993 cp->cp_ebx = xcp->cp_ebx;
2994 2994 cp->cp_ecx = xcp->cp_ecx;
2995 2995 cp->cp_edx = xcp->cp_edx;
2996 2996 return (cp->cp_eax);
2997 2997 }
2998 2998
2999 2999 int
3000 3000 cpuid_checkpass(cpu_t *cpu, int pass)
3001 3001 {
3002 3002 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
3003 3003 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
3004 3004 }
3005 3005
3006 3006 int
3007 3007 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
3008 3008 {
3009 3009 ASSERT(cpuid_checkpass(cpu, 3));
3010 3010
3011 3011 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
3012 3012 }
3013 3013
3014 3014 int
3015 3015 cpuid_is_cmt(cpu_t *cpu)
3016 3016 {
3017 3017 if (cpu == NULL)
3018 3018 cpu = CPU;
3019 3019
3020 3020 ASSERT(cpuid_checkpass(cpu, 1));
3021 3021
3022 3022 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
3023 3023 }
3024 3024
3025 3025 /*
3026 3026 * AMD and Intel both implement the 64-bit variant of the syscall
3027 3027 * instruction (syscallq), so if there's -any- support for syscall,
3028 3028 * cpuid currently says "yes, we support this".
3029 3029 *
3030 3030 * However, Intel decided to -not- implement the 32-bit variant of the
3031 3031 * syscall instruction, so we provide a predicate to allow our caller
3032 3032 * to test that subtlety here.
3033 3033 *
3034 3034 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
3035 3035 * even in the case where the hardware would in fact support it.
3036 3036 */
3037 3037 /*ARGSUSED*/
3038 3038 int
3039 3039 cpuid_syscall32_insn(cpu_t *cpu)
3040 3040 {
3041 3041 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
3042 3042
3043 3043 #if !defined(__xpv)
3044 3044 if (cpu == NULL)
3045 3045 cpu = CPU;
3046 3046
3047 3047 /*CSTYLED*/
3048 3048 {
3049 3049 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3050 3050
3051 3051 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
3052 3052 cpi->cpi_xmaxeax >= 0x80000001 &&
3053 3053 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
3054 3054 return (1);
3055 3055 }
3056 3056 #endif
3057 3057 return (0);
3058 3058 }
3059 3059
3060 3060 int
3061 3061 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
3062 3062 {
3063 3063 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3064 3064
3065 3065 static const char fmt[] =
3066 3066 "x86 (%s %X family %d model %d step %d clock %d MHz)";
3067 3067 static const char fmt_ht[] =
3068 3068 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
3069 3069
3070 3070 ASSERT(cpuid_checkpass(cpu, 1));
3071 3071
3072 3072 if (cpuid_is_cmt(cpu))
3073 3073 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3074 3074 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3075 3075 cpi->cpi_family, cpi->cpi_model,
3076 3076 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3077 3077 return (snprintf(s, n, fmt,
3078 3078 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3079 3079 cpi->cpi_family, cpi->cpi_model,
3080 3080 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3081 3081 }
3082 3082
3083 3083 const char *
3084 3084 cpuid_getvendorstr(cpu_t *cpu)
3085 3085 {
3086 3086 ASSERT(cpuid_checkpass(cpu, 1));
3087 3087 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
3088 3088 }
3089 3089
3090 3090 uint_t
3091 3091 cpuid_getvendor(cpu_t *cpu)
3092 3092 {
3093 3093 ASSERT(cpuid_checkpass(cpu, 1));
3094 3094 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
3095 3095 }
3096 3096
3097 3097 uint_t
3098 3098 cpuid_getfamily(cpu_t *cpu)
3099 3099 {
3100 3100 ASSERT(cpuid_checkpass(cpu, 1));
3101 3101 return (cpu->cpu_m.mcpu_cpi->cpi_family);
3102 3102 }
3103 3103
3104 3104 uint_t
3105 3105 cpuid_getmodel(cpu_t *cpu)
3106 3106 {
3107 3107 ASSERT(cpuid_checkpass(cpu, 1));
3108 3108 return (cpu->cpu_m.mcpu_cpi->cpi_model);
3109 3109 }
3110 3110
3111 3111 uint_t
3112 3112 cpuid_get_ncpu_per_chip(cpu_t *cpu)
3113 3113 {
3114 3114 ASSERT(cpuid_checkpass(cpu, 1));
3115 3115 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
3116 3116 }
3117 3117
3118 3118 uint_t
3119 3119 cpuid_get_ncore_per_chip(cpu_t *cpu)
3120 3120 {
3121 3121 ASSERT(cpuid_checkpass(cpu, 1));
3122 3122 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
3123 3123 }
3124 3124
3125 3125 uint_t
3126 3126 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
3127 3127 {
3128 3128 ASSERT(cpuid_checkpass(cpu, 2));
3129 3129 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
3130 3130 }
3131 3131
3132 3132 id_t
3133 3133 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
3134 3134 {
3135 3135 ASSERT(cpuid_checkpass(cpu, 2));
3136 3136 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3137 3137 }
3138 3138
3139 3139 uint_t
3140 3140 cpuid_getstep(cpu_t *cpu)
3141 3141 {
3142 3142 ASSERT(cpuid_checkpass(cpu, 1));
3143 3143 return (cpu->cpu_m.mcpu_cpi->cpi_step);
3144 3144 }
3145 3145
3146 3146 uint_t
3147 3147 cpuid_getsig(struct cpu *cpu)
3148 3148 {
3149 3149 ASSERT(cpuid_checkpass(cpu, 1));
3150 3150 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
3151 3151 }
3152 3152
3153 3153 uint32_t
3154 3154 cpuid_getchiprev(struct cpu *cpu)
3155 3155 {
3156 3156 ASSERT(cpuid_checkpass(cpu, 1));
3157 3157 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
3158 3158 }
3159 3159
3160 3160 const char *
3161 3161 cpuid_getchiprevstr(struct cpu *cpu)
3162 3162 {
3163 3163 ASSERT(cpuid_checkpass(cpu, 1));
3164 3164 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
3165 3165 }
3166 3166
3167 3167 uint32_t
3168 3168 cpuid_getsockettype(struct cpu *cpu)
3169 3169 {
3170 3170 ASSERT(cpuid_checkpass(cpu, 1));
3171 3171 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
3172 3172 }
3173 3173
3174 3174 const char *
3175 3175 cpuid_getsocketstr(cpu_t *cpu)
3176 3176 {
3177 3177 static const char *socketstr = NULL;
3178 3178 struct cpuid_info *cpi;
3179 3179
3180 3180 ASSERT(cpuid_checkpass(cpu, 1));
3181 3181 cpi = cpu->cpu_m.mcpu_cpi;
3182 3182
3183 3183 /* Assume that socket types are the same across the system */
3184 3184 if (socketstr == NULL)
3185 3185 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
3186 3186 cpi->cpi_model, cpi->cpi_step);
3187 3187
3188 3188
3189 3189 return (socketstr);
3190 3190 }
3191 3191
3192 3192 int
3193 3193 cpuid_get_chipid(cpu_t *cpu)
3194 3194 {
3195 3195 ASSERT(cpuid_checkpass(cpu, 1));
3196 3196
3197 3197 if (cpuid_is_cmt(cpu))
3198 3198 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
3199 3199 return (cpu->cpu_id);
3200 3200 }
3201 3201
3202 3202 id_t
3203 3203 cpuid_get_coreid(cpu_t *cpu)
3204 3204 {
3205 3205 ASSERT(cpuid_checkpass(cpu, 1));
3206 3206 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
3207 3207 }
3208 3208
3209 3209 int
3210 3210 cpuid_get_pkgcoreid(cpu_t *cpu)
3211 3211 {
3212 3212 ASSERT(cpuid_checkpass(cpu, 1));
3213 3213 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
3214 3214 }
3215 3215
3216 3216 int
3217 3217 cpuid_get_clogid(cpu_t *cpu)
3218 3218 {
3219 3219 ASSERT(cpuid_checkpass(cpu, 1));
3220 3220 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
3221 3221 }
3222 3222
3223 3223 int
3224 3224 cpuid_get_cacheid(cpu_t *cpu)
3225 3225 {
3226 3226 ASSERT(cpuid_checkpass(cpu, 1));
3227 3227 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3228 3228 }
3229 3229
3230 3230 uint_t
3231 3231 cpuid_get_procnodeid(cpu_t *cpu)
3232 3232 {
3233 3233 ASSERT(cpuid_checkpass(cpu, 1));
3234 3234 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3235 3235 }
3236 3236
3237 3237 uint_t
3238 3238 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3239 3239 {
3240 3240 ASSERT(cpuid_checkpass(cpu, 1));
3241 3241 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3242 3242 }
3243 3243
3244 3244 uint_t
3245 3245 cpuid_get_compunitid(cpu_t *cpu)
3246 3246 {
3247 3247 ASSERT(cpuid_checkpass(cpu, 1));
3248 3248 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3249 3249 }
3250 3250
3251 3251 uint_t
3252 3252 cpuid_get_cores_per_compunit(cpu_t *cpu)
3253 3253 {
3254 3254 ASSERT(cpuid_checkpass(cpu, 1));
3255 3255 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3256 3256 }
3257 3257
3258 3258 /*ARGSUSED*/
3259 3259 int
3260 3260 cpuid_have_cr8access(cpu_t *cpu)
3261 3261 {
3262 3262 #if defined(__amd64)
3263 3263 return (1);
3264 3264 #else
3265 3265 struct cpuid_info *cpi;
3266 3266
3267 3267 ASSERT(cpu != NULL);
3268 3268 cpi = cpu->cpu_m.mcpu_cpi;
3269 3269 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3270 3270 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3271 3271 return (1);
3272 3272 return (0);
3273 3273 #endif
3274 3274 }
3275 3275
3276 3276 uint32_t
3277 3277 cpuid_get_apicid(cpu_t *cpu)
3278 3278 {
3279 3279 ASSERT(cpuid_checkpass(cpu, 1));
3280 3280 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
3281 3281 return (UINT32_MAX);
3282 3282 } else {
3283 3283 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
3284 3284 }
3285 3285 }
3286 3286
3287 3287 void
3288 3288 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
3289 3289 {
3290 3290 struct cpuid_info *cpi;
3291 3291
3292 3292 if (cpu == NULL)
3293 3293 cpu = CPU;
3294 3294 cpi = cpu->cpu_m.mcpu_cpi;
3295 3295
3296 3296 ASSERT(cpuid_checkpass(cpu, 1));
3297 3297
3298 3298 if (pabits)
3299 3299 *pabits = cpi->cpi_pabits;
3300 3300 if (vabits)
3301 3301 *vabits = cpi->cpi_vabits;
3302 3302 }
3303 3303
3304 3304 /*
3305 3305 * Returns the number of data TLB entries for a corresponding
3306 3306 * pagesize. If it can't be computed, or isn't known, the
3307 3307 * routine returns zero. If you ask about an architecturally
3308 3308 * impossible pagesize, the routine will panic (so that the
3309 3309 * hat implementor knows that things are inconsistent.)
3310 3310 */
3311 3311 uint_t
3312 3312 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
3313 3313 {
3314 3314 struct cpuid_info *cpi;
3315 3315 uint_t dtlb_nent = 0;
3316 3316
3317 3317 if (cpu == NULL)
3318 3318 cpu = CPU;
3319 3319 cpi = cpu->cpu_m.mcpu_cpi;
3320 3320
3321 3321 ASSERT(cpuid_checkpass(cpu, 1));
3322 3322
3323 3323 /*
3324 3324 * Check the L2 TLB info
3325 3325 */
3326 3326 if (cpi->cpi_xmaxeax >= 0x80000006) {
3327 3327 struct cpuid_regs *cp = &cpi->cpi_extd[6];
3328 3328
3329 3329 switch (pagesize) {
3330 3330
3331 3331 case 4 * 1024:
3332 3332 /*
3333 3333 * All zero in the top 16 bits of the register
3334 3334 * indicates a unified TLB. Size is in low 16 bits.
3335 3335 */
3336 3336 if ((cp->cp_ebx & 0xffff0000) == 0)
3337 3337 dtlb_nent = cp->cp_ebx & 0x0000ffff;
3338 3338 else
3339 3339 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
3340 3340 break;
3341 3341
3342 3342 case 2 * 1024 * 1024:
3343 3343 if ((cp->cp_eax & 0xffff0000) == 0)
3344 3344 dtlb_nent = cp->cp_eax & 0x0000ffff;
3345 3345 else
3346 3346 dtlb_nent = BITX(cp->cp_eax, 27, 16);
3347 3347 break;
3348 3348
3349 3349 default:
3350 3350 panic("unknown L2 pagesize");
3351 3351 /*NOTREACHED*/
3352 3352 }
3353 3353 }
3354 3354
3355 3355 if (dtlb_nent != 0)
3356 3356 return (dtlb_nent);
3357 3357
3358 3358 /*
3359 3359 * No L2 TLB support for this size, try L1.
3360 3360 */
3361 3361 if (cpi->cpi_xmaxeax >= 0x80000005) {
3362 3362 struct cpuid_regs *cp = &cpi->cpi_extd[5];
3363 3363
3364 3364 switch (pagesize) {
3365 3365 case 4 * 1024:
3366 3366 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
3367 3367 break;
3368 3368 case 2 * 1024 * 1024:
3369 3369 dtlb_nent = BITX(cp->cp_eax, 23, 16);
3370 3370 break;
3371 3371 default:
3372 3372 panic("unknown L1 d-TLB pagesize");
3373 3373 /*NOTREACHED*/
3374 3374 }
3375 3375 }
3376 3376
3377 3377 return (dtlb_nent);
3378 3378 }
3379 3379
3380 3380 /*
3381 3381 * Return 0 if the erratum is not present or not applicable, positive
3382 3382 * if it is, and negative if the status of the erratum is unknown.
3383 3383 *
3384 3384 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
3385 3385 * Processors" #25759, Rev 3.57, August 2005
3386 3386 */
3387 3387 int
3388 3388 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
3389 3389 {
3390 3390 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3391 3391 uint_t eax;
3392 3392
3393 3393 /*
3394 3394 * Bail out if this CPU isn't an AMD CPU, or if it's
3395 3395 * a legacy (32-bit) AMD CPU.
3396 3396 */
3397 3397 if (cpi->cpi_vendor != X86_VENDOR_AMD ||
3398 3398 cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
3399 3399 cpi->cpi_family == 6)
3400 3400
3401 3401 return (0);
3402 3402
3403 3403 eax = cpi->cpi_std[1].cp_eax;
3404 3404
3405 3405 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
3406 3406 #define SH_B3(eax) (eax == 0xf51)
3407 3407 #define B(eax) (SH_B0(eax) || SH_B3(eax))
3408 3408
3409 3409 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
3410 3410
3411 3411 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
3412 3412 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
3413 3413 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
3414 3414 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
3415 3415
3416 3416 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
3417 3417 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
3418 3418 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
3419 3419 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
3420 3420
3421 3421 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
3422 3422 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
3423 3423 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
3424 3424 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
3425 3425 #define BH_E4(eax) (eax == 0x20fb1)
3426 3426 #define SH_E5(eax) (eax == 0x20f42)
3427 3427 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
3428 3428 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
3429 3429 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
3430 3430 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
3431 3431 DH_E6(eax) || JH_E6(eax))
3432 3432
3433 3433 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02)
3434 3434 #define DR_B0(eax) (eax == 0x100f20)
3435 3435 #define DR_B1(eax) (eax == 0x100f21)
3436 3436 #define DR_BA(eax) (eax == 0x100f2a)
3437 3437 #define DR_B2(eax) (eax == 0x100f22)
3438 3438 #define DR_B3(eax) (eax == 0x100f23)
3439 3439 #define RB_C0(eax) (eax == 0x100f40)
3440 3440
3441 3441 switch (erratum) {
3442 3442 case 1:
3443 3443 return (cpi->cpi_family < 0x10);
3444 3444 case 51: /* what does the asterisk mean? */
3445 3445 return (B(eax) || SH_C0(eax) || CG(eax));
3446 3446 case 52:
3447 3447 return (B(eax));
3448 3448 case 57:
3449 3449 return (cpi->cpi_family <= 0x11);
3450 3450 case 58:
3451 3451 return (B(eax));
3452 3452 case 60:
3453 3453 return (cpi->cpi_family <= 0x11);
3454 3454 case 61:
3455 3455 case 62:
3456 3456 case 63:
3457 3457 case 64:
3458 3458 case 65:
3459 3459 case 66:
3460 3460 case 68:
3461 3461 case 69:
3462 3462 case 70:
3463 3463 case 71:
3464 3464 return (B(eax));
3465 3465 case 72:
3466 3466 return (SH_B0(eax));
3467 3467 case 74:
3468 3468 return (B(eax));
3469 3469 case 75:
3470 3470 return (cpi->cpi_family < 0x10);
3471 3471 case 76:
3472 3472 return (B(eax));
3473 3473 case 77:
3474 3474 return (cpi->cpi_family <= 0x11);
3475 3475 case 78:
3476 3476 return (B(eax) || SH_C0(eax));
3477 3477 case 79:
3478 3478 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3479 3479 case 80:
3480 3480 case 81:
3481 3481 case 82:
3482 3482 return (B(eax));
3483 3483 case 83:
3484 3484 return (B(eax) || SH_C0(eax) || CG(eax));
3485 3485 case 85:
3486 3486 return (cpi->cpi_family < 0x10);
3487 3487 case 86:
3488 3488 return (SH_C0(eax) || CG(eax));
3489 3489 case 88:
3490 3490 #if !defined(__amd64)
3491 3491 return (0);
3492 3492 #else
3493 3493 return (B(eax) || SH_C0(eax));
3494 3494 #endif
3495 3495 case 89:
3496 3496 return (cpi->cpi_family < 0x10);
3497 3497 case 90:
3498 3498 return (B(eax) || SH_C0(eax) || CG(eax));
3499 3499 case 91:
3500 3500 case 92:
3501 3501 return (B(eax) || SH_C0(eax));
3502 3502 case 93:
3503 3503 return (SH_C0(eax));
3504 3504 case 94:
3505 3505 return (B(eax) || SH_C0(eax) || CG(eax));
3506 3506 case 95:
3507 3507 #if !defined(__amd64)
3508 3508 return (0);
3509 3509 #else
3510 3510 return (B(eax) || SH_C0(eax));
3511 3511 #endif
3512 3512 case 96:
3513 3513 return (B(eax) || SH_C0(eax) || CG(eax));
3514 3514 case 97:
3515 3515 case 98:
3516 3516 return (SH_C0(eax) || CG(eax));
3517 3517 case 99:
3518 3518 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3519 3519 case 100:
3520 3520 return (B(eax) || SH_C0(eax));
3521 3521 case 101:
3522 3522 case 103:
3523 3523 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3524 3524 case 104:
3525 3525 return (SH_C0(eax) || CG(eax) || D0(eax));
3526 3526 case 105:
3527 3527 case 106:
3528 3528 case 107:
3529 3529 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3530 3530 case 108:
3531 3531 return (DH_CG(eax));
3532 3532 case 109:
3533 3533 return (SH_C0(eax) || CG(eax) || D0(eax));
3534 3534 case 110:
3535 3535 return (D0(eax) || EX(eax));
3536 3536 case 111:
3537 3537 return (CG(eax));
3538 3538 case 112:
3539 3539 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3540 3540 case 113:
3541 3541 return (eax == 0x20fc0);
3542 3542 case 114:
3543 3543 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3544 3544 case 115:
3545 3545 return (SH_E0(eax) || JH_E1(eax));
3546 3546 case 116:
3547 3547 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3548 3548 case 117:
3549 3549 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3550 3550 case 118:
3551 3551 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
3552 3552 JH_E6(eax));
3553 3553 case 121:
3554 3554 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3555 3555 case 122:
3556 3556 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11);
3557 3557 case 123:
3558 3558 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
3559 3559 case 131:
3560 3560 return (cpi->cpi_family < 0x10);
3561 3561 case 6336786:
3562 3562 /*
3563 3563 * Test for AdvPowerMgmtInfo.TscPStateInvariant
3564 3564 * if this is a K8 family or newer processor
3565 3565 */
3566 3566 if (CPI_FAMILY(cpi) == 0xf) {
3567 3567 struct cpuid_regs regs;
3568 3568 regs.cp_eax = 0x80000007;
3569 3569 (void) __cpuid_insn(®s);
3570 3570 return (!(regs.cp_edx & 0x100));
3571 3571 }
3572 3572 return (0);
3573 3573 case 6323525:
3574 3574 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
3575 3575 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
3576 3576
3577 3577 case 6671130:
3578 3578 /*
3579 3579 * check for processors (pre-Shanghai) that do not provide
3580 3580 * optimal management of 1gb ptes in its tlb.
3581 3581 */
3582 3582 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
3583 3583
3584 3584 case 298:
3585 3585 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
3586 3586 DR_B2(eax) || RB_C0(eax));
3587 3587
3588 3588 case 721:
3589 3589 #if defined(__amd64)
3590 3590 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
3591 3591 #else
3592 3592 return (0);
3593 3593 #endif
3594 3594
3595 3595 default:
3596 3596 return (-1);
3597 3597
3598 3598 }
3599 3599 }
3600 3600
3601 3601 /*
3602 3602 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
3603 3603 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
3604 3604 */
3605 3605 int
3606 3606 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
3607 3607 {
3608 3608 struct cpuid_info *cpi;
3609 3609 uint_t osvwid;
3610 3610 static int osvwfeature = -1;
3611 3611 uint64_t osvwlength;
3612 3612
3613 3613
3614 3614 cpi = cpu->cpu_m.mcpu_cpi;
3615 3615
3616 3616 /* confirm OSVW supported */
3617 3617 if (osvwfeature == -1) {
3618 3618 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
3619 3619 } else {
3620 3620 /* assert that osvw feature setting is consistent on all cpus */
3621 3621 ASSERT(osvwfeature ==
3622 3622 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
3623 3623 }
3624 3624 if (!osvwfeature)
3625 3625 return (-1);
3626 3626
3627 3627 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
3628 3628
3629 3629 switch (erratum) {
3630 3630 case 298: /* osvwid is 0 */
3631 3631 osvwid = 0;
3632 3632 if (osvwlength <= (uint64_t)osvwid) {
3633 3633 /* osvwid 0 is unknown */
3634 3634 return (-1);
3635 3635 }
3636 3636
3637 3637 /*
3638 3638 * Check the OSVW STATUS MSR to determine the state
3639 3639 * of the erratum where:
3640 3640 * 0 - fixed by HW
3641 3641 * 1 - BIOS has applied the workaround when BIOS
3642 3642 * workaround is available. (Or for other errata,
3643 3643 * OS workaround is required.)
3644 3644 * For a value of 1, caller will confirm that the
3645 3645 * erratum 298 workaround has indeed been applied by BIOS.
3646 3646 *
3647 3647 * A 1 may be set in cpus that have a HW fix
3648 3648 * in a mixed cpu system. Regarding erratum 298:
3649 3649 * In a multiprocessor platform, the workaround above
3650 3650 * should be applied to all processors regardless of
3651 3651 * silicon revision when an affected processor is
3652 3652 * present.
3653 3653 */
3654 3654
3655 3655 return (rdmsr(MSR_AMD_OSVW_STATUS +
3656 3656 (osvwid / OSVW_ID_CNT_PER_MSR)) &
3657 3657 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
3658 3658
3659 3659 default:
3660 3660 return (-1);
3661 3661 }
3662 3662 }
3663 3663
3664 3664 static const char assoc_str[] = "associativity";
3665 3665 static const char line_str[] = "line-size";
3666 3666 static const char size_str[] = "size";
3667 3667
3668 3668 static void
3669 3669 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
3670 3670 uint32_t val)
3671 3671 {
3672 3672 char buf[128];
3673 3673
3674 3674 /*
3675 3675 * ndi_prop_update_int() is used because it is desirable for
3676 3676 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
3677 3677 */
3678 3678 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
3679 3679 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
3680 3680 }
3681 3681
3682 3682 /*
3683 3683 * Intel-style cache/tlb description
3684 3684 *
3685 3685 * Standard cpuid level 2 gives a randomly ordered
3686 3686 * selection of tags that index into a table that describes
3687 3687 * cache and tlb properties.
3688 3688 */
3689 3689
3690 3690 static const char l1_icache_str[] = "l1-icache";
3691 3691 static const char l1_dcache_str[] = "l1-dcache";
3692 3692 static const char l2_cache_str[] = "l2-cache";
3693 3693 static const char l3_cache_str[] = "l3-cache";
3694 3694 static const char itlb4k_str[] = "itlb-4K";
3695 3695 static const char dtlb4k_str[] = "dtlb-4K";
3696 3696 static const char itlb2M_str[] = "itlb-2M";
3697 3697 static const char itlb4M_str[] = "itlb-4M";
3698 3698 static const char dtlb4M_str[] = "dtlb-4M";
3699 3699 static const char dtlb24_str[] = "dtlb0-2M-4M";
3700 3700 static const char itlb424_str[] = "itlb-4K-2M-4M";
3701 3701 static const char itlb24_str[] = "itlb-2M-4M";
3702 3702 static const char dtlb44_str[] = "dtlb-4K-4M";
3703 3703 static const char sl1_dcache_str[] = "sectored-l1-dcache";
3704 3704 static const char sl2_cache_str[] = "sectored-l2-cache";
3705 3705 static const char itrace_str[] = "itrace-cache";
3706 3706 static const char sl3_cache_str[] = "sectored-l3-cache";
3707 3707 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
3708 3708
3709 3709 static const struct cachetab {
3710 3710 uint8_t ct_code;
3711 3711 uint8_t ct_assoc;
3712 3712 uint16_t ct_line_size;
3713 3713 size_t ct_size;
3714 3714 const char *ct_label;
3715 3715 } intel_ctab[] = {
3716 3716 /*
3717 3717 * maintain descending order!
3718 3718 *
3719 3719 * Codes ignored - Reason
3720 3720 * ----------------------
3721 3721 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3722 3722 * f0H/f1H - Currently we do not interpret prefetch size by design
3723 3723 */
3724 3724 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str},
3725 3725 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str},
3726 3726 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str},
3727 3727 { 0xde, 12, 64, 6*1024*1024, l3_cache_str},
3728 3728 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str},
3729 3729 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str},
3730 3730 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str},
3731 3731 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str},
3732 3732 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str},
3733 3733 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str},
3734 3734 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str},
3735 3735 { 0xd0, 4, 64, 512*1024, l3_cache_str},
3736 3736 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
3737 3737 { 0xc0, 4, 0, 8, dtlb44_str },
3738 3738 { 0xba, 4, 0, 64, dtlb4k_str },
3739 3739 { 0xb4, 4, 0, 256, dtlb4k_str },
3740 3740 { 0xb3, 4, 0, 128, dtlb4k_str },
3741 3741 { 0xb2, 4, 0, 64, itlb4k_str },
3742 3742 { 0xb0, 4, 0, 128, itlb4k_str },
3743 3743 { 0x87, 8, 64, 1024*1024, l2_cache_str},
3744 3744 { 0x86, 4, 64, 512*1024, l2_cache_str},
3745 3745 { 0x85, 8, 32, 2*1024*1024, l2_cache_str},
3746 3746 { 0x84, 8, 32, 1024*1024, l2_cache_str},
3747 3747 { 0x83, 8, 32, 512*1024, l2_cache_str},
3748 3748 { 0x82, 8, 32, 256*1024, l2_cache_str},
3749 3749 { 0x80, 8, 64, 512*1024, l2_cache_str},
3750 3750 { 0x7f, 2, 64, 512*1024, l2_cache_str},
3751 3751 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
3752 3752 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
3753 3753 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
3754 3754 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
3755 3755 { 0x79, 8, 64, 128*1024, sl2_cache_str},
3756 3756 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3757 3757 { 0x73, 8, 0, 64*1024, itrace_str},
3758 3758 { 0x72, 8, 0, 32*1024, itrace_str},
3759 3759 { 0x71, 8, 0, 16*1024, itrace_str},
3760 3760 { 0x70, 8, 0, 12*1024, itrace_str},
3761 3761 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
3762 3762 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
3763 3763 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
3764 3764 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
3765 3765 { 0x5d, 0, 0, 256, dtlb44_str},
3766 3766 { 0x5c, 0, 0, 128, dtlb44_str},
3767 3767 { 0x5b, 0, 0, 64, dtlb44_str},
3768 3768 { 0x5a, 4, 0, 32, dtlb24_str},
3769 3769 { 0x59, 0, 0, 16, dtlb4k_str},
3770 3770 { 0x57, 4, 0, 16, dtlb4k_str},
3771 3771 { 0x56, 4, 0, 16, dtlb4M_str},
3772 3772 { 0x55, 0, 0, 7, itlb24_str},
3773 3773 { 0x52, 0, 0, 256, itlb424_str},
3774 3774 { 0x51, 0, 0, 128, itlb424_str},
3775 3775 { 0x50, 0, 0, 64, itlb424_str},
3776 3776 { 0x4f, 0, 0, 32, itlb4k_str},
3777 3777 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str},
3778 3778 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
3779 3779 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
3780 3780 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
3781 3781 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
3782 3782 { 0x49, 16, 64, 4*1024*1024, l3_cache_str},
3783 3783 { 0x48, 12, 64, 3*1024*1024, l2_cache_str},
3784 3784 { 0x47, 8, 64, 8*1024*1024, l3_cache_str},
3785 3785 { 0x46, 4, 64, 4*1024*1024, l3_cache_str},
3786 3786 { 0x45, 4, 32, 2*1024*1024, l2_cache_str},
3787 3787 { 0x44, 4, 32, 1024*1024, l2_cache_str},
3788 3788 { 0x43, 4, 32, 512*1024, l2_cache_str},
3789 3789 { 0x42, 4, 32, 256*1024, l2_cache_str},
3790 3790 { 0x41, 4, 32, 128*1024, l2_cache_str},
3791 3791 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
3792 3792 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
3793 3793 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
3794 3794 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3795 3795 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
3796 3796 { 0x39, 4, 64, 128*1024, sl2_cache_str},
3797 3797 { 0x30, 8, 64, 32*1024, l1_icache_str},
3798 3798 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
3799 3799 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
3800 3800 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
3801 3801 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
3802 3802 { 0x22, 4, 64, 512*1024, sl3_cache_str},
3803 3803 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
3804 3804 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
3805 3805 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3806 3806 { 0x0b, 4, 0, 4, itlb4M_str},
3807 3807 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
3808 3808 { 0x08, 4, 32, 16*1024, l1_icache_str},
3809 3809 { 0x06, 4, 32, 8*1024, l1_icache_str},
3810 3810 { 0x05, 4, 0, 32, dtlb4M_str},
3811 3811 { 0x04, 4, 0, 8, dtlb4M_str},
3812 3812 { 0x03, 4, 0, 64, dtlb4k_str},
3813 3813 { 0x02, 4, 0, 2, itlb4M_str},
3814 3814 { 0x01, 4, 0, 32, itlb4k_str},
3815 3815 { 0 }
3816 3816 };
3817 3817
3818 3818 static const struct cachetab cyrix_ctab[] = {
3819 3819 { 0x70, 4, 0, 32, "tlb-4K" },
3820 3820 { 0x80, 4, 16, 16*1024, "l1-cache" },
3821 3821 { 0 }
3822 3822 };
3823 3823
3824 3824 /*
3825 3825 * Search a cache table for a matching entry
3826 3826 */
3827 3827 static const struct cachetab *
3828 3828 find_cacheent(const struct cachetab *ct, uint_t code)
3829 3829 {
3830 3830 if (code != 0) {
3831 3831 for (; ct->ct_code != 0; ct++)
3832 3832 if (ct->ct_code <= code)
3833 3833 break;
3834 3834 if (ct->ct_code == code)
3835 3835 return (ct);
3836 3836 }
3837 3837 return (NULL);
3838 3838 }
3839 3839
3840 3840 /*
3841 3841 * Populate cachetab entry with L2 or L3 cache-information using
3842 3842 * cpuid function 4. This function is called from intel_walk_cacheinfo()
3843 3843 * when descriptor 0x49 is encountered. It returns 0 if no such cache
3844 3844 * information is found.
3845 3845 */
3846 3846 static int
3847 3847 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
3848 3848 {
3849 3849 uint32_t level, i;
3850 3850 int ret = 0;
3851 3851
3852 3852 for (i = 0; i < cpi->cpi_std_4_size; i++) {
3853 3853 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
3854 3854
3855 3855 if (level == 2 || level == 3) {
3856 3856 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
3857 3857 ct->ct_line_size =
3858 3858 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
3859 3859 ct->ct_size = ct->ct_assoc *
3860 3860 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
3861 3861 ct->ct_line_size *
3862 3862 (cpi->cpi_std_4[i]->cp_ecx + 1);
3863 3863
3864 3864 if (level == 2) {
3865 3865 ct->ct_label = l2_cache_str;
3866 3866 } else if (level == 3) {
3867 3867 ct->ct_label = l3_cache_str;
3868 3868 }
3869 3869 ret = 1;
3870 3870 }
3871 3871 }
3872 3872
3873 3873 return (ret);
3874 3874 }
3875 3875
3876 3876 /*
3877 3877 * Walk the cacheinfo descriptor, applying 'func' to every valid element
3878 3878 * The walk is terminated if the walker returns non-zero.
3879 3879 */
3880 3880 static void
3881 3881 intel_walk_cacheinfo(struct cpuid_info *cpi,
3882 3882 void *arg, int (*func)(void *, const struct cachetab *))
3883 3883 {
3884 3884 const struct cachetab *ct;
3885 3885 struct cachetab des_49_ct, des_b1_ct;
3886 3886 uint8_t *dp;
3887 3887 int i;
3888 3888
3889 3889 if ((dp = cpi->cpi_cacheinfo) == NULL)
3890 3890 return;
3891 3891 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3892 3892 /*
3893 3893 * For overloaded descriptor 0x49 we use cpuid function 4
3894 3894 * if supported by the current processor, to create
3895 3895 * cache information.
3896 3896 * For overloaded descriptor 0xb1 we use X86_PAE flag
3897 3897 * to disambiguate the cache information.
3898 3898 */
3899 3899 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
3900 3900 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
3901 3901 ct = &des_49_ct;
3902 3902 } else if (*dp == 0xb1) {
3903 3903 des_b1_ct.ct_code = 0xb1;
3904 3904 des_b1_ct.ct_assoc = 4;
3905 3905 des_b1_ct.ct_line_size = 0;
3906 3906 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
3907 3907 des_b1_ct.ct_size = 8;
3908 3908 des_b1_ct.ct_label = itlb2M_str;
3909 3909 } else {
3910 3910 des_b1_ct.ct_size = 4;
3911 3911 des_b1_ct.ct_label = itlb4M_str;
3912 3912 }
3913 3913 ct = &des_b1_ct;
3914 3914 } else {
3915 3915 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
3916 3916 continue;
3917 3917 }
3918 3918 }
3919 3919
3920 3920 if (func(arg, ct) != 0) {
3921 3921 break;
3922 3922 }
3923 3923 }
3924 3924 }
3925 3925
3926 3926 /*
3927 3927 * (Like the Intel one, except for Cyrix CPUs)
3928 3928 */
3929 3929 static void
3930 3930 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
3931 3931 void *arg, int (*func)(void *, const struct cachetab *))
3932 3932 {
3933 3933 const struct cachetab *ct;
3934 3934 uint8_t *dp;
3935 3935 int i;
3936 3936
3937 3937 if ((dp = cpi->cpi_cacheinfo) == NULL)
3938 3938 return;
3939 3939 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3940 3940 /*
3941 3941 * Search Cyrix-specific descriptor table first ..
3942 3942 */
3943 3943 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
3944 3944 if (func(arg, ct) != 0)
3945 3945 break;
3946 3946 continue;
3947 3947 }
3948 3948 /*
3949 3949 * .. else fall back to the Intel one
3950 3950 */
3951 3951 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
3952 3952 if (func(arg, ct) != 0)
3953 3953 break;
3954 3954 continue;
3955 3955 }
3956 3956 }
3957 3957 }
3958 3958
3959 3959 /*
3960 3960 * A cacheinfo walker that adds associativity, line-size, and size properties
3961 3961 * to the devinfo node it is passed as an argument.
3962 3962 */
3963 3963 static int
3964 3964 add_cacheent_props(void *arg, const struct cachetab *ct)
3965 3965 {
3966 3966 dev_info_t *devi = arg;
3967 3967
3968 3968 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
3969 3969 if (ct->ct_line_size != 0)
3970 3970 add_cache_prop(devi, ct->ct_label, line_str,
3971 3971 ct->ct_line_size);
3972 3972 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
3973 3973 return (0);
3974 3974 }
3975 3975
3976 3976
3977 3977 static const char fully_assoc[] = "fully-associative?";
3978 3978
3979 3979 /*
3980 3980 * AMD style cache/tlb description
3981 3981 *
3982 3982 * Extended functions 5 and 6 directly describe properties of
3983 3983 * tlbs and various cache levels.
3984 3984 */
3985 3985 static void
3986 3986 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3987 3987 {
3988 3988 switch (assoc) {
3989 3989 case 0: /* reserved; ignore */
3990 3990 break;
3991 3991 default:
3992 3992 add_cache_prop(devi, label, assoc_str, assoc);
3993 3993 break;
3994 3994 case 0xff:
3995 3995 add_cache_prop(devi, label, fully_assoc, 1);
3996 3996 break;
3997 3997 }
3998 3998 }
3999 3999
4000 4000 static void
4001 4001 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4002 4002 {
4003 4003 if (size == 0)
4004 4004 return;
4005 4005 add_cache_prop(devi, label, size_str, size);
4006 4006 add_amd_assoc(devi, label, assoc);
4007 4007 }
4008 4008
4009 4009 static void
4010 4010 add_amd_cache(dev_info_t *devi, const char *label,
4011 4011 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4012 4012 {
4013 4013 if (size == 0 || line_size == 0)
4014 4014 return;
4015 4015 add_amd_assoc(devi, label, assoc);
4016 4016 /*
4017 4017 * Most AMD parts have a sectored cache. Multiple cache lines are
4018 4018 * associated with each tag. A sector consists of all cache lines
4019 4019 * associated with a tag. For example, the AMD K6-III has a sector
4020 4020 * size of 2 cache lines per tag.
4021 4021 */
4022 4022 if (lines_per_tag != 0)
4023 4023 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4024 4024 add_cache_prop(devi, label, line_str, line_size);
4025 4025 add_cache_prop(devi, label, size_str, size * 1024);
4026 4026 }
4027 4027
4028 4028 static void
4029 4029 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4030 4030 {
4031 4031 switch (assoc) {
4032 4032 case 0: /* off */
4033 4033 break;
4034 4034 case 1:
4035 4035 case 2:
4036 4036 case 4:
4037 4037 add_cache_prop(devi, label, assoc_str, assoc);
4038 4038 break;
4039 4039 case 6:
4040 4040 add_cache_prop(devi, label, assoc_str, 8);
4041 4041 break;
4042 4042 case 8:
4043 4043 add_cache_prop(devi, label, assoc_str, 16);
4044 4044 break;
4045 4045 case 0xf:
4046 4046 add_cache_prop(devi, label, fully_assoc, 1);
4047 4047 break;
4048 4048 default: /* reserved; ignore */
4049 4049 break;
4050 4050 }
4051 4051 }
4052 4052
4053 4053 static void
4054 4054 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4055 4055 {
4056 4056 if (size == 0 || assoc == 0)
4057 4057 return;
4058 4058 add_amd_l2_assoc(devi, label, assoc);
4059 4059 add_cache_prop(devi, label, size_str, size);
4060 4060 }
4061 4061
4062 4062 static void
4063 4063 add_amd_l2_cache(dev_info_t *devi, const char *label,
4064 4064 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4065 4065 {
4066 4066 if (size == 0 || assoc == 0 || line_size == 0)
4067 4067 return;
4068 4068 add_amd_l2_assoc(devi, label, assoc);
4069 4069 if (lines_per_tag != 0)
4070 4070 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4071 4071 add_cache_prop(devi, label, line_str, line_size);
4072 4072 add_cache_prop(devi, label, size_str, size * 1024);
4073 4073 }
4074 4074
4075 4075 static void
4076 4076 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
4077 4077 {
4078 4078 struct cpuid_regs *cp;
4079 4079
4080 4080 if (cpi->cpi_xmaxeax < 0x80000005)
4081 4081 return;
4082 4082 cp = &cpi->cpi_extd[5];
4083 4083
4084 4084 /*
4085 4085 * 4M/2M L1 TLB configuration
4086 4086 *
4087 4087 * We report the size for 2M pages because AMD uses two
4088 4088 * TLB entries for one 4M page.
4089 4089 */
4090 4090 add_amd_tlb(devi, "dtlb-2M",
4091 4091 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
4092 4092 add_amd_tlb(devi, "itlb-2M",
4093 4093 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
4094 4094
4095 4095 /*
4096 4096 * 4K L1 TLB configuration
4097 4097 */
4098 4098
4099 4099 switch (cpi->cpi_vendor) {
4100 4100 uint_t nentries;
4101 4101 case X86_VENDOR_TM:
4102 4102 if (cpi->cpi_family >= 5) {
4103 4103 /*
4104 4104 * Crusoe processors have 256 TLB entries, but
4105 4105 * cpuid data format constrains them to only
4106 4106 * reporting 255 of them.
4107 4107 */
4108 4108 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
4109 4109 nentries = 256;
4110 4110 /*
4111 4111 * Crusoe processors also have a unified TLB
4112 4112 */
4113 4113 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
4114 4114 nentries);
4115 4115 break;
4116 4116 }
4117 4117 /*FALLTHROUGH*/
4118 4118 default:
4119 4119 add_amd_tlb(devi, itlb4k_str,
4120 4120 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
4121 4121 add_amd_tlb(devi, dtlb4k_str,
4122 4122 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
4123 4123 break;
4124 4124 }
4125 4125
4126 4126 /*
4127 4127 * data L1 cache configuration
4128 4128 */
4129 4129
4130 4130 add_amd_cache(devi, l1_dcache_str,
4131 4131 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
4132 4132 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
4133 4133
4134 4134 /*
4135 4135 * code L1 cache configuration
4136 4136 */
4137 4137
4138 4138 add_amd_cache(devi, l1_icache_str,
4139 4139 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
4140 4140 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
4141 4141
4142 4142 if (cpi->cpi_xmaxeax < 0x80000006)
4143 4143 return;
4144 4144 cp = &cpi->cpi_extd[6];
4145 4145
4146 4146 /* Check for a unified L2 TLB for large pages */
4147 4147
4148 4148 if (BITX(cp->cp_eax, 31, 16) == 0)
4149 4149 add_amd_l2_tlb(devi, "l2-tlb-2M",
4150 4150 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4151 4151 else {
4152 4152 add_amd_l2_tlb(devi, "l2-dtlb-2M",
4153 4153 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4154 4154 add_amd_l2_tlb(devi, "l2-itlb-2M",
4155 4155 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4156 4156 }
4157 4157
4158 4158 /* Check for a unified L2 TLB for 4K pages */
4159 4159
4160 4160 if (BITX(cp->cp_ebx, 31, 16) == 0) {
4161 4161 add_amd_l2_tlb(devi, "l2-tlb-4K",
4162 4162 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4163 4163 } else {
4164 4164 add_amd_l2_tlb(devi, "l2-dtlb-4K",
4165 4165 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4166 4166 add_amd_l2_tlb(devi, "l2-itlb-4K",
4167 4167 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4168 4168 }
4169 4169
4170 4170 add_amd_l2_cache(devi, l2_cache_str,
4171 4171 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
4172 4172 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
4173 4173 }
4174 4174
4175 4175 /*
4176 4176 * There are two basic ways that the x86 world describes it cache
4177 4177 * and tlb architecture - Intel's way and AMD's way.
4178 4178 *
4179 4179 * Return which flavor of cache architecture we should use
4180 4180 */
4181 4181 static int
4182 4182 x86_which_cacheinfo(struct cpuid_info *cpi)
4183 4183 {
4184 4184 switch (cpi->cpi_vendor) {
4185 4185 case X86_VENDOR_Intel:
4186 4186 if (cpi->cpi_maxeax >= 2)
4187 4187 return (X86_VENDOR_Intel);
4188 4188 break;
4189 4189 case X86_VENDOR_AMD:
4190 4190 /*
4191 4191 * The K5 model 1 was the first part from AMD that reported
4192 4192 * cache sizes via extended cpuid functions.
4193 4193 */
4194 4194 if (cpi->cpi_family > 5 ||
4195 4195 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
4196 4196 return (X86_VENDOR_AMD);
4197 4197 break;
4198 4198 case X86_VENDOR_TM:
4199 4199 if (cpi->cpi_family >= 5)
4200 4200 return (X86_VENDOR_AMD);
4201 4201 /*FALLTHROUGH*/
4202 4202 default:
4203 4203 /*
4204 4204 * If they have extended CPU data for 0x80000005
4205 4205 * then we assume they have AMD-format cache
4206 4206 * information.
4207 4207 *
4208 4208 * If not, and the vendor happens to be Cyrix,
4209 4209 * then try our-Cyrix specific handler.
4210 4210 *
4211 4211 * If we're not Cyrix, then assume we're using Intel's
4212 4212 * table-driven format instead.
4213 4213 */
4214 4214 if (cpi->cpi_xmaxeax >= 0x80000005)
4215 4215 return (X86_VENDOR_AMD);
4216 4216 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
4217 4217 return (X86_VENDOR_Cyrix);
4218 4218 else if (cpi->cpi_maxeax >= 2)
4219 4219 return (X86_VENDOR_Intel);
4220 4220 break;
4221 4221 }
4222 4222 return (-1);
4223 4223 }
4224 4224
4225 4225 void
4226 4226 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
4227 4227 struct cpuid_info *cpi)
4228 4228 {
4229 4229 dev_info_t *cpu_devi;
4230 4230 int create;
4231 4231
4232 4232 cpu_devi = (dev_info_t *)dip;
4233 4233
4234 4234 /* device_type */
4235 4235 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4236 4236 "device_type", "cpu");
4237 4237
4238 4238 /* reg */
4239 4239 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4240 4240 "reg", cpu_id);
4241 4241
4242 4242 /* cpu-mhz, and clock-frequency */
4243 4243 if (cpu_freq > 0) {
4244 4244 long long mul;
4245 4245
4246 4246 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4247 4247 "cpu-mhz", cpu_freq);
4248 4248 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
4249 4249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4250 4250 "clock-frequency", (int)mul);
4251 4251 }
4252 4252
4253 4253 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
4254 4254 return;
4255 4255 }
4256 4256
4257 4257 /* vendor-id */
4258 4258 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4259 4259 "vendor-id", cpi->cpi_vendorstr);
4260 4260
4261 4261 if (cpi->cpi_maxeax == 0) {
4262 4262 return;
4263 4263 }
4264 4264
4265 4265 /*
4266 4266 * family, model, and step
4267 4267 */
4268 4268 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4269 4269 "family", CPI_FAMILY(cpi));
4270 4270 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4271 4271 "cpu-model", CPI_MODEL(cpi));
4272 4272 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4273 4273 "stepping-id", CPI_STEP(cpi));
4274 4274
4275 4275 /* type */
4276 4276 switch (cpi->cpi_vendor) {
4277 4277 case X86_VENDOR_Intel:
4278 4278 create = 1;
4279 4279 break;
4280 4280 default:
4281 4281 create = 0;
4282 4282 break;
4283 4283 }
4284 4284 if (create)
4285 4285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4286 4286 "type", CPI_TYPE(cpi));
4287 4287
4288 4288 /* ext-family */
4289 4289 switch (cpi->cpi_vendor) {
4290 4290 case X86_VENDOR_Intel:
4291 4291 case X86_VENDOR_AMD:
4292 4292 create = cpi->cpi_family >= 0xf;
4293 4293 break;
4294 4294 default:
4295 4295 create = 0;
4296 4296 break;
4297 4297 }
4298 4298 if (create)
4299 4299 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4300 4300 "ext-family", CPI_FAMILY_XTD(cpi));
4301 4301
4302 4302 /* ext-model */
4303 4303 switch (cpi->cpi_vendor) {
4304 4304 case X86_VENDOR_Intel:
4305 4305 create = IS_EXTENDED_MODEL_INTEL(cpi);
4306 4306 break;
4307 4307 case X86_VENDOR_AMD:
4308 4308 create = CPI_FAMILY(cpi) == 0xf;
4309 4309 break;
4310 4310 default:
4311 4311 create = 0;
4312 4312 break;
4313 4313 }
4314 4314 if (create)
4315 4315 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4316 4316 "ext-model", CPI_MODEL_XTD(cpi));
4317 4317
4318 4318 /* generation */
4319 4319 switch (cpi->cpi_vendor) {
4320 4320 case X86_VENDOR_AMD:
4321 4321 /*
4322 4322 * AMD K5 model 1 was the first part to support this
4323 4323 */
4324 4324 create = cpi->cpi_xmaxeax >= 0x80000001;
4325 4325 break;
4326 4326 default:
4327 4327 create = 0;
4328 4328 break;
4329 4329 }
4330 4330 if (create)
4331 4331 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4332 4332 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
4333 4333
4334 4334 /* brand-id */
4335 4335 switch (cpi->cpi_vendor) {
4336 4336 case X86_VENDOR_Intel:
4337 4337 /*
4338 4338 * brand id first appeared on Pentium III Xeon model 8,
4339 4339 * and Celeron model 8 processors and Opteron
4340 4340 */
4341 4341 create = cpi->cpi_family > 6 ||
4342 4342 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
4343 4343 break;
4344 4344 case X86_VENDOR_AMD:
4345 4345 create = cpi->cpi_family >= 0xf;
4346 4346 break;
4347 4347 default:
4348 4348 create = 0;
4349 4349 break;
4350 4350 }
4351 4351 if (create && cpi->cpi_brandid != 0) {
4352 4352 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4353 4353 "brand-id", cpi->cpi_brandid);
4354 4354 }
4355 4355
4356 4356 /* chunks, and apic-id */
4357 4357 switch (cpi->cpi_vendor) {
4358 4358 /*
4359 4359 * first available on Pentium IV and Opteron (K8)
4360 4360 */
4361 4361 case X86_VENDOR_Intel:
4362 4362 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4363 4363 break;
4364 4364 case X86_VENDOR_AMD:
4365 4365 create = cpi->cpi_family >= 0xf;
4366 4366 break;
4367 4367 default:
4368 4368 create = 0;
4369 4369 break;
4370 4370 }
4371 4371 if (create) {
4372 4372 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4373 4373 "chunks", CPI_CHUNKS(cpi));
4374 4374 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4375 4375 "apic-id", cpi->cpi_apicid);
4376 4376 if (cpi->cpi_chipid >= 0) {
4377 4377 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4378 4378 "chip#", cpi->cpi_chipid);
4379 4379 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4380 4380 "clog#", cpi->cpi_clogid);
4381 4381 }
4382 4382 }
4383 4383
4384 4384 /* cpuid-features */
4385 4385 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4386 4386 "cpuid-features", CPI_FEATURES_EDX(cpi));
4387 4387
4388 4388
4389 4389 /* cpuid-features-ecx */
4390 4390 switch (cpi->cpi_vendor) {
4391 4391 case X86_VENDOR_Intel:
4392 4392 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4393 4393 break;
4394 4394 case X86_VENDOR_AMD:
4395 4395 create = cpi->cpi_family >= 0xf;
4396 4396 break;
4397 4397 default:
4398 4398 create = 0;
4399 4399 break;
4400 4400 }
4401 4401 if (create)
4402 4402 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4403 4403 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4404 4404
4405 4405 /* ext-cpuid-features */
4406 4406 switch (cpi->cpi_vendor) {
4407 4407 case X86_VENDOR_Intel:
4408 4408 case X86_VENDOR_AMD:
4409 4409 case X86_VENDOR_Cyrix:
4410 4410 case X86_VENDOR_TM:
4411 4411 case X86_VENDOR_Centaur:
4412 4412 create = cpi->cpi_xmaxeax >= 0x80000001;
4413 4413 break;
4414 4414 default:
4415 4415 create = 0;
4416 4416 break;
4417 4417 }
4418 4418 if (create) {
4419 4419 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4420 4420 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
4421 4421 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4422 4422 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
4423 4423 }
4424 4424
4425 4425 /*
4426 4426 * Brand String first appeared in Intel Pentium IV, AMD K5
4427 4427 * model 1, and Cyrix GXm. On earlier models we try and
4428 4428 * simulate something similar .. so this string should always
4429 4429 * same -something- about the processor, however lame.
4430 4430 */
4431 4431 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4432 4432 "brand-string", cpi->cpi_brandstr);
4433 4433
4434 4434 /*
4435 4435 * Finally, cache and tlb information
4436 4436 */
4437 4437 switch (x86_which_cacheinfo(cpi)) {
4438 4438 case X86_VENDOR_Intel:
4439 4439 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4440 4440 break;
4441 4441 case X86_VENDOR_Cyrix:
4442 4442 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4443 4443 break;
4444 4444 case X86_VENDOR_AMD:
4445 4445 amd_cache_info(cpi, cpu_devi);
4446 4446 break;
4447 4447 default:
4448 4448 break;
4449 4449 }
4450 4450 }
4451 4451
4452 4452 struct l2info {
4453 4453 int *l2i_csz;
4454 4454 int *l2i_lsz;
4455 4455 int *l2i_assoc;
4456 4456 int l2i_ret;
4457 4457 };
4458 4458
4459 4459 /*
4460 4460 * A cacheinfo walker that fetches the size, line-size and associativity
4461 4461 * of the L2 cache
4462 4462 */
4463 4463 static int
4464 4464 intel_l2cinfo(void *arg, const struct cachetab *ct)
4465 4465 {
4466 4466 struct l2info *l2i = arg;
4467 4467 int *ip;
4468 4468
4469 4469 if (ct->ct_label != l2_cache_str &&
4470 4470 ct->ct_label != sl2_cache_str)
4471 4471 return (0); /* not an L2 -- keep walking */
4472 4472
4473 4473 if ((ip = l2i->l2i_csz) != NULL)
4474 4474 *ip = ct->ct_size;
4475 4475 if ((ip = l2i->l2i_lsz) != NULL)
4476 4476 *ip = ct->ct_line_size;
4477 4477 if ((ip = l2i->l2i_assoc) != NULL)
4478 4478 *ip = ct->ct_assoc;
4479 4479 l2i->l2i_ret = ct->ct_size;
4480 4480 return (1); /* was an L2 -- terminate walk */
4481 4481 }
4482 4482
4483 4483 /*
4484 4484 * AMD L2/L3 Cache and TLB Associativity Field Definition:
4485 4485 *
4486 4486 * Unlike the associativity for the L1 cache and tlb where the 8 bit
4487 4487 * value is the associativity, the associativity for the L2 cache and
4488 4488 * tlb is encoded in the following table. The 4 bit L2 value serves as
4489 4489 * an index into the amd_afd[] array to determine the associativity.
4490 4490 * -1 is undefined. 0 is fully associative.
4491 4491 */
4492 4492
4493 4493 static int amd_afd[] =
4494 4494 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
4495 4495
4496 4496 static void
4497 4497 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
4498 4498 {
4499 4499 struct cpuid_regs *cp;
4500 4500 uint_t size, assoc;
4501 4501 int i;
4502 4502 int *ip;
4503 4503
4504 4504 if (cpi->cpi_xmaxeax < 0x80000006)
4505 4505 return;
4506 4506 cp = &cpi->cpi_extd[6];
4507 4507
4508 4508 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
4509 4509 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
4510 4510 uint_t cachesz = size * 1024;
4511 4511 assoc = amd_afd[i];
4512 4512
4513 4513 ASSERT(assoc != -1);
4514 4514
4515 4515 if ((ip = l2i->l2i_csz) != NULL)
4516 4516 *ip = cachesz;
4517 4517 if ((ip = l2i->l2i_lsz) != NULL)
4518 4518 *ip = BITX(cp->cp_ecx, 7, 0);
4519 4519 if ((ip = l2i->l2i_assoc) != NULL)
4520 4520 *ip = assoc;
4521 4521 l2i->l2i_ret = cachesz;
4522 4522 }
4523 4523 }
4524 4524
4525 4525 int
4526 4526 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
4527 4527 {
4528 4528 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
4529 4529 struct l2info __l2info, *l2i = &__l2info;
4530 4530
4531 4531 l2i->l2i_csz = csz;
4532 4532 l2i->l2i_lsz = lsz;
4533 4533 l2i->l2i_assoc = assoc;
4534 4534 l2i->l2i_ret = -1;
4535 4535
4536 4536 switch (x86_which_cacheinfo(cpi)) {
4537 4537 case X86_VENDOR_Intel:
4538 4538 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4539 4539 break;
4540 4540 case X86_VENDOR_Cyrix:
4541 4541 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4542 4542 break;
4543 4543 case X86_VENDOR_AMD:
4544 4544 amd_l2cacheinfo(cpi, l2i);
4545 4545 break;
4546 4546 default:
4547 4547 break;
4548 4548 }
4549 4549 return (l2i->l2i_ret);
4550 4550 }
4551 4551
4552 4552 #if !defined(__xpv)
4553 4553
4554 4554 uint32_t *
4555 4555 cpuid_mwait_alloc(cpu_t *cpu)
4556 4556 {
4557 4557 uint32_t *ret;
4558 4558 size_t mwait_size;
4559 4559
4560 4560 ASSERT(cpuid_checkpass(CPU, 2));
4561 4561
4562 4562 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
4563 4563 if (mwait_size == 0)
4564 4564 return (NULL);
4565 4565
4566 4566 /*
4567 4567 * kmem_alloc() returns cache line size aligned data for mwait_size
4568 4568 * allocations. mwait_size is currently cache line sized. Neither
4569 4569 * of these implementation details are guarantied to be true in the
4570 4570 * future.
4571 4571 *
4572 4572 * First try allocating mwait_size as kmem_alloc() currently returns
4573 4573 * correctly aligned memory. If kmem_alloc() does not return
4574 4574 * mwait_size aligned memory, then use mwait_size ROUNDUP.
4575 4575 *
4576 4576 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
4577 4577 * decide to free this memory.
4578 4578 */
4579 4579 ret = kmem_zalloc(mwait_size, KM_SLEEP);
4580 4580 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
4581 4581 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4582 4582 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
4583 4583 *ret = MWAIT_RUNNING;
4584 4584 return (ret);
4585 4585 } else {
4586 4586 kmem_free(ret, mwait_size);
4587 4587 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
4588 4588 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4589 4589 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
4590 4590 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
4591 4591 *ret = MWAIT_RUNNING;
4592 4592 return (ret);
4593 4593 }
4594 4594 }
4595 4595
4596 4596 void
4597 4597 cpuid_mwait_free(cpu_t *cpu)
4598 4598 {
4599 4599 if (cpu->cpu_m.mcpu_cpi == NULL) {
4600 4600 return;
4601 4601 }
4602 4602
4603 4603 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
4604 4604 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
4605 4605 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
4606 4606 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
4607 4607 }
4608 4608
4609 4609 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
4610 4610 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4611 4611 }
4612 4612
4613 4613 void
4614 4614 patch_tsc_read(int flag)
4615 4615 {
4616 4616 size_t cnt;
4617 4617
4618 4618 switch (flag) {
4619 4619 case TSC_NONE:
4620 4620 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
4621 4621 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
4622 4622 break;
4623 4623 case TSC_RDTSC_MFENCE:
4624 4624 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
4625 4625 (void) memcpy((void *)tsc_read,
4626 4626 (void *)&_tsc_mfence_start, cnt);
4627 4627 break;
4628 4628 case TSC_RDTSC_LFENCE:
4629 4629 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
4630 4630 (void) memcpy((void *)tsc_read,
4631 4631 (void *)&_tsc_lfence_start, cnt);
4632 4632 break;
4633 4633 case TSC_TSCP:
4634 4634 cnt = &_tscp_end - &_tscp_start;
4635 4635 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
4636 4636 break;
4637 4637 default:
4638 4638 /* Bail for unexpected TSC types. (TSC_NONE covers 0) */
4639 4639 cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag);
4640 4640 break;
4641 4641 }
4642 4642 tsc_type = flag;
4643 4643 }
4644 4644
4645 4645 int
4646 4646 cpuid_deep_cstates_supported(void)
4647 4647 {
4648 4648 struct cpuid_info *cpi;
4649 4649 struct cpuid_regs regs;
4650 4650
4651 4651 ASSERT(cpuid_checkpass(CPU, 1));
4652 4652
4653 4653 cpi = CPU->cpu_m.mcpu_cpi;
4654 4654
4655 4655 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
4656 4656 return (0);
4657 4657
4658 4658 switch (cpi->cpi_vendor) {
4659 4659 case X86_VENDOR_Intel:
4660 4660 if (cpi->cpi_xmaxeax < 0x80000007)
4661 4661 return (0);
4662 4662
4663 4663 /*
4664 4664 * TSC run at a constant rate in all ACPI C-states?
4665 4665 */
4666 4666 regs.cp_eax = 0x80000007;
4667 4667 (void) __cpuid_insn(®s);
4668 4668 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
4669 4669
4670 4670 default:
4671 4671 return (0);
4672 4672 }
4673 4673 }
4674 4674
4675 4675 #endif /* !__xpv */
4676 4676
4677 4677 void
4678 4678 post_startup_cpu_fixups(void)
4679 4679 {
4680 4680 #ifndef __xpv
4681 4681 /*
4682 4682 * Some AMD processors support C1E state. Entering this state will
4683 4683 * cause the local APIC timer to stop, which we can't deal with at
4684 4684 * this time.
4685 4685 */
4686 4686 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
4687 4687 on_trap_data_t otd;
4688 4688 uint64_t reg;
4689 4689
4690 4690 if (!on_trap(&otd, OT_DATA_ACCESS)) {
4691 4691 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
4692 4692 /* Disable C1E state if it is enabled by BIOS */
4693 4693 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
4694 4694 AMD_ACTONCMPHALT_MASK) {
4695 4695 reg &= ~(AMD_ACTONCMPHALT_MASK <<
4696 4696 AMD_ACTONCMPHALT_SHIFT);
4697 4697 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
4698 4698 }
4699 4699 }
4700 4700 no_trap();
4701 4701 }
4702 4702 #endif /* !__xpv */
4703 4703 }
4704 4704
4705 4705 /*
4706 4706 * Setup necessary registers to enable XSAVE feature on this processor.
4707 4707 * This function needs to be called early enough, so that no xsave/xrstor
4708 4708 * ops will execute on the processor before the MSRs are properly set up.
4709 4709 *
4710 4710 * Current implementation has the following assumption:
4711 4711 * - cpuid_pass1() is done, so that X86 features are known.
4712 4712 * - fpu_probe() is done, so that fp_save_mech is chosen.
4713 4713 */
4714 4714 void
4715 4715 xsave_setup_msr(cpu_t *cpu)
4716 4716 {
4717 4717 ASSERT(fp_save_mech == FP_XSAVE);
4718 4718 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
4719 4719
4720 4720 /* Enable OSXSAVE in CR4. */
4721 4721 setcr4(getcr4() | CR4_OSXSAVE);
4722 4722 /*
4723 4723 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
4724 4724 * correct value.
4725 4725 */
4726 4726 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE;
4727 4727 setup_xfem();
4728 4728 }
4729 4729
4730 4730 /*
4731 4731 * Starting with the Westmere processor the local
4732 4732 * APIC timer will continue running in all C-states,
4733 4733 * including the deepest C-states.
4734 4734 */
4735 4735 int
4736 4736 cpuid_arat_supported(void)
4737 4737 {
4738 4738 struct cpuid_info *cpi;
4739 4739 struct cpuid_regs regs;
4740 4740
4741 4741 ASSERT(cpuid_checkpass(CPU, 1));
4742 4742 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4743 4743
4744 4744 cpi = CPU->cpu_m.mcpu_cpi;
4745 4745
4746 4746 switch (cpi->cpi_vendor) {
4747 4747 case X86_VENDOR_Intel:
4748 4748 /*
4749 4749 * Always-running Local APIC Timer is
4750 4750 * indicated by CPUID.6.EAX[2].
4751 4751 */
4752 4752 if (cpi->cpi_maxeax >= 6) {
4753 4753 regs.cp_eax = 6;
4754 4754 (void) cpuid_insn(NULL, ®s);
4755 4755 return (regs.cp_eax & CPUID_CSTATE_ARAT);
4756 4756 } else {
4757 4757 return (0);
4758 4758 }
4759 4759 default:
4760 4760 return (0);
4761 4761 }
4762 4762 }
4763 4763
4764 4764 /*
4765 4765 * Check support for Intel ENERGY_PERF_BIAS feature
4766 4766 */
4767 4767 int
4768 4768 cpuid_iepb_supported(struct cpu *cp)
4769 4769 {
4770 4770 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
4771 4771 struct cpuid_regs regs;
4772 4772
4773 4773 ASSERT(cpuid_checkpass(cp, 1));
4774 4774
4775 4775 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) ||
4776 4776 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
4777 4777 return (0);
4778 4778 }
4779 4779
4780 4780 /*
4781 4781 * Intel ENERGY_PERF_BIAS MSR is indicated by
4782 4782 * capability bit CPUID.6.ECX.3
4783 4783 */
4784 4784 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6))
4785 4785 return (0);
4786 4786
4787 4787 regs.cp_eax = 0x6;
4788 4788 (void) cpuid_insn(NULL, ®s);
4789 4789 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
4790 4790 }
4791 4791
4792 4792 /*
4793 4793 * Check support for TSC deadline timer
4794 4794 *
4795 4795 * TSC deadline timer provides a superior software programming
4796 4796 * model over local APIC timer that eliminates "time drifts".
4797 4797 * Instead of specifying a relative time, software specifies an
4798 4798 * absolute time as the target at which the processor should
4799 4799 * generate a timer event.
4800 4800 */
4801 4801 int
4802 4802 cpuid_deadline_tsc_supported(void)
4803 4803 {
4804 4804 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
4805 4805 struct cpuid_regs regs;
4806 4806
4807 4807 ASSERT(cpuid_checkpass(CPU, 1));
4808 4808 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4809 4809
4810 4810 switch (cpi->cpi_vendor) {
4811 4811 case X86_VENDOR_Intel:
4812 4812 if (cpi->cpi_maxeax >= 1) {
4813 4813 regs.cp_eax = 1;
4814 4814 (void) cpuid_insn(NULL, ®s);
4815 4815 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
4816 4816 } else {
4817 4817 return (0);
4818 4818 }
4819 4819 default:
4820 4820 return (0);
4821 4821 }
4822 4822 }
4823 4823
4824 4824 #if defined(__amd64) && !defined(__xpv)
4825 4825 /*
4826 4826 * Patch in versions of bcopy for high performance Intel Nhm processors
4827 4827 * and later...
4828 4828 */
4829 4829 void
4830 4830 patch_memops(uint_t vendor)
4831 4831 {
4832 4832 size_t cnt, i;
4833 4833 caddr_t to, from;
4834 4834
4835 4835 if ((vendor == X86_VENDOR_Intel) &&
4836 4836 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
4837 4837 cnt = &bcopy_patch_end - &bcopy_patch_start;
4838 4838 to = &bcopy_ck_size;
4839 4839 from = &bcopy_patch_start;
4840 4840 for (i = 0; i < cnt; i++) {
4841 4841 *to++ = *from++;
4842 4842 }
4843 4843 }
4844 4844 }
4845 4845 #endif /* __amd64 && !__xpv */
4846 4846
4847 4847 /*
4848 4848 * This function finds the number of bits to represent the number of cores per
4849 4849 * chip and the number of strands per core for the Intel platforms.
4850 4850 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
4851 4851 */
4852 4852 void
4853 4853 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits)
4854 4854 {
4855 4855 struct cpuid_regs regs;
4856 4856 struct cpuid_regs *cp = ®s;
4857 4857
4858 4858 if (vendor != X86_VENDOR_Intel) {
4859 4859 return;
4860 4860 }
4861 4861
4862 4862 /* if the cpuid level is 0xB, extended topo is available. */
4863 4863 cp->cp_eax = 0;
4864 4864 if (__cpuid_insn(cp) >= 0xB) {
4865 4865
4866 4866 cp->cp_eax = 0xB;
4867 4867 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
4868 4868 (void) __cpuid_insn(cp);
4869 4869
4870 4870 /*
4871 4871 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
4872 4872 * indicates that the extended topology enumeration leaf is
4873 4873 * available.
4874 4874 */
4875 4875 if (cp->cp_ebx) {
4876 4876 uint_t coreid_shift = 0;
4877 4877 uint_t chipid_shift = 0;
4878 4878 uint_t i;
4879 4879 uint_t level;
4880 4880
4881 4881 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
4882 4882 cp->cp_eax = 0xB;
4883 4883 cp->cp_ecx = i;
4884 4884
4885 4885 (void) __cpuid_insn(cp);
4886 4886 level = CPI_CPU_LEVEL_TYPE(cp);
4887 4887
4888 4888 if (level == 1) {
4889 4889 /*
4890 4890 * Thread level processor topology
4891 4891 * Number of bits shift right APIC ID
4892 4892 * to get the coreid.
4893 4893 */
4894 4894 coreid_shift = BITX(cp->cp_eax, 4, 0);
4895 4895 } else if (level == 2) {
4896 4896 /*
4897 4897 * Core level processor topology
4898 4898 * Number of bits shift right APIC ID
4899 4899 * to get the chipid.
4900 4900 */
4901 4901 chipid_shift = BITX(cp->cp_eax, 4, 0);
4902 4902 }
4903 4903 }
4904 4904
4905 4905 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
4906 4906 *strand_nbits = coreid_shift;
4907 4907 *core_nbits = chipid_shift - coreid_shift;
4908 4908 }
4909 4909 }
4910 4910 }
4911 4911 }
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