1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
26 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31 /*
32 * Portions Copyright 2009 Advanced Micro Devices, Inc.
33 */
34 /*
35 * Copyright 2016 Joyent, Inc.
36 */
37 /*
38 * Various routines to handle identification
39 * and classification of x86 processors.
40 */
41
42 #include <sys/types.h>
43 #include <sys/archsystm.h>
44 #include <sys/x86_archext.h>
45 #include <sys/kmem.h>
46 #include <sys/systm.h>
47 #include <sys/cmn_err.h>
48 #include <sys/sunddi.h>
49 #include <sys/sunndi.h>
50 #include <sys/cpuvar.h>
51 #include <sys/processor.h>
52 #include <sys/sysmacros.h>
53 #include <sys/pg.h>
54 #include <sys/fp.h>
55 #include <sys/controlregs.h>
56 #include <sys/bitmap.h>
57 #include <sys/auxv_386.h>
58 #include <sys/memnode.h>
59 #include <sys/pci_cfgspace.h>
60 #include <sys/comm_page.h>
61 #include <sys/tsc.h>
62
63 #ifdef __xpv
64 #include <sys/hypervisor.h>
65 #else
66 #include <sys/ontrap.h>
67 #endif
68
69 /*
70 * Pass 0 of cpuid feature analysis happens in locore. It contains special code
71 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
72 * them accordingly. For most modern processors, feature detection occurs here
73 * in pass 1.
74 *
75 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
76 * for the boot CPU and does the basic analysis that the early kernel needs.
77 * x86_featureset is set based on the return value of cpuid_pass1() of the boot
78 * CPU.
79 *
80 * Pass 1 includes:
81 *
82 * o Determining vendor/model/family/stepping and setting x86_type and
83 * x86_vendor accordingly.
84 * o Processing the feature flags returned by the cpuid instruction while
85 * applying any workarounds or tricks for the specific processor.
86 * o Mapping the feature flags into Solaris feature bits (X86_*).
87 * o Processing extended feature flags if supported by the processor,
88 * again while applying specific processor knowledge.
89 * o Determining the CMT characteristics of the system.
90 *
91 * Pass 1 is done on non-boot CPUs during their initialization and the results
92 * are used only as a meager attempt at ensuring that all processors within the
93 * system support the same features.
94 *
95 * Pass 2 of cpuid feature analysis happens just at the beginning
96 * of startup(). It just copies in and corrects the remainder
97 * of the cpuid data we depend on: standard cpuid functions that we didn't
98 * need for pass1 feature analysis, and extended cpuid functions beyond the
99 * simple feature processing done in pass1.
100 *
101 * Pass 3 of cpuid analysis is invoked after basic kernel services; in
102 * particular kernel memory allocation has been made available. It creates a
103 * readable brand string based on the data collected in the first two passes.
104 *
105 * Pass 4 of cpuid analysis is invoked after post_startup() when all
106 * the support infrastructure for various hardware features has been
107 * initialized. It determines which processor features will be reported
108 * to userland via the aux vector.
109 *
110 * All passes are executed on all CPUs, but only the boot CPU determines what
111 * features the kernel will use.
112 *
113 * Much of the worst junk in this file is for the support of processors
114 * that didn't really implement the cpuid instruction properly.
115 *
116 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
117 * the pass numbers. Accordingly, changes to the pass code may require changes
118 * to the accessor code.
119 */
120
121 uint_t x86_vendor = X86_VENDOR_IntelClone;
122 uint_t x86_type = X86_TYPE_OTHER;
123 uint_t x86_clflush_size = 0;
124
125 uint_t pentiumpro_bug4046376;
126
127 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
128
129 static char *x86_feature_names[NUM_X86_FEATURES] = {
130 "lgpg",
131 "tsc",
132 "msr",
133 "mtrr",
134 "pge",
135 "de",
136 "cmov",
137 "mmx",
138 "mca",
139 "pae",
140 "cv8",
141 "pat",
142 "sep",
143 "sse",
144 "sse2",
145 "htt",
146 "asysc",
147 "nx",
148 "sse3",
149 "cx16",
150 "cmp",
151 "tscp",
152 "mwait",
153 "sse4a",
154 "cpuid",
155 "ssse3",
156 "sse4_1",
157 "sse4_2",
158 "1gpg",
159 "clfsh",
160 "64",
161 "aes",
162 "pclmulqdq",
163 "xsave",
164 "avx",
165 "vmx",
166 "svm",
167 "topoext",
168 "f16c",
169 "rdrand",
170 "x2apic",
171 "avx2",
172 "bmi1",
173 "bmi2",
174 "fma",
175 "smep",
176 "smap",
177 "adx",
178 "rdseed"
179 };
180
181 boolean_t
182 is_x86_feature(void *featureset, uint_t feature)
183 {
184 ASSERT(feature < NUM_X86_FEATURES);
185 return (BT_TEST((ulong_t *)featureset, feature));
186 }
187
188 void
189 add_x86_feature(void *featureset, uint_t feature)
190 {
191 ASSERT(feature < NUM_X86_FEATURES);
192 BT_SET((ulong_t *)featureset, feature);
193 }
194
195 void
196 remove_x86_feature(void *featureset, uint_t feature)
197 {
198 ASSERT(feature < NUM_X86_FEATURES);
199 BT_CLEAR((ulong_t *)featureset, feature);
200 }
201
202 boolean_t
203 compare_x86_featureset(void *setA, void *setB)
204 {
205 /*
206 * We assume that the unused bits of the bitmap are always zero.
207 */
208 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) {
209 return (B_TRUE);
210 } else {
211 return (B_FALSE);
212 }
213 }
214
215 void
216 print_x86_featureset(void *featureset)
217 {
218 uint_t i;
219
220 for (i = 0; i < NUM_X86_FEATURES; i++) {
221 if (is_x86_feature(featureset, i)) {
222 cmn_err(CE_CONT, "?x86_feature: %s\n",
223 x86_feature_names[i]);
224 }
225 }
226 }
227
228 static size_t xsave_state_size = 0;
229 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE);
230 boolean_t xsave_force_disable = B_FALSE;
231 extern int disable_smap;
232
233 /*
234 * This is set to platform type we are running on.
235 */
236 static int platform_type = -1;
237
238 #if !defined(__xpv)
239 /*
240 * Variable to patch if hypervisor platform detection needs to be
241 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0).
242 */
243 int enable_platform_detection = 1;
244 #endif
245
246 /*
247 * monitor/mwait info.
248 *
249 * size_actual and buf_actual are the real address and size allocated to get
250 * proper mwait_buf alignement. buf_actual and size_actual should be passed
251 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use
252 * processor cache-line alignment, but this is not guarantied in the furture.
253 */
254 struct mwait_info {
255 size_t mon_min; /* min size to avoid missed wakeups */
256 size_t mon_max; /* size to avoid false wakeups */
257 size_t size_actual; /* size actually allocated */
258 void *buf_actual; /* memory actually allocated */
259 uint32_t support; /* processor support of monitor/mwait */
260 };
261
262 /*
263 * xsave/xrestor info.
264 *
265 * This structure contains HW feature bits and size of the xsave save area.
266 * Note: the kernel will use the maximum size required for all hardware
267 * features. It is not optimize for potential memory savings if features at
268 * the end of the save area are not enabled.
269 */
270 struct xsave_info {
271 uint32_t xsav_hw_features_low; /* Supported HW features */
272 uint32_t xsav_hw_features_high; /* Supported HW features */
273 size_t xsav_max_size; /* max size save area for HW features */
274 size_t ymm_size; /* AVX: size of ymm save area */
275 size_t ymm_offset; /* AVX: offset for ymm save area */
276 };
277
278
279 /*
280 * These constants determine how many of the elements of the
281 * cpuid we cache in the cpuid_info data structure; the
282 * remaining elements are accessible via the cpuid instruction.
283 */
284
285 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */
286 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */
287
288 /*
289 * Some terminology needs to be explained:
290 * - Socket: Something that can be plugged into a motherboard.
291 * - Package: Same as socket
292 * - Chip: Same as socket. Note that AMD's documentation uses term "chip"
293 * differently: there, chip is the same as processor node (below)
294 * - Processor node: Some AMD processors have more than one
295 * "subprocessor" embedded in a package. These subprocessors (nodes)
296 * are fully-functional processors themselves with cores, caches,
297 * memory controllers, PCI configuration spaces. They are connected
298 * inside the package with Hypertransport links. On single-node
299 * processors, processor node is equivalent to chip/socket/package.
300 * - Compute Unit: Some AMD processors pair cores in "compute units" that
301 * share the FPU and the I$ and L2 caches.
302 */
303
304 struct cpuid_info {
305 uint_t cpi_pass; /* last pass completed */
306 /*
307 * standard function information
308 */
309 uint_t cpi_maxeax; /* fn 0: %eax */
310 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
311 uint_t cpi_vendor; /* enum of cpi_vendorstr */
312
313 uint_t cpi_family; /* fn 1: extended family */
314 uint_t cpi_model; /* fn 1: extended model */
315 uint_t cpi_step; /* fn 1: stepping */
316 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */
317 /* AMD: package/socket # */
318 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */
319 int cpi_clogid; /* fn 1: %ebx: thread # */
320 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */
321 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */
322 uint_t cpi_ncache; /* fn 2: number of elements */
323 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */
324 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */
325 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */
326 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */
327 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */
328 /*
329 * extended function information
330 */
331 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */
332 char cpi_brandstr[49]; /* fn 0x8000000[234] */
333 uint8_t cpi_pabits; /* fn 0x80000006: %eax */
334 uint8_t cpi_vabits; /* fn 0x80000006: %eax */
335 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */
336
337 id_t cpi_coreid; /* same coreid => strands share core */
338 int cpi_pkgcoreid; /* core number within single package */
339 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */
340 /* Intel: fn 4: %eax[31-26] */
341 /*
342 * supported feature information
343 */
344 uint32_t cpi_support[6];
345 #define STD_EDX_FEATURES 0
346 #define AMD_EDX_FEATURES 1
347 #define TM_EDX_FEATURES 2
348 #define STD_ECX_FEATURES 3
349 #define AMD_ECX_FEATURES 4
350 #define STD_EBX_FEATURES 5
351 /*
352 * Synthesized information, where known.
353 */
354 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */
355 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */
356 uint32_t cpi_socket; /* Chip package/socket type */
357
358 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */
359 uint32_t cpi_apicid;
360 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */
361 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */
362 /* Intel: 1 */
363 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */
364 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */
365
366 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */
367 };
368
369
370 static struct cpuid_info cpuid_info0;
371
372 /*
373 * These bit fields are defined by the Intel Application Note AP-485
374 * "Intel Processor Identification and the CPUID Instruction"
375 */
376 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
377 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
378 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
379 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
380 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
381 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
382
383 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx)
384 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx)
385 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx)
386 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx)
387 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx)
388
389 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
390 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
391 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
392 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
393
394 #define CPI_MAXEAX_MAX 0x100 /* sanity control */
395 #define CPI_XMAXEAX_MAX 0x80000100
396 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */
397 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */
398
399 /*
400 * Function 4 (Deterministic Cache Parameters) macros
401 * Defined by Intel Application Note AP-485
402 */
403 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26)
404 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14)
405 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9)
406 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8)
407 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5)
408 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0)
409 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8)
410
411 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22)
412 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12)
413 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0)
414
415 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0)
416
417 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0)
418
419
420 /*
421 * A couple of shorthand macros to identify "later" P6-family chips
422 * like the Pentium M and Core. First, the "older" P6-based stuff
423 * (loosely defined as "pre-Pentium-4"):
424 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
425 */
426
427 #define IS_LEGACY_P6(cpi) ( \
428 cpi->cpi_family == 6 && \
429 (cpi->cpi_model == 1 || \
430 cpi->cpi_model == 3 || \
431 cpi->cpi_model == 5 || \
432 cpi->cpi_model == 6 || \
433 cpi->cpi_model == 7 || \
434 cpi->cpi_model == 8 || \
435 cpi->cpi_model == 0xA || \
436 cpi->cpi_model == 0xB) \
437 )
438
439 /* A "new F6" is everything with family 6 that's not the above */
440 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
441
442 /* Extended family/model support */
443 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \
444 cpi->cpi_family >= 0xf)
445
446 /*
447 * Info for monitor/mwait idle loop.
448 *
449 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's
450 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November
451 * 2006.
452 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual
453 * Documentation Updates" #33633, Rev 2.05, December 2006.
454 */
455 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */
456 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */
457 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */
458 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON)
459 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2)
460 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1)
461 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0)
462 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0)
463 /*
464 * Number of sub-cstates for a given c-state.
465 */
466 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \
467 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state)
468
469 /*
470 * XSAVE leaf 0xD enumeration
471 */
472 #define CPUID_LEAFD_2_YMM_OFFSET 576
473 #define CPUID_LEAFD_2_YMM_SIZE 256
474
475 /*
476 * Functions we consune from cpuid_subr.c; don't publish these in a header
477 * file to try and keep people using the expected cpuid_* interfaces.
478 */
479 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t);
480 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t);
481 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t);
482 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t);
483 extern uint_t _cpuid_vendorstr_to_vendorcode(char *);
484
485 /*
486 * Apply up various platform-dependent restrictions where the
487 * underlying platform restrictions mean the CPU can be marked
488 * as less capable than its cpuid instruction would imply.
489 */
490 #if defined(__xpv)
491 static void
492 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
493 {
494 switch (eax) {
495 case 1: {
496 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ?
497 0 : CPUID_INTC_EDX_MCA;
498 cp->cp_edx &=
499 ~(mcamask |
500 CPUID_INTC_EDX_PSE |
501 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
502 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR |
503 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT |
504 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
505 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT);
506 break;
507 }
508
509 case 0x80000001:
510 cp->cp_edx &=
511 ~(CPUID_AMD_EDX_PSE |
512 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE |
513 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE |
514 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 |
515 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP |
516 CPUID_AMD_EDX_TSCP);
517 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY;
518 break;
519 default:
520 break;
521 }
522
523 switch (vendor) {
524 case X86_VENDOR_Intel:
525 switch (eax) {
526 case 4:
527 /*
528 * Zero out the (ncores-per-chip - 1) field
529 */
530 cp->cp_eax &= 0x03fffffff;
531 break;
532 default:
533 break;
534 }
535 break;
536 case X86_VENDOR_AMD:
537 switch (eax) {
538
539 case 0x80000001:
540 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D;
541 break;
542
543 case 0x80000008:
544 /*
545 * Zero out the (ncores-per-chip - 1) field
546 */
547 cp->cp_ecx &= 0xffffff00;
548 break;
549 default:
550 break;
551 }
552 break;
553 default:
554 break;
555 }
556 }
557 #else
558 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */
559 #endif
560
561 /*
562 * Some undocumented ways of patching the results of the cpuid
563 * instruction to permit running Solaris 10 on future cpus that
564 * we don't currently support. Could be set to non-zero values
565 * via settings in eeprom.
566 */
567
568 uint32_t cpuid_feature_ecx_include;
569 uint32_t cpuid_feature_ecx_exclude;
570 uint32_t cpuid_feature_edx_include;
571 uint32_t cpuid_feature_edx_exclude;
572
573 /*
574 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs.
575 */
576 void
577 cpuid_alloc_space(cpu_t *cpu)
578 {
579 /*
580 * By convention, cpu0 is the boot cpu, which is set up
581 * before memory allocation is available. All other cpus get
582 * their cpuid_info struct allocated here.
583 */
584 ASSERT(cpu->cpu_id != 0);
585 ASSERT(cpu->cpu_m.mcpu_cpi == NULL);
586 cpu->cpu_m.mcpu_cpi =
587 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
588 }
589
590 void
591 cpuid_free_space(cpu_t *cpu)
592 {
593 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
594 int i;
595
596 ASSERT(cpi != NULL);
597 ASSERT(cpi != &cpuid_info0);
598
599 /*
600 * Free up any function 4 related dynamic storage
601 */
602 for (i = 1; i < cpi->cpi_std_4_size; i++)
603 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs));
604 if (cpi->cpi_std_4_size > 0)
605 kmem_free(cpi->cpi_std_4,
606 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *));
607
608 kmem_free(cpi, sizeof (*cpi));
609 cpu->cpu_m.mcpu_cpi = NULL;
610 }
611
612 #if !defined(__xpv)
613 /*
614 * Determine the type of the underlying platform. This is used to customize
615 * initialization of various subsystems (e.g. TSC). determine_platform() must
616 * only ever be called once to prevent two processors from seeing different
617 * values of platform_type. Must be called before cpuid_pass1(), the earliest
618 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv).
619 */
620 void
621 determine_platform(void)
622 {
623 struct cpuid_regs cp;
624 uint32_t base;
625 uint32_t regs[4];
626 char *hvstr = (char *)regs;
627
628 ASSERT(platform_type == -1);
629
630 platform_type = HW_NATIVE;
631
632 if (!enable_platform_detection)
633 return;
634
635 /*
636 * If Hypervisor CPUID bit is set, try to determine hypervisor
637 * vendor signature, and set platform type accordingly.
638 *
639 * References:
640 * http://lkml.org/lkml/2008/10/1/246
641 * http://kb.vmware.com/kb/1009458
642 */
643 cp.cp_eax = 0x1;
644 (void) __cpuid_insn(&cp);
645 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) {
646 cp.cp_eax = 0x40000000;
647 (void) __cpuid_insn(&cp);
648 regs[0] = cp.cp_ebx;
649 regs[1] = cp.cp_ecx;
650 regs[2] = cp.cp_edx;
651 regs[3] = 0;
652 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) {
653 platform_type = HW_XEN_HVM;
654 return;
655 }
656 if (strcmp(hvstr, HVSIG_VMWARE) == 0) {
657 platform_type = HW_VMWARE;
658 return;
659 }
660 if (strcmp(hvstr, HVSIG_KVM) == 0) {
661 platform_type = HW_KVM;
662 return;
663 }
664 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0)
665 platform_type = HW_MICROSOFT;
666 } else {
667 /*
668 * Check older VMware hardware versions. VMware hypervisor is
669 * detected by performing an IN operation to VMware hypervisor
670 * port and checking that value returned in %ebx is VMware
671 * hypervisor magic value.
672 *
673 * References: http://kb.vmware.com/kb/1009458
674 */
675 vmware_port(VMWARE_HVCMD_GETVERSION, regs);
676 if (regs[1] == VMWARE_HVMAGIC) {
677 platform_type = HW_VMWARE;
678 return;
679 }
680 }
681
682 /*
683 * Check Xen hypervisor. In a fully virtualized domain,
684 * Xen's pseudo-cpuid function returns a string representing the
685 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum
686 * supported cpuid function. We need at least a (base + 2) leaf value
687 * to do what we want to do. Try different base values, since the
688 * hypervisor might use a different one depending on whether Hyper-V
689 * emulation is switched on by default or not.
690 */
691 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
692 cp.cp_eax = base;
693 (void) __cpuid_insn(&cp);
694 regs[0] = cp.cp_ebx;
695 regs[1] = cp.cp_ecx;
696 regs[2] = cp.cp_edx;
697 regs[3] = 0;
698 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 &&
699 cp.cp_eax >= (base + 2)) {
700 platform_type &= ~HW_NATIVE;
701 platform_type |= HW_XEN_HVM;
702 return;
703 }
704 }
705 }
706
707 int
708 get_hwenv(void)
709 {
710 ASSERT(platform_type != -1);
711 return (platform_type);
712 }
713
714 int
715 is_controldom(void)
716 {
717 return (0);
718 }
719
720 #else
721
722 int
723 get_hwenv(void)
724 {
725 return (HW_XEN_PV);
726 }
727
728 int
729 is_controldom(void)
730 {
731 return (DOMAIN_IS_INITDOMAIN(xen_info));
732 }
733
734 #endif /* __xpv */
735
736 static void
737 cpuid_intel_getids(cpu_t *cpu, void *feature)
738 {
739 uint_t i;
740 uint_t chipid_shift = 0;
741 uint_t coreid_shift = 0;
742 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
743
744 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
745 chipid_shift++;
746
747 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift;
748 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1);
749
750 if (is_x86_feature(feature, X86FSET_CMP)) {
751 /*
752 * Multi-core (and possibly multi-threaded)
753 * processors.
754 */
755 uint_t ncpu_per_core;
756 if (cpi->cpi_ncore_per_chip == 1)
757 ncpu_per_core = cpi->cpi_ncpu_per_chip;
758 else if (cpi->cpi_ncore_per_chip > 1)
759 ncpu_per_core = cpi->cpi_ncpu_per_chip /
760 cpi->cpi_ncore_per_chip;
761 /*
762 * 8bit APIC IDs on dual core Pentiums
763 * look like this:
764 *
765 * +-----------------------+------+------+
766 * | Physical Package ID | MC | HT |
767 * +-----------------------+------+------+
768 * <------- chipid -------->
769 * <------- coreid --------------->
770 * <--- clogid -->
771 * <------>
772 * pkgcoreid
773 *
774 * Where the number of bits necessary to
775 * represent MC and HT fields together equals
776 * to the minimum number of bits necessary to
777 * store the value of cpi->cpi_ncpu_per_chip.
778 * Of those bits, the MC part uses the number
779 * of bits necessary to store the value of
780 * cpi->cpi_ncore_per_chip.
781 */
782 for (i = 1; i < ncpu_per_core; i <<= 1)
783 coreid_shift++;
784 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift;
785 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
786 } else if (is_x86_feature(feature, X86FSET_HTT)) {
787 /*
788 * Single-core multi-threaded processors.
789 */
790 cpi->cpi_coreid = cpi->cpi_chipid;
791 cpi->cpi_pkgcoreid = 0;
792 }
793 cpi->cpi_procnodeid = cpi->cpi_chipid;
794 cpi->cpi_compunitid = cpi->cpi_coreid;
795 }
796
797 static void
798 cpuid_amd_getids(cpu_t *cpu)
799 {
800 int i, first_half, coreidsz;
801 uint32_t nb_caps_reg;
802 uint_t node2_1;
803 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
804 struct cpuid_regs *cp;
805
806 /*
807 * AMD CMP chips currently have a single thread per core.
808 *
809 * Since no two cpus share a core we must assign a distinct coreid
810 * per cpu, and we do this by using the cpu_id. This scheme does not,
811 * however, guarantee that sibling cores of a chip will have sequential
812 * coreids starting at a multiple of the number of cores per chip -
813 * that is usually the case, but if the ACPI MADT table is presented
814 * in a different order then we need to perform a few more gymnastics
815 * for the pkgcoreid.
816 *
817 * All processors in the system have the same number of enabled
818 * cores. Cores within a processor are always numbered sequentially
819 * from 0 regardless of how many or which are disabled, and there
820 * is no way for operating system to discover the real core id when some
821 * are disabled.
822 *
823 * In family 0x15, the cores come in pairs called compute units. They
824 * share I$ and L2 caches and the FPU. Enumeration of this feature is
825 * simplified by the new topology extensions CPUID leaf, indicated by
826 * the X86 feature X86FSET_TOPOEXT.
827 */
828
829 cpi->cpi_coreid = cpu->cpu_id;
830 cpi->cpi_compunitid = cpu->cpu_id;
831
832 if (cpi->cpi_xmaxeax >= 0x80000008) {
833
834 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12);
835
836 /*
837 * In AMD parlance chip is really a node while Solaris
838 * sees chip as equivalent to socket/package.
839 */
840 cpi->cpi_ncore_per_chip =
841 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
842 if (coreidsz == 0) {
843 /* Use legacy method */
844 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1)
845 coreidsz++;
846 if (coreidsz == 0)
847 coreidsz = 1;
848 }
849 } else {
850 /* Assume single-core part */
851 cpi->cpi_ncore_per_chip = 1;
852 coreidsz = 1;
853 }
854
855 cpi->cpi_clogid = cpi->cpi_pkgcoreid =
856 cpi->cpi_apicid & ((1<<coreidsz) - 1);
857 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip;
858
859 /* Get node ID, compute unit ID */
860 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
861 cpi->cpi_xmaxeax >= 0x8000001e) {
862 cp = &cpi->cpi_extd[0x1e];
863 cp->cp_eax = 0x8000001e;
864 (void) __cpuid_insn(cp);
865
866 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1;
867 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0);
868 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1;
869 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0)
870 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit)
871 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg);
872 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) {
873 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7;
874 } else if (cpi->cpi_family == 0x10) {
875 /*
876 * See if we are a multi-node processor.
877 * All processors in the system have the same number of nodes
878 */
879 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8);
880 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) {
881 /* Single-node */
882 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5,
883 coreidsz);
884 } else {
885
886 /*
887 * Multi-node revision D (2 nodes per package
888 * are supported)
889 */
890 cpi->cpi_procnodes_per_pkg = 2;
891
892 first_half = (cpi->cpi_pkgcoreid <=
893 (cpi->cpi_ncore_per_chip/2 - 1));
894
895 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) {
896 /* We are BSP */
897 cpi->cpi_procnodeid = (first_half ? 0 : 1);
898 } else {
899
900 /* We are AP */
901 /* NodeId[2:1] bits to use for reading F3xe8 */
902 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1;
903
904 nb_caps_reg =
905 pci_getl_func(0, 24 + node2_1, 3, 0xe8);
906
907 /*
908 * Check IntNodeNum bit (31:30, but bit 31 is
909 * always 0 on dual-node processors)
910 */
911 if (BITX(nb_caps_reg, 30, 30) == 0)
912 cpi->cpi_procnodeid = node2_1 +
913 !first_half;
914 else
915 cpi->cpi_procnodeid = node2_1 +
916 first_half;
917 }
918 }
919 } else {
920 cpi->cpi_procnodeid = 0;
921 }
922
923 cpi->cpi_chipid =
924 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg;
925 }
926
927 /*
928 * Setup XFeature_Enabled_Mask register. Required by xsave feature.
929 */
930 void
931 setup_xfem(void)
932 {
933 uint64_t flags = XFEATURE_LEGACY_FP;
934
935 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
936
937 if (is_x86_feature(x86_featureset, X86FSET_SSE))
938 flags |= XFEATURE_SSE;
939
940 if (is_x86_feature(x86_featureset, X86FSET_AVX))
941 flags |= XFEATURE_AVX;
942
943 set_xcr(XFEATURE_ENABLED_MASK, flags);
944
945 xsave_bv_all = flags;
946 }
947
948 void
949 cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
950 {
951 uint32_t mask_ecx, mask_edx;
952 struct cpuid_info *cpi;
953 struct cpuid_regs *cp;
954 int xcpuid;
955 #if !defined(__xpv)
956 extern int idle_cpu_prefer_mwait;
957 #endif
958
959 /*
960 * Space statically allocated for BSP, ensure pointer is set
961 */
962 if (cpu->cpu_id == 0) {
963 if (cpu->cpu_m.mcpu_cpi == NULL)
964 cpu->cpu_m.mcpu_cpi = &cpuid_info0;
965 }
966
967 add_x86_feature(featureset, X86FSET_CPUID);
968
969 cpi = cpu->cpu_m.mcpu_cpi;
970 ASSERT(cpi != NULL);
971 cp = &cpi->cpi_std[0];
972 cp->cp_eax = 0;
973 cpi->cpi_maxeax = __cpuid_insn(cp);
974 {
975 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
976 *iptr++ = cp->cp_ebx;
977 *iptr++ = cp->cp_edx;
978 *iptr++ = cp->cp_ecx;
979 *(char *)&cpi->cpi_vendorstr[12] = '\0';
980 }
981
982 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr);
983 x86_vendor = cpi->cpi_vendor; /* for compatibility */
984
985 /*
986 * Limit the range in case of weird hardware
987 */
988 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
989 cpi->cpi_maxeax = CPI_MAXEAX_MAX;
990 if (cpi->cpi_maxeax < 1)
991 goto pass1_done;
992
993 cp = &cpi->cpi_std[1];
994 cp->cp_eax = 1;
995 (void) __cpuid_insn(cp);
996
997 /*
998 * Extract identifying constants for easy access.
999 */
1000 cpi->cpi_model = CPI_MODEL(cpi);
1001 cpi->cpi_family = CPI_FAMILY(cpi);
1002
1003 if (cpi->cpi_family == 0xf)
1004 cpi->cpi_family += CPI_FAMILY_XTD(cpi);
1005
1006 /*
1007 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
1008 * Intel, and presumably everyone else, uses model == 0xf, as
1009 * one would expect (max value means possible overflow). Sigh.
1010 */
1011
1012 switch (cpi->cpi_vendor) {
1013 case X86_VENDOR_Intel:
1014 if (IS_EXTENDED_MODEL_INTEL(cpi))
1015 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1016 break;
1017 case X86_VENDOR_AMD:
1018 if (CPI_FAMILY(cpi) == 0xf)
1019 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1020 break;
1021 default:
1022 if (cpi->cpi_model == 0xf)
1023 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
1024 break;
1025 }
1026
1027 cpi->cpi_step = CPI_STEP(cpi);
1028 cpi->cpi_brandid = CPI_BRANDID(cpi);
1029
1030 /*
1031 * *default* assumptions:
1032 * - believe %edx feature word
1033 * - ignore %ecx feature word
1034 * - 32-bit virtual and physical addressing
1035 */
1036 mask_edx = 0xffffffff;
1037 mask_ecx = 0;
1038
1039 cpi->cpi_pabits = cpi->cpi_vabits = 32;
1040
1041 switch (cpi->cpi_vendor) {
1042 case X86_VENDOR_Intel:
1043 if (cpi->cpi_family == 5)
1044 x86_type = X86_TYPE_P5;
1045 else if (IS_LEGACY_P6(cpi)) {
1046 x86_type = X86_TYPE_P6;
1047 pentiumpro_bug4046376 = 1;
1048 /*
1049 * Clear the SEP bit when it was set erroneously
1050 */
1051 if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
1052 cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
1053 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
1054 x86_type = X86_TYPE_P4;
1055 /*
1056 * We don't currently depend on any of the %ecx
1057 * features until Prescott, so we'll only check
1058 * this from P4 onwards. We might want to revisit
1059 * that idea later.
1060 */
1061 mask_ecx = 0xffffffff;
1062 } else if (cpi->cpi_family > 0xf)
1063 mask_ecx = 0xffffffff;
1064 /*
1065 * We don't support MONITOR/MWAIT if leaf 5 is not available
1066 * to obtain the monitor linesize.
1067 */
1068 if (cpi->cpi_maxeax < 5)
1069 mask_ecx &= ~CPUID_INTC_ECX_MON;
1070 break;
1071 case X86_VENDOR_IntelClone:
1072 default:
1073 break;
1074 case X86_VENDOR_AMD:
1075 #if defined(OPTERON_ERRATUM_108)
1076 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
1077 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
1078 cpi->cpi_model = 0xc;
1079 } else
1080 #endif
1081 if (cpi->cpi_family == 5) {
1082 /*
1083 * AMD K5 and K6
1084 *
1085 * These CPUs have an incomplete implementation
1086 * of MCA/MCE which we mask away.
1087 */
1088 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
1089
1090 /*
1091 * Model 0 uses the wrong (APIC) bit
1092 * to indicate PGE. Fix it here.
1093 */
1094 if (cpi->cpi_model == 0) {
1095 if (cp->cp_edx & 0x200) {
1096 cp->cp_edx &= ~0x200;
1097 cp->cp_edx |= CPUID_INTC_EDX_PGE;
1098 }
1099 }
1100
1101 /*
1102 * Early models had problems w/ MMX; disable.
1103 */
1104 if (cpi->cpi_model < 6)
1105 mask_edx &= ~CPUID_INTC_EDX_MMX;
1106 }
1107
1108 /*
1109 * For newer families, SSE3 and CX16, at least, are valid;
1110 * enable all
1111 */
1112 if (cpi->cpi_family >= 0xf)
1113 mask_ecx = 0xffffffff;
1114 /*
1115 * We don't support MONITOR/MWAIT if leaf 5 is not available
1116 * to obtain the monitor linesize.
1117 */
1118 if (cpi->cpi_maxeax < 5)
1119 mask_ecx &= ~CPUID_INTC_ECX_MON;
1120
1121 #if !defined(__xpv)
1122 /*
1123 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD
1124 * processors. AMD does not intend MWAIT to be used in the cpu
1125 * idle loop on current and future processors. 10h and future
1126 * AMD processors use more power in MWAIT than HLT.
1127 * Pre-family-10h Opterons do not have the MWAIT instruction.
1128 */
1129 idle_cpu_prefer_mwait = 0;
1130 #endif
1131
1132 break;
1133 case X86_VENDOR_TM:
1134 /*
1135 * workaround the NT workaround in CMS 4.1
1136 */
1137 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
1138 (cpi->cpi_step == 2 || cpi->cpi_step == 3))
1139 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1140 break;
1141 case X86_VENDOR_Centaur:
1142 /*
1143 * workaround the NT workarounds again
1144 */
1145 if (cpi->cpi_family == 6)
1146 cp->cp_edx |= CPUID_INTC_EDX_CX8;
1147 break;
1148 case X86_VENDOR_Cyrix:
1149 /*
1150 * We rely heavily on the probing in locore
1151 * to actually figure out what parts, if any,
1152 * of the Cyrix cpuid instruction to believe.
1153 */
1154 switch (x86_type) {
1155 case X86_TYPE_CYRIX_486:
1156 mask_edx = 0;
1157 break;
1158 case X86_TYPE_CYRIX_6x86:
1159 mask_edx = 0;
1160 break;
1161 case X86_TYPE_CYRIX_6x86L:
1162 mask_edx =
1163 CPUID_INTC_EDX_DE |
1164 CPUID_INTC_EDX_CX8;
1165 break;
1166 case X86_TYPE_CYRIX_6x86MX:
1167 mask_edx =
1168 CPUID_INTC_EDX_DE |
1169 CPUID_INTC_EDX_MSR |
1170 CPUID_INTC_EDX_CX8 |
1171 CPUID_INTC_EDX_PGE |
1172 CPUID_INTC_EDX_CMOV |
1173 CPUID_INTC_EDX_MMX;
1174 break;
1175 case X86_TYPE_CYRIX_GXm:
1176 mask_edx =
1177 CPUID_INTC_EDX_MSR |
1178 CPUID_INTC_EDX_CX8 |
1179 CPUID_INTC_EDX_CMOV |
1180 CPUID_INTC_EDX_MMX;
1181 break;
1182 case X86_TYPE_CYRIX_MediaGX:
1183 break;
1184 case X86_TYPE_CYRIX_MII:
1185 case X86_TYPE_VIA_CYRIX_III:
1186 mask_edx =
1187 CPUID_INTC_EDX_DE |
1188 CPUID_INTC_EDX_TSC |
1189 CPUID_INTC_EDX_MSR |
1190 CPUID_INTC_EDX_CX8 |
1191 CPUID_INTC_EDX_PGE |
1192 CPUID_INTC_EDX_CMOV |
1193 CPUID_INTC_EDX_MMX;
1194 break;
1195 default:
1196 break;
1197 }
1198 break;
1199 }
1200
1201 #if defined(__xpv)
1202 /*
1203 * Do not support MONITOR/MWAIT under a hypervisor
1204 */
1205 mask_ecx &= ~CPUID_INTC_ECX_MON;
1206 /*
1207 * Do not support XSAVE under a hypervisor for now
1208 */
1209 xsave_force_disable = B_TRUE;
1210
1211 #endif /* __xpv */
1212
1213 if (xsave_force_disable) {
1214 mask_ecx &= ~CPUID_INTC_ECX_XSAVE;
1215 mask_ecx &= ~CPUID_INTC_ECX_AVX;
1216 mask_ecx &= ~CPUID_INTC_ECX_F16C;
1217 mask_ecx &= ~CPUID_INTC_ECX_FMA;
1218 }
1219
1220 /*
1221 * Now we've figured out the masks that determine
1222 * which bits we choose to believe, apply the masks
1223 * to the feature words, then map the kernel's view
1224 * of these feature words into its feature word.
1225 */
1226 cp->cp_edx &= mask_edx;
1227 cp->cp_ecx &= mask_ecx;
1228
1229 /*
1230 * apply any platform restrictions (we don't call this
1231 * immediately after __cpuid_insn here, because we need the
1232 * workarounds applied above first)
1233 */
1234 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
1235
1236 /*
1237 * In addition to ecx and edx, Intel is storing a bunch of instruction
1238 * set extensions in leaf 7's ebx.
1239 */
1240 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) {
1241 struct cpuid_regs *ecp;
1242 ecp = &cpi->cpi_std[7];
1243 ecp->cp_eax = 7;
1244 ecp->cp_ecx = 0;
1245 (void) __cpuid_insn(ecp);
1246 /*
1247 * If XSAVE has been disabled, just ignore all of the AVX
1248 * dependent flags here.
1249 */
1250 if (xsave_force_disable) {
1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
1252 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
1253 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
1254 }
1255
1256 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP)
1257 add_x86_feature(featureset, X86FSET_SMEP);
1258
1259 /*
1260 * We check disable_smap here in addition to in startup_smap()
1261 * to ensure CPUs that aren't the boot CPU don't accidentally
1262 * include it in the feature set and thus generate a mismatched
1263 * x86 feature set across CPUs. Note that at this time we only
1264 * enable SMAP for the 64-bit kernel.
1265 */
1266 #if defined(__amd64)
1267 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMAP &&
1268 disable_smap == 0)
1269 add_x86_feature(featureset, X86FSET_SMAP);
1270 #endif
1271 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED)
1272 add_x86_feature(featureset, X86FSET_RDSEED);
1273
1274 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX)
1275 add_x86_feature(featureset, X86FSET_ADX);
1276 }
1277
1278 /*
1279 * fold in overrides from the "eeprom" mechanism
1280 */
1281 cp->cp_edx |= cpuid_feature_edx_include;
1282 cp->cp_edx &= ~cpuid_feature_edx_exclude;
1283
1284 cp->cp_ecx |= cpuid_feature_ecx_include;
1285 cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
1286
1287 if (cp->cp_edx & CPUID_INTC_EDX_PSE) {
1288 add_x86_feature(featureset, X86FSET_LARGEPAGE);
1289 }
1290 if (cp->cp_edx & CPUID_INTC_EDX_TSC) {
1291 add_x86_feature(featureset, X86FSET_TSC);
1292 }
1293 if (cp->cp_edx & CPUID_INTC_EDX_MSR) {
1294 add_x86_feature(featureset, X86FSET_MSR);
1295 }
1296 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) {
1297 add_x86_feature(featureset, X86FSET_MTRR);
1298 }
1299 if (cp->cp_edx & CPUID_INTC_EDX_PGE) {
1300 add_x86_feature(featureset, X86FSET_PGE);
1301 }
1302 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) {
1303 add_x86_feature(featureset, X86FSET_CMOV);
1304 }
1305 if (cp->cp_edx & CPUID_INTC_EDX_MMX) {
1306 add_x86_feature(featureset, X86FSET_MMX);
1307 }
1308 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
1309 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) {
1310 add_x86_feature(featureset, X86FSET_MCA);
1311 }
1312 if (cp->cp_edx & CPUID_INTC_EDX_PAE) {
1313 add_x86_feature(featureset, X86FSET_PAE);
1314 }
1315 if (cp->cp_edx & CPUID_INTC_EDX_CX8) {
1316 add_x86_feature(featureset, X86FSET_CX8);
1317 }
1318 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) {
1319 add_x86_feature(featureset, X86FSET_CX16);
1320 }
1321 if (cp->cp_edx & CPUID_INTC_EDX_PAT) {
1322 add_x86_feature(featureset, X86FSET_PAT);
1323 }
1324 if (cp->cp_edx & CPUID_INTC_EDX_SEP) {
1325 add_x86_feature(featureset, X86FSET_SEP);
1326 }
1327 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
1328 /*
1329 * In our implementation, fxsave/fxrstor
1330 * are prerequisites before we'll even
1331 * try and do SSE things.
1332 */
1333 if (cp->cp_edx & CPUID_INTC_EDX_SSE) {
1334 add_x86_feature(featureset, X86FSET_SSE);
1335 }
1336 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) {
1337 add_x86_feature(featureset, X86FSET_SSE2);
1338 }
1339 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) {
1340 add_x86_feature(featureset, X86FSET_SSE3);
1341 }
1342 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) {
1343 add_x86_feature(featureset, X86FSET_SSSE3);
1344 }
1345 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) {
1346 add_x86_feature(featureset, X86FSET_SSE4_1);
1347 }
1348 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) {
1349 add_x86_feature(featureset, X86FSET_SSE4_2);
1350 }
1351 if (cp->cp_ecx & CPUID_INTC_ECX_AES) {
1352 add_x86_feature(featureset, X86FSET_AES);
1353 }
1354 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) {
1355 add_x86_feature(featureset, X86FSET_PCLMULQDQ);
1356 }
1357
1358 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) {
1359 add_x86_feature(featureset, X86FSET_XSAVE);
1360
1361 /* We only test AVX when there is XSAVE */
1362 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) {
1363 add_x86_feature(featureset,
1364 X86FSET_AVX);
1365
1366 /*
1367 * Intel says we can't check these without also
1368 * checking AVX.
1369 */
1370 if (cp->cp_ecx & CPUID_INTC_ECX_F16C)
1371 add_x86_feature(featureset,
1372 X86FSET_F16C);
1373
1374 if (cp->cp_ecx & CPUID_INTC_ECX_FMA)
1375 add_x86_feature(featureset,
1376 X86FSET_FMA);
1377
1378 if (cpi->cpi_std[7].cp_ebx &
1379 CPUID_INTC_EBX_7_0_BMI1)
1380 add_x86_feature(featureset,
1381 X86FSET_BMI1);
1382
1383 if (cpi->cpi_std[7].cp_ebx &
1384 CPUID_INTC_EBX_7_0_BMI2)
1385 add_x86_feature(featureset,
1386 X86FSET_BMI2);
1387
1388 if (cpi->cpi_std[7].cp_ebx &
1389 CPUID_INTC_EBX_7_0_AVX2)
1390 add_x86_feature(featureset,
1391 X86FSET_AVX2);
1392 }
1393 }
1394 }
1395 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) {
1396 add_x86_feature(featureset, X86FSET_X2APIC);
1397 }
1398 if (cp->cp_edx & CPUID_INTC_EDX_DE) {
1399 add_x86_feature(featureset, X86FSET_DE);
1400 }
1401 #if !defined(__xpv)
1402 if (cp->cp_ecx & CPUID_INTC_ECX_MON) {
1403
1404 /*
1405 * We require the CLFLUSH instruction for erratum workaround
1406 * to use MONITOR/MWAIT.
1407 */
1408 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1409 cpi->cpi_mwait.support |= MWAIT_SUPPORT;
1410 add_x86_feature(featureset, X86FSET_MWAIT);
1411 } else {
1412 extern int idle_cpu_assert_cflush_monitor;
1413
1414 /*
1415 * All processors we are aware of which have
1416 * MONITOR/MWAIT also have CLFLUSH.
1417 */
1418 if (idle_cpu_assert_cflush_monitor) {
1419 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) &&
1420 (cp->cp_edx & CPUID_INTC_EDX_CLFSH));
1421 }
1422 }
1423 }
1424 #endif /* __xpv */
1425
1426 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) {
1427 add_x86_feature(featureset, X86FSET_VMX);
1428 }
1429
1430 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND)
1431 add_x86_feature(featureset, X86FSET_RDRAND);
1432
1433 /*
1434 * Only need it first time, rest of the cpus would follow suit.
1435 * we only capture this for the bootcpu.
1436 */
1437 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) {
1438 add_x86_feature(featureset, X86FSET_CLFSH);
1439 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8);
1440 }
1441 if (is_x86_feature(featureset, X86FSET_PAE))
1442 cpi->cpi_pabits = 36;
1443
1444 /*
1445 * Hyperthreading configuration is slightly tricky on Intel
1446 * and pure clones, and even trickier on AMD.
1447 *
1448 * (AMD chose to set the HTT bit on their CMP processors,
1449 * even though they're not actually hyperthreaded. Thus it
1450 * takes a bit more work to figure out what's really going
1451 * on ... see the handling of the CMP_LGCY bit below)
1452 */
1453 if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
1454 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
1455 if (cpi->cpi_ncpu_per_chip > 1)
1456 add_x86_feature(featureset, X86FSET_HTT);
1457 } else {
1458 cpi->cpi_ncpu_per_chip = 1;
1459 }
1460
1461 /*
1462 * Work on the "extended" feature information, doing
1463 * some basic initialization for cpuid_pass2()
1464 */
1465 xcpuid = 0;
1466 switch (cpi->cpi_vendor) {
1467 case X86_VENDOR_Intel:
1468 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
1469 xcpuid++;
1470 break;
1471 case X86_VENDOR_AMD:
1472 if (cpi->cpi_family > 5 ||
1473 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
1474 xcpuid++;
1475 break;
1476 case X86_VENDOR_Cyrix:
1477 /*
1478 * Only these Cyrix CPUs are -known- to support
1479 * extended cpuid operations.
1480 */
1481 if (x86_type == X86_TYPE_VIA_CYRIX_III ||
1482 x86_type == X86_TYPE_CYRIX_GXm)
1483 xcpuid++;
1484 break;
1485 case X86_VENDOR_Centaur:
1486 case X86_VENDOR_TM:
1487 default:
1488 xcpuid++;
1489 break;
1490 }
1491
1492 if (xcpuid) {
1493 cp = &cpi->cpi_extd[0];
1494 cp->cp_eax = 0x80000000;
1495 cpi->cpi_xmaxeax = __cpuid_insn(cp);
1496 }
1497
1498 if (cpi->cpi_xmaxeax & 0x80000000) {
1499
1500 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
1501 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
1502
1503 switch (cpi->cpi_vendor) {
1504 case X86_VENDOR_Intel:
1505 case X86_VENDOR_AMD:
1506 if (cpi->cpi_xmaxeax < 0x80000001)
1507 break;
1508 cp = &cpi->cpi_extd[1];
1509 cp->cp_eax = 0x80000001;
1510 (void) __cpuid_insn(cp);
1511
1512 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1513 cpi->cpi_family == 5 &&
1514 cpi->cpi_model == 6 &&
1515 cpi->cpi_step == 6) {
1516 /*
1517 * K6 model 6 uses bit 10 to indicate SYSC
1518 * Later models use bit 11. Fix it here.
1519 */
1520 if (cp->cp_edx & 0x400) {
1521 cp->cp_edx &= ~0x400;
1522 cp->cp_edx |= CPUID_AMD_EDX_SYSC;
1523 }
1524 }
1525
1526 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
1527
1528 /*
1529 * Compute the additions to the kernel's feature word.
1530 */
1531 if (cp->cp_edx & CPUID_AMD_EDX_NX) {
1532 add_x86_feature(featureset, X86FSET_NX);
1533 }
1534
1535 /*
1536 * Regardless whether or not we boot 64-bit,
1537 * we should have a way to identify whether
1538 * the CPU is capable of running 64-bit.
1539 */
1540 if (cp->cp_edx & CPUID_AMD_EDX_LM) {
1541 add_x86_feature(featureset, X86FSET_64);
1542 }
1543
1544 #if defined(__amd64)
1545 /* 1 GB large page - enable only for 64 bit kernel */
1546 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) {
1547 add_x86_feature(featureset, X86FSET_1GPG);
1548 }
1549 #endif
1550
1551 if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
1552 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
1553 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
1554 add_x86_feature(featureset, X86FSET_SSE4A);
1555 }
1556
1557 /*
1558 * If both the HTT and CMP_LGCY bits are set,
1559 * then we're not actually HyperThreaded. Read
1560 * "AMD CPUID Specification" for more details.
1561 */
1562 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1563 is_x86_feature(featureset, X86FSET_HTT) &&
1564 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
1565 remove_x86_feature(featureset, X86FSET_HTT);
1566 add_x86_feature(featureset, X86FSET_CMP);
1567 }
1568 #if defined(__amd64)
1569 /*
1570 * It's really tricky to support syscall/sysret in
1571 * the i386 kernel; we rely on sysenter/sysexit
1572 * instead. In the amd64 kernel, things are -way-
1573 * better.
1574 */
1575 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) {
1576 add_x86_feature(featureset, X86FSET_ASYSC);
1577 }
1578
1579 /*
1580 * While we're thinking about system calls, note
1581 * that AMD processors don't support sysenter
1582 * in long mode at all, so don't try to program them.
1583 */
1584 if (x86_vendor == X86_VENDOR_AMD) {
1585 remove_x86_feature(featureset, X86FSET_SEP);
1586 }
1587 #endif
1588 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) {
1589 add_x86_feature(featureset, X86FSET_TSCP);
1590 }
1591
1592 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) {
1593 add_x86_feature(featureset, X86FSET_SVM);
1594 }
1595
1596 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) {
1597 add_x86_feature(featureset, X86FSET_TOPOEXT);
1598 }
1599 break;
1600 default:
1601 break;
1602 }
1603
1604 /*
1605 * Get CPUID data about processor cores and hyperthreads.
1606 */
1607 switch (cpi->cpi_vendor) {
1608 case X86_VENDOR_Intel:
1609 if (cpi->cpi_maxeax >= 4) {
1610 cp = &cpi->cpi_std[4];
1611 cp->cp_eax = 4;
1612 cp->cp_ecx = 0;
1613 (void) __cpuid_insn(cp);
1614 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
1615 }
1616 /*FALLTHROUGH*/
1617 case X86_VENDOR_AMD:
1618 if (cpi->cpi_xmaxeax < 0x80000008)
1619 break;
1620 cp = &cpi->cpi_extd[8];
1621 cp->cp_eax = 0x80000008;
1622 (void) __cpuid_insn(cp);
1623 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
1624
1625 /*
1626 * Virtual and physical address limits from
1627 * cpuid override previously guessed values.
1628 */
1629 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
1630 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
1631 break;
1632 default:
1633 break;
1634 }
1635
1636 /*
1637 * Derive the number of cores per chip
1638 */
1639 switch (cpi->cpi_vendor) {
1640 case X86_VENDOR_Intel:
1641 if (cpi->cpi_maxeax < 4) {
1642 cpi->cpi_ncore_per_chip = 1;
1643 break;
1644 } else {
1645 cpi->cpi_ncore_per_chip =
1646 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
1647 }
1648 break;
1649 case X86_VENDOR_AMD:
1650 if (cpi->cpi_xmaxeax < 0x80000008) {
1651 cpi->cpi_ncore_per_chip = 1;
1652 break;
1653 } else {
1654 /*
1655 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is
1656 * 1 less than the number of physical cores on
1657 * the chip. In family 0x10 this value can
1658 * be affected by "downcoring" - it reflects
1659 * 1 less than the number of cores actually
1660 * enabled on this node.
1661 */
1662 cpi->cpi_ncore_per_chip =
1663 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
1664 }
1665 break;
1666 default:
1667 cpi->cpi_ncore_per_chip = 1;
1668 break;
1669 }
1670
1671 /*
1672 * Get CPUID data about TSC Invariance in Deep C-State.
1673 */
1674 switch (cpi->cpi_vendor) {
1675 case X86_VENDOR_Intel:
1676 if (cpi->cpi_maxeax >= 7) {
1677 cp = &cpi->cpi_extd[7];
1678 cp->cp_eax = 0x80000007;
1679 cp->cp_ecx = 0;
1680 (void) __cpuid_insn(cp);
1681 }
1682 break;
1683 default:
1684 break;
1685 }
1686 } else {
1687 cpi->cpi_ncore_per_chip = 1;
1688 }
1689
1690 /*
1691 * If more than one core, then this processor is CMP.
1692 */
1693 if (cpi->cpi_ncore_per_chip > 1) {
1694 add_x86_feature(featureset, X86FSET_CMP);
1695 }
1696
1697 /*
1698 * If the number of cores is the same as the number
1699 * of CPUs, then we cannot have HyperThreading.
1700 */
1701 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) {
1702 remove_x86_feature(featureset, X86FSET_HTT);
1703 }
1704
1705 cpi->cpi_apicid = CPI_APIC_ID(cpi);
1706 cpi->cpi_procnodes_per_pkg = 1;
1707 cpi->cpi_cores_per_compunit = 1;
1708 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE &&
1709 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) {
1710 /*
1711 * Single-core single-threaded processors.
1712 */
1713 cpi->cpi_chipid = -1;
1714 cpi->cpi_clogid = 0;
1715 cpi->cpi_coreid = cpu->cpu_id;
1716 cpi->cpi_pkgcoreid = 0;
1717 if (cpi->cpi_vendor == X86_VENDOR_AMD)
1718 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
1719 else
1720 cpi->cpi_procnodeid = cpi->cpi_chipid;
1721 } else if (cpi->cpi_ncpu_per_chip > 1) {
1722 if (cpi->cpi_vendor == X86_VENDOR_Intel)
1723 cpuid_intel_getids(cpu, featureset);
1724 else if (cpi->cpi_vendor == X86_VENDOR_AMD)
1725 cpuid_amd_getids(cpu);
1726 else {
1727 /*
1728 * All other processors are currently
1729 * assumed to have single cores.
1730 */
1731 cpi->cpi_coreid = cpi->cpi_chipid;
1732 cpi->cpi_pkgcoreid = 0;
1733 cpi->cpi_procnodeid = cpi->cpi_chipid;
1734 cpi->cpi_compunitid = cpi->cpi_chipid;
1735 }
1736 }
1737
1738 /*
1739 * Synthesize chip "revision" and socket type
1740 */
1741 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family,
1742 cpi->cpi_model, cpi->cpi_step);
1743 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor,
1744 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step);
1745 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
1746 cpi->cpi_model, cpi->cpi_step);
1747
1748 pass1_done:
1749 cpi->cpi_pass = 1;
1750 }
1751
1752 /*
1753 * Make copies of the cpuid table entries we depend on, in
1754 * part for ease of parsing now, in part so that we have only
1755 * one place to correct any of it, in part for ease of
1756 * later export to userland, and in part so we can look at
1757 * this stuff in a crash dump.
1758 */
1759
1760 /*ARGSUSED*/
1761 void
1762 cpuid_pass2(cpu_t *cpu)
1763 {
1764 uint_t n, nmax;
1765 int i;
1766 struct cpuid_regs *cp;
1767 uint8_t *dp;
1768 uint32_t *iptr;
1769 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1770
1771 ASSERT(cpi->cpi_pass == 1);
1772
1773 if (cpi->cpi_maxeax < 1)
1774 goto pass2_done;
1775
1776 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1777 nmax = NMAX_CPI_STD;
1778 /*
1779 * (We already handled n == 0 and n == 1 in pass 1)
1780 */
1781 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1782 cp->cp_eax = n;
1783
1784 /*
1785 * CPUID function 4 expects %ecx to be initialized
1786 * with an index which indicates which cache to return
1787 * information about. The OS is expected to call function 4
1788 * with %ecx set to 0, 1, 2, ... until it returns with
1789 * EAX[4:0] set to 0, which indicates there are no more
1790 * caches.
1791 *
1792 * Here, populate cpi_std[4] with the information returned by
1793 * function 4 when %ecx == 0, and do the rest in cpuid_pass3()
1794 * when dynamic memory allocation becomes available.
1795 *
1796 * Note: we need to explicitly initialize %ecx here, since
1797 * function 4 may have been previously invoked.
1798 */
1799 if (n == 4)
1800 cp->cp_ecx = 0;
1801
1802 (void) __cpuid_insn(cp);
1803 platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1804 switch (n) {
1805 case 2:
1806 /*
1807 * "the lower 8 bits of the %eax register
1808 * contain a value that identifies the number
1809 * of times the cpuid [instruction] has to be
1810 * executed to obtain a complete image of the
1811 * processor's caching systems."
1812 *
1813 * How *do* they make this stuff up?
1814 */
1815 cpi->cpi_ncache = sizeof (*cp) *
1816 BITX(cp->cp_eax, 7, 0);
1817 if (cpi->cpi_ncache == 0)
1818 break;
1819 cpi->cpi_ncache--; /* skip count byte */
1820
1821 /*
1822 * Well, for now, rather than attempt to implement
1823 * this slightly dubious algorithm, we just look
1824 * at the first 15 ..
1825 */
1826 if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1827 cpi->cpi_ncache = sizeof (*cp) - 1;
1828
1829 dp = cpi->cpi_cacheinfo;
1830 if (BITX(cp->cp_eax, 31, 31) == 0) {
1831 uint8_t *p = (void *)&cp->cp_eax;
1832 for (i = 1; i < 4; i++)
1833 if (p[i] != 0)
1834 *dp++ = p[i];
1835 }
1836 if (BITX(cp->cp_ebx, 31, 31) == 0) {
1837 uint8_t *p = (void *)&cp->cp_ebx;
1838 for (i = 0; i < 4; i++)
1839 if (p[i] != 0)
1840 *dp++ = p[i];
1841 }
1842 if (BITX(cp->cp_ecx, 31, 31) == 0) {
1843 uint8_t *p = (void *)&cp->cp_ecx;
1844 for (i = 0; i < 4; i++)
1845 if (p[i] != 0)
1846 *dp++ = p[i];
1847 }
1848 if (BITX(cp->cp_edx, 31, 31) == 0) {
1849 uint8_t *p = (void *)&cp->cp_edx;
1850 for (i = 0; i < 4; i++)
1851 if (p[i] != 0)
1852 *dp++ = p[i];
1853 }
1854 break;
1855
1856 case 3: /* Processor serial number, if PSN supported */
1857 break;
1858
1859 case 4: /* Deterministic cache parameters */
1860 break;
1861
1862 case 5: /* Monitor/Mwait parameters */
1863 {
1864 size_t mwait_size;
1865
1866 /*
1867 * check cpi_mwait.support which was set in cpuid_pass1
1868 */
1869 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT))
1870 break;
1871
1872 /*
1873 * Protect ourself from insane mwait line size.
1874 * Workaround for incomplete hardware emulator(s).
1875 */
1876 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi);
1877 if (mwait_size < sizeof (uint32_t) ||
1878 !ISP2(mwait_size)) {
1879 #if DEBUG
1880 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait "
1881 "size %ld", cpu->cpu_id, (long)mwait_size);
1882 #endif
1883 break;
1884 }
1885
1886 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi);
1887 cpi->cpi_mwait.mon_max = mwait_size;
1888 if (MWAIT_EXTENSION(cpi)) {
1889 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS;
1890 if (MWAIT_INT_ENABLE(cpi))
1891 cpi->cpi_mwait.support |=
1892 MWAIT_ECX_INT_ENABLE;
1893 }
1894 break;
1895 }
1896 default:
1897 break;
1898 }
1899 }
1900
1901 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) {
1902 struct cpuid_regs regs;
1903
1904 cp = ®s;
1905 cp->cp_eax = 0xB;
1906 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1907
1908 (void) __cpuid_insn(cp);
1909
1910 /*
1911 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
1912 * indicates that the extended topology enumeration leaf is
1913 * available.
1914 */
1915 if (cp->cp_ebx) {
1916 uint32_t x2apic_id;
1917 uint_t coreid_shift = 0;
1918 uint_t ncpu_per_core = 1;
1919 uint_t chipid_shift = 0;
1920 uint_t ncpu_per_chip = 1;
1921 uint_t i;
1922 uint_t level;
1923
1924 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
1925 cp->cp_eax = 0xB;
1926 cp->cp_ecx = i;
1927
1928 (void) __cpuid_insn(cp);
1929 level = CPI_CPU_LEVEL_TYPE(cp);
1930
1931 if (level == 1) {
1932 x2apic_id = cp->cp_edx;
1933 coreid_shift = BITX(cp->cp_eax, 4, 0);
1934 ncpu_per_core = BITX(cp->cp_ebx, 15, 0);
1935 } else if (level == 2) {
1936 x2apic_id = cp->cp_edx;
1937 chipid_shift = BITX(cp->cp_eax, 4, 0);
1938 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0);
1939 }
1940 }
1941
1942 cpi->cpi_apicid = x2apic_id;
1943 cpi->cpi_ncpu_per_chip = ncpu_per_chip;
1944 cpi->cpi_ncore_per_chip = ncpu_per_chip /
1945 ncpu_per_core;
1946 cpi->cpi_chipid = x2apic_id >> chipid_shift;
1947 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1);
1948 cpi->cpi_coreid = x2apic_id >> coreid_shift;
1949 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift;
1950 }
1951
1952 /* Make cp NULL so that we don't stumble on others */
1953 cp = NULL;
1954 }
1955
1956 /*
1957 * XSAVE enumeration
1958 */
1959 if (cpi->cpi_maxeax >= 0xD) {
1960 struct cpuid_regs regs;
1961 boolean_t cpuid_d_valid = B_TRUE;
1962
1963 cp = ®s;
1964 cp->cp_eax = 0xD;
1965 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
1966
1967 (void) __cpuid_insn(cp);
1968
1969 /*
1970 * Sanity checks for debug
1971 */
1972 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 ||
1973 (cp->cp_eax & XFEATURE_SSE) == 0) {
1974 cpuid_d_valid = B_FALSE;
1975 }
1976
1977 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax;
1978 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx;
1979 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx;
1980
1981 /*
1982 * If the hw supports AVX, get the size and offset in the save
1983 * area for the ymm state.
1984 */
1985 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) {
1986 cp->cp_eax = 0xD;
1987 cp->cp_ecx = 2;
1988 cp->cp_edx = cp->cp_ebx = 0;
1989
1990 (void) __cpuid_insn(cp);
1991
1992 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET ||
1993 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) {
1994 cpuid_d_valid = B_FALSE;
1995 }
1996
1997 cpi->cpi_xsave.ymm_size = cp->cp_eax;
1998 cpi->cpi_xsave.ymm_offset = cp->cp_ebx;
1999 }
2000
2001 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) {
2002 xsave_state_size = 0;
2003 } else if (cpuid_d_valid) {
2004 xsave_state_size = cpi->cpi_xsave.xsav_max_size;
2005 } else {
2006 /* Broken CPUID 0xD, probably in HVM */
2007 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid "
2008 "value: hw_low = %d, hw_high = %d, xsave_size = %d"
2009 ", ymm_size = %d, ymm_offset = %d\n",
2010 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low,
2011 cpi->cpi_xsave.xsav_hw_features_high,
2012 (int)cpi->cpi_xsave.xsav_max_size,
2013 (int)cpi->cpi_xsave.ymm_size,
2014 (int)cpi->cpi_xsave.ymm_offset);
2015
2016 if (xsave_state_size != 0) {
2017 /*
2018 * This must be a non-boot CPU. We cannot
2019 * continue, because boot cpu has already
2020 * enabled XSAVE.
2021 */
2022 ASSERT(cpu->cpu_id != 0);
2023 cmn_err(CE_PANIC, "cpu%d: we have already "
2024 "enabled XSAVE on boot cpu, cannot "
2025 "continue.", cpu->cpu_id);
2026 } else {
2027 /*
2028 * If we reached here on the boot CPU, it's also
2029 * almost certain that we'll reach here on the
2030 * non-boot CPUs. When we're here on a boot CPU
2031 * we should disable the feature, on a non-boot
2032 * CPU we need to confirm that we have.
2033 */
2034 if (cpu->cpu_id == 0) {
2035 remove_x86_feature(x86_featureset,
2036 X86FSET_XSAVE);
2037 remove_x86_feature(x86_featureset,
2038 X86FSET_AVX);
2039 remove_x86_feature(x86_featureset,
2040 X86FSET_F16C);
2041 remove_x86_feature(x86_featureset,
2042 X86FSET_BMI1);
2043 remove_x86_feature(x86_featureset,
2044 X86FSET_BMI2);
2045 remove_x86_feature(x86_featureset,
2046 X86FSET_FMA);
2047 remove_x86_feature(x86_featureset,
2048 X86FSET_AVX2);
2049 CPI_FEATURES_ECX(cpi) &=
2050 ~CPUID_INTC_ECX_XSAVE;
2051 CPI_FEATURES_ECX(cpi) &=
2052 ~CPUID_INTC_ECX_AVX;
2053 CPI_FEATURES_ECX(cpi) &=
2054 ~CPUID_INTC_ECX_F16C;
2055 CPI_FEATURES_ECX(cpi) &=
2056 ~CPUID_INTC_ECX_FMA;
2057 CPI_FEATURES_7_0_EBX(cpi) &=
2058 ~CPUID_INTC_EBX_7_0_BMI1;
2059 CPI_FEATURES_7_0_EBX(cpi) &=
2060 ~CPUID_INTC_EBX_7_0_BMI2;
2061 CPI_FEATURES_7_0_EBX(cpi) &=
2062 ~CPUID_INTC_EBX_7_0_AVX2;
2063 xsave_force_disable = B_TRUE;
2064 } else {
2065 VERIFY(is_x86_feature(x86_featureset,
2066 X86FSET_XSAVE) == B_FALSE);
2067 }
2068 }
2069 }
2070 }
2071
2072
2073 if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
2074 goto pass2_done;
2075
2076 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
2077 nmax = NMAX_CPI_EXTD;
2078 /*
2079 * Copy the extended properties, fixing them as we go.
2080 * (We already handled n == 0 and n == 1 in pass 1)
2081 */
2082 iptr = (void *)cpi->cpi_brandstr;
2083 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
2084 cp->cp_eax = 0x80000000 + n;
2085 (void) __cpuid_insn(cp);
2086 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
2087 switch (n) {
2088 case 2:
2089 case 3:
2090 case 4:
2091 /*
2092 * Extract the brand string
2093 */
2094 *iptr++ = cp->cp_eax;
2095 *iptr++ = cp->cp_ebx;
2096 *iptr++ = cp->cp_ecx;
2097 *iptr++ = cp->cp_edx;
2098 break;
2099 case 5:
2100 switch (cpi->cpi_vendor) {
2101 case X86_VENDOR_AMD:
2102 /*
2103 * The Athlon and Duron were the first
2104 * parts to report the sizes of the
2105 * TLB for large pages. Before then,
2106 * we don't trust the data.
2107 */
2108 if (cpi->cpi_family < 6 ||
2109 (cpi->cpi_family == 6 &&
2110 cpi->cpi_model < 1))
2111 cp->cp_eax = 0;
2112 break;
2113 default:
2114 break;
2115 }
2116 break;
2117 case 6:
2118 switch (cpi->cpi_vendor) {
2119 case X86_VENDOR_AMD:
2120 /*
2121 * The Athlon and Duron were the first
2122 * AMD parts with L2 TLB's.
2123 * Before then, don't trust the data.
2124 */
2125 if (cpi->cpi_family < 6 ||
2126 cpi->cpi_family == 6 &&
2127 cpi->cpi_model < 1)
2128 cp->cp_eax = cp->cp_ebx = 0;
2129 /*
2130 * AMD Duron rev A0 reports L2
2131 * cache size incorrectly as 1K
2132 * when it is really 64K
2133 */
2134 if (cpi->cpi_family == 6 &&
2135 cpi->cpi_model == 3 &&
2136 cpi->cpi_step == 0) {
2137 cp->cp_ecx &= 0xffff;
2138 cp->cp_ecx |= 0x400000;
2139 }
2140 break;
2141 case X86_VENDOR_Cyrix: /* VIA C3 */
2142 /*
2143 * VIA C3 processors are a bit messed
2144 * up w.r.t. encoding cache sizes in %ecx
2145 */
2146 if (cpi->cpi_family != 6)
2147 break;
2148 /*
2149 * model 7 and 8 were incorrectly encoded
2150 *
2151 * xxx is model 8 really broken?
2152 */
2153 if (cpi->cpi_model == 7 ||
2154 cpi->cpi_model == 8)
2155 cp->cp_ecx =
2156 BITX(cp->cp_ecx, 31, 24) << 16 |
2157 BITX(cp->cp_ecx, 23, 16) << 12 |
2158 BITX(cp->cp_ecx, 15, 8) << 8 |
2159 BITX(cp->cp_ecx, 7, 0);
2160 /*
2161 * model 9 stepping 1 has wrong associativity
2162 */
2163 if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
2164 cp->cp_ecx |= 8 << 12;
2165 break;
2166 case X86_VENDOR_Intel:
2167 /*
2168 * Extended L2 Cache features function.
2169 * First appeared on Prescott.
2170 */
2171 default:
2172 break;
2173 }
2174 break;
2175 default:
2176 break;
2177 }
2178 }
2179
2180 pass2_done:
2181 cpi->cpi_pass = 2;
2182 }
2183
2184 static const char *
2185 intel_cpubrand(const struct cpuid_info *cpi)
2186 {
2187 int i;
2188
2189 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2190 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2191 return ("i486");
2192
2193 switch (cpi->cpi_family) {
2194 case 5:
2195 return ("Intel Pentium(r)");
2196 case 6:
2197 switch (cpi->cpi_model) {
2198 uint_t celeron, xeon;
2199 const struct cpuid_regs *cp;
2200 case 0:
2201 case 1:
2202 case 2:
2203 return ("Intel Pentium(r) Pro");
2204 case 3:
2205 case 4:
2206 return ("Intel Pentium(r) II");
2207 case 6:
2208 return ("Intel Celeron(r)");
2209 case 5:
2210 case 7:
2211 celeron = xeon = 0;
2212 cp = &cpi->cpi_std[2]; /* cache info */
2213
2214 for (i = 1; i < 4; i++) {
2215 uint_t tmp;
2216
2217 tmp = (cp->cp_eax >> (8 * i)) & 0xff;
2218 if (tmp == 0x40)
2219 celeron++;
2220 if (tmp >= 0x44 && tmp <= 0x45)
2221 xeon++;
2222 }
2223
2224 for (i = 0; i < 2; i++) {
2225 uint_t tmp;
2226
2227 tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
2228 if (tmp == 0x40)
2229 celeron++;
2230 else if (tmp >= 0x44 && tmp <= 0x45)
2231 xeon++;
2232 }
2233
2234 for (i = 0; i < 4; i++) {
2235 uint_t tmp;
2236
2237 tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
2238 if (tmp == 0x40)
2239 celeron++;
2240 else if (tmp >= 0x44 && tmp <= 0x45)
2241 xeon++;
2242 }
2243
2244 for (i = 0; i < 4; i++) {
2245 uint_t tmp;
2246
2247 tmp = (cp->cp_edx >> (8 * i)) & 0xff;
2248 if (tmp == 0x40)
2249 celeron++;
2250 else if (tmp >= 0x44 && tmp <= 0x45)
2251 xeon++;
2252 }
2253
2254 if (celeron)
2255 return ("Intel Celeron(r)");
2256 if (xeon)
2257 return (cpi->cpi_model == 5 ?
2258 "Intel Pentium(r) II Xeon(tm)" :
2259 "Intel Pentium(r) III Xeon(tm)");
2260 return (cpi->cpi_model == 5 ?
2261 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
2262 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
2263 default:
2264 break;
2265 }
2266 default:
2267 break;
2268 }
2269
2270 /* BrandID is present if the field is nonzero */
2271 if (cpi->cpi_brandid != 0) {
2272 static const struct {
2273 uint_t bt_bid;
2274 const char *bt_str;
2275 } brand_tbl[] = {
2276 { 0x1, "Intel(r) Celeron(r)" },
2277 { 0x2, "Intel(r) Pentium(r) III" },
2278 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" },
2279 { 0x4, "Intel(r) Pentium(r) III" },
2280 { 0x6, "Mobile Intel(r) Pentium(r) III" },
2281 { 0x7, "Mobile Intel(r) Celeron(r)" },
2282 { 0x8, "Intel(r) Pentium(r) 4" },
2283 { 0x9, "Intel(r) Pentium(r) 4" },
2284 { 0xa, "Intel(r) Celeron(r)" },
2285 { 0xb, "Intel(r) Xeon(tm)" },
2286 { 0xc, "Intel(r) Xeon(tm) MP" },
2287 { 0xe, "Mobile Intel(r) Pentium(r) 4" },
2288 { 0xf, "Mobile Intel(r) Celeron(r)" },
2289 { 0x11, "Mobile Genuine Intel(r)" },
2290 { 0x12, "Intel(r) Celeron(r) M" },
2291 { 0x13, "Mobile Intel(r) Celeron(r)" },
2292 { 0x14, "Intel(r) Celeron(r)" },
2293 { 0x15, "Mobile Genuine Intel(r)" },
2294 { 0x16, "Intel(r) Pentium(r) M" },
2295 { 0x17, "Mobile Intel(r) Celeron(r)" }
2296 };
2297 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
2298 uint_t sgn;
2299
2300 sgn = (cpi->cpi_family << 8) |
2301 (cpi->cpi_model << 4) | cpi->cpi_step;
2302
2303 for (i = 0; i < btblmax; i++)
2304 if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
2305 break;
2306 if (i < btblmax) {
2307 if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
2308 return ("Intel(r) Celeron(r)");
2309 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
2310 return ("Intel(r) Xeon(tm) MP");
2311 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
2312 return ("Intel(r) Xeon(tm)");
2313 return (brand_tbl[i].bt_str);
2314 }
2315 }
2316
2317 return (NULL);
2318 }
2319
2320 static const char *
2321 amd_cpubrand(const struct cpuid_info *cpi)
2322 {
2323 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2324 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
2325 return ("i486 compatible");
2326
2327 switch (cpi->cpi_family) {
2328 case 5:
2329 switch (cpi->cpi_model) {
2330 case 0:
2331 case 1:
2332 case 2:
2333 case 3:
2334 case 4:
2335 case 5:
2336 return ("AMD-K5(r)");
2337 case 6:
2338 case 7:
2339 return ("AMD-K6(r)");
2340 case 8:
2341 return ("AMD-K6(r)-2");
2342 case 9:
2343 return ("AMD-K6(r)-III");
2344 default:
2345 return ("AMD (family 5)");
2346 }
2347 case 6:
2348 switch (cpi->cpi_model) {
2349 case 1:
2350 return ("AMD-K7(tm)");
2351 case 0:
2352 case 2:
2353 case 4:
2354 return ("AMD Athlon(tm)");
2355 case 3:
2356 case 7:
2357 return ("AMD Duron(tm)");
2358 case 6:
2359 case 8:
2360 case 10:
2361 /*
2362 * Use the L2 cache size to distinguish
2363 */
2364 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
2365 "AMD Athlon(tm)" : "AMD Duron(tm)");
2366 default:
2367 return ("AMD (family 6)");
2368 }
2369 default:
2370 break;
2371 }
2372
2373 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
2374 cpi->cpi_brandid != 0) {
2375 switch (BITX(cpi->cpi_brandid, 7, 5)) {
2376 case 3:
2377 return ("AMD Opteron(tm) UP 1xx");
2378 case 4:
2379 return ("AMD Opteron(tm) DP 2xx");
2380 case 5:
2381 return ("AMD Opteron(tm) MP 8xx");
2382 default:
2383 return ("AMD Opteron(tm)");
2384 }
2385 }
2386
2387 return (NULL);
2388 }
2389
2390 static const char *
2391 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
2392 {
2393 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) ||
2394 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
2395 type == X86_TYPE_CYRIX_486)
2396 return ("i486 compatible");
2397
2398 switch (type) {
2399 case X86_TYPE_CYRIX_6x86:
2400 return ("Cyrix 6x86");
2401 case X86_TYPE_CYRIX_6x86L:
2402 return ("Cyrix 6x86L");
2403 case X86_TYPE_CYRIX_6x86MX:
2404 return ("Cyrix 6x86MX");
2405 case X86_TYPE_CYRIX_GXm:
2406 return ("Cyrix GXm");
2407 case X86_TYPE_CYRIX_MediaGX:
2408 return ("Cyrix MediaGX");
2409 case X86_TYPE_CYRIX_MII:
2410 return ("Cyrix M2");
2411 case X86_TYPE_VIA_CYRIX_III:
2412 return ("VIA Cyrix M3");
2413 default:
2414 /*
2415 * Have another wild guess ..
2416 */
2417 if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
2418 return ("Cyrix 5x86");
2419 else if (cpi->cpi_family == 5) {
2420 switch (cpi->cpi_model) {
2421 case 2:
2422 return ("Cyrix 6x86"); /* Cyrix M1 */
2423 case 4:
2424 return ("Cyrix MediaGX");
2425 default:
2426 break;
2427 }
2428 } else if (cpi->cpi_family == 6) {
2429 switch (cpi->cpi_model) {
2430 case 0:
2431 return ("Cyrix 6x86MX"); /* Cyrix M2? */
2432 case 5:
2433 case 6:
2434 case 7:
2435 case 8:
2436 case 9:
2437 return ("VIA C3");
2438 default:
2439 break;
2440 }
2441 }
2442 break;
2443 }
2444 return (NULL);
2445 }
2446
2447 /*
2448 * This only gets called in the case that the CPU extended
2449 * feature brand string (0x80000002, 0x80000003, 0x80000004)
2450 * aren't available, or contain null bytes for some reason.
2451 */
2452 static void
2453 fabricate_brandstr(struct cpuid_info *cpi)
2454 {
2455 const char *brand = NULL;
2456
2457 switch (cpi->cpi_vendor) {
2458 case X86_VENDOR_Intel:
2459 brand = intel_cpubrand(cpi);
2460 break;
2461 case X86_VENDOR_AMD:
2462 brand = amd_cpubrand(cpi);
2463 break;
2464 case X86_VENDOR_Cyrix:
2465 brand = cyrix_cpubrand(cpi, x86_type);
2466 break;
2467 case X86_VENDOR_NexGen:
2468 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2469 brand = "NexGen Nx586";
2470 break;
2471 case X86_VENDOR_Centaur:
2472 if (cpi->cpi_family == 5)
2473 switch (cpi->cpi_model) {
2474 case 4:
2475 brand = "Centaur C6";
2476 break;
2477 case 8:
2478 brand = "Centaur C2";
2479 break;
2480 case 9:
2481 brand = "Centaur C3";
2482 break;
2483 default:
2484 break;
2485 }
2486 break;
2487 case X86_VENDOR_Rise:
2488 if (cpi->cpi_family == 5 &&
2489 (cpi->cpi_model == 0 || cpi->cpi_model == 2))
2490 brand = "Rise mP6";
2491 break;
2492 case X86_VENDOR_SiS:
2493 if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
2494 brand = "SiS 55x";
2495 break;
2496 case X86_VENDOR_TM:
2497 if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
2498 brand = "Transmeta Crusoe TM3x00 or TM5x00";
2499 break;
2500 case X86_VENDOR_NSC:
2501 case X86_VENDOR_UMC:
2502 default:
2503 break;
2504 }
2505 if (brand) {
2506 (void) strcpy((char *)cpi->cpi_brandstr, brand);
2507 return;
2508 }
2509
2510 /*
2511 * If all else fails ...
2512 */
2513 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
2514 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
2515 cpi->cpi_model, cpi->cpi_step);
2516 }
2517
2518 /*
2519 * This routine is called just after kernel memory allocation
2520 * becomes available on cpu0, and as part of mp_startup() on
2521 * the other cpus.
2522 *
2523 * Fixup the brand string, and collect any information from cpuid
2524 * that requires dynamically allocated storage to represent.
2525 */
2526 /*ARGSUSED*/
2527 void
2528 cpuid_pass3(cpu_t *cpu)
2529 {
2530 int i, max, shft, level, size;
2531 struct cpuid_regs regs;
2532 struct cpuid_regs *cp;
2533 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2534
2535 ASSERT(cpi->cpi_pass == 2);
2536
2537 /*
2538 * Function 4: Deterministic cache parameters
2539 *
2540 * Take this opportunity to detect the number of threads
2541 * sharing the last level cache, and construct a corresponding
2542 * cache id. The respective cpuid_info members are initialized
2543 * to the default case of "no last level cache sharing".
2544 */
2545 cpi->cpi_ncpu_shr_last_cache = 1;
2546 cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
2547
2548 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) {
2549
2550 /*
2551 * Find the # of elements (size) returned by fn 4, and along
2552 * the way detect last level cache sharing details.
2553 */
2554 bzero(®s, sizeof (regs));
2555 cp = ®s;
2556 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) {
2557 cp->cp_eax = 4;
2558 cp->cp_ecx = i;
2559
2560 (void) __cpuid_insn(cp);
2561
2562 if (CPI_CACHE_TYPE(cp) == 0)
2563 break;
2564 level = CPI_CACHE_LVL(cp);
2565 if (level > max) {
2566 max = level;
2567 cpi->cpi_ncpu_shr_last_cache =
2568 CPI_NTHR_SHR_CACHE(cp) + 1;
2569 }
2570 }
2571 cpi->cpi_std_4_size = size = i;
2572
2573 /*
2574 * Allocate the cpi_std_4 array. The first element
2575 * references the regs for fn 4, %ecx == 0, which
2576 * cpuid_pass2() stashed in cpi->cpi_std[4].
2577 */
2578 if (size > 0) {
2579 cpi->cpi_std_4 =
2580 kmem_alloc(size * sizeof (cp), KM_SLEEP);
2581 cpi->cpi_std_4[0] = &cpi->cpi_std[4];
2582
2583 /*
2584 * Allocate storage to hold the additional regs
2585 * for function 4, %ecx == 1 .. cpi_std_4_size.
2586 *
2587 * The regs for fn 4, %ecx == 0 has already
2588 * been allocated as indicated above.
2589 */
2590 for (i = 1; i < size; i++) {
2591 cp = cpi->cpi_std_4[i] =
2592 kmem_zalloc(sizeof (regs), KM_SLEEP);
2593 cp->cp_eax = 4;
2594 cp->cp_ecx = i;
2595
2596 (void) __cpuid_insn(cp);
2597 }
2598 }
2599 /*
2600 * Determine the number of bits needed to represent
2601 * the number of CPUs sharing the last level cache.
2602 *
2603 * Shift off that number of bits from the APIC id to
2604 * derive the cache id.
2605 */
2606 shft = 0;
2607 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1)
2608 shft++;
2609 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft;
2610 }
2611
2612 /*
2613 * Now fixup the brand string
2614 */
2615 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
2616 fabricate_brandstr(cpi);
2617 } else {
2618
2619 /*
2620 * If we successfully extracted a brand string from the cpuid
2621 * instruction, clean it up by removing leading spaces and
2622 * similar junk.
2623 */
2624 if (cpi->cpi_brandstr[0]) {
2625 size_t maxlen = sizeof (cpi->cpi_brandstr);
2626 char *src, *dst;
2627
2628 dst = src = (char *)cpi->cpi_brandstr;
2629 src[maxlen - 1] = '\0';
2630 /*
2631 * strip leading spaces
2632 */
2633 while (*src == ' ')
2634 src++;
2635 /*
2636 * Remove any 'Genuine' or "Authentic" prefixes
2637 */
2638 if (strncmp(src, "Genuine ", 8) == 0)
2639 src += 8;
2640 if (strncmp(src, "Authentic ", 10) == 0)
2641 src += 10;
2642
2643 /*
2644 * Now do an in-place copy.
2645 * Map (R) to (r) and (TM) to (tm).
2646 * The era of teletypes is long gone, and there's
2647 * -really- no need to shout.
2648 */
2649 while (*src != '\0') {
2650 if (src[0] == '(') {
2651 if (strncmp(src + 1, "R)", 2) == 0) {
2652 (void) strncpy(dst, "(r)", 3);
2653 src += 3;
2654 dst += 3;
2655 continue;
2656 }
2657 if (strncmp(src + 1, "TM)", 3) == 0) {
2658 (void) strncpy(dst, "(tm)", 4);
2659 src += 4;
2660 dst += 4;
2661 continue;
2662 }
2663 }
2664 *dst++ = *src++;
2665 }
2666 *dst = '\0';
2667
2668 /*
2669 * Finally, remove any trailing spaces
2670 */
2671 while (--dst > cpi->cpi_brandstr)
2672 if (*dst == ' ')
2673 *dst = '\0';
2674 else
2675 break;
2676 } else
2677 fabricate_brandstr(cpi);
2678 }
2679 cpi->cpi_pass = 3;
2680 }
2681
2682 /*
2683 * This routine is called out of bind_hwcap() much later in the life
2684 * of the kernel (post_startup()). The job of this routine is to resolve
2685 * the hardware feature support and kernel support for those features into
2686 * what we're actually going to tell applications via the aux vector.
2687 */
2688 void
2689 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
2690 {
2691 struct cpuid_info *cpi;
2692 uint_t hwcap_flags = 0, hwcap_flags_2 = 0;
2693
2694 if (cpu == NULL)
2695 cpu = CPU;
2696 cpi = cpu->cpu_m.mcpu_cpi;
2697
2698 ASSERT(cpi->cpi_pass == 3);
2699
2700 if (cpi->cpi_maxeax >= 1) {
2701 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
2702 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
2703 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES];
2704
2705 *edx = CPI_FEATURES_EDX(cpi);
2706 *ecx = CPI_FEATURES_ECX(cpi);
2707 *ebx = CPI_FEATURES_7_0_EBX(cpi);
2708
2709 /*
2710 * [these require explicit kernel support]
2711 */
2712 if (!is_x86_feature(x86_featureset, X86FSET_SEP))
2713 *edx &= ~CPUID_INTC_EDX_SEP;
2714
2715 if (!is_x86_feature(x86_featureset, X86FSET_SSE))
2716 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
2717 if (!is_x86_feature(x86_featureset, X86FSET_SSE2))
2718 *edx &= ~CPUID_INTC_EDX_SSE2;
2719
2720 if (!is_x86_feature(x86_featureset, X86FSET_HTT))
2721 *edx &= ~CPUID_INTC_EDX_HTT;
2722
2723 if (!is_x86_feature(x86_featureset, X86FSET_SSE3))
2724 *ecx &= ~CPUID_INTC_ECX_SSE3;
2725
2726 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3))
2727 *ecx &= ~CPUID_INTC_ECX_SSSE3;
2728 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1))
2729 *ecx &= ~CPUID_INTC_ECX_SSE4_1;
2730 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2))
2731 *ecx &= ~CPUID_INTC_ECX_SSE4_2;
2732 if (!is_x86_feature(x86_featureset, X86FSET_AES))
2733 *ecx &= ~CPUID_INTC_ECX_AES;
2734 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ))
2735 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ;
2736 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE))
2737 *ecx &= ~(CPUID_INTC_ECX_XSAVE |
2738 CPUID_INTC_ECX_OSXSAVE);
2739 if (!is_x86_feature(x86_featureset, X86FSET_AVX))
2740 *ecx &= ~CPUID_INTC_ECX_AVX;
2741 if (!is_x86_feature(x86_featureset, X86FSET_F16C))
2742 *ecx &= ~CPUID_INTC_ECX_F16C;
2743 if (!is_x86_feature(x86_featureset, X86FSET_FMA))
2744 *ecx &= ~CPUID_INTC_ECX_FMA;
2745 if (!is_x86_feature(x86_featureset, X86FSET_BMI1))
2746 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1;
2747 if (!is_x86_feature(x86_featureset, X86FSET_BMI2))
2748 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2;
2749 if (!is_x86_feature(x86_featureset, X86FSET_AVX2))
2750 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2;
2751 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED))
2752 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED;
2753 if (!is_x86_feature(x86_featureset, X86FSET_ADX))
2754 *ebx &= ~CPUID_INTC_EBX_7_0_ADX;
2755
2756 /*
2757 * [no explicit support required beyond x87 fp context]
2758 */
2759 if (!fpu_exists)
2760 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
2761
2762 /*
2763 * Now map the supported feature vector to things that we
2764 * think userland will care about.
2765 */
2766 if (*edx & CPUID_INTC_EDX_SEP)
2767 hwcap_flags |= AV_386_SEP;
2768 if (*edx & CPUID_INTC_EDX_SSE)
2769 hwcap_flags |= AV_386_FXSR | AV_386_SSE;
2770 if (*edx & CPUID_INTC_EDX_SSE2)
2771 hwcap_flags |= AV_386_SSE2;
2772 if (*ecx & CPUID_INTC_ECX_SSE3)
2773 hwcap_flags |= AV_386_SSE3;
2774 if (*ecx & CPUID_INTC_ECX_SSSE3)
2775 hwcap_flags |= AV_386_SSSE3;
2776 if (*ecx & CPUID_INTC_ECX_SSE4_1)
2777 hwcap_flags |= AV_386_SSE4_1;
2778 if (*ecx & CPUID_INTC_ECX_SSE4_2)
2779 hwcap_flags |= AV_386_SSE4_2;
2780 if (*ecx & CPUID_INTC_ECX_MOVBE)
2781 hwcap_flags |= AV_386_MOVBE;
2782 if (*ecx & CPUID_INTC_ECX_AES)
2783 hwcap_flags |= AV_386_AES;
2784 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ)
2785 hwcap_flags |= AV_386_PCLMULQDQ;
2786 if ((*ecx & CPUID_INTC_ECX_XSAVE) &&
2787 (*ecx & CPUID_INTC_ECX_OSXSAVE)) {
2788 hwcap_flags |= AV_386_XSAVE;
2789
2790 if (*ecx & CPUID_INTC_ECX_AVX) {
2791 hwcap_flags |= AV_386_AVX;
2792 if (*ecx & CPUID_INTC_ECX_F16C)
2793 hwcap_flags_2 |= AV_386_2_F16C;
2794 if (*ecx & CPUID_INTC_ECX_FMA)
2795 hwcap_flags_2 |= AV_386_2_FMA;
2796 if (*ebx & CPUID_INTC_EBX_7_0_BMI1)
2797 hwcap_flags_2 |= AV_386_2_BMI1;
2798 if (*ebx & CPUID_INTC_EBX_7_0_BMI2)
2799 hwcap_flags_2 |= AV_386_2_BMI2;
2800 if (*ebx & CPUID_INTC_EBX_7_0_AVX2)
2801 hwcap_flags_2 |= AV_386_2_AVX2;
2802 }
2803 }
2804 if (*ecx & CPUID_INTC_ECX_VMX)
2805 hwcap_flags |= AV_386_VMX;
2806 if (*ecx & CPUID_INTC_ECX_POPCNT)
2807 hwcap_flags |= AV_386_POPCNT;
2808 if (*edx & CPUID_INTC_EDX_FPU)
2809 hwcap_flags |= AV_386_FPU;
2810 if (*edx & CPUID_INTC_EDX_MMX)
2811 hwcap_flags |= AV_386_MMX;
2812
2813 if (*edx & CPUID_INTC_EDX_TSC)
2814 hwcap_flags |= AV_386_TSC;
2815 if (*edx & CPUID_INTC_EDX_CX8)
2816 hwcap_flags |= AV_386_CX8;
2817 if (*edx & CPUID_INTC_EDX_CMOV)
2818 hwcap_flags |= AV_386_CMOV;
2819 if (*ecx & CPUID_INTC_ECX_CX16)
2820 hwcap_flags |= AV_386_CX16;
2821
2822 if (*ecx & CPUID_INTC_ECX_RDRAND)
2823 hwcap_flags_2 |= AV_386_2_RDRAND;
2824 if (*ebx & CPUID_INTC_EBX_7_0_ADX)
2825 hwcap_flags_2 |= AV_386_2_ADX;
2826 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED)
2827 hwcap_flags_2 |= AV_386_2_RDSEED;
2828
2829 }
2830
2831 /* Detect systems with a potential CPUID limit */
2832 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax < 4) {
2833 cmn_err(CE_NOTE, "CPUID limit detected, "
2834 "see the CPUID(7D) man page for details\n");
2835 }
2836
2837
2838 if (cpi->cpi_xmaxeax < 0x80000001)
2839 goto pass4_done;
2840
2841 switch (cpi->cpi_vendor) {
2842 struct cpuid_regs cp;
2843 uint32_t *edx, *ecx;
2844
2845 case X86_VENDOR_Intel:
2846 /*
2847 * Seems like Intel duplicated what we necessary
2848 * here to make the initial crop of 64-bit OS's work.
2849 * Hopefully, those are the only "extended" bits
2850 * they'll add.
2851 */
2852 /*FALLTHROUGH*/
2853
2854 case X86_VENDOR_AMD:
2855 edx = &cpi->cpi_support[AMD_EDX_FEATURES];
2856 ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
2857
2858 *edx = CPI_FEATURES_XTD_EDX(cpi);
2859 *ecx = CPI_FEATURES_XTD_ECX(cpi);
2860
2861 /*
2862 * [these features require explicit kernel support]
2863 */
2864 switch (cpi->cpi_vendor) {
2865 case X86_VENDOR_Intel:
2866 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2867 *edx &= ~CPUID_AMD_EDX_TSCP;
2868 break;
2869
2870 case X86_VENDOR_AMD:
2871 if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
2872 *edx &= ~CPUID_AMD_EDX_TSCP;
2873 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
2874 *ecx &= ~CPUID_AMD_ECX_SSE4A;
2875 break;
2876
2877 default:
2878 break;
2879 }
2880
2881 /*
2882 * [no explicit support required beyond
2883 * x87 fp context and exception handlers]
2884 */
2885 if (!fpu_exists)
2886 *edx &= ~(CPUID_AMD_EDX_MMXamd |
2887 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
2888
2889 if (!is_x86_feature(x86_featureset, X86FSET_NX))
2890 *edx &= ~CPUID_AMD_EDX_NX;
2891 #if !defined(__amd64)
2892 *edx &= ~CPUID_AMD_EDX_LM;
2893 #endif
2894 /*
2895 * Now map the supported feature vector to
2896 * things that we think userland will care about.
2897 */
2898 #if defined(__amd64)
2899 if (*edx & CPUID_AMD_EDX_SYSC)
2900 hwcap_flags |= AV_386_AMD_SYSC;
2901 #endif
2902 if (*edx & CPUID_AMD_EDX_MMXamd)
2903 hwcap_flags |= AV_386_AMD_MMX;
2904 if (*edx & CPUID_AMD_EDX_3DNow)
2905 hwcap_flags |= AV_386_AMD_3DNow;
2906 if (*edx & CPUID_AMD_EDX_3DNowx)
2907 hwcap_flags |= AV_386_AMD_3DNowx;
2908 if (*ecx & CPUID_AMD_ECX_SVM)
2909 hwcap_flags |= AV_386_AMD_SVM;
2910
2911 switch (cpi->cpi_vendor) {
2912 case X86_VENDOR_AMD:
2913 if (*edx & CPUID_AMD_EDX_TSCP)
2914 hwcap_flags |= AV_386_TSCP;
2915 if (*ecx & CPUID_AMD_ECX_AHF64)
2916 hwcap_flags |= AV_386_AHF;
2917 if (*ecx & CPUID_AMD_ECX_SSE4A)
2918 hwcap_flags |= AV_386_AMD_SSE4A;
2919 if (*ecx & CPUID_AMD_ECX_LZCNT)
2920 hwcap_flags |= AV_386_AMD_LZCNT;
2921 break;
2922
2923 case X86_VENDOR_Intel:
2924 if (*edx & CPUID_AMD_EDX_TSCP)
2925 hwcap_flags |= AV_386_TSCP;
2926 /*
2927 * Aarrgh.
2928 * Intel uses a different bit in the same word.
2929 */
2930 if (*ecx & CPUID_INTC_ECX_AHF64)
2931 hwcap_flags |= AV_386_AHF;
2932 break;
2933
2934 default:
2935 break;
2936 }
2937 break;
2938
2939 case X86_VENDOR_TM:
2940 cp.cp_eax = 0x80860001;
2941 (void) __cpuid_insn(&cp);
2942 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
2943 break;
2944
2945 default:
2946 break;
2947 }
2948
2949 pass4_done:
2950 cpi->cpi_pass = 4;
2951 if (hwcap_out != NULL) {
2952 hwcap_out[0] = hwcap_flags;
2953 hwcap_out[1] = hwcap_flags_2;
2954 }
2955 }
2956
2957
2958 /*
2959 * Simulate the cpuid instruction using the data we previously
2960 * captured about this CPU. We try our best to return the truth
2961 * about the hardware, independently of kernel support.
2962 */
2963 uint32_t
2964 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
2965 {
2966 struct cpuid_info *cpi;
2967 struct cpuid_regs *xcp;
2968
2969 if (cpu == NULL)
2970 cpu = CPU;
2971 cpi = cpu->cpu_m.mcpu_cpi;
2972
2973 ASSERT(cpuid_checkpass(cpu, 3));
2974
2975 /*
2976 * CPUID data is cached in two separate places: cpi_std for standard
2977 * CPUID functions, and cpi_extd for extended CPUID functions.
2978 */
2979 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
2980 xcp = &cpi->cpi_std[cp->cp_eax];
2981 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
2982 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
2983 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
2984 else
2985 /*
2986 * The caller is asking for data from an input parameter which
2987 * the kernel has not cached. In this case we go fetch from
2988 * the hardware and return the data directly to the user.
2989 */
2990 return (__cpuid_insn(cp));
2991
2992 cp->cp_eax = xcp->cp_eax;
2993 cp->cp_ebx = xcp->cp_ebx;
2994 cp->cp_ecx = xcp->cp_ecx;
2995 cp->cp_edx = xcp->cp_edx;
2996 return (cp->cp_eax);
2997 }
2998
2999 int
3000 cpuid_checkpass(cpu_t *cpu, int pass)
3001 {
3002 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
3003 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
3004 }
3005
3006 int
3007 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
3008 {
3009 ASSERT(cpuid_checkpass(cpu, 3));
3010
3011 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
3012 }
3013
3014 int
3015 cpuid_is_cmt(cpu_t *cpu)
3016 {
3017 if (cpu == NULL)
3018 cpu = CPU;
3019
3020 ASSERT(cpuid_checkpass(cpu, 1));
3021
3022 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
3023 }
3024
3025 /*
3026 * AMD and Intel both implement the 64-bit variant of the syscall
3027 * instruction (syscallq), so if there's -any- support for syscall,
3028 * cpuid currently says "yes, we support this".
3029 *
3030 * However, Intel decided to -not- implement the 32-bit variant of the
3031 * syscall instruction, so we provide a predicate to allow our caller
3032 * to test that subtlety here.
3033 *
3034 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor,
3035 * even in the case where the hardware would in fact support it.
3036 */
3037 /*ARGSUSED*/
3038 int
3039 cpuid_syscall32_insn(cpu_t *cpu)
3040 {
3041 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
3042
3043 #if !defined(__xpv)
3044 if (cpu == NULL)
3045 cpu = CPU;
3046
3047 /*CSTYLED*/
3048 {
3049 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3050
3051 if (cpi->cpi_vendor == X86_VENDOR_AMD &&
3052 cpi->cpi_xmaxeax >= 0x80000001 &&
3053 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
3054 return (1);
3055 }
3056 #endif
3057 return (0);
3058 }
3059
3060 int
3061 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
3062 {
3063 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3064
3065 static const char fmt[] =
3066 "x86 (%s %X family %d model %d step %d clock %d MHz)";
3067 static const char fmt_ht[] =
3068 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
3069
3070 ASSERT(cpuid_checkpass(cpu, 1));
3071
3072 if (cpuid_is_cmt(cpu))
3073 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
3074 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3075 cpi->cpi_family, cpi->cpi_model,
3076 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3077 return (snprintf(s, n, fmt,
3078 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
3079 cpi->cpi_family, cpi->cpi_model,
3080 cpi->cpi_step, cpu->cpu_type_info.pi_clock));
3081 }
3082
3083 const char *
3084 cpuid_getvendorstr(cpu_t *cpu)
3085 {
3086 ASSERT(cpuid_checkpass(cpu, 1));
3087 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
3088 }
3089
3090 uint_t
3091 cpuid_getvendor(cpu_t *cpu)
3092 {
3093 ASSERT(cpuid_checkpass(cpu, 1));
3094 return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
3095 }
3096
3097 uint_t
3098 cpuid_getfamily(cpu_t *cpu)
3099 {
3100 ASSERT(cpuid_checkpass(cpu, 1));
3101 return (cpu->cpu_m.mcpu_cpi->cpi_family);
3102 }
3103
3104 uint_t
3105 cpuid_getmodel(cpu_t *cpu)
3106 {
3107 ASSERT(cpuid_checkpass(cpu, 1));
3108 return (cpu->cpu_m.mcpu_cpi->cpi_model);
3109 }
3110
3111 uint_t
3112 cpuid_get_ncpu_per_chip(cpu_t *cpu)
3113 {
3114 ASSERT(cpuid_checkpass(cpu, 1));
3115 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
3116 }
3117
3118 uint_t
3119 cpuid_get_ncore_per_chip(cpu_t *cpu)
3120 {
3121 ASSERT(cpuid_checkpass(cpu, 1));
3122 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
3123 }
3124
3125 uint_t
3126 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu)
3127 {
3128 ASSERT(cpuid_checkpass(cpu, 2));
3129 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache);
3130 }
3131
3132 id_t
3133 cpuid_get_last_lvl_cacheid(cpu_t *cpu)
3134 {
3135 ASSERT(cpuid_checkpass(cpu, 2));
3136 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3137 }
3138
3139 uint_t
3140 cpuid_getstep(cpu_t *cpu)
3141 {
3142 ASSERT(cpuid_checkpass(cpu, 1));
3143 return (cpu->cpu_m.mcpu_cpi->cpi_step);
3144 }
3145
3146 uint_t
3147 cpuid_getsig(struct cpu *cpu)
3148 {
3149 ASSERT(cpuid_checkpass(cpu, 1));
3150 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax);
3151 }
3152
3153 uint32_t
3154 cpuid_getchiprev(struct cpu *cpu)
3155 {
3156 ASSERT(cpuid_checkpass(cpu, 1));
3157 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
3158 }
3159
3160 const char *
3161 cpuid_getchiprevstr(struct cpu *cpu)
3162 {
3163 ASSERT(cpuid_checkpass(cpu, 1));
3164 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
3165 }
3166
3167 uint32_t
3168 cpuid_getsockettype(struct cpu *cpu)
3169 {
3170 ASSERT(cpuid_checkpass(cpu, 1));
3171 return (cpu->cpu_m.mcpu_cpi->cpi_socket);
3172 }
3173
3174 const char *
3175 cpuid_getsocketstr(cpu_t *cpu)
3176 {
3177 static const char *socketstr = NULL;
3178 struct cpuid_info *cpi;
3179
3180 ASSERT(cpuid_checkpass(cpu, 1));
3181 cpi = cpu->cpu_m.mcpu_cpi;
3182
3183 /* Assume that socket types are the same across the system */
3184 if (socketstr == NULL)
3185 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family,
3186 cpi->cpi_model, cpi->cpi_step);
3187
3188
3189 return (socketstr);
3190 }
3191
3192 int
3193 cpuid_get_chipid(cpu_t *cpu)
3194 {
3195 ASSERT(cpuid_checkpass(cpu, 1));
3196
3197 if (cpuid_is_cmt(cpu))
3198 return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
3199 return (cpu->cpu_id);
3200 }
3201
3202 id_t
3203 cpuid_get_coreid(cpu_t *cpu)
3204 {
3205 ASSERT(cpuid_checkpass(cpu, 1));
3206 return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
3207 }
3208
3209 int
3210 cpuid_get_pkgcoreid(cpu_t *cpu)
3211 {
3212 ASSERT(cpuid_checkpass(cpu, 1));
3213 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid);
3214 }
3215
3216 int
3217 cpuid_get_clogid(cpu_t *cpu)
3218 {
3219 ASSERT(cpuid_checkpass(cpu, 1));
3220 return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
3221 }
3222
3223 int
3224 cpuid_get_cacheid(cpu_t *cpu)
3225 {
3226 ASSERT(cpuid_checkpass(cpu, 1));
3227 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid);
3228 }
3229
3230 uint_t
3231 cpuid_get_procnodeid(cpu_t *cpu)
3232 {
3233 ASSERT(cpuid_checkpass(cpu, 1));
3234 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid);
3235 }
3236
3237 uint_t
3238 cpuid_get_procnodes_per_pkg(cpu_t *cpu)
3239 {
3240 ASSERT(cpuid_checkpass(cpu, 1));
3241 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg);
3242 }
3243
3244 uint_t
3245 cpuid_get_compunitid(cpu_t *cpu)
3246 {
3247 ASSERT(cpuid_checkpass(cpu, 1));
3248 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid);
3249 }
3250
3251 uint_t
3252 cpuid_get_cores_per_compunit(cpu_t *cpu)
3253 {
3254 ASSERT(cpuid_checkpass(cpu, 1));
3255 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit);
3256 }
3257
3258 /*ARGSUSED*/
3259 int
3260 cpuid_have_cr8access(cpu_t *cpu)
3261 {
3262 #if defined(__amd64)
3263 return (1);
3264 #else
3265 struct cpuid_info *cpi;
3266
3267 ASSERT(cpu != NULL);
3268 cpi = cpu->cpu_m.mcpu_cpi;
3269 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
3270 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
3271 return (1);
3272 return (0);
3273 #endif
3274 }
3275
3276 uint32_t
3277 cpuid_get_apicid(cpu_t *cpu)
3278 {
3279 ASSERT(cpuid_checkpass(cpu, 1));
3280 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) {
3281 return (UINT32_MAX);
3282 } else {
3283 return (cpu->cpu_m.mcpu_cpi->cpi_apicid);
3284 }
3285 }
3286
3287 void
3288 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
3289 {
3290 struct cpuid_info *cpi;
3291
3292 if (cpu == NULL)
3293 cpu = CPU;
3294 cpi = cpu->cpu_m.mcpu_cpi;
3295
3296 ASSERT(cpuid_checkpass(cpu, 1));
3297
3298 if (pabits)
3299 *pabits = cpi->cpi_pabits;
3300 if (vabits)
3301 *vabits = cpi->cpi_vabits;
3302 }
3303
3304 /*
3305 * Returns the number of data TLB entries for a corresponding
3306 * pagesize. If it can't be computed, or isn't known, the
3307 * routine returns zero. If you ask about an architecturally
3308 * impossible pagesize, the routine will panic (so that the
3309 * hat implementor knows that things are inconsistent.)
3310 */
3311 uint_t
3312 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
3313 {
3314 struct cpuid_info *cpi;
3315 uint_t dtlb_nent = 0;
3316
3317 if (cpu == NULL)
3318 cpu = CPU;
3319 cpi = cpu->cpu_m.mcpu_cpi;
3320
3321 ASSERT(cpuid_checkpass(cpu, 1));
3322
3323 /*
3324 * Check the L2 TLB info
3325 */
3326 if (cpi->cpi_xmaxeax >= 0x80000006) {
3327 struct cpuid_regs *cp = &cpi->cpi_extd[6];
3328
3329 switch (pagesize) {
3330
3331 case 4 * 1024:
3332 /*
3333 * All zero in the top 16 bits of the register
3334 * indicates a unified TLB. Size is in low 16 bits.
3335 */
3336 if ((cp->cp_ebx & 0xffff0000) == 0)
3337 dtlb_nent = cp->cp_ebx & 0x0000ffff;
3338 else
3339 dtlb_nent = BITX(cp->cp_ebx, 27, 16);
3340 break;
3341
3342 case 2 * 1024 * 1024:
3343 if ((cp->cp_eax & 0xffff0000) == 0)
3344 dtlb_nent = cp->cp_eax & 0x0000ffff;
3345 else
3346 dtlb_nent = BITX(cp->cp_eax, 27, 16);
3347 break;
3348
3349 default:
3350 panic("unknown L2 pagesize");
3351 /*NOTREACHED*/
3352 }
3353 }
3354
3355 if (dtlb_nent != 0)
3356 return (dtlb_nent);
3357
3358 /*
3359 * No L2 TLB support for this size, try L1.
3360 */
3361 if (cpi->cpi_xmaxeax >= 0x80000005) {
3362 struct cpuid_regs *cp = &cpi->cpi_extd[5];
3363
3364 switch (pagesize) {
3365 case 4 * 1024:
3366 dtlb_nent = BITX(cp->cp_ebx, 23, 16);
3367 break;
3368 case 2 * 1024 * 1024:
3369 dtlb_nent = BITX(cp->cp_eax, 23, 16);
3370 break;
3371 default:
3372 panic("unknown L1 d-TLB pagesize");
3373 /*NOTREACHED*/
3374 }
3375 }
3376
3377 return (dtlb_nent);
3378 }
3379
3380 /*
3381 * Return 0 if the erratum is not present or not applicable, positive
3382 * if it is, and negative if the status of the erratum is unknown.
3383 *
3384 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
3385 * Processors" #25759, Rev 3.57, August 2005
3386 */
3387 int
3388 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
3389 {
3390 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3391 uint_t eax;
3392
3393 /*
3394 * Bail out if this CPU isn't an AMD CPU, or if it's
3395 * a legacy (32-bit) AMD CPU.
3396 */
3397 if (cpi->cpi_vendor != X86_VENDOR_AMD ||
3398 cpi->cpi_family == 4 || cpi->cpi_family == 5 ||
3399 cpi->cpi_family == 6)
3400
3401 return (0);
3402
3403 eax = cpi->cpi_std[1].cp_eax;
3404
3405 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50)
3406 #define SH_B3(eax) (eax == 0xf51)
3407 #define B(eax) (SH_B0(eax) || SH_B3(eax))
3408
3409 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58)
3410
3411 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
3412 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
3413 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2)
3414 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
3415
3416 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
3417 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0)
3418 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0)
3419 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
3420
3421 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
3422 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */
3423 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0)
3424 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71)
3425 #define BH_E4(eax) (eax == 0x20fb1)
3426 #define SH_E5(eax) (eax == 0x20f42)
3427 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2)
3428 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32)
3429 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
3430 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
3431 DH_E6(eax) || JH_E6(eax))
3432
3433 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02)
3434 #define DR_B0(eax) (eax == 0x100f20)
3435 #define DR_B1(eax) (eax == 0x100f21)
3436 #define DR_BA(eax) (eax == 0x100f2a)
3437 #define DR_B2(eax) (eax == 0x100f22)
3438 #define DR_B3(eax) (eax == 0x100f23)
3439 #define RB_C0(eax) (eax == 0x100f40)
3440
3441 switch (erratum) {
3442 case 1:
3443 return (cpi->cpi_family < 0x10);
3444 case 51: /* what does the asterisk mean? */
3445 return (B(eax) || SH_C0(eax) || CG(eax));
3446 case 52:
3447 return (B(eax));
3448 case 57:
3449 return (cpi->cpi_family <= 0x11);
3450 case 58:
3451 return (B(eax));
3452 case 60:
3453 return (cpi->cpi_family <= 0x11);
3454 case 61:
3455 case 62:
3456 case 63:
3457 case 64:
3458 case 65:
3459 case 66:
3460 case 68:
3461 case 69:
3462 case 70:
3463 case 71:
3464 return (B(eax));
3465 case 72:
3466 return (SH_B0(eax));
3467 case 74:
3468 return (B(eax));
3469 case 75:
3470 return (cpi->cpi_family < 0x10);
3471 case 76:
3472 return (B(eax));
3473 case 77:
3474 return (cpi->cpi_family <= 0x11);
3475 case 78:
3476 return (B(eax) || SH_C0(eax));
3477 case 79:
3478 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3479 case 80:
3480 case 81:
3481 case 82:
3482 return (B(eax));
3483 case 83:
3484 return (B(eax) || SH_C0(eax) || CG(eax));
3485 case 85:
3486 return (cpi->cpi_family < 0x10);
3487 case 86:
3488 return (SH_C0(eax) || CG(eax));
3489 case 88:
3490 #if !defined(__amd64)
3491 return (0);
3492 #else
3493 return (B(eax) || SH_C0(eax));
3494 #endif
3495 case 89:
3496 return (cpi->cpi_family < 0x10);
3497 case 90:
3498 return (B(eax) || SH_C0(eax) || CG(eax));
3499 case 91:
3500 case 92:
3501 return (B(eax) || SH_C0(eax));
3502 case 93:
3503 return (SH_C0(eax));
3504 case 94:
3505 return (B(eax) || SH_C0(eax) || CG(eax));
3506 case 95:
3507 #if !defined(__amd64)
3508 return (0);
3509 #else
3510 return (B(eax) || SH_C0(eax));
3511 #endif
3512 case 96:
3513 return (B(eax) || SH_C0(eax) || CG(eax));
3514 case 97:
3515 case 98:
3516 return (SH_C0(eax) || CG(eax));
3517 case 99:
3518 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3519 case 100:
3520 return (B(eax) || SH_C0(eax));
3521 case 101:
3522 case 103:
3523 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3524 case 104:
3525 return (SH_C0(eax) || CG(eax) || D0(eax));
3526 case 105:
3527 case 106:
3528 case 107:
3529 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3530 case 108:
3531 return (DH_CG(eax));
3532 case 109:
3533 return (SH_C0(eax) || CG(eax) || D0(eax));
3534 case 110:
3535 return (D0(eax) || EX(eax));
3536 case 111:
3537 return (CG(eax));
3538 case 112:
3539 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3540 case 113:
3541 return (eax == 0x20fc0);
3542 case 114:
3543 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3544 case 115:
3545 return (SH_E0(eax) || JH_E1(eax));
3546 case 116:
3547 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
3548 case 117:
3549 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
3550 case 118:
3551 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
3552 JH_E6(eax));
3553 case 121:
3554 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
3555 case 122:
3556 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11);
3557 case 123:
3558 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
3559 case 131:
3560 return (cpi->cpi_family < 0x10);
3561 case 6336786:
3562 /*
3563 * Test for AdvPowerMgmtInfo.TscPStateInvariant
3564 * if this is a K8 family or newer processor
3565 */
3566 if (CPI_FAMILY(cpi) == 0xf) {
3567 struct cpuid_regs regs;
3568 regs.cp_eax = 0x80000007;
3569 (void) __cpuid_insn(®s);
3570 return (!(regs.cp_edx & 0x100));
3571 }
3572 return (0);
3573 case 6323525:
3574 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
3575 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
3576
3577 case 6671130:
3578 /*
3579 * check for processors (pre-Shanghai) that do not provide
3580 * optimal management of 1gb ptes in its tlb.
3581 */
3582 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4);
3583
3584 case 298:
3585 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) ||
3586 DR_B2(eax) || RB_C0(eax));
3587
3588 case 721:
3589 #if defined(__amd64)
3590 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12);
3591 #else
3592 return (0);
3593 #endif
3594
3595 default:
3596 return (-1);
3597
3598 }
3599 }
3600
3601 /*
3602 * Determine if specified erratum is present via OSVW (OS Visible Workaround).
3603 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate.
3604 */
3605 int
3606 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum)
3607 {
3608 struct cpuid_info *cpi;
3609 uint_t osvwid;
3610 static int osvwfeature = -1;
3611 uint64_t osvwlength;
3612
3613
3614 cpi = cpu->cpu_m.mcpu_cpi;
3615
3616 /* confirm OSVW supported */
3617 if (osvwfeature == -1) {
3618 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW;
3619 } else {
3620 /* assert that osvw feature setting is consistent on all cpus */
3621 ASSERT(osvwfeature ==
3622 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW));
3623 }
3624 if (!osvwfeature)
3625 return (-1);
3626
3627 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK;
3628
3629 switch (erratum) {
3630 case 298: /* osvwid is 0 */
3631 osvwid = 0;
3632 if (osvwlength <= (uint64_t)osvwid) {
3633 /* osvwid 0 is unknown */
3634 return (-1);
3635 }
3636
3637 /*
3638 * Check the OSVW STATUS MSR to determine the state
3639 * of the erratum where:
3640 * 0 - fixed by HW
3641 * 1 - BIOS has applied the workaround when BIOS
3642 * workaround is available. (Or for other errata,
3643 * OS workaround is required.)
3644 * For a value of 1, caller will confirm that the
3645 * erratum 298 workaround has indeed been applied by BIOS.
3646 *
3647 * A 1 may be set in cpus that have a HW fix
3648 * in a mixed cpu system. Regarding erratum 298:
3649 * In a multiprocessor platform, the workaround above
3650 * should be applied to all processors regardless of
3651 * silicon revision when an affected processor is
3652 * present.
3653 */
3654
3655 return (rdmsr(MSR_AMD_OSVW_STATUS +
3656 (osvwid / OSVW_ID_CNT_PER_MSR)) &
3657 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR)));
3658
3659 default:
3660 return (-1);
3661 }
3662 }
3663
3664 static const char assoc_str[] = "associativity";
3665 static const char line_str[] = "line-size";
3666 static const char size_str[] = "size";
3667
3668 static void
3669 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
3670 uint32_t val)
3671 {
3672 char buf[128];
3673
3674 /*
3675 * ndi_prop_update_int() is used because it is desirable for
3676 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
3677 */
3678 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
3679 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
3680 }
3681
3682 /*
3683 * Intel-style cache/tlb description
3684 *
3685 * Standard cpuid level 2 gives a randomly ordered
3686 * selection of tags that index into a table that describes
3687 * cache and tlb properties.
3688 */
3689
3690 static const char l1_icache_str[] = "l1-icache";
3691 static const char l1_dcache_str[] = "l1-dcache";
3692 static const char l2_cache_str[] = "l2-cache";
3693 static const char l3_cache_str[] = "l3-cache";
3694 static const char itlb4k_str[] = "itlb-4K";
3695 static const char dtlb4k_str[] = "dtlb-4K";
3696 static const char itlb2M_str[] = "itlb-2M";
3697 static const char itlb4M_str[] = "itlb-4M";
3698 static const char dtlb4M_str[] = "dtlb-4M";
3699 static const char dtlb24_str[] = "dtlb0-2M-4M";
3700 static const char itlb424_str[] = "itlb-4K-2M-4M";
3701 static const char itlb24_str[] = "itlb-2M-4M";
3702 static const char dtlb44_str[] = "dtlb-4K-4M";
3703 static const char sl1_dcache_str[] = "sectored-l1-dcache";
3704 static const char sl2_cache_str[] = "sectored-l2-cache";
3705 static const char itrace_str[] = "itrace-cache";
3706 static const char sl3_cache_str[] = "sectored-l3-cache";
3707 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
3708
3709 static const struct cachetab {
3710 uint8_t ct_code;
3711 uint8_t ct_assoc;
3712 uint16_t ct_line_size;
3713 size_t ct_size;
3714 const char *ct_label;
3715 } intel_ctab[] = {
3716 /*
3717 * maintain descending order!
3718 *
3719 * Codes ignored - Reason
3720 * ----------------------
3721 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache
3722 * f0H/f1H - Currently we do not interpret prefetch size by design
3723 */
3724 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str},
3725 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str},
3726 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str},
3727 { 0xde, 12, 64, 6*1024*1024, l3_cache_str},
3728 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str},
3729 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str},
3730 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str},
3731 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str},
3732 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str},
3733 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str},
3734 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str},
3735 { 0xd0, 4, 64, 512*1024, l3_cache_str},
3736 { 0xca, 4, 0, 512, sh_l2_tlb4k_str},
3737 { 0xc0, 4, 0, 8, dtlb44_str },
3738 { 0xba, 4, 0, 64, dtlb4k_str },
3739 { 0xb4, 4, 0, 256, dtlb4k_str },
3740 { 0xb3, 4, 0, 128, dtlb4k_str },
3741 { 0xb2, 4, 0, 64, itlb4k_str },
3742 { 0xb0, 4, 0, 128, itlb4k_str },
3743 { 0x87, 8, 64, 1024*1024, l2_cache_str},
3744 { 0x86, 4, 64, 512*1024, l2_cache_str},
3745 { 0x85, 8, 32, 2*1024*1024, l2_cache_str},
3746 { 0x84, 8, 32, 1024*1024, l2_cache_str},
3747 { 0x83, 8, 32, 512*1024, l2_cache_str},
3748 { 0x82, 8, 32, 256*1024, l2_cache_str},
3749 { 0x80, 8, 64, 512*1024, l2_cache_str},
3750 { 0x7f, 2, 64, 512*1024, l2_cache_str},
3751 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
3752 { 0x7c, 8, 64, 1024*1024, sl2_cache_str},
3753 { 0x7b, 8, 64, 512*1024, sl2_cache_str},
3754 { 0x7a, 8, 64, 256*1024, sl2_cache_str},
3755 { 0x79, 8, 64, 128*1024, sl2_cache_str},
3756 { 0x78, 8, 64, 1024*1024, l2_cache_str},
3757 { 0x73, 8, 0, 64*1024, itrace_str},
3758 { 0x72, 8, 0, 32*1024, itrace_str},
3759 { 0x71, 8, 0, 16*1024, itrace_str},
3760 { 0x70, 8, 0, 12*1024, itrace_str},
3761 { 0x68, 4, 64, 32*1024, sl1_dcache_str},
3762 { 0x67, 4, 64, 16*1024, sl1_dcache_str},
3763 { 0x66, 4, 64, 8*1024, sl1_dcache_str},
3764 { 0x60, 8, 64, 16*1024, sl1_dcache_str},
3765 { 0x5d, 0, 0, 256, dtlb44_str},
3766 { 0x5c, 0, 0, 128, dtlb44_str},
3767 { 0x5b, 0, 0, 64, dtlb44_str},
3768 { 0x5a, 4, 0, 32, dtlb24_str},
3769 { 0x59, 0, 0, 16, dtlb4k_str},
3770 { 0x57, 4, 0, 16, dtlb4k_str},
3771 { 0x56, 4, 0, 16, dtlb4M_str},
3772 { 0x55, 0, 0, 7, itlb24_str},
3773 { 0x52, 0, 0, 256, itlb424_str},
3774 { 0x51, 0, 0, 128, itlb424_str},
3775 { 0x50, 0, 0, 64, itlb424_str},
3776 { 0x4f, 0, 0, 32, itlb4k_str},
3777 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str},
3778 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
3779 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
3780 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
3781 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
3782 { 0x49, 16, 64, 4*1024*1024, l3_cache_str},
3783 { 0x48, 12, 64, 3*1024*1024, l2_cache_str},
3784 { 0x47, 8, 64, 8*1024*1024, l3_cache_str},
3785 { 0x46, 4, 64, 4*1024*1024, l3_cache_str},
3786 { 0x45, 4, 32, 2*1024*1024, l2_cache_str},
3787 { 0x44, 4, 32, 1024*1024, l2_cache_str},
3788 { 0x43, 4, 32, 512*1024, l2_cache_str},
3789 { 0x42, 4, 32, 256*1024, l2_cache_str},
3790 { 0x41, 4, 32, 128*1024, l2_cache_str},
3791 { 0x3e, 4, 64, 512*1024, sl2_cache_str},
3792 { 0x3d, 6, 64, 384*1024, sl2_cache_str},
3793 { 0x3c, 4, 64, 256*1024, sl2_cache_str},
3794 { 0x3b, 2, 64, 128*1024, sl2_cache_str},
3795 { 0x3a, 6, 64, 192*1024, sl2_cache_str},
3796 { 0x39, 4, 64, 128*1024, sl2_cache_str},
3797 { 0x30, 8, 64, 32*1024, l1_icache_str},
3798 { 0x2c, 8, 64, 32*1024, l1_dcache_str},
3799 { 0x29, 8, 64, 4096*1024, sl3_cache_str},
3800 { 0x25, 8, 64, 2048*1024, sl3_cache_str},
3801 { 0x23, 8, 64, 1024*1024, sl3_cache_str},
3802 { 0x22, 4, 64, 512*1024, sl3_cache_str},
3803 { 0x0e, 6, 64, 24*1024, l1_dcache_str},
3804 { 0x0d, 4, 32, 16*1024, l1_dcache_str},
3805 { 0x0c, 4, 32, 16*1024, l1_dcache_str},
3806 { 0x0b, 4, 0, 4, itlb4M_str},
3807 { 0x0a, 2, 32, 8*1024, l1_dcache_str},
3808 { 0x08, 4, 32, 16*1024, l1_icache_str},
3809 { 0x06, 4, 32, 8*1024, l1_icache_str},
3810 { 0x05, 4, 0, 32, dtlb4M_str},
3811 { 0x04, 4, 0, 8, dtlb4M_str},
3812 { 0x03, 4, 0, 64, dtlb4k_str},
3813 { 0x02, 4, 0, 2, itlb4M_str},
3814 { 0x01, 4, 0, 32, itlb4k_str},
3815 { 0 }
3816 };
3817
3818 static const struct cachetab cyrix_ctab[] = {
3819 { 0x70, 4, 0, 32, "tlb-4K" },
3820 { 0x80, 4, 16, 16*1024, "l1-cache" },
3821 { 0 }
3822 };
3823
3824 /*
3825 * Search a cache table for a matching entry
3826 */
3827 static const struct cachetab *
3828 find_cacheent(const struct cachetab *ct, uint_t code)
3829 {
3830 if (code != 0) {
3831 for (; ct->ct_code != 0; ct++)
3832 if (ct->ct_code <= code)
3833 break;
3834 if (ct->ct_code == code)
3835 return (ct);
3836 }
3837 return (NULL);
3838 }
3839
3840 /*
3841 * Populate cachetab entry with L2 or L3 cache-information using
3842 * cpuid function 4. This function is called from intel_walk_cacheinfo()
3843 * when descriptor 0x49 is encountered. It returns 0 if no such cache
3844 * information is found.
3845 */
3846 static int
3847 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi)
3848 {
3849 uint32_t level, i;
3850 int ret = 0;
3851
3852 for (i = 0; i < cpi->cpi_std_4_size; i++) {
3853 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]);
3854
3855 if (level == 2 || level == 3) {
3856 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1;
3857 ct->ct_line_size =
3858 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1;
3859 ct->ct_size = ct->ct_assoc *
3860 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) *
3861 ct->ct_line_size *
3862 (cpi->cpi_std_4[i]->cp_ecx + 1);
3863
3864 if (level == 2) {
3865 ct->ct_label = l2_cache_str;
3866 } else if (level == 3) {
3867 ct->ct_label = l3_cache_str;
3868 }
3869 ret = 1;
3870 }
3871 }
3872
3873 return (ret);
3874 }
3875
3876 /*
3877 * Walk the cacheinfo descriptor, applying 'func' to every valid element
3878 * The walk is terminated if the walker returns non-zero.
3879 */
3880 static void
3881 intel_walk_cacheinfo(struct cpuid_info *cpi,
3882 void *arg, int (*func)(void *, const struct cachetab *))
3883 {
3884 const struct cachetab *ct;
3885 struct cachetab des_49_ct, des_b1_ct;
3886 uint8_t *dp;
3887 int i;
3888
3889 if ((dp = cpi->cpi_cacheinfo) == NULL)
3890 return;
3891 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3892 /*
3893 * For overloaded descriptor 0x49 we use cpuid function 4
3894 * if supported by the current processor, to create
3895 * cache information.
3896 * For overloaded descriptor 0xb1 we use X86_PAE flag
3897 * to disambiguate the cache information.
3898 */
3899 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 &&
3900 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) {
3901 ct = &des_49_ct;
3902 } else if (*dp == 0xb1) {
3903 des_b1_ct.ct_code = 0xb1;
3904 des_b1_ct.ct_assoc = 4;
3905 des_b1_ct.ct_line_size = 0;
3906 if (is_x86_feature(x86_featureset, X86FSET_PAE)) {
3907 des_b1_ct.ct_size = 8;
3908 des_b1_ct.ct_label = itlb2M_str;
3909 } else {
3910 des_b1_ct.ct_size = 4;
3911 des_b1_ct.ct_label = itlb4M_str;
3912 }
3913 ct = &des_b1_ct;
3914 } else {
3915 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) {
3916 continue;
3917 }
3918 }
3919
3920 if (func(arg, ct) != 0) {
3921 break;
3922 }
3923 }
3924 }
3925
3926 /*
3927 * (Like the Intel one, except for Cyrix CPUs)
3928 */
3929 static void
3930 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
3931 void *arg, int (*func)(void *, const struct cachetab *))
3932 {
3933 const struct cachetab *ct;
3934 uint8_t *dp;
3935 int i;
3936
3937 if ((dp = cpi->cpi_cacheinfo) == NULL)
3938 return;
3939 for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
3940 /*
3941 * Search Cyrix-specific descriptor table first ..
3942 */
3943 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
3944 if (func(arg, ct) != 0)
3945 break;
3946 continue;
3947 }
3948 /*
3949 * .. else fall back to the Intel one
3950 */
3951 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
3952 if (func(arg, ct) != 0)
3953 break;
3954 continue;
3955 }
3956 }
3957 }
3958
3959 /*
3960 * A cacheinfo walker that adds associativity, line-size, and size properties
3961 * to the devinfo node it is passed as an argument.
3962 */
3963 static int
3964 add_cacheent_props(void *arg, const struct cachetab *ct)
3965 {
3966 dev_info_t *devi = arg;
3967
3968 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
3969 if (ct->ct_line_size != 0)
3970 add_cache_prop(devi, ct->ct_label, line_str,
3971 ct->ct_line_size);
3972 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
3973 return (0);
3974 }
3975
3976
3977 static const char fully_assoc[] = "fully-associative?";
3978
3979 /*
3980 * AMD style cache/tlb description
3981 *
3982 * Extended functions 5 and 6 directly describe properties of
3983 * tlbs and various cache levels.
3984 */
3985 static void
3986 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
3987 {
3988 switch (assoc) {
3989 case 0: /* reserved; ignore */
3990 break;
3991 default:
3992 add_cache_prop(devi, label, assoc_str, assoc);
3993 break;
3994 case 0xff:
3995 add_cache_prop(devi, label, fully_assoc, 1);
3996 break;
3997 }
3998 }
3999
4000 static void
4001 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4002 {
4003 if (size == 0)
4004 return;
4005 add_cache_prop(devi, label, size_str, size);
4006 add_amd_assoc(devi, label, assoc);
4007 }
4008
4009 static void
4010 add_amd_cache(dev_info_t *devi, const char *label,
4011 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4012 {
4013 if (size == 0 || line_size == 0)
4014 return;
4015 add_amd_assoc(devi, label, assoc);
4016 /*
4017 * Most AMD parts have a sectored cache. Multiple cache lines are
4018 * associated with each tag. A sector consists of all cache lines
4019 * associated with a tag. For example, the AMD K6-III has a sector
4020 * size of 2 cache lines per tag.
4021 */
4022 if (lines_per_tag != 0)
4023 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4024 add_cache_prop(devi, label, line_str, line_size);
4025 add_cache_prop(devi, label, size_str, size * 1024);
4026 }
4027
4028 static void
4029 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
4030 {
4031 switch (assoc) {
4032 case 0: /* off */
4033 break;
4034 case 1:
4035 case 2:
4036 case 4:
4037 add_cache_prop(devi, label, assoc_str, assoc);
4038 break;
4039 case 6:
4040 add_cache_prop(devi, label, assoc_str, 8);
4041 break;
4042 case 8:
4043 add_cache_prop(devi, label, assoc_str, 16);
4044 break;
4045 case 0xf:
4046 add_cache_prop(devi, label, fully_assoc, 1);
4047 break;
4048 default: /* reserved; ignore */
4049 break;
4050 }
4051 }
4052
4053 static void
4054 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
4055 {
4056 if (size == 0 || assoc == 0)
4057 return;
4058 add_amd_l2_assoc(devi, label, assoc);
4059 add_cache_prop(devi, label, size_str, size);
4060 }
4061
4062 static void
4063 add_amd_l2_cache(dev_info_t *devi, const char *label,
4064 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
4065 {
4066 if (size == 0 || assoc == 0 || line_size == 0)
4067 return;
4068 add_amd_l2_assoc(devi, label, assoc);
4069 if (lines_per_tag != 0)
4070 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
4071 add_cache_prop(devi, label, line_str, line_size);
4072 add_cache_prop(devi, label, size_str, size * 1024);
4073 }
4074
4075 static void
4076 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
4077 {
4078 struct cpuid_regs *cp;
4079
4080 if (cpi->cpi_xmaxeax < 0x80000005)
4081 return;
4082 cp = &cpi->cpi_extd[5];
4083
4084 /*
4085 * 4M/2M L1 TLB configuration
4086 *
4087 * We report the size for 2M pages because AMD uses two
4088 * TLB entries for one 4M page.
4089 */
4090 add_amd_tlb(devi, "dtlb-2M",
4091 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
4092 add_amd_tlb(devi, "itlb-2M",
4093 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
4094
4095 /*
4096 * 4K L1 TLB configuration
4097 */
4098
4099 switch (cpi->cpi_vendor) {
4100 uint_t nentries;
4101 case X86_VENDOR_TM:
4102 if (cpi->cpi_family >= 5) {
4103 /*
4104 * Crusoe processors have 256 TLB entries, but
4105 * cpuid data format constrains them to only
4106 * reporting 255 of them.
4107 */
4108 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
4109 nentries = 256;
4110 /*
4111 * Crusoe processors also have a unified TLB
4112 */
4113 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
4114 nentries);
4115 break;
4116 }
4117 /*FALLTHROUGH*/
4118 default:
4119 add_amd_tlb(devi, itlb4k_str,
4120 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
4121 add_amd_tlb(devi, dtlb4k_str,
4122 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
4123 break;
4124 }
4125
4126 /*
4127 * data L1 cache configuration
4128 */
4129
4130 add_amd_cache(devi, l1_dcache_str,
4131 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
4132 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
4133
4134 /*
4135 * code L1 cache configuration
4136 */
4137
4138 add_amd_cache(devi, l1_icache_str,
4139 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
4140 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
4141
4142 if (cpi->cpi_xmaxeax < 0x80000006)
4143 return;
4144 cp = &cpi->cpi_extd[6];
4145
4146 /* Check for a unified L2 TLB for large pages */
4147
4148 if (BITX(cp->cp_eax, 31, 16) == 0)
4149 add_amd_l2_tlb(devi, "l2-tlb-2M",
4150 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4151 else {
4152 add_amd_l2_tlb(devi, "l2-dtlb-2M",
4153 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4154 add_amd_l2_tlb(devi, "l2-itlb-2M",
4155 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4156 }
4157
4158 /* Check for a unified L2 TLB for 4K pages */
4159
4160 if (BITX(cp->cp_ebx, 31, 16) == 0) {
4161 add_amd_l2_tlb(devi, "l2-tlb-4K",
4162 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4163 } else {
4164 add_amd_l2_tlb(devi, "l2-dtlb-4K",
4165 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
4166 add_amd_l2_tlb(devi, "l2-itlb-4K",
4167 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
4168 }
4169
4170 add_amd_l2_cache(devi, l2_cache_str,
4171 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
4172 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
4173 }
4174
4175 /*
4176 * There are two basic ways that the x86 world describes it cache
4177 * and tlb architecture - Intel's way and AMD's way.
4178 *
4179 * Return which flavor of cache architecture we should use
4180 */
4181 static int
4182 x86_which_cacheinfo(struct cpuid_info *cpi)
4183 {
4184 switch (cpi->cpi_vendor) {
4185 case X86_VENDOR_Intel:
4186 if (cpi->cpi_maxeax >= 2)
4187 return (X86_VENDOR_Intel);
4188 break;
4189 case X86_VENDOR_AMD:
4190 /*
4191 * The K5 model 1 was the first part from AMD that reported
4192 * cache sizes via extended cpuid functions.
4193 */
4194 if (cpi->cpi_family > 5 ||
4195 (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
4196 return (X86_VENDOR_AMD);
4197 break;
4198 case X86_VENDOR_TM:
4199 if (cpi->cpi_family >= 5)
4200 return (X86_VENDOR_AMD);
4201 /*FALLTHROUGH*/
4202 default:
4203 /*
4204 * If they have extended CPU data for 0x80000005
4205 * then we assume they have AMD-format cache
4206 * information.
4207 *
4208 * If not, and the vendor happens to be Cyrix,
4209 * then try our-Cyrix specific handler.
4210 *
4211 * If we're not Cyrix, then assume we're using Intel's
4212 * table-driven format instead.
4213 */
4214 if (cpi->cpi_xmaxeax >= 0x80000005)
4215 return (X86_VENDOR_AMD);
4216 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
4217 return (X86_VENDOR_Cyrix);
4218 else if (cpi->cpi_maxeax >= 2)
4219 return (X86_VENDOR_Intel);
4220 break;
4221 }
4222 return (-1);
4223 }
4224
4225 void
4226 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
4227 struct cpuid_info *cpi)
4228 {
4229 dev_info_t *cpu_devi;
4230 int create;
4231
4232 cpu_devi = (dev_info_t *)dip;
4233
4234 /* device_type */
4235 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4236 "device_type", "cpu");
4237
4238 /* reg */
4239 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4240 "reg", cpu_id);
4241
4242 /* cpu-mhz, and clock-frequency */
4243 if (cpu_freq > 0) {
4244 long long mul;
4245
4246 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4247 "cpu-mhz", cpu_freq);
4248 if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
4249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4250 "clock-frequency", (int)mul);
4251 }
4252
4253 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) {
4254 return;
4255 }
4256
4257 /* vendor-id */
4258 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4259 "vendor-id", cpi->cpi_vendorstr);
4260
4261 if (cpi->cpi_maxeax == 0) {
4262 return;
4263 }
4264
4265 /*
4266 * family, model, and step
4267 */
4268 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4269 "family", CPI_FAMILY(cpi));
4270 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4271 "cpu-model", CPI_MODEL(cpi));
4272 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4273 "stepping-id", CPI_STEP(cpi));
4274
4275 /* type */
4276 switch (cpi->cpi_vendor) {
4277 case X86_VENDOR_Intel:
4278 create = 1;
4279 break;
4280 default:
4281 create = 0;
4282 break;
4283 }
4284 if (create)
4285 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4286 "type", CPI_TYPE(cpi));
4287
4288 /* ext-family */
4289 switch (cpi->cpi_vendor) {
4290 case X86_VENDOR_Intel:
4291 case X86_VENDOR_AMD:
4292 create = cpi->cpi_family >= 0xf;
4293 break;
4294 default:
4295 create = 0;
4296 break;
4297 }
4298 if (create)
4299 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4300 "ext-family", CPI_FAMILY_XTD(cpi));
4301
4302 /* ext-model */
4303 switch (cpi->cpi_vendor) {
4304 case X86_VENDOR_Intel:
4305 create = IS_EXTENDED_MODEL_INTEL(cpi);
4306 break;
4307 case X86_VENDOR_AMD:
4308 create = CPI_FAMILY(cpi) == 0xf;
4309 break;
4310 default:
4311 create = 0;
4312 break;
4313 }
4314 if (create)
4315 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4316 "ext-model", CPI_MODEL_XTD(cpi));
4317
4318 /* generation */
4319 switch (cpi->cpi_vendor) {
4320 case X86_VENDOR_AMD:
4321 /*
4322 * AMD K5 model 1 was the first part to support this
4323 */
4324 create = cpi->cpi_xmaxeax >= 0x80000001;
4325 break;
4326 default:
4327 create = 0;
4328 break;
4329 }
4330 if (create)
4331 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4332 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
4333
4334 /* brand-id */
4335 switch (cpi->cpi_vendor) {
4336 case X86_VENDOR_Intel:
4337 /*
4338 * brand id first appeared on Pentium III Xeon model 8,
4339 * and Celeron model 8 processors and Opteron
4340 */
4341 create = cpi->cpi_family > 6 ||
4342 (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
4343 break;
4344 case X86_VENDOR_AMD:
4345 create = cpi->cpi_family >= 0xf;
4346 break;
4347 default:
4348 create = 0;
4349 break;
4350 }
4351 if (create && cpi->cpi_brandid != 0) {
4352 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4353 "brand-id", cpi->cpi_brandid);
4354 }
4355
4356 /* chunks, and apic-id */
4357 switch (cpi->cpi_vendor) {
4358 /*
4359 * first available on Pentium IV and Opteron (K8)
4360 */
4361 case X86_VENDOR_Intel:
4362 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4363 break;
4364 case X86_VENDOR_AMD:
4365 create = cpi->cpi_family >= 0xf;
4366 break;
4367 default:
4368 create = 0;
4369 break;
4370 }
4371 if (create) {
4372 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4373 "chunks", CPI_CHUNKS(cpi));
4374 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4375 "apic-id", cpi->cpi_apicid);
4376 if (cpi->cpi_chipid >= 0) {
4377 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4378 "chip#", cpi->cpi_chipid);
4379 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4380 "clog#", cpi->cpi_clogid);
4381 }
4382 }
4383
4384 /* cpuid-features */
4385 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4386 "cpuid-features", CPI_FEATURES_EDX(cpi));
4387
4388
4389 /* cpuid-features-ecx */
4390 switch (cpi->cpi_vendor) {
4391 case X86_VENDOR_Intel:
4392 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
4393 break;
4394 case X86_VENDOR_AMD:
4395 create = cpi->cpi_family >= 0xf;
4396 break;
4397 default:
4398 create = 0;
4399 break;
4400 }
4401 if (create)
4402 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4403 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
4404
4405 /* ext-cpuid-features */
4406 switch (cpi->cpi_vendor) {
4407 case X86_VENDOR_Intel:
4408 case X86_VENDOR_AMD:
4409 case X86_VENDOR_Cyrix:
4410 case X86_VENDOR_TM:
4411 case X86_VENDOR_Centaur:
4412 create = cpi->cpi_xmaxeax >= 0x80000001;
4413 break;
4414 default:
4415 create = 0;
4416 break;
4417 }
4418 if (create) {
4419 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4420 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
4421 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
4422 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
4423 }
4424
4425 /*
4426 * Brand String first appeared in Intel Pentium IV, AMD K5
4427 * model 1, and Cyrix GXm. On earlier models we try and
4428 * simulate something similar .. so this string should always
4429 * same -something- about the processor, however lame.
4430 */
4431 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
4432 "brand-string", cpi->cpi_brandstr);
4433
4434 /*
4435 * Finally, cache and tlb information
4436 */
4437 switch (x86_which_cacheinfo(cpi)) {
4438 case X86_VENDOR_Intel:
4439 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4440 break;
4441 case X86_VENDOR_Cyrix:
4442 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
4443 break;
4444 case X86_VENDOR_AMD:
4445 amd_cache_info(cpi, cpu_devi);
4446 break;
4447 default:
4448 break;
4449 }
4450 }
4451
4452 struct l2info {
4453 int *l2i_csz;
4454 int *l2i_lsz;
4455 int *l2i_assoc;
4456 int l2i_ret;
4457 };
4458
4459 /*
4460 * A cacheinfo walker that fetches the size, line-size and associativity
4461 * of the L2 cache
4462 */
4463 static int
4464 intel_l2cinfo(void *arg, const struct cachetab *ct)
4465 {
4466 struct l2info *l2i = arg;
4467 int *ip;
4468
4469 if (ct->ct_label != l2_cache_str &&
4470 ct->ct_label != sl2_cache_str)
4471 return (0); /* not an L2 -- keep walking */
4472
4473 if ((ip = l2i->l2i_csz) != NULL)
4474 *ip = ct->ct_size;
4475 if ((ip = l2i->l2i_lsz) != NULL)
4476 *ip = ct->ct_line_size;
4477 if ((ip = l2i->l2i_assoc) != NULL)
4478 *ip = ct->ct_assoc;
4479 l2i->l2i_ret = ct->ct_size;
4480 return (1); /* was an L2 -- terminate walk */
4481 }
4482
4483 /*
4484 * AMD L2/L3 Cache and TLB Associativity Field Definition:
4485 *
4486 * Unlike the associativity for the L1 cache and tlb where the 8 bit
4487 * value is the associativity, the associativity for the L2 cache and
4488 * tlb is encoded in the following table. The 4 bit L2 value serves as
4489 * an index into the amd_afd[] array to determine the associativity.
4490 * -1 is undefined. 0 is fully associative.
4491 */
4492
4493 static int amd_afd[] =
4494 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0};
4495
4496 static void
4497 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
4498 {
4499 struct cpuid_regs *cp;
4500 uint_t size, assoc;
4501 int i;
4502 int *ip;
4503
4504 if (cpi->cpi_xmaxeax < 0x80000006)
4505 return;
4506 cp = &cpi->cpi_extd[6];
4507
4508 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 &&
4509 (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
4510 uint_t cachesz = size * 1024;
4511 assoc = amd_afd[i];
4512
4513 ASSERT(assoc != -1);
4514
4515 if ((ip = l2i->l2i_csz) != NULL)
4516 *ip = cachesz;
4517 if ((ip = l2i->l2i_lsz) != NULL)
4518 *ip = BITX(cp->cp_ecx, 7, 0);
4519 if ((ip = l2i->l2i_assoc) != NULL)
4520 *ip = assoc;
4521 l2i->l2i_ret = cachesz;
4522 }
4523 }
4524
4525 int
4526 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
4527 {
4528 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
4529 struct l2info __l2info, *l2i = &__l2info;
4530
4531 l2i->l2i_csz = csz;
4532 l2i->l2i_lsz = lsz;
4533 l2i->l2i_assoc = assoc;
4534 l2i->l2i_ret = -1;
4535
4536 switch (x86_which_cacheinfo(cpi)) {
4537 case X86_VENDOR_Intel:
4538 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4539 break;
4540 case X86_VENDOR_Cyrix:
4541 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
4542 break;
4543 case X86_VENDOR_AMD:
4544 amd_l2cacheinfo(cpi, l2i);
4545 break;
4546 default:
4547 break;
4548 }
4549 return (l2i->l2i_ret);
4550 }
4551
4552 #if !defined(__xpv)
4553
4554 uint32_t *
4555 cpuid_mwait_alloc(cpu_t *cpu)
4556 {
4557 uint32_t *ret;
4558 size_t mwait_size;
4559
4560 ASSERT(cpuid_checkpass(CPU, 2));
4561
4562 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max;
4563 if (mwait_size == 0)
4564 return (NULL);
4565
4566 /*
4567 * kmem_alloc() returns cache line size aligned data for mwait_size
4568 * allocations. mwait_size is currently cache line sized. Neither
4569 * of these implementation details are guarantied to be true in the
4570 * future.
4571 *
4572 * First try allocating mwait_size as kmem_alloc() currently returns
4573 * correctly aligned memory. If kmem_alloc() does not return
4574 * mwait_size aligned memory, then use mwait_size ROUNDUP.
4575 *
4576 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we
4577 * decide to free this memory.
4578 */
4579 ret = kmem_zalloc(mwait_size, KM_SLEEP);
4580 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) {
4581 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4582 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size;
4583 *ret = MWAIT_RUNNING;
4584 return (ret);
4585 } else {
4586 kmem_free(ret, mwait_size);
4587 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP);
4588 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret;
4589 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2;
4590 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size);
4591 *ret = MWAIT_RUNNING;
4592 return (ret);
4593 }
4594 }
4595
4596 void
4597 cpuid_mwait_free(cpu_t *cpu)
4598 {
4599 if (cpu->cpu_m.mcpu_cpi == NULL) {
4600 return;
4601 }
4602
4603 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL &&
4604 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) {
4605 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual,
4606 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual);
4607 }
4608
4609 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL;
4610 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0;
4611 }
4612
4613 void
4614 patch_tsc_read(int flag)
4615 {
4616 size_t cnt;
4617
4618 switch (flag) {
4619 case TSC_NONE:
4620 cnt = &_no_rdtsc_end - &_no_rdtsc_start;
4621 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
4622 break;
4623 case TSC_RDTSC_MFENCE:
4624 cnt = &_tsc_mfence_end - &_tsc_mfence_start;
4625 (void) memcpy((void *)tsc_read,
4626 (void *)&_tsc_mfence_start, cnt);
4627 break;
4628 case TSC_RDTSC_LFENCE:
4629 cnt = &_tsc_lfence_end - &_tsc_lfence_start;
4630 (void) memcpy((void *)tsc_read,
4631 (void *)&_tsc_lfence_start, cnt);
4632 break;
4633 case TSC_TSCP:
4634 cnt = &_tscp_end - &_tscp_start;
4635 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt);
4636 break;
4637 default:
4638 /* Bail for unexpected TSC types. (TSC_NONE covers 0) */
4639 cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag);
4640 break;
4641 }
4642 tsc_type = flag;
4643 }
4644
4645 int
4646 cpuid_deep_cstates_supported(void)
4647 {
4648 struct cpuid_info *cpi;
4649 struct cpuid_regs regs;
4650
4651 ASSERT(cpuid_checkpass(CPU, 1));
4652
4653 cpi = CPU->cpu_m.mcpu_cpi;
4654
4655 if (!is_x86_feature(x86_featureset, X86FSET_CPUID))
4656 return (0);
4657
4658 switch (cpi->cpi_vendor) {
4659 case X86_VENDOR_Intel:
4660 if (cpi->cpi_xmaxeax < 0x80000007)
4661 return (0);
4662
4663 /*
4664 * TSC run at a constant rate in all ACPI C-states?
4665 */
4666 regs.cp_eax = 0x80000007;
4667 (void) __cpuid_insn(®s);
4668 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE);
4669
4670 default:
4671 return (0);
4672 }
4673 }
4674
4675 #endif /* !__xpv */
4676
4677 void
4678 post_startup_cpu_fixups(void)
4679 {
4680 #ifndef __xpv
4681 /*
4682 * Some AMD processors support C1E state. Entering this state will
4683 * cause the local APIC timer to stop, which we can't deal with at
4684 * this time.
4685 */
4686 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) {
4687 on_trap_data_t otd;
4688 uint64_t reg;
4689
4690 if (!on_trap(&otd, OT_DATA_ACCESS)) {
4691 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT);
4692 /* Disable C1E state if it is enabled by BIOS */
4693 if ((reg >> AMD_ACTONCMPHALT_SHIFT) &
4694 AMD_ACTONCMPHALT_MASK) {
4695 reg &= ~(AMD_ACTONCMPHALT_MASK <<
4696 AMD_ACTONCMPHALT_SHIFT);
4697 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg);
4698 }
4699 }
4700 no_trap();
4701 }
4702 #endif /* !__xpv */
4703 }
4704
4705 /*
4706 * Setup necessary registers to enable XSAVE feature on this processor.
4707 * This function needs to be called early enough, so that no xsave/xrstor
4708 * ops will execute on the processor before the MSRs are properly set up.
4709 *
4710 * Current implementation has the following assumption:
4711 * - cpuid_pass1() is done, so that X86 features are known.
4712 * - fpu_probe() is done, so that fp_save_mech is chosen.
4713 */
4714 void
4715 xsave_setup_msr(cpu_t *cpu)
4716 {
4717 ASSERT(fp_save_mech == FP_XSAVE);
4718 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE));
4719
4720 /* Enable OSXSAVE in CR4. */
4721 setcr4(getcr4() | CR4_OSXSAVE);
4722 /*
4723 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report
4724 * correct value.
4725 */
4726 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE;
4727 setup_xfem();
4728 }
4729
4730 /*
4731 * Starting with the Westmere processor the local
4732 * APIC timer will continue running in all C-states,
4733 * including the deepest C-states.
4734 */
4735 int
4736 cpuid_arat_supported(void)
4737 {
4738 struct cpuid_info *cpi;
4739 struct cpuid_regs regs;
4740
4741 ASSERT(cpuid_checkpass(CPU, 1));
4742 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4743
4744 cpi = CPU->cpu_m.mcpu_cpi;
4745
4746 switch (cpi->cpi_vendor) {
4747 case X86_VENDOR_Intel:
4748 /*
4749 * Always-running Local APIC Timer is
4750 * indicated by CPUID.6.EAX[2].
4751 */
4752 if (cpi->cpi_maxeax >= 6) {
4753 regs.cp_eax = 6;
4754 (void) cpuid_insn(NULL, ®s);
4755 return (regs.cp_eax & CPUID_CSTATE_ARAT);
4756 } else {
4757 return (0);
4758 }
4759 default:
4760 return (0);
4761 }
4762 }
4763
4764 /*
4765 * Check support for Intel ENERGY_PERF_BIAS feature
4766 */
4767 int
4768 cpuid_iepb_supported(struct cpu *cp)
4769 {
4770 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi;
4771 struct cpuid_regs regs;
4772
4773 ASSERT(cpuid_checkpass(cp, 1));
4774
4775 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) ||
4776 !(is_x86_feature(x86_featureset, X86FSET_MSR))) {
4777 return (0);
4778 }
4779
4780 /*
4781 * Intel ENERGY_PERF_BIAS MSR is indicated by
4782 * capability bit CPUID.6.ECX.3
4783 */
4784 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6))
4785 return (0);
4786
4787 regs.cp_eax = 0x6;
4788 (void) cpuid_insn(NULL, ®s);
4789 return (regs.cp_ecx & CPUID_EPB_SUPPORT);
4790 }
4791
4792 /*
4793 * Check support for TSC deadline timer
4794 *
4795 * TSC deadline timer provides a superior software programming
4796 * model over local APIC timer that eliminates "time drifts".
4797 * Instead of specifying a relative time, software specifies an
4798 * absolute time as the target at which the processor should
4799 * generate a timer event.
4800 */
4801 int
4802 cpuid_deadline_tsc_supported(void)
4803 {
4804 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi;
4805 struct cpuid_regs regs;
4806
4807 ASSERT(cpuid_checkpass(CPU, 1));
4808 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID));
4809
4810 switch (cpi->cpi_vendor) {
4811 case X86_VENDOR_Intel:
4812 if (cpi->cpi_maxeax >= 1) {
4813 regs.cp_eax = 1;
4814 (void) cpuid_insn(NULL, ®s);
4815 return (regs.cp_ecx & CPUID_DEADLINE_TSC);
4816 } else {
4817 return (0);
4818 }
4819 default:
4820 return (0);
4821 }
4822 }
4823
4824 #if defined(__amd64) && !defined(__xpv)
4825 /*
4826 * Patch in versions of bcopy for high performance Intel Nhm processors
4827 * and later...
4828 */
4829 void
4830 patch_memops(uint_t vendor)
4831 {
4832 size_t cnt, i;
4833 caddr_t to, from;
4834
4835 if ((vendor == X86_VENDOR_Intel) &&
4836 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) {
4837 cnt = &bcopy_patch_end - &bcopy_patch_start;
4838 to = &bcopy_ck_size;
4839 from = &bcopy_patch_start;
4840 for (i = 0; i < cnt; i++) {
4841 *to++ = *from++;
4842 }
4843 }
4844 }
4845 #endif /* __amd64 && !__xpv */
4846
4847 /*
4848 * This function finds the number of bits to represent the number of cores per
4849 * chip and the number of strands per core for the Intel platforms.
4850 * It re-uses the x2APIC cpuid code of the cpuid_pass2().
4851 */
4852 void
4853 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits)
4854 {
4855 struct cpuid_regs regs;
4856 struct cpuid_regs *cp = ®s;
4857
4858 if (vendor != X86_VENDOR_Intel) {
4859 return;
4860 }
4861
4862 /* if the cpuid level is 0xB, extended topo is available. */
4863 cp->cp_eax = 0;
4864 if (__cpuid_insn(cp) >= 0xB) {
4865
4866 cp->cp_eax = 0xB;
4867 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0;
4868 (void) __cpuid_insn(cp);
4869
4870 /*
4871 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which
4872 * indicates that the extended topology enumeration leaf is
4873 * available.
4874 */
4875 if (cp->cp_ebx) {
4876 uint_t coreid_shift = 0;
4877 uint_t chipid_shift = 0;
4878 uint_t i;
4879 uint_t level;
4880
4881 for (i = 0; i < CPI_FNB_ECX_MAX; i++) {
4882 cp->cp_eax = 0xB;
4883 cp->cp_ecx = i;
4884
4885 (void) __cpuid_insn(cp);
4886 level = CPI_CPU_LEVEL_TYPE(cp);
4887
4888 if (level == 1) {
4889 /*
4890 * Thread level processor topology
4891 * Number of bits shift right APIC ID
4892 * to get the coreid.
4893 */
4894 coreid_shift = BITX(cp->cp_eax, 4, 0);
4895 } else if (level == 2) {
4896 /*
4897 * Core level processor topology
4898 * Number of bits shift right APIC ID
4899 * to get the chipid.
4900 */
4901 chipid_shift = BITX(cp->cp_eax, 4, 0);
4902 }
4903 }
4904
4905 if (coreid_shift > 0 && chipid_shift > coreid_shift) {
4906 *strand_nbits = coreid_shift;
4907 *core_nbits = chipid_shift - coreid_shift;
4908 }
4909 }
4910 }
4911 }