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3534 Disable EEE support in igb for I350
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--- old/usr/src/uts/common/io/igb/igb_main.c
+++ new/usr/src/uts/common/io/igb/igb_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 + * Copyright 2013, Nexenta Systems, Inc. All rights reserved.
28 29 */
29 30
30 31 #include "igb_sw.h"
31 32
32 33 static char ident[] = "Intel 1Gb Ethernet";
33 34 static char igb_version[] = "igb 1.1.18";
34 35
35 36 /*
36 37 * Local function protoypes
37 38 */
38 39 static int igb_register_mac(igb_t *);
39 40 static int igb_identify_hardware(igb_t *);
40 41 static int igb_regs_map(igb_t *);
41 42 static void igb_init_properties(igb_t *);
42 43 static int igb_init_driver_settings(igb_t *);
43 44 static void igb_init_locks(igb_t *);
44 45 static void igb_destroy_locks(igb_t *);
45 46 static int igb_init_mac_address(igb_t *);
46 47 static int igb_init(igb_t *);
47 48 static int igb_init_adapter(igb_t *);
48 49 static void igb_stop_adapter(igb_t *);
49 50 static int igb_reset(igb_t *);
50 51 static void igb_tx_clean(igb_t *);
51 52 static boolean_t igb_tx_drain(igb_t *);
52 53 static boolean_t igb_rx_drain(igb_t *);
53 54 static int igb_alloc_rings(igb_t *);
54 55 static int igb_alloc_rx_data(igb_t *);
55 56 static void igb_free_rx_data(igb_t *);
56 57 static void igb_free_rings(igb_t *);
57 58 static void igb_setup_rings(igb_t *);
58 59 static void igb_setup_rx(igb_t *);
59 60 static void igb_setup_tx(igb_t *);
60 61 static void igb_setup_rx_ring(igb_rx_ring_t *);
61 62 static void igb_setup_tx_ring(igb_tx_ring_t *);
62 63 static void igb_setup_rss(igb_t *);
63 64 static void igb_setup_mac_rss_classify(igb_t *);
64 65 static void igb_setup_mac_classify(igb_t *);
65 66 static void igb_init_unicst(igb_t *);
66 67 static void igb_setup_multicst(igb_t *);
67 68 static void igb_get_phy_state(igb_t *);
68 69 static void igb_param_sync(igb_t *);
69 70 static void igb_get_conf(igb_t *);
70 71 static int igb_get_prop(igb_t *, char *, int, int, int);
71 72 static boolean_t igb_is_link_up(igb_t *);
72 73 static boolean_t igb_link_check(igb_t *);
73 74 static void igb_local_timer(void *);
74 75 static void igb_link_timer(void *);
75 76 static void igb_arm_watchdog_timer(igb_t *);
76 77 static void igb_start_watchdog_timer(igb_t *);
77 78 static void igb_restart_watchdog_timer(igb_t *);
78 79 static void igb_stop_watchdog_timer(igb_t *);
79 80 static void igb_start_link_timer(igb_t *);
80 81 static void igb_stop_link_timer(igb_t *);
81 82 static void igb_disable_adapter_interrupts(igb_t *);
82 83 static void igb_enable_adapter_interrupts_82575(igb_t *);
83 84 static void igb_enable_adapter_interrupts_82576(igb_t *);
84 85 static void igb_enable_adapter_interrupts_82580(igb_t *);
85 86 static boolean_t is_valid_mac_addr(uint8_t *);
86 87 static boolean_t igb_stall_check(igb_t *);
87 88 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t);
88 89 static void igb_set_external_loopback(igb_t *);
89 90 static void igb_set_internal_phy_loopback(igb_t *);
90 91 static void igb_set_internal_serdes_loopback(igb_t *);
91 92 static boolean_t igb_find_mac_address(igb_t *);
92 93 static int igb_alloc_intrs(igb_t *);
93 94 static int igb_alloc_intr_handles(igb_t *, int);
94 95 static int igb_add_intr_handlers(igb_t *);
95 96 static void igb_rem_intr_handlers(igb_t *);
96 97 static void igb_rem_intrs(igb_t *);
97 98 static int igb_enable_intrs(igb_t *);
98 99 static int igb_disable_intrs(igb_t *);
99 100 static void igb_setup_msix_82575(igb_t *);
100 101 static void igb_setup_msix_82576(igb_t *);
101 102 static void igb_setup_msix_82580(igb_t *);
102 103 static uint_t igb_intr_legacy(void *, void *);
103 104 static uint_t igb_intr_msi(void *, void *);
104 105 static uint_t igb_intr_rx(void *, void *);
105 106 static uint_t igb_intr_tx(void *, void *);
106 107 static uint_t igb_intr_tx_other(void *, void *);
107 108 static void igb_intr_rx_work(igb_rx_ring_t *);
108 109 static void igb_intr_tx_work(igb_tx_ring_t *);
109 110 static void igb_intr_link_work(igb_t *);
110 111 static void igb_get_driver_control(struct e1000_hw *);
111 112 static void igb_release_driver_control(struct e1000_hw *);
112 113
113 114 static int igb_attach(dev_info_t *, ddi_attach_cmd_t);
114 115 static int igb_detach(dev_info_t *, ddi_detach_cmd_t);
115 116 static int igb_resume(dev_info_t *);
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116 117 static int igb_suspend(dev_info_t *);
117 118 static int igb_quiesce(dev_info_t *);
118 119 static void igb_unconfigure(dev_info_t *, igb_t *);
119 120 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
120 121 const void *);
121 122 static void igb_fm_init(igb_t *);
122 123 static void igb_fm_fini(igb_t *);
123 124 static void igb_release_multicast(igb_t *);
124 125
125 126 char *igb_priv_props[] = {
127 + "_eee_support",
126 128 "_tx_copy_thresh",
127 129 "_tx_recycle_thresh",
128 130 "_tx_overload_thresh",
129 131 "_tx_resched_thresh",
130 132 "_rx_copy_thresh",
131 133 "_rx_limit_per_intr",
132 134 "_intr_throttling",
133 135 "_adv_pause_cap",
134 136 "_adv_asym_pause_cap",
135 137 NULL
136 138 };
137 139
138 140 static struct cb_ops igb_cb_ops = {
139 141 nulldev, /* cb_open */
140 142 nulldev, /* cb_close */
141 143 nodev, /* cb_strategy */
142 144 nodev, /* cb_print */
143 145 nodev, /* cb_dump */
144 146 nodev, /* cb_read */
145 147 nodev, /* cb_write */
146 148 nodev, /* cb_ioctl */
147 149 nodev, /* cb_devmap */
148 150 nodev, /* cb_mmap */
149 151 nodev, /* cb_segmap */
150 152 nochpoll, /* cb_chpoll */
151 153 ddi_prop_op, /* cb_prop_op */
152 154 NULL, /* cb_stream */
153 155 D_MP | D_HOTPLUG, /* cb_flag */
154 156 CB_REV, /* cb_rev */
155 157 nodev, /* cb_aread */
156 158 nodev /* cb_awrite */
157 159 };
158 160
159 161 static struct dev_ops igb_dev_ops = {
160 162 DEVO_REV, /* devo_rev */
161 163 0, /* devo_refcnt */
162 164 NULL, /* devo_getinfo */
163 165 nulldev, /* devo_identify */
164 166 nulldev, /* devo_probe */
165 167 igb_attach, /* devo_attach */
166 168 igb_detach, /* devo_detach */
167 169 nodev, /* devo_reset */
168 170 &igb_cb_ops, /* devo_cb_ops */
169 171 NULL, /* devo_bus_ops */
170 172 ddi_power, /* devo_power */
171 173 igb_quiesce, /* devo_quiesce */
172 174 };
173 175
174 176 static struct modldrv igb_modldrv = {
175 177 &mod_driverops, /* Type of module. This one is a driver */
176 178 ident, /* Discription string */
177 179 &igb_dev_ops, /* driver ops */
178 180 };
179 181
180 182 static struct modlinkage igb_modlinkage = {
181 183 MODREV_1, &igb_modldrv, NULL
182 184 };
183 185
184 186 /* Access attributes for register mapping */
185 187 ddi_device_acc_attr_t igb_regs_acc_attr = {
186 188 DDI_DEVICE_ATTR_V1,
187 189 DDI_STRUCTURE_LE_ACC,
188 190 DDI_STRICTORDER_ACC,
189 191 DDI_FLAGERR_ACC
190 192 };
191 193
192 194 #define IGB_M_CALLBACK_FLAGS \
193 195 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
194 196
195 197 static mac_callbacks_t igb_m_callbacks = {
196 198 IGB_M_CALLBACK_FLAGS,
197 199 igb_m_stat,
198 200 igb_m_start,
199 201 igb_m_stop,
200 202 igb_m_promisc,
201 203 igb_m_multicst,
202 204 NULL,
203 205 NULL,
204 206 NULL,
205 207 igb_m_ioctl,
206 208 igb_m_getcapab,
207 209 NULL,
208 210 NULL,
209 211 igb_m_setprop,
210 212 igb_m_getprop,
211 213 igb_m_propinfo
212 214 };
213 215
214 216 /*
215 217 * Initialize capabilities of each supported adapter type
216 218 */
217 219 static adapter_info_t igb_82575_cap = {
218 220 /* limits */
219 221 4, /* maximum number of rx queues */
220 222 1, /* minimum number of rx queues */
221 223 4, /* default number of rx queues */
222 224 4, /* maximum number of tx queues */
223 225 1, /* minimum number of tx queues */
224 226 4, /* default number of tx queues */
225 227 65535, /* maximum interrupt throttle rate */
226 228 0, /* minimum interrupt throttle rate */
227 229 200, /* default interrupt throttle rate */
228 230
229 231 /* function pointers */
230 232 igb_enable_adapter_interrupts_82575,
231 233 igb_setup_msix_82575,
232 234
233 235 /* capabilities */
234 236 (IGB_FLAG_HAS_DCA | /* capability flags */
235 237 IGB_FLAG_VMDQ_POOL),
236 238
237 239 0xffc00000 /* mask for RXDCTL register */
238 240 };
239 241
240 242 static adapter_info_t igb_82576_cap = {
241 243 /* limits */
242 244 16, /* maximum number of rx queues */
243 245 1, /* minimum number of rx queues */
244 246 4, /* default number of rx queues */
245 247 16, /* maximum number of tx queues */
246 248 1, /* minimum number of tx queues */
247 249 4, /* default number of tx queues */
248 250 65535, /* maximum interrupt throttle rate */
249 251 0, /* minimum interrupt throttle rate */
250 252 200, /* default interrupt throttle rate */
251 253
252 254 /* function pointers */
253 255 igb_enable_adapter_interrupts_82576,
254 256 igb_setup_msix_82576,
255 257
256 258 /* capabilities */
257 259 (IGB_FLAG_HAS_DCA | /* capability flags */
258 260 IGB_FLAG_VMDQ_POOL |
259 261 IGB_FLAG_NEED_CTX_IDX),
260 262
261 263 0xffe00000 /* mask for RXDCTL register */
262 264 };
263 265
264 266 static adapter_info_t igb_82580_cap = {
265 267 /* limits */
266 268 8, /* maximum number of rx queues */
267 269 1, /* minimum number of rx queues */
268 270 4, /* default number of rx queues */
269 271 8, /* maximum number of tx queues */
270 272 1, /* minimum number of tx queues */
271 273 4, /* default number of tx queues */
272 274 65535, /* maximum interrupt throttle rate */
273 275 0, /* minimum interrupt throttle rate */
274 276 200, /* default interrupt throttle rate */
275 277
276 278 /* function pointers */
277 279 igb_enable_adapter_interrupts_82580,
278 280 igb_setup_msix_82580,
279 281
280 282 /* capabilities */
281 283 (IGB_FLAG_HAS_DCA | /* capability flags */
282 284 IGB_FLAG_VMDQ_POOL |
283 285 IGB_FLAG_NEED_CTX_IDX),
284 286
285 287 0xffe00000 /* mask for RXDCTL register */
286 288 };
287 289
288 290 static adapter_info_t igb_i350_cap = {
289 291 /* limits */
290 292 8, /* maximum number of rx queues */
291 293 1, /* minimum number of rx queues */
292 294 4, /* default number of rx queues */
293 295 8, /* maximum number of tx queues */
294 296 1, /* minimum number of tx queues */
295 297 4, /* default number of tx queues */
296 298 65535, /* maximum interrupt throttle rate */
297 299 0, /* minimum interrupt throttle rate */
298 300 200, /* default interrupt throttle rate */
299 301
300 302 /* function pointers */
301 303 igb_enable_adapter_interrupts_82580,
302 304 igb_setup_msix_82580,
303 305
304 306 /* capabilities */
305 307 (IGB_FLAG_HAS_DCA | /* capability flags */
306 308 IGB_FLAG_VMDQ_POOL |
307 309 IGB_FLAG_NEED_CTX_IDX),
308 310
309 311 0xffe00000 /* mask for RXDCTL register */
310 312 };
311 313
312 314 /*
313 315 * Module Initialization Functions
314 316 */
315 317
316 318 int
317 319 _init(void)
318 320 {
319 321 int status;
320 322
321 323 mac_init_ops(&igb_dev_ops, MODULE_NAME);
322 324
323 325 status = mod_install(&igb_modlinkage);
324 326
325 327 if (status != DDI_SUCCESS) {
326 328 mac_fini_ops(&igb_dev_ops);
327 329 }
328 330
329 331 return (status);
330 332 }
331 333
332 334 int
333 335 _fini(void)
334 336 {
335 337 int status;
336 338
337 339 status = mod_remove(&igb_modlinkage);
338 340
339 341 if (status == DDI_SUCCESS) {
340 342 mac_fini_ops(&igb_dev_ops);
341 343 }
342 344
343 345 return (status);
344 346
345 347 }
346 348
347 349 int
348 350 _info(struct modinfo *modinfop)
349 351 {
350 352 int status;
351 353
352 354 status = mod_info(&igb_modlinkage, modinfop);
353 355
354 356 return (status);
355 357 }
356 358
357 359 /*
358 360 * igb_attach - driver attach
359 361 *
360 362 * This function is the device specific initialization entry
361 363 * point. This entry point is required and must be written.
362 364 * The DDI_ATTACH command must be provided in the attach entry
363 365 * point. When attach() is called with cmd set to DDI_ATTACH,
364 366 * all normal kernel services (such as kmem_alloc(9F)) are
365 367 * available for use by the driver.
366 368 *
367 369 * The attach() function will be called once for each instance
368 370 * of the device on the system with cmd set to DDI_ATTACH.
369 371 * Until attach() succeeds, the only driver entry points which
370 372 * may be called are open(9E) and getinfo(9E).
371 373 */
372 374 static int
373 375 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
374 376 {
375 377 igb_t *igb;
376 378 struct igb_osdep *osdep;
377 379 struct e1000_hw *hw;
378 380 int instance;
379 381
380 382 /*
381 383 * Check the command and perform corresponding operations
382 384 */
383 385 switch (cmd) {
384 386 default:
385 387 return (DDI_FAILURE);
386 388
387 389 case DDI_RESUME:
388 390 return (igb_resume(devinfo));
389 391
390 392 case DDI_ATTACH:
391 393 break;
392 394 }
393 395
394 396 /* Get the device instance */
395 397 instance = ddi_get_instance(devinfo);
396 398
397 399 /* Allocate memory for the instance data structure */
398 400 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP);
399 401
400 402 igb->dip = devinfo;
401 403 igb->instance = instance;
402 404
403 405 hw = &igb->hw;
404 406 osdep = &igb->osdep;
405 407 hw->back = osdep;
406 408 osdep->igb = igb;
407 409
408 410 /* Attach the instance pointer to the dev_info data structure */
409 411 ddi_set_driver_private(devinfo, igb);
410 412
411 413
412 414 /* Initialize for fma support */
413 415 igb->fm_capabilities = igb_get_prop(igb, "fm-capable",
414 416 0, 0x0f,
415 417 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
416 418 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
417 419 igb_fm_init(igb);
418 420 igb->attach_progress |= ATTACH_PROGRESS_FMINIT;
419 421
420 422 /*
421 423 * Map PCI config space registers
422 424 */
423 425 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
424 426 igb_error(igb, "Failed to map PCI configurations");
425 427 goto attach_fail;
426 428 }
427 429 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
428 430
429 431 /*
430 432 * Identify the chipset family
431 433 */
432 434 if (igb_identify_hardware(igb) != IGB_SUCCESS) {
433 435 igb_error(igb, "Failed to identify hardware");
434 436 goto attach_fail;
435 437 }
436 438
437 439 /*
438 440 * Map device registers
439 441 */
440 442 if (igb_regs_map(igb) != IGB_SUCCESS) {
441 443 igb_error(igb, "Failed to map device registers");
442 444 goto attach_fail;
443 445 }
444 446 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
445 447
446 448 /*
447 449 * Initialize driver parameters
448 450 */
449 451 igb_init_properties(igb);
450 452 igb->attach_progress |= ATTACH_PROGRESS_PROPS;
451 453
452 454 /*
453 455 * Allocate interrupts
454 456 */
455 457 if (igb_alloc_intrs(igb) != IGB_SUCCESS) {
456 458 igb_error(igb, "Failed to allocate interrupts");
457 459 goto attach_fail;
458 460 }
459 461 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
460 462
461 463 /*
462 464 * Allocate rx/tx rings based on the ring numbers.
463 465 * The actual numbers of rx/tx rings are decided by the number of
464 466 * allocated interrupt vectors, so we should allocate the rings after
465 467 * interrupts are allocated.
466 468 */
467 469 if (igb_alloc_rings(igb) != IGB_SUCCESS) {
468 470 igb_error(igb, "Failed to allocate rx/tx rings or groups");
469 471 goto attach_fail;
470 472 }
471 473 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
472 474
473 475 /*
474 476 * Add interrupt handlers
475 477 */
476 478 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) {
477 479 igb_error(igb, "Failed to add interrupt handlers");
478 480 goto attach_fail;
479 481 }
480 482 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
481 483
482 484 /*
483 485 * Initialize driver parameters
484 486 */
485 487 if (igb_init_driver_settings(igb) != IGB_SUCCESS) {
486 488 igb_error(igb, "Failed to initialize driver settings");
487 489 goto attach_fail;
488 490 }
489 491
490 492 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) {
491 493 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
492 494 goto attach_fail;
493 495 }
494 496
495 497 /*
496 498 * Initialize mutexes for this device.
497 499 * Do this before enabling the interrupt handler and
498 500 * register the softint to avoid the condition where
499 501 * interrupt handler can try using uninitialized mutex
500 502 */
501 503 igb_init_locks(igb);
502 504 igb->attach_progress |= ATTACH_PROGRESS_LOCKS;
503 505
504 506 /*
505 507 * Initialize the adapter
506 508 */
507 509 if (igb_init(igb) != IGB_SUCCESS) {
508 510 igb_error(igb, "Failed to initialize adapter");
509 511 goto attach_fail;
510 512 }
511 513 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
512 514
513 515 /*
514 516 * Initialize statistics
515 517 */
516 518 if (igb_init_stats(igb) != IGB_SUCCESS) {
517 519 igb_error(igb, "Failed to initialize statistics");
518 520 goto attach_fail;
519 521 }
520 522 igb->attach_progress |= ATTACH_PROGRESS_STATS;
521 523
522 524 /*
523 525 * Register the driver to the MAC
524 526 */
525 527 if (igb_register_mac(igb) != IGB_SUCCESS) {
526 528 igb_error(igb, "Failed to register MAC");
527 529 goto attach_fail;
528 530 }
529 531 igb->attach_progress |= ATTACH_PROGRESS_MAC;
530 532
531 533 /*
532 534 * Now that mutex locks are initialized, and the chip is also
533 535 * initialized, enable interrupts.
534 536 */
535 537 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
536 538 igb_error(igb, "Failed to enable DDI interrupts");
537 539 goto attach_fail;
538 540 }
539 541 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
540 542
541 543 igb_log(igb, "%s", igb_version);
542 544 atomic_or_32(&igb->igb_state, IGB_INITIALIZED);
543 545
544 546 /*
545 547 * Newer models have Energy Efficient Ethernet, let's disable this by
546 548 * default.
547 549 */
548 550 if (igb->hw.mac.type == e1000_i350)
549 551 (void) e1000_set_eee_i350(&igb->hw);
550 552
551 553 return (DDI_SUCCESS);
552 554
553 555 attach_fail:
554 556 igb_unconfigure(devinfo, igb);
555 557 return (DDI_FAILURE);
556 558 }
557 559
558 560 /*
559 561 * igb_detach - driver detach
560 562 *
561 563 * The detach() function is the complement of the attach routine.
562 564 * If cmd is set to DDI_DETACH, detach() is used to remove the
563 565 * state associated with a given instance of a device node
564 566 * prior to the removal of that instance from the system.
565 567 *
566 568 * The detach() function will be called once for each instance
567 569 * of the device for which there has been a successful attach()
568 570 * once there are no longer any opens on the device.
569 571 *
570 572 * Interrupts routine are disabled, All memory allocated by this
571 573 * driver are freed.
572 574 */
573 575 static int
574 576 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
575 577 {
576 578 igb_t *igb;
577 579
578 580 /*
579 581 * Check detach command
580 582 */
581 583 switch (cmd) {
582 584 default:
583 585 return (DDI_FAILURE);
584 586
585 587 case DDI_SUSPEND:
586 588 return (igb_suspend(devinfo));
587 589
588 590 case DDI_DETACH:
589 591 break;
590 592 }
591 593
592 594
593 595 /*
594 596 * Get the pointer to the driver private data structure
595 597 */
596 598 igb = (igb_t *)ddi_get_driver_private(devinfo);
597 599 if (igb == NULL)
598 600 return (DDI_FAILURE);
599 601
600 602 /*
601 603 * Unregister MAC. If failed, we have to fail the detach
602 604 */
603 605 if (mac_unregister(igb->mac_hdl) != 0) {
604 606 igb_error(igb, "Failed to unregister MAC");
605 607 return (DDI_FAILURE);
606 608 }
607 609 igb->attach_progress &= ~ATTACH_PROGRESS_MAC;
608 610
609 611 /*
610 612 * If the device is still running, it needs to be stopped first.
611 613 * This check is necessary because under some specific circumstances,
612 614 * the detach routine can be called without stopping the interface
613 615 * first.
614 616 */
615 617 mutex_enter(&igb->gen_lock);
616 618 if (igb->igb_state & IGB_STARTED) {
617 619 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
618 620 igb_stop(igb, B_TRUE);
619 621 mutex_exit(&igb->gen_lock);
620 622 /* Disable and stop the watchdog timer */
621 623 igb_disable_watchdog_timer(igb);
622 624 } else
623 625 mutex_exit(&igb->gen_lock);
624 626
625 627 /*
626 628 * Check if there are still rx buffers held by the upper layer.
627 629 * If so, fail the detach.
628 630 */
629 631 if (!igb_rx_drain(igb))
630 632 return (DDI_FAILURE);
631 633
632 634 /*
633 635 * Do the remaining unconfigure routines
634 636 */
635 637 igb_unconfigure(devinfo, igb);
636 638
637 639 return (DDI_SUCCESS);
638 640 }
639 641
640 642 /*
641 643 * quiesce(9E) entry point.
642 644 *
643 645 * This function is called when the system is single-threaded at high
644 646 * PIL with preemption disabled. Therefore, this function must not be
645 647 * blocked.
646 648 *
647 649 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
648 650 * DDI_FAILURE indicates an error condition and should almost never happen.
649 651 */
650 652 static int
651 653 igb_quiesce(dev_info_t *devinfo)
652 654 {
653 655 igb_t *igb;
654 656 struct e1000_hw *hw;
655 657
656 658 igb = (igb_t *)ddi_get_driver_private(devinfo);
657 659
658 660 if (igb == NULL)
659 661 return (DDI_FAILURE);
660 662
661 663 hw = &igb->hw;
662 664
663 665 /*
664 666 * Disable the adapter interrupts
665 667 */
666 668 igb_disable_adapter_interrupts(igb);
667 669
668 670 /* Tell firmware driver is no longer in control */
669 671 igb_release_driver_control(hw);
670 672
671 673 /*
672 674 * Reset the chipset
673 675 */
674 676 (void) e1000_reset_hw(hw);
675 677
676 678 /*
677 679 * Reset PHY if possible
678 680 */
679 681 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
680 682 (void) e1000_phy_hw_reset(hw);
681 683
682 684 return (DDI_SUCCESS);
683 685 }
684 686
685 687 /*
686 688 * igb_unconfigure - release all resources held by this instance
687 689 */
688 690 static void
689 691 igb_unconfigure(dev_info_t *devinfo, igb_t *igb)
690 692 {
691 693 /*
692 694 * Disable interrupt
693 695 */
694 696 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
695 697 (void) igb_disable_intrs(igb);
696 698 }
697 699
698 700 /*
699 701 * Unregister MAC
700 702 */
701 703 if (igb->attach_progress & ATTACH_PROGRESS_MAC) {
702 704 (void) mac_unregister(igb->mac_hdl);
703 705 }
704 706
705 707 /*
706 708 * Free statistics
707 709 */
708 710 if (igb->attach_progress & ATTACH_PROGRESS_STATS) {
709 711 kstat_delete((kstat_t *)igb->igb_ks);
710 712 }
711 713
712 714 /*
713 715 * Remove interrupt handlers
714 716 */
715 717 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
716 718 igb_rem_intr_handlers(igb);
717 719 }
718 720
719 721 /*
720 722 * Remove interrupts
721 723 */
722 724 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
723 725 igb_rem_intrs(igb);
724 726 }
725 727
726 728 /*
727 729 * Remove driver properties
728 730 */
729 731 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) {
730 732 (void) ddi_prop_remove_all(devinfo);
731 733 }
732 734
733 735 /*
734 736 * Stop the adapter
735 737 */
736 738 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) {
737 739 mutex_enter(&igb->gen_lock);
738 740 igb_stop_adapter(igb);
739 741 mutex_exit(&igb->gen_lock);
740 742 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
741 743 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED);
742 744 }
743 745
744 746 /*
745 747 * Free multicast table
746 748 */
747 749 igb_release_multicast(igb);
748 750
749 751 /*
750 752 * Free register handle
751 753 */
752 754 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
753 755 if (igb->osdep.reg_handle != NULL)
754 756 ddi_regs_map_free(&igb->osdep.reg_handle);
755 757 }
756 758
757 759 /*
758 760 * Free PCI config handle
759 761 */
760 762 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
761 763 if (igb->osdep.cfg_handle != NULL)
762 764 pci_config_teardown(&igb->osdep.cfg_handle);
763 765 }
764 766
765 767 /*
766 768 * Free locks
767 769 */
768 770 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) {
769 771 igb_destroy_locks(igb);
770 772 }
771 773
772 774 /*
773 775 * Free the rx/tx rings
774 776 */
775 777 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
776 778 igb_free_rings(igb);
777 779 }
778 780
779 781 /*
780 782 * Remove FMA
781 783 */
782 784 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) {
783 785 igb_fm_fini(igb);
784 786 }
785 787
786 788 /*
787 789 * Free the driver data structure
788 790 */
789 791 kmem_free(igb, sizeof (igb_t));
790 792
791 793 ddi_set_driver_private(devinfo, NULL);
792 794 }
793 795
794 796 /*
795 797 * igb_register_mac - Register the driver and its function pointers with
796 798 * the GLD interface
797 799 */
798 800 static int
799 801 igb_register_mac(igb_t *igb)
800 802 {
801 803 struct e1000_hw *hw = &igb->hw;
802 804 mac_register_t *mac;
803 805 int status;
804 806
805 807 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
806 808 return (IGB_FAILURE);
807 809
808 810 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
809 811 mac->m_driver = igb;
810 812 mac->m_dip = igb->dip;
811 813 mac->m_src_addr = hw->mac.addr;
812 814 mac->m_callbacks = &igb_m_callbacks;
813 815 mac->m_min_sdu = 0;
814 816 mac->m_max_sdu = igb->max_frame_size -
815 817 sizeof (struct ether_vlan_header) - ETHERFCSL;
816 818 mac->m_margin = VLAN_TAGSZ;
817 819 mac->m_priv_props = igb_priv_props;
818 820 mac->m_v12n = MAC_VIRT_LEVEL1;
819 821
820 822 status = mac_register(mac, &igb->mac_hdl);
821 823
822 824 mac_free(mac);
823 825
824 826 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE);
825 827 }
826 828
827 829 /*
828 830 * igb_identify_hardware - Identify the type of the chipset
829 831 */
830 832 static int
831 833 igb_identify_hardware(igb_t *igb)
832 834 {
833 835 struct e1000_hw *hw = &igb->hw;
834 836 struct igb_osdep *osdep = &igb->osdep;
835 837
836 838 /*
837 839 * Get the device id
838 840 */
839 841 hw->vendor_id =
840 842 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
841 843 hw->device_id =
842 844 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
843 845 hw->revision_id =
844 846 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
845 847 hw->subsystem_device_id =
846 848 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
847 849 hw->subsystem_vendor_id =
848 850 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
849 851
850 852 /*
851 853 * Set the mac type of the adapter based on the device id
852 854 */
853 855 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
854 856 return (IGB_FAILURE);
855 857 }
856 858
857 859 /*
858 860 * Install adapter capabilities based on mac type
859 861 */
860 862 switch (hw->mac.type) {
861 863 case e1000_82575:
862 864 igb->capab = &igb_82575_cap;
863 865 break;
864 866 case e1000_82576:
865 867 igb->capab = &igb_82576_cap;
866 868 break;
867 869 case e1000_82580:
868 870 igb->capab = &igb_82580_cap;
869 871 break;
870 872 case e1000_i350:
871 873 igb->capab = &igb_i350_cap;
872 874 break;
873 875 default:
874 876 return (IGB_FAILURE);
875 877 }
876 878
877 879 return (IGB_SUCCESS);
878 880 }
879 881
880 882 /*
881 883 * igb_regs_map - Map the device registers
882 884 */
883 885 static int
884 886 igb_regs_map(igb_t *igb)
885 887 {
886 888 dev_info_t *devinfo = igb->dip;
887 889 struct e1000_hw *hw = &igb->hw;
888 890 struct igb_osdep *osdep = &igb->osdep;
889 891 off_t mem_size;
890 892
891 893 /*
892 894 * First get the size of device registers to be mapped.
893 895 */
894 896 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) !=
895 897 DDI_SUCCESS) {
896 898 return (IGB_FAILURE);
897 899 }
898 900
899 901 /*
900 902 * Call ddi_regs_map_setup() to map registers
901 903 */
902 904 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET,
903 905 (caddr_t *)&hw->hw_addr, 0,
904 906 mem_size, &igb_regs_acc_attr,
905 907 &osdep->reg_handle)) != DDI_SUCCESS) {
906 908 return (IGB_FAILURE);
907 909 }
908 910
909 911 return (IGB_SUCCESS);
910 912 }
911 913
912 914 /*
913 915 * igb_init_properties - Initialize driver properties
914 916 */
915 917 static void
916 918 igb_init_properties(igb_t *igb)
917 919 {
918 920 /*
919 921 * Get conf file properties, including link settings
920 922 * jumbo frames, ring number, descriptor number, etc.
921 923 */
922 924 igb_get_conf(igb);
923 925 }
924 926
925 927 /*
926 928 * igb_init_driver_settings - Initialize driver settings
927 929 *
928 930 * The settings include hardware function pointers, bus information,
929 931 * rx/tx rings settings, link state, and any other parameters that
930 932 * need to be setup during driver initialization.
931 933 */
932 934 static int
933 935 igb_init_driver_settings(igb_t *igb)
934 936 {
935 937 struct e1000_hw *hw = &igb->hw;
936 938 igb_rx_ring_t *rx_ring;
937 939 igb_tx_ring_t *tx_ring;
938 940 uint32_t rx_size;
939 941 uint32_t tx_size;
940 942 int i;
941 943
942 944 /*
943 945 * Initialize chipset specific hardware function pointers
944 946 */
945 947 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
946 948 return (IGB_FAILURE);
947 949 }
948 950
949 951 /*
950 952 * Get bus information
951 953 */
952 954 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
953 955 return (IGB_FAILURE);
954 956 }
955 957
956 958 /*
957 959 * Get the system page size
958 960 */
959 961 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1);
960 962
961 963 /*
962 964 * Set rx buffer size
963 965 * The IP header alignment room is counted in the calculation.
964 966 * The rx buffer size is in unit of 1K that is required by the
965 967 * chipset hardware.
966 968 */
967 969 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
968 970 igb->rx_buf_size = ((rx_size >> 10) +
969 971 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
970 972
971 973 /*
972 974 * Set tx buffer size
973 975 */
974 976 tx_size = igb->max_frame_size;
975 977 igb->tx_buf_size = ((tx_size >> 10) +
976 978 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
977 979
978 980 /*
979 981 * Initialize rx/tx rings parameters
980 982 */
981 983 for (i = 0; i < igb->num_rx_rings; i++) {
982 984 rx_ring = &igb->rx_rings[i];
983 985 rx_ring->index = i;
984 986 rx_ring->igb = igb;
985 987 }
986 988
987 989 for (i = 0; i < igb->num_tx_rings; i++) {
988 990 tx_ring = &igb->tx_rings[i];
989 991 tx_ring->index = i;
990 992 tx_ring->igb = igb;
991 993 if (igb->tx_head_wb_enable)
992 994 tx_ring->tx_recycle = igb_tx_recycle_head_wb;
993 995 else
994 996 tx_ring->tx_recycle = igb_tx_recycle_legacy;
995 997
996 998 tx_ring->ring_size = igb->tx_ring_size;
997 999 tx_ring->free_list_size = igb->tx_ring_size +
998 1000 (igb->tx_ring_size >> 1);
999 1001 }
1000 1002
1001 1003 /*
1002 1004 * Initialize values of interrupt throttling rates
1003 1005 */
1004 1006 for (i = 1; i < MAX_NUM_EITR; i++)
1005 1007 igb->intr_throttling[i] = igb->intr_throttling[0];
1006 1008
1007 1009 /*
1008 1010 * The initial link state should be "unknown"
1009 1011 */
1010 1012 igb->link_state = LINK_STATE_UNKNOWN;
1011 1013
1012 1014 return (IGB_SUCCESS);
1013 1015 }
1014 1016
1015 1017 /*
1016 1018 * igb_init_locks - Initialize locks
1017 1019 */
1018 1020 static void
1019 1021 igb_init_locks(igb_t *igb)
1020 1022 {
1021 1023 igb_rx_ring_t *rx_ring;
1022 1024 igb_tx_ring_t *tx_ring;
1023 1025 int i;
1024 1026
1025 1027 for (i = 0; i < igb->num_rx_rings; i++) {
1026 1028 rx_ring = &igb->rx_rings[i];
1027 1029 mutex_init(&rx_ring->rx_lock, NULL,
1028 1030 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1029 1031 }
1030 1032
1031 1033 for (i = 0; i < igb->num_tx_rings; i++) {
1032 1034 tx_ring = &igb->tx_rings[i];
1033 1035 mutex_init(&tx_ring->tx_lock, NULL,
1034 1036 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1035 1037 mutex_init(&tx_ring->recycle_lock, NULL,
1036 1038 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1037 1039 mutex_init(&tx_ring->tcb_head_lock, NULL,
1038 1040 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1039 1041 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1040 1042 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1041 1043 }
1042 1044
1043 1045 mutex_init(&igb->gen_lock, NULL,
1044 1046 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1045 1047
1046 1048 mutex_init(&igb->watchdog_lock, NULL,
1047 1049 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1048 1050
1049 1051 mutex_init(&igb->link_lock, NULL,
1050 1052 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1051 1053 }
1052 1054
1053 1055 /*
1054 1056 * igb_destroy_locks - Destroy locks
1055 1057 */
1056 1058 static void
1057 1059 igb_destroy_locks(igb_t *igb)
1058 1060 {
1059 1061 igb_rx_ring_t *rx_ring;
1060 1062 igb_tx_ring_t *tx_ring;
1061 1063 int i;
1062 1064
1063 1065 for (i = 0; i < igb->num_rx_rings; i++) {
1064 1066 rx_ring = &igb->rx_rings[i];
1065 1067 mutex_destroy(&rx_ring->rx_lock);
1066 1068 }
1067 1069
1068 1070 for (i = 0; i < igb->num_tx_rings; i++) {
1069 1071 tx_ring = &igb->tx_rings[i];
1070 1072 mutex_destroy(&tx_ring->tx_lock);
1071 1073 mutex_destroy(&tx_ring->recycle_lock);
1072 1074 mutex_destroy(&tx_ring->tcb_head_lock);
1073 1075 mutex_destroy(&tx_ring->tcb_tail_lock);
1074 1076 }
1075 1077
1076 1078 mutex_destroy(&igb->gen_lock);
1077 1079 mutex_destroy(&igb->watchdog_lock);
1078 1080 mutex_destroy(&igb->link_lock);
1079 1081 }
1080 1082
1081 1083 static int
1082 1084 igb_resume(dev_info_t *devinfo)
1083 1085 {
1084 1086 igb_t *igb;
1085 1087
1086 1088 igb = (igb_t *)ddi_get_driver_private(devinfo);
1087 1089 if (igb == NULL)
1088 1090 return (DDI_FAILURE);
1089 1091
1090 1092 mutex_enter(&igb->gen_lock);
1091 1093
1092 1094 /*
1093 1095 * Enable interrupts
1094 1096 */
1095 1097 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1096 1098 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
1097 1099 igb_error(igb, "Failed to enable DDI interrupts");
1098 1100 mutex_exit(&igb->gen_lock);
1099 1101 return (DDI_FAILURE);
1100 1102 }
1101 1103 }
1102 1104
1103 1105 if (igb->igb_state & IGB_STARTED) {
1104 1106 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) {
1105 1107 mutex_exit(&igb->gen_lock);
1106 1108 return (DDI_FAILURE);
1107 1109 }
1108 1110
1109 1111 /*
1110 1112 * Enable and start the watchdog timer
1111 1113 */
1112 1114 igb_enable_watchdog_timer(igb);
1113 1115 }
1114 1116
1115 1117 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED);
1116 1118
1117 1119 mutex_exit(&igb->gen_lock);
1118 1120
1119 1121 return (DDI_SUCCESS);
1120 1122 }
1121 1123
1122 1124 static int
1123 1125 igb_suspend(dev_info_t *devinfo)
1124 1126 {
1125 1127 igb_t *igb;
1126 1128
1127 1129 igb = (igb_t *)ddi_get_driver_private(devinfo);
1128 1130 if (igb == NULL)
1129 1131 return (DDI_FAILURE);
1130 1132
1131 1133 mutex_enter(&igb->gen_lock);
1132 1134
1133 1135 atomic_or_32(&igb->igb_state, IGB_SUSPENDED);
1134 1136
1135 1137 /*
1136 1138 * Disable interrupts
1137 1139 */
1138 1140 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1139 1141 (void) igb_disable_intrs(igb);
1140 1142 }
1141 1143
1142 1144 if (!(igb->igb_state & IGB_STARTED)) {
1143 1145 mutex_exit(&igb->gen_lock);
1144 1146 return (DDI_SUCCESS);
1145 1147 }
1146 1148
1147 1149 igb_stop(igb, B_FALSE);
1148 1150
1149 1151 mutex_exit(&igb->gen_lock);
1150 1152
1151 1153 /*
1152 1154 * Disable and stop the watchdog timer
1153 1155 */
1154 1156 igb_disable_watchdog_timer(igb);
1155 1157
1156 1158 return (DDI_SUCCESS);
1157 1159 }
1158 1160
1159 1161 static int
1160 1162 igb_init(igb_t *igb)
1161 1163 {
1162 1164 mutex_enter(&igb->gen_lock);
1163 1165
1164 1166 /*
1165 1167 * Initilize the adapter
1166 1168 */
1167 1169 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1168 1170 mutex_exit(&igb->gen_lock);
1169 1171 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1170 1172 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1171 1173 return (IGB_FAILURE);
1172 1174 }
1173 1175
1174 1176 mutex_exit(&igb->gen_lock);
1175 1177
1176 1178 return (IGB_SUCCESS);
1177 1179 }
1178 1180
1179 1181 /*
1180 1182 * igb_init_mac_address - Initialize the default MAC address
1181 1183 *
1182 1184 * On success, the MAC address is entered in the igb->hw.mac.addr
1183 1185 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive
1184 1186 * address register.
1185 1187 *
1186 1188 * Important side effects:
1187 1189 * 1. adapter is reset - this is required to put it in a known state.
1188 1190 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where
1189 1191 * MAC address and all default settings are stored, so a valid checksum
1190 1192 * is required.
1191 1193 */
1192 1194 static int
1193 1195 igb_init_mac_address(igb_t *igb)
1194 1196 {
1195 1197 struct e1000_hw *hw = &igb->hw;
1196 1198
1197 1199 ASSERT(mutex_owned(&igb->gen_lock));
1198 1200
1199 1201 /*
1200 1202 * Reset chipset to put the hardware in a known state
1201 1203 * before we try to get MAC address from NVM.
1202 1204 */
1203 1205 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1204 1206 igb_error(igb, "Adapter reset failed.");
1205 1207 goto init_mac_fail;
1206 1208 }
1207 1209
1208 1210 /*
1209 1211 * NVM validation
1210 1212 */
1211 1213 if (e1000_validate_nvm_checksum(hw) < 0) {
1212 1214 /*
1213 1215 * Some PCI-E parts fail the first check due to
1214 1216 * the link being in sleep state. Call it again,
1215 1217 * if it fails a second time its a real issue.
1216 1218 */
1217 1219 if (e1000_validate_nvm_checksum(hw) < 0) {
1218 1220 igb_error(igb,
1219 1221 "Invalid NVM checksum. Please contact "
1220 1222 "the vendor to update the NVM.");
1221 1223 goto init_mac_fail;
1222 1224 }
1223 1225 }
1224 1226
1225 1227 /*
1226 1228 * Get the mac address
1227 1229 * This function should handle SPARC case correctly.
1228 1230 */
1229 1231 if (!igb_find_mac_address(igb)) {
1230 1232 igb_error(igb, "Failed to get the mac address");
1231 1233 goto init_mac_fail;
1232 1234 }
1233 1235
1234 1236 /* Validate mac address */
1235 1237 if (!is_valid_mac_addr(hw->mac.addr)) {
1236 1238 igb_error(igb, "Invalid mac address");
1237 1239 goto init_mac_fail;
1238 1240 }
1239 1241
1240 1242 return (IGB_SUCCESS);
1241 1243
1242 1244 init_mac_fail:
1243 1245 return (IGB_FAILURE);
1244 1246 }
1245 1247
1246 1248 /*
1247 1249 * igb_init_adapter - Initialize the adapter
1248 1250 */
1249 1251 static int
1250 1252 igb_init_adapter(igb_t *igb)
1251 1253 {
1252 1254 struct e1000_hw *hw = &igb->hw;
1253 1255 uint32_t pba;
1254 1256 uint32_t high_water;
1255 1257 int i;
1256 1258
1257 1259 ASSERT(mutex_owned(&igb->gen_lock));
1258 1260
1259 1261 /*
1260 1262 * In order to obtain the default MAC address, this will reset the
1261 1263 * adapter and validate the NVM that the address and many other
1262 1264 * default settings come from.
1263 1265 */
1264 1266 if (igb_init_mac_address(igb) != IGB_SUCCESS) {
1265 1267 igb_error(igb, "Failed to initialize MAC address");
1266 1268 goto init_adapter_fail;
1267 1269 }
1268 1270
1269 1271 /*
1270 1272 * Setup flow control
1271 1273 *
1272 1274 * These parameters set thresholds for the adapter's generation(Tx)
1273 1275 * and response(Rx) to Ethernet PAUSE frames. These are just threshold
1274 1276 * settings. Flow control is enabled or disabled in the configuration
1275 1277 * file.
1276 1278 * High-water mark is set down from the top of the rx fifo (not
1277 1279 * sensitive to max_frame_size) and low-water is set just below
1278 1280 * high-water mark.
1279 1281 * The high water mark must be low enough to fit one full frame above
1280 1282 * it in the rx FIFO. Should be the lower of:
1281 1283 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full
1282 1284 * frame.
1283 1285 */
1284 1286 /*
1285 1287 * The default setting of PBA is correct for 82575 and other supported
1286 1288 * adapters do not have the E1000_PBA register, so PBA value is only
1287 1289 * used for calculation here and is never written to the adapter.
1288 1290 */
1289 1291 if (hw->mac.type == e1000_82575) {
1290 1292 pba = E1000_PBA_34K;
1291 1293 } else {
1292 1294 pba = E1000_PBA_64K;
1293 1295 }
1294 1296
1295 1297 high_water = min(((pba << 10) * 9 / 10),
1296 1298 ((pba << 10) - igb->max_frame_size));
1297 1299
1298 1300 if (hw->mac.type == e1000_82575) {
1299 1301 /* 8-byte granularity */
1300 1302 hw->fc.high_water = high_water & 0xFFF8;
1301 1303 hw->fc.low_water = hw->fc.high_water - 8;
1302 1304 } else {
1303 1305 /* 16-byte granularity */
1304 1306 hw->fc.high_water = high_water & 0xFFF0;
1305 1307 hw->fc.low_water = hw->fc.high_water - 16;
1306 1308 }
1307 1309
1308 1310 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1309 1311 hw->fc.send_xon = B_TRUE;
1310 1312
1311 1313 (void) e1000_validate_mdi_setting(hw);
1312 1314
1313 1315 /*
1314 1316 * Reset the chipset hardware the second time to put PBA settings
1315 1317 * into effect.
1316 1318 */
1317 1319 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1318 1320 igb_error(igb, "Second reset failed");
1319 1321 goto init_adapter_fail;
1320 1322 }
1321 1323
1322 1324 /*
1323 1325 * Don't wait for auto-negotiation to complete
1324 1326 */
1325 1327 hw->phy.autoneg_wait_to_complete = B_FALSE;
1326 1328
1327 1329 /*
1328 1330 * Copper options
1329 1331 */
1330 1332 if (hw->phy.media_type == e1000_media_type_copper) {
1331 1333 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1332 1334 hw->phy.disable_polarity_correction = B_FALSE;
1333 1335 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
1334 1336 }
1335 1337
1336 1338 /*
1337 1339 * Initialize link settings
1338 1340 */
1339 1341 (void) igb_setup_link(igb, B_FALSE);
1340 1342
1341 1343 /*
1342 1344 * Configure/Initialize hardware
1343 1345 */
1344 1346 if (e1000_init_hw(hw) != E1000_SUCCESS) {
1345 1347 igb_error(igb, "Failed to initialize hardware");
1346 1348 goto init_adapter_fail;
1347 1349 }
1348 1350
1349 1351 /*
1350 1352 * Start the link setup timer
1351 1353 */
1352 1354 igb_start_link_timer(igb);
1353 1355
1354 1356 /*
1355 1357 * Disable wakeup control by default
1356 1358 */
1357 1359 E1000_WRITE_REG(hw, E1000_WUC, 0);
1358 1360
1359 1361 /*
1360 1362 * Record phy info in hw struct
1361 1363 */
1362 1364 (void) e1000_get_phy_info(hw);
1363 1365
1364 1366 /*
1365 1367 * Make sure driver has control
1366 1368 */
1367 1369 igb_get_driver_control(hw);
1368 1370
1369 1371 /*
1370 1372 * Restore LED settings to the default from EEPROM
1371 1373 * to meet the standard for Sun platforms.
1372 1374 */
1373 1375 (void) e1000_cleanup_led(hw);
1374 1376
1375 1377 /*
1376 1378 * Setup MSI-X interrupts
1377 1379 */
1378 1380 if (igb->intr_type == DDI_INTR_TYPE_MSIX)
1379 1381 igb->capab->setup_msix(igb);
1380 1382
1381 1383 /*
1382 1384 * Initialize unicast addresses.
1383 1385 */
1384 1386 igb_init_unicst(igb);
1385 1387
1386 1388 /*
1387 1389 * Setup and initialize the mctable structures.
1388 1390 */
1389 1391 igb_setup_multicst(igb);
1390 1392
1391 1393 /*
1392 1394 * Set interrupt throttling rate
1393 1395 */
1394 1396 for (i = 0; i < igb->intr_cnt; i++)
1395 1397 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]);
1396 1398
1397 1399 /*
1398 1400 * Save the state of the phy
1399 1401 */
1400 1402 igb_get_phy_state(igb);
1401 1403
1402 1404 igb_param_sync(igb);
1403 1405
1404 1406 return (IGB_SUCCESS);
1405 1407
1406 1408 init_adapter_fail:
1407 1409 /*
1408 1410 * Reset PHY if possible
1409 1411 */
1410 1412 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
1411 1413 (void) e1000_phy_hw_reset(hw);
1412 1414
1413 1415 return (IGB_FAILURE);
1414 1416 }
1415 1417
1416 1418 /*
1417 1419 * igb_stop_adapter - Stop the adapter
1418 1420 */
1419 1421 static void
1420 1422 igb_stop_adapter(igb_t *igb)
1421 1423 {
1422 1424 struct e1000_hw *hw = &igb->hw;
1423 1425
1424 1426 ASSERT(mutex_owned(&igb->gen_lock));
1425 1427
1426 1428 /* Stop the link setup timer */
1427 1429 igb_stop_link_timer(igb);
1428 1430
1429 1431 /* Tell firmware driver is no longer in control */
1430 1432 igb_release_driver_control(hw);
1431 1433
1432 1434 /*
1433 1435 * Reset the chipset
1434 1436 */
1435 1437 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1436 1438 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1437 1439 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1438 1440 }
1439 1441
1440 1442 /*
1441 1443 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient
1442 1444 */
1443 1445 }
1444 1446
1445 1447 /*
1446 1448 * igb_reset - Reset the chipset and restart the driver.
1447 1449 *
1448 1450 * It involves stopping and re-starting the chipset,
1449 1451 * and re-configuring the rx/tx rings.
1450 1452 */
1451 1453 static int
1452 1454 igb_reset(igb_t *igb)
1453 1455 {
1454 1456 int i;
1455 1457
1456 1458 mutex_enter(&igb->gen_lock);
1457 1459
1458 1460 ASSERT(igb->igb_state & IGB_STARTED);
1459 1461 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
1460 1462
1461 1463 /*
1462 1464 * Disable the adapter interrupts to stop any rx/tx activities
1463 1465 * before draining pending data and resetting hardware.
1464 1466 */
1465 1467 igb_disable_adapter_interrupts(igb);
1466 1468
1467 1469 /*
1468 1470 * Drain the pending transmit packets
1469 1471 */
1470 1472 (void) igb_tx_drain(igb);
1471 1473
1472 1474 for (i = 0; i < igb->num_rx_rings; i++)
1473 1475 mutex_enter(&igb->rx_rings[i].rx_lock);
1474 1476 for (i = 0; i < igb->num_tx_rings; i++)
1475 1477 mutex_enter(&igb->tx_rings[i].tx_lock);
1476 1478
1477 1479 /*
1478 1480 * Stop the adapter
1479 1481 */
1480 1482 igb_stop_adapter(igb);
1481 1483
1482 1484 /*
1483 1485 * Clean the pending tx data/resources
1484 1486 */
1485 1487 igb_tx_clean(igb);
1486 1488
1487 1489 /*
1488 1490 * Start the adapter
1489 1491 */
1490 1492 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1491 1493 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1492 1494 goto reset_failure;
1493 1495 }
1494 1496
1495 1497 /*
1496 1498 * Setup the rx/tx rings
1497 1499 */
1498 1500 igb->tx_ring_init = B_FALSE;
1499 1501 igb_setup_rings(igb);
1500 1502
1501 1503 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL));
1502 1504
1503 1505 /*
1504 1506 * Enable adapter interrupts
1505 1507 * The interrupts must be enabled after the driver state is START
1506 1508 */
1507 1509 igb->capab->enable_intr(igb);
1508 1510
1509 1511 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1510 1512 goto reset_failure;
1511 1513
1512 1514 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1513 1515 goto reset_failure;
1514 1516
1515 1517 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1516 1518 mutex_exit(&igb->tx_rings[i].tx_lock);
1517 1519 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1518 1520 mutex_exit(&igb->rx_rings[i].rx_lock);
1519 1521
1520 1522 atomic_or_32(&igb->igb_state, IGB_STARTED);
1521 1523
1522 1524 mutex_exit(&igb->gen_lock);
1523 1525
1524 1526 return (IGB_SUCCESS);
1525 1527
1526 1528 reset_failure:
1527 1529 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1528 1530 mutex_exit(&igb->tx_rings[i].tx_lock);
1529 1531 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1530 1532 mutex_exit(&igb->rx_rings[i].rx_lock);
1531 1533
1532 1534 mutex_exit(&igb->gen_lock);
1533 1535
1534 1536 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1535 1537
1536 1538 return (IGB_FAILURE);
1537 1539 }
1538 1540
1539 1541 /*
1540 1542 * igb_tx_clean - Clean the pending transmit packets and DMA resources
1541 1543 */
1542 1544 static void
1543 1545 igb_tx_clean(igb_t *igb)
1544 1546 {
1545 1547 igb_tx_ring_t *tx_ring;
1546 1548 tx_control_block_t *tcb;
1547 1549 link_list_t pending_list;
1548 1550 uint32_t desc_num;
1549 1551 int i, j;
1550 1552
1551 1553 LINK_LIST_INIT(&pending_list);
1552 1554
1553 1555 for (i = 0; i < igb->num_tx_rings; i++) {
1554 1556 tx_ring = &igb->tx_rings[i];
1555 1557
1556 1558 mutex_enter(&tx_ring->recycle_lock);
1557 1559
1558 1560 /*
1559 1561 * Clean the pending tx data - the pending packets in the
1560 1562 * work_list that have no chances to be transmitted again.
1561 1563 *
1562 1564 * We must ensure the chipset is stopped or the link is down
1563 1565 * before cleaning the transmit packets.
1564 1566 */
1565 1567 desc_num = 0;
1566 1568 for (j = 0; j < tx_ring->ring_size; j++) {
1567 1569 tcb = tx_ring->work_list[j];
1568 1570 if (tcb != NULL) {
1569 1571 desc_num += tcb->desc_num;
1570 1572
1571 1573 tx_ring->work_list[j] = NULL;
1572 1574
1573 1575 igb_free_tcb(tcb);
1574 1576
1575 1577 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1576 1578 }
1577 1579 }
1578 1580
1579 1581 if (desc_num > 0) {
1580 1582 atomic_add_32(&tx_ring->tbd_free, desc_num);
1581 1583 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1582 1584
1583 1585 /*
1584 1586 * Reset the head and tail pointers of the tbd ring;
1585 1587 * Reset the head write-back if it is enabled.
1586 1588 */
1587 1589 tx_ring->tbd_head = 0;
1588 1590 tx_ring->tbd_tail = 0;
1589 1591 if (igb->tx_head_wb_enable)
1590 1592 *tx_ring->tbd_head_wb = 0;
1591 1593
1592 1594 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0);
1593 1595 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0);
1594 1596 }
1595 1597
1596 1598 mutex_exit(&tx_ring->recycle_lock);
1597 1599
1598 1600 /*
1599 1601 * Add the tx control blocks in the pending list to
1600 1602 * the free list.
1601 1603 */
1602 1604 igb_put_free_list(tx_ring, &pending_list);
1603 1605 }
1604 1606 }
1605 1607
1606 1608 /*
1607 1609 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted
1608 1610 */
1609 1611 static boolean_t
1610 1612 igb_tx_drain(igb_t *igb)
1611 1613 {
1612 1614 igb_tx_ring_t *tx_ring;
1613 1615 boolean_t done;
1614 1616 int i, j;
1615 1617
1616 1618 /*
1617 1619 * Wait for a specific time to allow pending tx packets
1618 1620 * to be transmitted.
1619 1621 *
1620 1622 * Check the counter tbd_free to see if transmission is done.
1621 1623 * No lock protection is needed here.
1622 1624 *
1623 1625 * Return B_TRUE if all pending packets have been transmitted;
1624 1626 * Otherwise return B_FALSE;
1625 1627 */
1626 1628 for (i = 0; i < TX_DRAIN_TIME; i++) {
1627 1629
1628 1630 done = B_TRUE;
1629 1631 for (j = 0; j < igb->num_tx_rings; j++) {
1630 1632 tx_ring = &igb->tx_rings[j];
1631 1633 done = done &&
1632 1634 (tx_ring->tbd_free == tx_ring->ring_size);
1633 1635 }
1634 1636
1635 1637 if (done)
1636 1638 break;
1637 1639
1638 1640 msec_delay(1);
1639 1641 }
1640 1642
1641 1643 return (done);
1642 1644 }
1643 1645
1644 1646 /*
1645 1647 * igb_rx_drain - Wait for all rx buffers to be released by upper layer
1646 1648 */
1647 1649 static boolean_t
1648 1650 igb_rx_drain(igb_t *igb)
1649 1651 {
1650 1652 boolean_t done;
1651 1653 int i;
1652 1654
1653 1655 /*
1654 1656 * Polling the rx free list to check if those rx buffers held by
1655 1657 * the upper layer are released.
1656 1658 *
1657 1659 * Check the counter rcb_free to see if all pending buffers are
1658 1660 * released. No lock protection is needed here.
1659 1661 *
1660 1662 * Return B_TRUE if all pending buffers have been released;
1661 1663 * Otherwise return B_FALSE;
1662 1664 */
1663 1665 for (i = 0; i < RX_DRAIN_TIME; i++) {
1664 1666 done = (igb->rcb_pending == 0);
1665 1667
1666 1668 if (done)
1667 1669 break;
1668 1670
1669 1671 msec_delay(1);
1670 1672 }
1671 1673
1672 1674 return (done);
1673 1675 }
1674 1676
1675 1677 /*
1676 1678 * igb_start - Start the driver/chipset
1677 1679 */
1678 1680 int
1679 1681 igb_start(igb_t *igb, boolean_t alloc_buffer)
1680 1682 {
1681 1683 int i;
1682 1684
1683 1685 ASSERT(mutex_owned(&igb->gen_lock));
1684 1686
1685 1687 if (alloc_buffer) {
1686 1688 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) {
1687 1689 igb_error(igb,
1688 1690 "Failed to allocate software receive rings");
1689 1691 return (IGB_FAILURE);
1690 1692 }
1691 1693
1692 1694 /* Allocate buffers for all the rx/tx rings */
1693 1695 if (igb_alloc_dma(igb) != IGB_SUCCESS) {
1694 1696 igb_error(igb, "Failed to allocate DMA resource");
1695 1697 return (IGB_FAILURE);
1696 1698 }
1697 1699
1698 1700 igb->tx_ring_init = B_TRUE;
1699 1701 } else {
1700 1702 igb->tx_ring_init = B_FALSE;
1701 1703 }
1702 1704
1703 1705 for (i = 0; i < igb->num_rx_rings; i++)
1704 1706 mutex_enter(&igb->rx_rings[i].rx_lock);
1705 1707 for (i = 0; i < igb->num_tx_rings; i++)
1706 1708 mutex_enter(&igb->tx_rings[i].tx_lock);
1707 1709
1708 1710 /*
1709 1711 * Start the adapter
1710 1712 */
1711 1713 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) {
1712 1714 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1713 1715 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1714 1716 goto start_failure;
1715 1717 }
1716 1718 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
1717 1719 }
1718 1720
1719 1721 /*
1720 1722 * Setup the rx/tx rings
1721 1723 */
1722 1724 igb_setup_rings(igb);
1723 1725
1724 1726 /*
1725 1727 * Enable adapter interrupts
1726 1728 * The interrupts must be enabled after the driver state is START
1727 1729 */
1728 1730 igb->capab->enable_intr(igb);
1729 1731
1730 1732 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1731 1733 goto start_failure;
1732 1734
1733 1735 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1734 1736 goto start_failure;
1735 1737
1736 1738 if (igb->hw.mac.type == e1000_i350)
1737 1739 (void) e1000_set_eee_i350(&igb->hw);
1738 1740
1739 1741 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1740 1742 mutex_exit(&igb->tx_rings[i].tx_lock);
1741 1743 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1742 1744 mutex_exit(&igb->rx_rings[i].rx_lock);
1743 1745
1744 1746 return (IGB_SUCCESS);
1745 1747
1746 1748 start_failure:
1747 1749 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1748 1750 mutex_exit(&igb->tx_rings[i].tx_lock);
1749 1751 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1750 1752 mutex_exit(&igb->rx_rings[i].rx_lock);
1751 1753
1752 1754 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1753 1755
1754 1756 return (IGB_FAILURE);
1755 1757 }
1756 1758
1757 1759 /*
1758 1760 * igb_stop - Stop the driver/chipset
1759 1761 */
1760 1762 void
1761 1763 igb_stop(igb_t *igb, boolean_t free_buffer)
1762 1764 {
1763 1765 int i;
1764 1766
1765 1767 ASSERT(mutex_owned(&igb->gen_lock));
1766 1768
1767 1769 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER;
1768 1770
1769 1771 /*
1770 1772 * Disable the adapter interrupts
1771 1773 */
1772 1774 igb_disable_adapter_interrupts(igb);
1773 1775
1774 1776 /*
1775 1777 * Drain the pending tx packets
1776 1778 */
1777 1779 (void) igb_tx_drain(igb);
1778 1780
1779 1781 for (i = 0; i < igb->num_rx_rings; i++)
1780 1782 mutex_enter(&igb->rx_rings[i].rx_lock);
1781 1783 for (i = 0; i < igb->num_tx_rings; i++)
1782 1784 mutex_enter(&igb->tx_rings[i].tx_lock);
1783 1785
1784 1786 /*
1785 1787 * Stop the adapter
1786 1788 */
1787 1789 igb_stop_adapter(igb);
1788 1790
1789 1791 /*
1790 1792 * Clean the pending tx data/resources
1791 1793 */
1792 1794 igb_tx_clean(igb);
1793 1795
1794 1796 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1795 1797 mutex_exit(&igb->tx_rings[i].tx_lock);
1796 1798 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1797 1799 mutex_exit(&igb->rx_rings[i].rx_lock);
1798 1800
1799 1801 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1800 1802 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1801 1803
1802 1804 if (igb->link_state == LINK_STATE_UP) {
1803 1805 igb->link_state = LINK_STATE_UNKNOWN;
1804 1806 mac_link_update(igb->mac_hdl, igb->link_state);
1805 1807 }
1806 1808
1807 1809 if (free_buffer) {
1808 1810 /*
1809 1811 * Release the DMA/memory resources of rx/tx rings
1810 1812 */
1811 1813 igb_free_dma(igb);
1812 1814 igb_free_rx_data(igb);
1813 1815 }
1814 1816 }
1815 1817
1816 1818 /*
1817 1819 * igb_alloc_rings - Allocate memory space for rx/tx rings
1818 1820 */
1819 1821 static int
1820 1822 igb_alloc_rings(igb_t *igb)
1821 1823 {
1822 1824 /*
1823 1825 * Allocate memory space for rx rings
1824 1826 */
1825 1827 igb->rx_rings = kmem_zalloc(
1826 1828 sizeof (igb_rx_ring_t) * igb->num_rx_rings,
1827 1829 KM_NOSLEEP);
1828 1830
1829 1831 if (igb->rx_rings == NULL) {
1830 1832 return (IGB_FAILURE);
1831 1833 }
1832 1834
1833 1835 /*
1834 1836 * Allocate memory space for tx rings
1835 1837 */
1836 1838 igb->tx_rings = kmem_zalloc(
1837 1839 sizeof (igb_tx_ring_t) * igb->num_tx_rings,
1838 1840 KM_NOSLEEP);
1839 1841
1840 1842 if (igb->tx_rings == NULL) {
1841 1843 kmem_free(igb->rx_rings,
1842 1844 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1843 1845 igb->rx_rings = NULL;
1844 1846 return (IGB_FAILURE);
1845 1847 }
1846 1848
1847 1849 /*
1848 1850 * Allocate memory space for rx ring groups
1849 1851 */
1850 1852 igb->rx_groups = kmem_zalloc(
1851 1853 sizeof (igb_rx_group_t) * igb->num_rx_groups,
1852 1854 KM_NOSLEEP);
1853 1855
1854 1856 if (igb->rx_groups == NULL) {
1855 1857 kmem_free(igb->rx_rings,
1856 1858 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1857 1859 kmem_free(igb->tx_rings,
1858 1860 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1859 1861 igb->rx_rings = NULL;
1860 1862 igb->tx_rings = NULL;
1861 1863 return (IGB_FAILURE);
1862 1864 }
1863 1865
1864 1866 return (IGB_SUCCESS);
1865 1867 }
1866 1868
1867 1869 /*
1868 1870 * igb_free_rings - Free the memory space of rx/tx rings.
1869 1871 */
1870 1872 static void
1871 1873 igb_free_rings(igb_t *igb)
1872 1874 {
1873 1875 if (igb->rx_rings != NULL) {
1874 1876 kmem_free(igb->rx_rings,
1875 1877 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1876 1878 igb->rx_rings = NULL;
1877 1879 }
1878 1880
1879 1881 if (igb->tx_rings != NULL) {
1880 1882 kmem_free(igb->tx_rings,
1881 1883 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1882 1884 igb->tx_rings = NULL;
1883 1885 }
1884 1886
1885 1887 if (igb->rx_groups != NULL) {
1886 1888 kmem_free(igb->rx_groups,
1887 1889 sizeof (igb_rx_group_t) * igb->num_rx_groups);
1888 1890 igb->rx_groups = NULL;
1889 1891 }
1890 1892 }
1891 1893
1892 1894 static int
1893 1895 igb_alloc_rx_data(igb_t *igb)
1894 1896 {
1895 1897 igb_rx_ring_t *rx_ring;
1896 1898 int i;
1897 1899
1898 1900 for (i = 0; i < igb->num_rx_rings; i++) {
1899 1901 rx_ring = &igb->rx_rings[i];
1900 1902 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS)
1901 1903 goto alloc_rx_rings_failure;
1902 1904 }
1903 1905 return (IGB_SUCCESS);
1904 1906
1905 1907 alloc_rx_rings_failure:
1906 1908 igb_free_rx_data(igb);
1907 1909 return (IGB_FAILURE);
1908 1910 }
1909 1911
1910 1912 static void
1911 1913 igb_free_rx_data(igb_t *igb)
1912 1914 {
1913 1915 igb_rx_ring_t *rx_ring;
1914 1916 igb_rx_data_t *rx_data;
1915 1917 int i;
1916 1918
1917 1919 for (i = 0; i < igb->num_rx_rings; i++) {
1918 1920 rx_ring = &igb->rx_rings[i];
1919 1921
1920 1922 mutex_enter(&igb->rx_pending_lock);
1921 1923 rx_data = rx_ring->rx_data;
1922 1924
1923 1925 if (rx_data != NULL) {
1924 1926 rx_data->flag |= IGB_RX_STOPPED;
1925 1927
1926 1928 if (rx_data->rcb_pending == 0) {
1927 1929 igb_free_rx_ring_data(rx_data);
1928 1930 rx_ring->rx_data = NULL;
1929 1931 }
1930 1932 }
1931 1933
1932 1934 mutex_exit(&igb->rx_pending_lock);
1933 1935 }
1934 1936 }
1935 1937
1936 1938 /*
1937 1939 * igb_setup_rings - Setup rx/tx rings
1938 1940 */
1939 1941 static void
1940 1942 igb_setup_rings(igb_t *igb)
1941 1943 {
1942 1944 /*
1943 1945 * Setup the rx/tx rings, including the following:
1944 1946 *
1945 1947 * 1. Setup the descriptor ring and the control block buffers;
1946 1948 * 2. Initialize necessary registers for receive/transmit;
1947 1949 * 3. Initialize software pointers/parameters for receive/transmit;
1948 1950 */
1949 1951 igb_setup_rx(igb);
1950 1952
1951 1953 igb_setup_tx(igb);
1952 1954 }
1953 1955
1954 1956 static void
1955 1957 igb_setup_rx_ring(igb_rx_ring_t *rx_ring)
1956 1958 {
1957 1959 igb_t *igb = rx_ring->igb;
1958 1960 igb_rx_data_t *rx_data = rx_ring->rx_data;
1959 1961 struct e1000_hw *hw = &igb->hw;
1960 1962 rx_control_block_t *rcb;
1961 1963 union e1000_adv_rx_desc *rbd;
1962 1964 uint32_t size;
1963 1965 uint32_t buf_low;
1964 1966 uint32_t buf_high;
1965 1967 uint32_t rxdctl;
1966 1968 int i;
1967 1969
1968 1970 ASSERT(mutex_owned(&rx_ring->rx_lock));
1969 1971 ASSERT(mutex_owned(&igb->gen_lock));
1970 1972
1971 1973 /*
1972 1974 * Initialize descriptor ring with buffer addresses
1973 1975 */
1974 1976 for (i = 0; i < igb->rx_ring_size; i++) {
1975 1977 rcb = rx_data->work_list[i];
1976 1978 rbd = &rx_data->rbd_ring[i];
1977 1979
1978 1980 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
1979 1981 rbd->read.hdr_addr = NULL;
1980 1982 }
1981 1983
1982 1984 /*
1983 1985 * Initialize the base address registers
1984 1986 */
1985 1987 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
1986 1988 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
1987 1989 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high);
1988 1990 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low);
1989 1991
1990 1992 /*
1991 1993 * Initialize the length register
1992 1994 */
1993 1995 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc);
1994 1996 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size);
1995 1997
1996 1998 /*
1997 1999 * Initialize buffer size & descriptor type
1998 2000 */
1999 2001 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index),
2000 2002 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) |
2001 2003 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF));
2002 2004
2003 2005 /*
2004 2006 * Setup the Receive Descriptor Control Register (RXDCTL)
2005 2007 */
2006 2008 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index));
2007 2009 rxdctl &= igb->capab->rxdctl_mask;
2008 2010 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2009 2011 rxdctl |= 16; /* pthresh */
2010 2012 rxdctl |= 8 << 8; /* hthresh */
2011 2013 rxdctl |= 1 << 16; /* wthresh */
2012 2014 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl);
2013 2015
2014 2016 rx_data->rbd_next = 0;
2015 2017 }
2016 2018
2017 2019 static void
2018 2020 igb_setup_rx(igb_t *igb)
2019 2021 {
2020 2022 igb_rx_ring_t *rx_ring;
2021 2023 igb_rx_data_t *rx_data;
2022 2024 igb_rx_group_t *rx_group;
2023 2025 struct e1000_hw *hw = &igb->hw;
2024 2026 uint32_t rctl, rxcsum;
2025 2027 uint32_t ring_per_group;
2026 2028 int i;
2027 2029
2028 2030 /*
2029 2031 * Setup the Receive Control Register (RCTL), and enable the
2030 2032 * receiver. The initial configuration is to: enable the receiver,
2031 2033 * accept broadcasts, discard bad packets, accept long packets,
2032 2034 * disable VLAN filter checking, and set receive buffer size to
2033 2035 * 2k. For 82575, also set the receive descriptor minimum
2034 2036 * threshold size to 1/2 the ring.
2035 2037 */
2036 2038 rctl = E1000_READ_REG(hw, E1000_RCTL);
2037 2039
2038 2040 /*
2039 2041 * Clear the field used for wakeup control. This driver doesn't do
2040 2042 * wakeup but leave this here for completeness.
2041 2043 */
2042 2044 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2043 2045 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2044 2046
2045 2047 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */
2046 2048 E1000_RCTL_BAM | /* Accept Broadcast Packets */
2047 2049 E1000_RCTL_LPE | /* Large Packet Enable */
2048 2050 /* Multicast filter offset */
2049 2051 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
2050 2052 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */
2051 2053 E1000_RCTL_SECRC); /* Strip Ethernet CRC */
2052 2054
2053 2055 for (i = 0; i < igb->num_rx_groups; i++) {
2054 2056 rx_group = &igb->rx_groups[i];
2055 2057 rx_group->index = i;
2056 2058 rx_group->igb = igb;
2057 2059 }
2058 2060
2059 2061 /*
2060 2062 * Set up all rx descriptor rings - must be called before receive unit
2061 2063 * enabled.
2062 2064 */
2063 2065 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2064 2066 for (i = 0; i < igb->num_rx_rings; i++) {
2065 2067 rx_ring = &igb->rx_rings[i];
2066 2068 igb_setup_rx_ring(rx_ring);
2067 2069
2068 2070 /*
2069 2071 * Map a ring to a group by assigning a group index
2070 2072 */
2071 2073 rx_ring->group_index = i / ring_per_group;
2072 2074 }
2073 2075
2074 2076 /*
2075 2077 * Setup the Rx Long Packet Max Length register
2076 2078 */
2077 2079 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size);
2078 2080
2079 2081 /*
2080 2082 * Hardware checksum settings
2081 2083 */
2082 2084 if (igb->rx_hcksum_enable) {
2083 2085 rxcsum =
2084 2086 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */
2085 2087 E1000_RXCSUM_IPOFL; /* IP checksum */
2086 2088
2087 2089 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2088 2090 }
2089 2091
2090 2092 /*
2091 2093 * Setup classify and RSS for multiple receive queues
2092 2094 */
2093 2095 switch (igb->vmdq_mode) {
2094 2096 case E1000_VMDQ_OFF:
2095 2097 /*
2096 2098 * One ring group, only RSS is needed when more than
2097 2099 * one ring enabled.
2098 2100 */
2099 2101 if (igb->num_rx_rings > 1)
2100 2102 igb_setup_rss(igb);
2101 2103 break;
2102 2104 case E1000_VMDQ_MAC:
2103 2105 /*
2104 2106 * Multiple groups, each group has one ring,
2105 2107 * only the MAC classification is needed.
2106 2108 */
2107 2109 igb_setup_mac_classify(igb);
2108 2110 break;
2109 2111 case E1000_VMDQ_MAC_RSS:
2110 2112 /*
2111 2113 * Multiple groups and multiple rings, both
2112 2114 * MAC classification and RSS are needed.
2113 2115 */
2114 2116 igb_setup_mac_rss_classify(igb);
2115 2117 break;
2116 2118 }
2117 2119
2118 2120 /*
2119 2121 * Enable the receive unit - must be done after all
2120 2122 * the rx setup above.
2121 2123 */
2122 2124 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2123 2125
2124 2126 /*
2125 2127 * Initialize all adapter ring head & tail pointers - must
2126 2128 * be done after receive unit is enabled
2127 2129 */
2128 2130 for (i = 0; i < igb->num_rx_rings; i++) {
2129 2131 rx_ring = &igb->rx_rings[i];
2130 2132 rx_data = rx_ring->rx_data;
2131 2133 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2132 2134 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1);
2133 2135 }
2134 2136
2135 2137 /*
2136 2138 * 82575 with manageability enabled needs a special flush to make
2137 2139 * sure the fifos start clean.
2138 2140 */
2139 2141 if ((hw->mac.type == e1000_82575) &&
2140 2142 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) {
2141 2143 e1000_rx_fifo_flush_82575(hw);
2142 2144 }
2143 2145 }
2144 2146
2145 2147 static void
2146 2148 igb_setup_tx_ring(igb_tx_ring_t *tx_ring)
2147 2149 {
2148 2150 igb_t *igb = tx_ring->igb;
2149 2151 struct e1000_hw *hw = &igb->hw;
2150 2152 uint32_t size;
2151 2153 uint32_t buf_low;
2152 2154 uint32_t buf_high;
2153 2155 uint32_t reg_val;
2154 2156
2155 2157 ASSERT(mutex_owned(&tx_ring->tx_lock));
2156 2158 ASSERT(mutex_owned(&igb->gen_lock));
2157 2159
2158 2160
2159 2161 /*
2160 2162 * Initialize the length register
2161 2163 */
2162 2164 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc);
2163 2165 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size);
2164 2166
2165 2167 /*
2166 2168 * Initialize the base address registers
2167 2169 */
2168 2170 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2169 2171 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2170 2172 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low);
2171 2173 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high);
2172 2174
2173 2175 /*
2174 2176 * Setup head & tail pointers
2175 2177 */
2176 2178 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0);
2177 2179 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0);
2178 2180
2179 2181 /*
2180 2182 * Setup head write-back
2181 2183 */
2182 2184 if (igb->tx_head_wb_enable) {
2183 2185 /*
2184 2186 * The memory of the head write-back is allocated using
2185 2187 * the extra tbd beyond the tail of the tbd ring.
2186 2188 */
2187 2189 tx_ring->tbd_head_wb = (uint32_t *)
2188 2190 ((uintptr_t)tx_ring->tbd_area.address + size);
2189 2191 *tx_ring->tbd_head_wb = 0;
2190 2192
2191 2193 buf_low = (uint32_t)
2192 2194 (tx_ring->tbd_area.dma_address + size);
2193 2195 buf_high = (uint32_t)
2194 2196 ((tx_ring->tbd_area.dma_address + size) >> 32);
2195 2197
2196 2198 /* Set the head write-back enable bit */
2197 2199 buf_low |= E1000_TX_HEAD_WB_ENABLE;
2198 2200
2199 2201 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low);
2200 2202 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high);
2201 2203
2202 2204 /*
2203 2205 * Turn off relaxed ordering for head write back or it will
2204 2206 * cause problems with the tx recycling
2205 2207 */
2206 2208 reg_val = E1000_READ_REG(hw,
2207 2209 E1000_DCA_TXCTRL(tx_ring->index));
2208 2210 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2209 2211 E1000_WRITE_REG(hw,
2210 2212 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2211 2213 } else {
2212 2214 tx_ring->tbd_head_wb = NULL;
2213 2215 }
2214 2216
2215 2217 tx_ring->tbd_head = 0;
2216 2218 tx_ring->tbd_tail = 0;
2217 2219 tx_ring->tbd_free = tx_ring->ring_size;
2218 2220
2219 2221 if (igb->tx_ring_init == B_TRUE) {
2220 2222 tx_ring->tcb_head = 0;
2221 2223 tx_ring->tcb_tail = 0;
2222 2224 tx_ring->tcb_free = tx_ring->free_list_size;
2223 2225 }
2224 2226
2225 2227 /*
2226 2228 * Enable TXDCTL per queue
2227 2229 */
2228 2230 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2229 2231 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2230 2232 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2231 2233
2232 2234 /*
2233 2235 * Initialize hardware checksum offload settings
2234 2236 */
2235 2237 bzero(&tx_ring->tx_context, sizeof (tx_context_t));
2236 2238 }
2237 2239
2238 2240 static void
2239 2241 igb_setup_tx(igb_t *igb)
2240 2242 {
2241 2243 igb_tx_ring_t *tx_ring;
2242 2244 struct e1000_hw *hw = &igb->hw;
2243 2245 uint32_t reg_val;
2244 2246 int i;
2245 2247
2246 2248 for (i = 0; i < igb->num_tx_rings; i++) {
2247 2249 tx_ring = &igb->tx_rings[i];
2248 2250 igb_setup_tx_ring(tx_ring);
2249 2251 }
2250 2252
2251 2253 /*
2252 2254 * Setup the Transmit Control Register (TCTL)
2253 2255 */
2254 2256 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2255 2257 reg_val &= ~E1000_TCTL_CT;
2256 2258 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2257 2259 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2258 2260
2259 2261 /* Enable transmits */
2260 2262 reg_val |= E1000_TCTL_EN;
2261 2263
2262 2264 E1000_WRITE_REG(hw, E1000_TCTL, reg_val);
2263 2265 }
2264 2266
2265 2267 /*
2266 2268 * igb_setup_rss - Setup receive-side scaling feature
2267 2269 */
2268 2270 static void
2269 2271 igb_setup_rss(igb_t *igb)
2270 2272 {
2271 2273 struct e1000_hw *hw = &igb->hw;
2272 2274 uint32_t i, mrqc, rxcsum;
2273 2275 int shift = 0;
2274 2276 uint32_t random;
2275 2277 union e1000_reta {
2276 2278 uint32_t dword;
2277 2279 uint8_t bytes[4];
2278 2280 } reta;
2279 2281
2280 2282 /* Setup the Redirection Table */
2281 2283 if (hw->mac.type == e1000_82576) {
2282 2284 shift = 3;
2283 2285 } else if (hw->mac.type == e1000_82575) {
2284 2286 shift = 6;
2285 2287 }
2286 2288 for (i = 0; i < (32 * 4); i++) {
2287 2289 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift;
2288 2290 if ((i & 3) == 3) {
2289 2291 E1000_WRITE_REG(hw,
2290 2292 (E1000_RETA(0) + (i & ~3)), reta.dword);
2291 2293 }
2292 2294 }
2293 2295
2294 2296 /* Fill out hash function seeds */
2295 2297 for (i = 0; i < 10; i++) {
2296 2298 (void) random_get_pseudo_bytes((uint8_t *)&random,
2297 2299 sizeof (uint32_t));
2298 2300 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2299 2301 }
2300 2302
2301 2303 /* Setup the Multiple Receive Queue Control register */
2302 2304 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2303 2305 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2304 2306 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2305 2307 E1000_MRQC_RSS_FIELD_IPV6 |
2306 2308 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2307 2309 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2308 2310 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2309 2311 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2310 2312 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2311 2313
2312 2314 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2313 2315
2314 2316 /*
2315 2317 * Disable Packet Checksum to enable RSS for multiple receive queues.
2316 2318 *
2317 2319 * The Packet Checksum is not ethernet CRC. It is another kind of
2318 2320 * checksum offloading provided by the 82575 chipset besides the IP
2319 2321 * header checksum offloading and the TCP/UDP checksum offloading.
2320 2322 * The Packet Checksum is by default computed over the entire packet
2321 2323 * from the first byte of the DA through the last byte of the CRC,
2322 2324 * including the Ethernet and IP headers.
2323 2325 *
2324 2326 * It is a hardware limitation that Packet Checksum is mutually
2325 2327 * exclusive with RSS.
2326 2328 */
2327 2329 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2328 2330 rxcsum |= E1000_RXCSUM_PCSD;
2329 2331 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2330 2332 }
2331 2333
2332 2334 /*
2333 2335 * igb_setup_mac_rss_classify - Setup MAC classification and rss
2334 2336 */
2335 2337 static void
2336 2338 igb_setup_mac_rss_classify(igb_t *igb)
2337 2339 {
2338 2340 struct e1000_hw *hw = &igb->hw;
2339 2341 uint32_t i, mrqc, vmdctl, rxcsum;
2340 2342 uint32_t ring_per_group;
2341 2343 int shift_group0, shift_group1;
2342 2344 uint32_t random;
2343 2345 union e1000_reta {
2344 2346 uint32_t dword;
2345 2347 uint8_t bytes[4];
2346 2348 } reta;
2347 2349
2348 2350 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2349 2351
2350 2352 /* Setup the Redirection Table, it is shared between two groups */
2351 2353 shift_group0 = 2;
2352 2354 shift_group1 = 6;
2353 2355 for (i = 0; i < (32 * 4); i++) {
2354 2356 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) |
2355 2357 ((ring_per_group + (i % ring_per_group)) << shift_group1);
2356 2358 if ((i & 3) == 3) {
2357 2359 E1000_WRITE_REG(hw,
2358 2360 (E1000_RETA(0) + (i & ~3)), reta.dword);
2359 2361 }
2360 2362 }
2361 2363
2362 2364 /* Fill out hash function seeds */
2363 2365 for (i = 0; i < 10; i++) {
2364 2366 (void) random_get_pseudo_bytes((uint8_t *)&random,
2365 2367 sizeof (uint32_t));
2366 2368 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2367 2369 }
2368 2370
2369 2371 /*
2370 2372 * Setup the Multiple Receive Queue Control register,
2371 2373 * enable VMDq based on packet destination MAC address and RSS.
2372 2374 */
2373 2375 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP;
2374 2376 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2375 2377 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2376 2378 E1000_MRQC_RSS_FIELD_IPV6 |
2377 2379 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2378 2380 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2379 2381 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2380 2382 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2381 2383 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2382 2384
2383 2385 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2384 2386
2385 2387
2386 2388 /* Define the default group and default queues */
2387 2389 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE;
2388 2390 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl);
2389 2391
2390 2392 /*
2391 2393 * Disable Packet Checksum to enable RSS for multiple receive queues.
2392 2394 *
2393 2395 * The Packet Checksum is not ethernet CRC. It is another kind of
2394 2396 * checksum offloading provided by the 82575 chipset besides the IP
2395 2397 * header checksum offloading and the TCP/UDP checksum offloading.
2396 2398 * The Packet Checksum is by default computed over the entire packet
2397 2399 * from the first byte of the DA through the last byte of the CRC,
2398 2400 * including the Ethernet and IP headers.
2399 2401 *
2400 2402 * It is a hardware limitation that Packet Checksum is mutually
2401 2403 * exclusive with RSS.
2402 2404 */
2403 2405 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2404 2406 rxcsum |= E1000_RXCSUM_PCSD;
2405 2407 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2406 2408 }
2407 2409
2408 2410 /*
2409 2411 * igb_setup_mac_classify - Setup MAC classification feature
2410 2412 */
2411 2413 static void
2412 2414 igb_setup_mac_classify(igb_t *igb)
2413 2415 {
2414 2416 struct e1000_hw *hw = &igb->hw;
2415 2417 uint32_t mrqc, rxcsum;
2416 2418
2417 2419 /*
2418 2420 * Setup the Multiple Receive Queue Control register,
2419 2421 * enable VMDq based on packet destination MAC address.
2420 2422 */
2421 2423 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP;
2422 2424 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2423 2425
2424 2426 /*
2425 2427 * Disable Packet Checksum to enable RSS for multiple receive queues.
2426 2428 *
2427 2429 * The Packet Checksum is not ethernet CRC. It is another kind of
2428 2430 * checksum offloading provided by the 82575 chipset besides the IP
2429 2431 * header checksum offloading and the TCP/UDP checksum offloading.
2430 2432 * The Packet Checksum is by default computed over the entire packet
2431 2433 * from the first byte of the DA through the last byte of the CRC,
2432 2434 * including the Ethernet and IP headers.
2433 2435 *
2434 2436 * It is a hardware limitation that Packet Checksum is mutually
2435 2437 * exclusive with RSS.
2436 2438 */
2437 2439 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2438 2440 rxcsum |= E1000_RXCSUM_PCSD;
2439 2441 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2440 2442
2441 2443 }
2442 2444
2443 2445 /*
2444 2446 * igb_init_unicst - Initialize the unicast addresses
2445 2447 */
2446 2448 static void
2447 2449 igb_init_unicst(igb_t *igb)
2448 2450 {
2449 2451 struct e1000_hw *hw = &igb->hw;
2450 2452 int slot;
2451 2453
2452 2454 /*
2453 2455 * Here we should consider two situations:
2454 2456 *
2455 2457 * 1. Chipset is initialized the first time
2456 2458 * Initialize the multiple unicast addresses, and
2457 2459 * save the default MAC address.
2458 2460 *
2459 2461 * 2. Chipset is reset
2460 2462 * Recover the multiple unicast addresses from the
2461 2463 * software data structure to the RAR registers.
2462 2464 */
2463 2465
2464 2466 /*
2465 2467 * Clear the default MAC address in the RAR0 rgister,
2466 2468 * which is loaded from EEPROM when system boot or chipreset,
2467 2469 * this will cause the conficts with add_mac/rem_mac entry
2468 2470 * points when VMDq is enabled. For this reason, the RAR0
2469 2471 * must be cleared for both cases mentioned above.
2470 2472 */
2471 2473 e1000_rar_clear(hw, 0);
2472 2474
2473 2475 if (!igb->unicst_init) {
2474 2476
2475 2477 /* Initialize the multiple unicast addresses */
2476 2478 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2477 2479 igb->unicst_avail = igb->unicst_total;
2478 2480
2479 2481 for (slot = 0; slot < igb->unicst_total; slot++)
2480 2482 igb->unicst_addr[slot].mac.set = 0;
2481 2483
2482 2484 igb->unicst_init = B_TRUE;
2483 2485 } else {
2484 2486 /* Re-configure the RAR registers */
2485 2487 for (slot = 0; slot < igb->unicst_total; slot++) {
2486 2488 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr,
2487 2489 slot, igb->vmdq_mode,
2488 2490 igb->unicst_addr[slot].mac.group_index);
2489 2491 }
2490 2492 }
2491 2493 }
2492 2494
2493 2495 /*
2494 2496 * igb_unicst_find - Find the slot for the specified unicast address
2495 2497 */
2496 2498 int
2497 2499 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr)
2498 2500 {
2499 2501 int slot;
2500 2502
2501 2503 ASSERT(mutex_owned(&igb->gen_lock));
2502 2504
2503 2505 for (slot = 0; slot < igb->unicst_total; slot++) {
2504 2506 if (bcmp(igb->unicst_addr[slot].mac.addr,
2505 2507 mac_addr, ETHERADDRL) == 0)
2506 2508 return (slot);
2507 2509 }
2508 2510
2509 2511 return (-1);
2510 2512 }
2511 2513
2512 2514 /*
2513 2515 * igb_unicst_set - Set the unicast address to the specified slot
2514 2516 */
2515 2517 int
2516 2518 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr,
2517 2519 int slot)
2518 2520 {
2519 2521 struct e1000_hw *hw = &igb->hw;
2520 2522
2521 2523 ASSERT(mutex_owned(&igb->gen_lock));
2522 2524
2523 2525 /*
2524 2526 * Save the unicast address in the software data structure
2525 2527 */
2526 2528 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
2527 2529
2528 2530 /*
2529 2531 * Set the unicast address to the RAR register
2530 2532 */
2531 2533 e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2532 2534
2533 2535 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2534 2536 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2535 2537 return (EIO);
2536 2538 }
2537 2539
2538 2540 return (0);
2539 2541 }
2540 2542
2541 2543 /*
2542 2544 * igb_multicst_add - Add a multicst address
2543 2545 */
2544 2546 int
2545 2547 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr)
2546 2548 {
2547 2549 struct ether_addr *new_table;
2548 2550 size_t new_len;
2549 2551 size_t old_len;
2550 2552
2551 2553 ASSERT(mutex_owned(&igb->gen_lock));
2552 2554
2553 2555 if ((multiaddr[0] & 01) == 0) {
2554 2556 igb_error(igb, "Illegal multicast address");
2555 2557 return (EINVAL);
2556 2558 }
2557 2559
2558 2560 if (igb->mcast_count >= igb->mcast_max_num) {
2559 2561 igb_error(igb, "Adapter requested more than %d mcast addresses",
2560 2562 igb->mcast_max_num);
2561 2563 return (ENOENT);
2562 2564 }
2563 2565
2564 2566 if (igb->mcast_count == igb->mcast_alloc_count) {
2565 2567 old_len = igb->mcast_alloc_count *
2566 2568 sizeof (struct ether_addr);
2567 2569 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) *
2568 2570 sizeof (struct ether_addr);
2569 2571
2570 2572 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2571 2573 if (new_table == NULL) {
2572 2574 igb_error(igb,
2573 2575 "Not enough memory to alloc mcast table");
2574 2576 return (ENOMEM);
2575 2577 }
2576 2578
2577 2579 if (igb->mcast_table != NULL) {
2578 2580 bcopy(igb->mcast_table, new_table, old_len);
2579 2581 kmem_free(igb->mcast_table, old_len);
2580 2582 }
2581 2583 igb->mcast_alloc_count += MCAST_ALLOC_COUNT;
2582 2584 igb->mcast_table = new_table;
2583 2585 }
2584 2586
2585 2587 bcopy(multiaddr,
2586 2588 &igb->mcast_table[igb->mcast_count], ETHERADDRL);
2587 2589 igb->mcast_count++;
2588 2590
2589 2591 /*
2590 2592 * Update the multicast table in the hardware
2591 2593 */
2592 2594 igb_setup_multicst(igb);
2593 2595
2594 2596 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2595 2597 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2596 2598 return (EIO);
2597 2599 }
2598 2600
2599 2601 return (0);
2600 2602 }
2601 2603
2602 2604 /*
2603 2605 * igb_multicst_remove - Remove a multicst address
2604 2606 */
2605 2607 int
2606 2608 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr)
2607 2609 {
2608 2610 struct ether_addr *new_table;
2609 2611 size_t new_len;
2610 2612 size_t old_len;
2611 2613 int i;
2612 2614
2613 2615 ASSERT(mutex_owned(&igb->gen_lock));
2614 2616
2615 2617 for (i = 0; i < igb->mcast_count; i++) {
2616 2618 if (bcmp(multiaddr, &igb->mcast_table[i],
2617 2619 ETHERADDRL) == 0) {
2618 2620 for (i++; i < igb->mcast_count; i++) {
2619 2621 igb->mcast_table[i - 1] =
2620 2622 igb->mcast_table[i];
2621 2623 }
2622 2624 igb->mcast_count--;
2623 2625 break;
2624 2626 }
2625 2627 }
2626 2628
2627 2629 if ((igb->mcast_alloc_count - igb->mcast_count) >
2628 2630 MCAST_ALLOC_COUNT) {
2629 2631 old_len = igb->mcast_alloc_count *
2630 2632 sizeof (struct ether_addr);
2631 2633 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) *
2632 2634 sizeof (struct ether_addr);
2633 2635
2634 2636 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2635 2637 if (new_table != NULL) {
2636 2638 bcopy(igb->mcast_table, new_table, new_len);
2637 2639 kmem_free(igb->mcast_table, old_len);
2638 2640 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT;
2639 2641 igb->mcast_table = new_table;
2640 2642 }
2641 2643 }
2642 2644
2643 2645 /*
2644 2646 * Update the multicast table in the hardware
2645 2647 */
2646 2648 igb_setup_multicst(igb);
2647 2649
2648 2650 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2649 2651 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2650 2652 return (EIO);
2651 2653 }
2652 2654
2653 2655 return (0);
2654 2656 }
2655 2657
2656 2658 static void
2657 2659 igb_release_multicast(igb_t *igb)
2658 2660 {
2659 2661 if (igb->mcast_table != NULL) {
2660 2662 kmem_free(igb->mcast_table,
2661 2663 igb->mcast_alloc_count * sizeof (struct ether_addr));
2662 2664 igb->mcast_table = NULL;
2663 2665 }
2664 2666 }
2665 2667
2666 2668 /*
2667 2669 * igb_setup_multicast - setup multicast data structures
2668 2670 *
2669 2671 * This routine initializes all of the multicast related structures
2670 2672 * and save them in the hardware registers.
2671 2673 */
2672 2674 static void
2673 2675 igb_setup_multicst(igb_t *igb)
2674 2676 {
2675 2677 uint8_t *mc_addr_list;
2676 2678 uint32_t mc_addr_count;
2677 2679 struct e1000_hw *hw = &igb->hw;
2678 2680
2679 2681 ASSERT(mutex_owned(&igb->gen_lock));
2680 2682 ASSERT(igb->mcast_count <= igb->mcast_max_num);
2681 2683
2682 2684 mc_addr_list = (uint8_t *)igb->mcast_table;
2683 2685 mc_addr_count = igb->mcast_count;
2684 2686
2685 2687 /*
2686 2688 * Update the multicase addresses to the MTA registers
2687 2689 */
2688 2690 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
2689 2691 }
2690 2692
2691 2693 /*
2692 2694 * igb_get_conf - Get driver configurations set in driver.conf
2693 2695 *
2694 2696 * This routine gets user-configured values out of the configuration
2695 2697 * file igb.conf.
2696 2698 *
2697 2699 * For each configurable value, there is a minimum, a maximum, and a
2698 2700 * default.
2699 2701 * If user does not configure a value, use the default.
2700 2702 * If user configures below the minimum, use the minumum.
2701 2703 * If user configures above the maximum, use the maxumum.
2702 2704 */
2703 2705 static void
2704 2706 igb_get_conf(igb_t *igb)
2705 2707 {
2706 2708 struct e1000_hw *hw = &igb->hw;
2707 2709 uint32_t default_mtu;
2708 2710 uint32_t flow_control;
2709 2711 uint32_t ring_per_group;
2710 2712 int i;
2711 2713
2712 2714 /*
2713 2715 * igb driver supports the following user configurations:
2714 2716 *
2715 2717 * Link configurations:
2716 2718 * adv_autoneg_cap
2717 2719 * adv_1000fdx_cap
2718 2720 * adv_100fdx_cap
2719 2721 * adv_100hdx_cap
2720 2722 * adv_10fdx_cap
2721 2723 * adv_10hdx_cap
2722 2724 * Note: 1000hdx is not supported.
2723 2725 *
2724 2726 * Jumbo frame configuration:
2725 2727 * default_mtu
2726 2728 *
2727 2729 * Ethernet flow control configuration:
2728 2730 * flow_control
2729 2731 *
2730 2732 * Multiple rings configurations:
2731 2733 * tx_queue_number
2732 2734 * tx_ring_size
2733 2735 * rx_queue_number
2734 2736 * rx_ring_size
2735 2737 *
2736 2738 * Call igb_get_prop() to get the value for a specific
2737 2739 * configuration parameter.
2738 2740 */
2739 2741
2740 2742 /*
2741 2743 * Link configurations
2742 2744 */
2743 2745 igb->param_adv_autoneg_cap = igb_get_prop(igb,
2744 2746 PROP_ADV_AUTONEG_CAP, 0, 1, 1);
2745 2747 igb->param_adv_1000fdx_cap = igb_get_prop(igb,
2746 2748 PROP_ADV_1000FDX_CAP, 0, 1, 1);
2747 2749 igb->param_adv_100fdx_cap = igb_get_prop(igb,
2748 2750 PROP_ADV_100FDX_CAP, 0, 1, 1);
2749 2751 igb->param_adv_100hdx_cap = igb_get_prop(igb,
2750 2752 PROP_ADV_100HDX_CAP, 0, 1, 1);
2751 2753 igb->param_adv_10fdx_cap = igb_get_prop(igb,
2752 2754 PROP_ADV_10FDX_CAP, 0, 1, 1);
2753 2755 igb->param_adv_10hdx_cap = igb_get_prop(igb,
2754 2756 PROP_ADV_10HDX_CAP, 0, 1, 1);
2755 2757
2756 2758 /*
2757 2759 * Jumbo frame configurations
2758 2760 */
2759 2761 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
2760 2762 MIN_MTU, MAX_MTU, DEFAULT_MTU);
2761 2763
2762 2764 igb->max_frame_size = default_mtu +
2763 2765 sizeof (struct ether_vlan_header) + ETHERFCSL;
2764 2766
2765 2767 /*
2766 2768 * Ethernet flow control configuration
2767 2769 */
2768 2770 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL,
2769 2771 e1000_fc_none, 4, e1000_fc_full);
2770 2772 if (flow_control == 4)
2771 2773 flow_control = e1000_fc_default;
2772 2774
2773 2775 hw->fc.requested_mode = flow_control;
2774 2776
2775 2777 /*
2776 2778 * Multiple rings configurations
2777 2779 */
2778 2780 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE,
2779 2781 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
2780 2782 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE,
2781 2783 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
2782 2784
2783 2785 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0);
2784 2786 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM,
2785 2787 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM);
2786 2788 /*
2787 2789 * Currently we do not support VMDq for 82576 and 82580.
2788 2790 * If it is e1000_82576, set num_rx_groups to 1.
2789 2791 */
2790 2792 if (hw->mac.type >= e1000_82576)
2791 2793 igb->num_rx_groups = 1;
2792 2794
2793 2795 if (igb->mr_enable) {
2794 2796 igb->num_tx_rings = igb->capab->def_tx_que_num;
2795 2797 igb->num_rx_rings = igb->capab->def_rx_que_num;
2796 2798 } else {
2797 2799 igb->num_tx_rings = 1;
2798 2800 igb->num_rx_rings = 1;
2799 2801
2800 2802 if (igb->num_rx_groups > 1) {
2801 2803 igb_error(igb,
2802 2804 "Invalid rx groups number. Please enable multiple "
2803 2805 "rings first");
2804 2806 igb->num_rx_groups = 1;
2805 2807 }
2806 2808 }
2807 2809
2808 2810 /*
2809 2811 * Check the divisibility between rx rings and rx groups.
2810 2812 */
2811 2813 for (i = igb->num_rx_groups; i > 0; i--) {
2812 2814 if ((igb->num_rx_rings % i) == 0)
2813 2815 break;
2814 2816 }
2815 2817 if (i != igb->num_rx_groups) {
2816 2818 igb_error(igb,
2817 2819 "Invalid rx groups number. Downgrade the rx group "
2818 2820 "number to %d.", i);
2819 2821 igb->num_rx_groups = i;
2820 2822 }
2821 2823
2822 2824 /*
2823 2825 * Get the ring number per group.
2824 2826 */
2825 2827 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2826 2828
2827 2829 if (igb->num_rx_groups == 1) {
2828 2830 /*
2829 2831 * One rx ring group, the rx ring number is num_rx_rings.
2830 2832 */
2831 2833 igb->vmdq_mode = E1000_VMDQ_OFF;
2832 2834 } else if (ring_per_group == 1) {
2833 2835 /*
2834 2836 * Multiple rx groups, each group has one rx ring.
2835 2837 */
2836 2838 igb->vmdq_mode = E1000_VMDQ_MAC;
2837 2839 } else {
2838 2840 /*
2839 2841 * Multiple groups and multiple rings.
2840 2842 */
2841 2843 igb->vmdq_mode = E1000_VMDQ_MAC_RSS;
2842 2844 }
2843 2845
2844 2846 /*
2845 2847 * Tunable used to force an interrupt type. The only use is
2846 2848 * for testing of the lesser interrupt types.
2847 2849 * 0 = don't force interrupt type
2848 2850 * 1 = force interrupt type MSIX
2849 2851 * 2 = force interrupt type MSI
2850 2852 * 3 = force interrupt type Legacy
2851 2853 */
2852 2854 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE,
2853 2855 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE);
2854 2856
2855 2857 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE,
2856 2858 0, 1, 1);
2857 2859 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE,
2858 2860 0, 1, 1);
2859 2861 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE,
2860 2862 0, 1, 1);
2861 2863 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE,
2862 2864 0, 1, 1);
2863 2865
2864 2866 /*
2865 2867 * igb LSO needs the tx h/w checksum support.
2866 2868 * Here LSO will be disabled if tx h/w checksum has been disabled.
2867 2869 */
2868 2870 if (igb->tx_hcksum_enable == B_FALSE)
2869 2871 igb->lso_enable = B_FALSE;
2870 2872
2871 2873 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD,
2872 2874 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
2873 2875 DEFAULT_TX_COPY_THRESHOLD);
2874 2876 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD,
2875 2877 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD,
2876 2878 DEFAULT_TX_RECYCLE_THRESHOLD);
2877 2879 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD,
2878 2880 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD,
2879 2881 DEFAULT_TX_OVERLOAD_THRESHOLD);
2880 2882 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD,
2881 2883 MIN_TX_RESCHED_THRESHOLD,
2882 2884 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD),
2883 2885 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ?
2884 2886 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW);
2885 2887
2886 2888 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD,
2887 2889 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
2888 2890 DEFAULT_RX_COPY_THRESHOLD);
2889 2891 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR,
2890 2892 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
2891 2893 DEFAULT_RX_LIMIT_PER_INTR);
2892 2894
2893 2895 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING,
2894 2896 igb->capab->min_intr_throttle,
2895 2897 igb->capab->max_intr_throttle,
2896 2898 igb->capab->def_intr_throttle);
2897 2899
2898 2900 /*
2899 2901 * Max number of multicast addresses
2900 2902 */
2901 2903 igb->mcast_max_num =
2902 2904 igb_get_prop(igb, PROP_MCAST_MAX_NUM,
2903 2905 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM);
2904 2906 }
2905 2907
2906 2908 /*
2907 2909 * igb_get_prop - Get a property value out of the configuration file igb.conf
2908 2910 *
2909 2911 * Caller provides the name of the property, a default value, a minimum
2910 2912 * value, and a maximum value.
2911 2913 *
2912 2914 * Return configured value of the property, with default, minimum and
2913 2915 * maximum properly applied.
2914 2916 */
2915 2917 static int
2916 2918 igb_get_prop(igb_t *igb,
2917 2919 char *propname, /* name of the property */
2918 2920 int minval, /* minimum acceptable value */
2919 2921 int maxval, /* maximim acceptable value */
2920 2922 int defval) /* default value */
2921 2923 {
2922 2924 int value;
2923 2925
2924 2926 /*
2925 2927 * Call ddi_prop_get_int() to read the conf settings
2926 2928 */
2927 2929 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip,
2928 2930 DDI_PROP_DONTPASS, propname, defval);
2929 2931
2930 2932 if (value > maxval)
2931 2933 value = maxval;
2932 2934
2933 2935 if (value < minval)
2934 2936 value = minval;
2935 2937
2936 2938 return (value);
2937 2939 }
2938 2940
2939 2941 /*
2940 2942 * igb_setup_link - Using the link properties to setup the link
2941 2943 */
2942 2944 int
2943 2945 igb_setup_link(igb_t *igb, boolean_t setup_hw)
2944 2946 {
2945 2947 struct e1000_mac_info *mac;
2946 2948 struct e1000_phy_info *phy;
2947 2949 boolean_t invalid;
2948 2950
2949 2951 mac = &igb->hw.mac;
2950 2952 phy = &igb->hw.phy;
2951 2953 invalid = B_FALSE;
2952 2954
2953 2955 if (igb->param_adv_autoneg_cap == 1) {
2954 2956 mac->autoneg = B_TRUE;
2955 2957 phy->autoneg_advertised = 0;
2956 2958
2957 2959 /*
2958 2960 * 1000hdx is not supported for autonegotiation
2959 2961 */
2960 2962 if (igb->param_adv_1000fdx_cap == 1)
2961 2963 phy->autoneg_advertised |= ADVERTISE_1000_FULL;
2962 2964
2963 2965 if (igb->param_adv_100fdx_cap == 1)
2964 2966 phy->autoneg_advertised |= ADVERTISE_100_FULL;
2965 2967
2966 2968 if (igb->param_adv_100hdx_cap == 1)
2967 2969 phy->autoneg_advertised |= ADVERTISE_100_HALF;
2968 2970
2969 2971 if (igb->param_adv_10fdx_cap == 1)
2970 2972 phy->autoneg_advertised |= ADVERTISE_10_FULL;
2971 2973
2972 2974 if (igb->param_adv_10hdx_cap == 1)
2973 2975 phy->autoneg_advertised |= ADVERTISE_10_HALF;
2974 2976
2975 2977 if (phy->autoneg_advertised == 0)
2976 2978 invalid = B_TRUE;
2977 2979 } else {
2978 2980 mac->autoneg = B_FALSE;
2979 2981
2980 2982 /*
2981 2983 * 1000fdx and 1000hdx are not supported for forced link
2982 2984 */
2983 2985 if (igb->param_adv_100fdx_cap == 1)
2984 2986 mac->forced_speed_duplex = ADVERTISE_100_FULL;
2985 2987 else if (igb->param_adv_100hdx_cap == 1)
2986 2988 mac->forced_speed_duplex = ADVERTISE_100_HALF;
2987 2989 else if (igb->param_adv_10fdx_cap == 1)
2988 2990 mac->forced_speed_duplex = ADVERTISE_10_FULL;
2989 2991 else if (igb->param_adv_10hdx_cap == 1)
2990 2992 mac->forced_speed_duplex = ADVERTISE_10_HALF;
2991 2993 else
2992 2994 invalid = B_TRUE;
2993 2995 }
2994 2996
2995 2997 if (invalid) {
2996 2998 igb_notice(igb, "Invalid link settings. Setup link to "
2997 2999 "autonegotiation with full link capabilities.");
2998 3000 mac->autoneg = B_TRUE;
2999 3001 phy->autoneg_advertised = ADVERTISE_1000_FULL |
3000 3002 ADVERTISE_100_FULL | ADVERTISE_100_HALF |
3001 3003 ADVERTISE_10_FULL | ADVERTISE_10_HALF;
3002 3004 }
3003 3005
3004 3006 if (setup_hw) {
3005 3007 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS)
3006 3008 return (IGB_FAILURE);
3007 3009 }
3008 3010
3009 3011 return (IGB_SUCCESS);
3010 3012 }
3011 3013
3012 3014
3013 3015 /*
3014 3016 * igb_is_link_up - Check if the link is up
3015 3017 */
3016 3018 static boolean_t
3017 3019 igb_is_link_up(igb_t *igb)
3018 3020 {
3019 3021 struct e1000_hw *hw = &igb->hw;
3020 3022 boolean_t link_up = B_FALSE;
3021 3023
3022 3024 ASSERT(mutex_owned(&igb->gen_lock));
3023 3025
3024 3026 /*
3025 3027 * get_link_status is set in the interrupt handler on link-status-change
3026 3028 * or rx sequence error interrupt. get_link_status will stay
3027 3029 * false until the e1000_check_for_link establishes link only
3028 3030 * for copper adapters.
3029 3031 */
3030 3032 switch (hw->phy.media_type) {
3031 3033 case e1000_media_type_copper:
3032 3034 if (hw->mac.get_link_status) {
3033 3035 (void) e1000_check_for_link(hw);
3034 3036 link_up = !hw->mac.get_link_status;
3035 3037 } else {
3036 3038 link_up = B_TRUE;
3037 3039 }
3038 3040 break;
3039 3041 case e1000_media_type_fiber:
3040 3042 (void) e1000_check_for_link(hw);
3041 3043 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
3042 3044 break;
3043 3045 case e1000_media_type_internal_serdes:
3044 3046 (void) e1000_check_for_link(hw);
3045 3047 link_up = hw->mac.serdes_has_link;
3046 3048 break;
3047 3049 }
3048 3050
3049 3051 return (link_up);
3050 3052 }
3051 3053
3052 3054 /*
3053 3055 * igb_link_check - Link status processing
3054 3056 */
3055 3057 static boolean_t
3056 3058 igb_link_check(igb_t *igb)
3057 3059 {
3058 3060 struct e1000_hw *hw = &igb->hw;
3059 3061 uint16_t speed = 0, duplex = 0;
3060 3062 boolean_t link_changed = B_FALSE;
3061 3063
3062 3064 ASSERT(mutex_owned(&igb->gen_lock));
3063 3065
3064 3066 if (igb_is_link_up(igb)) {
3065 3067 /*
3066 3068 * The Link is up, check whether it was marked as down earlier
3067 3069 */
3068 3070 if (igb->link_state != LINK_STATE_UP) {
3069 3071 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
3070 3072 igb->link_speed = speed;
3071 3073 igb->link_duplex = duplex;
3072 3074 igb->link_state = LINK_STATE_UP;
3073 3075 link_changed = B_TRUE;
3074 3076 if (!igb->link_complete)
3075 3077 igb_stop_link_timer(igb);
3076 3078 }
3077 3079 } else if (igb->link_complete) {
3078 3080 if (igb->link_state != LINK_STATE_DOWN) {
3079 3081 igb->link_speed = 0;
3080 3082 igb->link_duplex = 0;
3081 3083 igb->link_state = LINK_STATE_DOWN;
3082 3084 link_changed = B_TRUE;
3083 3085 }
3084 3086 }
3085 3087
3086 3088 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3087 3089 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3088 3090 return (B_FALSE);
3089 3091 }
3090 3092
3091 3093 return (link_changed);
3092 3094 }
3093 3095
3094 3096 /*
3095 3097 * igb_local_timer - driver watchdog function
3096 3098 *
3097 3099 * This function will handle the hardware stall check, link status
3098 3100 * check and other routines.
3099 3101 */
3100 3102 static void
3101 3103 igb_local_timer(void *arg)
3102 3104 {
3103 3105 igb_t *igb = (igb_t *)arg;
3104 3106 boolean_t link_changed = B_FALSE;
3105 3107
3106 3108 if (igb->igb_state & IGB_ERROR) {
3107 3109 igb->reset_count++;
3108 3110 if (igb_reset(igb) == IGB_SUCCESS)
3109 3111 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3110 3112
3111 3113 igb_restart_watchdog_timer(igb);
3112 3114 return;
3113 3115 }
3114 3116
3115 3117 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) {
3116 3118 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL);
3117 3119 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
3118 3120 igb->reset_count++;
3119 3121 if (igb_reset(igb) == IGB_SUCCESS)
3120 3122 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3121 3123
3122 3124 igb_restart_watchdog_timer(igb);
3123 3125 return;
3124 3126 }
3125 3127
3126 3128 mutex_enter(&igb->gen_lock);
3127 3129 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED))
3128 3130 link_changed = igb_link_check(igb);
3129 3131 mutex_exit(&igb->gen_lock);
3130 3132
3131 3133 if (link_changed)
3132 3134 mac_link_update(igb->mac_hdl, igb->link_state);
3133 3135
3134 3136 igb_restart_watchdog_timer(igb);
3135 3137 }
3136 3138
3137 3139 /*
3138 3140 * igb_link_timer - link setup timer function
3139 3141 *
3140 3142 * It is called when the timer for link setup is expired, which indicates
3141 3143 * the completion of the link setup. The link state will not be updated
3142 3144 * until the link setup is completed. And the link state will not be sent
3143 3145 * to the upper layer through mac_link_update() in this function. It will
3144 3146 * be updated in the local timer routine or the interrupts service routine
3145 3147 * after the interface is started (plumbed).
3146 3148 */
3147 3149 static void
3148 3150 igb_link_timer(void *arg)
3149 3151 {
3150 3152 igb_t *igb = (igb_t *)arg;
3151 3153
3152 3154 mutex_enter(&igb->link_lock);
3153 3155 igb->link_complete = B_TRUE;
3154 3156 igb->link_tid = 0;
3155 3157 mutex_exit(&igb->link_lock);
3156 3158 }
3157 3159 /*
3158 3160 * igb_stall_check - check for transmit stall
3159 3161 *
3160 3162 * This function checks if the adapter is stalled (in transmit).
3161 3163 *
3162 3164 * It is called each time the watchdog timeout is invoked.
3163 3165 * If the transmit descriptor reclaim continuously fails,
3164 3166 * the watchdog value will increment by 1. If the watchdog
3165 3167 * value exceeds the threshold, the igb is assumed to
3166 3168 * have stalled and need to be reset.
3167 3169 */
3168 3170 static boolean_t
3169 3171 igb_stall_check(igb_t *igb)
3170 3172 {
3171 3173 igb_tx_ring_t *tx_ring;
3172 3174 struct e1000_hw *hw = &igb->hw;
3173 3175 boolean_t result;
3174 3176 int i;
3175 3177
3176 3178 if (igb->link_state != LINK_STATE_UP)
3177 3179 return (B_FALSE);
3178 3180
3179 3181 /*
3180 3182 * If any tx ring is stalled, we'll reset the chipset
3181 3183 */
3182 3184 result = B_FALSE;
3183 3185 for (i = 0; i < igb->num_tx_rings; i++) {
3184 3186 tx_ring = &igb->tx_rings[i];
3185 3187
3186 3188 if (tx_ring->recycle_fail > 0)
3187 3189 tx_ring->stall_watchdog++;
3188 3190 else
3189 3191 tx_ring->stall_watchdog = 0;
3190 3192
3191 3193 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
3192 3194 result = B_TRUE;
3193 3195 if (hw->mac.type == e1000_82580) {
3194 3196 hw->dev_spec._82575.global_device_reset
3195 3197 = B_TRUE;
3196 3198 }
3197 3199 break;
3198 3200 }
3199 3201 }
3200 3202
3201 3203 if (result) {
3202 3204 tx_ring->stall_watchdog = 0;
3203 3205 tx_ring->recycle_fail = 0;
3204 3206 }
3205 3207
3206 3208 return (result);
3207 3209 }
3208 3210
3209 3211
3210 3212 /*
3211 3213 * is_valid_mac_addr - Check if the mac address is valid
3212 3214 */
3213 3215 static boolean_t
3214 3216 is_valid_mac_addr(uint8_t *mac_addr)
3215 3217 {
3216 3218 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
3217 3219 const uint8_t addr_test2[6] =
3218 3220 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3219 3221
3220 3222 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
3221 3223 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
3222 3224 return (B_FALSE);
3223 3225
3224 3226 return (B_TRUE);
3225 3227 }
3226 3228
3227 3229 static boolean_t
3228 3230 igb_find_mac_address(igb_t *igb)
3229 3231 {
3230 3232 struct e1000_hw *hw = &igb->hw;
3231 3233 #ifdef __sparc
3232 3234 uchar_t *bytes;
3233 3235 struct ether_addr sysaddr;
3234 3236 uint_t nelts;
3235 3237 int err;
3236 3238 boolean_t found = B_FALSE;
3237 3239
3238 3240 /*
3239 3241 * The "vendor's factory-set address" may already have
3240 3242 * been extracted from the chip, but if the property
3241 3243 * "local-mac-address" is set we use that instead.
3242 3244 *
3243 3245 * We check whether it looks like an array of 6
3244 3246 * bytes (which it should, if OBP set it). If we can't
3245 3247 * make sense of it this way, we'll ignore it.
3246 3248 */
3247 3249 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3248 3250 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
3249 3251 if (err == DDI_PROP_SUCCESS) {
3250 3252 if (nelts == ETHERADDRL) {
3251 3253 while (nelts--)
3252 3254 hw->mac.addr[nelts] = bytes[nelts];
3253 3255 found = B_TRUE;
3254 3256 }
3255 3257 ddi_prop_free(bytes);
3256 3258 }
3257 3259
3258 3260 /*
3259 3261 * Look up the OBP property "local-mac-address?". If the user has set
3260 3262 * 'local-mac-address? = false', use "the system address" instead.
3261 3263 */
3262 3264 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0,
3263 3265 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
3264 3266 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
3265 3267 if (localetheraddr(NULL, &sysaddr) != 0) {
3266 3268 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
3267 3269 found = B_TRUE;
3268 3270 }
3269 3271 }
3270 3272 ddi_prop_free(bytes);
3271 3273 }
3272 3274
3273 3275 /*
3274 3276 * Finally(!), if there's a valid "mac-address" property (created
3275 3277 * if we netbooted from this interface), we must use this instead
3276 3278 * of any of the above to ensure that the NFS/install server doesn't
3277 3279 * get confused by the address changing as Solaris takes over!
3278 3280 */
3279 3281 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3280 3282 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
3281 3283 if (err == DDI_PROP_SUCCESS) {
3282 3284 if (nelts == ETHERADDRL) {
3283 3285 while (nelts--)
3284 3286 hw->mac.addr[nelts] = bytes[nelts];
3285 3287 found = B_TRUE;
3286 3288 }
3287 3289 ddi_prop_free(bytes);
3288 3290 }
3289 3291
3290 3292 if (found) {
3291 3293 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
3292 3294 return (B_TRUE);
3293 3295 }
3294 3296 #endif
3295 3297
3296 3298 /*
3297 3299 * Read the device MAC address from the EEPROM
3298 3300 */
3299 3301 if (e1000_read_mac_addr(hw) != E1000_SUCCESS)
3300 3302 return (B_FALSE);
3301 3303
3302 3304 return (B_TRUE);
3303 3305 }
3304 3306
3305 3307 #pragma inline(igb_arm_watchdog_timer)
3306 3308
3307 3309 static void
3308 3310 igb_arm_watchdog_timer(igb_t *igb)
3309 3311 {
3310 3312 /*
3311 3313 * Fire a watchdog timer
3312 3314 */
3313 3315 igb->watchdog_tid =
3314 3316 timeout(igb_local_timer,
3315 3317 (void *)igb, 1 * drv_usectohz(1000000));
3316 3318
3317 3319 }
3318 3320
3319 3321 /*
3320 3322 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer
3321 3323 */
3322 3324 void
3323 3325 igb_enable_watchdog_timer(igb_t *igb)
3324 3326 {
3325 3327 mutex_enter(&igb->watchdog_lock);
3326 3328
3327 3329 if (!igb->watchdog_enable) {
3328 3330 igb->watchdog_enable = B_TRUE;
3329 3331 igb->watchdog_start = B_TRUE;
3330 3332 igb_arm_watchdog_timer(igb);
3331 3333 }
3332 3334
3333 3335 mutex_exit(&igb->watchdog_lock);
3334 3336
3335 3337 }
3336 3338
3337 3339 /*
3338 3340 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer
3339 3341 */
3340 3342 void
3341 3343 igb_disable_watchdog_timer(igb_t *igb)
3342 3344 {
3343 3345 timeout_id_t tid;
3344 3346
3345 3347 mutex_enter(&igb->watchdog_lock);
3346 3348
3347 3349 igb->watchdog_enable = B_FALSE;
3348 3350 igb->watchdog_start = B_FALSE;
3349 3351 tid = igb->watchdog_tid;
3350 3352 igb->watchdog_tid = 0;
3351 3353
3352 3354 mutex_exit(&igb->watchdog_lock);
3353 3355
3354 3356 if (tid != 0)
3355 3357 (void) untimeout(tid);
3356 3358
3357 3359 }
3358 3360
3359 3361 /*
3360 3362 * igb_start_watchdog_timer - Start the driver watchdog timer
3361 3363 */
3362 3364 static void
3363 3365 igb_start_watchdog_timer(igb_t *igb)
3364 3366 {
3365 3367 mutex_enter(&igb->watchdog_lock);
3366 3368
3367 3369 if (igb->watchdog_enable) {
3368 3370 if (!igb->watchdog_start) {
3369 3371 igb->watchdog_start = B_TRUE;
3370 3372 igb_arm_watchdog_timer(igb);
3371 3373 }
3372 3374 }
3373 3375
3374 3376 mutex_exit(&igb->watchdog_lock);
3375 3377 }
3376 3378
3377 3379 /*
3378 3380 * igb_restart_watchdog_timer - Restart the driver watchdog timer
3379 3381 */
3380 3382 static void
3381 3383 igb_restart_watchdog_timer(igb_t *igb)
3382 3384 {
3383 3385 mutex_enter(&igb->watchdog_lock);
3384 3386
3385 3387 if (igb->watchdog_start)
3386 3388 igb_arm_watchdog_timer(igb);
3387 3389
3388 3390 mutex_exit(&igb->watchdog_lock);
3389 3391 }
3390 3392
3391 3393 /*
3392 3394 * igb_stop_watchdog_timer - Stop the driver watchdog timer
3393 3395 */
3394 3396 static void
3395 3397 igb_stop_watchdog_timer(igb_t *igb)
3396 3398 {
3397 3399 timeout_id_t tid;
3398 3400
3399 3401 mutex_enter(&igb->watchdog_lock);
3400 3402
3401 3403 igb->watchdog_start = B_FALSE;
3402 3404 tid = igb->watchdog_tid;
3403 3405 igb->watchdog_tid = 0;
3404 3406
3405 3407 mutex_exit(&igb->watchdog_lock);
3406 3408
3407 3409 if (tid != 0)
3408 3410 (void) untimeout(tid);
3409 3411 }
3410 3412
3411 3413 /*
3412 3414 * igb_start_link_timer - Start the link setup timer
3413 3415 */
3414 3416 static void
3415 3417 igb_start_link_timer(struct igb *igb)
3416 3418 {
3417 3419 struct e1000_hw *hw = &igb->hw;
3418 3420 clock_t link_timeout;
3419 3421
3420 3422 if (hw->mac.autoneg)
3421 3423 link_timeout = PHY_AUTO_NEG_LIMIT *
3422 3424 drv_usectohz(100000);
3423 3425 else
3424 3426 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
3425 3427
3426 3428 mutex_enter(&igb->link_lock);
3427 3429 if (hw->phy.autoneg_wait_to_complete) {
3428 3430 igb->link_complete = B_TRUE;
3429 3431 } else {
3430 3432 igb->link_complete = B_FALSE;
3431 3433 igb->link_tid = timeout(igb_link_timer, (void *)igb,
3432 3434 link_timeout);
3433 3435 }
3434 3436 mutex_exit(&igb->link_lock);
3435 3437 }
3436 3438
3437 3439 /*
3438 3440 * igb_stop_link_timer - Stop the link setup timer
3439 3441 */
3440 3442 static void
3441 3443 igb_stop_link_timer(struct igb *igb)
3442 3444 {
3443 3445 timeout_id_t tid;
3444 3446
3445 3447 mutex_enter(&igb->link_lock);
3446 3448 igb->link_complete = B_TRUE;
3447 3449 tid = igb->link_tid;
3448 3450 igb->link_tid = 0;
3449 3451 mutex_exit(&igb->link_lock);
3450 3452
3451 3453 if (tid != 0)
3452 3454 (void) untimeout(tid);
3453 3455 }
3454 3456
3455 3457 /*
3456 3458 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts
3457 3459 */
3458 3460 static void
3459 3461 igb_disable_adapter_interrupts(igb_t *igb)
3460 3462 {
3461 3463 struct e1000_hw *hw = &igb->hw;
3462 3464
3463 3465 /*
3464 3466 * Set the IMC register to mask all the interrupts,
3465 3467 * including the tx interrupts.
3466 3468 */
3467 3469 E1000_WRITE_REG(hw, E1000_IMC, ~0);
3468 3470 E1000_WRITE_REG(hw, E1000_IAM, 0);
3469 3471
3470 3472 /*
3471 3473 * Additional disabling for MSI-X
3472 3474 */
3473 3475 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3474 3476 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
3475 3477 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3476 3478 E1000_WRITE_REG(hw, E1000_EIAM, 0);
3477 3479 }
3478 3480
3479 3481 E1000_WRITE_FLUSH(hw);
3480 3482 }
3481 3483
3482 3484 /*
3483 3485 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580
3484 3486 */
3485 3487 static void
3486 3488 igb_enable_adapter_interrupts_82580(igb_t *igb)
3487 3489 {
3488 3490 struct e1000_hw *hw = &igb->hw;
3489 3491
3490 3492 /* Clear any pending interrupts */
3491 3493 (void) E1000_READ_REG(hw, E1000_ICR);
3492 3494 igb->ims_mask |= E1000_IMS_DRSTA;
3493 3495
3494 3496 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3495 3497
3496 3498 /* Interrupt enabling for MSI-X */
3497 3499 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3498 3500 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3499 3501 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA);
3500 3502 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3501 3503 } else { /* Interrupt enabling for MSI and legacy */
3502 3504 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3503 3505 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3504 3506 igb->ims_mask |= E1000_IMS_DRSTA;
3505 3507 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3506 3508 }
3507 3509
3508 3510 /* Disable auto-mask for ICR interrupt bits */
3509 3511 E1000_WRITE_REG(hw, E1000_IAM, 0);
3510 3512
3511 3513 E1000_WRITE_FLUSH(hw);
3512 3514 }
3513 3515
3514 3516 /*
3515 3517 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576
3516 3518 */
3517 3519 static void
3518 3520 igb_enable_adapter_interrupts_82576(igb_t *igb)
3519 3521 {
3520 3522 struct e1000_hw *hw = &igb->hw;
3521 3523
3522 3524 /* Clear any pending interrupts */
3523 3525 (void) E1000_READ_REG(hw, E1000_ICR);
3524 3526
3525 3527 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3526 3528
3527 3529 /* Interrupt enabling for MSI-X */
3528 3530 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3529 3531 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3530 3532 igb->ims_mask = E1000_IMS_LSC;
3531 3533 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3532 3534 } else {
3533 3535 /* Interrupt enabling for MSI and legacy */
3534 3536 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3535 3537 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3536 3538 E1000_WRITE_REG(hw, E1000_IMS,
3537 3539 (IMS_ENABLE_MASK | E1000_IMS_TXQE));
3538 3540 }
3539 3541
3540 3542 /* Disable auto-mask for ICR interrupt bits */
3541 3543 E1000_WRITE_REG(hw, E1000_IAM, 0);
3542 3544
3543 3545 E1000_WRITE_FLUSH(hw);
3544 3546 }
3545 3547
3546 3548 /*
3547 3549 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575
3548 3550 */
3549 3551 static void
3550 3552 igb_enable_adapter_interrupts_82575(igb_t *igb)
3551 3553 {
3552 3554 struct e1000_hw *hw = &igb->hw;
3553 3555 uint32_t reg;
3554 3556
3555 3557 /* Clear any pending interrupts */
3556 3558 (void) E1000_READ_REG(hw, E1000_ICR);
3557 3559
3558 3560 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3559 3561 /* Interrupt enabling for MSI-X */
3560 3562 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3561 3563 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3562 3564 igb->ims_mask = E1000_IMS_LSC;
3563 3565 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3564 3566
3565 3567 /* Enable MSI-X PBA support */
3566 3568 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3567 3569 reg |= E1000_CTRL_EXT_PBA_CLR;
3568 3570
3569 3571 /* Non-selective interrupt clear-on-read */
3570 3572 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */
3571 3573
3572 3574 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3573 3575 } else {
3574 3576 /* Interrupt enabling for MSI and legacy */
3575 3577 igb->ims_mask = IMS_ENABLE_MASK;
3576 3578 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3577 3579 }
3578 3580
3579 3581 E1000_WRITE_FLUSH(hw);
3580 3582 }
3581 3583
3582 3584 /*
3583 3585 * Loopback Support
3584 3586 */
3585 3587 static lb_property_t lb_normal =
3586 3588 { normal, "normal", IGB_LB_NONE };
3587 3589 static lb_property_t lb_external =
3588 3590 { external, "External", IGB_LB_EXTERNAL };
3589 3591 static lb_property_t lb_phy =
3590 3592 { internal, "PHY", IGB_LB_INTERNAL_PHY };
3591 3593 static lb_property_t lb_serdes =
3592 3594 { internal, "SerDes", IGB_LB_INTERNAL_SERDES };
3593 3595
3594 3596 enum ioc_reply
3595 3597 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp)
3596 3598 {
3597 3599 lb_info_sz_t *lbsp;
3598 3600 lb_property_t *lbpp;
3599 3601 struct e1000_hw *hw;
3600 3602 uint32_t *lbmp;
3601 3603 uint32_t size;
3602 3604 uint32_t value;
3603 3605
3604 3606 hw = &igb->hw;
3605 3607
3606 3608 if (mp->b_cont == NULL)
3607 3609 return (IOC_INVAL);
3608 3610
3609 3611 switch (iocp->ioc_cmd) {
3610 3612 default:
3611 3613 return (IOC_INVAL);
3612 3614
3613 3615 case LB_GET_INFO_SIZE:
3614 3616 size = sizeof (lb_info_sz_t);
3615 3617 if (iocp->ioc_count != size)
3616 3618 return (IOC_INVAL);
3617 3619
3618 3620 value = sizeof (lb_normal);
3619 3621 if (hw->phy.media_type == e1000_media_type_copper)
3620 3622 value += sizeof (lb_phy);
3621 3623 else
3622 3624 value += sizeof (lb_serdes);
3623 3625 value += sizeof (lb_external);
3624 3626
3625 3627 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
3626 3628 *lbsp = value;
3627 3629 break;
3628 3630
3629 3631 case LB_GET_INFO:
3630 3632 value = sizeof (lb_normal);
3631 3633 if (hw->phy.media_type == e1000_media_type_copper)
3632 3634 value += sizeof (lb_phy);
3633 3635 else
3634 3636 value += sizeof (lb_serdes);
3635 3637 value += sizeof (lb_external);
3636 3638
3637 3639 size = value;
3638 3640 if (iocp->ioc_count != size)
3639 3641 return (IOC_INVAL);
3640 3642
3641 3643 value = 0;
3642 3644 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
3643 3645
3644 3646 lbpp[value++] = lb_normal;
3645 3647 if (hw->phy.media_type == e1000_media_type_copper)
3646 3648 lbpp[value++] = lb_phy;
3647 3649 else
3648 3650 lbpp[value++] = lb_serdes;
3649 3651 lbpp[value++] = lb_external;
3650 3652 break;
3651 3653
3652 3654 case LB_GET_MODE:
3653 3655 size = sizeof (uint32_t);
3654 3656 if (iocp->ioc_count != size)
3655 3657 return (IOC_INVAL);
3656 3658
3657 3659 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3658 3660 *lbmp = igb->loopback_mode;
3659 3661 break;
3660 3662
3661 3663 case LB_SET_MODE:
3662 3664 size = 0;
3663 3665 if (iocp->ioc_count != sizeof (uint32_t))
3664 3666 return (IOC_INVAL);
3665 3667
3666 3668 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3667 3669 if (!igb_set_loopback_mode(igb, *lbmp))
3668 3670 return (IOC_INVAL);
3669 3671 break;
3670 3672 }
3671 3673
3672 3674 iocp->ioc_count = size;
3673 3675 iocp->ioc_error = 0;
3674 3676
3675 3677 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3676 3678 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3677 3679 return (IOC_INVAL);
3678 3680 }
3679 3681
3680 3682 return (IOC_REPLY);
3681 3683 }
3682 3684
3683 3685 /*
3684 3686 * igb_set_loopback_mode - Setup loopback based on the loopback mode
3685 3687 */
3686 3688 static boolean_t
3687 3689 igb_set_loopback_mode(igb_t *igb, uint32_t mode)
3688 3690 {
3689 3691 struct e1000_hw *hw;
3690 3692 int i;
3691 3693
3692 3694 if (mode == igb->loopback_mode)
3693 3695 return (B_TRUE);
3694 3696
3695 3697 hw = &igb->hw;
3696 3698
3697 3699 igb->loopback_mode = mode;
3698 3700
3699 3701 if (mode == IGB_LB_NONE) {
3700 3702 /* Reset the chip */
3701 3703 hw->phy.autoneg_wait_to_complete = B_TRUE;
3702 3704 (void) igb_reset(igb);
3703 3705 hw->phy.autoneg_wait_to_complete = B_FALSE;
3704 3706 return (B_TRUE);
3705 3707 }
3706 3708
3707 3709 mutex_enter(&igb->gen_lock);
3708 3710
3709 3711 switch (mode) {
3710 3712 default:
3711 3713 mutex_exit(&igb->gen_lock);
3712 3714 return (B_FALSE);
3713 3715
3714 3716 case IGB_LB_EXTERNAL:
3715 3717 igb_set_external_loopback(igb);
3716 3718 break;
3717 3719
3718 3720 case IGB_LB_INTERNAL_PHY:
3719 3721 igb_set_internal_phy_loopback(igb);
3720 3722 break;
3721 3723
3722 3724 case IGB_LB_INTERNAL_SERDES:
3723 3725 igb_set_internal_serdes_loopback(igb);
3724 3726 break;
3725 3727 }
3726 3728
3727 3729 mutex_exit(&igb->gen_lock);
3728 3730
3729 3731 /*
3730 3732 * When external loopback is set, wait up to 1000ms to get the link up.
3731 3733 * According to test, 1000ms can work and it's an experimental value.
3732 3734 */
3733 3735 if (mode == IGB_LB_EXTERNAL) {
3734 3736 for (i = 0; i <= 10; i++) {
3735 3737 mutex_enter(&igb->gen_lock);
3736 3738 (void) igb_link_check(igb);
3737 3739 mutex_exit(&igb->gen_lock);
3738 3740
3739 3741 if (igb->link_state == LINK_STATE_UP)
3740 3742 break;
3741 3743
3742 3744 msec_delay(100);
3743 3745 }
3744 3746
3745 3747 if (igb->link_state != LINK_STATE_UP) {
3746 3748 /*
3747 3749 * Does not support external loopback.
3748 3750 * Reset driver to loopback none.
3749 3751 */
3750 3752 igb->loopback_mode = IGB_LB_NONE;
3751 3753
3752 3754 /* Reset the chip */
3753 3755 hw->phy.autoneg_wait_to_complete = B_TRUE;
3754 3756 (void) igb_reset(igb);
3755 3757 hw->phy.autoneg_wait_to_complete = B_FALSE;
3756 3758
3757 3759 IGB_DEBUGLOG_0(igb, "Set external loopback failed, "
3758 3760 "reset to loopback none.");
3759 3761
3760 3762 return (B_FALSE);
3761 3763 }
3762 3764 }
3763 3765
3764 3766 return (B_TRUE);
3765 3767 }
3766 3768
3767 3769 /*
3768 3770 * igb_set_external_loopback - Set the external loopback mode
3769 3771 */
3770 3772 static void
3771 3773 igb_set_external_loopback(igb_t *igb)
3772 3774 {
3773 3775 struct e1000_hw *hw;
3774 3776 uint32_t ctrl_ext;
3775 3777
3776 3778 hw = &igb->hw;
3777 3779
3778 3780 /* Set link mode to PHY (00b) in the Extended Control register */
3779 3781 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3780 3782 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3781 3783 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3782 3784
3783 3785 (void) e1000_write_phy_reg(hw, 0x0, 0x0140);
3784 3786 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00);
3785 3787 (void) e1000_write_phy_reg(hw, 0x12, 0x1610);
3786 3788 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c);
3787 3789 }
3788 3790
3789 3791 /*
3790 3792 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode
3791 3793 */
3792 3794 static void
3793 3795 igb_set_internal_phy_loopback(igb_t *igb)
3794 3796 {
3795 3797 struct e1000_hw *hw;
3796 3798 uint32_t ctrl_ext;
3797 3799 uint16_t phy_ctrl;
3798 3800 uint16_t phy_pconf;
3799 3801
3800 3802 hw = &igb->hw;
3801 3803
3802 3804 /* Set link mode to PHY (00b) in the Extended Control register */
3803 3805 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3804 3806 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3805 3807 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3806 3808
3807 3809 /*
3808 3810 * Set PHY control register (0x4140):
3809 3811 * Set full duplex mode
3810 3812 * Set loopback bit
3811 3813 * Clear auto-neg enable bit
3812 3814 * Set PHY speed
3813 3815 */
3814 3816 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK;
3815 3817 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
3816 3818
3817 3819 /* Set the link disable bit in the Port Configuration register */
3818 3820 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf);
3819 3821 phy_pconf |= (uint16_t)1 << 14;
3820 3822 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf);
3821 3823 }
3822 3824
3823 3825 /*
3824 3826 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode
3825 3827 */
3826 3828 static void
3827 3829 igb_set_internal_serdes_loopback(igb_t *igb)
3828 3830 {
3829 3831 struct e1000_hw *hw;
3830 3832 uint32_t ctrl_ext;
3831 3833 uint32_t ctrl;
3832 3834 uint32_t pcs_lctl;
3833 3835 uint32_t connsw;
3834 3836
3835 3837 hw = &igb->hw;
3836 3838
3837 3839 /* Set link mode to SerDes (11b) in the Extended Control register */
3838 3840 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3839 3841 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
3840 3842 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3841 3843
3842 3844 /* Configure the SerDes to loopback */
3843 3845 E1000_WRITE_REG(hw, E1000_SCTL, 0x410);
3844 3846
3845 3847 /* Set Device Control register */
3846 3848 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3847 3849 ctrl |= (E1000_CTRL_FD | /* Force full duplex */
3848 3850 E1000_CTRL_SLU); /* Force link up */
3849 3851 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */
3850 3852 E1000_CTRL_TFCE | /* Disable transmit flow control */
3851 3853 E1000_CTRL_LRST); /* Clear link reset */
3852 3854 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3853 3855
3854 3856 /* Set PCS Link Control register */
3855 3857 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL);
3856 3858 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK |
3857 3859 E1000_PCS_LCTL_FSD |
3858 3860 E1000_PCS_LCTL_FDV_FULL |
3859 3861 E1000_PCS_LCTL_FLV_LINK_UP);
3860 3862 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE;
3861 3863 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl);
3862 3864
3863 3865 /* Set the Copper/Fiber Switch Control - CONNSW register */
3864 3866 connsw = E1000_READ_REG(hw, E1000_CONNSW);
3865 3867 connsw &= ~E1000_CONNSW_ENRGSRC;
3866 3868 E1000_WRITE_REG(hw, E1000_CONNSW, connsw);
3867 3869 }
3868 3870
3869 3871 #pragma inline(igb_intr_rx_work)
3870 3872 /*
3871 3873 * igb_intr_rx_work - rx processing of ISR
3872 3874 */
3873 3875 static void
3874 3876 igb_intr_rx_work(igb_rx_ring_t *rx_ring)
3875 3877 {
3876 3878 mblk_t *mp;
3877 3879
3878 3880 mutex_enter(&rx_ring->rx_lock);
3879 3881 mp = igb_rx(rx_ring, IGB_NO_POLL);
3880 3882 mutex_exit(&rx_ring->rx_lock);
3881 3883
3882 3884 if (mp != NULL)
3883 3885 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp,
3884 3886 rx_ring->ring_gen_num);
3885 3887 }
3886 3888
3887 3889 #pragma inline(igb_intr_tx_work)
3888 3890 /*
3889 3891 * igb_intr_tx_work - tx processing of ISR
3890 3892 */
3891 3893 static void
3892 3894 igb_intr_tx_work(igb_tx_ring_t *tx_ring)
3893 3895 {
3894 3896 igb_t *igb = tx_ring->igb;
3895 3897
3896 3898 /* Recycle the tx descriptors */
3897 3899 tx_ring->tx_recycle(tx_ring);
3898 3900
3899 3901 /* Schedule the re-transmit */
3900 3902 if (tx_ring->reschedule &&
3901 3903 (tx_ring->tbd_free >= igb->tx_resched_thresh)) {
3902 3904 tx_ring->reschedule = B_FALSE;
3903 3905 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle);
3904 3906 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
3905 3907 }
3906 3908 }
3907 3909
3908 3910 #pragma inline(igb_intr_link_work)
3909 3911 /*
3910 3912 * igb_intr_link_work - link-status-change processing of ISR
3911 3913 */
3912 3914 static void
3913 3915 igb_intr_link_work(igb_t *igb)
3914 3916 {
3915 3917 boolean_t link_changed;
3916 3918
3917 3919 igb_stop_watchdog_timer(igb);
3918 3920
3919 3921 mutex_enter(&igb->gen_lock);
3920 3922
3921 3923 /*
3922 3924 * Because we got a link-status-change interrupt, force
3923 3925 * e1000_check_for_link() to look at phy
3924 3926 */
3925 3927 igb->hw.mac.get_link_status = B_TRUE;
3926 3928
3927 3929 /* igb_link_check takes care of link status change */
3928 3930 link_changed = igb_link_check(igb);
3929 3931
3930 3932 /* Get new phy state */
3931 3933 igb_get_phy_state(igb);
3932 3934
3933 3935 mutex_exit(&igb->gen_lock);
3934 3936
3935 3937 if (link_changed)
3936 3938 mac_link_update(igb->mac_hdl, igb->link_state);
3937 3939
3938 3940 igb_start_watchdog_timer(igb);
3939 3941 }
3940 3942
3941 3943 /*
3942 3944 * igb_intr_legacy - Interrupt handler for legacy interrupts
3943 3945 */
3944 3946 static uint_t
3945 3947 igb_intr_legacy(void *arg1, void *arg2)
3946 3948 {
3947 3949 igb_t *igb = (igb_t *)arg1;
3948 3950 igb_tx_ring_t *tx_ring;
3949 3951 uint32_t icr;
3950 3952 mblk_t *mp;
3951 3953 boolean_t tx_reschedule;
3952 3954 boolean_t link_changed;
3953 3955 uint_t result;
3954 3956
3955 3957 _NOTE(ARGUNUSED(arg2));
3956 3958
3957 3959 mutex_enter(&igb->gen_lock);
3958 3960
3959 3961 if (igb->igb_state & IGB_SUSPENDED) {
3960 3962 mutex_exit(&igb->gen_lock);
3961 3963 return (DDI_INTR_UNCLAIMED);
3962 3964 }
3963 3965
3964 3966 mp = NULL;
3965 3967 tx_reschedule = B_FALSE;
3966 3968 link_changed = B_FALSE;
3967 3969 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
3968 3970
3969 3971 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3970 3972 mutex_exit(&igb->gen_lock);
3971 3973 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3972 3974 atomic_or_32(&igb->igb_state, IGB_ERROR);
3973 3975 return (DDI_INTR_UNCLAIMED);
3974 3976 }
3975 3977
3976 3978 if (icr & E1000_ICR_INT_ASSERTED) {
3977 3979 /*
3978 3980 * E1000_ICR_INT_ASSERTED bit was set:
3979 3981 * Read(Clear) the ICR, claim this interrupt,
3980 3982 * look for work to do.
3981 3983 */
3982 3984 ASSERT(igb->num_rx_rings == 1);
3983 3985 ASSERT(igb->num_tx_rings == 1);
3984 3986
3985 3987 /* Make sure all interrupt causes cleared */
3986 3988 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
3987 3989
3988 3990 if (icr & E1000_ICR_RXT0) {
3989 3991 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL);
3990 3992 }
3991 3993
3992 3994 if (icr & E1000_ICR_TXDW) {
3993 3995 tx_ring = &igb->tx_rings[0];
3994 3996
3995 3997 /* Recycle the tx descriptors */
3996 3998 tx_ring->tx_recycle(tx_ring);
3997 3999
3998 4000 /* Schedule the re-transmit */
3999 4001 tx_reschedule = (tx_ring->reschedule &&
4000 4002 (tx_ring->tbd_free >= igb->tx_resched_thresh));
4001 4003 }
4002 4004
4003 4005 if (icr & E1000_ICR_LSC) {
4004 4006 /*
4005 4007 * Because we got a link-status-change interrupt, force
4006 4008 * e1000_check_for_link() to look at phy
4007 4009 */
4008 4010 igb->hw.mac.get_link_status = B_TRUE;
4009 4011
4010 4012 /* igb_link_check takes care of link status change */
4011 4013 link_changed = igb_link_check(igb);
4012 4014
4013 4015 /* Get new phy state */
4014 4016 igb_get_phy_state(igb);
4015 4017 }
4016 4018
4017 4019 if (icr & E1000_ICR_DRSTA) {
4018 4020 /* 82580 Full Device Reset needed */
4019 4021 atomic_or_32(&igb->igb_state, IGB_STALL);
4020 4022 }
4021 4023
4022 4024 result = DDI_INTR_CLAIMED;
4023 4025 } else {
4024 4026 /*
4025 4027 * E1000_ICR_INT_ASSERTED bit was not set:
4026 4028 * Don't claim this interrupt.
4027 4029 */
4028 4030 result = DDI_INTR_UNCLAIMED;
4029 4031 }
4030 4032
4031 4033 mutex_exit(&igb->gen_lock);
4032 4034
4033 4035 /*
4034 4036 * Do the following work outside of the gen_lock
4035 4037 */
4036 4038 if (mp != NULL)
4037 4039 mac_rx(igb->mac_hdl, NULL, mp);
4038 4040
4039 4041 if (tx_reschedule) {
4040 4042 tx_ring->reschedule = B_FALSE;
4041 4043 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle);
4042 4044 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4043 4045 }
4044 4046
4045 4047 if (link_changed)
4046 4048 mac_link_update(igb->mac_hdl, igb->link_state);
4047 4049
4048 4050 return (result);
4049 4051 }
4050 4052
4051 4053 /*
4052 4054 * igb_intr_msi - Interrupt handler for MSI
4053 4055 */
4054 4056 static uint_t
4055 4057 igb_intr_msi(void *arg1, void *arg2)
4056 4058 {
4057 4059 igb_t *igb = (igb_t *)arg1;
4058 4060 uint32_t icr;
4059 4061
4060 4062 _NOTE(ARGUNUSED(arg2));
4061 4063
4062 4064 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4063 4065
4064 4066 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4065 4067 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4066 4068 atomic_or_32(&igb->igb_state, IGB_ERROR);
4067 4069 return (DDI_INTR_CLAIMED);
4068 4070 }
4069 4071
4070 4072 /* Make sure all interrupt causes cleared */
4071 4073 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4072 4074
4073 4075 /*
4074 4076 * For MSI interrupt, we have only one vector,
4075 4077 * so we have only one rx ring and one tx ring enabled.
4076 4078 */
4077 4079 ASSERT(igb->num_rx_rings == 1);
4078 4080 ASSERT(igb->num_tx_rings == 1);
4079 4081
4080 4082 if (icr & E1000_ICR_RXT0) {
4081 4083 igb_intr_rx_work(&igb->rx_rings[0]);
4082 4084 }
4083 4085
4084 4086 if (icr & E1000_ICR_TXDW) {
4085 4087 igb_intr_tx_work(&igb->tx_rings[0]);
4086 4088 }
4087 4089
4088 4090 if (icr & E1000_ICR_LSC) {
4089 4091 igb_intr_link_work(igb);
4090 4092 }
4091 4093
4092 4094 if (icr & E1000_ICR_DRSTA) {
4093 4095 /* 82580 Full Device Reset needed */
4094 4096 atomic_or_32(&igb->igb_state, IGB_STALL);
4095 4097 }
4096 4098
4097 4099 return (DDI_INTR_CLAIMED);
4098 4100 }
4099 4101
4100 4102 /*
4101 4103 * igb_intr_rx - Interrupt handler for rx
4102 4104 */
4103 4105 static uint_t
4104 4106 igb_intr_rx(void *arg1, void *arg2)
4105 4107 {
4106 4108 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1;
4107 4109
4108 4110 _NOTE(ARGUNUSED(arg2));
4109 4111
4110 4112 /*
4111 4113 * Only used via MSI-X vector so don't check cause bits
4112 4114 * and only clean the given ring.
4113 4115 */
4114 4116 igb_intr_rx_work(rx_ring);
4115 4117
4116 4118 return (DDI_INTR_CLAIMED);
4117 4119 }
4118 4120
4119 4121 /*
4120 4122 * igb_intr_tx - Interrupt handler for tx
4121 4123 */
4122 4124 static uint_t
4123 4125 igb_intr_tx(void *arg1, void *arg2)
4124 4126 {
4125 4127 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1;
4126 4128
4127 4129 _NOTE(ARGUNUSED(arg2));
4128 4130
4129 4131 /*
4130 4132 * Only used via MSI-X vector so don't check cause bits
4131 4133 * and only clean the given ring.
4132 4134 */
4133 4135 igb_intr_tx_work(tx_ring);
4134 4136
4135 4137 return (DDI_INTR_CLAIMED);
4136 4138 }
4137 4139
4138 4140 /*
4139 4141 * igb_intr_tx_other - Interrupt handler for both tx and other
4140 4142 *
4141 4143 */
4142 4144 static uint_t
4143 4145 igb_intr_tx_other(void *arg1, void *arg2)
4144 4146 {
4145 4147 igb_t *igb = (igb_t *)arg1;
4146 4148 uint32_t icr;
4147 4149
4148 4150 _NOTE(ARGUNUSED(arg2));
4149 4151
4150 4152 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4151 4153
4152 4154 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4153 4155 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4154 4156 atomic_or_32(&igb->igb_state, IGB_ERROR);
4155 4157 return (DDI_INTR_CLAIMED);
4156 4158 }
4157 4159
4158 4160 /*
4159 4161 * Look for tx reclaiming work first. Remember, in the
4160 4162 * case of only interrupt sharing, only one tx ring is
4161 4163 * used
4162 4164 */
4163 4165 igb_intr_tx_work(&igb->tx_rings[0]);
4164 4166
4165 4167 /*
4166 4168 * Check for "other" causes.
4167 4169 */
4168 4170 if (icr & E1000_ICR_LSC) {
4169 4171 igb_intr_link_work(igb);
4170 4172 }
4171 4173
4172 4174 /*
4173 4175 * The DOUTSYNC bit indicates a tx packet dropped because
4174 4176 * DMA engine gets "out of sync". There isn't a real fix
4175 4177 * for this. The Intel recommendation is to count the number
4176 4178 * of occurrences so user can detect when it is happening.
4177 4179 * The issue is non-fatal and there's no recovery action
4178 4180 * available.
4179 4181 */
4180 4182 if (icr & E1000_ICR_DOUTSYNC) {
4181 4183 IGB_STAT(igb->dout_sync);
4182 4184 }
4183 4185
4184 4186 if (icr & E1000_ICR_DRSTA) {
4185 4187 /* 82580 Full Device Reset needed */
4186 4188 atomic_or_32(&igb->igb_state, IGB_STALL);
4187 4189 }
4188 4190
4189 4191 return (DDI_INTR_CLAIMED);
4190 4192 }
4191 4193
4192 4194 /*
4193 4195 * igb_alloc_intrs - Allocate interrupts for the driver
4194 4196 *
4195 4197 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4196 4198 * if not successful, try Legacy.
4197 4199 * igb->intr_force can be used to force sequence to start with
4198 4200 * any of the 3 types.
4199 4201 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4200 4202 */
4201 4203 static int
4202 4204 igb_alloc_intrs(igb_t *igb)
4203 4205 {
4204 4206 dev_info_t *devinfo;
4205 4207 int intr_types;
4206 4208 int rc;
4207 4209
4208 4210 devinfo = igb->dip;
4209 4211
4210 4212 /* Get supported interrupt types */
4211 4213 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4212 4214
4213 4215 if (rc != DDI_SUCCESS) {
4214 4216 igb_log(igb,
4215 4217 "Get supported interrupt types failed: %d", rc);
4216 4218 return (IGB_FAILURE);
4217 4219 }
4218 4220 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types);
4219 4221
4220 4222 igb->intr_type = 0;
4221 4223
4222 4224 /* Install MSI-X interrupts */
4223 4225 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
4224 4226 (igb->intr_force <= IGB_INTR_MSIX)) {
4225 4227 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX);
4226 4228
4227 4229 if (rc == IGB_SUCCESS)
4228 4230 return (IGB_SUCCESS);
4229 4231
4230 4232 igb_log(igb,
4231 4233 "Allocate MSI-X failed, trying MSI interrupts...");
4232 4234 }
4233 4235
4234 4236 /* MSI-X not used, force rings to 1 */
4235 4237 igb->num_rx_rings = 1;
4236 4238 igb->num_tx_rings = 1;
4237 4239 igb_log(igb,
4238 4240 "MSI-X not used, force rx and tx queue number to 1");
4239 4241
4240 4242 /* Install MSI interrupts */
4241 4243 if ((intr_types & DDI_INTR_TYPE_MSI) &&
4242 4244 (igb->intr_force <= IGB_INTR_MSI)) {
4243 4245 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI);
4244 4246
4245 4247 if (rc == IGB_SUCCESS)
4246 4248 return (IGB_SUCCESS);
4247 4249
4248 4250 igb_log(igb,
4249 4251 "Allocate MSI failed, trying Legacy interrupts...");
4250 4252 }
4251 4253
4252 4254 /* Install legacy interrupts */
4253 4255 if (intr_types & DDI_INTR_TYPE_FIXED) {
4254 4256 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED);
4255 4257
4256 4258 if (rc == IGB_SUCCESS)
4257 4259 return (IGB_SUCCESS);
4258 4260
4259 4261 igb_log(igb,
4260 4262 "Allocate Legacy interrupts failed");
4261 4263 }
4262 4264
4263 4265 /* If none of the 3 types succeeded, return failure */
4264 4266 return (IGB_FAILURE);
4265 4267 }
4266 4268
4267 4269 /*
4268 4270 * igb_alloc_intr_handles - Allocate interrupt handles.
4269 4271 *
4270 4272 * For legacy and MSI, only 1 handle is needed. For MSI-X,
4271 4273 * if fewer than 2 handles are available, return failure.
4272 4274 * Upon success, this sets the number of Rx rings to a number that
4273 4275 * matches the handles available for Rx interrupts.
4274 4276 */
4275 4277 static int
4276 4278 igb_alloc_intr_handles(igb_t *igb, int intr_type)
4277 4279 {
4278 4280 dev_info_t *devinfo;
4279 4281 int orig, request, count, avail, actual;
4280 4282 int diff, minimum;
4281 4283 int rc;
4282 4284
4283 4285 devinfo = igb->dip;
4284 4286
4285 4287 switch (intr_type) {
4286 4288 case DDI_INTR_TYPE_FIXED:
4287 4289 request = 1; /* Request 1 legacy interrupt handle */
4288 4290 minimum = 1;
4289 4291 IGB_DEBUGLOG_0(igb, "interrupt type: legacy");
4290 4292 break;
4291 4293
4292 4294 case DDI_INTR_TYPE_MSI:
4293 4295 request = 1; /* Request 1 MSI interrupt handle */
4294 4296 minimum = 1;
4295 4297 IGB_DEBUGLOG_0(igb, "interrupt type: MSI");
4296 4298 break;
4297 4299
4298 4300 case DDI_INTR_TYPE_MSIX:
4299 4301 /*
4300 4302 * Number of vectors for the adapter is
4301 4303 * # rx rings + # tx rings
4302 4304 * One of tx vectors is for tx & other
4303 4305 */
4304 4306 request = igb->num_rx_rings + igb->num_tx_rings;
4305 4307 orig = request;
4306 4308 minimum = 2;
4307 4309 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X");
4308 4310 break;
4309 4311
4310 4312 default:
4311 4313 igb_log(igb,
4312 4314 "invalid call to igb_alloc_intr_handles(): %d\n",
4313 4315 intr_type);
4314 4316 return (IGB_FAILURE);
4315 4317 }
4316 4318 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d",
4317 4319 request, minimum);
4318 4320
4319 4321 /*
4320 4322 * Get number of supported interrupts
4321 4323 */
4322 4324 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
4323 4325 if ((rc != DDI_SUCCESS) || (count < minimum)) {
4324 4326 igb_log(igb,
4325 4327 "Get supported interrupt number failed. "
4326 4328 "Return: %d, count: %d", rc, count);
4327 4329 return (IGB_FAILURE);
4328 4330 }
4329 4331 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count);
4330 4332
4331 4333 /*
4332 4334 * Get number of available interrupts
4333 4335 */
4334 4336 rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
4335 4337 if ((rc != DDI_SUCCESS) || (avail < minimum)) {
4336 4338 igb_log(igb,
4337 4339 "Get available interrupt number failed. "
4338 4340 "Return: %d, available: %d", rc, avail);
4339 4341 return (IGB_FAILURE);
4340 4342 }
4341 4343 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail);
4342 4344
4343 4345 if (avail < request) {
4344 4346 igb_log(igb, "Request %d handles, %d available",
4345 4347 request, avail);
4346 4348 request = avail;
4347 4349 }
4348 4350
4349 4351 actual = 0;
4350 4352 igb->intr_cnt = 0;
4351 4353
4352 4354 /*
4353 4355 * Allocate an array of interrupt handles
4354 4356 */
4355 4357 igb->intr_size = request * sizeof (ddi_intr_handle_t);
4356 4358 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP);
4357 4359
4358 4360 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0,
4359 4361 request, &actual, DDI_INTR_ALLOC_NORMAL);
4360 4362 if (rc != DDI_SUCCESS) {
4361 4363 igb_log(igb, "Allocate interrupts failed. "
4362 4364 "return: %d, request: %d, actual: %d",
4363 4365 rc, request, actual);
4364 4366 goto alloc_handle_fail;
4365 4367 }
4366 4368 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual);
4367 4369
4368 4370 igb->intr_cnt = actual;
4369 4371
4370 4372 if (actual < minimum) {
4371 4373 igb_log(igb, "Insufficient interrupt handles allocated: %d",
4372 4374 actual);
4373 4375 goto alloc_handle_fail;
4374 4376 }
4375 4377
4376 4378 /*
4377 4379 * For MSI-X, actual might force us to reduce number of tx & rx rings
4378 4380 */
4379 4381 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) {
4380 4382 diff = orig - actual;
4381 4383 if (diff < igb->num_tx_rings) {
4382 4384 igb_log(igb,
4383 4385 "MSI-X vectors force Tx queue number to %d",
4384 4386 igb->num_tx_rings - diff);
4385 4387 igb->num_tx_rings -= diff;
4386 4388 } else {
4387 4389 igb_log(igb,
4388 4390 "MSI-X vectors force Tx queue number to 1");
4389 4391 igb->num_tx_rings = 1;
4390 4392
4391 4393 igb_log(igb,
4392 4394 "MSI-X vectors force Rx queue number to %d",
4393 4395 actual - 1);
4394 4396 igb->num_rx_rings = actual - 1;
4395 4397 }
4396 4398 }
4397 4399
4398 4400 /*
4399 4401 * Get priority for first vector, assume remaining are all the same
4400 4402 */
4401 4403 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri);
4402 4404 if (rc != DDI_SUCCESS) {
4403 4405 igb_log(igb,
4404 4406 "Get interrupt priority failed: %d", rc);
4405 4407 goto alloc_handle_fail;
4406 4408 }
4407 4409
4408 4410 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap);
4409 4411 if (rc != DDI_SUCCESS) {
4410 4412 igb_log(igb,
4411 4413 "Get interrupt cap failed: %d", rc);
4412 4414 goto alloc_handle_fail;
4413 4415 }
4414 4416
4415 4417 igb->intr_type = intr_type;
4416 4418
4417 4419 return (IGB_SUCCESS);
4418 4420
4419 4421 alloc_handle_fail:
4420 4422 igb_rem_intrs(igb);
4421 4423
4422 4424 return (IGB_FAILURE);
4423 4425 }
4424 4426
4425 4427 /*
4426 4428 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type
4427 4429 *
4428 4430 * Before adding the interrupt handlers, the interrupt vectors have
4429 4431 * been allocated, and the rx/tx rings have also been allocated.
4430 4432 */
4431 4433 static int
4432 4434 igb_add_intr_handlers(igb_t *igb)
4433 4435 {
4434 4436 igb_rx_ring_t *rx_ring;
4435 4437 igb_tx_ring_t *tx_ring;
4436 4438 int vector;
4437 4439 int rc;
4438 4440 int i;
4439 4441
4440 4442 vector = 0;
4441 4443
4442 4444 switch (igb->intr_type) {
4443 4445 case DDI_INTR_TYPE_MSIX:
4444 4446 /* Add interrupt handler for tx + other */
4445 4447 tx_ring = &igb->tx_rings[0];
4446 4448 rc = ddi_intr_add_handler(igb->htable[vector],
4447 4449 (ddi_intr_handler_t *)igb_intr_tx_other,
4448 4450 (void *)igb, NULL);
4449 4451
4450 4452 if (rc != DDI_SUCCESS) {
4451 4453 igb_log(igb,
4452 4454 "Add tx/other interrupt handler failed: %d", rc);
4453 4455 return (IGB_FAILURE);
4454 4456 }
4455 4457 tx_ring->intr_vector = vector;
4456 4458 vector++;
4457 4459
4458 4460 /* Add interrupt handler for each rx ring */
4459 4461 for (i = 0; i < igb->num_rx_rings; i++) {
4460 4462 rx_ring = &igb->rx_rings[i];
4461 4463
4462 4464 rc = ddi_intr_add_handler(igb->htable[vector],
4463 4465 (ddi_intr_handler_t *)igb_intr_rx,
4464 4466 (void *)rx_ring, NULL);
4465 4467
4466 4468 if (rc != DDI_SUCCESS) {
4467 4469 igb_log(igb,
4468 4470 "Add rx interrupt handler failed. "
4469 4471 "return: %d, rx ring: %d", rc, i);
4470 4472 for (vector--; vector >= 0; vector--) {
4471 4473 (void) ddi_intr_remove_handler(
4472 4474 igb->htable[vector]);
4473 4475 }
4474 4476 return (IGB_FAILURE);
4475 4477 }
4476 4478
4477 4479 rx_ring->intr_vector = vector;
4478 4480
4479 4481 vector++;
4480 4482 }
4481 4483
4482 4484 /* Add interrupt handler for each tx ring from 2nd ring */
4483 4485 for (i = 1; i < igb->num_tx_rings; i++) {
4484 4486 tx_ring = &igb->tx_rings[i];
4485 4487
4486 4488 rc = ddi_intr_add_handler(igb->htable[vector],
4487 4489 (ddi_intr_handler_t *)igb_intr_tx,
4488 4490 (void *)tx_ring, NULL);
4489 4491
4490 4492 if (rc != DDI_SUCCESS) {
4491 4493 igb_log(igb,
4492 4494 "Add tx interrupt handler failed. "
4493 4495 "return: %d, tx ring: %d", rc, i);
4494 4496 for (vector--; vector >= 0; vector--) {
4495 4497 (void) ddi_intr_remove_handler(
4496 4498 igb->htable[vector]);
4497 4499 }
4498 4500 return (IGB_FAILURE);
4499 4501 }
4500 4502
4501 4503 tx_ring->intr_vector = vector;
4502 4504
4503 4505 vector++;
4504 4506 }
4505 4507
4506 4508 break;
4507 4509
4508 4510 case DDI_INTR_TYPE_MSI:
4509 4511 /* Add interrupt handlers for the only vector */
4510 4512 rc = ddi_intr_add_handler(igb->htable[vector],
4511 4513 (ddi_intr_handler_t *)igb_intr_msi,
4512 4514 (void *)igb, NULL);
4513 4515
4514 4516 if (rc != DDI_SUCCESS) {
4515 4517 igb_log(igb,
4516 4518 "Add MSI interrupt handler failed: %d", rc);
4517 4519 return (IGB_FAILURE);
4518 4520 }
4519 4521
4520 4522 rx_ring = &igb->rx_rings[0];
4521 4523 rx_ring->intr_vector = vector;
4522 4524
4523 4525 vector++;
4524 4526 break;
4525 4527
4526 4528 case DDI_INTR_TYPE_FIXED:
4527 4529 /* Add interrupt handlers for the only vector */
4528 4530 rc = ddi_intr_add_handler(igb->htable[vector],
4529 4531 (ddi_intr_handler_t *)igb_intr_legacy,
4530 4532 (void *)igb, NULL);
4531 4533
4532 4534 if (rc != DDI_SUCCESS) {
4533 4535 igb_log(igb,
4534 4536 "Add legacy interrupt handler failed: %d", rc);
4535 4537 return (IGB_FAILURE);
4536 4538 }
4537 4539
4538 4540 rx_ring = &igb->rx_rings[0];
4539 4541 rx_ring->intr_vector = vector;
4540 4542
4541 4543 vector++;
4542 4544 break;
4543 4545
4544 4546 default:
4545 4547 return (IGB_FAILURE);
4546 4548 }
4547 4549
4548 4550 ASSERT(vector == igb->intr_cnt);
4549 4551
4550 4552 return (IGB_SUCCESS);
4551 4553 }
4552 4554
4553 4555 /*
4554 4556 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts
4555 4557 *
4556 4558 * For each vector enabled on the adapter, Set the MSIXBM register accordingly
4557 4559 */
4558 4560 static void
4559 4561 igb_setup_msix_82575(igb_t *igb)
4560 4562 {
4561 4563 uint32_t eims = 0;
4562 4564 int i, vector;
4563 4565 struct e1000_hw *hw = &igb->hw;
4564 4566
4565 4567 /*
4566 4568 * Set vector for tx ring 0 and other causes.
4567 4569 * NOTE assumption that it is vector 0.
4568 4570 */
4569 4571 vector = 0;
4570 4572
4571 4573 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER;
4572 4574 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask);
4573 4575 vector++;
4574 4576
4575 4577 for (i = 0; i < igb->num_rx_rings; i++) {
4576 4578 /*
4577 4579 * Set vector for each rx ring
4578 4580 */
4579 4581 eims = (E1000_EICR_RX_QUEUE0 << i);
4580 4582 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4581 4583
4582 4584 /*
4583 4585 * Accumulate bits to enable in
4584 4586 * igb_enable_adapter_interrupts_82575()
4585 4587 */
4586 4588 igb->eims_mask |= eims;
4587 4589
4588 4590 vector++;
4589 4591 }
4590 4592
4591 4593 for (i = 1; i < igb->num_tx_rings; i++) {
4592 4594 /*
4593 4595 * Set vector for each tx ring from 2nd tx ring
4594 4596 */
4595 4597 eims = (E1000_EICR_TX_QUEUE0 << i);
4596 4598 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4597 4599
4598 4600 /*
4599 4601 * Accumulate bits to enable in
4600 4602 * igb_enable_adapter_interrupts_82575()
4601 4603 */
4602 4604 igb->eims_mask |= eims;
4603 4605
4604 4606 vector++;
4605 4607 }
4606 4608
4607 4609 ASSERT(vector == igb->intr_cnt);
4608 4610
4609 4611 /*
4610 4612 * Disable IAM for ICR interrupt bits
4611 4613 */
4612 4614 E1000_WRITE_REG(hw, E1000_IAM, 0);
4613 4615 E1000_WRITE_FLUSH(hw);
4614 4616 }
4615 4617
4616 4618 /*
4617 4619 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts
4618 4620 *
4619 4621 * 82576 uses a table based method for assigning vectors. Each queue has a
4620 4622 * single entry in the table to which we write a vector number along with a
4621 4623 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors
4622 4624 * take a different position in the 4-byte register depending on whether
4623 4625 * they are numbered above or below 8.
4624 4626 */
4625 4627 static void
4626 4628 igb_setup_msix_82576(igb_t *igb)
4627 4629 {
4628 4630 struct e1000_hw *hw = &igb->hw;
4629 4631 uint32_t ivar, index, vector;
4630 4632 int i;
4631 4633
4632 4634 /* must enable msi-x capability before IVAR settings */
4633 4635 E1000_WRITE_REG(hw, E1000_GPIE,
4634 4636 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR));
4635 4637
4636 4638 /*
4637 4639 * Set vector for tx ring 0 and other causes.
4638 4640 * NOTE assumption that it is vector 0.
4639 4641 * This is also interdependent with installation of interrupt service
4640 4642 * routines in igb_add_intr_handlers().
4641 4643 */
4642 4644
4643 4645 /* assign "other" causes to vector 0 */
4644 4646 vector = 0;
4645 4647 ivar = ((vector | E1000_IVAR_VALID) << 8);
4646 4648 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4647 4649
4648 4650 /* assign tx ring 0 to vector 0 */
4649 4651 ivar = ((vector | E1000_IVAR_VALID) << 8);
4650 4652 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4651 4653
4652 4654 /* prepare to enable tx & other interrupt causes */
4653 4655 igb->eims_mask = (1 << vector);
4654 4656
4655 4657 vector ++;
4656 4658 for (i = 0; i < igb->num_rx_rings; i++) {
4657 4659 /*
4658 4660 * Set vector for each rx ring
4659 4661 */
4660 4662 index = (i & 0x7);
4661 4663 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4662 4664
4663 4665 if (i < 8) {
4664 4666 /* vector goes into low byte of register */
4665 4667 ivar = ivar & 0xFFFFFF00;
4666 4668 ivar |= (vector | E1000_IVAR_VALID);
4667 4669 } else {
4668 4670 /* vector goes into third byte of register */
4669 4671 ivar = ivar & 0xFF00FFFF;
4670 4672 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4671 4673 }
4672 4674 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4673 4675
4674 4676 /* Accumulate interrupt-cause bits to enable */
4675 4677 igb->eims_mask |= (1 << vector);
4676 4678
4677 4679 vector ++;
4678 4680 }
4679 4681
4680 4682 for (i = 1; i < igb->num_tx_rings; i++) {
4681 4683 /*
4682 4684 * Set vector for each tx ring from 2nd tx ring.
4683 4685 * Note assumption that tx vectors numericall follow rx vectors.
4684 4686 */
4685 4687 index = (i & 0x7);
4686 4688 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4687 4689
4688 4690 if (i < 8) {
4689 4691 /* vector goes into second byte of register */
4690 4692 ivar = ivar & 0xFFFF00FF;
4691 4693 ivar |= ((vector | E1000_IVAR_VALID) << 8);
4692 4694 } else {
4693 4695 /* vector goes into fourth byte of register */
4694 4696 ivar = ivar & 0x00FFFFFF;
4695 4697 ivar |= (vector | E1000_IVAR_VALID) << 24;
4696 4698 }
4697 4699 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4698 4700
4699 4701 /* Accumulate interrupt-cause bits to enable */
4700 4702 igb->eims_mask |= (1 << vector);
4701 4703
4702 4704 vector ++;
4703 4705 }
4704 4706
4705 4707 ASSERT(vector == igb->intr_cnt);
4706 4708 }
4707 4709
4708 4710 /*
4709 4711 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts
4710 4712 *
4711 4713 * 82580 uses same table approach at 82576 but has fewer entries. Each
4712 4714 * queue has a single entry in the table to which we write a vector number
4713 4715 * along with a "valid" bit. Vectors take a different position in the
4714 4716 * register depending on * whether * they are numbered above or below 4.
4715 4717 */
4716 4718 static void
4717 4719 igb_setup_msix_82580(igb_t *igb)
4718 4720 {
4719 4721 struct e1000_hw *hw = &igb->hw;
4720 4722 uint32_t ivar, index, vector;
4721 4723 int i;
4722 4724
4723 4725 /* must enable msi-x capability before IVAR settings */
4724 4726 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE |
4725 4727 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME));
4726 4728 /*
4727 4729 * Set vector for tx ring 0 and other causes.
4728 4730 * NOTE assumption that it is vector 0.
4729 4731 * This is also interdependent with installation of interrupt service
4730 4732 * routines in igb_add_intr_handlers().
4731 4733 */
4732 4734
4733 4735 /* assign "other" causes to vector 0 */
4734 4736 vector = 0;
4735 4737 ivar = ((vector | E1000_IVAR_VALID) << 8);
4736 4738 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4737 4739
4738 4740 /* assign tx ring 0 to vector 0 */
4739 4741 ivar = ((vector | E1000_IVAR_VALID) << 8);
4740 4742 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4741 4743
4742 4744 /* prepare to enable tx & other interrupt causes */
4743 4745 igb->eims_mask = (1 << vector);
4744 4746
4745 4747 vector ++;
4746 4748
4747 4749 for (i = 0; i < igb->num_rx_rings; i++) {
4748 4750 /*
4749 4751 * Set vector for each rx ring
4750 4752 */
4751 4753 index = (i >> 1);
4752 4754 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4753 4755
4754 4756 if (i & 1) {
4755 4757 /* vector goes into third byte of register */
4756 4758 ivar = ivar & 0xFF00FFFF;
4757 4759 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4758 4760 } else {
4759 4761 /* vector goes into low byte of register */
4760 4762 ivar = ivar & 0xFFFFFF00;
4761 4763 ivar |= (vector | E1000_IVAR_VALID);
4762 4764 }
4763 4765 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4764 4766
4765 4767 /* Accumulate interrupt-cause bits to enable */
4766 4768 igb->eims_mask |= (1 << vector);
4767 4769
4768 4770 vector ++;
4769 4771 }
4770 4772
4771 4773 for (i = 1; i < igb->num_tx_rings; i++) {
4772 4774 /*
4773 4775 * Set vector for each tx ring from 2nd tx ring.
4774 4776 * Note assumption that tx vectors numericall follow rx vectors.
4775 4777 */
4776 4778 index = (i >> 1);
4777 4779 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4778 4780
4779 4781 if (i & 1) {
4780 4782 /* vector goes into high byte of register */
4781 4783 ivar = ivar & 0x00FFFFFF;
4782 4784 ivar |= ((vector | E1000_IVAR_VALID) << 24);
4783 4785 } else {
4784 4786 /* vector goes into second byte of register */
4785 4787 ivar = ivar & 0xFFFF00FF;
4786 4788 ivar |= (vector | E1000_IVAR_VALID) << 8;
4787 4789 }
4788 4790 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4789 4791
4790 4792 /* Accumulate interrupt-cause bits to enable */
4791 4793 igb->eims_mask |= (1 << vector);
4792 4794
4793 4795 vector ++;
4794 4796 }
4795 4797 ASSERT(vector == igb->intr_cnt);
4796 4798 }
4797 4799
4798 4800 /*
4799 4801 * igb_rem_intr_handlers - remove the interrupt handlers
4800 4802 */
4801 4803 static void
4802 4804 igb_rem_intr_handlers(igb_t *igb)
4803 4805 {
4804 4806 int i;
4805 4807 int rc;
4806 4808
4807 4809 for (i = 0; i < igb->intr_cnt; i++) {
4808 4810 rc = ddi_intr_remove_handler(igb->htable[i]);
4809 4811 if (rc != DDI_SUCCESS) {
4810 4812 IGB_DEBUGLOG_1(igb,
4811 4813 "Remove intr handler failed: %d", rc);
4812 4814 }
4813 4815 }
4814 4816 }
4815 4817
4816 4818 /*
4817 4819 * igb_rem_intrs - remove the allocated interrupts
4818 4820 */
4819 4821 static void
4820 4822 igb_rem_intrs(igb_t *igb)
4821 4823 {
4822 4824 int i;
4823 4825 int rc;
4824 4826
4825 4827 for (i = 0; i < igb->intr_cnt; i++) {
4826 4828 rc = ddi_intr_free(igb->htable[i]);
4827 4829 if (rc != DDI_SUCCESS) {
4828 4830 IGB_DEBUGLOG_1(igb,
4829 4831 "Free intr failed: %d", rc);
4830 4832 }
4831 4833 }
4832 4834
4833 4835 kmem_free(igb->htable, igb->intr_size);
4834 4836 igb->htable = NULL;
4835 4837 }
4836 4838
4837 4839 /*
4838 4840 * igb_enable_intrs - enable all the ddi interrupts
4839 4841 */
4840 4842 static int
4841 4843 igb_enable_intrs(igb_t *igb)
4842 4844 {
4843 4845 int i;
4844 4846 int rc;
4845 4847
4846 4848 /* Enable interrupts */
4847 4849 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4848 4850 /* Call ddi_intr_block_enable() for MSI */
4849 4851 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt);
4850 4852 if (rc != DDI_SUCCESS) {
4851 4853 igb_log(igb,
4852 4854 "Enable block intr failed: %d", rc);
4853 4855 return (IGB_FAILURE);
4854 4856 }
4855 4857 } else {
4856 4858 /* Call ddi_intr_enable() for Legacy/MSI non block enable */
4857 4859 for (i = 0; i < igb->intr_cnt; i++) {
4858 4860 rc = ddi_intr_enable(igb->htable[i]);
4859 4861 if (rc != DDI_SUCCESS) {
4860 4862 igb_log(igb,
4861 4863 "Enable intr failed: %d", rc);
4862 4864 return (IGB_FAILURE);
4863 4865 }
4864 4866 }
4865 4867 }
4866 4868
4867 4869 return (IGB_SUCCESS);
4868 4870 }
4869 4871
4870 4872 /*
4871 4873 * igb_disable_intrs - disable all the ddi interrupts
4872 4874 */
4873 4875 static int
4874 4876 igb_disable_intrs(igb_t *igb)
4875 4877 {
4876 4878 int i;
4877 4879 int rc;
4878 4880
4879 4881 /* Disable all interrupts */
4880 4882 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4881 4883 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt);
4882 4884 if (rc != DDI_SUCCESS) {
4883 4885 igb_log(igb,
4884 4886 "Disable block intr failed: %d", rc);
4885 4887 return (IGB_FAILURE);
4886 4888 }
4887 4889 } else {
4888 4890 for (i = 0; i < igb->intr_cnt; i++) {
4889 4891 rc = ddi_intr_disable(igb->htable[i]);
4890 4892 if (rc != DDI_SUCCESS) {
4891 4893 igb_log(igb,
4892 4894 "Disable intr failed: %d", rc);
4893 4895 return (IGB_FAILURE);
4894 4896 }
4895 4897 }
4896 4898 }
4897 4899
4898 4900 return (IGB_SUCCESS);
4899 4901 }
4900 4902
4901 4903 /*
4902 4904 * igb_get_phy_state - Get and save the parameters read from PHY registers
4903 4905 */
4904 4906 static void
4905 4907 igb_get_phy_state(igb_t *igb)
4906 4908 {
4907 4909 struct e1000_hw *hw = &igb->hw;
4908 4910 uint16_t phy_ctrl;
4909 4911 uint16_t phy_status;
4910 4912 uint16_t phy_an_adv;
4911 4913 uint16_t phy_an_exp;
4912 4914 uint16_t phy_ext_status;
4913 4915 uint16_t phy_1000t_ctrl;
4914 4916 uint16_t phy_1000t_status;
4915 4917 uint16_t phy_lp_able;
4916 4918
4917 4919 ASSERT(mutex_owned(&igb->gen_lock));
4918 4920
4919 4921 if (hw->phy.media_type == e1000_media_type_copper) {
4920 4922 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
4921 4923 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
4922 4924 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv);
4923 4925 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp);
4924 4926 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status);
4925 4927 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl);
4926 4928 (void) e1000_read_phy_reg(hw,
4927 4929 PHY_1000T_STATUS, &phy_1000t_status);
4928 4930 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able);
4929 4931
4930 4932 igb->param_autoneg_cap =
4931 4933 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
4932 4934 igb->param_pause_cap =
4933 4935 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
4934 4936 igb->param_asym_pause_cap =
4935 4937 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
4936 4938 igb->param_1000fdx_cap =
4937 4939 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
4938 4940 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
4939 4941 igb->param_1000hdx_cap =
4940 4942 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
4941 4943 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
4942 4944 igb->param_100t4_cap =
4943 4945 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
4944 4946 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) ||
4945 4947 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
4946 4948 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) ||
4947 4949 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
4948 4950 igb->param_10fdx_cap =
4949 4951 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
4950 4952 igb->param_10hdx_cap =
4951 4953 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
4952 4954 igb->param_rem_fault =
4953 4955 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0;
4954 4956
4955 4957 igb->param_adv_autoneg_cap = hw->mac.autoneg;
4956 4958 igb->param_adv_pause_cap =
4957 4959 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
4958 4960 igb->param_adv_asym_pause_cap =
4959 4961 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
4960 4962 igb->param_adv_1000hdx_cap =
4961 4963 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
4962 4964 igb->param_adv_100t4_cap =
4963 4965 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
4964 4966 igb->param_adv_rem_fault =
4965 4967 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0;
4966 4968 if (igb->param_adv_autoneg_cap == 1) {
4967 4969 igb->param_adv_1000fdx_cap =
4968 4970 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
4969 4971 igb->param_adv_100fdx_cap =
4970 4972 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
4971 4973 igb->param_adv_100hdx_cap =
4972 4974 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
4973 4975 igb->param_adv_10fdx_cap =
4974 4976 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
4975 4977 igb->param_adv_10hdx_cap =
4976 4978 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
4977 4979 }
4978 4980
4979 4981 igb->param_lp_autoneg_cap =
4980 4982 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
4981 4983 igb->param_lp_pause_cap =
4982 4984 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
4983 4985 igb->param_lp_asym_pause_cap =
4984 4986 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
4985 4987 igb->param_lp_1000fdx_cap =
4986 4988 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
4987 4989 igb->param_lp_1000hdx_cap =
4988 4990 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
4989 4991 igb->param_lp_100t4_cap =
4990 4992 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
4991 4993 igb->param_lp_100fdx_cap =
4992 4994 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
4993 4995 igb->param_lp_100hdx_cap =
4994 4996 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
4995 4997 igb->param_lp_10fdx_cap =
4996 4998 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
4997 4999 igb->param_lp_10hdx_cap =
4998 5000 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
4999 5001 igb->param_lp_rem_fault =
5000 5002 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0;
5001 5003 } else {
5002 5004 /*
5003 5005 * 1Gig Fiber adapter only offers 1Gig Full Duplex.
5004 5006 */
5005 5007 igb->param_autoneg_cap = 0;
5006 5008 igb->param_pause_cap = 1;
5007 5009 igb->param_asym_pause_cap = 1;
5008 5010 igb->param_1000fdx_cap = 1;
5009 5011 igb->param_1000hdx_cap = 0;
5010 5012 igb->param_100t4_cap = 0;
5011 5013 igb->param_100fdx_cap = 0;
5012 5014 igb->param_100hdx_cap = 0;
5013 5015 igb->param_10fdx_cap = 0;
5014 5016 igb->param_10hdx_cap = 0;
5015 5017
5016 5018 igb->param_adv_autoneg_cap = 0;
5017 5019 igb->param_adv_pause_cap = 1;
5018 5020 igb->param_adv_asym_pause_cap = 1;
5019 5021 igb->param_adv_1000fdx_cap = 1;
5020 5022 igb->param_adv_1000hdx_cap = 0;
5021 5023 igb->param_adv_100t4_cap = 0;
5022 5024 igb->param_adv_100fdx_cap = 0;
5023 5025 igb->param_adv_100hdx_cap = 0;
5024 5026 igb->param_adv_10fdx_cap = 0;
5025 5027 igb->param_adv_10hdx_cap = 0;
5026 5028
5027 5029 igb->param_lp_autoneg_cap = 0;
5028 5030 igb->param_lp_pause_cap = 0;
5029 5031 igb->param_lp_asym_pause_cap = 0;
5030 5032 igb->param_lp_1000fdx_cap = 0;
5031 5033 igb->param_lp_1000hdx_cap = 0;
5032 5034 igb->param_lp_100t4_cap = 0;
5033 5035 igb->param_lp_100fdx_cap = 0;
5034 5036 igb->param_lp_100hdx_cap = 0;
5035 5037 igb->param_lp_10fdx_cap = 0;
5036 5038 igb->param_lp_10hdx_cap = 0;
5037 5039 igb->param_lp_rem_fault = 0;
5038 5040 }
5039 5041 }
5040 5042
5041 5043 /*
5042 5044 * synchronize the adv* and en* parameters.
5043 5045 *
5044 5046 * See comments in <sys/dld.h> for details of the *_en_*
5045 5047 * parameters. The usage of ndd for setting adv parameters will
5046 5048 * synchronize all the en parameters with the e1000g parameters,
5047 5049 * implicitly disabling any settings made via dladm.
5048 5050 */
5049 5051 static void
5050 5052 igb_param_sync(igb_t *igb)
5051 5053 {
5052 5054 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap;
5053 5055 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap;
5054 5056 igb->param_en_100t4_cap = igb->param_adv_100t4_cap;
5055 5057 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap;
5056 5058 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap;
5057 5059 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap;
5058 5060 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap;
5059 5061 }
5060 5062
5061 5063 /*
5062 5064 * igb_get_driver_control
5063 5065 */
5064 5066 static void
5065 5067 igb_get_driver_control(struct e1000_hw *hw)
5066 5068 {
5067 5069 uint32_t ctrl_ext;
5068 5070
5069 5071 /* Notify firmware that driver is in control of device */
5070 5072 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5071 5073 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD;
5072 5074 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5073 5075 }
5074 5076
5075 5077 /*
5076 5078 * igb_release_driver_control
5077 5079 */
5078 5080 static void
5079 5081 igb_release_driver_control(struct e1000_hw *hw)
5080 5082 {
5081 5083 uint32_t ctrl_ext;
5082 5084
5083 5085 /* Notify firmware that driver is no longer in control of device */
5084 5086 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5085 5087 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD;
5086 5088 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5087 5089 }
5088 5090
5089 5091 /*
5090 5092 * igb_atomic_reserve - Atomic decrease operation
5091 5093 */
5092 5094 int
5093 5095 igb_atomic_reserve(uint32_t *count_p, uint32_t n)
5094 5096 {
5095 5097 uint32_t oldval;
5096 5098 uint32_t newval;
5097 5099
5098 5100 /* ATOMICALLY */
5099 5101 do {
5100 5102 oldval = *count_p;
5101 5103 if (oldval < n)
5102 5104 return (-1);
5103 5105 newval = oldval - n;
5104 5106 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5105 5107
5106 5108 return (newval);
5107 5109 }
5108 5110
5109 5111 /*
5110 5112 * FMA support
5111 5113 */
5112 5114
5113 5115 int
5114 5116 igb_check_acc_handle(ddi_acc_handle_t handle)
5115 5117 {
5116 5118 ddi_fm_error_t de;
5117 5119
5118 5120 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5119 5121 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5120 5122 return (de.fme_status);
5121 5123 }
5122 5124
5123 5125 int
5124 5126 igb_check_dma_handle(ddi_dma_handle_t handle)
5125 5127 {
5126 5128 ddi_fm_error_t de;
5127 5129
5128 5130 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5129 5131 return (de.fme_status);
5130 5132 }
5131 5133
5132 5134 /*
5133 5135 * The IO fault service error handling callback function
5134 5136 */
5135 5137 /*ARGSUSED*/
5136 5138 static int
5137 5139 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5138 5140 {
5139 5141 /*
5140 5142 * as the driver can always deal with an error in any dma or
5141 5143 * access handle, we can just return the fme_status value.
5142 5144 */
5143 5145 pci_ereport_post(dip, err, NULL);
5144 5146 return (err->fme_status);
5145 5147 }
5146 5148
5147 5149 static void
5148 5150 igb_fm_init(igb_t *igb)
5149 5151 {
5150 5152 ddi_iblock_cookie_t iblk;
5151 5153 int fma_dma_flag;
5152 5154
5153 5155 /* Only register with IO Fault Services if we have some capability */
5154 5156 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5155 5157 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5156 5158 } else {
5157 5159 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5158 5160 }
5159 5161
5160 5162 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5161 5163 fma_dma_flag = 1;
5162 5164 } else {
5163 5165 fma_dma_flag = 0;
5164 5166 }
5165 5167
5166 5168 (void) igb_set_fma_flags(fma_dma_flag);
5167 5169
5168 5170 if (igb->fm_capabilities) {
5169 5171
5170 5172 /* Register capabilities with IO Fault Services */
5171 5173 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk);
5172 5174
5173 5175 /*
5174 5176 * Initialize pci ereport capabilities if ereport capable
5175 5177 */
5176 5178 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5177 5179 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5178 5180 pci_ereport_setup(igb->dip);
5179 5181
5180 5182 /*
5181 5183 * Register error callback if error callback capable
5182 5184 */
5183 5185 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5184 5186 ddi_fm_handler_register(igb->dip,
5185 5187 igb_fm_error_cb, (void*) igb);
5186 5188 }
5187 5189 }
5188 5190
5189 5191 static void
5190 5192 igb_fm_fini(igb_t *igb)
5191 5193 {
5192 5194 /* Only unregister FMA capabilities if we registered some */
5193 5195 if (igb->fm_capabilities) {
5194 5196
5195 5197 /*
5196 5198 * Release any resources allocated by pci_ereport_setup()
5197 5199 */
5198 5200 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5199 5201 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5200 5202 pci_ereport_teardown(igb->dip);
5201 5203
5202 5204 /*
5203 5205 * Un-register error callback if error callback capable
5204 5206 */
5205 5207 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5206 5208 ddi_fm_handler_unregister(igb->dip);
5207 5209
5208 5210 /* Unregister from IO Fault Services */
5209 5211 ddi_fm_fini(igb->dip);
5210 5212 }
5211 5213 }
5212 5214
5213 5215 void
5214 5216 igb_fm_ereport(igb_t *igb, char *detail)
5215 5217 {
5216 5218 uint64_t ena;
5217 5219 char buf[FM_MAX_CLASS];
5218 5220
5219 5221 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5220 5222 ena = fm_ena_generate(0, FM_ENA_FMT1);
5221 5223 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) {
5222 5224 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP,
5223 5225 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5224 5226 }
5225 5227 }
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