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2038 Add in I350 and ET2 support into igb
Reviewed by: Dan McDonald <danmcd@nexenta.com>
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--- old/usr/src/uts/common/io/igb/igb_regs.h
+++ new/usr/src/uts/common/io/igb/igb_regs.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
23 + * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 */
29 29
30 30 /* IntelVersion: 1.82.2.1 v3_3_14_3_BHSW1 */
31 31
32 32 #ifndef _IGB_REGS_H
33 33 #define _IGB_REGS_H
34 34
35 35 #ifdef __cplusplus
36 36 extern "C" {
37 37 #endif
38 38
39 39 #define E1000_CTRL 0x00000 /* Device Control - RW */
40 40 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
41 41 #define E1000_STATUS 0x00008 /* Device Status - RO */
42 42 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
43 43 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
44 44 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
45 45 #define E1000_FLA 0x0001C /* Flash Access - RW */
46 46 #define E1000_MDIC 0x00020 /* MDI Control - RW */
47 47 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
48 48 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */
49 49 #define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */
50 50 #define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */
51 51 #define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */
52 52 #define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */
53 53 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
54 54 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
55 55 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
56 56 #define E1000_FEXT 0x0002C /* Future Extended - RW */
57 57 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */
58 58 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
59 59 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
60 60 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
61 61 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
62 62 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
63 63 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
64 64 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
65 65 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
66 66 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
67 67 #define E1000_RCTL 0x00100 /* Rx Control - RW */
68 68 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
69 69 #define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
70 70 #define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */
71 71 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
72 72 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
73 73 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
74 74 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
75 75 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
76 76 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
77 77 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
78 78 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
79 79 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
80 80 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
81 81 #define E1000_TCTL 0x00400 /* Tx Control - RW */
82 82 #define E1000_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
83 83 #define E1000_TIPG 0x00410 /* Tx Inter-packet gap -RW */
84 84 #define E1000_TBT 0x00448 /* Tx Burst Timer - RW */
85 85 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
86 86 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
87 87 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
88 88 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
89 89 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
90 90 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
91 91 #define E1000_PBS 0x01008 /* Packet Buffer Size */
92 92 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
93 93 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
94 94 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
95 95 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
96 96 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
97 97 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
98 98 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
99 99 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
100 100 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */
101 101 #define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
102 102 #define E1000_WDSTP 0x01040 /* Watchdog Setup - RW */
103 103 #define E1000_SWDSTS 0x01044 /* SW Device Status - RW */
104 104 #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
105 105 #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */
106 106 #define E1000_VPDDIAG 0x01060 /* VPD Diagnostic - RO */
107 107 #define E1000_ICR_V2 0x01500 /* Interrupt Cause - new location - RC */
108 108 #define E1000_ICS_V2 0x01504 /* Interrupt Cause Set - new location - WO */
109 109 /* Interrupt Mask Set/Read - new location - RW */
110 110 #define E1000_IMS_V2 0x01508
111 111 #define E1000_IMC_V2 0x0150C /* Interrupt Mask Clear - new location - WO */
112 112 /* Interrupt Ack Auto Mask - new location - RW */
113 113 #define E1000_IAM_V2 0x01510
114 114 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
115 115 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
116 116 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
117 117 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
118 118 #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n)))
119 119 #define E1000_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
120 120 #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
121 121 /* Split and Replication Rx Control - RW */
122 122 #define E1000_RDPUMB 0x025CC /* DMA Rx Descriptor uC Mailbox - RW */
123 123 #define E1000_RDPUAD 0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */
124 124 #define E1000_RDPUWD 0x025D4 /* DMA Rx Descriptor uC Data Write - RW */
125 125 #define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */
126 126 #define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */
127 127 #define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */
128 128 #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
129 129 /* Same as RXPBS, renamed for newer adapters - RW */
130 130 #define E1000_IRPBS 0x02404
131 131 #define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */
132 132 #define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
133 133 /*
134 134 * Convenience macros
135 135 *
136 136 * Note: "_n" is the queue number of the register to be written to.
137 137 *
138 138 * Example usage:
139 139 * E1000_RDBAL_REG(current_rx_queue)
140 140 */
141 141 #define E1000_RDBAL(_n) ((_n) < 4 ? \
142 142 (0x02800 + ((_n) * 0x100)) : \
143 143 (0x0C000 + ((_n) * 0x40)))
144 144 #define E1000_RDBAH(_n) ((_n) < 4 ? \
145 145 (0x02804 + ((_n) * 0x100)) : \
146 146 (0x0C004 + ((_n) * 0x40)))
147 147 #define E1000_RDLEN(_n) ((_n) < 4 ? \
148 148 (0x02808 + ((_n) * 0x100)) : \
149 149 (0x0C008 + ((_n) * 0x40)))
150 150 #define E1000_SRRCTL(_n) ((_n) < 4 ? \
151 151 (0x0280C + ((_n) * 0x100)) : \
152 152 (0x0C00C + ((_n) * 0x40)))
153 153 #define E1000_RDH(_n) ((_n) < 4 ? \
154 154 (0x02810 + ((_n) * 0x100)) : \
155 155 (0x0C010 + ((_n) * 0x40)))
156 156 #define E1000_RXCTL(_n) ((_n) < 4 ? \
157 157 (0x02814 + ((_n) * 0x100)) : \
158 158 (0x0C014 + ((_n) * 0x40)))
159 159 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
160 160 #define E1000_RDT(_n) ((_n) < 4 ? \
161 161 (0x02818 + ((_n) * 0x100)) : \
162 162 (0x0C018 + ((_n) * 0x40)))
163 163 #define E1000_RXDCTL(_n) ((_n) < 4 ? \
164 164 (0x02828 + ((_n) * 0x100)) : \
165 165 (0x0C028 + ((_n) * 0x40)))
166 166 #define E1000_RQDPC(_n) ((_n) < 4 ? \
167 167 (0x02830 + ((_n) * 0x100)) : \
168 168 (0x0C030 + ((_n) * 0x40)))
169 169 #define E1000_TDBAL(_n) ((_n) < 4 ? \
170 170 (0x03800 + ((_n) * 0x100)) : \
171 171 (0x0E000 + ((_n) * 0x40)))
172 172 #define E1000_TDBAH(_n) ((_n) < 4 ? \
173 173 (0x03804 + ((_n) * 0x100)) : \
174 174 (0x0E004 + ((_n) * 0x40)))
175 175 #define E1000_TDLEN(_n) ((_n) < 4 ? \
176 176 (0x03808 + ((_n) * 0x100)) : \
177 177 (0x0E008 + ((_n) * 0x40)))
178 178 #define E1000_TDH(_n) ((_n) < 4 ? \
179 179 (0x03810 + ((_n) * 0x100)) : \
180 180 (0x0E010 + ((_n) * 0x40)))
181 181 #define E1000_TXCTL(_n) ((_n) < 4 ? \
182 182 (0x03814 + ((_n) * 0x100)) : \
183 183 (0x0E014 + ((_n) * 0x40)))
184 184 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
185 185 #define E1000_TDT(_n) ((_n) < 4 ? \
186 186 (0x03818 + ((_n) * 0x100)) : \
187 187 (0x0E018 + ((_n) * 0x40)))
188 188 #define E1000_TXDCTL(_n) ((_n) < 4 ? \
189 189 (0x03828 + ((_n) * 0x100)) : \
190 190 (0x0E028 + ((_n) * 0x40)))
191 191 #define E1000_TDWBAL(_n) ((_n) < 4 ? \
192 192 (0x03838 + ((_n) * 0x100)) : \
193 193 (0x0E038 + ((_n) * 0x40)))
194 194 #define E1000_TDWBAH(_n) ((_n) < 4 ? \
195 195 (0x0383C + ((_n) * 0x100)) : \
196 196 (0x0E03C + ((_n) * 0x40)))
197 197 #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
198 198 #define E1000_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
199 199 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
200 200 #define E1000_TXDMAC 0x03000 /* Tx DMA Control - RW */
201 201 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
202 202 #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
203 203 #define E1000_RAL(_i) (((_i) <= 15) ? \
204 204 (0x05400 + ((_i) * 8)) : \
205 205 (0x054E0 + ((_i - 16) * 8)))
206 206 #define E1000_RAH(_i) (((_i) <= 15) ? \
207 207 (0x05404 + ((_i) * 8)) : \
208 208 (0x054E4 + ((_i - 16) * 8)))
209 209 #define E1000_IP4AT_REG(_i) (0x05840 + ((_i) * 8))
210 210 #define E1000_IP6AT_REG(_i) (0x05880 + ((_i) * 4))
211 211 #define E1000_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
212 212 #define E1000_FFMT_REG(_i) (0x09000 + ((_i) * 8))
213 213 #define E1000_FFVT_REG(_i) (0x09800 + ((_i) * 8))
214 214 #define E1000_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
215 215 #define E1000_PBSLAC 0x03100 /* Packet Buffer Slave Access Control */
216 216 /* Packet Buffer DWORD (_n) */
217 217 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n)))
218 218 #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
219 219 /* Same as TXPBS, renamed for newer adpaters - RW */
220 220 #define E1000_ITPBS 0x03404
221 221 #define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
222 222 #define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
223 223 #define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
224 224 #define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
225 225 #define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
226 226 #define E1000_TDPUMB 0x0357C /* DMA Tx Descriptor uC Mail Box - RW */
227 227 #define E1000_TDPUAD 0x03580 /* DMA Tx Descriptor uC Addr Command - RW */
228 228 #define E1000_TDPUWD 0x03584 /* DMA Tx Descriptor uC Data Write - RW */
229 229 #define E1000_TDPURD 0x03588 /* DMA Tx Descriptor uC Data Read - RW */
230 230 #define E1000_TDPUCTL 0x0358C /* DMA Tx Descriptor uC Control - RW */
231 231 #define E1000_DTXCTL 0x03590 /* DMA Tx Control - RW */
232 232 #define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
233 233 #define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
234 234 #define E1000_DTXMXSZRQ 0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
235 235 #define E1000_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
236 236 #define E1000_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
237 237 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
238 238 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
239 239 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
240 240 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
241 241 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
242 242 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
243 243 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
244 244 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
245 245 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
246 246 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
247 247 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
248 248 #define E1000_DC 0x04030 /* Defer Count - R/clr */
249 249 #define E1000_TNCRS 0x04034 /* Tx-No CRS - R/clr */
250 250 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
251 251 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
252 252 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
253 253 #define E1000_XONRXC 0x04048 /* XON Rx Count - R/clr */
254 254 #define E1000_XONTXC 0x0404C /* XON Tx Count - R/clr */
255 255 #define E1000_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
256 256 #define E1000_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
257 257 #define E1000_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
258 258 #define E1000_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
259 259 #define E1000_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
260 260 #define E1000_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
261 261 #define E1000_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
262 262 #define E1000_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
263 263 #define E1000_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
264 264 #define E1000_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
265 265 #define E1000_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
266 266 #define E1000_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
267 267 #define E1000_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
268 268 #define E1000_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
269 269 #define E1000_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
270 270 #define E1000_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
271 271 #define E1000_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
272 272 #define E1000_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
273 273 #define E1000_RUC 0x040A4 /* Rx Undersize Count - R/clr */
274 274 #define E1000_RFC 0x040A8 /* Rx Fragment Count - R/clr */
275 275 #define E1000_ROC 0x040AC /* Rx Oversize Count - R/clr */
276 276 #define E1000_RJC 0x040B0 /* Rx Jabber Count - R/clr */
277 277 #define E1000_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
278 278 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
279 279 #define E1000_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
280 280 #define E1000_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
281 281 #define E1000_TORH 0x040C4 /* Total Octets Rx High - R/clr */
282 282 #define E1000_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
283 283 #define E1000_TOTH 0x040CC /* Total Octets Tx High - R/clr */
284 284 #define E1000_TPR 0x040D0 /* Total Packets Rx - R/clr */
285 285 #define E1000_TPT 0x040D4 /* Total Packets Tx - R/clr */
286 286 #define E1000_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
287 287 #define E1000_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
288 288 #define E1000_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
289 289 #define E1000_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
290 290 #define E1000_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
291 291 #define E1000_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
292 292 #define E1000_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
293 293 #define E1000_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
294 294 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
295 295 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */
296 296 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
297 297 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */
298 298 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */
299 299 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */
300 300 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */
301 301 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
302 302 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */
303 303 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */
304 304 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
305 305
306 306 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
307 307 #define E1000_LSECTXUT 0x04300
308 308 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
309 309 #define E1000_LSECTXPKTE 0x04304
310 310 /* LinkSec Protected Tx Packet Count - OutPktsProtected */
311 311 #define E1000_LSECTXPKTP 0x04308
312 312 /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
313 313 #define E1000_LSECTXOCTE 0x0430C
314 314 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
315 315 #define E1000_LSECTXOCTP 0x04310
316 316 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
317 317 #define E1000_LSECRXUT 0x04314
318 318 /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
319 319 #define E1000_LSECRXOCTD 0x0431C
320 320 /* LinkSec Rx Octets Validated - InOctetsValidated */
321 321 #define E1000_LSECRXOCTV 0x04320
322 322 /* LinkSec Rx Bad Tag - InPktsBadTag */
323 323 #define E1000_LSECRXBAD 0x04324
324 324 /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
325 325 #define E1000_LSECRXNOSCI 0x04328
326 326 /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
327 327 #define E1000_LSECRXUNSCI 0x0432C
328 328 /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
329 329 #define E1000_LSECRXUNCH 0x04330
330 330 /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
331 331 #define E1000_LSECRXDELAY 0x04340
332 332 /* LinkSec Rx Late Packets Count - InPktsLate */
333 333 #define E1000_LSECRXLATE 0x04350
334 334 /* LinkSec Rx Packet OK Count - InPktsOk */
335 335 #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n)))
336 336 /* LinkSec Rx Invalid Count - InPktsInvalid */
337 337 #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n)))
338 338 /* LinkSec Rx Not Valid Count - InPktsNotValid */
339 339 #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n)))
340 340 /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
341 341 #define E1000_LSECRXUNSA 0x043C0
342 342 /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
343 343 #define E1000_LSECRXNUSA 0x043D0
344 344 /* LinkSec Tx Capabilities Register - RO */
345 345 #define E1000_LSECTXCAP 0x0B000
346 346 /* LinkSec Rx Capabilities Register - RO */
347 347 #define E1000_LSECRXCAP 0x0B300
348 348 #define E1000_LSECTXCTRL 0x0B004 /* LinkSec Tx Control - RW */
349 349 #define E1000_LSECRXCTRL 0x0B304 /* LinkSec Rx Control - RW */
350 350 #define E1000_LSECTXSCL 0x0B008 /* LinkSec Tx SCI Low - RW */
351 351 #define E1000_LSECTXSCH 0x0B00C /* LinkSec Tx SCI High - RW */
352 352 #define E1000_LSECTXSA 0x0B010 /* LinkSec Tx SA0 - RW */
353 353 #define E1000_LSECTXPN0 0x0B018 /* LinkSec Tx SA PN 0 - RW */
354 354 #define E1000_LSECTXPN1 0x0B01C /* LinkSec Tx SA PN 1 - RW */
355 355 #define E1000_LSECRXSCL 0x0B3D0 /* LinkSec Rx SCI Low - RW */
356 356 #define E1000_LSECRXSCH 0x0B3E0 /* LinkSec Rx SCI High - RW */
357 357 /* LinkSec Tx 128-bit Key 0 - WO */
358 358 #define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n)))
359 359 /* LinkSec Tx 128-bit Key 1 - WO */
360 360 #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))
361 361 /* LinkSec Rx SAs - RW */
362 362 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n)))
363 363 /* LinkSec Rx SAs - RW */
364 364 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n)))
365 365 /*
366 366 * LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
367 367 * key - RW.
368 368 */
369 369 #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
370 370
371 371 #define E1000_SSVPC 0x041A0 /* Switch Security Violation Packet Count */
372 372 #define E1000_IPSCTRL 0xB430 /* IpSec Control Register */
373 373 #define E1000_IPSRXCMD 0x0B408 /* IPSec Rx Command Register - RW */
374 374 #define E1000_IPSRXIDX 0x0B400 /* IPSec Rx Index - RW */
375 375 /* IPSec Rx IPv4/v6 Address - RW */
376 376 #define E1000_IPSRXIPADDR(_n) (0x0B420+ (0x04 * (_n)))
377 377 /* IPSec Rx 128-bit Key - RW */
378 378 #define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n)))
379 379 #define E1000_IPSRXSALT 0x0B404 /* IPSec Rx Salt - RW */
380 380 #define E1000_IPSRXSPI 0x0B40C /* IPSec Rx SPI - RW */
381 381 /* IPSec Tx 128-bit Key - RW */
382 382 #define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n)))
383 383 #define E1000_IPSTXSALT 0x0B454 /* IPSec Tx Salt - RW */
384 384 #define E1000_IPSTXIDX 0x0B450 /* IPSec Tx SA IDX - RW */
385 385 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */
386 386 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */
387 387 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */
388 388 #define E1000_CBTMPC 0x0402C /* Circuit Breaker Tx Packet Count */
389 389 #define E1000_HTDPMC 0x0403C /* Host Transmit Discarded Packets */
390 390 #define E1000_CBRDPC 0x04044 /* Circuit Breaker Rx Dropped Count */
391 391 #define E1000_CBRMPC 0x040FC /* Circuit Breaker Rx Packet Count */
392 392 #define E1000_RPTHC 0x04104 /* Rx Packets To Host */
393 393 #define E1000_HGPTC 0x04118 /* Host Good Packets Tx Count */
394 394 #define E1000_HTCBDPC 0x04124 /* Host Tx Circuit Breaker Dropped Count */
395 395 #define E1000_HGORCL 0x04128 /* Host Good Octets Received Count Low */
396 396 #define E1000_HGORCH 0x0412C /* Host Good Octets Received Count High */
397 397 #define E1000_HGOTCL 0x04130 /* Host Good Octets Transmit Count Low */
398 398 #define E1000_HGOTCH 0x04134 /* Host Good Octets Transmit Count High */
399 399 #define E1000_LENERRS 0x04138 /* Length Errors Count */
400 400 #define E1000_SCVPC 0x04228 /* SerDes/SGMII Code Violation Pkt Count */
401 401 #define E1000_HRMPC 0x0A018 /* Header Redirection Missed Packet Count */
402 402 #define E1000_PCS_ANADV 0x04218 /* AN advertisement - RW */
403 403 #define E1000_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
404 404 #define E1000_PCS_NPTX 0x04220 /* AN Next Page Transmit - RW */
405 405 #define E1000_PCS_LPABNP 0x04224 /* Link Partner Ability Next Page - RW */
406 406 #define E1000_1GSTAT_RCV 0x04228 /* 1GSTAT Code Violation Packet Count - RW */
407 407 #define E1000_RXCSUM 0x05000 /* Rx Checksum Control - RW */
408 408 #define E1000_RLPML 0x05004 /* Rx Long Packet Max Length */
409 409 #define E1000_RFCTL 0x05008 /* Receive Filter Control */
410 410 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
411 411 #define E1000_RA 0x05400 /* Receive Address - RW Array */
412 412 /* 2nd half of receive address array - RW Array */
413 413 #define E1000_RA2 0x054E0
414 414 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
415 415 #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
416 416 #define E1000_VFQA0 0x0B000 /* VLAN Filter Queue Array 0 - RW Array */
417 417 #define E1000_VFQA1 0x0B200 /* VLAN Filter Queue Array 1 - RW Array */
418 418 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
419 419 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
420 420 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
421 421 #define E1000_MANC 0x05820 /* Management Control - RW */
422 422 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
423 423 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
424 424 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
425 425 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
426 426 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
427 427 #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
428 428 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
429 429 #define E1000_HOST_IF 0x08800 /* Host Interface */
430 430 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
431 431 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
432 432 /* Flexible Host Filter Table */
433 433 #define E1000_FHFT(_n) (0x09000 + (_n * 0x100))
434 434 /* Ext Flexible Host Filter Table */
435 435 #define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100))
436 436
437 437 #define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
438 438 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
439 439 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */
440 440 /* Software-Firmware Synchronization - RW */
441 441 #define E1000_SW_FW_SYNC 0x05B5C
442 442 #define E1000_CCMCTL 0x05B48 /* CCM Control Register */
443 443 #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */
444 444 #define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */
445 445 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
446 446 #define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */
447 447 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
448 448 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
449 449 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
450 450 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
451 451 /* Function Active and Power State to MNG */
452 452 #define E1000_FACTPS 0x05B30
453 453 #define E1000_SWSM 0x05B50 /* SW Semaphore */
454 454 #define E1000_FWSM 0x05B54 /* FW Semaphore */
455 455 /* Driver-only SW semaphore (not used by BOOT agents) */
456 456 #define E1000_SWSM2 0x05B58
457 457 #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */
458 458 #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */
459 459 #define E1000_UFUSE 0x05B78 /* UFUSE - RO */
460 460 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
461 461 #define E1000_HICR 0x08F00 /* Host Interface Control */
462 462
463 463 /* RSS registers */
464 464 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
465 465 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
466 466 #define E1000_IMIR(_i) (0x05A80 + ((_i) * 4)) /* Immediate Interrupt */
467 467 /* Immediate Interrupt Ext */
468 468 #define E1000_IMIREXT(_i) (0x05AA0 + ((_i) * 4))
469 469 #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
470 470 /* MSI-X Allocation Register (_i) - RW */
471 471 #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4))
472 472 /* MSI-X Table entry addr low reg 0 - RW */
473 473 #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10))
474 474 /* MSI-X Table entry addr upper reg 0 - RW */
475 475 #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10))
476 476 /* MSI-X Table entry message reg 0 - RW */
477 477 #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10))
478 478 /* MSI-X Table entry vector ctrl reg 0 - RW */
479 479 #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10))
480 480 #define E1000_MSIXPBA 0x0E000 /* MSI-X Pending bit array */
481 481 /* Redirection Table - RW Array */
482 482 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
483 483 /* RSS Random Key - RW Array */
484 484 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4))
485 485 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
486 486 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
487 487 /* VT Registers */
488 488 #define E1000_SWPBS 0x03004 /* Switch Packet Buffer Size - RW */
489 489 #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
490 490 #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
491 491 #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
492 492 #define E1000_VFRE 0x00C8C /* VF Receive Enables */
493 493 #define E1000_VFTE 0x00C90 /* VF Transmit Enables */
494 494 #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
495 495 #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
496 496 #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
497 497 #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
498 498 #define E1000_IOVTCL 0x05BBC /* IOV Control Register */
499 499 #define E1000_VMRCTL 0X05D80 /* Virtual Mirror Rule Control */
500 500 /* These act per VF so an array friendly macro is used */
501 501 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
502 502 #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
503 503 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
504 504 #define E1000_VFVMBMEM(_n) (0x00800 + (_n))
505 505 #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
506 506 /* VLAN Virtual Machine Filter - RW */
507 507 #define E1000_VLVF(_n) (0x05D00 + (4 * (_n)))
508 508 #define E1000_VMVIR(_n) (0x03700 + (4 * (_n)))
509 509
510 510 /* Filtering Registers */
511 511 #define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
512 512 #define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
513 513 #define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
514 514 #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
515 515 #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
516 516 #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
517 517 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
518 518
519 519 #define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */
520 520 #define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */
521 521 #define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */
522 522 #define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */
523 523 #define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */
524 524 /* Tx Desc plane TC Rate-scheduler config */
525 525 #define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4))
526 526 /* Tx Packet plane TC Rate-Scheduler Config */
527 527 #define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4))
528 528 /* Rx Packet plane TC Rate-Scheduler Config */
529 529 #define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4))
530 530 /* Tx Desc Plane TC Rate-Scheduler Status */
531 531 #define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4))
532 532 /* Tx Desc Plane TC Rate-Scheduler MMW */
533 533 #define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4))
534 534 /* Tx Packet plane TC Rate-Scheduler Status */
535 535 #define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4))
536 536 /* Tx Packet plane TC Rate-scheduler MMW */
537 537 #define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4))
538 538 /* Rx Packet plane TC Rate-Scheduler Status */
539 539 #define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4))
540 540 /* Rx Packet plane TC Rate-Scheduler MMW */
541 541 #define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4))
542 542 /* Tx Desc plane VM Rate-Scheduler MMW */
543 543 #define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4))
544 544 /* Tx BCN Rate-Scheduler MMW */
545 545 #define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4))
546 546 #define E1000_RTTDQSEL 0x3604 /* Tx Desc Plane Queue Select */
547 547 #define E1000_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */
548 548 #define E1000_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */
549 549 #define E1000_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */
550 550 #define E1000_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */
551 551 #define E1000_RTTBCNCR 0xB200 /* Tx BCN Control Register */
552 552 #define E1000_RTTBCNTG 0x35A4 /* Tx BCN Tagging */
553 553 #define E1000_RTTBCNCP 0xB208 /* Tx BCN Congestion point */
554 554 #define E1000_RTRBCNCR 0xB20C /* Rx BCN Control Register */
555 555 #define E1000_RTTBCNRD 0x36B8 /* Tx BCN Rate Drift */
556 556 #define E1000_PFCTOP 0x1080 /* Priority Flow Control Type and Opcode */
557 557 #define E1000_RTTBCNIDX 0xB204 /* Tx BCN Congestion Point */
558 558 #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */
559 559 #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */
560 560
561 561 /* DMA Coalescing registers */
562 562 #define E1000_DMACR 0x02508 /* Control Register */
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563 563 #define E1000_DMCTXTH 0x03550 /* Transmit Threshold */
564 564 #define E1000_DMCTLX 0x02514 /* Time to Lx Request */
565 565 #define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */
566 566 #define E1000_DMCCNT 0x05DD4 /* Current RX Count */
567 567 #define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */
568 568 #define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */
569 569
570 570 /* PCIe Parity Status Register */
571 571 #define E1000_PCIEERRSTS 0x05BA8
572 572
573 +/* Energy Efficient Ethernet "EEE" registers */
574 +#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */
575 +#define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */
576 +#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE" */
577 +#define E1000_EEE_SU 0x0E34 /* EEE Setup */
578 +#define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */
579 +#define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */
580 +
573 581 #ifdef __cplusplus
574 582 }
575 583 #endif
576 584 #endif /* _IGB_REGS_H */
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