3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
  24  */
  25 
  26 /*
  27  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
  28  */
  29 
  30 /* IntelVersion: 1.82.2.1 v3_3_14_3_BHSW1 */
  31 
  32 #ifndef _IGB_REGS_H
  33 #define _IGB_REGS_H
  34 
  35 #ifdef __cplusplus
  36 extern "C" {
  37 #endif
  38 
  39 #define E1000_CTRL      0x00000  /* Device Control - RW */
  40 #define E1000_CTRL_DUP  0x00004  /* Device Control Duplicate (Shadow) - RW */
  41 #define E1000_STATUS    0x00008  /* Device Status - RO */
  42 #define E1000_EECD      0x00010  /* EEPROM/Flash Control - RW */
  43 #define E1000_EERD      0x00014  /* EEPROM Read - RW */

 553 #define E1000_RTTBCNCP  0xB208  /* Tx BCN Congestion point */
 554 #define E1000_RTRBCNCR  0xB20C  /* Rx BCN Control Register */
 555 #define E1000_RTTBCNRD  0x36B8  /* Tx BCN Rate Drift */
 556 #define E1000_PFCTOP    0x1080  /* Priority Flow Control Type and Opcode */
 557 #define E1000_RTTBCNIDX 0xB204  /* Tx BCN Congestion Point */
 558 #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */
 559 #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */
 560 
 561 /* DMA Coalescing registers */
 562 #define E1000_DMACR     0x02508 /* Control Register */
 563 #define E1000_DMCTXTH   0x03550 /* Transmit Threshold */
 564 #define E1000_DMCTLX    0x02514 /* Time to Lx Request */
 565 #define E1000_DMCRTRH   0x05DD0 /* Receive Packet Rate Threshold */
 566 #define E1000_DMCCNT    0x05DD4 /* Current RX Count */
 567 #define E1000_FCRTC     0x02170 /* Flow Control Rx high watermark */
 568 #define E1000_PCIEMISC  0x05BB8 /* PCIE misc config register */
 569 
 570 /* PCIe Parity Status Register */
 571 #define E1000_PCIEERRSTS        0x05BA8
 572 








 573 #ifdef __cplusplus
 574 }
 575 #endif
 576 #endif  /* _IGB_REGS_H */

   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
  24  */
  25 
  26 /*
  27  * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
  28  */
  29 
  30 /* IntelVersion: 1.82.2.1 v3_3_14_3_BHSW1 */
  31 
  32 #ifndef _IGB_REGS_H
  33 #define _IGB_REGS_H
  34 
  35 #ifdef __cplusplus
  36 extern "C" {
  37 #endif
  38 
  39 #define E1000_CTRL      0x00000  /* Device Control - RW */
  40 #define E1000_CTRL_DUP  0x00004  /* Device Control Duplicate (Shadow) - RW */
  41 #define E1000_STATUS    0x00008  /* Device Status - RO */
  42 #define E1000_EECD      0x00010  /* EEPROM/Flash Control - RW */
  43 #define E1000_EERD      0x00014  /* EEPROM Read - RW */

 553 #define E1000_RTTBCNCP  0xB208  /* Tx BCN Congestion point */
 554 #define E1000_RTRBCNCR  0xB20C  /* Rx BCN Control Register */
 555 #define E1000_RTTBCNRD  0x36B8  /* Tx BCN Rate Drift */
 556 #define E1000_PFCTOP    0x1080  /* Priority Flow Control Type and Opcode */
 557 #define E1000_RTTBCNIDX 0xB204  /* Tx BCN Congestion Point */
 558 #define E1000_RTTBCNACH 0x0B214 /* Tx BCN Control High */
 559 #define E1000_RTTBCNACL 0x0B210 /* Tx BCN Control Low */
 560 
 561 /* DMA Coalescing registers */
 562 #define E1000_DMACR     0x02508 /* Control Register */
 563 #define E1000_DMCTXTH   0x03550 /* Transmit Threshold */
 564 #define E1000_DMCTLX    0x02514 /* Time to Lx Request */
 565 #define E1000_DMCRTRH   0x05DD0 /* Receive Packet Rate Threshold */
 566 #define E1000_DMCCNT    0x05DD4 /* Current RX Count */
 567 #define E1000_FCRTC     0x02170 /* Flow Control Rx high watermark */
 568 #define E1000_PCIEMISC  0x05BB8 /* PCIE misc config register */
 569 
 570 /* PCIe Parity Status Register */
 571 #define E1000_PCIEERRSTS        0x05BA8
 572 
 573 /* Energy Efficient Ethernet "EEE" registers */
 574 #define E1000_IPCNFG    0x0E38 /* Internal PHY Configuration */
 575 #define E1000_LTRC      0x01A0 /* Latency Tolerance Reporting Control */
 576 #define E1000_EEER      0x0E30 /* Energy Efficient Ethernet "EEE" */
 577 #define E1000_EEE_SU    0x0E34 /* EEE Setup */
 578 #define E1000_TLPIC     0x4148 /* EEE Tx LPI Count - TLPIC */
 579 #define E1000_RLPIC     0x414C /* EEE Rx LPI Count - RLPIC */
 580 
 581 #ifdef __cplusplus
 582 }
 583 #endif
 584 #endif  /* _IGB_REGS_H */