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2038 Add in I350 and ET2 support into igb
Reviewed by: Dan McDonald <danmcd@nexenta.com>
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--- old/usr/src/uts/common/io/igb/igb_main.c
+++ new/usr/src/uts/common/io/igb/igb_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
23 + * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 */
29 29
30 30 #include "igb_sw.h"
31 31
32 32 static char ident[] = "Intel 1Gb Ethernet";
33 -static char igb_version[] = "igb 1.1.17";
33 +static char igb_version[] = "igb 1.1.18";
34 34
35 35 /*
36 36 * Local function protoypes
37 37 */
38 38 static int igb_register_mac(igb_t *);
39 39 static int igb_identify_hardware(igb_t *);
40 40 static int igb_regs_map(igb_t *);
41 41 static void igb_init_properties(igb_t *);
42 42 static int igb_init_driver_settings(igb_t *);
43 43 static void igb_init_locks(igb_t *);
44 44 static void igb_destroy_locks(igb_t *);
45 45 static int igb_init_mac_address(igb_t *);
46 46 static int igb_init(igb_t *);
47 47 static int igb_init_adapter(igb_t *);
48 48 static void igb_stop_adapter(igb_t *);
49 49 static int igb_reset(igb_t *);
50 50 static void igb_tx_clean(igb_t *);
51 51 static boolean_t igb_tx_drain(igb_t *);
52 52 static boolean_t igb_rx_drain(igb_t *);
53 53 static int igb_alloc_rings(igb_t *);
54 54 static int igb_alloc_rx_data(igb_t *);
55 55 static void igb_free_rx_data(igb_t *);
56 56 static void igb_free_rings(igb_t *);
57 57 static void igb_setup_rings(igb_t *);
58 58 static void igb_setup_rx(igb_t *);
59 59 static void igb_setup_tx(igb_t *);
60 60 static void igb_setup_rx_ring(igb_rx_ring_t *);
61 61 static void igb_setup_tx_ring(igb_tx_ring_t *);
62 62 static void igb_setup_rss(igb_t *);
63 63 static void igb_setup_mac_rss_classify(igb_t *);
64 64 static void igb_setup_mac_classify(igb_t *);
65 65 static void igb_init_unicst(igb_t *);
66 66 static void igb_setup_multicst(igb_t *);
67 67 static void igb_get_phy_state(igb_t *);
68 68 static void igb_param_sync(igb_t *);
69 69 static void igb_get_conf(igb_t *);
70 70 static int igb_get_prop(igb_t *, char *, int, int, int);
71 71 static boolean_t igb_is_link_up(igb_t *);
72 72 static boolean_t igb_link_check(igb_t *);
73 73 static void igb_local_timer(void *);
74 74 static void igb_link_timer(void *);
75 75 static void igb_arm_watchdog_timer(igb_t *);
76 76 static void igb_start_watchdog_timer(igb_t *);
77 77 static void igb_restart_watchdog_timer(igb_t *);
78 78 static void igb_stop_watchdog_timer(igb_t *);
79 79 static void igb_start_link_timer(igb_t *);
80 80 static void igb_stop_link_timer(igb_t *);
81 81 static void igb_disable_adapter_interrupts(igb_t *);
82 82 static void igb_enable_adapter_interrupts_82575(igb_t *);
83 83 static void igb_enable_adapter_interrupts_82576(igb_t *);
84 84 static void igb_enable_adapter_interrupts_82580(igb_t *);
85 85 static boolean_t is_valid_mac_addr(uint8_t *);
86 86 static boolean_t igb_stall_check(igb_t *);
87 87 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t);
88 88 static void igb_set_external_loopback(igb_t *);
89 89 static void igb_set_internal_phy_loopback(igb_t *);
90 90 static void igb_set_internal_serdes_loopback(igb_t *);
91 91 static boolean_t igb_find_mac_address(igb_t *);
92 92 static int igb_alloc_intrs(igb_t *);
93 93 static int igb_alloc_intr_handles(igb_t *, int);
94 94 static int igb_add_intr_handlers(igb_t *);
95 95 static void igb_rem_intr_handlers(igb_t *);
96 96 static void igb_rem_intrs(igb_t *);
97 97 static int igb_enable_intrs(igb_t *);
98 98 static int igb_disable_intrs(igb_t *);
99 99 static void igb_setup_msix_82575(igb_t *);
100 100 static void igb_setup_msix_82576(igb_t *);
101 101 static void igb_setup_msix_82580(igb_t *);
102 102 static uint_t igb_intr_legacy(void *, void *);
103 103 static uint_t igb_intr_msi(void *, void *);
104 104 static uint_t igb_intr_rx(void *, void *);
105 105 static uint_t igb_intr_tx(void *, void *);
106 106 static uint_t igb_intr_tx_other(void *, void *);
107 107 static void igb_intr_rx_work(igb_rx_ring_t *);
108 108 static void igb_intr_tx_work(igb_tx_ring_t *);
109 109 static void igb_intr_link_work(igb_t *);
110 110 static void igb_get_driver_control(struct e1000_hw *);
111 111 static void igb_release_driver_control(struct e1000_hw *);
112 112
113 113 static int igb_attach(dev_info_t *, ddi_attach_cmd_t);
114 114 static int igb_detach(dev_info_t *, ddi_detach_cmd_t);
115 115 static int igb_resume(dev_info_t *);
116 116 static int igb_suspend(dev_info_t *);
117 117 static int igb_quiesce(dev_info_t *);
118 118 static void igb_unconfigure(dev_info_t *, igb_t *);
119 119 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
120 120 const void *);
121 121 static void igb_fm_init(igb_t *);
122 122 static void igb_fm_fini(igb_t *);
123 123 static void igb_release_multicast(igb_t *);
124 124
125 125 char *igb_priv_props[] = {
126 126 "_tx_copy_thresh",
127 127 "_tx_recycle_thresh",
128 128 "_tx_overload_thresh",
129 129 "_tx_resched_thresh",
130 130 "_rx_copy_thresh",
131 131 "_rx_limit_per_intr",
132 132 "_intr_throttling",
133 133 "_adv_pause_cap",
134 134 "_adv_asym_pause_cap",
135 135 NULL
136 136 };
137 137
138 138 static struct cb_ops igb_cb_ops = {
139 139 nulldev, /* cb_open */
140 140 nulldev, /* cb_close */
141 141 nodev, /* cb_strategy */
142 142 nodev, /* cb_print */
143 143 nodev, /* cb_dump */
144 144 nodev, /* cb_read */
145 145 nodev, /* cb_write */
146 146 nodev, /* cb_ioctl */
147 147 nodev, /* cb_devmap */
148 148 nodev, /* cb_mmap */
149 149 nodev, /* cb_segmap */
150 150 nochpoll, /* cb_chpoll */
151 151 ddi_prop_op, /* cb_prop_op */
152 152 NULL, /* cb_stream */
153 153 D_MP | D_HOTPLUG, /* cb_flag */
154 154 CB_REV, /* cb_rev */
155 155 nodev, /* cb_aread */
156 156 nodev /* cb_awrite */
157 157 };
158 158
159 159 static struct dev_ops igb_dev_ops = {
160 160 DEVO_REV, /* devo_rev */
161 161 0, /* devo_refcnt */
162 162 NULL, /* devo_getinfo */
163 163 nulldev, /* devo_identify */
164 164 nulldev, /* devo_probe */
165 165 igb_attach, /* devo_attach */
166 166 igb_detach, /* devo_detach */
167 167 nodev, /* devo_reset */
168 168 &igb_cb_ops, /* devo_cb_ops */
169 169 NULL, /* devo_bus_ops */
170 170 ddi_power, /* devo_power */
171 171 igb_quiesce, /* devo_quiesce */
172 172 };
173 173
174 174 static struct modldrv igb_modldrv = {
175 175 &mod_driverops, /* Type of module. This one is a driver */
176 176 ident, /* Discription string */
177 177 &igb_dev_ops, /* driver ops */
178 178 };
179 179
180 180 static struct modlinkage igb_modlinkage = {
181 181 MODREV_1, &igb_modldrv, NULL
182 182 };
183 183
184 184 /* Access attributes for register mapping */
185 185 ddi_device_acc_attr_t igb_regs_acc_attr = {
186 186 DDI_DEVICE_ATTR_V1,
187 187 DDI_STRUCTURE_LE_ACC,
188 188 DDI_STRICTORDER_ACC,
189 189 DDI_FLAGERR_ACC
190 190 };
191 191
192 192 #define IGB_M_CALLBACK_FLAGS \
193 193 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
194 194
195 195 static mac_callbacks_t igb_m_callbacks = {
196 196 IGB_M_CALLBACK_FLAGS,
197 197 igb_m_stat,
198 198 igb_m_start,
199 199 igb_m_stop,
200 200 igb_m_promisc,
201 201 igb_m_multicst,
202 202 NULL,
203 203 NULL,
204 204 NULL,
205 205 igb_m_ioctl,
206 206 igb_m_getcapab,
207 207 NULL,
208 208 NULL,
209 209 igb_m_setprop,
210 210 igb_m_getprop,
211 211 igb_m_propinfo
212 212 };
213 213
214 214 /*
215 215 * Initialize capabilities of each supported adapter type
216 216 */
217 217 static adapter_info_t igb_82575_cap = {
218 218 /* limits */
219 219 4, /* maximum number of rx queues */
220 220 1, /* minimum number of rx queues */
221 221 4, /* default number of rx queues */
222 222 4, /* maximum number of tx queues */
223 223 1, /* minimum number of tx queues */
224 224 4, /* default number of tx queues */
225 225 65535, /* maximum interrupt throttle rate */
226 226 0, /* minimum interrupt throttle rate */
227 227 200, /* default interrupt throttle rate */
228 228
229 229 /* function pointers */
230 230 igb_enable_adapter_interrupts_82575,
231 231 igb_setup_msix_82575,
232 232
233 233 /* capabilities */
234 234 (IGB_FLAG_HAS_DCA | /* capability flags */
235 235 IGB_FLAG_VMDQ_POOL),
236 236
237 237 0xffc00000 /* mask for RXDCTL register */
238 238 };
239 239
240 240 static adapter_info_t igb_82576_cap = {
241 241 /* limits */
242 242 16, /* maximum number of rx queues */
243 243 1, /* minimum number of rx queues */
244 244 4, /* default number of rx queues */
245 245 16, /* maximum number of tx queues */
246 246 1, /* minimum number of tx queues */
247 247 4, /* default number of tx queues */
248 248 65535, /* maximum interrupt throttle rate */
249 249 0, /* minimum interrupt throttle rate */
250 250 200, /* default interrupt throttle rate */
251 251
252 252 /* function pointers */
253 253 igb_enable_adapter_interrupts_82576,
254 254 igb_setup_msix_82576,
255 255
256 256 /* capabilities */
257 257 (IGB_FLAG_HAS_DCA | /* capability flags */
258 258 IGB_FLAG_VMDQ_POOL |
259 259 IGB_FLAG_NEED_CTX_IDX),
260 260
261 261 0xffe00000 /* mask for RXDCTL register */
262 262 };
263 263
264 264 static adapter_info_t igb_82580_cap = {
265 265 /* limits */
266 266 8, /* maximum number of rx queues */
267 267 1, /* minimum number of rx queues */
268 268 4, /* default number of rx queues */
269 269 8, /* maximum number of tx queues */
270 270 1, /* minimum number of tx queues */
271 271 4, /* default number of tx queues */
272 272 65535, /* maximum interrupt throttle rate */
273 273 0, /* minimum interrupt throttle rate */
274 274 200, /* default interrupt throttle rate */
275 275
276 276 /* function pointers */
277 277 igb_enable_adapter_interrupts_82580,
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278 278 igb_setup_msix_82580,
279 279
280 280 /* capabilities */
281 281 (IGB_FLAG_HAS_DCA | /* capability flags */
282 282 IGB_FLAG_VMDQ_POOL |
283 283 IGB_FLAG_NEED_CTX_IDX),
284 284
285 285 0xffe00000 /* mask for RXDCTL register */
286 286 };
287 287
288 +static adapter_info_t igb_i350_cap = {
289 + /* limits */
290 + 8, /* maximum number of rx queues */
291 + 1, /* minimum number of rx queues */
292 + 4, /* default number of rx queues */
293 + 8, /* maximum number of tx queues */
294 + 1, /* minimum number of tx queues */
295 + 4, /* default number of tx queues */
296 + 65535, /* maximum interrupt throttle rate */
297 + 0, /* minimum interrupt throttle rate */
298 + 200, /* default interrupt throttle rate */
299 +
300 + /* function pointers */
301 + igb_enable_adapter_interrupts_82580,
302 + igb_setup_msix_82580,
303 +
304 + /* capabilities */
305 + (IGB_FLAG_HAS_DCA | /* capability flags */
306 + IGB_FLAG_VMDQ_POOL |
307 + IGB_FLAG_NEED_CTX_IDX),
308 +
309 + 0xffe00000 /* mask for RXDCTL register */
310 +};
311 +
288 312 /*
289 313 * Module Initialization Functions
290 314 */
291 315
292 316 int
293 317 _init(void)
294 318 {
295 319 int status;
296 320
297 321 mac_init_ops(&igb_dev_ops, MODULE_NAME);
298 322
299 323 status = mod_install(&igb_modlinkage);
300 324
301 325 if (status != DDI_SUCCESS) {
302 326 mac_fini_ops(&igb_dev_ops);
303 327 }
304 328
305 329 return (status);
306 330 }
307 331
308 332 int
309 333 _fini(void)
310 334 {
311 335 int status;
312 336
313 337 status = mod_remove(&igb_modlinkage);
314 338
315 339 if (status == DDI_SUCCESS) {
316 340 mac_fini_ops(&igb_dev_ops);
317 341 }
318 342
319 343 return (status);
320 344
321 345 }
322 346
323 347 int
324 348 _info(struct modinfo *modinfop)
325 349 {
326 350 int status;
327 351
328 352 status = mod_info(&igb_modlinkage, modinfop);
329 353
330 354 return (status);
331 355 }
332 356
333 357 /*
334 358 * igb_attach - driver attach
335 359 *
336 360 * This function is the device specific initialization entry
337 361 * point. This entry point is required and must be written.
338 362 * The DDI_ATTACH command must be provided in the attach entry
339 363 * point. When attach() is called with cmd set to DDI_ATTACH,
340 364 * all normal kernel services (such as kmem_alloc(9F)) are
341 365 * available for use by the driver.
342 366 *
343 367 * The attach() function will be called once for each instance
344 368 * of the device on the system with cmd set to DDI_ATTACH.
345 369 * Until attach() succeeds, the only driver entry points which
346 370 * may be called are open(9E) and getinfo(9E).
347 371 */
348 372 static int
349 373 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
350 374 {
351 375 igb_t *igb;
352 376 struct igb_osdep *osdep;
353 377 struct e1000_hw *hw;
354 378 int instance;
355 379
356 380 /*
357 381 * Check the command and perform corresponding operations
358 382 */
359 383 switch (cmd) {
360 384 default:
361 385 return (DDI_FAILURE);
362 386
363 387 case DDI_RESUME:
364 388 return (igb_resume(devinfo));
365 389
366 390 case DDI_ATTACH:
367 391 break;
368 392 }
369 393
370 394 /* Get the device instance */
371 395 instance = ddi_get_instance(devinfo);
372 396
373 397 /* Allocate memory for the instance data structure */
374 398 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP);
375 399
376 400 igb->dip = devinfo;
377 401 igb->instance = instance;
378 402
379 403 hw = &igb->hw;
380 404 osdep = &igb->osdep;
381 405 hw->back = osdep;
382 406 osdep->igb = igb;
383 407
384 408 /* Attach the instance pointer to the dev_info data structure */
385 409 ddi_set_driver_private(devinfo, igb);
386 410
387 411
388 412 /* Initialize for fma support */
389 413 igb->fm_capabilities = igb_get_prop(igb, "fm-capable",
390 414 0, 0x0f,
391 415 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
392 416 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
393 417 igb_fm_init(igb);
394 418 igb->attach_progress |= ATTACH_PROGRESS_FMINIT;
395 419
396 420 /*
397 421 * Map PCI config space registers
398 422 */
399 423 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
400 424 igb_error(igb, "Failed to map PCI configurations");
401 425 goto attach_fail;
402 426 }
403 427 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
404 428
405 429 /*
406 430 * Identify the chipset family
407 431 */
408 432 if (igb_identify_hardware(igb) != IGB_SUCCESS) {
409 433 igb_error(igb, "Failed to identify hardware");
410 434 goto attach_fail;
411 435 }
412 436
413 437 /*
414 438 * Map device registers
415 439 */
416 440 if (igb_regs_map(igb) != IGB_SUCCESS) {
417 441 igb_error(igb, "Failed to map device registers");
418 442 goto attach_fail;
419 443 }
420 444 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
421 445
422 446 /*
423 447 * Initialize driver parameters
424 448 */
425 449 igb_init_properties(igb);
426 450 igb->attach_progress |= ATTACH_PROGRESS_PROPS;
427 451
428 452 /*
429 453 * Allocate interrupts
430 454 */
431 455 if (igb_alloc_intrs(igb) != IGB_SUCCESS) {
432 456 igb_error(igb, "Failed to allocate interrupts");
433 457 goto attach_fail;
434 458 }
435 459 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
436 460
437 461 /*
438 462 * Allocate rx/tx rings based on the ring numbers.
439 463 * The actual numbers of rx/tx rings are decided by the number of
440 464 * allocated interrupt vectors, so we should allocate the rings after
441 465 * interrupts are allocated.
442 466 */
443 467 if (igb_alloc_rings(igb) != IGB_SUCCESS) {
444 468 igb_error(igb, "Failed to allocate rx/tx rings or groups");
445 469 goto attach_fail;
446 470 }
447 471 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
448 472
449 473 /*
450 474 * Add interrupt handlers
451 475 */
452 476 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) {
453 477 igb_error(igb, "Failed to add interrupt handlers");
454 478 goto attach_fail;
455 479 }
456 480 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
457 481
458 482 /*
459 483 * Initialize driver parameters
460 484 */
461 485 if (igb_init_driver_settings(igb) != IGB_SUCCESS) {
462 486 igb_error(igb, "Failed to initialize driver settings");
463 487 goto attach_fail;
464 488 }
465 489
466 490 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) {
467 491 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
468 492 goto attach_fail;
469 493 }
470 494
471 495 /*
472 496 * Initialize mutexes for this device.
473 497 * Do this before enabling the interrupt handler and
474 498 * register the softint to avoid the condition where
475 499 * interrupt handler can try using uninitialized mutex
476 500 */
477 501 igb_init_locks(igb);
478 502 igb->attach_progress |= ATTACH_PROGRESS_LOCKS;
479 503
480 504 /*
481 505 * Initialize the adapter
482 506 */
483 507 if (igb_init(igb) != IGB_SUCCESS) {
484 508 igb_error(igb, "Failed to initialize adapter");
485 509 goto attach_fail;
486 510 }
487 511 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
488 512
489 513 /*
490 514 * Initialize statistics
491 515 */
492 516 if (igb_init_stats(igb) != IGB_SUCCESS) {
493 517 igb_error(igb, "Failed to initialize statistics");
494 518 goto attach_fail;
495 519 }
496 520 igb->attach_progress |= ATTACH_PROGRESS_STATS;
497 521
498 522 /*
499 523 * Register the driver to the MAC
500 524 */
501 525 if (igb_register_mac(igb) != IGB_SUCCESS) {
502 526 igb_error(igb, "Failed to register MAC");
503 527 goto attach_fail;
504 528 }
505 529 igb->attach_progress |= ATTACH_PROGRESS_MAC;
506 530
507 531 /*
508 532 * Now that mutex locks are initialized, and the chip is also
509 533 * initialized, enable interrupts.
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510 534 */
511 535 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
512 536 igb_error(igb, "Failed to enable DDI interrupts");
513 537 goto attach_fail;
514 538 }
515 539 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
516 540
517 541 igb_log(igb, "%s", igb_version);
518 542 atomic_or_32(&igb->igb_state, IGB_INITIALIZED);
519 543
544 + /*
545 + * Newer models have Energy Efficient Ethernet, let's disable this by
546 + * default.
547 + */
548 + if (igb->hw.mac.type == e1000_i350)
549 + (void) e1000_set_eee_i350(&igb->hw);
550 +
520 551 return (DDI_SUCCESS);
521 552
522 553 attach_fail:
523 554 igb_unconfigure(devinfo, igb);
524 555 return (DDI_FAILURE);
525 556 }
526 557
527 558 /*
528 559 * igb_detach - driver detach
529 560 *
530 561 * The detach() function is the complement of the attach routine.
531 562 * If cmd is set to DDI_DETACH, detach() is used to remove the
532 563 * state associated with a given instance of a device node
533 564 * prior to the removal of that instance from the system.
534 565 *
535 566 * The detach() function will be called once for each instance
536 567 * of the device for which there has been a successful attach()
537 568 * once there are no longer any opens on the device.
538 569 *
539 570 * Interrupts routine are disabled, All memory allocated by this
540 571 * driver are freed.
541 572 */
542 573 static int
543 574 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
544 575 {
545 576 igb_t *igb;
546 577
547 578 /*
548 579 * Check detach command
549 580 */
550 581 switch (cmd) {
551 582 default:
552 583 return (DDI_FAILURE);
553 584
554 585 case DDI_SUSPEND:
555 586 return (igb_suspend(devinfo));
556 587
557 588 case DDI_DETACH:
558 589 break;
559 590 }
560 591
561 592
562 593 /*
563 594 * Get the pointer to the driver private data structure
564 595 */
565 596 igb = (igb_t *)ddi_get_driver_private(devinfo);
566 597 if (igb == NULL)
567 598 return (DDI_FAILURE);
568 599
569 600 /*
570 601 * Unregister MAC. If failed, we have to fail the detach
571 602 */
572 603 if (mac_unregister(igb->mac_hdl) != 0) {
573 604 igb_error(igb, "Failed to unregister MAC");
574 605 return (DDI_FAILURE);
575 606 }
576 607 igb->attach_progress &= ~ATTACH_PROGRESS_MAC;
577 608
578 609 /*
579 610 * If the device is still running, it needs to be stopped first.
580 611 * This check is necessary because under some specific circumstances,
581 612 * the detach routine can be called without stopping the interface
582 613 * first.
583 614 */
584 615 mutex_enter(&igb->gen_lock);
585 616 if (igb->igb_state & IGB_STARTED) {
586 617 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
587 618 igb_stop(igb, B_TRUE);
588 619 mutex_exit(&igb->gen_lock);
589 620 /* Disable and stop the watchdog timer */
590 621 igb_disable_watchdog_timer(igb);
591 622 } else
592 623 mutex_exit(&igb->gen_lock);
593 624
594 625 /*
595 626 * Check if there are still rx buffers held by the upper layer.
596 627 * If so, fail the detach.
597 628 */
598 629 if (!igb_rx_drain(igb))
599 630 return (DDI_FAILURE);
600 631
601 632 /*
602 633 * Do the remaining unconfigure routines
603 634 */
604 635 igb_unconfigure(devinfo, igb);
605 636
606 637 return (DDI_SUCCESS);
607 638 }
608 639
609 640 /*
610 641 * quiesce(9E) entry point.
611 642 *
612 643 * This function is called when the system is single-threaded at high
613 644 * PIL with preemption disabled. Therefore, this function must not be
614 645 * blocked.
615 646 *
616 647 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
617 648 * DDI_FAILURE indicates an error condition and should almost never happen.
618 649 */
619 650 static int
620 651 igb_quiesce(dev_info_t *devinfo)
621 652 {
622 653 igb_t *igb;
623 654 struct e1000_hw *hw;
624 655
625 656 igb = (igb_t *)ddi_get_driver_private(devinfo);
626 657
627 658 if (igb == NULL)
628 659 return (DDI_FAILURE);
629 660
630 661 hw = &igb->hw;
631 662
632 663 /*
633 664 * Disable the adapter interrupts
634 665 */
635 666 igb_disable_adapter_interrupts(igb);
636 667
637 668 /* Tell firmware driver is no longer in control */
638 669 igb_release_driver_control(hw);
639 670
640 671 /*
641 672 * Reset the chipset
642 673 */
643 674 (void) e1000_reset_hw(hw);
644 675
645 676 /*
646 677 * Reset PHY if possible
647 678 */
648 679 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
649 680 (void) e1000_phy_hw_reset(hw);
650 681
651 682 return (DDI_SUCCESS);
652 683 }
653 684
654 685 /*
655 686 * igb_unconfigure - release all resources held by this instance
656 687 */
657 688 static void
658 689 igb_unconfigure(dev_info_t *devinfo, igb_t *igb)
659 690 {
660 691 /*
661 692 * Disable interrupt
662 693 */
663 694 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
664 695 (void) igb_disable_intrs(igb);
665 696 }
666 697
667 698 /*
668 699 * Unregister MAC
669 700 */
670 701 if (igb->attach_progress & ATTACH_PROGRESS_MAC) {
671 702 (void) mac_unregister(igb->mac_hdl);
672 703 }
673 704
674 705 /*
675 706 * Free statistics
676 707 */
677 708 if (igb->attach_progress & ATTACH_PROGRESS_STATS) {
678 709 kstat_delete((kstat_t *)igb->igb_ks);
679 710 }
680 711
681 712 /*
682 713 * Remove interrupt handlers
683 714 */
684 715 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
685 716 igb_rem_intr_handlers(igb);
686 717 }
687 718
688 719 /*
689 720 * Remove interrupts
690 721 */
691 722 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
692 723 igb_rem_intrs(igb);
693 724 }
694 725
695 726 /*
696 727 * Remove driver properties
697 728 */
698 729 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) {
699 730 (void) ddi_prop_remove_all(devinfo);
700 731 }
701 732
702 733 /*
703 734 * Stop the adapter
704 735 */
705 736 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) {
706 737 mutex_enter(&igb->gen_lock);
707 738 igb_stop_adapter(igb);
708 739 mutex_exit(&igb->gen_lock);
709 740 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
710 741 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED);
711 742 }
712 743
713 744 /*
714 745 * Free multicast table
715 746 */
716 747 igb_release_multicast(igb);
717 748
718 749 /*
719 750 * Free register handle
720 751 */
721 752 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
722 753 if (igb->osdep.reg_handle != NULL)
723 754 ddi_regs_map_free(&igb->osdep.reg_handle);
724 755 }
725 756
726 757 /*
727 758 * Free PCI config handle
728 759 */
729 760 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
730 761 if (igb->osdep.cfg_handle != NULL)
731 762 pci_config_teardown(&igb->osdep.cfg_handle);
732 763 }
733 764
734 765 /*
735 766 * Free locks
736 767 */
737 768 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) {
738 769 igb_destroy_locks(igb);
739 770 }
740 771
741 772 /*
742 773 * Free the rx/tx rings
743 774 */
744 775 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
745 776 igb_free_rings(igb);
746 777 }
747 778
748 779 /*
749 780 * Remove FMA
750 781 */
751 782 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) {
752 783 igb_fm_fini(igb);
753 784 }
754 785
755 786 /*
756 787 * Free the driver data structure
757 788 */
758 789 kmem_free(igb, sizeof (igb_t));
759 790
760 791 ddi_set_driver_private(devinfo, NULL);
761 792 }
762 793
763 794 /*
764 795 * igb_register_mac - Register the driver and its function pointers with
765 796 * the GLD interface
766 797 */
767 798 static int
768 799 igb_register_mac(igb_t *igb)
769 800 {
770 801 struct e1000_hw *hw = &igb->hw;
771 802 mac_register_t *mac;
772 803 int status;
773 804
774 805 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
775 806 return (IGB_FAILURE);
776 807
777 808 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
778 809 mac->m_driver = igb;
779 810 mac->m_dip = igb->dip;
780 811 mac->m_src_addr = hw->mac.addr;
781 812 mac->m_callbacks = &igb_m_callbacks;
782 813 mac->m_min_sdu = 0;
783 814 mac->m_max_sdu = igb->max_frame_size -
784 815 sizeof (struct ether_vlan_header) - ETHERFCSL;
785 816 mac->m_margin = VLAN_TAGSZ;
786 817 mac->m_priv_props = igb_priv_props;
787 818 mac->m_v12n = MAC_VIRT_LEVEL1;
788 819
789 820 status = mac_register(mac, &igb->mac_hdl);
790 821
791 822 mac_free(mac);
792 823
793 824 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE);
794 825 }
795 826
796 827 /*
797 828 * igb_identify_hardware - Identify the type of the chipset
798 829 */
799 830 static int
800 831 igb_identify_hardware(igb_t *igb)
801 832 {
802 833 struct e1000_hw *hw = &igb->hw;
803 834 struct igb_osdep *osdep = &igb->osdep;
804 835
805 836 /*
806 837 * Get the device id
807 838 */
808 839 hw->vendor_id =
809 840 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
810 841 hw->device_id =
811 842 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
812 843 hw->revision_id =
813 844 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
814 845 hw->subsystem_device_id =
815 846 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
816 847 hw->subsystem_vendor_id =
817 848 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
818 849
819 850 /*
820 851 * Set the mac type of the adapter based on the device id
821 852 */
822 853 if (e1000_set_mac_type(hw) != E1000_SUCCESS) {
823 854 return (IGB_FAILURE);
824 855 }
825 856
826 857 /*
827 858 * Install adapter capabilities based on mac type
828 859 */
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829 860 switch (hw->mac.type) {
830 861 case e1000_82575:
831 862 igb->capab = &igb_82575_cap;
832 863 break;
833 864 case e1000_82576:
834 865 igb->capab = &igb_82576_cap;
835 866 break;
836 867 case e1000_82580:
837 868 igb->capab = &igb_82580_cap;
838 869 break;
870 + case e1000_i350:
871 + igb->capab = &igb_i350_cap;
872 + break;
839 873 default:
840 874 return (IGB_FAILURE);
841 875 }
842 876
843 877 return (IGB_SUCCESS);
844 878 }
845 879
846 880 /*
847 881 * igb_regs_map - Map the device registers
848 882 */
849 883 static int
850 884 igb_regs_map(igb_t *igb)
851 885 {
852 886 dev_info_t *devinfo = igb->dip;
853 887 struct e1000_hw *hw = &igb->hw;
854 888 struct igb_osdep *osdep = &igb->osdep;
855 889 off_t mem_size;
856 890
857 891 /*
858 892 * First get the size of device registers to be mapped.
859 893 */
860 894 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) !=
861 895 DDI_SUCCESS) {
862 896 return (IGB_FAILURE);
863 897 }
864 898
865 899 /*
866 900 * Call ddi_regs_map_setup() to map registers
867 901 */
868 902 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET,
869 903 (caddr_t *)&hw->hw_addr, 0,
870 904 mem_size, &igb_regs_acc_attr,
871 905 &osdep->reg_handle)) != DDI_SUCCESS) {
872 906 return (IGB_FAILURE);
873 907 }
874 908
875 909 return (IGB_SUCCESS);
876 910 }
877 911
878 912 /*
879 913 * igb_init_properties - Initialize driver properties
880 914 */
881 915 static void
882 916 igb_init_properties(igb_t *igb)
883 917 {
884 918 /*
885 919 * Get conf file properties, including link settings
886 920 * jumbo frames, ring number, descriptor number, etc.
887 921 */
888 922 igb_get_conf(igb);
889 923 }
890 924
891 925 /*
892 926 * igb_init_driver_settings - Initialize driver settings
893 927 *
894 928 * The settings include hardware function pointers, bus information,
895 929 * rx/tx rings settings, link state, and any other parameters that
896 930 * need to be setup during driver initialization.
897 931 */
898 932 static int
899 933 igb_init_driver_settings(igb_t *igb)
900 934 {
901 935 struct e1000_hw *hw = &igb->hw;
902 936 igb_rx_ring_t *rx_ring;
903 937 igb_tx_ring_t *tx_ring;
904 938 uint32_t rx_size;
905 939 uint32_t tx_size;
906 940 int i;
907 941
908 942 /*
909 943 * Initialize chipset specific hardware function pointers
910 944 */
911 945 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) {
912 946 return (IGB_FAILURE);
913 947 }
914 948
915 949 /*
916 950 * Get bus information
917 951 */
918 952 if (e1000_get_bus_info(hw) != E1000_SUCCESS) {
919 953 return (IGB_FAILURE);
920 954 }
921 955
922 956 /*
923 957 * Get the system page size
924 958 */
925 959 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1);
926 960
927 961 /*
928 962 * Set rx buffer size
929 963 * The IP header alignment room is counted in the calculation.
930 964 * The rx buffer size is in unit of 1K that is required by the
931 965 * chipset hardware.
932 966 */
933 967 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM;
934 968 igb->rx_buf_size = ((rx_size >> 10) +
935 969 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
936 970
937 971 /*
938 972 * Set tx buffer size
939 973 */
940 974 tx_size = igb->max_frame_size;
941 975 igb->tx_buf_size = ((tx_size >> 10) +
942 976 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
943 977
944 978 /*
945 979 * Initialize rx/tx rings parameters
946 980 */
947 981 for (i = 0; i < igb->num_rx_rings; i++) {
948 982 rx_ring = &igb->rx_rings[i];
949 983 rx_ring->index = i;
950 984 rx_ring->igb = igb;
951 985 }
952 986
953 987 for (i = 0; i < igb->num_tx_rings; i++) {
954 988 tx_ring = &igb->tx_rings[i];
955 989 tx_ring->index = i;
956 990 tx_ring->igb = igb;
957 991 if (igb->tx_head_wb_enable)
958 992 tx_ring->tx_recycle = igb_tx_recycle_head_wb;
959 993 else
960 994 tx_ring->tx_recycle = igb_tx_recycle_legacy;
961 995
962 996 tx_ring->ring_size = igb->tx_ring_size;
963 997 tx_ring->free_list_size = igb->tx_ring_size +
964 998 (igb->tx_ring_size >> 1);
965 999 }
966 1000
967 1001 /*
968 1002 * Initialize values of interrupt throttling rates
969 1003 */
970 1004 for (i = 1; i < MAX_NUM_EITR; i++)
971 1005 igb->intr_throttling[i] = igb->intr_throttling[0];
972 1006
973 1007 /*
974 1008 * The initial link state should be "unknown"
975 1009 */
976 1010 igb->link_state = LINK_STATE_UNKNOWN;
977 1011
978 1012 return (IGB_SUCCESS);
979 1013 }
980 1014
981 1015 /*
982 1016 * igb_init_locks - Initialize locks
983 1017 */
984 1018 static void
985 1019 igb_init_locks(igb_t *igb)
986 1020 {
987 1021 igb_rx_ring_t *rx_ring;
988 1022 igb_tx_ring_t *tx_ring;
989 1023 int i;
990 1024
991 1025 for (i = 0; i < igb->num_rx_rings; i++) {
992 1026 rx_ring = &igb->rx_rings[i];
993 1027 mutex_init(&rx_ring->rx_lock, NULL,
994 1028 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
995 1029 }
996 1030
997 1031 for (i = 0; i < igb->num_tx_rings; i++) {
998 1032 tx_ring = &igb->tx_rings[i];
999 1033 mutex_init(&tx_ring->tx_lock, NULL,
1000 1034 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1001 1035 mutex_init(&tx_ring->recycle_lock, NULL,
1002 1036 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1003 1037 mutex_init(&tx_ring->tcb_head_lock, NULL,
1004 1038 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1005 1039 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1006 1040 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1007 1041 }
1008 1042
1009 1043 mutex_init(&igb->gen_lock, NULL,
1010 1044 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1011 1045
1012 1046 mutex_init(&igb->watchdog_lock, NULL,
1013 1047 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1014 1048
1015 1049 mutex_init(&igb->link_lock, NULL,
1016 1050 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri));
1017 1051 }
1018 1052
1019 1053 /*
1020 1054 * igb_destroy_locks - Destroy locks
1021 1055 */
1022 1056 static void
1023 1057 igb_destroy_locks(igb_t *igb)
1024 1058 {
1025 1059 igb_rx_ring_t *rx_ring;
1026 1060 igb_tx_ring_t *tx_ring;
1027 1061 int i;
1028 1062
1029 1063 for (i = 0; i < igb->num_rx_rings; i++) {
1030 1064 rx_ring = &igb->rx_rings[i];
1031 1065 mutex_destroy(&rx_ring->rx_lock);
1032 1066 }
1033 1067
1034 1068 for (i = 0; i < igb->num_tx_rings; i++) {
1035 1069 tx_ring = &igb->tx_rings[i];
1036 1070 mutex_destroy(&tx_ring->tx_lock);
1037 1071 mutex_destroy(&tx_ring->recycle_lock);
1038 1072 mutex_destroy(&tx_ring->tcb_head_lock);
1039 1073 mutex_destroy(&tx_ring->tcb_tail_lock);
1040 1074 }
1041 1075
1042 1076 mutex_destroy(&igb->gen_lock);
1043 1077 mutex_destroy(&igb->watchdog_lock);
1044 1078 mutex_destroy(&igb->link_lock);
1045 1079 }
1046 1080
1047 1081 static int
1048 1082 igb_resume(dev_info_t *devinfo)
1049 1083 {
1050 1084 igb_t *igb;
1051 1085
1052 1086 igb = (igb_t *)ddi_get_driver_private(devinfo);
1053 1087 if (igb == NULL)
1054 1088 return (DDI_FAILURE);
1055 1089
1056 1090 mutex_enter(&igb->gen_lock);
1057 1091
1058 1092 /*
1059 1093 * Enable interrupts
1060 1094 */
1061 1095 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1062 1096 if (igb_enable_intrs(igb) != IGB_SUCCESS) {
1063 1097 igb_error(igb, "Failed to enable DDI interrupts");
1064 1098 mutex_exit(&igb->gen_lock);
1065 1099 return (DDI_FAILURE);
1066 1100 }
1067 1101 }
1068 1102
1069 1103 if (igb->igb_state & IGB_STARTED) {
1070 1104 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) {
1071 1105 mutex_exit(&igb->gen_lock);
1072 1106 return (DDI_FAILURE);
1073 1107 }
1074 1108
1075 1109 /*
1076 1110 * Enable and start the watchdog timer
1077 1111 */
1078 1112 igb_enable_watchdog_timer(igb);
1079 1113 }
1080 1114
1081 1115 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED);
1082 1116
1083 1117 mutex_exit(&igb->gen_lock);
1084 1118
1085 1119 return (DDI_SUCCESS);
1086 1120 }
1087 1121
1088 1122 static int
1089 1123 igb_suspend(dev_info_t *devinfo)
1090 1124 {
1091 1125 igb_t *igb;
1092 1126
1093 1127 igb = (igb_t *)ddi_get_driver_private(devinfo);
1094 1128 if (igb == NULL)
1095 1129 return (DDI_FAILURE);
1096 1130
1097 1131 mutex_enter(&igb->gen_lock);
1098 1132
1099 1133 atomic_or_32(&igb->igb_state, IGB_SUSPENDED);
1100 1134
1101 1135 /*
1102 1136 * Disable interrupts
1103 1137 */
1104 1138 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1105 1139 (void) igb_disable_intrs(igb);
1106 1140 }
1107 1141
1108 1142 if (!(igb->igb_state & IGB_STARTED)) {
1109 1143 mutex_exit(&igb->gen_lock);
1110 1144 return (DDI_SUCCESS);
1111 1145 }
1112 1146
1113 1147 igb_stop(igb, B_FALSE);
1114 1148
1115 1149 mutex_exit(&igb->gen_lock);
1116 1150
1117 1151 /*
1118 1152 * Disable and stop the watchdog timer
1119 1153 */
1120 1154 igb_disable_watchdog_timer(igb);
1121 1155
1122 1156 return (DDI_SUCCESS);
1123 1157 }
1124 1158
1125 1159 static int
1126 1160 igb_init(igb_t *igb)
1127 1161 {
1128 1162 mutex_enter(&igb->gen_lock);
1129 1163
1130 1164 /*
1131 1165 * Initilize the adapter
1132 1166 */
1133 1167 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1134 1168 mutex_exit(&igb->gen_lock);
1135 1169 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1136 1170 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1137 1171 return (IGB_FAILURE);
1138 1172 }
1139 1173
1140 1174 mutex_exit(&igb->gen_lock);
1141 1175
1142 1176 return (IGB_SUCCESS);
1143 1177 }
1144 1178
1145 1179 /*
1146 1180 * igb_init_mac_address - Initialize the default MAC address
1147 1181 *
1148 1182 * On success, the MAC address is entered in the igb->hw.mac.addr
1149 1183 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive
1150 1184 * address register.
1151 1185 *
1152 1186 * Important side effects:
1153 1187 * 1. adapter is reset - this is required to put it in a known state.
1154 1188 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where
1155 1189 * MAC address and all default settings are stored, so a valid checksum
1156 1190 * is required.
1157 1191 */
1158 1192 static int
1159 1193 igb_init_mac_address(igb_t *igb)
1160 1194 {
1161 1195 struct e1000_hw *hw = &igb->hw;
1162 1196
1163 1197 ASSERT(mutex_owned(&igb->gen_lock));
1164 1198
1165 1199 /*
1166 1200 * Reset chipset to put the hardware in a known state
1167 1201 * before we try to get MAC address from NVM.
1168 1202 */
1169 1203 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1170 1204 igb_error(igb, "Adapter reset failed.");
1171 1205 goto init_mac_fail;
1172 1206 }
1173 1207
1174 1208 /*
1175 1209 * NVM validation
1176 1210 */
1177 1211 if (e1000_validate_nvm_checksum(hw) < 0) {
1178 1212 /*
1179 1213 * Some PCI-E parts fail the first check due to
1180 1214 * the link being in sleep state. Call it again,
1181 1215 * if it fails a second time its a real issue.
1182 1216 */
1183 1217 if (e1000_validate_nvm_checksum(hw) < 0) {
1184 1218 igb_error(igb,
1185 1219 "Invalid NVM checksum. Please contact "
1186 1220 "the vendor to update the NVM.");
1187 1221 goto init_mac_fail;
1188 1222 }
1189 1223 }
1190 1224
1191 1225 /*
1192 1226 * Get the mac address
1193 1227 * This function should handle SPARC case correctly.
1194 1228 */
1195 1229 if (!igb_find_mac_address(igb)) {
1196 1230 igb_error(igb, "Failed to get the mac address");
1197 1231 goto init_mac_fail;
1198 1232 }
1199 1233
1200 1234 /* Validate mac address */
1201 1235 if (!is_valid_mac_addr(hw->mac.addr)) {
1202 1236 igb_error(igb, "Invalid mac address");
1203 1237 goto init_mac_fail;
1204 1238 }
1205 1239
1206 1240 return (IGB_SUCCESS);
1207 1241
1208 1242 init_mac_fail:
1209 1243 return (IGB_FAILURE);
1210 1244 }
1211 1245
1212 1246 /*
1213 1247 * igb_init_adapter - Initialize the adapter
1214 1248 */
1215 1249 static int
1216 1250 igb_init_adapter(igb_t *igb)
1217 1251 {
1218 1252 struct e1000_hw *hw = &igb->hw;
1219 1253 uint32_t pba;
1220 1254 uint32_t high_water;
1221 1255 int i;
1222 1256
1223 1257 ASSERT(mutex_owned(&igb->gen_lock));
1224 1258
1225 1259 /*
1226 1260 * In order to obtain the default MAC address, this will reset the
1227 1261 * adapter and validate the NVM that the address and many other
1228 1262 * default settings come from.
1229 1263 */
1230 1264 if (igb_init_mac_address(igb) != IGB_SUCCESS) {
1231 1265 igb_error(igb, "Failed to initialize MAC address");
1232 1266 goto init_adapter_fail;
1233 1267 }
1234 1268
1235 1269 /*
1236 1270 * Setup flow control
1237 1271 *
1238 1272 * These parameters set thresholds for the adapter's generation(Tx)
1239 1273 * and response(Rx) to Ethernet PAUSE frames. These are just threshold
1240 1274 * settings. Flow control is enabled or disabled in the configuration
1241 1275 * file.
1242 1276 * High-water mark is set down from the top of the rx fifo (not
1243 1277 * sensitive to max_frame_size) and low-water is set just below
1244 1278 * high-water mark.
1245 1279 * The high water mark must be low enough to fit one full frame above
1246 1280 * it in the rx FIFO. Should be the lower of:
1247 1281 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full
1248 1282 * frame.
1249 1283 */
1250 1284 /*
1251 1285 * The default setting of PBA is correct for 82575 and other supported
1252 1286 * adapters do not have the E1000_PBA register, so PBA value is only
1253 1287 * used for calculation here and is never written to the adapter.
1254 1288 */
1255 1289 if (hw->mac.type == e1000_82575) {
1256 1290 pba = E1000_PBA_34K;
1257 1291 } else {
1258 1292 pba = E1000_PBA_64K;
1259 1293 }
1260 1294
1261 1295 high_water = min(((pba << 10) * 9 / 10),
1262 1296 ((pba << 10) - igb->max_frame_size));
1263 1297
1264 1298 if (hw->mac.type == e1000_82575) {
1265 1299 /* 8-byte granularity */
1266 1300 hw->fc.high_water = high_water & 0xFFF8;
1267 1301 hw->fc.low_water = hw->fc.high_water - 8;
1268 1302 } else {
1269 1303 /* 16-byte granularity */
1270 1304 hw->fc.high_water = high_water & 0xFFF0;
1271 1305 hw->fc.low_water = hw->fc.high_water - 16;
1272 1306 }
1273 1307
1274 1308 hw->fc.pause_time = E1000_FC_PAUSE_TIME;
1275 1309 hw->fc.send_xon = B_TRUE;
1276 1310
1277 1311 (void) e1000_validate_mdi_setting(hw);
1278 1312
1279 1313 /*
1280 1314 * Reset the chipset hardware the second time to put PBA settings
1281 1315 * into effect.
1282 1316 */
1283 1317 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1284 1318 igb_error(igb, "Second reset failed");
1285 1319 goto init_adapter_fail;
1286 1320 }
1287 1321
1288 1322 /*
1289 1323 * Don't wait for auto-negotiation to complete
1290 1324 */
1291 1325 hw->phy.autoneg_wait_to_complete = B_FALSE;
1292 1326
1293 1327 /*
1294 1328 * Copper options
1295 1329 */
1296 1330 if (hw->phy.media_type == e1000_media_type_copper) {
1297 1331 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1298 1332 hw->phy.disable_polarity_correction = B_FALSE;
1299 1333 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */
1300 1334 }
1301 1335
1302 1336 /*
1303 1337 * Initialize link settings
1304 1338 */
1305 1339 (void) igb_setup_link(igb, B_FALSE);
1306 1340
1307 1341 /*
1308 1342 * Configure/Initialize hardware
1309 1343 */
1310 1344 if (e1000_init_hw(hw) != E1000_SUCCESS) {
1311 1345 igb_error(igb, "Failed to initialize hardware");
1312 1346 goto init_adapter_fail;
1313 1347 }
1314 1348
1315 1349 /*
1316 1350 * Start the link setup timer
1317 1351 */
1318 1352 igb_start_link_timer(igb);
1319 1353
1320 1354 /*
1321 1355 * Disable wakeup control by default
1322 1356 */
1323 1357 E1000_WRITE_REG(hw, E1000_WUC, 0);
1324 1358
1325 1359 /*
1326 1360 * Record phy info in hw struct
1327 1361 */
1328 1362 (void) e1000_get_phy_info(hw);
1329 1363
1330 1364 /*
1331 1365 * Make sure driver has control
1332 1366 */
1333 1367 igb_get_driver_control(hw);
1334 1368
1335 1369 /*
1336 1370 * Restore LED settings to the default from EEPROM
1337 1371 * to meet the standard for Sun platforms.
1338 1372 */
1339 1373 (void) e1000_cleanup_led(hw);
1340 1374
1341 1375 /*
1342 1376 * Setup MSI-X interrupts
1343 1377 */
1344 1378 if (igb->intr_type == DDI_INTR_TYPE_MSIX)
1345 1379 igb->capab->setup_msix(igb);
1346 1380
1347 1381 /*
1348 1382 * Initialize unicast addresses.
1349 1383 */
1350 1384 igb_init_unicst(igb);
1351 1385
1352 1386 /*
1353 1387 * Setup and initialize the mctable structures.
1354 1388 */
1355 1389 igb_setup_multicst(igb);
1356 1390
1357 1391 /*
1358 1392 * Set interrupt throttling rate
1359 1393 */
1360 1394 for (i = 0; i < igb->intr_cnt; i++)
1361 1395 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]);
1362 1396
1363 1397 /*
1364 1398 * Save the state of the phy
1365 1399 */
1366 1400 igb_get_phy_state(igb);
1367 1401
1368 1402 igb_param_sync(igb);
1369 1403
1370 1404 return (IGB_SUCCESS);
1371 1405
1372 1406 init_adapter_fail:
1373 1407 /*
1374 1408 * Reset PHY if possible
1375 1409 */
1376 1410 if (e1000_check_reset_block(hw) == E1000_SUCCESS)
1377 1411 (void) e1000_phy_hw_reset(hw);
1378 1412
1379 1413 return (IGB_FAILURE);
1380 1414 }
1381 1415
1382 1416 /*
1383 1417 * igb_stop_adapter - Stop the adapter
1384 1418 */
1385 1419 static void
1386 1420 igb_stop_adapter(igb_t *igb)
1387 1421 {
1388 1422 struct e1000_hw *hw = &igb->hw;
1389 1423
1390 1424 ASSERT(mutex_owned(&igb->gen_lock));
1391 1425
1392 1426 /* Stop the link setup timer */
1393 1427 igb_stop_link_timer(igb);
1394 1428
1395 1429 /* Tell firmware driver is no longer in control */
1396 1430 igb_release_driver_control(hw);
1397 1431
1398 1432 /*
1399 1433 * Reset the chipset
1400 1434 */
1401 1435 if (e1000_reset_hw(hw) != E1000_SUCCESS) {
1402 1436 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1403 1437 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1404 1438 }
1405 1439
1406 1440 /*
1407 1441 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient
1408 1442 */
1409 1443 }
1410 1444
1411 1445 /*
1412 1446 * igb_reset - Reset the chipset and restart the driver.
1413 1447 *
1414 1448 * It involves stopping and re-starting the chipset,
1415 1449 * and re-configuring the rx/tx rings.
1416 1450 */
1417 1451 static int
1418 1452 igb_reset(igb_t *igb)
1419 1453 {
1420 1454 int i;
1421 1455
1422 1456 mutex_enter(&igb->gen_lock);
1423 1457
1424 1458 ASSERT(igb->igb_state & IGB_STARTED);
1425 1459 atomic_and_32(&igb->igb_state, ~IGB_STARTED);
1426 1460
1427 1461 /*
1428 1462 * Disable the adapter interrupts to stop any rx/tx activities
1429 1463 * before draining pending data and resetting hardware.
1430 1464 */
1431 1465 igb_disable_adapter_interrupts(igb);
1432 1466
1433 1467 /*
1434 1468 * Drain the pending transmit packets
1435 1469 */
1436 1470 (void) igb_tx_drain(igb);
1437 1471
1438 1472 for (i = 0; i < igb->num_rx_rings; i++)
1439 1473 mutex_enter(&igb->rx_rings[i].rx_lock);
1440 1474 for (i = 0; i < igb->num_tx_rings; i++)
1441 1475 mutex_enter(&igb->tx_rings[i].tx_lock);
1442 1476
1443 1477 /*
1444 1478 * Stop the adapter
1445 1479 */
1446 1480 igb_stop_adapter(igb);
1447 1481
1448 1482 /*
1449 1483 * Clean the pending tx data/resources
1450 1484 */
1451 1485 igb_tx_clean(igb);
1452 1486
1453 1487 /*
1454 1488 * Start the adapter
1455 1489 */
1456 1490 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1457 1491 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1458 1492 goto reset_failure;
1459 1493 }
1460 1494
1461 1495 /*
1462 1496 * Setup the rx/tx rings
1463 1497 */
1464 1498 igb->tx_ring_init = B_FALSE;
1465 1499 igb_setup_rings(igb);
1466 1500
1467 1501 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL));
1468 1502
1469 1503 /*
1470 1504 * Enable adapter interrupts
1471 1505 * The interrupts must be enabled after the driver state is START
1472 1506 */
1473 1507 igb->capab->enable_intr(igb);
1474 1508
1475 1509 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1476 1510 goto reset_failure;
1477 1511
1478 1512 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1479 1513 goto reset_failure;
1480 1514
1481 1515 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1482 1516 mutex_exit(&igb->tx_rings[i].tx_lock);
1483 1517 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1484 1518 mutex_exit(&igb->rx_rings[i].rx_lock);
1485 1519
1486 1520 atomic_or_32(&igb->igb_state, IGB_STARTED);
1487 1521
1488 1522 mutex_exit(&igb->gen_lock);
1489 1523
1490 1524 return (IGB_SUCCESS);
1491 1525
1492 1526 reset_failure:
1493 1527 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1494 1528 mutex_exit(&igb->tx_rings[i].tx_lock);
1495 1529 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1496 1530 mutex_exit(&igb->rx_rings[i].rx_lock);
1497 1531
1498 1532 mutex_exit(&igb->gen_lock);
1499 1533
1500 1534 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1501 1535
1502 1536 return (IGB_FAILURE);
1503 1537 }
1504 1538
1505 1539 /*
1506 1540 * igb_tx_clean - Clean the pending transmit packets and DMA resources
1507 1541 */
1508 1542 static void
1509 1543 igb_tx_clean(igb_t *igb)
1510 1544 {
1511 1545 igb_tx_ring_t *tx_ring;
1512 1546 tx_control_block_t *tcb;
1513 1547 link_list_t pending_list;
1514 1548 uint32_t desc_num;
1515 1549 int i, j;
1516 1550
1517 1551 LINK_LIST_INIT(&pending_list);
1518 1552
1519 1553 for (i = 0; i < igb->num_tx_rings; i++) {
1520 1554 tx_ring = &igb->tx_rings[i];
1521 1555
1522 1556 mutex_enter(&tx_ring->recycle_lock);
1523 1557
1524 1558 /*
1525 1559 * Clean the pending tx data - the pending packets in the
1526 1560 * work_list that have no chances to be transmitted again.
1527 1561 *
1528 1562 * We must ensure the chipset is stopped or the link is down
1529 1563 * before cleaning the transmit packets.
1530 1564 */
1531 1565 desc_num = 0;
1532 1566 for (j = 0; j < tx_ring->ring_size; j++) {
1533 1567 tcb = tx_ring->work_list[j];
1534 1568 if (tcb != NULL) {
1535 1569 desc_num += tcb->desc_num;
1536 1570
1537 1571 tx_ring->work_list[j] = NULL;
1538 1572
1539 1573 igb_free_tcb(tcb);
1540 1574
1541 1575 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1542 1576 }
1543 1577 }
1544 1578
1545 1579 if (desc_num > 0) {
1546 1580 atomic_add_32(&tx_ring->tbd_free, desc_num);
1547 1581 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1548 1582
1549 1583 /*
1550 1584 * Reset the head and tail pointers of the tbd ring;
1551 1585 * Reset the head write-back if it is enabled.
1552 1586 */
1553 1587 tx_ring->tbd_head = 0;
1554 1588 tx_ring->tbd_tail = 0;
1555 1589 if (igb->tx_head_wb_enable)
1556 1590 *tx_ring->tbd_head_wb = 0;
1557 1591
1558 1592 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0);
1559 1593 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0);
1560 1594 }
1561 1595
1562 1596 mutex_exit(&tx_ring->recycle_lock);
1563 1597
1564 1598 /*
1565 1599 * Add the tx control blocks in the pending list to
1566 1600 * the free list.
1567 1601 */
1568 1602 igb_put_free_list(tx_ring, &pending_list);
1569 1603 }
1570 1604 }
1571 1605
1572 1606 /*
1573 1607 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted
1574 1608 */
1575 1609 static boolean_t
1576 1610 igb_tx_drain(igb_t *igb)
1577 1611 {
1578 1612 igb_tx_ring_t *tx_ring;
1579 1613 boolean_t done;
1580 1614 int i, j;
1581 1615
1582 1616 /*
1583 1617 * Wait for a specific time to allow pending tx packets
1584 1618 * to be transmitted.
1585 1619 *
1586 1620 * Check the counter tbd_free to see if transmission is done.
1587 1621 * No lock protection is needed here.
1588 1622 *
1589 1623 * Return B_TRUE if all pending packets have been transmitted;
1590 1624 * Otherwise return B_FALSE;
1591 1625 */
1592 1626 for (i = 0; i < TX_DRAIN_TIME; i++) {
1593 1627
1594 1628 done = B_TRUE;
1595 1629 for (j = 0; j < igb->num_tx_rings; j++) {
1596 1630 tx_ring = &igb->tx_rings[j];
1597 1631 done = done &&
1598 1632 (tx_ring->tbd_free == tx_ring->ring_size);
1599 1633 }
1600 1634
1601 1635 if (done)
1602 1636 break;
1603 1637
1604 1638 msec_delay(1);
1605 1639 }
1606 1640
1607 1641 return (done);
1608 1642 }
1609 1643
1610 1644 /*
1611 1645 * igb_rx_drain - Wait for all rx buffers to be released by upper layer
1612 1646 */
1613 1647 static boolean_t
1614 1648 igb_rx_drain(igb_t *igb)
1615 1649 {
1616 1650 boolean_t done;
1617 1651 int i;
1618 1652
1619 1653 /*
1620 1654 * Polling the rx free list to check if those rx buffers held by
1621 1655 * the upper layer are released.
1622 1656 *
1623 1657 * Check the counter rcb_free to see if all pending buffers are
1624 1658 * released. No lock protection is needed here.
1625 1659 *
1626 1660 * Return B_TRUE if all pending buffers have been released;
1627 1661 * Otherwise return B_FALSE;
1628 1662 */
1629 1663 for (i = 0; i < RX_DRAIN_TIME; i++) {
1630 1664 done = (igb->rcb_pending == 0);
1631 1665
1632 1666 if (done)
1633 1667 break;
1634 1668
1635 1669 msec_delay(1);
1636 1670 }
1637 1671
1638 1672 return (done);
1639 1673 }
1640 1674
1641 1675 /*
1642 1676 * igb_start - Start the driver/chipset
1643 1677 */
1644 1678 int
1645 1679 igb_start(igb_t *igb, boolean_t alloc_buffer)
1646 1680 {
1647 1681 int i;
1648 1682
1649 1683 ASSERT(mutex_owned(&igb->gen_lock));
1650 1684
1651 1685 if (alloc_buffer) {
1652 1686 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) {
1653 1687 igb_error(igb,
1654 1688 "Failed to allocate software receive rings");
1655 1689 return (IGB_FAILURE);
1656 1690 }
1657 1691
1658 1692 /* Allocate buffers for all the rx/tx rings */
1659 1693 if (igb_alloc_dma(igb) != IGB_SUCCESS) {
1660 1694 igb_error(igb, "Failed to allocate DMA resource");
1661 1695 return (IGB_FAILURE);
1662 1696 }
1663 1697
1664 1698 igb->tx_ring_init = B_TRUE;
1665 1699 } else {
1666 1700 igb->tx_ring_init = B_FALSE;
1667 1701 }
1668 1702
1669 1703 for (i = 0; i < igb->num_rx_rings; i++)
1670 1704 mutex_enter(&igb->rx_rings[i].rx_lock);
1671 1705 for (i = 0; i < igb->num_tx_rings; i++)
1672 1706 mutex_enter(&igb->tx_rings[i].tx_lock);
1673 1707
1674 1708 /*
1675 1709 * Start the adapter
1676 1710 */
1677 1711 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) {
1678 1712 if (igb_init_adapter(igb) != IGB_SUCCESS) {
1679 1713 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE);
1680 1714 goto start_failure;
1681 1715 }
1682 1716 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER;
1683 1717 }
1684 1718
1685 1719 /*
1686 1720 * Setup the rx/tx rings
1687 1721 */
1688 1722 igb_setup_rings(igb);
1689 1723
1690 1724 /*
1691 1725 * Enable adapter interrupts
|
↓ open down ↓ |
843 lines elided |
↑ open up ↑ |
1692 1726 * The interrupts must be enabled after the driver state is START
1693 1727 */
1694 1728 igb->capab->enable_intr(igb);
1695 1729
1696 1730 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK)
1697 1731 goto start_failure;
1698 1732
1699 1733 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1700 1734 goto start_failure;
1701 1735
1736 + if (igb->hw.mac.type == e1000_i350)
1737 + (void) e1000_set_eee_i350(&igb->hw);
1738 +
1702 1739 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1703 1740 mutex_exit(&igb->tx_rings[i].tx_lock);
1704 1741 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1705 1742 mutex_exit(&igb->rx_rings[i].rx_lock);
1706 1743
1707 1744 return (IGB_SUCCESS);
1708 1745
1709 1746 start_failure:
1710 1747 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1711 1748 mutex_exit(&igb->tx_rings[i].tx_lock);
1712 1749 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1713 1750 mutex_exit(&igb->rx_rings[i].rx_lock);
1714 1751
1715 1752 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1716 1753
1717 1754 return (IGB_FAILURE);
1718 1755 }
1719 1756
1720 1757 /*
1721 1758 * igb_stop - Stop the driver/chipset
1722 1759 */
1723 1760 void
1724 1761 igb_stop(igb_t *igb, boolean_t free_buffer)
1725 1762 {
1726 1763 int i;
1727 1764
1728 1765 ASSERT(mutex_owned(&igb->gen_lock));
1729 1766
1730 1767 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER;
1731 1768
1732 1769 /*
1733 1770 * Disable the adapter interrupts
1734 1771 */
1735 1772 igb_disable_adapter_interrupts(igb);
1736 1773
1737 1774 /*
1738 1775 * Drain the pending tx packets
1739 1776 */
1740 1777 (void) igb_tx_drain(igb);
1741 1778
1742 1779 for (i = 0; i < igb->num_rx_rings; i++)
1743 1780 mutex_enter(&igb->rx_rings[i].rx_lock);
1744 1781 for (i = 0; i < igb->num_tx_rings; i++)
1745 1782 mutex_enter(&igb->tx_rings[i].tx_lock);
1746 1783
1747 1784 /*
1748 1785 * Stop the adapter
1749 1786 */
1750 1787 igb_stop_adapter(igb);
1751 1788
1752 1789 /*
1753 1790 * Clean the pending tx data/resources
1754 1791 */
1755 1792 igb_tx_clean(igb);
1756 1793
1757 1794 for (i = igb->num_tx_rings - 1; i >= 0; i--)
1758 1795 mutex_exit(&igb->tx_rings[i].tx_lock);
1759 1796 for (i = igb->num_rx_rings - 1; i >= 0; i--)
1760 1797 mutex_exit(&igb->rx_rings[i].rx_lock);
1761 1798
1762 1799 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK)
1763 1800 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
1764 1801
1765 1802 if (igb->link_state == LINK_STATE_UP) {
1766 1803 igb->link_state = LINK_STATE_UNKNOWN;
1767 1804 mac_link_update(igb->mac_hdl, igb->link_state);
1768 1805 }
1769 1806
1770 1807 if (free_buffer) {
1771 1808 /*
1772 1809 * Release the DMA/memory resources of rx/tx rings
1773 1810 */
1774 1811 igb_free_dma(igb);
1775 1812 igb_free_rx_data(igb);
1776 1813 }
1777 1814 }
1778 1815
1779 1816 /*
1780 1817 * igb_alloc_rings - Allocate memory space for rx/tx rings
1781 1818 */
1782 1819 static int
1783 1820 igb_alloc_rings(igb_t *igb)
1784 1821 {
1785 1822 /*
1786 1823 * Allocate memory space for rx rings
1787 1824 */
1788 1825 igb->rx_rings = kmem_zalloc(
1789 1826 sizeof (igb_rx_ring_t) * igb->num_rx_rings,
1790 1827 KM_NOSLEEP);
1791 1828
1792 1829 if (igb->rx_rings == NULL) {
1793 1830 return (IGB_FAILURE);
1794 1831 }
1795 1832
1796 1833 /*
1797 1834 * Allocate memory space for tx rings
1798 1835 */
1799 1836 igb->tx_rings = kmem_zalloc(
1800 1837 sizeof (igb_tx_ring_t) * igb->num_tx_rings,
1801 1838 KM_NOSLEEP);
1802 1839
1803 1840 if (igb->tx_rings == NULL) {
1804 1841 kmem_free(igb->rx_rings,
1805 1842 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1806 1843 igb->rx_rings = NULL;
1807 1844 return (IGB_FAILURE);
1808 1845 }
1809 1846
1810 1847 /*
1811 1848 * Allocate memory space for rx ring groups
1812 1849 */
1813 1850 igb->rx_groups = kmem_zalloc(
1814 1851 sizeof (igb_rx_group_t) * igb->num_rx_groups,
1815 1852 KM_NOSLEEP);
1816 1853
1817 1854 if (igb->rx_groups == NULL) {
1818 1855 kmem_free(igb->rx_rings,
1819 1856 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1820 1857 kmem_free(igb->tx_rings,
1821 1858 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1822 1859 igb->rx_rings = NULL;
1823 1860 igb->tx_rings = NULL;
1824 1861 return (IGB_FAILURE);
1825 1862 }
1826 1863
1827 1864 return (IGB_SUCCESS);
1828 1865 }
1829 1866
1830 1867 /*
1831 1868 * igb_free_rings - Free the memory space of rx/tx rings.
1832 1869 */
1833 1870 static void
1834 1871 igb_free_rings(igb_t *igb)
1835 1872 {
1836 1873 if (igb->rx_rings != NULL) {
1837 1874 kmem_free(igb->rx_rings,
1838 1875 sizeof (igb_rx_ring_t) * igb->num_rx_rings);
1839 1876 igb->rx_rings = NULL;
1840 1877 }
1841 1878
1842 1879 if (igb->tx_rings != NULL) {
1843 1880 kmem_free(igb->tx_rings,
1844 1881 sizeof (igb_tx_ring_t) * igb->num_tx_rings);
1845 1882 igb->tx_rings = NULL;
1846 1883 }
1847 1884
1848 1885 if (igb->rx_groups != NULL) {
1849 1886 kmem_free(igb->rx_groups,
1850 1887 sizeof (igb_rx_group_t) * igb->num_rx_groups);
1851 1888 igb->rx_groups = NULL;
1852 1889 }
1853 1890 }
1854 1891
1855 1892 static int
1856 1893 igb_alloc_rx_data(igb_t *igb)
1857 1894 {
1858 1895 igb_rx_ring_t *rx_ring;
1859 1896 int i;
1860 1897
1861 1898 for (i = 0; i < igb->num_rx_rings; i++) {
1862 1899 rx_ring = &igb->rx_rings[i];
1863 1900 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS)
1864 1901 goto alloc_rx_rings_failure;
1865 1902 }
1866 1903 return (IGB_SUCCESS);
1867 1904
1868 1905 alloc_rx_rings_failure:
1869 1906 igb_free_rx_data(igb);
1870 1907 return (IGB_FAILURE);
1871 1908 }
1872 1909
1873 1910 static void
1874 1911 igb_free_rx_data(igb_t *igb)
1875 1912 {
1876 1913 igb_rx_ring_t *rx_ring;
1877 1914 igb_rx_data_t *rx_data;
1878 1915 int i;
1879 1916
1880 1917 for (i = 0; i < igb->num_rx_rings; i++) {
1881 1918 rx_ring = &igb->rx_rings[i];
1882 1919
1883 1920 mutex_enter(&igb->rx_pending_lock);
1884 1921 rx_data = rx_ring->rx_data;
1885 1922
1886 1923 if (rx_data != NULL) {
1887 1924 rx_data->flag |= IGB_RX_STOPPED;
1888 1925
1889 1926 if (rx_data->rcb_pending == 0) {
1890 1927 igb_free_rx_ring_data(rx_data);
1891 1928 rx_ring->rx_data = NULL;
1892 1929 }
1893 1930 }
1894 1931
1895 1932 mutex_exit(&igb->rx_pending_lock);
1896 1933 }
1897 1934 }
1898 1935
1899 1936 /*
1900 1937 * igb_setup_rings - Setup rx/tx rings
1901 1938 */
1902 1939 static void
1903 1940 igb_setup_rings(igb_t *igb)
1904 1941 {
1905 1942 /*
1906 1943 * Setup the rx/tx rings, including the following:
1907 1944 *
1908 1945 * 1. Setup the descriptor ring and the control block buffers;
1909 1946 * 2. Initialize necessary registers for receive/transmit;
1910 1947 * 3. Initialize software pointers/parameters for receive/transmit;
1911 1948 */
1912 1949 igb_setup_rx(igb);
1913 1950
1914 1951 igb_setup_tx(igb);
1915 1952 }
1916 1953
1917 1954 static void
1918 1955 igb_setup_rx_ring(igb_rx_ring_t *rx_ring)
1919 1956 {
1920 1957 igb_t *igb = rx_ring->igb;
1921 1958 igb_rx_data_t *rx_data = rx_ring->rx_data;
1922 1959 struct e1000_hw *hw = &igb->hw;
1923 1960 rx_control_block_t *rcb;
1924 1961 union e1000_adv_rx_desc *rbd;
1925 1962 uint32_t size;
1926 1963 uint32_t buf_low;
1927 1964 uint32_t buf_high;
1928 1965 uint32_t rxdctl;
1929 1966 int i;
1930 1967
1931 1968 ASSERT(mutex_owned(&rx_ring->rx_lock));
1932 1969 ASSERT(mutex_owned(&igb->gen_lock));
1933 1970
1934 1971 /*
1935 1972 * Initialize descriptor ring with buffer addresses
1936 1973 */
1937 1974 for (i = 0; i < igb->rx_ring_size; i++) {
1938 1975 rcb = rx_data->work_list[i];
1939 1976 rbd = &rx_data->rbd_ring[i];
1940 1977
1941 1978 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
1942 1979 rbd->read.hdr_addr = NULL;
1943 1980 }
1944 1981
1945 1982 /*
1946 1983 * Initialize the base address registers
1947 1984 */
1948 1985 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
1949 1986 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
1950 1987 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high);
1951 1988 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low);
1952 1989
1953 1990 /*
1954 1991 * Initialize the length register
1955 1992 */
1956 1993 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc);
1957 1994 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size);
1958 1995
1959 1996 /*
1960 1997 * Initialize buffer size & descriptor type
1961 1998 */
1962 1999 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index),
1963 2000 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) |
1964 2001 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF));
1965 2002
1966 2003 /*
1967 2004 * Setup the Receive Descriptor Control Register (RXDCTL)
1968 2005 */
1969 2006 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index));
1970 2007 rxdctl &= igb->capab->rxdctl_mask;
1971 2008 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1972 2009 rxdctl |= 16; /* pthresh */
1973 2010 rxdctl |= 8 << 8; /* hthresh */
1974 2011 rxdctl |= 1 << 16; /* wthresh */
1975 2012 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl);
1976 2013
1977 2014 rx_data->rbd_next = 0;
1978 2015 }
1979 2016
1980 2017 static void
1981 2018 igb_setup_rx(igb_t *igb)
1982 2019 {
1983 2020 igb_rx_ring_t *rx_ring;
1984 2021 igb_rx_data_t *rx_data;
1985 2022 igb_rx_group_t *rx_group;
1986 2023 struct e1000_hw *hw = &igb->hw;
1987 2024 uint32_t rctl, rxcsum;
1988 2025 uint32_t ring_per_group;
1989 2026 int i;
1990 2027
1991 2028 /*
1992 2029 * Setup the Receive Control Register (RCTL), and enable the
1993 2030 * receiver. The initial configuration is to: enable the receiver,
1994 2031 * accept broadcasts, discard bad packets, accept long packets,
1995 2032 * disable VLAN filter checking, and set receive buffer size to
1996 2033 * 2k. For 82575, also set the receive descriptor minimum
1997 2034 * threshold size to 1/2 the ring.
1998 2035 */
1999 2036 rctl = E1000_READ_REG(hw, E1000_RCTL);
2000 2037
2001 2038 /*
2002 2039 * Clear the field used for wakeup control. This driver doesn't do
2003 2040 * wakeup but leave this here for completeness.
2004 2041 */
2005 2042 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2006 2043 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2007 2044
2008 2045 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */
2009 2046 E1000_RCTL_BAM | /* Accept Broadcast Packets */
2010 2047 E1000_RCTL_LPE | /* Large Packet Enable */
2011 2048 /* Multicast filter offset */
2012 2049 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) |
2013 2050 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */
2014 2051 E1000_RCTL_SECRC); /* Strip Ethernet CRC */
2015 2052
2016 2053 for (i = 0; i < igb->num_rx_groups; i++) {
2017 2054 rx_group = &igb->rx_groups[i];
2018 2055 rx_group->index = i;
2019 2056 rx_group->igb = igb;
2020 2057 }
2021 2058
2022 2059 /*
2023 2060 * Set up all rx descriptor rings - must be called before receive unit
2024 2061 * enabled.
2025 2062 */
2026 2063 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2027 2064 for (i = 0; i < igb->num_rx_rings; i++) {
2028 2065 rx_ring = &igb->rx_rings[i];
2029 2066 igb_setup_rx_ring(rx_ring);
2030 2067
2031 2068 /*
2032 2069 * Map a ring to a group by assigning a group index
2033 2070 */
2034 2071 rx_ring->group_index = i / ring_per_group;
2035 2072 }
2036 2073
2037 2074 /*
2038 2075 * Setup the Rx Long Packet Max Length register
2039 2076 */
2040 2077 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size);
2041 2078
2042 2079 /*
2043 2080 * Hardware checksum settings
2044 2081 */
2045 2082 if (igb->rx_hcksum_enable) {
2046 2083 rxcsum =
2047 2084 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */
2048 2085 E1000_RXCSUM_IPOFL; /* IP checksum */
2049 2086
2050 2087 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2051 2088 }
2052 2089
2053 2090 /*
2054 2091 * Setup classify and RSS for multiple receive queues
2055 2092 */
2056 2093 switch (igb->vmdq_mode) {
2057 2094 case E1000_VMDQ_OFF:
2058 2095 /*
2059 2096 * One ring group, only RSS is needed when more than
2060 2097 * one ring enabled.
2061 2098 */
2062 2099 if (igb->num_rx_rings > 1)
2063 2100 igb_setup_rss(igb);
2064 2101 break;
2065 2102 case E1000_VMDQ_MAC:
2066 2103 /*
2067 2104 * Multiple groups, each group has one ring,
2068 2105 * only the MAC classification is needed.
2069 2106 */
2070 2107 igb_setup_mac_classify(igb);
2071 2108 break;
2072 2109 case E1000_VMDQ_MAC_RSS:
2073 2110 /*
2074 2111 * Multiple groups and multiple rings, both
2075 2112 * MAC classification and RSS are needed.
2076 2113 */
2077 2114 igb_setup_mac_rss_classify(igb);
2078 2115 break;
2079 2116 }
2080 2117
2081 2118 /*
2082 2119 * Enable the receive unit - must be done after all
2083 2120 * the rx setup above.
2084 2121 */
2085 2122 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2086 2123
2087 2124 /*
2088 2125 * Initialize all adapter ring head & tail pointers - must
2089 2126 * be done after receive unit is enabled
2090 2127 */
2091 2128 for (i = 0; i < igb->num_rx_rings; i++) {
2092 2129 rx_ring = &igb->rx_rings[i];
2093 2130 rx_data = rx_ring->rx_data;
2094 2131 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2095 2132 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1);
2096 2133 }
2097 2134
2098 2135 /*
2099 2136 * 82575 with manageability enabled needs a special flush to make
2100 2137 * sure the fifos start clean.
2101 2138 */
2102 2139 if ((hw->mac.type == e1000_82575) &&
2103 2140 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) {
2104 2141 e1000_rx_fifo_flush_82575(hw);
2105 2142 }
2106 2143 }
2107 2144
2108 2145 static void
2109 2146 igb_setup_tx_ring(igb_tx_ring_t *tx_ring)
2110 2147 {
2111 2148 igb_t *igb = tx_ring->igb;
2112 2149 struct e1000_hw *hw = &igb->hw;
2113 2150 uint32_t size;
2114 2151 uint32_t buf_low;
2115 2152 uint32_t buf_high;
2116 2153 uint32_t reg_val;
2117 2154
2118 2155 ASSERT(mutex_owned(&tx_ring->tx_lock));
2119 2156 ASSERT(mutex_owned(&igb->gen_lock));
2120 2157
2121 2158
2122 2159 /*
2123 2160 * Initialize the length register
2124 2161 */
2125 2162 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc);
2126 2163 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size);
2127 2164
2128 2165 /*
2129 2166 * Initialize the base address registers
2130 2167 */
2131 2168 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2132 2169 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2133 2170 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low);
2134 2171 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high);
2135 2172
2136 2173 /*
2137 2174 * Setup head & tail pointers
2138 2175 */
2139 2176 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0);
2140 2177 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0);
2141 2178
2142 2179 /*
2143 2180 * Setup head write-back
2144 2181 */
2145 2182 if (igb->tx_head_wb_enable) {
2146 2183 /*
2147 2184 * The memory of the head write-back is allocated using
2148 2185 * the extra tbd beyond the tail of the tbd ring.
2149 2186 */
2150 2187 tx_ring->tbd_head_wb = (uint32_t *)
2151 2188 ((uintptr_t)tx_ring->tbd_area.address + size);
2152 2189 *tx_ring->tbd_head_wb = 0;
2153 2190
2154 2191 buf_low = (uint32_t)
2155 2192 (tx_ring->tbd_area.dma_address + size);
2156 2193 buf_high = (uint32_t)
2157 2194 ((tx_ring->tbd_area.dma_address + size) >> 32);
2158 2195
2159 2196 /* Set the head write-back enable bit */
2160 2197 buf_low |= E1000_TX_HEAD_WB_ENABLE;
2161 2198
2162 2199 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low);
2163 2200 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high);
2164 2201
2165 2202 /*
2166 2203 * Turn off relaxed ordering for head write back or it will
2167 2204 * cause problems with the tx recycling
2168 2205 */
2169 2206 reg_val = E1000_READ_REG(hw,
2170 2207 E1000_DCA_TXCTRL(tx_ring->index));
2171 2208 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
2172 2209 E1000_WRITE_REG(hw,
2173 2210 E1000_DCA_TXCTRL(tx_ring->index), reg_val);
2174 2211 } else {
2175 2212 tx_ring->tbd_head_wb = NULL;
2176 2213 }
2177 2214
2178 2215 tx_ring->tbd_head = 0;
2179 2216 tx_ring->tbd_tail = 0;
2180 2217 tx_ring->tbd_free = tx_ring->ring_size;
2181 2218
2182 2219 if (igb->tx_ring_init == B_TRUE) {
2183 2220 tx_ring->tcb_head = 0;
2184 2221 tx_ring->tcb_tail = 0;
2185 2222 tx_ring->tcb_free = tx_ring->free_list_size;
2186 2223 }
2187 2224
2188 2225 /*
2189 2226 * Enable TXDCTL per queue
2190 2227 */
2191 2228 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index));
2192 2229 reg_val |= E1000_TXDCTL_QUEUE_ENABLE;
2193 2230 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val);
2194 2231
2195 2232 /*
2196 2233 * Initialize hardware checksum offload settings
2197 2234 */
2198 2235 bzero(&tx_ring->tx_context, sizeof (tx_context_t));
2199 2236 }
2200 2237
2201 2238 static void
2202 2239 igb_setup_tx(igb_t *igb)
2203 2240 {
2204 2241 igb_tx_ring_t *tx_ring;
2205 2242 struct e1000_hw *hw = &igb->hw;
2206 2243 uint32_t reg_val;
2207 2244 int i;
2208 2245
2209 2246 for (i = 0; i < igb->num_tx_rings; i++) {
2210 2247 tx_ring = &igb->tx_rings[i];
2211 2248 igb_setup_tx_ring(tx_ring);
2212 2249 }
2213 2250
2214 2251 /*
2215 2252 * Setup the Transmit Control Register (TCTL)
2216 2253 */
2217 2254 reg_val = E1000_READ_REG(hw, E1000_TCTL);
2218 2255 reg_val &= ~E1000_TCTL_CT;
2219 2256 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2220 2257 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2221 2258
2222 2259 /* Enable transmits */
2223 2260 reg_val |= E1000_TCTL_EN;
2224 2261
2225 2262 E1000_WRITE_REG(hw, E1000_TCTL, reg_val);
2226 2263 }
2227 2264
2228 2265 /*
2229 2266 * igb_setup_rss - Setup receive-side scaling feature
2230 2267 */
2231 2268 static void
2232 2269 igb_setup_rss(igb_t *igb)
2233 2270 {
2234 2271 struct e1000_hw *hw = &igb->hw;
2235 2272 uint32_t i, mrqc, rxcsum;
2236 2273 int shift = 0;
2237 2274 uint32_t random;
2238 2275 union e1000_reta {
2239 2276 uint32_t dword;
2240 2277 uint8_t bytes[4];
2241 2278 } reta;
2242 2279
2243 2280 /* Setup the Redirection Table */
2244 2281 if (hw->mac.type == e1000_82576) {
2245 2282 shift = 3;
2246 2283 } else if (hw->mac.type == e1000_82575) {
2247 2284 shift = 6;
2248 2285 }
2249 2286 for (i = 0; i < (32 * 4); i++) {
2250 2287 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift;
2251 2288 if ((i & 3) == 3) {
2252 2289 E1000_WRITE_REG(hw,
2253 2290 (E1000_RETA(0) + (i & ~3)), reta.dword);
2254 2291 }
2255 2292 }
2256 2293
2257 2294 /* Fill out hash function seeds */
2258 2295 for (i = 0; i < 10; i++) {
2259 2296 (void) random_get_pseudo_bytes((uint8_t *)&random,
2260 2297 sizeof (uint32_t));
2261 2298 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2262 2299 }
2263 2300
2264 2301 /* Setup the Multiple Receive Queue Control register */
2265 2302 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2266 2303 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2267 2304 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2268 2305 E1000_MRQC_RSS_FIELD_IPV6 |
2269 2306 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2270 2307 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2271 2308 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2272 2309 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2273 2310 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2274 2311
2275 2312 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2276 2313
2277 2314 /*
2278 2315 * Disable Packet Checksum to enable RSS for multiple receive queues.
2279 2316 *
2280 2317 * The Packet Checksum is not ethernet CRC. It is another kind of
2281 2318 * checksum offloading provided by the 82575 chipset besides the IP
2282 2319 * header checksum offloading and the TCP/UDP checksum offloading.
2283 2320 * The Packet Checksum is by default computed over the entire packet
2284 2321 * from the first byte of the DA through the last byte of the CRC,
2285 2322 * including the Ethernet and IP headers.
2286 2323 *
2287 2324 * It is a hardware limitation that Packet Checksum is mutually
2288 2325 * exclusive with RSS.
2289 2326 */
2290 2327 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2291 2328 rxcsum |= E1000_RXCSUM_PCSD;
2292 2329 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2293 2330 }
2294 2331
2295 2332 /*
2296 2333 * igb_setup_mac_rss_classify - Setup MAC classification and rss
2297 2334 */
2298 2335 static void
2299 2336 igb_setup_mac_rss_classify(igb_t *igb)
2300 2337 {
2301 2338 struct e1000_hw *hw = &igb->hw;
2302 2339 uint32_t i, mrqc, vmdctl, rxcsum;
2303 2340 uint32_t ring_per_group;
2304 2341 int shift_group0, shift_group1;
2305 2342 uint32_t random;
2306 2343 union e1000_reta {
2307 2344 uint32_t dword;
2308 2345 uint8_t bytes[4];
2309 2346 } reta;
2310 2347
2311 2348 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2312 2349
2313 2350 /* Setup the Redirection Table, it is shared between two groups */
2314 2351 shift_group0 = 2;
2315 2352 shift_group1 = 6;
2316 2353 for (i = 0; i < (32 * 4); i++) {
2317 2354 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) |
2318 2355 ((ring_per_group + (i % ring_per_group)) << shift_group1);
2319 2356 if ((i & 3) == 3) {
2320 2357 E1000_WRITE_REG(hw,
2321 2358 (E1000_RETA(0) + (i & ~3)), reta.dword);
2322 2359 }
2323 2360 }
2324 2361
2325 2362 /* Fill out hash function seeds */
2326 2363 for (i = 0; i < 10; i++) {
2327 2364 (void) random_get_pseudo_bytes((uint8_t *)&random,
2328 2365 sizeof (uint32_t));
2329 2366 E1000_WRITE_REG(hw, E1000_RSSRK(i), random);
2330 2367 }
2331 2368
2332 2369 /*
2333 2370 * Setup the Multiple Receive Queue Control register,
2334 2371 * enable VMDq based on packet destination MAC address and RSS.
2335 2372 */
2336 2373 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP;
2337 2374 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2338 2375 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2339 2376 E1000_MRQC_RSS_FIELD_IPV6 |
2340 2377 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2341 2378 E1000_MRQC_RSS_FIELD_IPV4_UDP |
2342 2379 E1000_MRQC_RSS_FIELD_IPV6_UDP |
2343 2380 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2344 2381 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2345 2382
2346 2383 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2347 2384
2348 2385
2349 2386 /* Define the default group and default queues */
2350 2387 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE;
2351 2388 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl);
2352 2389
2353 2390 /*
2354 2391 * Disable Packet Checksum to enable RSS for multiple receive queues.
2355 2392 *
2356 2393 * The Packet Checksum is not ethernet CRC. It is another kind of
2357 2394 * checksum offloading provided by the 82575 chipset besides the IP
2358 2395 * header checksum offloading and the TCP/UDP checksum offloading.
2359 2396 * The Packet Checksum is by default computed over the entire packet
2360 2397 * from the first byte of the DA through the last byte of the CRC,
2361 2398 * including the Ethernet and IP headers.
2362 2399 *
2363 2400 * It is a hardware limitation that Packet Checksum is mutually
2364 2401 * exclusive with RSS.
2365 2402 */
2366 2403 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2367 2404 rxcsum |= E1000_RXCSUM_PCSD;
2368 2405 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2369 2406 }
2370 2407
2371 2408 /*
2372 2409 * igb_setup_mac_classify - Setup MAC classification feature
2373 2410 */
2374 2411 static void
2375 2412 igb_setup_mac_classify(igb_t *igb)
2376 2413 {
2377 2414 struct e1000_hw *hw = &igb->hw;
2378 2415 uint32_t mrqc, rxcsum;
2379 2416
2380 2417 /*
2381 2418 * Setup the Multiple Receive Queue Control register,
2382 2419 * enable VMDq based on packet destination MAC address.
2383 2420 */
2384 2421 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP;
2385 2422 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2386 2423
2387 2424 /*
2388 2425 * Disable Packet Checksum to enable RSS for multiple receive queues.
2389 2426 *
2390 2427 * The Packet Checksum is not ethernet CRC. It is another kind of
2391 2428 * checksum offloading provided by the 82575 chipset besides the IP
2392 2429 * header checksum offloading and the TCP/UDP checksum offloading.
2393 2430 * The Packet Checksum is by default computed over the entire packet
2394 2431 * from the first byte of the DA through the last byte of the CRC,
2395 2432 * including the Ethernet and IP headers.
2396 2433 *
2397 2434 * It is a hardware limitation that Packet Checksum is mutually
2398 2435 * exclusive with RSS.
2399 2436 */
2400 2437 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2401 2438 rxcsum |= E1000_RXCSUM_PCSD;
2402 2439 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2403 2440
2404 2441 }
2405 2442
2406 2443 /*
2407 2444 * igb_init_unicst - Initialize the unicast addresses
2408 2445 */
2409 2446 static void
2410 2447 igb_init_unicst(igb_t *igb)
2411 2448 {
2412 2449 struct e1000_hw *hw = &igb->hw;
2413 2450 int slot;
2414 2451
2415 2452 /*
2416 2453 * Here we should consider two situations:
2417 2454 *
2418 2455 * 1. Chipset is initialized the first time
2419 2456 * Initialize the multiple unicast addresses, and
2420 2457 * save the default MAC address.
2421 2458 *
2422 2459 * 2. Chipset is reset
2423 2460 * Recover the multiple unicast addresses from the
2424 2461 * software data structure to the RAR registers.
2425 2462 */
2426 2463
2427 2464 /*
2428 2465 * Clear the default MAC address in the RAR0 rgister,
2429 2466 * which is loaded from EEPROM when system boot or chipreset,
2430 2467 * this will cause the conficts with add_mac/rem_mac entry
2431 2468 * points when VMDq is enabled. For this reason, the RAR0
2432 2469 * must be cleared for both cases mentioned above.
2433 2470 */
2434 2471 e1000_rar_clear(hw, 0);
2435 2472
2436 2473 if (!igb->unicst_init) {
2437 2474
2438 2475 /* Initialize the multiple unicast addresses */
2439 2476 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES;
2440 2477 igb->unicst_avail = igb->unicst_total;
2441 2478
2442 2479 for (slot = 0; slot < igb->unicst_total; slot++)
2443 2480 igb->unicst_addr[slot].mac.set = 0;
2444 2481
2445 2482 igb->unicst_init = B_TRUE;
2446 2483 } else {
2447 2484 /* Re-configure the RAR registers */
2448 2485 for (slot = 0; slot < igb->unicst_total; slot++) {
2449 2486 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr,
2450 2487 slot, igb->vmdq_mode,
2451 2488 igb->unicst_addr[slot].mac.group_index);
2452 2489 }
2453 2490 }
2454 2491 }
2455 2492
2456 2493 /*
2457 2494 * igb_unicst_find - Find the slot for the specified unicast address
2458 2495 */
2459 2496 int
2460 2497 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr)
2461 2498 {
2462 2499 int slot;
2463 2500
2464 2501 ASSERT(mutex_owned(&igb->gen_lock));
2465 2502
2466 2503 for (slot = 0; slot < igb->unicst_total; slot++) {
2467 2504 if (bcmp(igb->unicst_addr[slot].mac.addr,
2468 2505 mac_addr, ETHERADDRL) == 0)
2469 2506 return (slot);
2470 2507 }
2471 2508
2472 2509 return (-1);
2473 2510 }
2474 2511
2475 2512 /*
2476 2513 * igb_unicst_set - Set the unicast address to the specified slot
2477 2514 */
2478 2515 int
2479 2516 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr,
2480 2517 int slot)
2481 2518 {
2482 2519 struct e1000_hw *hw = &igb->hw;
2483 2520
2484 2521 ASSERT(mutex_owned(&igb->gen_lock));
2485 2522
2486 2523 /*
2487 2524 * Save the unicast address in the software data structure
2488 2525 */
2489 2526 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL);
2490 2527
2491 2528 /*
2492 2529 * Set the unicast address to the RAR register
2493 2530 */
2494 2531 e1000_rar_set(hw, (uint8_t *)mac_addr, slot);
2495 2532
2496 2533 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2497 2534 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2498 2535 return (EIO);
2499 2536 }
2500 2537
2501 2538 return (0);
2502 2539 }
2503 2540
2504 2541 /*
2505 2542 * igb_multicst_add - Add a multicst address
2506 2543 */
2507 2544 int
2508 2545 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr)
2509 2546 {
2510 2547 struct ether_addr *new_table;
2511 2548 size_t new_len;
2512 2549 size_t old_len;
2513 2550
2514 2551 ASSERT(mutex_owned(&igb->gen_lock));
2515 2552
2516 2553 if ((multiaddr[0] & 01) == 0) {
2517 2554 igb_error(igb, "Illegal multicast address");
2518 2555 return (EINVAL);
2519 2556 }
2520 2557
2521 2558 if (igb->mcast_count >= igb->mcast_max_num) {
2522 2559 igb_error(igb, "Adapter requested more than %d mcast addresses",
2523 2560 igb->mcast_max_num);
2524 2561 return (ENOENT);
2525 2562 }
2526 2563
2527 2564 if (igb->mcast_count == igb->mcast_alloc_count) {
2528 2565 old_len = igb->mcast_alloc_count *
2529 2566 sizeof (struct ether_addr);
2530 2567 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) *
2531 2568 sizeof (struct ether_addr);
2532 2569
2533 2570 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2534 2571 if (new_table == NULL) {
2535 2572 igb_error(igb,
2536 2573 "Not enough memory to alloc mcast table");
2537 2574 return (ENOMEM);
2538 2575 }
2539 2576
2540 2577 if (igb->mcast_table != NULL) {
2541 2578 bcopy(igb->mcast_table, new_table, old_len);
2542 2579 kmem_free(igb->mcast_table, old_len);
2543 2580 }
2544 2581 igb->mcast_alloc_count += MCAST_ALLOC_COUNT;
2545 2582 igb->mcast_table = new_table;
2546 2583 }
2547 2584
2548 2585 bcopy(multiaddr,
2549 2586 &igb->mcast_table[igb->mcast_count], ETHERADDRL);
2550 2587 igb->mcast_count++;
2551 2588
2552 2589 /*
2553 2590 * Update the multicast table in the hardware
2554 2591 */
2555 2592 igb_setup_multicst(igb);
2556 2593
2557 2594 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2558 2595 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2559 2596 return (EIO);
2560 2597 }
2561 2598
2562 2599 return (0);
2563 2600 }
2564 2601
2565 2602 /*
2566 2603 * igb_multicst_remove - Remove a multicst address
2567 2604 */
2568 2605 int
2569 2606 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr)
2570 2607 {
2571 2608 struct ether_addr *new_table;
2572 2609 size_t new_len;
2573 2610 size_t old_len;
2574 2611 int i;
2575 2612
2576 2613 ASSERT(mutex_owned(&igb->gen_lock));
2577 2614
2578 2615 for (i = 0; i < igb->mcast_count; i++) {
2579 2616 if (bcmp(multiaddr, &igb->mcast_table[i],
2580 2617 ETHERADDRL) == 0) {
2581 2618 for (i++; i < igb->mcast_count; i++) {
2582 2619 igb->mcast_table[i - 1] =
2583 2620 igb->mcast_table[i];
2584 2621 }
2585 2622 igb->mcast_count--;
2586 2623 break;
2587 2624 }
2588 2625 }
2589 2626
2590 2627 if ((igb->mcast_alloc_count - igb->mcast_count) >
2591 2628 MCAST_ALLOC_COUNT) {
2592 2629 old_len = igb->mcast_alloc_count *
2593 2630 sizeof (struct ether_addr);
2594 2631 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) *
2595 2632 sizeof (struct ether_addr);
2596 2633
2597 2634 new_table = kmem_alloc(new_len, KM_NOSLEEP);
2598 2635 if (new_table != NULL) {
2599 2636 bcopy(igb->mcast_table, new_table, new_len);
2600 2637 kmem_free(igb->mcast_table, old_len);
2601 2638 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT;
2602 2639 igb->mcast_table = new_table;
2603 2640 }
2604 2641 }
2605 2642
2606 2643 /*
2607 2644 * Update the multicast table in the hardware
2608 2645 */
2609 2646 igb_setup_multicst(igb);
2610 2647
2611 2648 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
2612 2649 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
2613 2650 return (EIO);
2614 2651 }
2615 2652
2616 2653 return (0);
2617 2654 }
2618 2655
2619 2656 static void
2620 2657 igb_release_multicast(igb_t *igb)
2621 2658 {
2622 2659 if (igb->mcast_table != NULL) {
2623 2660 kmem_free(igb->mcast_table,
2624 2661 igb->mcast_alloc_count * sizeof (struct ether_addr));
2625 2662 igb->mcast_table = NULL;
2626 2663 }
2627 2664 }
2628 2665
2629 2666 /*
2630 2667 * igb_setup_multicast - setup multicast data structures
2631 2668 *
2632 2669 * This routine initializes all of the multicast related structures
2633 2670 * and save them in the hardware registers.
2634 2671 */
2635 2672 static void
2636 2673 igb_setup_multicst(igb_t *igb)
2637 2674 {
2638 2675 uint8_t *mc_addr_list;
2639 2676 uint32_t mc_addr_count;
2640 2677 struct e1000_hw *hw = &igb->hw;
2641 2678
2642 2679 ASSERT(mutex_owned(&igb->gen_lock));
2643 2680 ASSERT(igb->mcast_count <= igb->mcast_max_num);
2644 2681
2645 2682 mc_addr_list = (uint8_t *)igb->mcast_table;
2646 2683 mc_addr_count = igb->mcast_count;
2647 2684
2648 2685 /*
2649 2686 * Update the multicase addresses to the MTA registers
2650 2687 */
2651 2688 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count);
2652 2689 }
2653 2690
2654 2691 /*
2655 2692 * igb_get_conf - Get driver configurations set in driver.conf
2656 2693 *
2657 2694 * This routine gets user-configured values out of the configuration
2658 2695 * file igb.conf.
2659 2696 *
2660 2697 * For each configurable value, there is a minimum, a maximum, and a
2661 2698 * default.
2662 2699 * If user does not configure a value, use the default.
2663 2700 * If user configures below the minimum, use the minumum.
2664 2701 * If user configures above the maximum, use the maxumum.
2665 2702 */
2666 2703 static void
2667 2704 igb_get_conf(igb_t *igb)
2668 2705 {
2669 2706 struct e1000_hw *hw = &igb->hw;
2670 2707 uint32_t default_mtu;
2671 2708 uint32_t flow_control;
2672 2709 uint32_t ring_per_group;
2673 2710 int i;
2674 2711
2675 2712 /*
2676 2713 * igb driver supports the following user configurations:
2677 2714 *
2678 2715 * Link configurations:
2679 2716 * adv_autoneg_cap
2680 2717 * adv_1000fdx_cap
2681 2718 * adv_100fdx_cap
2682 2719 * adv_100hdx_cap
2683 2720 * adv_10fdx_cap
2684 2721 * adv_10hdx_cap
2685 2722 * Note: 1000hdx is not supported.
2686 2723 *
2687 2724 * Jumbo frame configuration:
2688 2725 * default_mtu
2689 2726 *
2690 2727 * Ethernet flow control configuration:
2691 2728 * flow_control
2692 2729 *
2693 2730 * Multiple rings configurations:
2694 2731 * tx_queue_number
2695 2732 * tx_ring_size
2696 2733 * rx_queue_number
2697 2734 * rx_ring_size
2698 2735 *
2699 2736 * Call igb_get_prop() to get the value for a specific
2700 2737 * configuration parameter.
2701 2738 */
2702 2739
2703 2740 /*
2704 2741 * Link configurations
2705 2742 */
2706 2743 igb->param_adv_autoneg_cap = igb_get_prop(igb,
2707 2744 PROP_ADV_AUTONEG_CAP, 0, 1, 1);
2708 2745 igb->param_adv_1000fdx_cap = igb_get_prop(igb,
2709 2746 PROP_ADV_1000FDX_CAP, 0, 1, 1);
2710 2747 igb->param_adv_100fdx_cap = igb_get_prop(igb,
2711 2748 PROP_ADV_100FDX_CAP, 0, 1, 1);
2712 2749 igb->param_adv_100hdx_cap = igb_get_prop(igb,
2713 2750 PROP_ADV_100HDX_CAP, 0, 1, 1);
2714 2751 igb->param_adv_10fdx_cap = igb_get_prop(igb,
2715 2752 PROP_ADV_10FDX_CAP, 0, 1, 1);
2716 2753 igb->param_adv_10hdx_cap = igb_get_prop(igb,
2717 2754 PROP_ADV_10HDX_CAP, 0, 1, 1);
2718 2755
2719 2756 /*
2720 2757 * Jumbo frame configurations
2721 2758 */
2722 2759 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU,
2723 2760 MIN_MTU, MAX_MTU, DEFAULT_MTU);
2724 2761
2725 2762 igb->max_frame_size = default_mtu +
2726 2763 sizeof (struct ether_vlan_header) + ETHERFCSL;
2727 2764
2728 2765 /*
2729 2766 * Ethernet flow control configuration
2730 2767 */
2731 2768 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL,
2732 2769 e1000_fc_none, 4, e1000_fc_full);
2733 2770 if (flow_control == 4)
2734 2771 flow_control = e1000_fc_default;
2735 2772
2736 2773 hw->fc.requested_mode = flow_control;
2737 2774
2738 2775 /*
2739 2776 * Multiple rings configurations
2740 2777 */
2741 2778 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE,
2742 2779 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
2743 2780 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE,
2744 2781 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
2745 2782
2746 2783 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0);
2747 2784 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM,
2748 2785 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM);
2749 2786 /*
2750 2787 * Currently we do not support VMDq for 82576 and 82580.
2751 2788 * If it is e1000_82576, set num_rx_groups to 1.
2752 2789 */
2753 2790 if (hw->mac.type >= e1000_82576)
2754 2791 igb->num_rx_groups = 1;
2755 2792
2756 2793 if (igb->mr_enable) {
2757 2794 igb->num_tx_rings = igb->capab->def_tx_que_num;
2758 2795 igb->num_rx_rings = igb->capab->def_rx_que_num;
2759 2796 } else {
2760 2797 igb->num_tx_rings = 1;
2761 2798 igb->num_rx_rings = 1;
2762 2799
2763 2800 if (igb->num_rx_groups > 1) {
2764 2801 igb_error(igb,
2765 2802 "Invalid rx groups number. Please enable multiple "
2766 2803 "rings first");
2767 2804 igb->num_rx_groups = 1;
2768 2805 }
2769 2806 }
2770 2807
2771 2808 /*
2772 2809 * Check the divisibility between rx rings and rx groups.
2773 2810 */
2774 2811 for (i = igb->num_rx_groups; i > 0; i--) {
2775 2812 if ((igb->num_rx_rings % i) == 0)
2776 2813 break;
2777 2814 }
2778 2815 if (i != igb->num_rx_groups) {
2779 2816 igb_error(igb,
2780 2817 "Invalid rx groups number. Downgrade the rx group "
2781 2818 "number to %d.", i);
2782 2819 igb->num_rx_groups = i;
2783 2820 }
2784 2821
2785 2822 /*
2786 2823 * Get the ring number per group.
2787 2824 */
2788 2825 ring_per_group = igb->num_rx_rings / igb->num_rx_groups;
2789 2826
2790 2827 if (igb->num_rx_groups == 1) {
2791 2828 /*
2792 2829 * One rx ring group, the rx ring number is num_rx_rings.
2793 2830 */
2794 2831 igb->vmdq_mode = E1000_VMDQ_OFF;
2795 2832 } else if (ring_per_group == 1) {
2796 2833 /*
2797 2834 * Multiple rx groups, each group has one rx ring.
2798 2835 */
2799 2836 igb->vmdq_mode = E1000_VMDQ_MAC;
2800 2837 } else {
2801 2838 /*
2802 2839 * Multiple groups and multiple rings.
2803 2840 */
2804 2841 igb->vmdq_mode = E1000_VMDQ_MAC_RSS;
2805 2842 }
2806 2843
2807 2844 /*
2808 2845 * Tunable used to force an interrupt type. The only use is
2809 2846 * for testing of the lesser interrupt types.
2810 2847 * 0 = don't force interrupt type
2811 2848 * 1 = force interrupt type MSIX
2812 2849 * 2 = force interrupt type MSI
2813 2850 * 3 = force interrupt type Legacy
2814 2851 */
2815 2852 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE,
2816 2853 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE);
2817 2854
2818 2855 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE,
2819 2856 0, 1, 1);
2820 2857 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE,
2821 2858 0, 1, 1);
2822 2859 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE,
2823 2860 0, 1, 1);
2824 2861 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE,
2825 2862 0, 1, 1);
2826 2863
2827 2864 /*
2828 2865 * igb LSO needs the tx h/w checksum support.
2829 2866 * Here LSO will be disabled if tx h/w checksum has been disabled.
2830 2867 */
2831 2868 if (igb->tx_hcksum_enable == B_FALSE)
2832 2869 igb->lso_enable = B_FALSE;
2833 2870
2834 2871 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD,
2835 2872 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
2836 2873 DEFAULT_TX_COPY_THRESHOLD);
2837 2874 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD,
2838 2875 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD,
2839 2876 DEFAULT_TX_RECYCLE_THRESHOLD);
2840 2877 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD,
2841 2878 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD,
2842 2879 DEFAULT_TX_OVERLOAD_THRESHOLD);
2843 2880 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD,
2844 2881 MIN_TX_RESCHED_THRESHOLD,
2845 2882 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD),
2846 2883 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ?
2847 2884 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW);
2848 2885
2849 2886 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD,
2850 2887 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
2851 2888 DEFAULT_RX_COPY_THRESHOLD);
2852 2889 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR,
2853 2890 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
2854 2891 DEFAULT_RX_LIMIT_PER_INTR);
2855 2892
2856 2893 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING,
2857 2894 igb->capab->min_intr_throttle,
2858 2895 igb->capab->max_intr_throttle,
2859 2896 igb->capab->def_intr_throttle);
2860 2897
2861 2898 /*
2862 2899 * Max number of multicast addresses
2863 2900 */
2864 2901 igb->mcast_max_num =
2865 2902 igb_get_prop(igb, PROP_MCAST_MAX_NUM,
2866 2903 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM);
2867 2904 }
2868 2905
2869 2906 /*
2870 2907 * igb_get_prop - Get a property value out of the configuration file igb.conf
2871 2908 *
2872 2909 * Caller provides the name of the property, a default value, a minimum
2873 2910 * value, and a maximum value.
2874 2911 *
2875 2912 * Return configured value of the property, with default, minimum and
2876 2913 * maximum properly applied.
2877 2914 */
2878 2915 static int
2879 2916 igb_get_prop(igb_t *igb,
2880 2917 char *propname, /* name of the property */
2881 2918 int minval, /* minimum acceptable value */
2882 2919 int maxval, /* maximim acceptable value */
2883 2920 int defval) /* default value */
2884 2921 {
2885 2922 int value;
2886 2923
2887 2924 /*
2888 2925 * Call ddi_prop_get_int() to read the conf settings
2889 2926 */
2890 2927 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip,
2891 2928 DDI_PROP_DONTPASS, propname, defval);
2892 2929
2893 2930 if (value > maxval)
2894 2931 value = maxval;
2895 2932
2896 2933 if (value < minval)
2897 2934 value = minval;
2898 2935
2899 2936 return (value);
2900 2937 }
2901 2938
2902 2939 /*
2903 2940 * igb_setup_link - Using the link properties to setup the link
2904 2941 */
2905 2942 int
2906 2943 igb_setup_link(igb_t *igb, boolean_t setup_hw)
2907 2944 {
2908 2945 struct e1000_mac_info *mac;
2909 2946 struct e1000_phy_info *phy;
2910 2947 boolean_t invalid;
2911 2948
2912 2949 mac = &igb->hw.mac;
2913 2950 phy = &igb->hw.phy;
2914 2951 invalid = B_FALSE;
2915 2952
2916 2953 if (igb->param_adv_autoneg_cap == 1) {
2917 2954 mac->autoneg = B_TRUE;
2918 2955 phy->autoneg_advertised = 0;
2919 2956
2920 2957 /*
2921 2958 * 1000hdx is not supported for autonegotiation
2922 2959 */
2923 2960 if (igb->param_adv_1000fdx_cap == 1)
2924 2961 phy->autoneg_advertised |= ADVERTISE_1000_FULL;
2925 2962
2926 2963 if (igb->param_adv_100fdx_cap == 1)
2927 2964 phy->autoneg_advertised |= ADVERTISE_100_FULL;
2928 2965
2929 2966 if (igb->param_adv_100hdx_cap == 1)
2930 2967 phy->autoneg_advertised |= ADVERTISE_100_HALF;
2931 2968
2932 2969 if (igb->param_adv_10fdx_cap == 1)
2933 2970 phy->autoneg_advertised |= ADVERTISE_10_FULL;
2934 2971
2935 2972 if (igb->param_adv_10hdx_cap == 1)
2936 2973 phy->autoneg_advertised |= ADVERTISE_10_HALF;
2937 2974
2938 2975 if (phy->autoneg_advertised == 0)
2939 2976 invalid = B_TRUE;
2940 2977 } else {
2941 2978 mac->autoneg = B_FALSE;
2942 2979
2943 2980 /*
2944 2981 * 1000fdx and 1000hdx are not supported for forced link
2945 2982 */
2946 2983 if (igb->param_adv_100fdx_cap == 1)
2947 2984 mac->forced_speed_duplex = ADVERTISE_100_FULL;
2948 2985 else if (igb->param_adv_100hdx_cap == 1)
2949 2986 mac->forced_speed_duplex = ADVERTISE_100_HALF;
2950 2987 else if (igb->param_adv_10fdx_cap == 1)
2951 2988 mac->forced_speed_duplex = ADVERTISE_10_FULL;
2952 2989 else if (igb->param_adv_10hdx_cap == 1)
2953 2990 mac->forced_speed_duplex = ADVERTISE_10_HALF;
2954 2991 else
2955 2992 invalid = B_TRUE;
2956 2993 }
2957 2994
2958 2995 if (invalid) {
2959 2996 igb_notice(igb, "Invalid link settings. Setup link to "
2960 2997 "autonegotiation with full link capabilities.");
2961 2998 mac->autoneg = B_TRUE;
2962 2999 phy->autoneg_advertised = ADVERTISE_1000_FULL |
2963 3000 ADVERTISE_100_FULL | ADVERTISE_100_HALF |
2964 3001 ADVERTISE_10_FULL | ADVERTISE_10_HALF;
2965 3002 }
2966 3003
2967 3004 if (setup_hw) {
2968 3005 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS)
2969 3006 return (IGB_FAILURE);
2970 3007 }
2971 3008
2972 3009 return (IGB_SUCCESS);
2973 3010 }
2974 3011
2975 3012
2976 3013 /*
2977 3014 * igb_is_link_up - Check if the link is up
2978 3015 */
2979 3016 static boolean_t
2980 3017 igb_is_link_up(igb_t *igb)
2981 3018 {
2982 3019 struct e1000_hw *hw = &igb->hw;
2983 3020 boolean_t link_up = B_FALSE;
2984 3021
2985 3022 ASSERT(mutex_owned(&igb->gen_lock));
2986 3023
2987 3024 /*
2988 3025 * get_link_status is set in the interrupt handler on link-status-change
2989 3026 * or rx sequence error interrupt. get_link_status will stay
2990 3027 * false until the e1000_check_for_link establishes link only
2991 3028 * for copper adapters.
2992 3029 */
2993 3030 switch (hw->phy.media_type) {
2994 3031 case e1000_media_type_copper:
2995 3032 if (hw->mac.get_link_status) {
2996 3033 (void) e1000_check_for_link(hw);
2997 3034 link_up = !hw->mac.get_link_status;
2998 3035 } else {
2999 3036 link_up = B_TRUE;
3000 3037 }
3001 3038 break;
3002 3039 case e1000_media_type_fiber:
3003 3040 (void) e1000_check_for_link(hw);
3004 3041 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
3005 3042 break;
3006 3043 case e1000_media_type_internal_serdes:
3007 3044 (void) e1000_check_for_link(hw);
3008 3045 link_up = hw->mac.serdes_has_link;
3009 3046 break;
3010 3047 }
3011 3048
3012 3049 return (link_up);
3013 3050 }
3014 3051
3015 3052 /*
3016 3053 * igb_link_check - Link status processing
3017 3054 */
3018 3055 static boolean_t
3019 3056 igb_link_check(igb_t *igb)
3020 3057 {
3021 3058 struct e1000_hw *hw = &igb->hw;
3022 3059 uint16_t speed = 0, duplex = 0;
3023 3060 boolean_t link_changed = B_FALSE;
3024 3061
3025 3062 ASSERT(mutex_owned(&igb->gen_lock));
3026 3063
3027 3064 if (igb_is_link_up(igb)) {
3028 3065 /*
3029 3066 * The Link is up, check whether it was marked as down earlier
3030 3067 */
3031 3068 if (igb->link_state != LINK_STATE_UP) {
3032 3069 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex);
3033 3070 igb->link_speed = speed;
3034 3071 igb->link_duplex = duplex;
3035 3072 igb->link_state = LINK_STATE_UP;
3036 3073 link_changed = B_TRUE;
3037 3074 if (!igb->link_complete)
3038 3075 igb_stop_link_timer(igb);
3039 3076 }
3040 3077 } else if (igb->link_complete) {
3041 3078 if (igb->link_state != LINK_STATE_DOWN) {
3042 3079 igb->link_speed = 0;
3043 3080 igb->link_duplex = 0;
3044 3081 igb->link_state = LINK_STATE_DOWN;
3045 3082 link_changed = B_TRUE;
3046 3083 }
3047 3084 }
3048 3085
3049 3086 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3050 3087 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3051 3088 return (B_FALSE);
3052 3089 }
3053 3090
3054 3091 return (link_changed);
3055 3092 }
3056 3093
3057 3094 /*
3058 3095 * igb_local_timer - driver watchdog function
3059 3096 *
3060 3097 * This function will handle the hardware stall check, link status
3061 3098 * check and other routines.
3062 3099 */
3063 3100 static void
3064 3101 igb_local_timer(void *arg)
3065 3102 {
3066 3103 igb_t *igb = (igb_t *)arg;
3067 3104 boolean_t link_changed = B_FALSE;
3068 3105
3069 3106 if (igb->igb_state & IGB_ERROR) {
3070 3107 igb->reset_count++;
3071 3108 if (igb_reset(igb) == IGB_SUCCESS)
3072 3109 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3073 3110
3074 3111 igb_restart_watchdog_timer(igb);
3075 3112 return;
3076 3113 }
3077 3114
3078 3115 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) {
3079 3116 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL);
3080 3117 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST);
3081 3118 igb->reset_count++;
3082 3119 if (igb_reset(igb) == IGB_SUCCESS)
3083 3120 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED);
3084 3121
3085 3122 igb_restart_watchdog_timer(igb);
3086 3123 return;
3087 3124 }
3088 3125
3089 3126 mutex_enter(&igb->gen_lock);
3090 3127 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED))
3091 3128 link_changed = igb_link_check(igb);
3092 3129 mutex_exit(&igb->gen_lock);
3093 3130
3094 3131 if (link_changed)
3095 3132 mac_link_update(igb->mac_hdl, igb->link_state);
3096 3133
3097 3134 igb_restart_watchdog_timer(igb);
3098 3135 }
3099 3136
3100 3137 /*
3101 3138 * igb_link_timer - link setup timer function
3102 3139 *
3103 3140 * It is called when the timer for link setup is expired, which indicates
3104 3141 * the completion of the link setup. The link state will not be updated
3105 3142 * until the link setup is completed. And the link state will not be sent
3106 3143 * to the upper layer through mac_link_update() in this function. It will
3107 3144 * be updated in the local timer routine or the interrupts service routine
3108 3145 * after the interface is started (plumbed).
3109 3146 */
3110 3147 static void
3111 3148 igb_link_timer(void *arg)
3112 3149 {
3113 3150 igb_t *igb = (igb_t *)arg;
3114 3151
3115 3152 mutex_enter(&igb->link_lock);
3116 3153 igb->link_complete = B_TRUE;
3117 3154 igb->link_tid = 0;
3118 3155 mutex_exit(&igb->link_lock);
3119 3156 }
3120 3157 /*
3121 3158 * igb_stall_check - check for transmit stall
3122 3159 *
3123 3160 * This function checks if the adapter is stalled (in transmit).
3124 3161 *
3125 3162 * It is called each time the watchdog timeout is invoked.
3126 3163 * If the transmit descriptor reclaim continuously fails,
3127 3164 * the watchdog value will increment by 1. If the watchdog
3128 3165 * value exceeds the threshold, the igb is assumed to
3129 3166 * have stalled and need to be reset.
3130 3167 */
3131 3168 static boolean_t
3132 3169 igb_stall_check(igb_t *igb)
3133 3170 {
3134 3171 igb_tx_ring_t *tx_ring;
3135 3172 struct e1000_hw *hw = &igb->hw;
3136 3173 boolean_t result;
3137 3174 int i;
3138 3175
3139 3176 if (igb->link_state != LINK_STATE_UP)
3140 3177 return (B_FALSE);
3141 3178
3142 3179 /*
3143 3180 * If any tx ring is stalled, we'll reset the chipset
3144 3181 */
3145 3182 result = B_FALSE;
3146 3183 for (i = 0; i < igb->num_tx_rings; i++) {
3147 3184 tx_ring = &igb->tx_rings[i];
3148 3185
3149 3186 if (tx_ring->recycle_fail > 0)
3150 3187 tx_ring->stall_watchdog++;
3151 3188 else
3152 3189 tx_ring->stall_watchdog = 0;
3153 3190
3154 3191 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
3155 3192 result = B_TRUE;
3156 3193 if (hw->mac.type == e1000_82580) {
3157 3194 hw->dev_spec._82575.global_device_reset
3158 3195 = B_TRUE;
3159 3196 }
3160 3197 break;
3161 3198 }
3162 3199 }
3163 3200
3164 3201 if (result) {
3165 3202 tx_ring->stall_watchdog = 0;
3166 3203 tx_ring->recycle_fail = 0;
3167 3204 }
3168 3205
3169 3206 return (result);
3170 3207 }
3171 3208
3172 3209
3173 3210 /*
3174 3211 * is_valid_mac_addr - Check if the mac address is valid
3175 3212 */
3176 3213 static boolean_t
3177 3214 is_valid_mac_addr(uint8_t *mac_addr)
3178 3215 {
3179 3216 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
3180 3217 const uint8_t addr_test2[6] =
3181 3218 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3182 3219
3183 3220 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
3184 3221 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
3185 3222 return (B_FALSE);
3186 3223
3187 3224 return (B_TRUE);
3188 3225 }
3189 3226
3190 3227 static boolean_t
3191 3228 igb_find_mac_address(igb_t *igb)
3192 3229 {
3193 3230 struct e1000_hw *hw = &igb->hw;
3194 3231 #ifdef __sparc
3195 3232 uchar_t *bytes;
3196 3233 struct ether_addr sysaddr;
3197 3234 uint_t nelts;
3198 3235 int err;
3199 3236 boolean_t found = B_FALSE;
3200 3237
3201 3238 /*
3202 3239 * The "vendor's factory-set address" may already have
3203 3240 * been extracted from the chip, but if the property
3204 3241 * "local-mac-address" is set we use that instead.
3205 3242 *
3206 3243 * We check whether it looks like an array of 6
3207 3244 * bytes (which it should, if OBP set it). If we can't
3208 3245 * make sense of it this way, we'll ignore it.
3209 3246 */
3210 3247 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3211 3248 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
3212 3249 if (err == DDI_PROP_SUCCESS) {
3213 3250 if (nelts == ETHERADDRL) {
3214 3251 while (nelts--)
3215 3252 hw->mac.addr[nelts] = bytes[nelts];
3216 3253 found = B_TRUE;
3217 3254 }
3218 3255 ddi_prop_free(bytes);
3219 3256 }
3220 3257
3221 3258 /*
3222 3259 * Look up the OBP property "local-mac-address?". If the user has set
3223 3260 * 'local-mac-address? = false', use "the system address" instead.
3224 3261 */
3225 3262 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0,
3226 3263 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
3227 3264 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
3228 3265 if (localetheraddr(NULL, &sysaddr) != 0) {
3229 3266 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
3230 3267 found = B_TRUE;
3231 3268 }
3232 3269 }
3233 3270 ddi_prop_free(bytes);
3234 3271 }
3235 3272
3236 3273 /*
3237 3274 * Finally(!), if there's a valid "mac-address" property (created
3238 3275 * if we netbooted from this interface), we must use this instead
3239 3276 * of any of the above to ensure that the NFS/install server doesn't
3240 3277 * get confused by the address changing as Solaris takes over!
3241 3278 */
3242 3279 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip,
3243 3280 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
3244 3281 if (err == DDI_PROP_SUCCESS) {
3245 3282 if (nelts == ETHERADDRL) {
3246 3283 while (nelts--)
3247 3284 hw->mac.addr[nelts] = bytes[nelts];
3248 3285 found = B_TRUE;
3249 3286 }
3250 3287 ddi_prop_free(bytes);
3251 3288 }
3252 3289
3253 3290 if (found) {
3254 3291 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
3255 3292 return (B_TRUE);
3256 3293 }
3257 3294 #endif
3258 3295
3259 3296 /*
3260 3297 * Read the device MAC address from the EEPROM
3261 3298 */
3262 3299 if (e1000_read_mac_addr(hw) != E1000_SUCCESS)
3263 3300 return (B_FALSE);
3264 3301
3265 3302 return (B_TRUE);
3266 3303 }
3267 3304
3268 3305 #pragma inline(igb_arm_watchdog_timer)
3269 3306
3270 3307 static void
3271 3308 igb_arm_watchdog_timer(igb_t *igb)
3272 3309 {
3273 3310 /*
3274 3311 * Fire a watchdog timer
3275 3312 */
3276 3313 igb->watchdog_tid =
3277 3314 timeout(igb_local_timer,
3278 3315 (void *)igb, 1 * drv_usectohz(1000000));
3279 3316
3280 3317 }
3281 3318
3282 3319 /*
3283 3320 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer
3284 3321 */
3285 3322 void
3286 3323 igb_enable_watchdog_timer(igb_t *igb)
3287 3324 {
3288 3325 mutex_enter(&igb->watchdog_lock);
3289 3326
3290 3327 if (!igb->watchdog_enable) {
3291 3328 igb->watchdog_enable = B_TRUE;
3292 3329 igb->watchdog_start = B_TRUE;
3293 3330 igb_arm_watchdog_timer(igb);
3294 3331 }
3295 3332
3296 3333 mutex_exit(&igb->watchdog_lock);
3297 3334
3298 3335 }
3299 3336
3300 3337 /*
3301 3338 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer
3302 3339 */
3303 3340 void
3304 3341 igb_disable_watchdog_timer(igb_t *igb)
3305 3342 {
3306 3343 timeout_id_t tid;
3307 3344
3308 3345 mutex_enter(&igb->watchdog_lock);
3309 3346
3310 3347 igb->watchdog_enable = B_FALSE;
3311 3348 igb->watchdog_start = B_FALSE;
3312 3349 tid = igb->watchdog_tid;
3313 3350 igb->watchdog_tid = 0;
3314 3351
3315 3352 mutex_exit(&igb->watchdog_lock);
3316 3353
3317 3354 if (tid != 0)
3318 3355 (void) untimeout(tid);
3319 3356
3320 3357 }
3321 3358
3322 3359 /*
3323 3360 * igb_start_watchdog_timer - Start the driver watchdog timer
3324 3361 */
3325 3362 static void
3326 3363 igb_start_watchdog_timer(igb_t *igb)
3327 3364 {
3328 3365 mutex_enter(&igb->watchdog_lock);
3329 3366
3330 3367 if (igb->watchdog_enable) {
3331 3368 if (!igb->watchdog_start) {
3332 3369 igb->watchdog_start = B_TRUE;
3333 3370 igb_arm_watchdog_timer(igb);
3334 3371 }
3335 3372 }
3336 3373
3337 3374 mutex_exit(&igb->watchdog_lock);
3338 3375 }
3339 3376
3340 3377 /*
3341 3378 * igb_restart_watchdog_timer - Restart the driver watchdog timer
3342 3379 */
3343 3380 static void
3344 3381 igb_restart_watchdog_timer(igb_t *igb)
3345 3382 {
3346 3383 mutex_enter(&igb->watchdog_lock);
3347 3384
3348 3385 if (igb->watchdog_start)
3349 3386 igb_arm_watchdog_timer(igb);
3350 3387
3351 3388 mutex_exit(&igb->watchdog_lock);
3352 3389 }
3353 3390
3354 3391 /*
3355 3392 * igb_stop_watchdog_timer - Stop the driver watchdog timer
3356 3393 */
3357 3394 static void
3358 3395 igb_stop_watchdog_timer(igb_t *igb)
3359 3396 {
3360 3397 timeout_id_t tid;
3361 3398
3362 3399 mutex_enter(&igb->watchdog_lock);
3363 3400
3364 3401 igb->watchdog_start = B_FALSE;
3365 3402 tid = igb->watchdog_tid;
3366 3403 igb->watchdog_tid = 0;
3367 3404
3368 3405 mutex_exit(&igb->watchdog_lock);
3369 3406
3370 3407 if (tid != 0)
3371 3408 (void) untimeout(tid);
3372 3409 }
3373 3410
3374 3411 /*
3375 3412 * igb_start_link_timer - Start the link setup timer
3376 3413 */
3377 3414 static void
3378 3415 igb_start_link_timer(struct igb *igb)
3379 3416 {
3380 3417 struct e1000_hw *hw = &igb->hw;
3381 3418 clock_t link_timeout;
3382 3419
3383 3420 if (hw->mac.autoneg)
3384 3421 link_timeout = PHY_AUTO_NEG_LIMIT *
3385 3422 drv_usectohz(100000);
3386 3423 else
3387 3424 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000);
3388 3425
3389 3426 mutex_enter(&igb->link_lock);
3390 3427 if (hw->phy.autoneg_wait_to_complete) {
3391 3428 igb->link_complete = B_TRUE;
3392 3429 } else {
3393 3430 igb->link_complete = B_FALSE;
3394 3431 igb->link_tid = timeout(igb_link_timer, (void *)igb,
3395 3432 link_timeout);
3396 3433 }
3397 3434 mutex_exit(&igb->link_lock);
3398 3435 }
3399 3436
3400 3437 /*
3401 3438 * igb_stop_link_timer - Stop the link setup timer
3402 3439 */
3403 3440 static void
3404 3441 igb_stop_link_timer(struct igb *igb)
3405 3442 {
3406 3443 timeout_id_t tid;
3407 3444
3408 3445 mutex_enter(&igb->link_lock);
3409 3446 igb->link_complete = B_TRUE;
3410 3447 tid = igb->link_tid;
3411 3448 igb->link_tid = 0;
3412 3449 mutex_exit(&igb->link_lock);
3413 3450
3414 3451 if (tid != 0)
3415 3452 (void) untimeout(tid);
3416 3453 }
3417 3454
3418 3455 /*
3419 3456 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts
3420 3457 */
3421 3458 static void
3422 3459 igb_disable_adapter_interrupts(igb_t *igb)
3423 3460 {
3424 3461 struct e1000_hw *hw = &igb->hw;
3425 3462
3426 3463 /*
3427 3464 * Set the IMC register to mask all the interrupts,
3428 3465 * including the tx interrupts.
3429 3466 */
3430 3467 E1000_WRITE_REG(hw, E1000_IMC, ~0);
3431 3468 E1000_WRITE_REG(hw, E1000_IAM, 0);
3432 3469
3433 3470 /*
3434 3471 * Additional disabling for MSI-X
3435 3472 */
3436 3473 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3437 3474 E1000_WRITE_REG(hw, E1000_EIMC, ~0);
3438 3475 E1000_WRITE_REG(hw, E1000_EIAC, 0);
3439 3476 E1000_WRITE_REG(hw, E1000_EIAM, 0);
3440 3477 }
3441 3478
3442 3479 E1000_WRITE_FLUSH(hw);
3443 3480 }
3444 3481
3445 3482 /*
3446 3483 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580
3447 3484 */
3448 3485 static void
3449 3486 igb_enable_adapter_interrupts_82580(igb_t *igb)
3450 3487 {
3451 3488 struct e1000_hw *hw = &igb->hw;
3452 3489
3453 3490 /* Clear any pending interrupts */
3454 3491 (void) E1000_READ_REG(hw, E1000_ICR);
3455 3492 igb->ims_mask |= E1000_IMS_DRSTA;
3456 3493
3457 3494 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3458 3495
3459 3496 /* Interrupt enabling for MSI-X */
3460 3497 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3461 3498 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3462 3499 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA);
3463 3500 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3464 3501 } else { /* Interrupt enabling for MSI and legacy */
3465 3502 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3466 3503 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3467 3504 igb->ims_mask |= E1000_IMS_DRSTA;
3468 3505 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask);
3469 3506 }
3470 3507
3471 3508 /* Disable auto-mask for ICR interrupt bits */
3472 3509 E1000_WRITE_REG(hw, E1000_IAM, 0);
3473 3510
3474 3511 E1000_WRITE_FLUSH(hw);
3475 3512 }
3476 3513
3477 3514 /*
3478 3515 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576
3479 3516 */
3480 3517 static void
3481 3518 igb_enable_adapter_interrupts_82576(igb_t *igb)
3482 3519 {
3483 3520 struct e1000_hw *hw = &igb->hw;
3484 3521
3485 3522 /* Clear any pending interrupts */
3486 3523 (void) E1000_READ_REG(hw, E1000_ICR);
3487 3524
3488 3525 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3489 3526
3490 3527 /* Interrupt enabling for MSI-X */
3491 3528 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3492 3529 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3493 3530 igb->ims_mask = E1000_IMS_LSC;
3494 3531 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3495 3532 } else {
3496 3533 /* Interrupt enabling for MSI and legacy */
3497 3534 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID);
3498 3535 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE;
3499 3536 E1000_WRITE_REG(hw, E1000_IMS,
3500 3537 (IMS_ENABLE_MASK | E1000_IMS_TXQE));
3501 3538 }
3502 3539
3503 3540 /* Disable auto-mask for ICR interrupt bits */
3504 3541 E1000_WRITE_REG(hw, E1000_IAM, 0);
3505 3542
3506 3543 E1000_WRITE_FLUSH(hw);
3507 3544 }
3508 3545
3509 3546 /*
3510 3547 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575
3511 3548 */
3512 3549 static void
3513 3550 igb_enable_adapter_interrupts_82575(igb_t *igb)
3514 3551 {
3515 3552 struct e1000_hw *hw = &igb->hw;
3516 3553 uint32_t reg;
3517 3554
3518 3555 /* Clear any pending interrupts */
3519 3556 (void) E1000_READ_REG(hw, E1000_ICR);
3520 3557
3521 3558 if (igb->intr_type == DDI_INTR_TYPE_MSIX) {
3522 3559 /* Interrupt enabling for MSI-X */
3523 3560 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask);
3524 3561 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask);
3525 3562 igb->ims_mask = E1000_IMS_LSC;
3526 3563 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC);
3527 3564
3528 3565 /* Enable MSI-X PBA support */
3529 3566 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
3530 3567 reg |= E1000_CTRL_EXT_PBA_CLR;
3531 3568
3532 3569 /* Non-selective interrupt clear-on-read */
3533 3570 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */
3534 3571
3535 3572 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
3536 3573 } else {
3537 3574 /* Interrupt enabling for MSI and legacy */
3538 3575 igb->ims_mask = IMS_ENABLE_MASK;
3539 3576 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
3540 3577 }
3541 3578
3542 3579 E1000_WRITE_FLUSH(hw);
3543 3580 }
3544 3581
3545 3582 /*
3546 3583 * Loopback Support
3547 3584 */
3548 3585 static lb_property_t lb_normal =
3549 3586 { normal, "normal", IGB_LB_NONE };
3550 3587 static lb_property_t lb_external =
3551 3588 { external, "External", IGB_LB_EXTERNAL };
3552 3589 static lb_property_t lb_phy =
3553 3590 { internal, "PHY", IGB_LB_INTERNAL_PHY };
3554 3591 static lb_property_t lb_serdes =
3555 3592 { internal, "SerDes", IGB_LB_INTERNAL_SERDES };
3556 3593
3557 3594 enum ioc_reply
3558 3595 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp)
3559 3596 {
3560 3597 lb_info_sz_t *lbsp;
3561 3598 lb_property_t *lbpp;
3562 3599 struct e1000_hw *hw;
3563 3600 uint32_t *lbmp;
3564 3601 uint32_t size;
3565 3602 uint32_t value;
3566 3603
3567 3604 hw = &igb->hw;
3568 3605
3569 3606 if (mp->b_cont == NULL)
3570 3607 return (IOC_INVAL);
3571 3608
3572 3609 switch (iocp->ioc_cmd) {
3573 3610 default:
3574 3611 return (IOC_INVAL);
3575 3612
3576 3613 case LB_GET_INFO_SIZE:
3577 3614 size = sizeof (lb_info_sz_t);
3578 3615 if (iocp->ioc_count != size)
3579 3616 return (IOC_INVAL);
3580 3617
3581 3618 value = sizeof (lb_normal);
3582 3619 if (hw->phy.media_type == e1000_media_type_copper)
3583 3620 value += sizeof (lb_phy);
3584 3621 else
3585 3622 value += sizeof (lb_serdes);
3586 3623 value += sizeof (lb_external);
3587 3624
3588 3625 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
3589 3626 *lbsp = value;
3590 3627 break;
3591 3628
3592 3629 case LB_GET_INFO:
3593 3630 value = sizeof (lb_normal);
3594 3631 if (hw->phy.media_type == e1000_media_type_copper)
3595 3632 value += sizeof (lb_phy);
3596 3633 else
3597 3634 value += sizeof (lb_serdes);
3598 3635 value += sizeof (lb_external);
3599 3636
3600 3637 size = value;
3601 3638 if (iocp->ioc_count != size)
3602 3639 return (IOC_INVAL);
3603 3640
3604 3641 value = 0;
3605 3642 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
3606 3643
3607 3644 lbpp[value++] = lb_normal;
3608 3645 if (hw->phy.media_type == e1000_media_type_copper)
3609 3646 lbpp[value++] = lb_phy;
3610 3647 else
3611 3648 lbpp[value++] = lb_serdes;
3612 3649 lbpp[value++] = lb_external;
3613 3650 break;
3614 3651
3615 3652 case LB_GET_MODE:
3616 3653 size = sizeof (uint32_t);
3617 3654 if (iocp->ioc_count != size)
3618 3655 return (IOC_INVAL);
3619 3656
3620 3657 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3621 3658 *lbmp = igb->loopback_mode;
3622 3659 break;
3623 3660
3624 3661 case LB_SET_MODE:
3625 3662 size = 0;
3626 3663 if (iocp->ioc_count != sizeof (uint32_t))
3627 3664 return (IOC_INVAL);
3628 3665
3629 3666 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3630 3667 if (!igb_set_loopback_mode(igb, *lbmp))
3631 3668 return (IOC_INVAL);
3632 3669 break;
3633 3670 }
3634 3671
3635 3672 iocp->ioc_count = size;
3636 3673 iocp->ioc_error = 0;
3637 3674
3638 3675 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3639 3676 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3640 3677 return (IOC_INVAL);
3641 3678 }
3642 3679
3643 3680 return (IOC_REPLY);
3644 3681 }
3645 3682
3646 3683 /*
3647 3684 * igb_set_loopback_mode - Setup loopback based on the loopback mode
3648 3685 */
3649 3686 static boolean_t
3650 3687 igb_set_loopback_mode(igb_t *igb, uint32_t mode)
3651 3688 {
3652 3689 struct e1000_hw *hw;
3653 3690 int i;
3654 3691
3655 3692 if (mode == igb->loopback_mode)
3656 3693 return (B_TRUE);
3657 3694
3658 3695 hw = &igb->hw;
3659 3696
3660 3697 igb->loopback_mode = mode;
3661 3698
3662 3699 if (mode == IGB_LB_NONE) {
3663 3700 /* Reset the chip */
3664 3701 hw->phy.autoneg_wait_to_complete = B_TRUE;
3665 3702 (void) igb_reset(igb);
3666 3703 hw->phy.autoneg_wait_to_complete = B_FALSE;
3667 3704 return (B_TRUE);
3668 3705 }
3669 3706
3670 3707 mutex_enter(&igb->gen_lock);
3671 3708
3672 3709 switch (mode) {
3673 3710 default:
3674 3711 mutex_exit(&igb->gen_lock);
3675 3712 return (B_FALSE);
3676 3713
3677 3714 case IGB_LB_EXTERNAL:
3678 3715 igb_set_external_loopback(igb);
3679 3716 break;
3680 3717
3681 3718 case IGB_LB_INTERNAL_PHY:
3682 3719 igb_set_internal_phy_loopback(igb);
3683 3720 break;
3684 3721
3685 3722 case IGB_LB_INTERNAL_SERDES:
3686 3723 igb_set_internal_serdes_loopback(igb);
3687 3724 break;
3688 3725 }
3689 3726
3690 3727 mutex_exit(&igb->gen_lock);
3691 3728
3692 3729 /*
3693 3730 * When external loopback is set, wait up to 1000ms to get the link up.
3694 3731 * According to test, 1000ms can work and it's an experimental value.
3695 3732 */
3696 3733 if (mode == IGB_LB_EXTERNAL) {
3697 3734 for (i = 0; i <= 10; i++) {
3698 3735 mutex_enter(&igb->gen_lock);
3699 3736 (void) igb_link_check(igb);
3700 3737 mutex_exit(&igb->gen_lock);
3701 3738
3702 3739 if (igb->link_state == LINK_STATE_UP)
3703 3740 break;
3704 3741
3705 3742 msec_delay(100);
3706 3743 }
3707 3744
3708 3745 if (igb->link_state != LINK_STATE_UP) {
3709 3746 /*
3710 3747 * Does not support external loopback.
3711 3748 * Reset driver to loopback none.
3712 3749 */
3713 3750 igb->loopback_mode = IGB_LB_NONE;
3714 3751
3715 3752 /* Reset the chip */
3716 3753 hw->phy.autoneg_wait_to_complete = B_TRUE;
3717 3754 (void) igb_reset(igb);
3718 3755 hw->phy.autoneg_wait_to_complete = B_FALSE;
3719 3756
3720 3757 IGB_DEBUGLOG_0(igb, "Set external loopback failed, "
3721 3758 "reset to loopback none.");
3722 3759
3723 3760 return (B_FALSE);
3724 3761 }
3725 3762 }
3726 3763
3727 3764 return (B_TRUE);
3728 3765 }
3729 3766
3730 3767 /*
3731 3768 * igb_set_external_loopback - Set the external loopback mode
3732 3769 */
3733 3770 static void
3734 3771 igb_set_external_loopback(igb_t *igb)
3735 3772 {
3736 3773 struct e1000_hw *hw;
3737 3774 uint32_t ctrl_ext;
3738 3775
3739 3776 hw = &igb->hw;
3740 3777
3741 3778 /* Set link mode to PHY (00b) in the Extended Control register */
3742 3779 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3743 3780 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3744 3781 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3745 3782
3746 3783 (void) e1000_write_phy_reg(hw, 0x0, 0x0140);
3747 3784 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00);
3748 3785 (void) e1000_write_phy_reg(hw, 0x12, 0x1610);
3749 3786 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c);
3750 3787 }
3751 3788
3752 3789 /*
3753 3790 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode
3754 3791 */
3755 3792 static void
3756 3793 igb_set_internal_phy_loopback(igb_t *igb)
3757 3794 {
3758 3795 struct e1000_hw *hw;
3759 3796 uint32_t ctrl_ext;
3760 3797 uint16_t phy_ctrl;
3761 3798 uint16_t phy_pconf;
3762 3799
3763 3800 hw = &igb->hw;
3764 3801
3765 3802 /* Set link mode to PHY (00b) in the Extended Control register */
3766 3803 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3767 3804 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
3768 3805 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3769 3806
3770 3807 /*
3771 3808 * Set PHY control register (0x4140):
3772 3809 * Set full duplex mode
3773 3810 * Set loopback bit
3774 3811 * Clear auto-neg enable bit
3775 3812 * Set PHY speed
3776 3813 */
3777 3814 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK;
3778 3815 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
3779 3816
3780 3817 /* Set the link disable bit in the Port Configuration register */
3781 3818 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf);
3782 3819 phy_pconf |= (uint16_t)1 << 14;
3783 3820 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf);
3784 3821 }
3785 3822
3786 3823 /*
3787 3824 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode
3788 3825 */
3789 3826 static void
3790 3827 igb_set_internal_serdes_loopback(igb_t *igb)
3791 3828 {
3792 3829 struct e1000_hw *hw;
3793 3830 uint32_t ctrl_ext;
3794 3831 uint32_t ctrl;
3795 3832 uint32_t pcs_lctl;
3796 3833 uint32_t connsw;
3797 3834
3798 3835 hw = &igb->hw;
3799 3836
3800 3837 /* Set link mode to SerDes (11b) in the Extended Control register */
3801 3838 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3802 3839 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
3803 3840 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3804 3841
3805 3842 /* Configure the SerDes to loopback */
3806 3843 E1000_WRITE_REG(hw, E1000_SCTL, 0x410);
3807 3844
3808 3845 /* Set Device Control register */
3809 3846 ctrl = E1000_READ_REG(hw, E1000_CTRL);
3810 3847 ctrl |= (E1000_CTRL_FD | /* Force full duplex */
3811 3848 E1000_CTRL_SLU); /* Force link up */
3812 3849 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */
3813 3850 E1000_CTRL_TFCE | /* Disable transmit flow control */
3814 3851 E1000_CTRL_LRST); /* Clear link reset */
3815 3852 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
3816 3853
3817 3854 /* Set PCS Link Control register */
3818 3855 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL);
3819 3856 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK |
3820 3857 E1000_PCS_LCTL_FSD |
3821 3858 E1000_PCS_LCTL_FDV_FULL |
3822 3859 E1000_PCS_LCTL_FLV_LINK_UP);
3823 3860 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE;
3824 3861 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl);
3825 3862
3826 3863 /* Set the Copper/Fiber Switch Control - CONNSW register */
3827 3864 connsw = E1000_READ_REG(hw, E1000_CONNSW);
3828 3865 connsw &= ~E1000_CONNSW_ENRGSRC;
3829 3866 E1000_WRITE_REG(hw, E1000_CONNSW, connsw);
3830 3867 }
3831 3868
3832 3869 #pragma inline(igb_intr_rx_work)
3833 3870 /*
3834 3871 * igb_intr_rx_work - rx processing of ISR
3835 3872 */
3836 3873 static void
3837 3874 igb_intr_rx_work(igb_rx_ring_t *rx_ring)
3838 3875 {
3839 3876 mblk_t *mp;
3840 3877
3841 3878 mutex_enter(&rx_ring->rx_lock);
3842 3879 mp = igb_rx(rx_ring, IGB_NO_POLL);
3843 3880 mutex_exit(&rx_ring->rx_lock);
3844 3881
3845 3882 if (mp != NULL)
3846 3883 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp,
3847 3884 rx_ring->ring_gen_num);
3848 3885 }
3849 3886
3850 3887 #pragma inline(igb_intr_tx_work)
3851 3888 /*
3852 3889 * igb_intr_tx_work - tx processing of ISR
3853 3890 */
3854 3891 static void
3855 3892 igb_intr_tx_work(igb_tx_ring_t *tx_ring)
3856 3893 {
3857 3894 igb_t *igb = tx_ring->igb;
3858 3895
3859 3896 /* Recycle the tx descriptors */
3860 3897 tx_ring->tx_recycle(tx_ring);
3861 3898
3862 3899 /* Schedule the re-transmit */
3863 3900 if (tx_ring->reschedule &&
3864 3901 (tx_ring->tbd_free >= igb->tx_resched_thresh)) {
3865 3902 tx_ring->reschedule = B_FALSE;
3866 3903 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle);
3867 3904 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
3868 3905 }
3869 3906 }
3870 3907
3871 3908 #pragma inline(igb_intr_link_work)
3872 3909 /*
3873 3910 * igb_intr_link_work - link-status-change processing of ISR
3874 3911 */
3875 3912 static void
3876 3913 igb_intr_link_work(igb_t *igb)
3877 3914 {
3878 3915 boolean_t link_changed;
3879 3916
3880 3917 igb_stop_watchdog_timer(igb);
3881 3918
3882 3919 mutex_enter(&igb->gen_lock);
3883 3920
3884 3921 /*
3885 3922 * Because we got a link-status-change interrupt, force
3886 3923 * e1000_check_for_link() to look at phy
3887 3924 */
3888 3925 igb->hw.mac.get_link_status = B_TRUE;
3889 3926
3890 3927 /* igb_link_check takes care of link status change */
3891 3928 link_changed = igb_link_check(igb);
3892 3929
3893 3930 /* Get new phy state */
3894 3931 igb_get_phy_state(igb);
3895 3932
3896 3933 mutex_exit(&igb->gen_lock);
3897 3934
3898 3935 if (link_changed)
3899 3936 mac_link_update(igb->mac_hdl, igb->link_state);
3900 3937
3901 3938 igb_start_watchdog_timer(igb);
3902 3939 }
3903 3940
3904 3941 /*
3905 3942 * igb_intr_legacy - Interrupt handler for legacy interrupts
3906 3943 */
3907 3944 static uint_t
3908 3945 igb_intr_legacy(void *arg1, void *arg2)
3909 3946 {
3910 3947 igb_t *igb = (igb_t *)arg1;
3911 3948 igb_tx_ring_t *tx_ring;
3912 3949 uint32_t icr;
3913 3950 mblk_t *mp;
3914 3951 boolean_t tx_reschedule;
3915 3952 boolean_t link_changed;
3916 3953 uint_t result;
3917 3954
3918 3955 _NOTE(ARGUNUSED(arg2));
3919 3956
3920 3957 mutex_enter(&igb->gen_lock);
3921 3958
3922 3959 if (igb->igb_state & IGB_SUSPENDED) {
3923 3960 mutex_exit(&igb->gen_lock);
3924 3961 return (DDI_INTR_UNCLAIMED);
3925 3962 }
3926 3963
3927 3964 mp = NULL;
3928 3965 tx_reschedule = B_FALSE;
3929 3966 link_changed = B_FALSE;
3930 3967 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
3931 3968
3932 3969 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
3933 3970 mutex_exit(&igb->gen_lock);
3934 3971 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
3935 3972 atomic_or_32(&igb->igb_state, IGB_ERROR);
3936 3973 return (DDI_INTR_UNCLAIMED);
3937 3974 }
3938 3975
3939 3976 if (icr & E1000_ICR_INT_ASSERTED) {
3940 3977 /*
3941 3978 * E1000_ICR_INT_ASSERTED bit was set:
3942 3979 * Read(Clear) the ICR, claim this interrupt,
3943 3980 * look for work to do.
3944 3981 */
3945 3982 ASSERT(igb->num_rx_rings == 1);
3946 3983 ASSERT(igb->num_tx_rings == 1);
3947 3984
3948 3985 /* Make sure all interrupt causes cleared */
3949 3986 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
3950 3987
3951 3988 if (icr & E1000_ICR_RXT0) {
3952 3989 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL);
3953 3990 }
3954 3991
3955 3992 if (icr & E1000_ICR_TXDW) {
3956 3993 tx_ring = &igb->tx_rings[0];
3957 3994
3958 3995 /* Recycle the tx descriptors */
3959 3996 tx_ring->tx_recycle(tx_ring);
3960 3997
3961 3998 /* Schedule the re-transmit */
3962 3999 tx_reschedule = (tx_ring->reschedule &&
3963 4000 (tx_ring->tbd_free >= igb->tx_resched_thresh));
3964 4001 }
3965 4002
3966 4003 if (icr & E1000_ICR_LSC) {
3967 4004 /*
3968 4005 * Because we got a link-status-change interrupt, force
3969 4006 * e1000_check_for_link() to look at phy
3970 4007 */
3971 4008 igb->hw.mac.get_link_status = B_TRUE;
3972 4009
3973 4010 /* igb_link_check takes care of link status change */
3974 4011 link_changed = igb_link_check(igb);
3975 4012
3976 4013 /* Get new phy state */
3977 4014 igb_get_phy_state(igb);
3978 4015 }
3979 4016
3980 4017 if (icr & E1000_ICR_DRSTA) {
3981 4018 /* 82580 Full Device Reset needed */
3982 4019 atomic_or_32(&igb->igb_state, IGB_STALL);
3983 4020 }
3984 4021
3985 4022 result = DDI_INTR_CLAIMED;
3986 4023 } else {
3987 4024 /*
3988 4025 * E1000_ICR_INT_ASSERTED bit was not set:
3989 4026 * Don't claim this interrupt.
3990 4027 */
3991 4028 result = DDI_INTR_UNCLAIMED;
3992 4029 }
3993 4030
3994 4031 mutex_exit(&igb->gen_lock);
3995 4032
3996 4033 /*
3997 4034 * Do the following work outside of the gen_lock
3998 4035 */
3999 4036 if (mp != NULL)
4000 4037 mac_rx(igb->mac_hdl, NULL, mp);
4001 4038
4002 4039 if (tx_reschedule) {
4003 4040 tx_ring->reschedule = B_FALSE;
4004 4041 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle);
4005 4042 IGB_DEBUG_STAT(tx_ring->stat_reschedule);
4006 4043 }
4007 4044
4008 4045 if (link_changed)
4009 4046 mac_link_update(igb->mac_hdl, igb->link_state);
4010 4047
4011 4048 return (result);
4012 4049 }
4013 4050
4014 4051 /*
4015 4052 * igb_intr_msi - Interrupt handler for MSI
4016 4053 */
4017 4054 static uint_t
4018 4055 igb_intr_msi(void *arg1, void *arg2)
4019 4056 {
4020 4057 igb_t *igb = (igb_t *)arg1;
4021 4058 uint32_t icr;
4022 4059
4023 4060 _NOTE(ARGUNUSED(arg2));
4024 4061
4025 4062 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4026 4063
4027 4064 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4028 4065 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4029 4066 atomic_or_32(&igb->igb_state, IGB_ERROR);
4030 4067 return (DDI_INTR_CLAIMED);
4031 4068 }
4032 4069
4033 4070 /* Make sure all interrupt causes cleared */
4034 4071 (void) E1000_READ_REG(&igb->hw, E1000_EICR);
4035 4072
4036 4073 /*
4037 4074 * For MSI interrupt, we have only one vector,
4038 4075 * so we have only one rx ring and one tx ring enabled.
4039 4076 */
4040 4077 ASSERT(igb->num_rx_rings == 1);
4041 4078 ASSERT(igb->num_tx_rings == 1);
4042 4079
4043 4080 if (icr & E1000_ICR_RXT0) {
4044 4081 igb_intr_rx_work(&igb->rx_rings[0]);
4045 4082 }
4046 4083
4047 4084 if (icr & E1000_ICR_TXDW) {
4048 4085 igb_intr_tx_work(&igb->tx_rings[0]);
4049 4086 }
4050 4087
4051 4088 if (icr & E1000_ICR_LSC) {
4052 4089 igb_intr_link_work(igb);
4053 4090 }
4054 4091
4055 4092 if (icr & E1000_ICR_DRSTA) {
4056 4093 /* 82580 Full Device Reset needed */
4057 4094 atomic_or_32(&igb->igb_state, IGB_STALL);
4058 4095 }
4059 4096
4060 4097 return (DDI_INTR_CLAIMED);
4061 4098 }
4062 4099
4063 4100 /*
4064 4101 * igb_intr_rx - Interrupt handler for rx
4065 4102 */
4066 4103 static uint_t
4067 4104 igb_intr_rx(void *arg1, void *arg2)
4068 4105 {
4069 4106 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1;
4070 4107
4071 4108 _NOTE(ARGUNUSED(arg2));
4072 4109
4073 4110 /*
4074 4111 * Only used via MSI-X vector so don't check cause bits
4075 4112 * and only clean the given ring.
4076 4113 */
4077 4114 igb_intr_rx_work(rx_ring);
4078 4115
4079 4116 return (DDI_INTR_CLAIMED);
4080 4117 }
4081 4118
4082 4119 /*
4083 4120 * igb_intr_tx - Interrupt handler for tx
4084 4121 */
4085 4122 static uint_t
4086 4123 igb_intr_tx(void *arg1, void *arg2)
4087 4124 {
4088 4125 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1;
4089 4126
4090 4127 _NOTE(ARGUNUSED(arg2));
4091 4128
4092 4129 /*
4093 4130 * Only used via MSI-X vector so don't check cause bits
4094 4131 * and only clean the given ring.
4095 4132 */
4096 4133 igb_intr_tx_work(tx_ring);
4097 4134
4098 4135 return (DDI_INTR_CLAIMED);
4099 4136 }
4100 4137
4101 4138 /*
4102 4139 * igb_intr_tx_other - Interrupt handler for both tx and other
4103 4140 *
4104 4141 */
4105 4142 static uint_t
4106 4143 igb_intr_tx_other(void *arg1, void *arg2)
4107 4144 {
4108 4145 igb_t *igb = (igb_t *)arg1;
4109 4146 uint32_t icr;
4110 4147
4111 4148 _NOTE(ARGUNUSED(arg2));
4112 4149
4113 4150 icr = E1000_READ_REG(&igb->hw, E1000_ICR);
4114 4151
4115 4152 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) {
4116 4153 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED);
4117 4154 atomic_or_32(&igb->igb_state, IGB_ERROR);
4118 4155 return (DDI_INTR_CLAIMED);
4119 4156 }
4120 4157
4121 4158 /*
4122 4159 * Look for tx reclaiming work first. Remember, in the
4123 4160 * case of only interrupt sharing, only one tx ring is
4124 4161 * used
4125 4162 */
4126 4163 igb_intr_tx_work(&igb->tx_rings[0]);
4127 4164
4128 4165 /*
4129 4166 * Check for "other" causes.
4130 4167 */
4131 4168 if (icr & E1000_ICR_LSC) {
4132 4169 igb_intr_link_work(igb);
4133 4170 }
4134 4171
4135 4172 /*
4136 4173 * The DOUTSYNC bit indicates a tx packet dropped because
4137 4174 * DMA engine gets "out of sync". There isn't a real fix
4138 4175 * for this. The Intel recommendation is to count the number
4139 4176 * of occurrences so user can detect when it is happening.
4140 4177 * The issue is non-fatal and there's no recovery action
4141 4178 * available.
4142 4179 */
4143 4180 if (icr & E1000_ICR_DOUTSYNC) {
4144 4181 IGB_STAT(igb->dout_sync);
4145 4182 }
4146 4183
4147 4184 if (icr & E1000_ICR_DRSTA) {
4148 4185 /* 82580 Full Device Reset needed */
4149 4186 atomic_or_32(&igb->igb_state, IGB_STALL);
4150 4187 }
4151 4188
4152 4189 return (DDI_INTR_CLAIMED);
4153 4190 }
4154 4191
4155 4192 /*
4156 4193 * igb_alloc_intrs - Allocate interrupts for the driver
4157 4194 *
4158 4195 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4159 4196 * if not successful, try Legacy.
4160 4197 * igb->intr_force can be used to force sequence to start with
4161 4198 * any of the 3 types.
4162 4199 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4163 4200 */
4164 4201 static int
4165 4202 igb_alloc_intrs(igb_t *igb)
4166 4203 {
4167 4204 dev_info_t *devinfo;
4168 4205 int intr_types;
4169 4206 int rc;
4170 4207
4171 4208 devinfo = igb->dip;
4172 4209
4173 4210 /* Get supported interrupt types */
4174 4211 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4175 4212
4176 4213 if (rc != DDI_SUCCESS) {
4177 4214 igb_log(igb,
4178 4215 "Get supported interrupt types failed: %d", rc);
4179 4216 return (IGB_FAILURE);
4180 4217 }
4181 4218 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types);
4182 4219
4183 4220 igb->intr_type = 0;
4184 4221
4185 4222 /* Install MSI-X interrupts */
4186 4223 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
4187 4224 (igb->intr_force <= IGB_INTR_MSIX)) {
4188 4225 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX);
4189 4226
4190 4227 if (rc == IGB_SUCCESS)
4191 4228 return (IGB_SUCCESS);
4192 4229
4193 4230 igb_log(igb,
4194 4231 "Allocate MSI-X failed, trying MSI interrupts...");
4195 4232 }
4196 4233
4197 4234 /* MSI-X not used, force rings to 1 */
4198 4235 igb->num_rx_rings = 1;
4199 4236 igb->num_tx_rings = 1;
4200 4237 igb_log(igb,
4201 4238 "MSI-X not used, force rx and tx queue number to 1");
4202 4239
4203 4240 /* Install MSI interrupts */
4204 4241 if ((intr_types & DDI_INTR_TYPE_MSI) &&
4205 4242 (igb->intr_force <= IGB_INTR_MSI)) {
4206 4243 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI);
4207 4244
4208 4245 if (rc == IGB_SUCCESS)
4209 4246 return (IGB_SUCCESS);
4210 4247
4211 4248 igb_log(igb,
4212 4249 "Allocate MSI failed, trying Legacy interrupts...");
4213 4250 }
4214 4251
4215 4252 /* Install legacy interrupts */
4216 4253 if (intr_types & DDI_INTR_TYPE_FIXED) {
4217 4254 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED);
4218 4255
4219 4256 if (rc == IGB_SUCCESS)
4220 4257 return (IGB_SUCCESS);
4221 4258
4222 4259 igb_log(igb,
4223 4260 "Allocate Legacy interrupts failed");
4224 4261 }
4225 4262
4226 4263 /* If none of the 3 types succeeded, return failure */
4227 4264 return (IGB_FAILURE);
4228 4265 }
4229 4266
4230 4267 /*
4231 4268 * igb_alloc_intr_handles - Allocate interrupt handles.
4232 4269 *
4233 4270 * For legacy and MSI, only 1 handle is needed. For MSI-X,
4234 4271 * if fewer than 2 handles are available, return failure.
4235 4272 * Upon success, this sets the number of Rx rings to a number that
4236 4273 * matches the handles available for Rx interrupts.
4237 4274 */
4238 4275 static int
4239 4276 igb_alloc_intr_handles(igb_t *igb, int intr_type)
4240 4277 {
4241 4278 dev_info_t *devinfo;
4242 4279 int orig, request, count, avail, actual;
4243 4280 int diff, minimum;
4244 4281 int rc;
4245 4282
4246 4283 devinfo = igb->dip;
4247 4284
4248 4285 switch (intr_type) {
4249 4286 case DDI_INTR_TYPE_FIXED:
4250 4287 request = 1; /* Request 1 legacy interrupt handle */
4251 4288 minimum = 1;
4252 4289 IGB_DEBUGLOG_0(igb, "interrupt type: legacy");
4253 4290 break;
4254 4291
4255 4292 case DDI_INTR_TYPE_MSI:
4256 4293 request = 1; /* Request 1 MSI interrupt handle */
4257 4294 minimum = 1;
4258 4295 IGB_DEBUGLOG_0(igb, "interrupt type: MSI");
4259 4296 break;
4260 4297
4261 4298 case DDI_INTR_TYPE_MSIX:
4262 4299 /*
4263 4300 * Number of vectors for the adapter is
4264 4301 * # rx rings + # tx rings
4265 4302 * One of tx vectors is for tx & other
4266 4303 */
4267 4304 request = igb->num_rx_rings + igb->num_tx_rings;
4268 4305 orig = request;
4269 4306 minimum = 2;
4270 4307 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X");
4271 4308 break;
4272 4309
4273 4310 default:
4274 4311 igb_log(igb,
4275 4312 "invalid call to igb_alloc_intr_handles(): %d\n",
4276 4313 intr_type);
4277 4314 return (IGB_FAILURE);
4278 4315 }
4279 4316 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d",
4280 4317 request, minimum);
4281 4318
4282 4319 /*
4283 4320 * Get number of supported interrupts
4284 4321 */
4285 4322 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
4286 4323 if ((rc != DDI_SUCCESS) || (count < minimum)) {
4287 4324 igb_log(igb,
4288 4325 "Get supported interrupt number failed. "
4289 4326 "Return: %d, count: %d", rc, count);
4290 4327 return (IGB_FAILURE);
4291 4328 }
4292 4329 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count);
4293 4330
4294 4331 /*
4295 4332 * Get number of available interrupts
4296 4333 */
4297 4334 rc = ddi_intr_get_navail(devinfo, intr_type, &avail);
4298 4335 if ((rc != DDI_SUCCESS) || (avail < minimum)) {
4299 4336 igb_log(igb,
4300 4337 "Get available interrupt number failed. "
4301 4338 "Return: %d, available: %d", rc, avail);
4302 4339 return (IGB_FAILURE);
4303 4340 }
4304 4341 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail);
4305 4342
4306 4343 if (avail < request) {
4307 4344 igb_log(igb, "Request %d handles, %d available",
4308 4345 request, avail);
4309 4346 request = avail;
4310 4347 }
4311 4348
4312 4349 actual = 0;
4313 4350 igb->intr_cnt = 0;
4314 4351
4315 4352 /*
4316 4353 * Allocate an array of interrupt handles
4317 4354 */
4318 4355 igb->intr_size = request * sizeof (ddi_intr_handle_t);
4319 4356 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP);
4320 4357
4321 4358 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0,
4322 4359 request, &actual, DDI_INTR_ALLOC_NORMAL);
4323 4360 if (rc != DDI_SUCCESS) {
4324 4361 igb_log(igb, "Allocate interrupts failed. "
4325 4362 "return: %d, request: %d, actual: %d",
4326 4363 rc, request, actual);
4327 4364 goto alloc_handle_fail;
4328 4365 }
4329 4366 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual);
4330 4367
4331 4368 igb->intr_cnt = actual;
4332 4369
4333 4370 if (actual < minimum) {
4334 4371 igb_log(igb, "Insufficient interrupt handles allocated: %d",
4335 4372 actual);
4336 4373 goto alloc_handle_fail;
4337 4374 }
4338 4375
4339 4376 /*
4340 4377 * For MSI-X, actual might force us to reduce number of tx & rx rings
4341 4378 */
4342 4379 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) {
4343 4380 diff = orig - actual;
4344 4381 if (diff < igb->num_tx_rings) {
4345 4382 igb_log(igb,
4346 4383 "MSI-X vectors force Tx queue number to %d",
4347 4384 igb->num_tx_rings - diff);
4348 4385 igb->num_tx_rings -= diff;
4349 4386 } else {
4350 4387 igb_log(igb,
4351 4388 "MSI-X vectors force Tx queue number to 1");
4352 4389 igb->num_tx_rings = 1;
4353 4390
4354 4391 igb_log(igb,
4355 4392 "MSI-X vectors force Rx queue number to %d",
4356 4393 actual - 1);
4357 4394 igb->num_rx_rings = actual - 1;
4358 4395 }
4359 4396 }
4360 4397
4361 4398 /*
4362 4399 * Get priority for first vector, assume remaining are all the same
4363 4400 */
4364 4401 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri);
4365 4402 if (rc != DDI_SUCCESS) {
4366 4403 igb_log(igb,
4367 4404 "Get interrupt priority failed: %d", rc);
4368 4405 goto alloc_handle_fail;
4369 4406 }
4370 4407
4371 4408 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap);
4372 4409 if (rc != DDI_SUCCESS) {
4373 4410 igb_log(igb,
4374 4411 "Get interrupt cap failed: %d", rc);
4375 4412 goto alloc_handle_fail;
4376 4413 }
4377 4414
4378 4415 igb->intr_type = intr_type;
4379 4416
4380 4417 return (IGB_SUCCESS);
4381 4418
4382 4419 alloc_handle_fail:
4383 4420 igb_rem_intrs(igb);
4384 4421
4385 4422 return (IGB_FAILURE);
4386 4423 }
4387 4424
4388 4425 /*
4389 4426 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type
4390 4427 *
4391 4428 * Before adding the interrupt handlers, the interrupt vectors have
4392 4429 * been allocated, and the rx/tx rings have also been allocated.
4393 4430 */
4394 4431 static int
4395 4432 igb_add_intr_handlers(igb_t *igb)
4396 4433 {
4397 4434 igb_rx_ring_t *rx_ring;
4398 4435 igb_tx_ring_t *tx_ring;
4399 4436 int vector;
4400 4437 int rc;
4401 4438 int i;
4402 4439
4403 4440 vector = 0;
4404 4441
4405 4442 switch (igb->intr_type) {
4406 4443 case DDI_INTR_TYPE_MSIX:
4407 4444 /* Add interrupt handler for tx + other */
4408 4445 tx_ring = &igb->tx_rings[0];
4409 4446 rc = ddi_intr_add_handler(igb->htable[vector],
4410 4447 (ddi_intr_handler_t *)igb_intr_tx_other,
4411 4448 (void *)igb, NULL);
4412 4449
4413 4450 if (rc != DDI_SUCCESS) {
4414 4451 igb_log(igb,
4415 4452 "Add tx/other interrupt handler failed: %d", rc);
4416 4453 return (IGB_FAILURE);
4417 4454 }
4418 4455 tx_ring->intr_vector = vector;
4419 4456 vector++;
4420 4457
4421 4458 /* Add interrupt handler for each rx ring */
4422 4459 for (i = 0; i < igb->num_rx_rings; i++) {
4423 4460 rx_ring = &igb->rx_rings[i];
4424 4461
4425 4462 rc = ddi_intr_add_handler(igb->htable[vector],
4426 4463 (ddi_intr_handler_t *)igb_intr_rx,
4427 4464 (void *)rx_ring, NULL);
4428 4465
4429 4466 if (rc != DDI_SUCCESS) {
4430 4467 igb_log(igb,
4431 4468 "Add rx interrupt handler failed. "
4432 4469 "return: %d, rx ring: %d", rc, i);
4433 4470 for (vector--; vector >= 0; vector--) {
4434 4471 (void) ddi_intr_remove_handler(
4435 4472 igb->htable[vector]);
4436 4473 }
4437 4474 return (IGB_FAILURE);
4438 4475 }
4439 4476
4440 4477 rx_ring->intr_vector = vector;
4441 4478
4442 4479 vector++;
4443 4480 }
4444 4481
4445 4482 /* Add interrupt handler for each tx ring from 2nd ring */
4446 4483 for (i = 1; i < igb->num_tx_rings; i++) {
4447 4484 tx_ring = &igb->tx_rings[i];
4448 4485
4449 4486 rc = ddi_intr_add_handler(igb->htable[vector],
4450 4487 (ddi_intr_handler_t *)igb_intr_tx,
4451 4488 (void *)tx_ring, NULL);
4452 4489
4453 4490 if (rc != DDI_SUCCESS) {
4454 4491 igb_log(igb,
4455 4492 "Add tx interrupt handler failed. "
4456 4493 "return: %d, tx ring: %d", rc, i);
4457 4494 for (vector--; vector >= 0; vector--) {
4458 4495 (void) ddi_intr_remove_handler(
4459 4496 igb->htable[vector]);
4460 4497 }
4461 4498 return (IGB_FAILURE);
4462 4499 }
4463 4500
4464 4501 tx_ring->intr_vector = vector;
4465 4502
4466 4503 vector++;
4467 4504 }
4468 4505
4469 4506 break;
4470 4507
4471 4508 case DDI_INTR_TYPE_MSI:
4472 4509 /* Add interrupt handlers for the only vector */
4473 4510 rc = ddi_intr_add_handler(igb->htable[vector],
4474 4511 (ddi_intr_handler_t *)igb_intr_msi,
4475 4512 (void *)igb, NULL);
4476 4513
4477 4514 if (rc != DDI_SUCCESS) {
4478 4515 igb_log(igb,
4479 4516 "Add MSI interrupt handler failed: %d", rc);
4480 4517 return (IGB_FAILURE);
4481 4518 }
4482 4519
4483 4520 rx_ring = &igb->rx_rings[0];
4484 4521 rx_ring->intr_vector = vector;
4485 4522
4486 4523 vector++;
4487 4524 break;
4488 4525
4489 4526 case DDI_INTR_TYPE_FIXED:
4490 4527 /* Add interrupt handlers for the only vector */
4491 4528 rc = ddi_intr_add_handler(igb->htable[vector],
4492 4529 (ddi_intr_handler_t *)igb_intr_legacy,
4493 4530 (void *)igb, NULL);
4494 4531
4495 4532 if (rc != DDI_SUCCESS) {
4496 4533 igb_log(igb,
4497 4534 "Add legacy interrupt handler failed: %d", rc);
4498 4535 return (IGB_FAILURE);
4499 4536 }
4500 4537
4501 4538 rx_ring = &igb->rx_rings[0];
4502 4539 rx_ring->intr_vector = vector;
4503 4540
4504 4541 vector++;
4505 4542 break;
4506 4543
4507 4544 default:
4508 4545 return (IGB_FAILURE);
4509 4546 }
4510 4547
4511 4548 ASSERT(vector == igb->intr_cnt);
4512 4549
4513 4550 return (IGB_SUCCESS);
4514 4551 }
4515 4552
4516 4553 /*
4517 4554 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts
4518 4555 *
4519 4556 * For each vector enabled on the adapter, Set the MSIXBM register accordingly
4520 4557 */
4521 4558 static void
4522 4559 igb_setup_msix_82575(igb_t *igb)
4523 4560 {
4524 4561 uint32_t eims = 0;
4525 4562 int i, vector;
4526 4563 struct e1000_hw *hw = &igb->hw;
4527 4564
4528 4565 /*
4529 4566 * Set vector for tx ring 0 and other causes.
4530 4567 * NOTE assumption that it is vector 0.
4531 4568 */
4532 4569 vector = 0;
4533 4570
4534 4571 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER;
4535 4572 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask);
4536 4573 vector++;
4537 4574
4538 4575 for (i = 0; i < igb->num_rx_rings; i++) {
4539 4576 /*
4540 4577 * Set vector for each rx ring
4541 4578 */
4542 4579 eims = (E1000_EICR_RX_QUEUE0 << i);
4543 4580 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4544 4581
4545 4582 /*
4546 4583 * Accumulate bits to enable in
4547 4584 * igb_enable_adapter_interrupts_82575()
4548 4585 */
4549 4586 igb->eims_mask |= eims;
4550 4587
4551 4588 vector++;
4552 4589 }
4553 4590
4554 4591 for (i = 1; i < igb->num_tx_rings; i++) {
4555 4592 /*
4556 4593 * Set vector for each tx ring from 2nd tx ring
4557 4594 */
4558 4595 eims = (E1000_EICR_TX_QUEUE0 << i);
4559 4596 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims);
4560 4597
4561 4598 /*
4562 4599 * Accumulate bits to enable in
4563 4600 * igb_enable_adapter_interrupts_82575()
4564 4601 */
4565 4602 igb->eims_mask |= eims;
4566 4603
4567 4604 vector++;
4568 4605 }
4569 4606
4570 4607 ASSERT(vector == igb->intr_cnt);
4571 4608
4572 4609 /*
4573 4610 * Disable IAM for ICR interrupt bits
4574 4611 */
4575 4612 E1000_WRITE_REG(hw, E1000_IAM, 0);
4576 4613 E1000_WRITE_FLUSH(hw);
4577 4614 }
4578 4615
4579 4616 /*
4580 4617 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts
4581 4618 *
4582 4619 * 82576 uses a table based method for assigning vectors. Each queue has a
4583 4620 * single entry in the table to which we write a vector number along with a
4584 4621 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors
4585 4622 * take a different position in the 4-byte register depending on whether
4586 4623 * they are numbered above or below 8.
4587 4624 */
4588 4625 static void
4589 4626 igb_setup_msix_82576(igb_t *igb)
4590 4627 {
4591 4628 struct e1000_hw *hw = &igb->hw;
4592 4629 uint32_t ivar, index, vector;
4593 4630 int i;
4594 4631
4595 4632 /* must enable msi-x capability before IVAR settings */
4596 4633 E1000_WRITE_REG(hw, E1000_GPIE,
4597 4634 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR));
4598 4635
4599 4636 /*
4600 4637 * Set vector for tx ring 0 and other causes.
4601 4638 * NOTE assumption that it is vector 0.
4602 4639 * This is also interdependent with installation of interrupt service
4603 4640 * routines in igb_add_intr_handlers().
4604 4641 */
4605 4642
4606 4643 /* assign "other" causes to vector 0 */
4607 4644 vector = 0;
4608 4645 ivar = ((vector | E1000_IVAR_VALID) << 8);
4609 4646 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4610 4647
4611 4648 /* assign tx ring 0 to vector 0 */
4612 4649 ivar = ((vector | E1000_IVAR_VALID) << 8);
4613 4650 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4614 4651
4615 4652 /* prepare to enable tx & other interrupt causes */
4616 4653 igb->eims_mask = (1 << vector);
4617 4654
4618 4655 vector ++;
4619 4656 for (i = 0; i < igb->num_rx_rings; i++) {
4620 4657 /*
4621 4658 * Set vector for each rx ring
4622 4659 */
4623 4660 index = (i & 0x7);
4624 4661 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4625 4662
4626 4663 if (i < 8) {
4627 4664 /* vector goes into low byte of register */
4628 4665 ivar = ivar & 0xFFFFFF00;
4629 4666 ivar |= (vector | E1000_IVAR_VALID);
4630 4667 } else {
4631 4668 /* vector goes into third byte of register */
4632 4669 ivar = ivar & 0xFF00FFFF;
4633 4670 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4634 4671 }
4635 4672 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4636 4673
4637 4674 /* Accumulate interrupt-cause bits to enable */
4638 4675 igb->eims_mask |= (1 << vector);
4639 4676
4640 4677 vector ++;
4641 4678 }
4642 4679
4643 4680 for (i = 1; i < igb->num_tx_rings; i++) {
4644 4681 /*
4645 4682 * Set vector for each tx ring from 2nd tx ring.
4646 4683 * Note assumption that tx vectors numericall follow rx vectors.
4647 4684 */
4648 4685 index = (i & 0x7);
4649 4686 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4650 4687
4651 4688 if (i < 8) {
4652 4689 /* vector goes into second byte of register */
4653 4690 ivar = ivar & 0xFFFF00FF;
4654 4691 ivar |= ((vector | E1000_IVAR_VALID) << 8);
4655 4692 } else {
4656 4693 /* vector goes into fourth byte of register */
4657 4694 ivar = ivar & 0x00FFFFFF;
4658 4695 ivar |= (vector | E1000_IVAR_VALID) << 24;
4659 4696 }
4660 4697 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4661 4698
4662 4699 /* Accumulate interrupt-cause bits to enable */
4663 4700 igb->eims_mask |= (1 << vector);
4664 4701
4665 4702 vector ++;
4666 4703 }
4667 4704
4668 4705 ASSERT(vector == igb->intr_cnt);
4669 4706 }
4670 4707
4671 4708 /*
4672 4709 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts
4673 4710 *
4674 4711 * 82580 uses same table approach at 82576 but has fewer entries. Each
4675 4712 * queue has a single entry in the table to which we write a vector number
4676 4713 * along with a "valid" bit. Vectors take a different position in the
4677 4714 * register depending on * whether * they are numbered above or below 4.
4678 4715 */
4679 4716 static void
4680 4717 igb_setup_msix_82580(igb_t *igb)
4681 4718 {
4682 4719 struct e1000_hw *hw = &igb->hw;
4683 4720 uint32_t ivar, index, vector;
4684 4721 int i;
4685 4722
4686 4723 /* must enable msi-x capability before IVAR settings */
4687 4724 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE |
4688 4725 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME));
4689 4726 /*
4690 4727 * Set vector for tx ring 0 and other causes.
4691 4728 * NOTE assumption that it is vector 0.
4692 4729 * This is also interdependent with installation of interrupt service
4693 4730 * routines in igb_add_intr_handlers().
4694 4731 */
4695 4732
4696 4733 /* assign "other" causes to vector 0 */
4697 4734 vector = 0;
4698 4735 ivar = ((vector | E1000_IVAR_VALID) << 8);
4699 4736 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
4700 4737
4701 4738 /* assign tx ring 0 to vector 0 */
4702 4739 ivar = ((vector | E1000_IVAR_VALID) << 8);
4703 4740 E1000_WRITE_REG(hw, E1000_IVAR0, ivar);
4704 4741
4705 4742 /* prepare to enable tx & other interrupt causes */
4706 4743 igb->eims_mask = (1 << vector);
4707 4744
4708 4745 vector ++;
4709 4746
4710 4747 for (i = 0; i < igb->num_rx_rings; i++) {
4711 4748 /*
4712 4749 * Set vector for each rx ring
4713 4750 */
4714 4751 index = (i >> 1);
4715 4752 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4716 4753
4717 4754 if (i & 1) {
4718 4755 /* vector goes into third byte of register */
4719 4756 ivar = ivar & 0xFF00FFFF;
4720 4757 ivar |= ((vector | E1000_IVAR_VALID) << 16);
4721 4758 } else {
4722 4759 /* vector goes into low byte of register */
4723 4760 ivar = ivar & 0xFFFFFF00;
4724 4761 ivar |= (vector | E1000_IVAR_VALID);
4725 4762 }
4726 4763 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4727 4764
4728 4765 /* Accumulate interrupt-cause bits to enable */
4729 4766 igb->eims_mask |= (1 << vector);
4730 4767
4731 4768 vector ++;
4732 4769 }
4733 4770
4734 4771 for (i = 1; i < igb->num_tx_rings; i++) {
4735 4772 /*
4736 4773 * Set vector for each tx ring from 2nd tx ring.
4737 4774 * Note assumption that tx vectors numericall follow rx vectors.
4738 4775 */
4739 4776 index = (i >> 1);
4740 4777 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4741 4778
4742 4779 if (i & 1) {
4743 4780 /* vector goes into high byte of register */
4744 4781 ivar = ivar & 0x00FFFFFF;
4745 4782 ivar |= ((vector | E1000_IVAR_VALID) << 24);
4746 4783 } else {
4747 4784 /* vector goes into second byte of register */
4748 4785 ivar = ivar & 0xFFFF00FF;
4749 4786 ivar |= (vector | E1000_IVAR_VALID) << 8;
4750 4787 }
4751 4788 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
4752 4789
4753 4790 /* Accumulate interrupt-cause bits to enable */
4754 4791 igb->eims_mask |= (1 << vector);
4755 4792
4756 4793 vector ++;
4757 4794 }
4758 4795 ASSERT(vector == igb->intr_cnt);
4759 4796 }
4760 4797
4761 4798 /*
4762 4799 * igb_rem_intr_handlers - remove the interrupt handlers
4763 4800 */
4764 4801 static void
4765 4802 igb_rem_intr_handlers(igb_t *igb)
4766 4803 {
4767 4804 int i;
4768 4805 int rc;
4769 4806
4770 4807 for (i = 0; i < igb->intr_cnt; i++) {
4771 4808 rc = ddi_intr_remove_handler(igb->htable[i]);
4772 4809 if (rc != DDI_SUCCESS) {
4773 4810 IGB_DEBUGLOG_1(igb,
4774 4811 "Remove intr handler failed: %d", rc);
4775 4812 }
4776 4813 }
4777 4814 }
4778 4815
4779 4816 /*
4780 4817 * igb_rem_intrs - remove the allocated interrupts
4781 4818 */
4782 4819 static void
4783 4820 igb_rem_intrs(igb_t *igb)
4784 4821 {
4785 4822 int i;
4786 4823 int rc;
4787 4824
4788 4825 for (i = 0; i < igb->intr_cnt; i++) {
4789 4826 rc = ddi_intr_free(igb->htable[i]);
4790 4827 if (rc != DDI_SUCCESS) {
4791 4828 IGB_DEBUGLOG_1(igb,
4792 4829 "Free intr failed: %d", rc);
4793 4830 }
4794 4831 }
4795 4832
4796 4833 kmem_free(igb->htable, igb->intr_size);
4797 4834 igb->htable = NULL;
4798 4835 }
4799 4836
4800 4837 /*
4801 4838 * igb_enable_intrs - enable all the ddi interrupts
4802 4839 */
4803 4840 static int
4804 4841 igb_enable_intrs(igb_t *igb)
4805 4842 {
4806 4843 int i;
4807 4844 int rc;
4808 4845
4809 4846 /* Enable interrupts */
4810 4847 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4811 4848 /* Call ddi_intr_block_enable() for MSI */
4812 4849 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt);
4813 4850 if (rc != DDI_SUCCESS) {
4814 4851 igb_log(igb,
4815 4852 "Enable block intr failed: %d", rc);
4816 4853 return (IGB_FAILURE);
4817 4854 }
4818 4855 } else {
4819 4856 /* Call ddi_intr_enable() for Legacy/MSI non block enable */
4820 4857 for (i = 0; i < igb->intr_cnt; i++) {
4821 4858 rc = ddi_intr_enable(igb->htable[i]);
4822 4859 if (rc != DDI_SUCCESS) {
4823 4860 igb_log(igb,
4824 4861 "Enable intr failed: %d", rc);
4825 4862 return (IGB_FAILURE);
4826 4863 }
4827 4864 }
4828 4865 }
4829 4866
4830 4867 return (IGB_SUCCESS);
4831 4868 }
4832 4869
4833 4870 /*
4834 4871 * igb_disable_intrs - disable all the ddi interrupts
4835 4872 */
4836 4873 static int
4837 4874 igb_disable_intrs(igb_t *igb)
4838 4875 {
4839 4876 int i;
4840 4877 int rc;
4841 4878
4842 4879 /* Disable all interrupts */
4843 4880 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) {
4844 4881 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt);
4845 4882 if (rc != DDI_SUCCESS) {
4846 4883 igb_log(igb,
4847 4884 "Disable block intr failed: %d", rc);
4848 4885 return (IGB_FAILURE);
4849 4886 }
4850 4887 } else {
4851 4888 for (i = 0; i < igb->intr_cnt; i++) {
4852 4889 rc = ddi_intr_disable(igb->htable[i]);
4853 4890 if (rc != DDI_SUCCESS) {
4854 4891 igb_log(igb,
4855 4892 "Disable intr failed: %d", rc);
4856 4893 return (IGB_FAILURE);
4857 4894 }
4858 4895 }
4859 4896 }
4860 4897
4861 4898 return (IGB_SUCCESS);
4862 4899 }
4863 4900
4864 4901 /*
4865 4902 * igb_get_phy_state - Get and save the parameters read from PHY registers
4866 4903 */
4867 4904 static void
4868 4905 igb_get_phy_state(igb_t *igb)
4869 4906 {
4870 4907 struct e1000_hw *hw = &igb->hw;
4871 4908 uint16_t phy_ctrl;
4872 4909 uint16_t phy_status;
4873 4910 uint16_t phy_an_adv;
4874 4911 uint16_t phy_an_exp;
4875 4912 uint16_t phy_ext_status;
4876 4913 uint16_t phy_1000t_ctrl;
4877 4914 uint16_t phy_1000t_status;
4878 4915 uint16_t phy_lp_able;
4879 4916
4880 4917 ASSERT(mutex_owned(&igb->gen_lock));
4881 4918
4882 4919 if (hw->phy.media_type == e1000_media_type_copper) {
4883 4920 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
4884 4921 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
4885 4922 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv);
4886 4923 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp);
4887 4924 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status);
4888 4925 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl);
4889 4926 (void) e1000_read_phy_reg(hw,
4890 4927 PHY_1000T_STATUS, &phy_1000t_status);
4891 4928 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able);
4892 4929
4893 4930 igb->param_autoneg_cap =
4894 4931 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0;
4895 4932 igb->param_pause_cap =
4896 4933 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
4897 4934 igb->param_asym_pause_cap =
4898 4935 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
4899 4936 igb->param_1000fdx_cap =
4900 4937 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) ||
4901 4938 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0;
4902 4939 igb->param_1000hdx_cap =
4903 4940 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) ||
4904 4941 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0;
4905 4942 igb->param_100t4_cap =
4906 4943 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0;
4907 4944 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) ||
4908 4945 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0;
4909 4946 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) ||
4910 4947 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0;
4911 4948 igb->param_10fdx_cap =
4912 4949 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0;
4913 4950 igb->param_10hdx_cap =
4914 4951 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0;
4915 4952 igb->param_rem_fault =
4916 4953 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0;
4917 4954
4918 4955 igb->param_adv_autoneg_cap = hw->mac.autoneg;
4919 4956 igb->param_adv_pause_cap =
4920 4957 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0;
4921 4958 igb->param_adv_asym_pause_cap =
4922 4959 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0;
4923 4960 igb->param_adv_1000hdx_cap =
4924 4961 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0;
4925 4962 igb->param_adv_100t4_cap =
4926 4963 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0;
4927 4964 igb->param_adv_rem_fault =
4928 4965 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0;
4929 4966 if (igb->param_adv_autoneg_cap == 1) {
4930 4967 igb->param_adv_1000fdx_cap =
4931 4968 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0;
4932 4969 igb->param_adv_100fdx_cap =
4933 4970 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0;
4934 4971 igb->param_adv_100hdx_cap =
4935 4972 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0;
4936 4973 igb->param_adv_10fdx_cap =
4937 4974 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0;
4938 4975 igb->param_adv_10hdx_cap =
4939 4976 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0;
4940 4977 }
4941 4978
4942 4979 igb->param_lp_autoneg_cap =
4943 4980 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0;
4944 4981 igb->param_lp_pause_cap =
4945 4982 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0;
4946 4983 igb->param_lp_asym_pause_cap =
4947 4984 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0;
4948 4985 igb->param_lp_1000fdx_cap =
4949 4986 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0;
4950 4987 igb->param_lp_1000hdx_cap =
4951 4988 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0;
4952 4989 igb->param_lp_100t4_cap =
4953 4990 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0;
4954 4991 igb->param_lp_100fdx_cap =
4955 4992 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0;
4956 4993 igb->param_lp_100hdx_cap =
4957 4994 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0;
4958 4995 igb->param_lp_10fdx_cap =
4959 4996 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0;
4960 4997 igb->param_lp_10hdx_cap =
4961 4998 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0;
4962 4999 igb->param_lp_rem_fault =
4963 5000 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0;
4964 5001 } else {
4965 5002 /*
4966 5003 * 1Gig Fiber adapter only offers 1Gig Full Duplex.
4967 5004 */
4968 5005 igb->param_autoneg_cap = 0;
4969 5006 igb->param_pause_cap = 1;
4970 5007 igb->param_asym_pause_cap = 1;
4971 5008 igb->param_1000fdx_cap = 1;
4972 5009 igb->param_1000hdx_cap = 0;
4973 5010 igb->param_100t4_cap = 0;
4974 5011 igb->param_100fdx_cap = 0;
4975 5012 igb->param_100hdx_cap = 0;
4976 5013 igb->param_10fdx_cap = 0;
4977 5014 igb->param_10hdx_cap = 0;
4978 5015
4979 5016 igb->param_adv_autoneg_cap = 0;
4980 5017 igb->param_adv_pause_cap = 1;
4981 5018 igb->param_adv_asym_pause_cap = 1;
4982 5019 igb->param_adv_1000fdx_cap = 1;
4983 5020 igb->param_adv_1000hdx_cap = 0;
4984 5021 igb->param_adv_100t4_cap = 0;
4985 5022 igb->param_adv_100fdx_cap = 0;
4986 5023 igb->param_adv_100hdx_cap = 0;
4987 5024 igb->param_adv_10fdx_cap = 0;
4988 5025 igb->param_adv_10hdx_cap = 0;
4989 5026
4990 5027 igb->param_lp_autoneg_cap = 0;
4991 5028 igb->param_lp_pause_cap = 0;
4992 5029 igb->param_lp_asym_pause_cap = 0;
4993 5030 igb->param_lp_1000fdx_cap = 0;
4994 5031 igb->param_lp_1000hdx_cap = 0;
4995 5032 igb->param_lp_100t4_cap = 0;
4996 5033 igb->param_lp_100fdx_cap = 0;
4997 5034 igb->param_lp_100hdx_cap = 0;
4998 5035 igb->param_lp_10fdx_cap = 0;
4999 5036 igb->param_lp_10hdx_cap = 0;
5000 5037 igb->param_lp_rem_fault = 0;
5001 5038 }
5002 5039 }
5003 5040
5004 5041 /*
5005 5042 * synchronize the adv* and en* parameters.
5006 5043 *
5007 5044 * See comments in <sys/dld.h> for details of the *_en_*
5008 5045 * parameters. The usage of ndd for setting adv parameters will
5009 5046 * synchronize all the en parameters with the e1000g parameters,
5010 5047 * implicitly disabling any settings made via dladm.
5011 5048 */
5012 5049 static void
5013 5050 igb_param_sync(igb_t *igb)
5014 5051 {
5015 5052 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap;
5016 5053 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap;
5017 5054 igb->param_en_100t4_cap = igb->param_adv_100t4_cap;
5018 5055 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap;
5019 5056 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap;
5020 5057 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap;
5021 5058 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap;
5022 5059 }
5023 5060
5024 5061 /*
5025 5062 * igb_get_driver_control
5026 5063 */
5027 5064 static void
5028 5065 igb_get_driver_control(struct e1000_hw *hw)
5029 5066 {
5030 5067 uint32_t ctrl_ext;
5031 5068
5032 5069 /* Notify firmware that driver is in control of device */
5033 5070 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5034 5071 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD;
5035 5072 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5036 5073 }
5037 5074
5038 5075 /*
5039 5076 * igb_release_driver_control
5040 5077 */
5041 5078 static void
5042 5079 igb_release_driver_control(struct e1000_hw *hw)
5043 5080 {
5044 5081 uint32_t ctrl_ext;
5045 5082
5046 5083 /* Notify firmware that driver is no longer in control of device */
5047 5084 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
5048 5085 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD;
5049 5086 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
5050 5087 }
5051 5088
5052 5089 /*
5053 5090 * igb_atomic_reserve - Atomic decrease operation
5054 5091 */
5055 5092 int
5056 5093 igb_atomic_reserve(uint32_t *count_p, uint32_t n)
5057 5094 {
5058 5095 uint32_t oldval;
5059 5096 uint32_t newval;
5060 5097
5061 5098 /* ATOMICALLY */
5062 5099 do {
5063 5100 oldval = *count_p;
5064 5101 if (oldval < n)
5065 5102 return (-1);
5066 5103 newval = oldval - n;
5067 5104 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5068 5105
5069 5106 return (newval);
5070 5107 }
5071 5108
5072 5109 /*
5073 5110 * FMA support
5074 5111 */
5075 5112
5076 5113 int
5077 5114 igb_check_acc_handle(ddi_acc_handle_t handle)
5078 5115 {
5079 5116 ddi_fm_error_t de;
5080 5117
5081 5118 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5082 5119 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5083 5120 return (de.fme_status);
5084 5121 }
5085 5122
5086 5123 int
5087 5124 igb_check_dma_handle(ddi_dma_handle_t handle)
5088 5125 {
5089 5126 ddi_fm_error_t de;
5090 5127
5091 5128 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5092 5129 return (de.fme_status);
5093 5130 }
5094 5131
5095 5132 /*
5096 5133 * The IO fault service error handling callback function
5097 5134 */
5098 5135 /*ARGSUSED*/
5099 5136 static int
5100 5137 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5101 5138 {
5102 5139 /*
5103 5140 * as the driver can always deal with an error in any dma or
5104 5141 * access handle, we can just return the fme_status value.
5105 5142 */
5106 5143 pci_ereport_post(dip, err, NULL);
5107 5144 return (err->fme_status);
5108 5145 }
5109 5146
5110 5147 static void
5111 5148 igb_fm_init(igb_t *igb)
5112 5149 {
5113 5150 ddi_iblock_cookie_t iblk;
5114 5151 int fma_dma_flag;
5115 5152
5116 5153 /* Only register with IO Fault Services if we have some capability */
5117 5154 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5118 5155 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5119 5156 } else {
5120 5157 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5121 5158 }
5122 5159
5123 5160 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5124 5161 fma_dma_flag = 1;
5125 5162 } else {
5126 5163 fma_dma_flag = 0;
5127 5164 }
5128 5165
5129 5166 (void) igb_set_fma_flags(fma_dma_flag);
5130 5167
5131 5168 if (igb->fm_capabilities) {
5132 5169
5133 5170 /* Register capabilities with IO Fault Services */
5134 5171 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk);
5135 5172
5136 5173 /*
5137 5174 * Initialize pci ereport capabilities if ereport capable
5138 5175 */
5139 5176 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5140 5177 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5141 5178 pci_ereport_setup(igb->dip);
5142 5179
5143 5180 /*
5144 5181 * Register error callback if error callback capable
5145 5182 */
5146 5183 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5147 5184 ddi_fm_handler_register(igb->dip,
5148 5185 igb_fm_error_cb, (void*) igb);
5149 5186 }
5150 5187 }
5151 5188
5152 5189 static void
5153 5190 igb_fm_fini(igb_t *igb)
5154 5191 {
5155 5192 /* Only unregister FMA capabilities if we registered some */
5156 5193 if (igb->fm_capabilities) {
5157 5194
5158 5195 /*
5159 5196 * Release any resources allocated by pci_ereport_setup()
5160 5197 */
5161 5198 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) ||
5162 5199 DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5163 5200 pci_ereport_teardown(igb->dip);
5164 5201
5165 5202 /*
5166 5203 * Un-register error callback if error callback capable
5167 5204 */
5168 5205 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities))
5169 5206 ddi_fm_handler_unregister(igb->dip);
5170 5207
5171 5208 /* Unregister from IO Fault Services */
5172 5209 ddi_fm_fini(igb->dip);
5173 5210 }
5174 5211 }
5175 5212
5176 5213 void
5177 5214 igb_fm_ereport(igb_t *igb, char *detail)
5178 5215 {
5179 5216 uint64_t ena;
5180 5217 char buf[FM_MAX_CLASS];
5181 5218
5182 5219 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5183 5220 ena = fm_ena_generate(0, FM_ENA_FMT1);
5184 5221 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) {
5185 5222 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP,
5186 5223 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5187 5224 }
5188 5225 }
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