Print this page
2038 Add in I350 and ET2 support into igb
Reviewed by: Dan McDonald <danmcd@nexenta.com>
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/igb/igb_hw.h
+++ new/usr/src/uts/common/io/igb/igb_hw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
|
↓ open down ↓ |
12 lines elided |
↑ open up ↑ |
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 - * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
23 + * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 */
29 29
30 30 /* IntelVersion: 1.446.2.1 v3_3_14_3_BHSW1 */
31 31
32 32 #ifndef _IGB_HW_H
33 33 #define _IGB_HW_H
34 34
35 35 #ifdef __cplusplus
36 36 extern "C" {
37 37 #endif
38 38
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
39 39 #include "igb_osdep.h"
40 40 #include "igb_regs.h"
41 41 #include "igb_defines.h"
42 42
43 43 struct e1000_hw;
44 44
45 45 #define E1000_DEV_ID_82576 0x10C9
46 46 #define E1000_DEV_ID_82576_FIBER 0x10E6
47 47 #define E1000_DEV_ID_82576_SERDES 0x10E7
48 48 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
49 +#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
49 50 #define E1000_DEV_ID_82576_NS 0x150A
50 51 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
51 52 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
52 53 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
53 54 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
54 55 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
55 56 #define E1000_DEV_ID_82580_COPPER 0x150E
56 57 #define E1000_DEV_ID_82580_FIBER 0x150F
57 58 #define E1000_DEV_ID_82580_SERDES 0x1510
58 59 #define E1000_DEV_ID_82580_SGMII 0x1511
59 60 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
61 +#define E1000_DEV_ID_I350_COPPER 0x1521
60 62
61 63 #define E1000_REVISION_0 0
62 64 #define E1000_REVISION_1 1
63 65 #define E1000_REVISION_2 2
64 66 #define E1000_REVISION_3 3
65 67 #define E1000_REVISION_4 4
66 68
67 69 #define E1000_FUNC_0 0
68 70 #define E1000_FUNC_1 1
69 71 #define E1000_FUNC_2 2
70 72 #define E1000_FUNC_3 3
71 73
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
72 74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
73 75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
74 76 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
75 77 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
76 78
77 79 enum e1000_mac_type {
78 80 e1000_undefined = 0,
79 81 e1000_82575,
80 82 e1000_82576,
81 83 e1000_82580,
84 + e1000_i350,
82 85 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
83 86 };
84 87
85 88 enum e1000_media_type {
86 89 e1000_media_type_unknown = 0,
87 90 e1000_media_type_copper = 1,
88 91 e1000_media_type_fiber = 2,
89 92 e1000_media_type_internal_serdes = 3,
90 93 e1000_num_media_types
91 94 };
92 95
93 96 enum e1000_nvm_type {
94 97 e1000_nvm_unknown = 0,
95 98 e1000_nvm_none,
96 99 e1000_nvm_eeprom_spi,
97 100 e1000_nvm_eeprom_microwire,
98 101 e1000_nvm_flash_hw,
99 102 e1000_nvm_flash_sw
100 103 };
101 104
102 105 enum e1000_nvm_override {
103 106 e1000_nvm_override_none = 0,
104 107 e1000_nvm_override_spi_small,
105 108 e1000_nvm_override_spi_large,
106 109 e1000_nvm_override_microwire_small,
107 110 e1000_nvm_override_microwire_large
108 111 };
109 112
110 113 enum e1000_phy_type {
111 114 e1000_phy_unknown = 0,
112 115 e1000_phy_none,
113 116 e1000_phy_m88,
114 117 e1000_phy_igp,
115 118 e1000_phy_igp_2,
116 119 e1000_phy_gg82563,
117 120 e1000_phy_igp_3,
118 121 e1000_phy_ife,
119 122 e1000_phy_82580,
120 123 e1000_phy_vf
121 124 };
122 125
123 126 enum e1000_bus_type {
124 127 e1000_bus_type_unknown = 0,
125 128 e1000_bus_type_pci,
126 129 e1000_bus_type_pcix,
127 130 e1000_bus_type_pci_express,
128 131 e1000_bus_type_reserved
129 132 };
130 133
131 134 enum e1000_bus_speed {
132 135 e1000_bus_speed_unknown = 0,
133 136 e1000_bus_speed_33,
134 137 e1000_bus_speed_66,
135 138 e1000_bus_speed_100,
136 139 e1000_bus_speed_120,
137 140 e1000_bus_speed_133,
138 141 e1000_bus_speed_2500,
139 142 e1000_bus_speed_5000,
140 143 e1000_bus_speed_reserved
141 144 };
142 145
143 146 enum e1000_bus_width {
144 147 e1000_bus_width_unknown = 0,
145 148 e1000_bus_width_pcie_x1,
146 149 e1000_bus_width_pcie_x2,
147 150 e1000_bus_width_pcie_x4 = 4,
148 151 e1000_bus_width_pcie_x8 = 8,
149 152 e1000_bus_width_32,
150 153 e1000_bus_width_64,
151 154 e1000_bus_width_reserved
152 155 };
153 156
154 157 enum e1000_1000t_rx_status {
155 158 e1000_1000t_rx_status_not_ok = 0,
156 159 e1000_1000t_rx_status_ok,
157 160 e1000_1000t_rx_status_undefined = 0xFF
158 161 };
159 162
160 163 enum e1000_rev_polarity {
161 164 e1000_rev_polarity_normal = 0,
162 165 e1000_rev_polarity_reversed,
163 166 e1000_rev_polarity_undefined = 0xFF
164 167 };
165 168
166 169 enum e1000_fc_mode {
167 170 e1000_fc_none = 0,
168 171 e1000_fc_rx_pause,
169 172 e1000_fc_tx_pause,
170 173 e1000_fc_full,
171 174 e1000_fc_default = 0xFF
172 175 };
173 176
174 177 enum e1000_ms_type {
175 178 e1000_ms_hw_default = 0,
176 179 e1000_ms_force_master,
177 180 e1000_ms_force_slave,
178 181 e1000_ms_auto
179 182 };
180 183
181 184 enum e1000_smart_speed {
182 185 e1000_smart_speed_default = 0,
183 186 e1000_smart_speed_on,
184 187 e1000_smart_speed_off
185 188 };
186 189
187 190 enum e1000_serdes_link_state {
188 191 e1000_serdes_link_down = 0,
189 192 e1000_serdes_link_autoneg_progress,
190 193 e1000_serdes_link_autoneg_complete,
191 194 e1000_serdes_link_forced_up
192 195 };
193 196
194 197 /* Receive Descriptor */
195 198 struct e1000_rx_desc {
196 199 __le64 buffer_addr; /* Address of the descriptor's data buffer */
197 200 __le16 length; /* Length of data DMAed into data buffer */
198 201 __le16 csum; /* Packet checksum */
199 202 u8 status; /* Descriptor status */
200 203 u8 errors; /* Descriptor Errors */
201 204 __le16 special;
202 205 };
203 206
204 207 /* Receive Descriptor - Extended */
205 208 union e1000_rx_desc_extended {
206 209 struct {
207 210 __le64 buffer_addr;
208 211 __le64 reserved;
209 212 } read;
210 213 struct {
211 214 struct {
212 215 __le32 mrq; /* Multiple Rx Queues */
213 216 union {
214 217 __le32 rss; /* RSS Hash */
215 218 struct {
216 219 __le16 ip_id; /* IP id */
217 220 __le16 csum; /* Packet Checksum */
218 221 } csum_ip;
219 222 } hi_dword;
220 223 } lower;
221 224 struct {
222 225 __le32 status_error; /* ext status/error */
223 226 __le16 length;
224 227 __le16 vlan; /* VLAN tag */
225 228 } upper;
226 229 } wb; /* writeback */
227 230 };
228 231
229 232 #define MAX_PS_BUFFERS 4
230 233 /* Receive Descriptor - Packet Split */
231 234 union e1000_rx_desc_packet_split {
232 235 struct {
233 236 /* one buffer for protocol header(s), three data buffers */
234 237 __le64 buffer_addr[MAX_PS_BUFFERS];
235 238 } read;
236 239 struct {
237 240 struct {
238 241 __le32 mrq; /* Multiple Rx Queues */
239 242 union {
240 243 __le32 rss; /* RSS Hash */
241 244 struct {
242 245 __le16 ip_id; /* IP id */
243 246 __le16 csum; /* Packet Checksum */
244 247 } csum_ip;
245 248 } hi_dword;
246 249 } lower;
247 250 struct {
248 251 __le32 status_error; /* ext status/error */
249 252 __le16 length0; /* length of buffer 0 */
250 253 __le16 vlan; /* VLAN tag */
251 254 } middle;
252 255 struct {
253 256 __le16 header_status;
254 257 __le16 length[3]; /* length of buffers 1-3 */
255 258 } upper;
256 259 __le64 reserved;
257 260 } wb; /* writeback */
258 261 };
259 262
260 263 /* Transmit Descriptor */
261 264 struct e1000_tx_desc {
262 265 __le64 buffer_addr; /* Address of the descriptor's data buffer */
263 266 union {
264 267 __le32 data;
265 268 struct {
266 269 __le16 length; /* Data buffer length */
267 270 u8 cso; /* Checksum offset */
268 271 u8 cmd; /* Descriptor control */
269 272 } flags;
270 273 } lower;
271 274 union {
272 275 __le32 data;
273 276 struct {
274 277 u8 status; /* Descriptor status */
275 278 u8 css; /* Checksum start */
276 279 __le16 special;
277 280 } fields;
278 281 } upper;
279 282 };
280 283
281 284 /* Offload Context Descriptor */
282 285 struct e1000_context_desc {
283 286 union {
284 287 __le32 ip_config;
285 288 struct {
286 289 u8 ipcss; /* IP checksum start */
287 290 u8 ipcso; /* IP checksum offset */
288 291 __le16 ipcse; /* IP checksum end */
289 292 } ip_fields;
290 293 } lower_setup;
291 294 union {
292 295 __le32 tcp_config;
293 296 struct {
294 297 u8 tucss; /* TCP checksum start */
295 298 u8 tucso; /* TCP checksum offset */
296 299 __le16 tucse; /* TCP checksum end */
297 300 } tcp_fields;
298 301 } upper_setup;
299 302 __le32 cmd_and_length;
300 303 union {
301 304 __le32 data;
302 305 struct {
303 306 u8 status; /* Descriptor status */
304 307 u8 hdr_len; /* Header length */
305 308 __le16 mss; /* Maximum segment size */
306 309 } fields;
307 310 } tcp_seg_setup;
308 311 };
309 312
310 313 /* Offload data descriptor */
311 314 struct e1000_data_desc {
312 315 __le64 buffer_addr; /* Address of the descriptor's buffer address */
313 316 union {
314 317 __le32 data;
315 318 struct {
316 319 __le16 length; /* Data buffer length */
317 320 u8 typ_len_ext;
318 321 u8 cmd;
319 322 } flags;
320 323 } lower;
321 324 union {
322 325 __le32 data;
323 326 struct {
324 327 u8 status; /* Descriptor status */
325 328 u8 popts; /* Packet Options */
326 329 __le16 special;
327 330 } fields;
328 331 } upper;
329 332 };
330 333
331 334 /* Statistics counters collected by the MAC */
332 335 struct e1000_hw_stats {
333 336 u64 crcerrs;
334 337 u64 algnerrc;
335 338 u64 symerrs;
336 339 u64 rxerrc;
337 340 u64 mpc;
338 341 u64 scc;
339 342 u64 ecol;
340 343 u64 mcc;
341 344 u64 latecol;
342 345 u64 colc;
343 346 u64 dc;
344 347 u64 tncrs;
345 348 u64 sec;
346 349 u64 cexterr;
347 350 u64 rlec;
348 351 u64 xonrxc;
349 352 u64 xontxc;
350 353 u64 xoffrxc;
351 354 u64 xofftxc;
352 355 u64 fcruc;
353 356 u64 prc64;
354 357 u64 prc127;
355 358 u64 prc255;
356 359 u64 prc511;
357 360 u64 prc1023;
358 361 u64 prc1522;
359 362 u64 gprc;
360 363 u64 bprc;
361 364 u64 mprc;
362 365 u64 gptc;
363 366 u64 gorc;
364 367 u64 gotc;
365 368 u64 rnbc;
366 369 u64 ruc;
367 370 u64 rfc;
368 371 u64 roc;
369 372 u64 rjc;
370 373 u64 mgprc;
371 374 u64 mgpdc;
372 375 u64 mgptc;
373 376 u64 tor;
374 377 u64 tot;
375 378 u64 tpr;
376 379 u64 tpt;
377 380 u64 ptc64;
378 381 u64 ptc127;
379 382 u64 ptc255;
380 383 u64 ptc511;
381 384 u64 ptc1023;
382 385 u64 ptc1522;
383 386 u64 mptc;
384 387 u64 bptc;
385 388 u64 tsctc;
386 389 u64 tsctfc;
387 390 u64 iac;
388 391 u64 icrxptc;
389 392 u64 icrxatc;
390 393 u64 ictxptc;
391 394 u64 ictxatc;
392 395 u64 ictxqec;
393 396 u64 ictxqmtc;
394 397 u64 icrxdmtc;
395 398 u64 icrxoc;
396 399 u64 cbtmpc;
397 400 u64 htdpmc;
398 401 u64 cbrdpc;
399 402 u64 cbrmpc;
400 403 u64 rpthc;
401 404 u64 hgptc;
402 405 u64 htcbdpc;
403 406 u64 hgorc;
404 407 u64 hgotc;
405 408 u64 lenerrs;
406 409 u64 scvpc;
407 410 u64 hrmpc;
408 411 u64 doosync;
409 412 };
410 413
411 414 struct e1000_phy_stats {
412 415 u32 idle_errors;
413 416 u32 receive_errors;
414 417 };
415 418
416 419 struct e1000_host_mng_dhcp_cookie {
417 420 u32 signature;
418 421 u8 status;
419 422 u8 reserved0;
420 423 u16 vlan_id;
421 424 u32 reserved1;
422 425 u16 reserved2;
423 426 u8 reserved3;
424 427 u8 checksum;
425 428 };
426 429
427 430 /* Host Interface "Rev 1" */
428 431 struct e1000_host_command_header {
429 432 u8 command_id;
430 433 u8 command_length;
431 434 u8 command_options;
432 435 u8 checksum;
433 436 };
434 437
435 438 #define E1000_HI_MAX_DATA_LENGTH 252
436 439 struct e1000_host_command_info {
437 440 struct e1000_host_command_header command_header;
438 441 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
439 442 };
440 443
441 444 /* Host Interface "Rev 2" */
442 445 struct e1000_host_mng_command_header {
443 446 u8 command_id;
444 447 u8 checksum;
445 448 u16 reserved1;
446 449 u16 reserved2;
447 450 u16 command_length;
448 451 };
449 452
450 453 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
451 454 struct e1000_host_mng_command_info {
452 455 struct e1000_host_mng_command_header command_header;
453 456 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
454 457 };
455 458
456 459 #include "igb_mac.h"
457 460 #include "igb_phy.h"
458 461 #include "igb_nvm.h"
459 462 #include "igb_manage.h"
460 463
461 464 struct e1000_mac_operations {
462 465 /* Function pointers for the MAC. */
463 466 s32 (*init_params)(struct e1000_hw *);
464 467 s32 (*id_led_init)(struct e1000_hw *);
465 468 s32 (*blink_led)(struct e1000_hw *);
466 469 s32 (*check_for_link)(struct e1000_hw *);
467 470 bool (*check_mng_mode)(struct e1000_hw *hw);
468 471 s32 (*cleanup_led)(struct e1000_hw *);
469 472 void (*clear_hw_cntrs)(struct e1000_hw *);
470 473 void (*clear_vfta)(struct e1000_hw *);
471 474 s32 (*get_bus_info)(struct e1000_hw *);
472 475 void (*set_lan_id)(struct e1000_hw *);
473 476 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
474 477 s32 (*led_on)(struct e1000_hw *);
475 478 s32 (*led_off)(struct e1000_hw *);
476 479 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
477 480 s32 (*reset_hw)(struct e1000_hw *);
478 481 s32 (*init_hw)(struct e1000_hw *);
479 482 void (*shutdown_serdes)(struct e1000_hw *);
480 483 s32 (*setup_link)(struct e1000_hw *);
481 484 s32 (*setup_physical_interface)(struct e1000_hw *);
482 485 s32 (*setup_led)(struct e1000_hw *);
483 486 void (*write_vfta)(struct e1000_hw *, u32, u32);
484 487 void (*mta_set)(struct e1000_hw *, u32);
485 488 void (*config_collision_dist)(struct e1000_hw *);
486 489 void (*rar_set)(struct e1000_hw *, u8*, u32);
487 490 s32 (*read_mac_addr)(struct e1000_hw *);
488 491 s32 (*validate_mdi_setting)(struct e1000_hw *);
489 492 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
490 493 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
491 494 struct e1000_host_mng_command_header *);
492 495 s32 (*mng_enable_host_if)(struct e1000_hw *);
493 496 s32 (*wait_autoneg)(struct e1000_hw *);
494 497 };
495 498
496 499 struct e1000_phy_operations {
497 500 s32 (*init_params)(struct e1000_hw *);
498 501 s32 (*acquire)(struct e1000_hw *);
499 502 s32 (*check_polarity)(struct e1000_hw *);
500 503 s32 (*check_reset_block)(struct e1000_hw *);
501 504 s32 (*commit)(struct e1000_hw *);
502 505 s32 (*force_speed_duplex)(struct e1000_hw *);
503 506 s32 (*get_cfg_done)(struct e1000_hw *hw);
504 507 s32 (*get_cable_length)(struct e1000_hw *);
505 508 s32 (*get_info)(struct e1000_hw *);
506 509 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
507 510 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
508 511 void (*release)(struct e1000_hw *);
509 512 s32 (*reset)(struct e1000_hw *);
510 513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
511 514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
512 515 s32 (*write_reg)(struct e1000_hw *, u32, u16);
513 516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
514 517 void (*power_up)(struct e1000_hw *);
515 518 void (*power_down)(struct e1000_hw *);
516 519 };
517 520
518 521 struct e1000_nvm_operations {
519 522 s32 (*init_params)(struct e1000_hw *);
520 523 s32 (*acquire)(struct e1000_hw *);
521 524 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
522 525 void (*release)(struct e1000_hw *);
523 526 void (*reload)(struct e1000_hw *);
524 527 s32 (*update)(struct e1000_hw *);
525 528 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
526 529 s32 (*validate)(struct e1000_hw *);
527 530 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
528 531 };
529 532
530 533 struct e1000_mac_info {
531 534 struct e1000_mac_operations ops;
532 535 u8 addr[6];
533 536 u8 perm_addr[6];
534 537
535 538 enum e1000_mac_type type;
536 539
537 540 u32 collision_delta;
538 541 u32 ledctl_default;
539 542 u32 ledctl_mode1;
540 543 u32 ledctl_mode2;
541 544 u32 mc_filter_type;
542 545 u32 tx_packet_delta;
543 546 u32 txcw;
544 547
545 548 u16 current_ifs_val;
546 549 u16 ifs_max_val;
547 550 u16 ifs_min_val;
548 551 u16 ifs_ratio;
549 552 u16 ifs_step_size;
550 553 u16 mta_reg_count;
551 554 u16 uta_reg_count;
552 555
553 556 /* Maximum size of the MTA register table in all supported adapters */
554 557 #define MAX_MTA_REG 128
555 558 u32 mta_shadow[MAX_MTA_REG];
556 559 u16 rar_entry_count;
557 560
558 561 u8 forced_speed_duplex;
559 562
560 563 bool adaptive_ifs;
561 564 bool arc_subsystem_valid;
562 565 bool asf_firmware_present;
563 566 bool autoneg;
564 567 bool autoneg_failed;
565 568 bool get_link_status;
566 569 bool in_ifs_mode;
567 570 enum e1000_serdes_link_state serdes_link_state;
568 571 bool serdes_has_link;
569 572 bool tx_pkt_filtering;
570 573 };
571 574
572 575 struct e1000_phy_info {
573 576 struct e1000_phy_operations ops;
574 577 enum e1000_phy_type type;
575 578
576 579 enum e1000_1000t_rx_status local_rx;
577 580 enum e1000_1000t_rx_status remote_rx;
578 581 enum e1000_ms_type ms_type;
579 582 enum e1000_ms_type original_ms_type;
580 583 enum e1000_rev_polarity cable_polarity;
581 584 enum e1000_smart_speed smart_speed;
582 585
583 586 u32 addr;
584 587 u32 id;
585 588 u32 reset_delay_us; /* in usec */
586 589 u32 revision;
587 590
588 591 enum e1000_media_type media_type;
589 592
590 593 u16 autoneg_advertised;
591 594 u16 autoneg_mask;
592 595 u16 cable_length;
593 596 u16 max_cable_length;
594 597 u16 min_cable_length;
595 598
596 599 u8 mdix;
597 600
598 601 bool disable_polarity_correction;
599 602 bool is_mdix;
600 603 bool polarity_correction;
601 604 bool reset_disable;
602 605 bool speed_downgraded;
603 606 bool autoneg_wait_to_complete;
604 607 };
605 608
606 609 struct e1000_nvm_info {
607 610 struct e1000_nvm_operations ops;
608 611 enum e1000_nvm_type type;
609 612 enum e1000_nvm_override override;
610 613
611 614 u32 flash_bank_size;
612 615 u32 flash_base_addr;
613 616
614 617 u16 word_size;
615 618 u16 delay_usec;
616 619 u16 address_bits;
617 620 u16 opcode_bits;
618 621 u16 page_size;
619 622 };
620 623
621 624 struct e1000_bus_info {
622 625 enum e1000_bus_type type;
623 626 enum e1000_bus_speed speed;
624 627 enum e1000_bus_width width;
625 628
626 629 u16 func;
627 630 u16 pci_cmd_word;
628 631 };
629 632
630 633 struct e1000_fc_info {
631 634 u32 high_water; /* Flow control high-water mark */
632 635 u32 low_water; /* Flow control low-water mark */
|
↓ open down ↓ |
541 lines elided |
↑ open up ↑ |
633 636 u16 pause_time; /* Flow control pause timer */
634 637 bool send_xon; /* Flow control send XON */
635 638 bool strict_ieee; /* Strict IEEE mode */
636 639 enum e1000_fc_mode current_mode; /* FC mode in effect */
637 640 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
638 641 };
639 642
640 643 struct e1000_dev_spec_82575 {
641 644 bool sgmii_active;
642 645 bool global_device_reset;
646 + int eee_disable;
643 647 };
644 648
645 649 struct e1000_dev_spec_vf {
646 650 u32 vf_number;
647 651 u32 v2p_mailbox;
648 652 };
649 653
650 654 struct e1000_hw {
651 655 void *back;
652 656
653 657 u8 *hw_addr;
654 658 u8 *flash_address;
655 659 unsigned long io_base;
656 660
657 661 struct e1000_mac_info mac;
658 662 struct e1000_fc_info fc;
659 663 struct e1000_phy_info phy;
660 664 struct e1000_nvm_info nvm;
661 665 struct e1000_bus_info bus;
662 666 struct e1000_host_mng_dhcp_cookie mng_cookie;
663 667
664 668 union {
665 669 struct e1000_dev_spec_82575 _82575;
666 670 struct e1000_dev_spec_vf vf;
667 671 } dev_spec;
668 672
669 673 u16 device_id;
670 674 u16 subsystem_vendor_id;
671 675 u16 subsystem_device_id;
672 676 u16 vendor_id;
673 677
674 678 u8 revision_id;
675 679 };
676 680
677 681 #include "igb_82575.h"
678 682
679 683 /* These functions must be implemented by drivers */
680 684 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
681 685 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
682 686
683 687 #ifdef __cplusplus
684 688 }
685 689 #endif
686 690
687 691 #endif /* _IGB_HW_H */
|
↓ open down ↓ |
35 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX