1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.446.2.1 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_HW_H
33 #define _IGB_HW_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #include "igb_osdep.h"
40 #include "igb_regs.h"
41 #include "igb_defines.h"
42
43 struct e1000_hw;
44
45 #define E1000_DEV_ID_82576 0x10C9
46 #define E1000_DEV_ID_82576_FIBER 0x10E6
47 #define E1000_DEV_ID_82576_SERDES 0x10E7
48 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
49 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
50 #define E1000_DEV_ID_82576_NS 0x150A
51 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
52 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
53 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
54 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
55 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
56 #define E1000_DEV_ID_82580_COPPER 0x150E
57 #define E1000_DEV_ID_82580_FIBER 0x150F
58 #define E1000_DEV_ID_82580_SERDES 0x1510
59 #define E1000_DEV_ID_82580_SGMII 0x1511
60 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
61 #define E1000_DEV_ID_I350_COPPER 0x1521
62
63 #define E1000_REVISION_0 0
64 #define E1000_REVISION_1 1
65 #define E1000_REVISION_2 2
66 #define E1000_REVISION_3 3
67 #define E1000_REVISION_4 4
68
69 #define E1000_FUNC_0 0
70 #define E1000_FUNC_1 1
71 #define E1000_FUNC_2 2
72 #define E1000_FUNC_3 3
73
74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
76 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
77 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
78
79 enum e1000_mac_type {
80 e1000_undefined = 0,
81 e1000_82575,
82 e1000_82576,
83 e1000_82580,
84 e1000_i350,
85 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
86 };
87
88 enum e1000_media_type {
89 e1000_media_type_unknown = 0,
90 e1000_media_type_copper = 1,
91 e1000_media_type_fiber = 2,
92 e1000_media_type_internal_serdes = 3,
93 e1000_num_media_types
94 };
95
96 enum e1000_nvm_type {
97 e1000_nvm_unknown = 0,
98 e1000_nvm_none,
99 e1000_nvm_eeprom_spi,
100 e1000_nvm_eeprom_microwire,
101 e1000_nvm_flash_hw,
102 e1000_nvm_flash_sw
103 };
104
105 enum e1000_nvm_override {
106 e1000_nvm_override_none = 0,
107 e1000_nvm_override_spi_small,
108 e1000_nvm_override_spi_large,
109 e1000_nvm_override_microwire_small,
110 e1000_nvm_override_microwire_large
111 };
112
113 enum e1000_phy_type {
114 e1000_phy_unknown = 0,
115 e1000_phy_none,
116 e1000_phy_m88,
117 e1000_phy_igp,
118 e1000_phy_igp_2,
119 e1000_phy_gg82563,
120 e1000_phy_igp_3,
121 e1000_phy_ife,
122 e1000_phy_82580,
123 e1000_phy_vf
124 };
125
126 enum e1000_bus_type {
127 e1000_bus_type_unknown = 0,
128 e1000_bus_type_pci,
129 e1000_bus_type_pcix,
130 e1000_bus_type_pci_express,
131 e1000_bus_type_reserved
132 };
133
134 enum e1000_bus_speed {
135 e1000_bus_speed_unknown = 0,
136 e1000_bus_speed_33,
137 e1000_bus_speed_66,
138 e1000_bus_speed_100,
139 e1000_bus_speed_120,
140 e1000_bus_speed_133,
141 e1000_bus_speed_2500,
142 e1000_bus_speed_5000,
143 e1000_bus_speed_reserved
144 };
145
146 enum e1000_bus_width {
147 e1000_bus_width_unknown = 0,
148 e1000_bus_width_pcie_x1,
149 e1000_bus_width_pcie_x2,
150 e1000_bus_width_pcie_x4 = 4,
151 e1000_bus_width_pcie_x8 = 8,
152 e1000_bus_width_32,
153 e1000_bus_width_64,
154 e1000_bus_width_reserved
155 };
156
157 enum e1000_1000t_rx_status {
158 e1000_1000t_rx_status_not_ok = 0,
159 e1000_1000t_rx_status_ok,
160 e1000_1000t_rx_status_undefined = 0xFF
161 };
162
163 enum e1000_rev_polarity {
164 e1000_rev_polarity_normal = 0,
165 e1000_rev_polarity_reversed,
166 e1000_rev_polarity_undefined = 0xFF
167 };
168
169 enum e1000_fc_mode {
170 e1000_fc_none = 0,
171 e1000_fc_rx_pause,
172 e1000_fc_tx_pause,
173 e1000_fc_full,
174 e1000_fc_default = 0xFF
175 };
176
177 enum e1000_ms_type {
178 e1000_ms_hw_default = 0,
179 e1000_ms_force_master,
180 e1000_ms_force_slave,
181 e1000_ms_auto
182 };
183
184 enum e1000_smart_speed {
185 e1000_smart_speed_default = 0,
186 e1000_smart_speed_on,
187 e1000_smart_speed_off
188 };
189
190 enum e1000_serdes_link_state {
191 e1000_serdes_link_down = 0,
192 e1000_serdes_link_autoneg_progress,
193 e1000_serdes_link_autoneg_complete,
194 e1000_serdes_link_forced_up
195 };
196
197 /* Receive Descriptor */
198 struct e1000_rx_desc {
199 __le64 buffer_addr; /* Address of the descriptor's data buffer */
200 __le16 length; /* Length of data DMAed into data buffer */
201 __le16 csum; /* Packet checksum */
202 u8 status; /* Descriptor status */
203 u8 errors; /* Descriptor Errors */
204 __le16 special;
205 };
206
207 /* Receive Descriptor - Extended */
208 union e1000_rx_desc_extended {
209 struct {
210 __le64 buffer_addr;
211 __le64 reserved;
212 } read;
213 struct {
214 struct {
215 __le32 mrq; /* Multiple Rx Queues */
216 union {
217 __le32 rss; /* RSS Hash */
218 struct {
219 __le16 ip_id; /* IP id */
220 __le16 csum; /* Packet Checksum */
221 } csum_ip;
222 } hi_dword;
223 } lower;
224 struct {
225 __le32 status_error; /* ext status/error */
226 __le16 length;
227 __le16 vlan; /* VLAN tag */
228 } upper;
229 } wb; /* writeback */
230 };
231
232 #define MAX_PS_BUFFERS 4
233 /* Receive Descriptor - Packet Split */
234 union e1000_rx_desc_packet_split {
235 struct {
236 /* one buffer for protocol header(s), three data buffers */
237 __le64 buffer_addr[MAX_PS_BUFFERS];
238 } read;
239 struct {
240 struct {
241 __le32 mrq; /* Multiple Rx Queues */
242 union {
243 __le32 rss; /* RSS Hash */
244 struct {
245 __le16 ip_id; /* IP id */
246 __le16 csum; /* Packet Checksum */
247 } csum_ip;
248 } hi_dword;
249 } lower;
250 struct {
251 __le32 status_error; /* ext status/error */
252 __le16 length0; /* length of buffer 0 */
253 __le16 vlan; /* VLAN tag */
254 } middle;
255 struct {
256 __le16 header_status;
257 __le16 length[3]; /* length of buffers 1-3 */
258 } upper;
259 __le64 reserved;
260 } wb; /* writeback */
261 };
262
263 /* Transmit Descriptor */
264 struct e1000_tx_desc {
265 __le64 buffer_addr; /* Address of the descriptor's data buffer */
266 union {
267 __le32 data;
268 struct {
269 __le16 length; /* Data buffer length */
270 u8 cso; /* Checksum offset */
271 u8 cmd; /* Descriptor control */
272 } flags;
273 } lower;
274 union {
275 __le32 data;
276 struct {
277 u8 status; /* Descriptor status */
278 u8 css; /* Checksum start */
279 __le16 special;
280 } fields;
281 } upper;
282 };
283
284 /* Offload Context Descriptor */
285 struct e1000_context_desc {
286 union {
287 __le32 ip_config;
288 struct {
289 u8 ipcss; /* IP checksum start */
290 u8 ipcso; /* IP checksum offset */
291 __le16 ipcse; /* IP checksum end */
292 } ip_fields;
293 } lower_setup;
294 union {
295 __le32 tcp_config;
296 struct {
297 u8 tucss; /* TCP checksum start */
298 u8 tucso; /* TCP checksum offset */
299 __le16 tucse; /* TCP checksum end */
300 } tcp_fields;
301 } upper_setup;
302 __le32 cmd_and_length;
303 union {
304 __le32 data;
305 struct {
306 u8 status; /* Descriptor status */
307 u8 hdr_len; /* Header length */
308 __le16 mss; /* Maximum segment size */
309 } fields;
310 } tcp_seg_setup;
311 };
312
313 /* Offload data descriptor */
314 struct e1000_data_desc {
315 __le64 buffer_addr; /* Address of the descriptor's buffer address */
316 union {
317 __le32 data;
318 struct {
319 __le16 length; /* Data buffer length */
320 u8 typ_len_ext;
321 u8 cmd;
322 } flags;
323 } lower;
324 union {
325 __le32 data;
326 struct {
327 u8 status; /* Descriptor status */
328 u8 popts; /* Packet Options */
329 __le16 special;
330 } fields;
331 } upper;
332 };
333
334 /* Statistics counters collected by the MAC */
335 struct e1000_hw_stats {
336 u64 crcerrs;
337 u64 algnerrc;
338 u64 symerrs;
339 u64 rxerrc;
340 u64 mpc;
341 u64 scc;
342 u64 ecol;
343 u64 mcc;
344 u64 latecol;
345 u64 colc;
346 u64 dc;
347 u64 tncrs;
348 u64 sec;
349 u64 cexterr;
350 u64 rlec;
351 u64 xonrxc;
352 u64 xontxc;
353 u64 xoffrxc;
354 u64 xofftxc;
355 u64 fcruc;
356 u64 prc64;
357 u64 prc127;
358 u64 prc255;
359 u64 prc511;
360 u64 prc1023;
361 u64 prc1522;
362 u64 gprc;
363 u64 bprc;
364 u64 mprc;
365 u64 gptc;
366 u64 gorc;
367 u64 gotc;
368 u64 rnbc;
369 u64 ruc;
370 u64 rfc;
371 u64 roc;
372 u64 rjc;
373 u64 mgprc;
374 u64 mgpdc;
375 u64 mgptc;
376 u64 tor;
377 u64 tot;
378 u64 tpr;
379 u64 tpt;
380 u64 ptc64;
381 u64 ptc127;
382 u64 ptc255;
383 u64 ptc511;
384 u64 ptc1023;
385 u64 ptc1522;
386 u64 mptc;
387 u64 bptc;
388 u64 tsctc;
389 u64 tsctfc;
390 u64 iac;
391 u64 icrxptc;
392 u64 icrxatc;
393 u64 ictxptc;
394 u64 ictxatc;
395 u64 ictxqec;
396 u64 ictxqmtc;
397 u64 icrxdmtc;
398 u64 icrxoc;
399 u64 cbtmpc;
400 u64 htdpmc;
401 u64 cbrdpc;
402 u64 cbrmpc;
403 u64 rpthc;
404 u64 hgptc;
405 u64 htcbdpc;
406 u64 hgorc;
407 u64 hgotc;
408 u64 lenerrs;
409 u64 scvpc;
410 u64 hrmpc;
411 u64 doosync;
412 };
413
414 struct e1000_phy_stats {
415 u32 idle_errors;
416 u32 receive_errors;
417 };
418
419 struct e1000_host_mng_dhcp_cookie {
420 u32 signature;
421 u8 status;
422 u8 reserved0;
423 u16 vlan_id;
424 u32 reserved1;
425 u16 reserved2;
426 u8 reserved3;
427 u8 checksum;
428 };
429
430 /* Host Interface "Rev 1" */
431 struct e1000_host_command_header {
432 u8 command_id;
433 u8 command_length;
434 u8 command_options;
435 u8 checksum;
436 };
437
438 #define E1000_HI_MAX_DATA_LENGTH 252
439 struct e1000_host_command_info {
440 struct e1000_host_command_header command_header;
441 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
442 };
443
444 /* Host Interface "Rev 2" */
445 struct e1000_host_mng_command_header {
446 u8 command_id;
447 u8 checksum;
448 u16 reserved1;
449 u16 reserved2;
450 u16 command_length;
451 };
452
453 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
454 struct e1000_host_mng_command_info {
455 struct e1000_host_mng_command_header command_header;
456 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
457 };
458
459 #include "igb_mac.h"
460 #include "igb_phy.h"
461 #include "igb_nvm.h"
462 #include "igb_manage.h"
463
464 struct e1000_mac_operations {
465 /* Function pointers for the MAC. */
466 s32 (*init_params)(struct e1000_hw *);
467 s32 (*id_led_init)(struct e1000_hw *);
468 s32 (*blink_led)(struct e1000_hw *);
469 s32 (*check_for_link)(struct e1000_hw *);
470 bool (*check_mng_mode)(struct e1000_hw *hw);
471 s32 (*cleanup_led)(struct e1000_hw *);
472 void (*clear_hw_cntrs)(struct e1000_hw *);
473 void (*clear_vfta)(struct e1000_hw *);
474 s32 (*get_bus_info)(struct e1000_hw *);
475 void (*set_lan_id)(struct e1000_hw *);
476 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
477 s32 (*led_on)(struct e1000_hw *);
478 s32 (*led_off)(struct e1000_hw *);
479 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
480 s32 (*reset_hw)(struct e1000_hw *);
481 s32 (*init_hw)(struct e1000_hw *);
482 void (*shutdown_serdes)(struct e1000_hw *);
483 s32 (*setup_link)(struct e1000_hw *);
484 s32 (*setup_physical_interface)(struct e1000_hw *);
485 s32 (*setup_led)(struct e1000_hw *);
486 void (*write_vfta)(struct e1000_hw *, u32, u32);
487 void (*mta_set)(struct e1000_hw *, u32);
488 void (*config_collision_dist)(struct e1000_hw *);
489 void (*rar_set)(struct e1000_hw *, u8*, u32);
490 s32 (*read_mac_addr)(struct e1000_hw *);
491 s32 (*validate_mdi_setting)(struct e1000_hw *);
492 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
493 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
494 struct e1000_host_mng_command_header *);
495 s32 (*mng_enable_host_if)(struct e1000_hw *);
496 s32 (*wait_autoneg)(struct e1000_hw *);
497 };
498
499 struct e1000_phy_operations {
500 s32 (*init_params)(struct e1000_hw *);
501 s32 (*acquire)(struct e1000_hw *);
502 s32 (*check_polarity)(struct e1000_hw *);
503 s32 (*check_reset_block)(struct e1000_hw *);
504 s32 (*commit)(struct e1000_hw *);
505 s32 (*force_speed_duplex)(struct e1000_hw *);
506 s32 (*get_cfg_done)(struct e1000_hw *hw);
507 s32 (*get_cable_length)(struct e1000_hw *);
508 s32 (*get_info)(struct e1000_hw *);
509 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
510 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
511 void (*release)(struct e1000_hw *);
512 s32 (*reset)(struct e1000_hw *);
513 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
514 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
515 s32 (*write_reg)(struct e1000_hw *, u32, u16);
516 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
517 void (*power_up)(struct e1000_hw *);
518 void (*power_down)(struct e1000_hw *);
519 };
520
521 struct e1000_nvm_operations {
522 s32 (*init_params)(struct e1000_hw *);
523 s32 (*acquire)(struct e1000_hw *);
524 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
525 void (*release)(struct e1000_hw *);
526 void (*reload)(struct e1000_hw *);
527 s32 (*update)(struct e1000_hw *);
528 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
529 s32 (*validate)(struct e1000_hw *);
530 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
531 };
532
533 struct e1000_mac_info {
534 struct e1000_mac_operations ops;
535 u8 addr[6];
536 u8 perm_addr[6];
537
538 enum e1000_mac_type type;
539
540 u32 collision_delta;
541 u32 ledctl_default;
542 u32 ledctl_mode1;
543 u32 ledctl_mode2;
544 u32 mc_filter_type;
545 u32 tx_packet_delta;
546 u32 txcw;
547
548 u16 current_ifs_val;
549 u16 ifs_max_val;
550 u16 ifs_min_val;
551 u16 ifs_ratio;
552 u16 ifs_step_size;
553 u16 mta_reg_count;
554 u16 uta_reg_count;
555
556 /* Maximum size of the MTA register table in all supported adapters */
557 #define MAX_MTA_REG 128
558 u32 mta_shadow[MAX_MTA_REG];
559 u16 rar_entry_count;
560
561 u8 forced_speed_duplex;
562
563 bool adaptive_ifs;
564 bool arc_subsystem_valid;
565 bool asf_firmware_present;
566 bool autoneg;
567 bool autoneg_failed;
568 bool get_link_status;
569 bool in_ifs_mode;
570 enum e1000_serdes_link_state serdes_link_state;
571 bool serdes_has_link;
572 bool tx_pkt_filtering;
573 };
574
575 struct e1000_phy_info {
576 struct e1000_phy_operations ops;
577 enum e1000_phy_type type;
578
579 enum e1000_1000t_rx_status local_rx;
580 enum e1000_1000t_rx_status remote_rx;
581 enum e1000_ms_type ms_type;
582 enum e1000_ms_type original_ms_type;
583 enum e1000_rev_polarity cable_polarity;
584 enum e1000_smart_speed smart_speed;
585
586 u32 addr;
587 u32 id;
588 u32 reset_delay_us; /* in usec */
589 u32 revision;
590
591 enum e1000_media_type media_type;
592
593 u16 autoneg_advertised;
594 u16 autoneg_mask;
595 u16 cable_length;
596 u16 max_cable_length;
597 u16 min_cable_length;
598
599 u8 mdix;
600
601 bool disable_polarity_correction;
602 bool is_mdix;
603 bool polarity_correction;
604 bool reset_disable;
605 bool speed_downgraded;
606 bool autoneg_wait_to_complete;
607 };
608
609 struct e1000_nvm_info {
610 struct e1000_nvm_operations ops;
611 enum e1000_nvm_type type;
612 enum e1000_nvm_override override;
613
614 u32 flash_bank_size;
615 u32 flash_base_addr;
616
617 u16 word_size;
618 u16 delay_usec;
619 u16 address_bits;
620 u16 opcode_bits;
621 u16 page_size;
622 };
623
624 struct e1000_bus_info {
625 enum e1000_bus_type type;
626 enum e1000_bus_speed speed;
627 enum e1000_bus_width width;
628
629 u16 func;
630 u16 pci_cmd_word;
631 };
632
633 struct e1000_fc_info {
634 u32 high_water; /* Flow control high-water mark */
635 u32 low_water; /* Flow control low-water mark */
636 u16 pause_time; /* Flow control pause timer */
637 bool send_xon; /* Flow control send XON */
638 bool strict_ieee; /* Strict IEEE mode */
639 enum e1000_fc_mode current_mode; /* FC mode in effect */
640 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
641 };
642
643 struct e1000_dev_spec_82575 {
644 bool sgmii_active;
645 bool global_device_reset;
646 int eee_disable;
647 };
648
649 struct e1000_dev_spec_vf {
650 u32 vf_number;
651 u32 v2p_mailbox;
652 };
653
654 struct e1000_hw {
655 void *back;
656
657 u8 *hw_addr;
658 u8 *flash_address;
659 unsigned long io_base;
660
661 struct e1000_mac_info mac;
662 struct e1000_fc_info fc;
663 struct e1000_phy_info phy;
664 struct e1000_nvm_info nvm;
665 struct e1000_bus_info bus;
666 struct e1000_host_mng_dhcp_cookie mng_cookie;
667
668 union {
669 struct e1000_dev_spec_82575 _82575;
670 struct e1000_dev_spec_vf vf;
671 } dev_spec;
672
673 u16 device_id;
674 u16 subsystem_vendor_id;
675 u16 subsystem_device_id;
676 u16 vendor_id;
677
678 u8 revision_id;
679 };
680
681 #include "igb_82575.h"
682
683 /* These functions must be implemented by drivers */
684 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
685 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
686
687 #ifdef __cplusplus
688 }
689 #endif
690
691 #endif /* _IGB_HW_H */