1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.446.2.1 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_HW_H
33 #define _IGB_HW_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #include "igb_osdep.h"
40 #include "igb_regs.h"
41 #include "igb_defines.h"
42
43 struct e1000_hw;
44
45 #define E1000_DEV_ID_82576 0x10C9
46 #define E1000_DEV_ID_82576_FIBER 0x10E6
47 #define E1000_DEV_ID_82576_SERDES 0x10E7
48 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
49 #define E1000_DEV_ID_82576_NS 0x150A
50 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
51 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
52 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
53 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
54 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
55 #define E1000_DEV_ID_82580_COPPER 0x150E
56 #define E1000_DEV_ID_82580_FIBER 0x150F
57 #define E1000_DEV_ID_82580_SERDES 0x1510
58 #define E1000_DEV_ID_82580_SGMII 0x1511
59 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
60
61 #define E1000_REVISION_0 0
62 #define E1000_REVISION_1 1
63 #define E1000_REVISION_2 2
64 #define E1000_REVISION_3 3
65 #define E1000_REVISION_4 4
66
67 #define E1000_FUNC_0 0
68 #define E1000_FUNC_1 1
69 #define E1000_FUNC_2 2
70 #define E1000_FUNC_3 3
71
72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
73 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
76
77 enum e1000_mac_type {
78 e1000_undefined = 0,
79 e1000_82575,
80 e1000_82576,
81 e1000_82580,
82 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
83 };
84
85 enum e1000_media_type {
86 e1000_media_type_unknown = 0,
87 e1000_media_type_copper = 1,
88 e1000_media_type_fiber = 2,
89 e1000_media_type_internal_serdes = 3,
90 e1000_num_media_types
91 };
92
93 enum e1000_nvm_type {
94 e1000_nvm_unknown = 0,
95 e1000_nvm_none,
96 e1000_nvm_eeprom_spi,
97 e1000_nvm_eeprom_microwire,
98 e1000_nvm_flash_hw,
99 e1000_nvm_flash_sw
100 };
101
102 enum e1000_nvm_override {
103 e1000_nvm_override_none = 0,
104 e1000_nvm_override_spi_small,
105 e1000_nvm_override_spi_large,
106 e1000_nvm_override_microwire_small,
107 e1000_nvm_override_microwire_large
108 };
109
110 enum e1000_phy_type {
111 e1000_phy_unknown = 0,
112 e1000_phy_none,
113 e1000_phy_m88,
114 e1000_phy_igp,
115 e1000_phy_igp_2,
116 e1000_phy_gg82563,
117 e1000_phy_igp_3,
118 e1000_phy_ife,
119 e1000_phy_82580,
120 e1000_phy_vf
121 };
122
123 enum e1000_bus_type {
124 e1000_bus_type_unknown = 0,
125 e1000_bus_type_pci,
126 e1000_bus_type_pcix,
127 e1000_bus_type_pci_express,
128 e1000_bus_type_reserved
129 };
130
131 enum e1000_bus_speed {
132 e1000_bus_speed_unknown = 0,
133 e1000_bus_speed_33,
134 e1000_bus_speed_66,
135 e1000_bus_speed_100,
136 e1000_bus_speed_120,
137 e1000_bus_speed_133,
138 e1000_bus_speed_2500,
139 e1000_bus_speed_5000,
140 e1000_bus_speed_reserved
141 };
142
143 enum e1000_bus_width {
144 e1000_bus_width_unknown = 0,
145 e1000_bus_width_pcie_x1,
146 e1000_bus_width_pcie_x2,
147 e1000_bus_width_pcie_x4 = 4,
148 e1000_bus_width_pcie_x8 = 8,
149 e1000_bus_width_32,
150 e1000_bus_width_64,
151 e1000_bus_width_reserved
152 };
153
154 enum e1000_1000t_rx_status {
155 e1000_1000t_rx_status_not_ok = 0,
156 e1000_1000t_rx_status_ok,
157 e1000_1000t_rx_status_undefined = 0xFF
158 };
159
160 enum e1000_rev_polarity {
161 e1000_rev_polarity_normal = 0,
162 e1000_rev_polarity_reversed,
163 e1000_rev_polarity_undefined = 0xFF
164 };
165
166 enum e1000_fc_mode {
167 e1000_fc_none = 0,
168 e1000_fc_rx_pause,
169 e1000_fc_tx_pause,
170 e1000_fc_full,
171 e1000_fc_default = 0xFF
172 };
173
174 enum e1000_ms_type {
175 e1000_ms_hw_default = 0,
176 e1000_ms_force_master,
177 e1000_ms_force_slave,
178 e1000_ms_auto
179 };
180
181 enum e1000_smart_speed {
182 e1000_smart_speed_default = 0,
183 e1000_smart_speed_on,
184 e1000_smart_speed_off
185 };
186
187 enum e1000_serdes_link_state {
188 e1000_serdes_link_down = 0,
189 e1000_serdes_link_autoneg_progress,
190 e1000_serdes_link_autoneg_complete,
191 e1000_serdes_link_forced_up
192 };
193
194 /* Receive Descriptor */
195 struct e1000_rx_desc {
196 __le64 buffer_addr; /* Address of the descriptor's data buffer */
197 __le16 length; /* Length of data DMAed into data buffer */
198 __le16 csum; /* Packet checksum */
199 u8 status; /* Descriptor status */
200 u8 errors; /* Descriptor Errors */
201 __le16 special;
202 };
203
204 /* Receive Descriptor - Extended */
205 union e1000_rx_desc_extended {
206 struct {
207 __le64 buffer_addr;
208 __le64 reserved;
209 } read;
210 struct {
211 struct {
212 __le32 mrq; /* Multiple Rx Queues */
213 union {
214 __le32 rss; /* RSS Hash */
215 struct {
216 __le16 ip_id; /* IP id */
217 __le16 csum; /* Packet Checksum */
218 } csum_ip;
219 } hi_dword;
220 } lower;
221 struct {
222 __le32 status_error; /* ext status/error */
223 __le16 length;
224 __le16 vlan; /* VLAN tag */
225 } upper;
226 } wb; /* writeback */
227 };
228
229 #define MAX_PS_BUFFERS 4
230 /* Receive Descriptor - Packet Split */
231 union e1000_rx_desc_packet_split {
232 struct {
233 /* one buffer for protocol header(s), three data buffers */
234 __le64 buffer_addr[MAX_PS_BUFFERS];
235 } read;
236 struct {
237 struct {
238 __le32 mrq; /* Multiple Rx Queues */
239 union {
240 __le32 rss; /* RSS Hash */
241 struct {
242 __le16 ip_id; /* IP id */
243 __le16 csum; /* Packet Checksum */
244 } csum_ip;
245 } hi_dword;
246 } lower;
247 struct {
248 __le32 status_error; /* ext status/error */
249 __le16 length0; /* length of buffer 0 */
250 __le16 vlan; /* VLAN tag */
251 } middle;
252 struct {
253 __le16 header_status;
254 __le16 length[3]; /* length of buffers 1-3 */
255 } upper;
256 __le64 reserved;
257 } wb; /* writeback */
258 };
259
260 /* Transmit Descriptor */
261 struct e1000_tx_desc {
262 __le64 buffer_addr; /* Address of the descriptor's data buffer */
263 union {
264 __le32 data;
265 struct {
266 __le16 length; /* Data buffer length */
267 u8 cso; /* Checksum offset */
268 u8 cmd; /* Descriptor control */
269 } flags;
270 } lower;
271 union {
272 __le32 data;
273 struct {
274 u8 status; /* Descriptor status */
275 u8 css; /* Checksum start */
276 __le16 special;
277 } fields;
278 } upper;
279 };
280
281 /* Offload Context Descriptor */
282 struct e1000_context_desc {
283 union {
284 __le32 ip_config;
285 struct {
286 u8 ipcss; /* IP checksum start */
287 u8 ipcso; /* IP checksum offset */
288 __le16 ipcse; /* IP checksum end */
289 } ip_fields;
290 } lower_setup;
291 union {
292 __le32 tcp_config;
293 struct {
294 u8 tucss; /* TCP checksum start */
295 u8 tucso; /* TCP checksum offset */
296 __le16 tucse; /* TCP checksum end */
297 } tcp_fields;
298 } upper_setup;
299 __le32 cmd_and_length;
300 union {
301 __le32 data;
302 struct {
303 u8 status; /* Descriptor status */
304 u8 hdr_len; /* Header length */
305 __le16 mss; /* Maximum segment size */
306 } fields;
307 } tcp_seg_setup;
308 };
309
310 /* Offload data descriptor */
311 struct e1000_data_desc {
312 __le64 buffer_addr; /* Address of the descriptor's buffer address */
313 union {
314 __le32 data;
315 struct {
316 __le16 length; /* Data buffer length */
317 u8 typ_len_ext;
318 u8 cmd;
319 } flags;
320 } lower;
321 union {
322 __le32 data;
323 struct {
324 u8 status; /* Descriptor status */
325 u8 popts; /* Packet Options */
326 __le16 special;
327 } fields;
328 } upper;
329 };
330
331 /* Statistics counters collected by the MAC */
332 struct e1000_hw_stats {
333 u64 crcerrs;
334 u64 algnerrc;
335 u64 symerrs;
336 u64 rxerrc;
337 u64 mpc;
338 u64 scc;
339 u64 ecol;
340 u64 mcc;
341 u64 latecol;
342 u64 colc;
343 u64 dc;
344 u64 tncrs;
345 u64 sec;
346 u64 cexterr;
347 u64 rlec;
348 u64 xonrxc;
349 u64 xontxc;
350 u64 xoffrxc;
351 u64 xofftxc;
352 u64 fcruc;
353 u64 prc64;
354 u64 prc127;
355 u64 prc255;
356 u64 prc511;
357 u64 prc1023;
358 u64 prc1522;
359 u64 gprc;
360 u64 bprc;
361 u64 mprc;
362 u64 gptc;
363 u64 gorc;
364 u64 gotc;
365 u64 rnbc;
366 u64 ruc;
367 u64 rfc;
368 u64 roc;
369 u64 rjc;
370 u64 mgprc;
371 u64 mgpdc;
372 u64 mgptc;
373 u64 tor;
374 u64 tot;
375 u64 tpr;
376 u64 tpt;
377 u64 ptc64;
378 u64 ptc127;
379 u64 ptc255;
380 u64 ptc511;
381 u64 ptc1023;
382 u64 ptc1522;
383 u64 mptc;
384 u64 bptc;
385 u64 tsctc;
386 u64 tsctfc;
387 u64 iac;
388 u64 icrxptc;
389 u64 icrxatc;
390 u64 ictxptc;
391 u64 ictxatc;
392 u64 ictxqec;
393 u64 ictxqmtc;
394 u64 icrxdmtc;
395 u64 icrxoc;
396 u64 cbtmpc;
397 u64 htdpmc;
398 u64 cbrdpc;
399 u64 cbrmpc;
400 u64 rpthc;
401 u64 hgptc;
402 u64 htcbdpc;
403 u64 hgorc;
404 u64 hgotc;
405 u64 lenerrs;
406 u64 scvpc;
407 u64 hrmpc;
408 u64 doosync;
409 };
410
411 struct e1000_phy_stats {
412 u32 idle_errors;
413 u32 receive_errors;
414 };
415
416 struct e1000_host_mng_dhcp_cookie {
417 u32 signature;
418 u8 status;
419 u8 reserved0;
420 u16 vlan_id;
421 u32 reserved1;
422 u16 reserved2;
423 u8 reserved3;
424 u8 checksum;
425 };
426
427 /* Host Interface "Rev 1" */
428 struct e1000_host_command_header {
429 u8 command_id;
430 u8 command_length;
431 u8 command_options;
432 u8 checksum;
433 };
434
435 #define E1000_HI_MAX_DATA_LENGTH 252
436 struct e1000_host_command_info {
437 struct e1000_host_command_header command_header;
438 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
439 };
440
441 /* Host Interface "Rev 2" */
442 struct e1000_host_mng_command_header {
443 u8 command_id;
444 u8 checksum;
445 u16 reserved1;
446 u16 reserved2;
447 u16 command_length;
448 };
449
450 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
451 struct e1000_host_mng_command_info {
452 struct e1000_host_mng_command_header command_header;
453 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
454 };
455
456 #include "igb_mac.h"
457 #include "igb_phy.h"
458 #include "igb_nvm.h"
459 #include "igb_manage.h"
460
461 struct e1000_mac_operations {
462 /* Function pointers for the MAC. */
463 s32 (*init_params)(struct e1000_hw *);
464 s32 (*id_led_init)(struct e1000_hw *);
465 s32 (*blink_led)(struct e1000_hw *);
466 s32 (*check_for_link)(struct e1000_hw *);
467 bool (*check_mng_mode)(struct e1000_hw *hw);
468 s32 (*cleanup_led)(struct e1000_hw *);
469 void (*clear_hw_cntrs)(struct e1000_hw *);
470 void (*clear_vfta)(struct e1000_hw *);
471 s32 (*get_bus_info)(struct e1000_hw *);
472 void (*set_lan_id)(struct e1000_hw *);
473 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
474 s32 (*led_on)(struct e1000_hw *);
475 s32 (*led_off)(struct e1000_hw *);
476 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
477 s32 (*reset_hw)(struct e1000_hw *);
478 s32 (*init_hw)(struct e1000_hw *);
479 void (*shutdown_serdes)(struct e1000_hw *);
480 s32 (*setup_link)(struct e1000_hw *);
481 s32 (*setup_physical_interface)(struct e1000_hw *);
482 s32 (*setup_led)(struct e1000_hw *);
483 void (*write_vfta)(struct e1000_hw *, u32, u32);
484 void (*mta_set)(struct e1000_hw *, u32);
485 void (*config_collision_dist)(struct e1000_hw *);
486 void (*rar_set)(struct e1000_hw *, u8*, u32);
487 s32 (*read_mac_addr)(struct e1000_hw *);
488 s32 (*validate_mdi_setting)(struct e1000_hw *);
489 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
490 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
491 struct e1000_host_mng_command_header *);
492 s32 (*mng_enable_host_if)(struct e1000_hw *);
493 s32 (*wait_autoneg)(struct e1000_hw *);
494 };
495
496 struct e1000_phy_operations {
497 s32 (*init_params)(struct e1000_hw *);
498 s32 (*acquire)(struct e1000_hw *);
499 s32 (*check_polarity)(struct e1000_hw *);
500 s32 (*check_reset_block)(struct e1000_hw *);
501 s32 (*commit)(struct e1000_hw *);
502 s32 (*force_speed_duplex)(struct e1000_hw *);
503 s32 (*get_cfg_done)(struct e1000_hw *hw);
504 s32 (*get_cable_length)(struct e1000_hw *);
505 s32 (*get_info)(struct e1000_hw *);
506 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
507 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
508 void (*release)(struct e1000_hw *);
509 s32 (*reset)(struct e1000_hw *);
510 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
511 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
512 s32 (*write_reg)(struct e1000_hw *, u32, u16);
513 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
514 void (*power_up)(struct e1000_hw *);
515 void (*power_down)(struct e1000_hw *);
516 };
517
518 struct e1000_nvm_operations {
519 s32 (*init_params)(struct e1000_hw *);
520 s32 (*acquire)(struct e1000_hw *);
521 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
522 void (*release)(struct e1000_hw *);
523 void (*reload)(struct e1000_hw *);
524 s32 (*update)(struct e1000_hw *);
525 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
526 s32 (*validate)(struct e1000_hw *);
527 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
528 };
529
530 struct e1000_mac_info {
531 struct e1000_mac_operations ops;
532 u8 addr[6];
533 u8 perm_addr[6];
534
535 enum e1000_mac_type type;
536
537 u32 collision_delta;
538 u32 ledctl_default;
539 u32 ledctl_mode1;
540 u32 ledctl_mode2;
541 u32 mc_filter_type;
542 u32 tx_packet_delta;
543 u32 txcw;
544
545 u16 current_ifs_val;
546 u16 ifs_max_val;
547 u16 ifs_min_val;
548 u16 ifs_ratio;
549 u16 ifs_step_size;
550 u16 mta_reg_count;
551 u16 uta_reg_count;
552
553 /* Maximum size of the MTA register table in all supported adapters */
554 #define MAX_MTA_REG 128
555 u32 mta_shadow[MAX_MTA_REG];
556 u16 rar_entry_count;
557
558 u8 forced_speed_duplex;
559
560 bool adaptive_ifs;
561 bool arc_subsystem_valid;
562 bool asf_firmware_present;
563 bool autoneg;
564 bool autoneg_failed;
565 bool get_link_status;
566 bool in_ifs_mode;
567 enum e1000_serdes_link_state serdes_link_state;
568 bool serdes_has_link;
569 bool tx_pkt_filtering;
570 };
571
572 struct e1000_phy_info {
573 struct e1000_phy_operations ops;
574 enum e1000_phy_type type;
575
576 enum e1000_1000t_rx_status local_rx;
577 enum e1000_1000t_rx_status remote_rx;
578 enum e1000_ms_type ms_type;
579 enum e1000_ms_type original_ms_type;
580 enum e1000_rev_polarity cable_polarity;
581 enum e1000_smart_speed smart_speed;
582
583 u32 addr;
584 u32 id;
585 u32 reset_delay_us; /* in usec */
586 u32 revision;
587
588 enum e1000_media_type media_type;
589
590 u16 autoneg_advertised;
591 u16 autoneg_mask;
592 u16 cable_length;
593 u16 max_cable_length;
594 u16 min_cable_length;
595
596 u8 mdix;
597
598 bool disable_polarity_correction;
599 bool is_mdix;
600 bool polarity_correction;
601 bool reset_disable;
602 bool speed_downgraded;
603 bool autoneg_wait_to_complete;
604 };
605
606 struct e1000_nvm_info {
607 struct e1000_nvm_operations ops;
608 enum e1000_nvm_type type;
609 enum e1000_nvm_override override;
610
611 u32 flash_bank_size;
612 u32 flash_base_addr;
613
614 u16 word_size;
615 u16 delay_usec;
616 u16 address_bits;
617 u16 opcode_bits;
618 u16 page_size;
619 };
620
621 struct e1000_bus_info {
622 enum e1000_bus_type type;
623 enum e1000_bus_speed speed;
624 enum e1000_bus_width width;
625
626 u16 func;
627 u16 pci_cmd_word;
628 };
629
630 struct e1000_fc_info {
631 u32 high_water; /* Flow control high-water mark */
632 u32 low_water; /* Flow control low-water mark */
633 u16 pause_time; /* Flow control pause timer */
634 bool send_xon; /* Flow control send XON */
635 bool strict_ieee; /* Strict IEEE mode */
636 enum e1000_fc_mode current_mode; /* FC mode in effect */
637 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
638 };
639
640 struct e1000_dev_spec_82575 {
641 bool sgmii_active;
642 bool global_device_reset;
643 };
644
645 struct e1000_dev_spec_vf {
646 u32 vf_number;
647 u32 v2p_mailbox;
648 };
649
650 struct e1000_hw {
651 void *back;
652
653 u8 *hw_addr;
654 u8 *flash_address;
655 unsigned long io_base;
656
657 struct e1000_mac_info mac;
658 struct e1000_fc_info fc;
659 struct e1000_phy_info phy;
660 struct e1000_nvm_info nvm;
661 struct e1000_bus_info bus;
662 struct e1000_host_mng_dhcp_cookie mng_cookie;
663
664 union {
665 struct e1000_dev_spec_82575 _82575;
666 struct e1000_dev_spec_vf vf;
667 } dev_spec;
668
669 u16 device_id;
670 u16 subsystem_vendor_id;
671 u16 subsystem_device_id;
672 u16 vendor_id;
673
674 u8 revision_id;
675 };
676
677 #include "igb_82575.h"
678
679 /* These functions must be implemented by drivers */
680 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
681 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
682
683 #ifdef __cplusplus
684 }
685 #endif
686
687 #endif /* _IGB_HW_H */