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2038 Add in I350 and ET2 support into igb
Reviewed by: Dan McDonald <danmcd@nexenta.com>
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          --- old/usr/src/uts/common/io/igb/igb_defines.h
          +++ new/usr/src/uts/common/io/igb/igb_defines.h
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  13   13   * When distributing Covered Code, include this CDDL HEADER in each
  14   14   * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15   15   * If applicable, add the following below this CDDL HEADER, with the
  16   16   * fields enclosed by brackets "[]" replaced with your own identifying
  17   17   * information: Portions Copyright [yyyy] [name of copyright owner]
  18   18   *
  19   19   * CDDL HEADER END
  20   20   */
  21   21  
  22   22  /*
  23      - * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
       23 + * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
  24   24   */
  25   25  
  26   26  /*
  27   27   * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
  28   28   */
  29   29  
  30   30  /* IntelVersion: 1.120.2.2 v3_3_14_3_BHSW1 */
  31   31  
  32   32  #ifndef _IGB_DEFINES_H
  33   33  #define _IGB_DEFINES_H
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1000 1000  #define E1000_TTQF_PROTOCOL_SCTP        0x2
1001 1001  #define E1000_TTQF_PROTOCOL_SHIFT       5 /* TTQF Protocol Shift */
1002 1002  #define E1000_TTQF_QUEUE_SHIFT          16 /* TTQF Queue Shfit */
1003 1003  #define E1000_TTQF_RX_QUEUE_MASK        0x70000 /* TTQF Queue Mask */
1004 1004  #define E1000_TTQF_MASK_ENABLE          0x10000000 /* TTQF Mask Enable Bit */
1005 1005  #define E1000_IMIR_CLEAR_MASK           0xF001FFFF /* IMIR Reg Clear Mask */
1006 1006  #define E1000_IMIR_PORT_BYPASS          0x20000 /* IMIR Port Bypass Bit */
1007 1007  #define E1000_IMIR_PRIORITY_SHIFT       29 /* IMIR Priority Shift */
1008 1008  #define E1000_IMIREXT_CLEAR_MASK        0x7FFFF /* IMIREXT Reg Clear Mask */
1009 1009  
     1010 +/* I350 EEE defines */
     1011 +#define E1000_IPCNFG_EEE_1G_AN          0x00000008 /* IPCNFG EEE Ena 1G AN */
     1012 +#define E1000_IPCNFG_EEE_100M_AN        0x00000004 /* IPCNFG EEE Ena 100M AN */
     1013 +#define E1000_EEER_TX_LPI_EN            0x00010000 /* EEER Tx LPI Enable */
     1014 +#define E1000_EEER_RX_LPI_EN            0x00020000 /* EEER Rx LPI Enable */
     1015 +#define E1000_EEER_LPI_FC               0x00040000 /* EEER Ena on Flow Cntrl */
     1016 +
     1017 +
1010 1018  /* PCI Express Control */
1011 1019  #define E1000_GCR_RXD_NO_SNOOP          0x00000001
1012 1020  #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
1013 1021  #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
1014 1022  #define E1000_GCR_TXD_NO_SNOOP          0x00000008
1015 1023  #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
1016 1024  #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
1017 1025  #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
1018 1026  #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
1019 1027  #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
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1141 1149  #define E1000_EECD_DI           0x00000004 /* NVM Data In */
1142 1150  #define E1000_EECD_DO           0x00000008 /* NVM Data Out */
1143 1151  #define E1000_EECD_FWE_MASK     0x00000030
1144 1152  #define E1000_EECD_FWE_DIS      0x00000010 /* Disable FLASH writes */
1145 1153  #define E1000_EECD_FWE_EN       0x00000020 /* Enable FLASH writes */
1146 1154  #define E1000_EECD_FWE_SHIFT    4
1147 1155  #define E1000_EECD_REQ          0x00000040 /* NVM Access Request */
1148 1156  #define E1000_EECD_GNT          0x00000080 /* NVM Access Grant */
1149 1157  #define E1000_EECD_PRES         0x00000100 /* NVM Present */
1150 1158  #define E1000_EECD_SIZE         0x00000200 /* NVM Size (0=64 word 1=256 word) */
     1159 +#define E1000_EECD_BLOCKED      0x00008000 /* Bit banging access blocked flag */
     1160 +#define E1000_EECD_ABORT        0x00010000 /* NVM operation aborted flag */
     1161 +#define E1000_EECD_TIMEOUT      0x00020000 /* NVM read operation timeout flag */
     1162 +#define E1000_EECD_ERROR_CLR    0x00040000 /* NVM error status clear bit */
     1163 +
1151 1164  /* NVM Addressing bits based on type 0=small, 1=large */
1152 1165  #define E1000_EECD_ADDR_BITS    0x00000400
1153 1166  #define E1000_EECD_TYPE         0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1154 1167  #ifndef E1000_NVM_GRANT_ATTEMPTS
1155 1168  #define E1000_NVM_GRANT_ATTEMPTS        1000 /* NVM # attempts to gain grant */
1156 1169  #endif
1157 1170  #define E1000_EECD_AUTO_RD      0x00000200 /* NVM Auto Read done */
1158 1171  #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1159 1172  #define E1000_EECD_SIZE_EX_SHIFT        11
1160 1173  #define E1000_EECD_NVADDS       0x00018000 /* NVM Address Size */
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1300 1313  #define M88E1011_I_PHY_ID       0x01410C20
1301 1314  #define IGP01E1000_I_PHY_ID     0x02A80380
1302 1315  #define M88E1011_I_REV_4        0x04
1303 1316  #define M88E1111_I_PHY_ID       0x01410CC0
1304 1317  #define GG82563_E_PHY_ID        0x01410CA0
1305 1318  #define IGP03E1000_E_PHY_ID     0x02A80390
1306 1319  #define IFE_E_PHY_ID            0x02A80330
1307 1320  #define IFE_PLUS_E_PHY_ID       0x02A80320
1308 1321  #define IFE_C_E_PHY_ID          0x02A80310
1309 1322  #define I82580_I_PHY_ID         0x015403A0
     1323 +#define I350_I_PHY_ID           0x015403B0
1310 1324  #define IGP04E1000_E_PHY_ID     0x02A80391
1311 1325  #define M88_VENDOR              0x0141
1312 1326  
1313 1327  /* M88E1000 Specific Registers */
1314 1328  #define M88E1000_PHY_SPEC_CTRL          0x10 /* PHY Specific Control Register */
1315 1329  #define M88E1000_PHY_SPEC_STATUS        0x11 /* PHY Specific Status Register */
1316 1330  #define M88E1000_INT_ENABLE             0x12 /* Interrupt Enable Register */
1317 1331  #define M88E1000_INT_STATUS             0x13 /* Interrupt Status Register */
1318 1332  #define M88E1000_EXT_PHY_SPEC_CTRL      0x14 /* Extended PHY Specific Control */
1319 1333  #define M88E1000_RX_ERR_CNTR            0x15 /* Receive Error Counter */
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