3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.120.2.2 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_DEFINES_H
33 #define _IGB_DEFINES_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
40 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
41 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
42
43 /* Definitions for power management and wakeup registers */
990
991 /* TUPLE Filtering Configuration */
992 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
993 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
994 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
995 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
996 #define E1000_TTQF_PROTOCOL_TCP 0x0
997 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
998 #define E1000_TTQF_PROTOCOL_UDP 0x1
999 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1000 #define E1000_TTQF_PROTOCOL_SCTP 0x2
1001 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1002 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1003 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1004 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1005 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1006 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1007 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1008 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1009
1010 /* PCI Express Control */
1011 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
1012 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1013 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1014 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
1015 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1016 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1017 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1018 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1019 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1020 #define E1000_GCR_CAP_VER2 0x00040000
1021
1022 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1023 E1000_GCR_RXDSCW_NO_SNOOP | \
1024 E1000_GCR_RXDSCR_NO_SNOOP | \
1025 E1000_GCR_TXD_NO_SNOOP | \
1026 E1000_GCR_TXDSCW_NO_SNOOP | \
1027 E1000_GCR_TXDSCR_NO_SNOOP)
1028
1029 /* PHY Control Register */
1131 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1132 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1133 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1134 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1135
1136 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1137
1138 /* NVM Control */
1139 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1140 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1141 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1142 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1143 #define E1000_EECD_FWE_MASK 0x00000030
1144 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1145 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1146 #define E1000_EECD_FWE_SHIFT 4
1147 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1148 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1149 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1150 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1151 /* NVM Addressing bits based on type 0=small, 1=large */
1152 #define E1000_EECD_ADDR_BITS 0x00000400
1153 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1154 #ifndef E1000_NVM_GRANT_ATTEMPTS
1155 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1156 #endif
1157 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1158 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1159 #define E1000_EECD_SIZE_EX_SHIFT 11
1160 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1161 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1162 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1163 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1164 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1165 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1166 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1167 #define E1000_EECD_SECVAL_SHIFT 22
1168 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1169
1170 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1290 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1291 #define MAX_PHY_MULTI_PAGE_REG 0xF
1292
1293 /* Bit definitions for valid PHY IDs. */
1294 /*
1295 * I = Integrated
1296 * E = External
1297 */
1298 #define M88E1000_E_PHY_ID 0x01410C50
1299 #define M88E1000_I_PHY_ID 0x01410C30
1300 #define M88E1011_I_PHY_ID 0x01410C20
1301 #define IGP01E1000_I_PHY_ID 0x02A80380
1302 #define M88E1011_I_REV_4 0x04
1303 #define M88E1111_I_PHY_ID 0x01410CC0
1304 #define GG82563_E_PHY_ID 0x01410CA0
1305 #define IGP03E1000_E_PHY_ID 0x02A80390
1306 #define IFE_E_PHY_ID 0x02A80330
1307 #define IFE_PLUS_E_PHY_ID 0x02A80320
1308 #define IFE_C_E_PHY_ID 0x02A80310
1309 #define I82580_I_PHY_ID 0x015403A0
1310 #define IGP04E1000_E_PHY_ID 0x02A80391
1311 #define M88_VENDOR 0x0141
1312
1313 /* M88E1000 Specific Registers */
1314 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1315 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1316 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1317 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1318 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1319 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1320
1321 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1322 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg29 for page number setting */
1323 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1324 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1325 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1326
1327 /* M88E1000 PHY Specific Control Register */
1328 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1329 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.120.2.2 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_DEFINES_H
33 #define _IGB_DEFINES_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
40 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
41 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
42
43 /* Definitions for power management and wakeup registers */
990
991 /* TUPLE Filtering Configuration */
992 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
993 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
994 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
995 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
996 #define E1000_TTQF_PROTOCOL_TCP 0x0
997 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
998 #define E1000_TTQF_PROTOCOL_UDP 0x1
999 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1000 #define E1000_TTQF_PROTOCOL_SCTP 0x2
1001 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1002 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1003 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1004 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1005 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1006 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1007 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1008 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1009
1010 /* I350 EEE defines */
1011 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
1012 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
1013 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
1014 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
1015 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
1016
1017
1018 /* PCI Express Control */
1019 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
1020 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1021 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1022 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
1023 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1024 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1025 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1026 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1027 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1028 #define E1000_GCR_CAP_VER2 0x00040000
1029
1030 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1031 E1000_GCR_RXDSCW_NO_SNOOP | \
1032 E1000_GCR_RXDSCR_NO_SNOOP | \
1033 E1000_GCR_TXD_NO_SNOOP | \
1034 E1000_GCR_TXDSCW_NO_SNOOP | \
1035 E1000_GCR_TXDSCR_NO_SNOOP)
1036
1037 /* PHY Control Register */
1139 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1140 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1141 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1142 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1143
1144 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1145
1146 /* NVM Control */
1147 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1148 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1149 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1150 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1151 #define E1000_EECD_FWE_MASK 0x00000030
1152 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1153 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1154 #define E1000_EECD_FWE_SHIFT 4
1155 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1156 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1157 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1158 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1159 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1160 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1161 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1162 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1163
1164 /* NVM Addressing bits based on type 0=small, 1=large */
1165 #define E1000_EECD_ADDR_BITS 0x00000400
1166 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1167 #ifndef E1000_NVM_GRANT_ATTEMPTS
1168 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1169 #endif
1170 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1171 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1172 #define E1000_EECD_SIZE_EX_SHIFT 11
1173 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1174 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1175 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1176 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1177 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1178 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1179 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1180 #define E1000_EECD_SECVAL_SHIFT 22
1181 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1182
1183 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1303 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1304 #define MAX_PHY_MULTI_PAGE_REG 0xF
1305
1306 /* Bit definitions for valid PHY IDs. */
1307 /*
1308 * I = Integrated
1309 * E = External
1310 */
1311 #define M88E1000_E_PHY_ID 0x01410C50
1312 #define M88E1000_I_PHY_ID 0x01410C30
1313 #define M88E1011_I_PHY_ID 0x01410C20
1314 #define IGP01E1000_I_PHY_ID 0x02A80380
1315 #define M88E1011_I_REV_4 0x04
1316 #define M88E1111_I_PHY_ID 0x01410CC0
1317 #define GG82563_E_PHY_ID 0x01410CA0
1318 #define IGP03E1000_E_PHY_ID 0x02A80390
1319 #define IFE_E_PHY_ID 0x02A80330
1320 #define IFE_PLUS_E_PHY_ID 0x02A80320
1321 #define IFE_C_E_PHY_ID 0x02A80310
1322 #define I82580_I_PHY_ID 0x015403A0
1323 #define I350_I_PHY_ID 0x015403B0
1324 #define IGP04E1000_E_PHY_ID 0x02A80391
1325 #define M88_VENDOR 0x0141
1326
1327 /* M88E1000 Specific Registers */
1328 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1329 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1330 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1331 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1332 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1333 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1334
1335 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1336 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg29 for page number setting */
1337 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1338 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1339 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1340
1341 /* M88E1000 PHY Specific Control Register */
1342 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1343 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|