1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.120.2.2 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_DEFINES_H
33 #define _IGB_DEFINES_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
40 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
41 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
42
43 /* Definitions for power management and wakeup registers */
44 /* Wake Up Control */
45 #define E1000_WUC_APME 0x00000001 /* APM Enable */
46 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
47 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
48 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
49 #define E1000_WUC_LSCWE 0x00000010 /* Link Status wake up enable */
50 #define E1000_WUC_LSCWO 0x00000020 /* Link Status wake up override */
51 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
52 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
53
54 /* Wake Up Filter Control */
55 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
56 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
57 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
58 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
59 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
60 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
61 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
62 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
63 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
64 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
65 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
66 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
67 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
68 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
69 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
70 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
71 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
72 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
73 /*
74 * For 82576 to utilize Extended filter masks in addition to
75 * existing (filter) masks
76 */
77 #define E1000_WUFC_EXT_FLX_FILTERS 0x00300000 /* Ext. FLX filter mask */
78
79 /* Wake Up Status */
80 #define E1000_WUS_LNKC E1000_WUFC_LNKC
81 #define E1000_WUS_MAG E1000_WUFC_MAG
82 #define E1000_WUS_EX E1000_WUFC_EX
83 #define E1000_WUS_MC E1000_WUFC_MC
84 #define E1000_WUS_BC E1000_WUFC_BC
85 #define E1000_WUS_ARP E1000_WUFC_ARP
86 #define E1000_WUS_IPV4 E1000_WUFC_IPV4
87 #define E1000_WUS_IPV6 E1000_WUFC_IPV6
88 #define E1000_WUS_FLX0 E1000_WUFC_FLX0
89 #define E1000_WUS_FLX1 E1000_WUFC_FLX1
90 #define E1000_WUS_FLX2 E1000_WUFC_FLX2
91 #define E1000_WUS_FLX3 E1000_WUFC_FLX3
92 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
93
94 /* Wake Up Packet Length */
95 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
96
97 /* Four Flexible Filters are supported */
98 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
99 /* Two Extended Flexible Filters are supported (82576) */
100 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
101 #define E1000_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
102 #define E1000_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
103
104 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
105 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
106
107 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
108 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
109 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
110
111 /* Extended Device Control */
112 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
113 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
114 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
115 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
116 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
117 /* Reserved (bits 4,5) in >= 82575 */
118 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
119 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
120 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
121 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
122 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
123 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
124 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
125 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
126 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
127 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
128 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
129 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
130 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
131 /* Physical Func Reset Done Indication */
132 #define E1000_CTRL_EXT_PFRSTD 0x00004000
133 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
134 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
135 /* DMA Dynamic Clock Gating */
136 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
137 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
138 #define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /* 82580 bit 24:22 */
139 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
140 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
141 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
142 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
143 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
144 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
145 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
146 #define E1000_CTRL_EXT_EIAME 0x01000000
147 #define E1000_CTRL_EXT_IRCA 0x00000001
148 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
149 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
150 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
151 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
152 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
153 #define E1000_CTRL_EXT_CANC 0x04000000 /* Int delay cancellation */
154 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
155 /* IAME enable bit (27) was removed in >= 82575 */
156 /* Interrupt acknowledge Auto-mask */
157 #define E1000_CTRL_EXT_IAME 0x08000000
158 /* Clear Interrupt timers after IMS clear */
159 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000
160 /* packet buffer parity error detection enabled */
161 #define E1000_CRTL_EXT_PB_PAREN 0x01000000
162 /* descriptor FIFO parity error detection enable */
163 #define E1000_CTRL_EXT_DF_PAREN 0x02000000
164 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
165 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
166 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
167 #define E1000_I2CCMD_REG_ADDR 0x00FF0000
168 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
169 #define E1000_I2CCMD_PHY_ADDR 0x07000000
170 #define E1000_I2CCMD_OPCODE_READ 0x08000000
171 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
172 #define E1000_I2CCMD_RESET 0x10000000
173 #define E1000_I2CCMD_READY 0x20000000
174 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
175 #define E1000_I2CCMD_ERROR 0x80000000
176 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
177 #define E1000_I2CCMD_PHY_TIMEOUT 200
178 #define E1000_IVAR_VALID 0x80
179 #define E1000_GPIE_NSICR 0x00000001
180 #define E1000_GPIE_MSIX_MODE 0x00000010
181 #define E1000_GPIE_EIAME 0x40000000
182 #define E1000_GPIE_PBA 0x80000000
183
184 /* Receive Descriptor bit definitions */
185 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
186 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
187 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
188 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
189 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
190 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
191 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
192 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
193 #define E1000_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
194 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
195 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
196 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
197 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
198 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
199 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
200 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
201 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
202 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
203 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
204 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
205 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
206 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
207 #define E1000_RXD_SPC_PRI_SHIFT 13
208 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
209 #define E1000_RXD_SPC_CFI_SHIFT 12
210
211 #define E1000_RXDEXT_STATERR_CE 0x01000000
212 #define E1000_RXDEXT_STATERR_SE 0x02000000
213 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
214 #define E1000_RXDEXT_STATERR_CXE 0x10000000
215 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
216 #define E1000_RXDEXT_STATERR_IPE 0x40000000
217 #define E1000_RXDEXT_STATERR_RXE 0x80000000
218
219 /* mask to determine if packets should be dropped due to frame errors */
220 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
221 E1000_RXD_ERR_CE | \
222 E1000_RXD_ERR_SE | \
223 E1000_RXD_ERR_SEQ | \
224 E1000_RXD_ERR_CXE | \
225 E1000_RXD_ERR_RXE)
226
227 /* Same mask, but for extended and packet split descriptors */
228 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
229 E1000_RXDEXT_STATERR_CE | \
230 E1000_RXDEXT_STATERR_SE | \
231 E1000_RXDEXT_STATERR_SEQ | \
232 E1000_RXDEXT_STATERR_CXE | \
233 E1000_RXDEXT_STATERR_RXE)
234
235 #define E1000_MRQC_ENABLE_MASK 0x00000007
236 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
237 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
238 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
239 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
240 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
241 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
242 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
243 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
244 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
245
246 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
247 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
248
249 /* Management Control */
250 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
251 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
252 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
253 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
254 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
255 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
256 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
257 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
258 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
259 /* Enable Neighbor Discovery Filtering */
260 #define E1000_MANC_NEIGHBOR_EN 0x00004000
261 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
262 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
263 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
264 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
265 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
266 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
267 /* Enable MAC address filtering */
268 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
269 /* Enable MNG packets to host memory */
270 #define E1000_MANC_EN_MNG2HOST 0x00200000
271 /* Enable IP address filtering */
272 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
273 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
274 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
275 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
276 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
277 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
278 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
279 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
280 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
281
282 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
283 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
284
285 /* Receive Control */
286 #define E1000_RCTL_RST 0x00000001 /* Software reset */
287 #define E1000_RCTL_EN 0x00000002 /* enable */
288 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
289 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
290 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
291 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
292 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
293 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
294 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
295 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
296 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
297 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
298 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
299 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
300 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
301 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
302 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
303 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
304 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
305 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
306 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
307 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
308 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
309 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
310 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
311 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
312 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
313 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
314 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
315 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
316 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
317 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
318 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
319 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
320 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
321 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
322 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
323 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
324 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
325 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
326
327 /*
328 * Use byte values for the following shift parameters
329 * Usage:
330 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
331 * E1000_PSRCTL_BSIZE0_MASK) |
332 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
333 * E1000_PSRCTL_BSIZE1_MASK) |
334 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
335 * E1000_PSRCTL_BSIZE2_MASK) |
336 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
337 * E1000_PSRCTL_BSIZE3_MASK))
338 * where value0 = [128..16256], default=256
339 * value1 = [1024..64512], default=4096
340 * value2 = [0..64512], default=4096
341 * value3 = [0..64512], default=0
342 */
343
344 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
345 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
346 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
347 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
348
349 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
350 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
351 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
352 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
353
354 /* SWFW_SYNC Definitions */
355 #define E1000_SWFW_EEP_SM 0x1
356 #define E1000_SWFW_PHY0_SM 0x2
357 #define E1000_SWFW_PHY1_SM 0x4
358 #define E1000_SWFW_CSR_SM 0x8
359 #define E1000_SWFW_PHY2_SM 0x20
360 #define E1000_SWFW_PHY3_SM 0x40
361
362 /* FACTPS Definitions */
363 #define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */
364 /* Device Control */
365 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
366 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
367 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
368 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /* Block new Master requests */
369 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
370 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
371 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
372 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
373 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
374 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
375 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
376 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
377 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
378 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
379 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
380 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
381 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
382 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
383 /* Defined polarity of Dock/Undock indication in SDP[0] */
384 #define E1000_CTRL_D_UD_POLARITY 0x00004000
385 /* Reset both PHY ports, through PHYRST_N pin */
386 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000
387 /* enable link status from external LINK_0 and LINK_1 pins */
388 #define E1000_CTRL_EXT_LINK_EN 0x00010000
389 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
390 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
391 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
392 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
393 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
394 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
395 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
396 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
397 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
398 #define E1000_CTRL_RST 0x04000000 /* Global reset */
399 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
400 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
401 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
402 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
403 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
404 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
405 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
406
407 /*
408 * Bit definitions for the Management Data IO (MDIO) and Management Data
409 * Clock (MDC) pins in the Device Control Register.
410 */
411 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
412 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
413 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
414 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
415 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
416 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
417 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
418 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
419
420 #define E1000_CONNSW_ENRGSRC 0x4
421 #define E1000_PCS_CFG_PCS_EN 8
422 #define E1000_PCS_LCTL_FLV_LINK_UP 1
423 #define E1000_PCS_LCTL_FSV_10 0
424 #define E1000_PCS_LCTL_FSV_100 2
425 #define E1000_PCS_LCTL_FSV_1000 4
426 #define E1000_PCS_LCTL_FDV_FULL 8
427 #define E1000_PCS_LCTL_FSD 0x10
428 #define E1000_PCS_LCTL_FORCE_LINK 0x20
429 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
430 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
431 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
432 #define E1000_PCS_LCTL_AN_RESTART 0x20000
433 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
434 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
435 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
436 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
437 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
438 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
439 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
440
441 #define E1000_PCS_LSTS_LINK_OK 1
442 #define E1000_PCS_LSTS_SPEED_10 0
443 #define E1000_PCS_LSTS_SPEED_100 2
444 #define E1000_PCS_LSTS_SPEED_1000 4
445 #define E1000_PCS_LSTS_DUPLEX_FULL 8
446 #define E1000_PCS_LSTS_SYNK_OK 0x10
447 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
448 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
449 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
450 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
451 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
452
453 /* Device Status */
454 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
455 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
456 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
457 #define E1000_STATUS_FUNC_SHIFT 2
458 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
459 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
460 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
461 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
462 #define E1000_STATUS_SPEED_MASK 0x000000C0
463 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
464 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
465 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
466 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
467 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
468 /* Change in Dock/Undock state. Clear on write '0'. */
469 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
470 #define E1000_STATUS_DOCK_CI 0x00000800
471 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
472 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
473 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
474 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
475 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
476 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
477 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
478 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
479 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
480 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
481 /* BMC external code execution disabled */
482 #define E1000_STATUS_BMC_LITE 0x01000000
483 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
484 #define E1000_STATUS_FUSE_8 0x04000000
485 #define E1000_STATUS_FUSE_9 0x08000000
486 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
487 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
488
489 /* Constants used to interpret the masked PCI-X bus speed. */
490 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
491 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
492 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
493
494 #define SPEED_10 10
495 #define SPEED_100 100
496 #define SPEED_1000 1000
497 #define HALF_DUPLEX 1
498 #define FULL_DUPLEX 2
499
500 #define PHY_FORCE_TIME 20
501
502 #define ADVERTISE_10_HALF 0x0001
503 #define ADVERTISE_10_FULL 0x0002
504 #define ADVERTISE_100_HALF 0x0004
505 #define ADVERTISE_100_FULL 0x0008
506 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
507 #define ADVERTISE_1000_FULL 0x0020
508
509 /* 1000/H is not supported, nor spec-compliant. */
510 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
511 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
512 ADVERTISE_1000_FULL)
513 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
514 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
515 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
516 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
517 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
518 ADVERTISE_1000_FULL)
519 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
520
521 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
522
523 /* LED Control */
524 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
525 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
526 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
527 #define E1000_LEDCTL_LED0_IVRT 0x00000040
528 #define E1000_LEDCTL_LED0_BLINK 0x00000080
529 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
530 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
531 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
532 #define E1000_LEDCTL_LED1_IVRT 0x00004000
533 #define E1000_LEDCTL_LED1_BLINK 0x00008000
534 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
535 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
536 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
537 #define E1000_LEDCTL_LED2_IVRT 0x00400000
538 #define E1000_LEDCTL_LED2_BLINK 0x00800000
539 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
540 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
541 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
542 #define E1000_LEDCTL_LED3_IVRT 0x40000000
543 #define E1000_LEDCTL_LED3_BLINK 0x80000000
544
545 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
546 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
547 #define E1000_LEDCTL_MODE_LINK_UP 0x2
548 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
549 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
550 #define E1000_LEDCTL_MODE_LINK_10 0x5
551 #define E1000_LEDCTL_MODE_LINK_100 0x6
552 #define E1000_LEDCTL_MODE_LINK_1000 0x7
553 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
554 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
555 #define E1000_LEDCTL_MODE_COLLISION 0xA
556 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
557 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
558 #define E1000_LEDCTL_MODE_PAUSED 0xD
559 #define E1000_LEDCTL_MODE_LED_ON 0xE
560 #define E1000_LEDCTL_MODE_LED_OFF 0xF
561
562 /* Transmit Descriptor bit definitions */
563 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
564 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
565 #define E1000_TXD_POPTS_SHIFT 8 /* POPTS shift */
566 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
567 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
568 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
569 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
570 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
571 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
572 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
573 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0=legacy) */
574 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
575 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
576 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
577 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
578 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
579 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
580 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
581 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
582 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
583 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
584 /* Extended desc bits for Linksec and timesync */
585
586 /* Transmit Control */
587 #define E1000_TCTL_RST 0x00000001 /* software reset */
588 #define E1000_TCTL_EN 0x00000002 /* enable tx */
589 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
590 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
591 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
592 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
593 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
594 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
595 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
596 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
597 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
598
599 /* Transmit Arbitration Count */
600 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
601
602 /* SerDes Control */
603 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
604
605 /* Receive Checksum Control */
606 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
607 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
608 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
609 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
610 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
611 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
612 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
613
614 /* Header split receive */
615 #define E1000_RFCTL_ISCSI_DIS 0x00000001
616 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
617 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
618 #define E1000_RFCTL_NFSW_DIS 0x00000040
619 #define E1000_RFCTL_NFSR_DIS 0x00000080
620 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
621 #define E1000_RFCTL_NFS_VER_SHIFT 8
622 #define E1000_RFCTL_IPV6_DIS 0x00000400
623 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
624 #define E1000_RFCTL_ACK_DIS 0x00001000
625 #define E1000_RFCTL_ACKD_DIS 0x00002000
626 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
627 #define E1000_RFCTL_EXTEN 0x00008000
628 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
629 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
630 #define E1000_RFCTL_LEF 0x00040000
631
632 /* Collision related configuration parameters */
633 #define E1000_COLLISION_THRESHOLD 15
634 #define E1000_CT_SHIFT 4
635 #define E1000_COLLISION_DISTANCE 63
636 #define E1000_COLD_SHIFT 12
637
638 /* Default values for the transmit IPG register */
639 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
640 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
641
642 #define E1000_TIPG_IPGT_MASK 0x000003FF
643 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
644 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
645
646 #define DEFAULT_82543_TIPG_IPGR1 8
647 #define E1000_TIPG_IPGR1_SHIFT 10
648
649 #define DEFAULT_82543_TIPG_IPGR2 6
650 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
651 #define E1000_TIPG_IPGR2_SHIFT 20
652
653 /* Ethertype field values */
654 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
655
656 #define ETHERNET_FCS_SIZE 4
657 #define MAX_JUMBO_FRAME_SIZE 0x3F00
658
659 /* Extended Configuration Control and Size */
660 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
661 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
662 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
663 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
664 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
665 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
666 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
667 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
668
669 #define E1000_PHY_CTRL_SPD_EN 0x00000001
670 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
671 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
672 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
673 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
674
675 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
676
677 /* PBA constants */
678 #define E1000_PBA_6K 0x0006 /* 6KB */
679 #define E1000_PBA_8K 0x0008 /* 8KB */
680 #define E1000_PBA_10K 0x000A /* 10KB */
681 #define E1000_PBA_12K 0x000C /* 12KB */
682 #define E1000_PBA_14K 0x000E /* 14KB */
683 #define E1000_PBA_16K 0x0010 /* 16KB */
684 #define E1000_PBA_18K 0x0012
685 #define E1000_PBA_20K 0x0014
686 #define E1000_PBA_22K 0x0016
687 #define E1000_PBA_24K 0x0018
688 #define E1000_PBA_26K 0x001A
689 #define E1000_PBA_30K 0x001E
690 #define E1000_PBA_32K 0x0020
691 #define E1000_PBA_34K 0x0022
692 #define E1000_PBA_35K 0x0023
693 #define E1000_PBA_38K 0x0026
694 #define E1000_PBA_40K 0x0028
695 #define E1000_PBA_48K 0x0030 /* 48KB */
696 #define E1000_PBA_64K 0x0040 /* 64KB */
697
698 #define E1000_PBS_16K E1000_PBA_16K
699 #define E1000_PBS_24K E1000_PBA_24K
700
701 #define IFS_MAX 80
702 #define IFS_MIN 40
703 #define IFS_RATIO 4
704 #define IFS_STEP 10
705 #define MIN_NUM_XMITS 1000
706
707 /* SW Semaphore Register */
708 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
709 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
710 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
711 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
712
713 /* Secondary driver semaphore bit */
714 #define E1000_SWSM2_LOCK 0x00000002
715
716 /* Interrupt Cause Read */
717 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
718 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
719 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
720 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
721 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
722 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
723 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
724 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
725 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
726 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
727 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
728 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
729 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
730 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
731 #define E1000_ICR_TXD_LOW 0x00008000
732 #define E1000_ICR_SRPD 0x00010000
733 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
734 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
735 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
736 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
737 /* If this bit asserted, the driver should claim the interrupt */
738 #define E1000_ICR_INT_ASSERTED 0x80000000
739 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
740 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
741 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
742 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
743 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
744 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
745 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
746 /* FW changed the status of DISSW bit in the FWSM */
747 #define E1000_ICR_DSW 0x00000020
748 /* LAN connected device generates an interrupt */
749 #define E1000_ICR_PHYINT 0x00001000
750 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
751 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
752 #define E1000_ICR_FER 0x00400000 /* Fatal Error */
753
754 /* Extended Interrupt Cause Read */
755 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
756 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
757 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
758 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
759 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
760 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
761 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
762 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
763 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
764 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
765 /* TCP Timer */
766 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
767 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
768 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
769 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
770
771 /*
772 * This defines the bits that are set in the Interrupt Mask
773 * Set/Read Register. Each bit is documented below:
774 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
775 * o RXSEQ = Receive Sequence Error
776 */
777 #define POLL_IMS_ENABLE_MASK ( \
778 E1000_IMS_RXDMT0 | \
779 E1000_IMS_RXSEQ)
780
781 /*
782 * This defines the bits that are set in the Interrupt Mask
783 * Set/Read Register. Each bit is documented below:
784 * o RXT0 = Receiver Timer Interrupt (ring 0)
785 * o TXDW = Transmit Descriptor Written Back
786 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
787 * o RXSEQ = Receive Sequence Error
788 * o LSC = Link Status Change
789 */
790 #define IMS_ENABLE_MASK ( \
791 E1000_IMS_RXT0 | \
792 E1000_IMS_TXDW | \
793 E1000_IMS_RXDMT0 | \
794 E1000_IMS_RXSEQ | \
795 E1000_IMS_LSC)
796
797 /* Interrupt Mask Set */
798 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
799 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
800 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
801 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
802 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
803 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
804 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
805 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
806 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
807 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
808 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
809 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
810 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
811 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
812 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
813 #define E1000_IMS_SRPD E1000_ICR_SRPD
814 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
815 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
816 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
817 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
818 /* queue 0 Rx descriptor FIFO parity error */
819 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
820 /* queue 0 Tx descriptor FIFO parity error */
821 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
822 /* host arb read buffer parity error */
823 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
824 /* packet buffer parity error */
825 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
826 /* queue 1 Rx descriptor FIFO parity error */
827 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
828 /* queue 1 Tx descriptor FIFO parity error */
829 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
830 #define E1000_IMS_DSW E1000_ICR_DSW
831 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
832 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
833 #define E1000_IMS_EPRST E1000_ICR_EPRST
834 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
835
836 /* Extended Interrupt Mask Set */
837 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
838 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
839 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
840 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
841 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
842 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
843 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
844 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
845 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
846 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
847
848 /* Interrupt Cause Set */
849 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
850 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
851 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
852 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
853 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
854 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
855 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
856 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
857 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* Rx /c/ ordered set */
858 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
859 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
860 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
861 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
862 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
863 #define E1000_ICS_SRPD E1000_ICR_SRPD
864 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
865 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
866 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
867 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */
868 /* queue 0 Rx descriptor FIFO parity error */
869 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
870 /* queue 0 Tx descriptor FIFO parity error */
871 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
872 /* host arb read buffer parity error */
873 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
874 /* packet buffer parity error */
875 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
876 /* queue 1 Rx descriptor FIFO parity error */
877 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
878 /* queue 1 Tx descriptor FIFO parity error */
879 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
880 #define E1000_ICS_DSW E1000_ICR_DSW
881 #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
882 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
883 #define E1000_ICS_EPRST E1000_ICR_EPRST
884
885 /* Extended Interrupt Cause Set */
886 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
887 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
888 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
889 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
890 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
891 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
892 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
893 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
894 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
895 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
896
897 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
898
899 /* Transmit Descriptor Control */
900 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
901 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
902 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
903 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
904 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
905 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
906 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
907 /* Enable the counting of descriptors still to be processed. */
908 #define E1000_TXDCTL_COUNT_DESC 0x00400000
909
910 /* Flow Control Constants */
911 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
912 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
913 #define FLOW_CONTROL_TYPE 0x8808
914
915 /* 802.1q VLAN Packet Size */
916 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
917 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
918
919 /* Receive Address */
920 /*
921 * Number of high/low register pairs in the RAR. The RAR (Receive Address
922 * Registers) holds the directed and multicast addresses that we monitor.
923 * Technically, we have 16 spots. However, we reserve one of these spots
924 * (RAR[15]) for our directed address used by controllers with
925 * manageability enabled, allowing us room for 15 multicast addresses.
926 */
927 #define E1000_RAR_ENTRIES 15
928 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
929 #define E1000_RAL_MAC_ADDR_LEN 4
930 #define E1000_RAH_MAC_ADDR_LEN 2
931 #define E1000_RAH_POOL_MASK 0x03FC0000
932 #define E1000_RAH_POOL_1 0x00040000
933
934 /* Error Codes */
935 #define E1000_SUCCESS 0
936 #define E1000_ERR_NVM 1
937 #define E1000_ERR_PHY 2
938 #define E1000_ERR_CONFIG 3
939 #define E1000_ERR_PARAM 4
940 #define E1000_ERR_MAC_INIT 5
941 #define E1000_ERR_PHY_TYPE 6
942 #define E1000_ERR_RESET 9
943 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
944 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
945 #define E1000_BLK_PHY_RESET 12
946 #define E1000_ERR_SWFW_SYNC 13
947 #define E1000_NOT_IMPLEMENTED 14
948 #define E1000_ERR_MBX 15
949
950 /* Loop limit on how long we wait for auto-negotiation to complete */
951 #define FIBER_LINK_UP_LIMIT 50
952 #define COPPER_LINK_UP_LIMIT 10
953 #define PHY_AUTO_NEG_LIMIT 45
954 #define PHY_FORCE_LIMIT 20
955 /* Number of 100 microseconds we wait for PCI Express master disable */
956 #define MASTER_DISABLE_TIMEOUT 800
957 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
958 #define PHY_CFG_TIMEOUT 100
959 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
960 #define MDIO_OWNERSHIP_TIMEOUT 10
961 /* Number of milliseconds for NVM auto read done after MAC reset. */
962 #define AUTO_READ_DONE_TIMEOUT 10
963
964 /* Flow Control */
965 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
966 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
967 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
968 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
969
970 /* Transmit Configuration Word */
971 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
972 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
973 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
974 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
975 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
976 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
977 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
978 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
979 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
980 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
981
982 /* Receive Configuration Word */
983 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
984 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
985 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
986 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
987 #define E1000_RXCW_C 0x20000000 /* Receive config */
988 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
989 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
990
991 /* TUPLE Filtering Configuration */
992 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
993 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
994 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
995 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
996 #define E1000_TTQF_PROTOCOL_TCP 0x0
997 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
998 #define E1000_TTQF_PROTOCOL_UDP 0x1
999 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
1000 #define E1000_TTQF_PROTOCOL_SCTP 0x2
1001 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
1002 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
1003 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
1004 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
1005 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
1006 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
1007 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
1008 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
1009
1010 /* I350 EEE defines */
1011 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
1012 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
1013 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
1014 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
1015 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
1016
1017
1018 /* PCI Express Control */
1019 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
1020 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
1021 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
1022 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
1023 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
1024 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
1025 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
1026 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
1027 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
1028 #define E1000_GCR_CAP_VER2 0x00040000
1029
1030 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
1031 E1000_GCR_RXDSCW_NO_SNOOP | \
1032 E1000_GCR_RXDSCR_NO_SNOOP | \
1033 E1000_GCR_TXD_NO_SNOOP | \
1034 E1000_GCR_TXDSCW_NO_SNOOP | \
1035 E1000_GCR_TXDSCR_NO_SNOOP)
1036
1037 /* PHY Control Register */
1038 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1039 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1040 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1041 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1042 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1043 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
1044 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1045 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1046 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1047 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1048 #define MII_CR_SPEED_1000 0x0040
1049 #define MII_CR_SPEED_100 0x2000
1050 #define MII_CR_SPEED_10 0x0000
1051
1052 /* PHY Status Register */
1053 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1054 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1055 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1056 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1057 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1058 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1059 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1060 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1061 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1062 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1063 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1064 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1065 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1066 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1067 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1068
1069 /* Autoneg Advertisement Register */
1070 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1071 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1072 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1073 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1074 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1075 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1076 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1077 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1078 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1079 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1080
1081 /* Link Partner Ability Register (Base Page) */
1082 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1083 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1084 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1085 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1086 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1087 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1088 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1089 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1090 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1091 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1092 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1093
1094 /* Autoneg Expansion Register */
1095 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1096 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1097 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1098 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1099 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1100
1101 /* 1000BASE-T Control Register */
1102 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1103 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1104 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1105 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1106 /* 0=DTE device */
1107 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1108 /* 0=Configure PHY as Slave */
1109 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1110 /* 0=Automatic Master/Slave config */
1111 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1112 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1113 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1114 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1115 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1116
1117 /* 1000BASE-T Status Register */
1118 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1119 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1120 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1121 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1122 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1123 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1124 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx is Master, 0=Slave */
1125 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1126
1127 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1128
1129 /* PHY 1000 MII Register/Bit Definitions */
1130 /* PHY Registers defined by IEEE */
1131 #define PHY_CONTROL 0x00 /* Control Register */
1132 #define PHY_STATUS 0x01 /* Status Register */
1133 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1134 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1135 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1136 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1137 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1138 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1139 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1140 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1141 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1142 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1143
1144 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1145
1146 /* NVM Control */
1147 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1148 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1149 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1150 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1151 #define E1000_EECD_FWE_MASK 0x00000030
1152 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1153 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1154 #define E1000_EECD_FWE_SHIFT 4
1155 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1156 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1157 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1158 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1159 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1160 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1161 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1162 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1163
1164 /* NVM Addressing bits based on type 0=small, 1=large */
1165 #define E1000_EECD_ADDR_BITS 0x00000400
1166 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1167 #ifndef E1000_NVM_GRANT_ATTEMPTS
1168 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1169 #endif
1170 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1171 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1172 #define E1000_EECD_SIZE_EX_SHIFT 11
1173 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1174 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1175 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1176 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1177 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1178 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1179 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1180 #define E1000_EECD_SECVAL_SHIFT 22
1181 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1182
1183 #define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */
1184 #define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */
1185 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
1186 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1187 #define E1000_NVM_RW_REG_START 1 /* Start operation */
1188 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1189 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1190 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1191 #define E1000_FLASH_UPDATES 2000
1192
1193 /* NVM Word Offsets */
1194 #define NVM_COMPAT 0x0003
1195 #define NVM_ID_LED_SETTINGS 0x0004
1196 #define NVM_VERSION 0x0005
1197 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1198 #define NVM_PHY_CLASS_WORD 0x0007
1199 #define NVM_INIT_CONTROL1_REG 0x000A
1200 #define NVM_INIT_CONTROL2_REG 0x000F
1201 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1202 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1203 #define NVM_INIT_3GIO_3 0x001A
1204 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1205 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1206 #define NVM_CFG 0x0012
1207 #define NVM_FLASH_VERSION 0x0032
1208 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1209 #define NVM_CHECKSUM_REG 0x003F
1210
1211 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */
1212 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */
1213 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1214 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1215
1216 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
1217
1218 /* Mask bits for fields in Word 0x0f of the NVM */
1219 #define NVM_WORD0F_PAUSE_MASK 0x3000
1220 #define NVM_WORD0F_PAUSE 0x1000
1221 #define NVM_WORD0F_ASM_DIR 0x2000
1222 #define NVM_WORD0F_ANE 0x0800
1223 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1224 #define NVM_WORD0F_LPLU 0x0001
1225
1226 /* Mask bits for fields in Word 0x1a of the NVM */
1227 #define NVM_WORD1A_ASPM_MASK 0x000C
1228
1229 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1230 #define NVM_SUM 0xBABA
1231
1232 #define NVM_MAC_ADDR_OFFSET 0
1233 #define NVM_PBA_OFFSET_0 8
1234 #define NVM_PBA_OFFSET_1 9
1235 #define NVM_RESERVED_WORD 0xFFFF
1236 #define NVM_PHY_CLASS_A 0x8000
1237 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1238 #define NVM_SIZE_MASK 0x1C00
1239 #define NVM_SIZE_SHIFT 10
1240 #define NVM_WORD_SIZE_BASE_SHIFT 6
1241 #define NVM_SWDPIO_EXT_SHIFT 4
1242
1243 /* NVM Commands - Microwire */
1244 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1245 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1246 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1247 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1248 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1249
1250 /* NVM Commands - SPI */
1251 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1252 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1253 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1254 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1255 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1256 #define NVM_WRDI_OPCODE_SPI 0x04 /* NVM reset Write Enable latch */
1257 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1258 #define NVM_WRSR_OPCODE_SPI 0x01 /* NVM write Status register */
1259
1260 /* SPI NVM Status Register */
1261 #define NVM_STATUS_RDY_SPI 0x01
1262 #define NVM_STATUS_WEN_SPI 0x02
1263 #define NVM_STATUS_BP0_SPI 0x04
1264 #define NVM_STATUS_BP1_SPI 0x08
1265 #define NVM_STATUS_WPEN_SPI 0x80
1266
1267 /* Word definitions for ID LED Settings */
1268 #define ID_LED_RESERVED_0000 0x0000
1269 #define ID_LED_RESERVED_FFFF 0xFFFF
1270 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1271 (ID_LED_OFF1_OFF2 << 8) | \
1272 (ID_LED_DEF1_DEF2 << 4) | \
1273 (ID_LED_DEF1_DEF2))
1274 #define ID_LED_DEF1_DEF2 0x1
1275 #define ID_LED_DEF1_ON2 0x2
1276 #define ID_LED_DEF1_OFF2 0x3
1277 #define ID_LED_ON1_DEF2 0x4
1278 #define ID_LED_ON1_ON2 0x5
1279 #define ID_LED_ON1_OFF2 0x6
1280 #define ID_LED_OFF1_DEF2 0x7
1281 #define ID_LED_OFF1_ON2 0x8
1282 #define ID_LED_OFF1_OFF2 0x9
1283
1284 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1285 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1286 #define IGP_LED3_MODE 0x07000000
1287
1288 /* PCI/PCI-X/PCI-EX Config space */
1289 #define PCI_HEADER_TYPE_REGISTER 0x0E
1290 #define PCIE_LINK_STATUS 0x12
1291 #define PCIE_DEVICE_CONTROL2 0x28
1292
1293 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1294 #define PCIE_LINK_WIDTH_MASK 0x3F0
1295 #define PCIE_LINK_WIDTH_SHIFT 4
1296 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
1297
1298 #ifndef ETH_ADDR_LEN
1299 #define ETH_ADDR_LEN 6
1300 #endif
1301
1302 #define PHY_REVISION_MASK 0xFFFFFFF0
1303 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1304 #define MAX_PHY_MULTI_PAGE_REG 0xF
1305
1306 /* Bit definitions for valid PHY IDs. */
1307 /*
1308 * I = Integrated
1309 * E = External
1310 */
1311 #define M88E1000_E_PHY_ID 0x01410C50
1312 #define M88E1000_I_PHY_ID 0x01410C30
1313 #define M88E1011_I_PHY_ID 0x01410C20
1314 #define IGP01E1000_I_PHY_ID 0x02A80380
1315 #define M88E1011_I_REV_4 0x04
1316 #define M88E1111_I_PHY_ID 0x01410CC0
1317 #define GG82563_E_PHY_ID 0x01410CA0
1318 #define IGP03E1000_E_PHY_ID 0x02A80390
1319 #define IFE_E_PHY_ID 0x02A80330
1320 #define IFE_PLUS_E_PHY_ID 0x02A80320
1321 #define IFE_C_E_PHY_ID 0x02A80310
1322 #define I82580_I_PHY_ID 0x015403A0
1323 #define I350_I_PHY_ID 0x015403B0
1324 #define IGP04E1000_E_PHY_ID 0x02A80391
1325 #define M88_VENDOR 0x0141
1326
1327 /* M88E1000 Specific Registers */
1328 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1329 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1330 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1331 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1332 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1333 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1334
1335 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1336 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg29 for page number setting */
1337 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1338 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1339 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1340
1341 /* M88E1000 PHY Specific Control Register */
1342 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1343 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1344 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1345 /* 1=CLK125 low, 0=CLK125 toggling */
1346 #define M88E1000_PSCR_CLK125_DISABLE 0x0010
1347 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1348 /* Manual MDI configuration */
1349 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1350 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1351 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1352 /* Auto crossover enabled all speeds */
1353 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1354 /*
1355 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1356 * 0=Normal 10BASE-T Rx Threshold
1357 */
1358 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1359 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1360 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1361 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1362 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1363 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1364
1365 /* M88E1000 PHY Specific Status Register */
1366 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1367 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1368 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1369 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1370 /*
1371 * 0 = <50M
1372 * 1 = 50-80M
1373 * 2 = 80-110M
1374 * 3 = 110-140M
1375 * 4 = >140M
1376 */
1377 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1378 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1379 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1380 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1381 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1382 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1383 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1384 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1385 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1386
1387 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1388
1389 /* M88E1000 Extended PHY Specific Control Register */
1390 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1391 /*
1392 * 1 = Lost lock detect enabled.
1393 * Will assert lost lock and bring
1394 * link down if idle not seen
1395 * within 1ms in 1000BASE-T
1396 */
1397 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1398 /*
1399 * Number of times we will attempt to autonegotiate before downshifting if we
1400 * are the master
1401 */
1402 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1403 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1404 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1405 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1406 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1407 /*
1408 * Number of times we will attempt to autonegotiate before downshifting if we
1409 * are the slave
1410 */
1411 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1412 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1413 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1414 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1415 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1416 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
1417 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1418 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1419
1420 /* M88EC018 Rev 2 specific DownShift settings */
1421 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1422 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1423 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1424 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1425 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1426 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1427 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1428 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1429 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1430
1431 /*
1432 * Bits...
1433 * 15-5: page
1434 * 4-0: register offset
1435 */
1436 #define GG82563_PAGE_SHIFT 5
1437 #define GG82563_REG(page, reg) \
1438 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1439 #define GG82563_MIN_ALT_REG 30
1440
1441 /* GG82563 Specific Registers */
1442 #define GG82563_PHY_SPEC_CTRL \
1443 GG82563_REG(0, 16) /* PHY Specific Control */
1444 #define GG82563_PHY_SPEC_STATUS \
1445 GG82563_REG(0, 17) /* PHY Specific Status */
1446 #define GG82563_PHY_INT_ENABLE \
1447 GG82563_REG(0, 18) /* Interrupt Enable */
1448 #define GG82563_PHY_SPEC_STATUS_2 \
1449 GG82563_REG(0, 19) /* PHY Specific Status 2 */
1450 #define GG82563_PHY_RX_ERR_CNTR \
1451 GG82563_REG(0, 21) /* Receive Error Counter */
1452 #define GG82563_PHY_PAGE_SELECT \
1453 GG82563_REG(0, 22) /* Page Select */
1454 #define GG82563_PHY_SPEC_CTRL_2 \
1455 GG82563_REG(0, 26) /* PHY Specific Control 2 */
1456 #define GG82563_PHY_PAGE_SELECT_ALT \
1457 GG82563_REG(0, 29) /* Alternate Page Select */
1458 #define GG82563_PHY_TEST_CLK_CTRL \
1459 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
1460
1461 #define GG82563_PHY_MAC_SPEC_CTRL \
1462 GG82563_REG(2, 21) /* MAC Specific Control Register */
1463 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
1464 GG82563_REG(2, 26) /* MAC Specific Control 2 */
1465
1466 #define GG82563_PHY_DSP_DISTANCE \
1467 GG82563_REG(5, 26) /* DSP Distance */
1468
1469 /* Page 193 - Port Control Registers */
1470 #define GG82563_PHY_KMRN_MODE_CTRL \
1471 GG82563_REG(193, 16) /* Kumeran Mode Control */
1472 #define GG82563_PHY_PORT_RESET \
1473 GG82563_REG(193, 17) /* Port Reset */
1474 #define GG82563_PHY_REVISION_ID \
1475 GG82563_REG(193, 18) /* Revision ID */
1476 #define GG82563_PHY_DEVICE_ID \
1477 GG82563_REG(193, 19) /* Device ID */
1478 #define GG82563_PHY_PWR_MGMT_CTRL \
1479 GG82563_REG(193, 20) /* Power Management Control */
1480 #define GG82563_PHY_RATE_ADAPT_CTRL \
1481 GG82563_REG(193, 25) /* Rate Adaptation Control */
1482
1483 /* Page 194 - KMRN Registers */
1484 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1485 GG82563_REG(194, 16) /* FIFO's Control/Status */
1486 #define GG82563_PHY_KMRN_CTRL \
1487 GG82563_REG(194, 17) /* Control */
1488 #define GG82563_PHY_INBAND_CTRL \
1489 GG82563_REG(194, 18) /* Inband Control */
1490 #define GG82563_PHY_KMRN_DIAGNOSTIC \
1491 GG82563_REG(194, 19) /* Diagnostic */
1492 #define GG82563_PHY_ACK_TIMEOUTS \
1493 GG82563_REG(194, 20) /* Acknowledge Timeouts */
1494 #define GG82563_PHY_ADV_ABILITY \
1495 GG82563_REG(194, 21) /* Advertised Ability */
1496 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1497 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
1498 #define GG82563_PHY_ADV_NEXT_PAGE \
1499 GG82563_REG(194, 24) /* Advertised Next Page */
1500 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1501 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
1502 #define GG82563_PHY_KMRN_MISC \
1503 GG82563_REG(194, 26) /* Misc. */
1504
1505 /* MDI Control */
1506 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1507 #define E1000_MDIC_REG_MASK 0x001F0000
1508 #define E1000_MDIC_REG_SHIFT 16
1509 #define E1000_MDIC_PHY_MASK 0x03E00000
1510 #define E1000_MDIC_PHY_SHIFT 21
1511 #define E1000_MDIC_OP_WRITE 0x04000000
1512 #define E1000_MDIC_OP_READ 0x08000000
1513 #define E1000_MDIC_READY 0x10000000
1514 #define E1000_MDIC_INT_EN 0x20000000
1515 #define E1000_MDIC_ERROR 0x40000000
1516
1517 /* SerDes Control */
1518 #define E1000_GEN_CTL_READY 0x80000000
1519 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1520 #define E1000_GEN_POLL_TIMEOUT 640
1521
1522 /* LinkSec register fields */
1523 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1524 #define E1000_LSECTXCAP_SUM_SHIFT 16
1525 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1526 #define E1000_LSECRXCAP_SUM_SHIFT 16
1527
1528 #define E1000_LSECTXCTRL_EN_MASK 0x00000003
1529 #define E1000_LSECTXCTRL_DISABLE 0x0
1530 #define E1000_LSECTXCTRL_AUTH 0x1
1531 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1532 #define E1000_LSECTXCTRL_AISCI 0x00000020
1533 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1534 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1535
1536 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1537 #define E1000_LSECRXCTRL_EN_SHIFT 2
1538 #define E1000_LSECRXCTRL_DISABLE 0x0
1539 #define E1000_LSECRXCTRL_CHECK 0x1
1540 #define E1000_LSECRXCTRL_STRICT 0x2
1541 #define E1000_LSECRXCTRL_DROP 0x3
1542 #define E1000_LSECRXCTRL_PLSH 0x00000040
1543 #define E1000_LSECRXCTRL_RP 0x00000080
1544 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1545
1546 /* DMA Coalescing register fields */
1547
1548 /* DMA Coalescing Watchdog Timer */
1549 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
1550 /* DMA Coalescing Receive Threshold */
1551 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1552 #define E1000_DMACR_DMACTHR_SHIFT 16
1553 /* Lx when no PCIe transactions */
1554 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
1555 #define E1000_DMACR_DMAC_LX_SHIFT 28
1556 /* Enable DMA Coalescing */
1557 #define E1000_DMACR_DMAC_EN 0x80000000
1558 /* DMA Coalescing Transmit Threshold */
1559 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1560 /* Time to LX request */
1561 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF
1562 /* Receive Traffic Rate Threshold */
1563 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1564 /* Rcv packet rate in current window */
1565 #define E1000_DMCRTRH_LRPRCW 0x80000000
1566 /* DMA Coal Rcv Traffic Current Cnt */
1567 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1568 /* Flow ctrl Rcv Threshold High val */
1569 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1570 #define E1000_FCRTC_RTH_COAL_SHIFT 4
1571 /* Lx power decision based on DMA coal */
1572 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1573
1574 #ifdef __cplusplus
1575 }
1576 #endif
1577
1578 #endif /* _IGB_DEFINES_H */