3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.88.2.1 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_82575_H
33 #define _IGB_82575_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
40 (ID_LED_DEF1_DEF2 << 8) | \
41 (ID_LED_DEF1_DEF2 << 4) | \
42 (ID_LED_OFF1_ON2))
43
44 /*
45 * Receive Address Register Count
46 * Number of high/low register pairs in the RAR. The RAR (Receive Address
47 * Registers) holds the directed and multicast addresses that we monitor.
48 * These entries are also used for MAC-based filtering.
49 */
50 /*
51 * For 82576, there are an additional set of RARs that begin at an offset
52 * separate from the first set of RARs.
53 */
54 #define E1000_RAR_ENTRIES_82575 16
55 #define E1000_RAR_ENTRIES_82576 24
56 #define E1000_RAR_ENTRIES_82580 24
57 #define E1000_SW_SYNCH_MB 0x00000100
58 #define E1000_STAT_DEV_RST_SET 0x00100000
59 #define E1000_CTRL_DEV_RST 0x20000000
60
61 #ifdef E1000_BIT_FIELDS
62 struct e1000_adv_data_desc {
63 __le64 buffer_addr; /* Address of the descriptor's data buffer */
64 union {
65 u32 data;
66 struct {
67 u32 datalen :16; /* Data buffer length */
68 u32 rsvd :4;
69 u32 dtyp :4; /* Descriptor type */
70 u32 dcmd :8; /* Descriptor command */
71 } config;
72 } lower;
73 union {
74 u32 data;
75 struct {
76 u32 status :4; /* Descriptor status */
449
450 #define E1000_IOVCTL 0x05BBC
451 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
452
453 #define E1000_RPLOLR_STRVLAN 0x40000000
454 #define E1000_RPLOLR_STRCRC 0x80000000
455
456 #define E1000_DTXCTL_8023LL 0x0004
457 #define E1000_DTXCTL_VLAN_ADDED 0x0008
458 #define E1000_DTXCTL_OOS_ENABLE 0x0010
459 #define E1000_DTXCTL_MDP_EN 0x0020
460 #define E1000_DTXCTL_SPOOF_INT 0x0040
461
462 #define ALL_QUEUES 0xFFFF
463
464 /* RX packet buffer size defines */
465 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
466 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
467 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
468 u16 e1000_rxpbs_adjust_82580(u32 data);
469
470 #ifdef __cplusplus
471 }
472 #endif
473
474 #endif /* _IGB_82575_H */
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.88.2.1 v3_3_14_3_BHSW1 */
31
32 #ifndef _IGB_82575_H
33 #define _IGB_82575_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
40 (ID_LED_DEF1_DEF2 << 8) | \
41 (ID_LED_DEF1_DEF2 << 4) | \
42 (ID_LED_OFF1_ON2))
43
44 /*
45 * Receive Address Register Count
46 * Number of high/low register pairs in the RAR. The RAR (Receive Address
47 * Registers) holds the directed and multicast addresses that we monitor.
48 * These entries are also used for MAC-based filtering.
49 */
50 /*
51 * For 82576, there are an additional set of RARs that begin at an offset
52 * separate from the first set of RARs.
53 */
54 #define E1000_RAR_ENTRIES_82575 16
55 #define E1000_RAR_ENTRIES_82576 24
56 #define E1000_RAR_ENTRIES_82580 24
57 #define E1000_RAR_ENTRIES_I350 32
58 #define E1000_SW_SYNCH_MB 0x00000100
59 #define E1000_STAT_DEV_RST_SET 0x00100000
60 #define E1000_CTRL_DEV_RST 0x20000000
61
62 #ifdef E1000_BIT_FIELDS
63 struct e1000_adv_data_desc {
64 __le64 buffer_addr; /* Address of the descriptor's data buffer */
65 union {
66 u32 data;
67 struct {
68 u32 datalen :16; /* Data buffer length */
69 u32 rsvd :4;
70 u32 dtyp :4; /* Descriptor type */
71 u32 dcmd :8; /* Descriptor command */
72 } config;
73 } lower;
74 union {
75 u32 data;
76 struct {
77 u32 status :4; /* Descriptor status */
450
451 #define E1000_IOVCTL 0x05BBC
452 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
453
454 #define E1000_RPLOLR_STRVLAN 0x40000000
455 #define E1000_RPLOLR_STRCRC 0x80000000
456
457 #define E1000_DTXCTL_8023LL 0x0004
458 #define E1000_DTXCTL_VLAN_ADDED 0x0008
459 #define E1000_DTXCTL_OOS_ENABLE 0x0010
460 #define E1000_DTXCTL_MDP_EN 0x0020
461 #define E1000_DTXCTL_SPOOF_INT 0x0040
462
463 #define ALL_QUEUES 0xFFFF
464
465 /* RX packet buffer size defines */
466 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
467 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
468 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
469 u16 e1000_rxpbs_adjust_82580(u32 data);
470 s32 e1000_set_eee_i350(struct e1000_hw *hw);
471
472 #ifdef __cplusplus
473 }
474 #endif
475
476 #endif /* _IGB_82575_H */
|