3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.146.2.2 v3_3_14_3_BHSW1 */
31
32 /*
33 * 82575EB Gigabit Network Connection
34 * 82575EB Gigabit Backplane Connection
35 * 82575GB Gigabit Network Connection
36 * 82576 Gigabit Network Connection
37 * 82576 Quad Port Gigabit Mezzanine Adapter
38 */
39
40 #include "igb_api.h"
41
42 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
63 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
64 bool active);
65 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
66 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
67 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
68 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
69 u32 offset, u16 data);
70 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
71 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
72 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
73 u16 *speed, u16 *duplex);
74 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
75 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
76 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
77 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
78 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
80 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
81 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
82
83 static const u16 e1000_82580_rxpbs_table[] =
84 {36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140};
85 #define E1000_82580_RXPBS_TABLE_SIZE \
86 (sizeof (e1000_82580_rxpbs_table)/sizeof (u16))
87
88 /*
89 * e1000_init_phy_params_82575 - Init PHY func ptrs.
90 * @hw: pointer to the HW structure
91 */
92 static s32
93 e1000_init_phy_params_82575(struct e1000_hw *hw)
94 {
95 struct e1000_phy_info *phy = &hw->phy;
96 s32 ret_val = E1000_SUCCESS;
97
98 DEBUGFUNC("e1000_init_phy_params_82575");
99
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 goto out;
134 /* Verify phy id and set remaining function pointers */
135 switch (phy->id) {
136 case M88E1111_I_PHY_ID:
137 phy->type = e1000_phy_m88;
138 phy->ops.check_polarity = e1000_check_polarity_m88;
139 phy->ops.get_info = e1000_get_phy_info_m88;
140 phy->ops.get_cable_length = e1000_get_cable_length_m88;
141 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
142 break;
143 case IGP03E1000_E_PHY_ID:
144 case IGP04E1000_E_PHY_ID:
145 phy->type = e1000_phy_igp_3;
146 phy->ops.check_polarity = e1000_check_polarity_igp;
147 phy->ops.get_info = e1000_get_phy_info_igp;
148 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
149 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
150 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
151 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
152 break;
153 case I82580_I_PHY_ID:
154 phy->type = e1000_phy_82580;
155 phy->ops.check_polarity = e1000_check_polarity_82577;
156 phy->ops.force_speed_duplex =
157 e1000_phy_force_speed_duplex_82577;
158 phy->ops.get_cable_length = e1000_get_cable_length_82577;
159 phy->ops.get_info = e1000_get_phy_info_82577;
160 break;
161 default:
162 ret_val = -E1000_ERR_PHY;
163 goto out;
164 }
165
166 out:
167 return (ret_val);
168 }
169
170 /*
171 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
172 * @hw: pointer to the HW structure
173 */
205 /*
206 * Added to a constant, "size" becomes the left-shift value
207 * for setting word_size.
208 */
209 size += NVM_WORD_SIZE_BASE_SHIFT;
210
211 /* EEPROM access above 16k is unsupported */
212 if (size > 14)
213 size = 14;
214 nvm->word_size = 1 << size;
215
216 /* Function Pointers */
217 nvm->ops.acquire = e1000_acquire_nvm_82575;
218 nvm->ops.read = e1000_read_nvm_eerd;
219 nvm->ops.release = e1000_release_nvm_82575;
220 nvm->ops.update = e1000_update_nvm_checksum_generic;
221 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
222 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
223 nvm->ops.write = e1000_write_nvm_spi;
224
225 return (E1000_SUCCESS);
226 }
227
228 /*
229 * e1000_init_mac_params_82575 - Init MAC func ptrs.
230 * @hw: pointer to the HW structure
231 */
232 static s32
233 e1000_init_mac_params_82575(struct e1000_hw *hw)
234 {
235 struct e1000_mac_info *mac = &hw->mac;
236 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
237 u32 ctrl_ext = 0;
238
239 DEBUGFUNC("e1000_init_mac_params_82575");
240
241 /* Set media type */
242 /*
243 * The 82575 uses bits 22:23 for link mode. The mode can be changed
244 * based on the EEPROM. We cannot rely upon device ID. There
267
268 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
269
270 /*
271 * if using i2c make certain the MDICNFG register is cleared to prevent
272 * communications from being misrouted to the mdic registers
273 */
274 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
275 E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
276
277 /* Set mta register count */
278 mac->mta_reg_count = 128;
279 /* Set uta register count */
280 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
281 /* Set rar entry count */
282 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
283 if (mac->type == e1000_82576)
284 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
285 if (mac->type == e1000_82580)
286 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
287 /* Set if part includes ASF firmware */
288 mac->asf_firmware_present = true;
289 /* Set if manageability features are enabled. */
290 mac->arc_subsystem_valid =
291 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
292 ? true : false;
293
294 /* Function pointers */
295
296 /* bus type/speed/width */
297 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
298 /* reset */
299 if (mac->type == e1000_82580)
300 mac->ops.reset_hw = e1000_reset_hw_82580;
301 else
302 mac->ops.reset_hw = e1000_reset_hw_82575;
303 /* hw initialization */
304 mac->ops.init_hw = e1000_init_hw_82575;
305 /* link setup */
306 mac->ops.setup_link = e1000_setup_link_generic;
307 /* physical interface link setup */
308 mac->ops.setup_physical_interface =
309 (hw->phy.media_type == e1000_media_type_copper)
310 ? e1000_setup_copper_link_82575
311 : e1000_setup_serdes_link_82575;
312 /* physical interface shutdown */
313 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
314 /* check for link */
315 mac->ops.check_for_link = e1000_check_for_link_82575;
316 /* receive address register setting */
317 mac->ops.rar_set = e1000_rar_set_generic;
318 /* read mac address */
319 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
320 /* multicast address update */
321 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
322 /* writing VFTA */
323 mac->ops.write_vfta = e1000_write_vfta_generic;
324 /* clearing VFTA */
325 mac->ops.clear_vfta = e1000_clear_vfta_generic;
326 /* setting MTA */
327 mac->ops.mta_set = e1000_mta_set_generic;
328 /* ID LED init */
329 mac->ops.id_led_init = e1000_id_led_init_generic;
330 /* blink LED */
331 mac->ops.blink_led = e1000_blink_led_generic;
332 /* setup LED */
333 mac->ops.setup_led = e1000_setup_led_generic;
334 /* cleanup LED */
335 mac->ops.cleanup_led = e1000_cleanup_led_generic;
336 /* turn on/off LED */
337 mac->ops.led_on = e1000_led_on_generic;
338 mac->ops.led_off = e1000_led_off_generic;
339 /* clear hardware counters */
340 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
341 /* link info */
342 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
343
344 /* set lan id for port to determine which phy lock to use */
345 hw->mac.ops.set_lan_id(hw);
680 /*
681 * e1000_acquire_nvm_82575 - Request for access to EEPROM
682 * @hw: pointer to the HW structure
683 *
684 * Acquire the necessary semaphores for exclusive access to the EEPROM.
685 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
686 * Return successful if access grant bit set, else clear the request for
687 * EEPROM access and return -E1000_ERR_NVM (-1).
688 */
689 static s32
690 e1000_acquire_nvm_82575(struct e1000_hw *hw)
691 {
692 s32 ret_val;
693
694 DEBUGFUNC("e1000_acquire_nvm_82575");
695
696 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
697 if (ret_val)
698 goto out;
699
700 ret_val = e1000_acquire_nvm_generic(hw);
701
702 if (ret_val)
703 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
704
705 out:
706 return (ret_val);
707 }
708
709 /*
710 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
711 * @hw: pointer to the HW structure
712 *
713 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
714 * then release the semaphores acquired.
715 */
716 static void
717 e1000_release_nvm_82575(struct e1000_hw *hw)
718 {
719 DEBUGFUNC("e1000_release_nvm_82575");
1848
1849 /*
1850 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1851 * @data: data received by reading RXPBS register
1852 *
1853 * The 82580 uses a table based approach for packet buffer allocation sizes.
1854 * This function converts the retrieved value into the correct table value
1855 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1856 * 0x0 36 72 144 1 2 4 8 16
1857 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1858 */
1859 u16
1860 e1000_rxpbs_adjust_82580(u32 data)
1861 {
1862 u16 ret_val = 0;
1863
1864 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1865 ret_val = e1000_82580_rxpbs_table[data];
1866
1867 return (ret_val);
1868 }
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.146.2.2 v3_3_14_3_BHSW1 */
31
32 /*
33 * 82575EB Gigabit Network Connection
34 * 82575EB Gigabit Backplane Connection
35 * 82575GB Gigabit Network Connection
36 * 82576 Gigabit Network Connection
37 * 82576 Quad Port Gigabit Mezzanine Adapter
38 */
39
40 #include "igb_api.h"
41
42 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
63 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
64 bool active);
65 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
66 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
67 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
68 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
69 u32 offset, u16 data);
70 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
71 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
72 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
73 u16 *speed, u16 *duplex);
74 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
75 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
76 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
77 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
78 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
80 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
81 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
82
83 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
84 u16 offset);
85 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
86 u16 offset);
87 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
88 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
89 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
90 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
91
92 static const u16 e1000_82580_rxpbs_table[] =
93 {36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140};
94 #define E1000_82580_RXPBS_TABLE_SIZE \
95 (sizeof (e1000_82580_rxpbs_table)/sizeof (u16))
96
97 /*
98 * e1000_init_phy_params_82575 - Init PHY func ptrs.
99 * @hw: pointer to the HW structure
100 */
101 static s32
102 e1000_init_phy_params_82575(struct e1000_hw *hw)
103 {
104 struct e1000_phy_info *phy = &hw->phy;
105 s32 ret_val = E1000_SUCCESS;
106
107 DEBUGFUNC("e1000_init_phy_params_82575");
108
109 if (hw->phy.media_type != e1000_media_type_copper) {
110 phy->type = e1000_phy_none;
111 goto out;
143 /* Verify phy id and set remaining function pointers */
144 switch (phy->id) {
145 case M88E1111_I_PHY_ID:
146 phy->type = e1000_phy_m88;
147 phy->ops.check_polarity = e1000_check_polarity_m88;
148 phy->ops.get_info = e1000_get_phy_info_m88;
149 phy->ops.get_cable_length = e1000_get_cable_length_m88;
150 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
151 break;
152 case IGP03E1000_E_PHY_ID:
153 case IGP04E1000_E_PHY_ID:
154 phy->type = e1000_phy_igp_3;
155 phy->ops.check_polarity = e1000_check_polarity_igp;
156 phy->ops.get_info = e1000_get_phy_info_igp;
157 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
158 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
159 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
160 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
161 break;
162 case I82580_I_PHY_ID:
163 case I350_I_PHY_ID:
164 phy->type = e1000_phy_82580;
165 phy->ops.check_polarity = e1000_check_polarity_82577;
166 phy->ops.force_speed_duplex =
167 e1000_phy_force_speed_duplex_82577;
168 phy->ops.get_cable_length = e1000_get_cable_length_82577;
169 phy->ops.get_info = e1000_get_phy_info_82577;
170 break;
171 default:
172 ret_val = -E1000_ERR_PHY;
173 goto out;
174 }
175
176 out:
177 return (ret_val);
178 }
179
180 /*
181 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
182 * @hw: pointer to the HW structure
183 */
215 /*
216 * Added to a constant, "size" becomes the left-shift value
217 * for setting word_size.
218 */
219 size += NVM_WORD_SIZE_BASE_SHIFT;
220
221 /* EEPROM access above 16k is unsupported */
222 if (size > 14)
223 size = 14;
224 nvm->word_size = 1 << size;
225
226 /* Function Pointers */
227 nvm->ops.acquire = e1000_acquire_nvm_82575;
228 nvm->ops.read = e1000_read_nvm_eerd;
229 nvm->ops.release = e1000_release_nvm_82575;
230 nvm->ops.update = e1000_update_nvm_checksum_generic;
231 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
232 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
233 nvm->ops.write = e1000_write_nvm_spi;
234
235 /* override genric family function pointers for specific descendants */
236 switch (hw->mac.type) {
237 case e1000_i350:
238 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
239 nvm->ops.update = e1000_update_nvm_checksum_i350;
240 break;
241 default:
242 break;
243 }
244
245
246 return (E1000_SUCCESS);
247 }
248
249 /*
250 * e1000_init_mac_params_82575 - Init MAC func ptrs.
251 * @hw: pointer to the HW structure
252 */
253 static s32
254 e1000_init_mac_params_82575(struct e1000_hw *hw)
255 {
256 struct e1000_mac_info *mac = &hw->mac;
257 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
258 u32 ctrl_ext = 0;
259
260 DEBUGFUNC("e1000_init_mac_params_82575");
261
262 /* Set media type */
263 /*
264 * The 82575 uses bits 22:23 for link mode. The mode can be changed
265 * based on the EEPROM. We cannot rely upon device ID. There
288
289 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
290
291 /*
292 * if using i2c make certain the MDICNFG register is cleared to prevent
293 * communications from being misrouted to the mdic registers
294 */
295 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
296 E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
297
298 /* Set mta register count */
299 mac->mta_reg_count = 128;
300 /* Set uta register count */
301 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
302 /* Set rar entry count */
303 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
304 if (mac->type == e1000_82576)
305 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
306 if (mac->type == e1000_82580)
307 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
308 if (mac->type == e1000_i350) {
309 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
310 /* Enable EEE default settings for i350 */
311 dev_spec->eee_disable = B_FALSE;
312 }
313 /* Set if part includes ASF firmware */
314 mac->asf_firmware_present = true;
315 /* Set if manageability features are enabled. */
316 mac->arc_subsystem_valid =
317 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
318 ? true : false;
319
320 /* Function pointers */
321
322 /* bus type/speed/width */
323 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
324 /* reset */
325 if (mac->type == e1000_82580)
326 mac->ops.reset_hw = e1000_reset_hw_82580;
327 else
328 mac->ops.reset_hw = e1000_reset_hw_82575;
329 /* hw initialization */
330 mac->ops.init_hw = e1000_init_hw_82575;
331 /* link setup */
332 mac->ops.setup_link = e1000_setup_link_generic;
333 /* physical interface link setup */
334 mac->ops.setup_physical_interface =
335 (hw->phy.media_type == e1000_media_type_copper)
336 ? e1000_setup_copper_link_82575
337 : e1000_setup_serdes_link_82575;
338 /* physical interface shutdown */
339 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
340 /* check for link */
341 mac->ops.check_for_link = e1000_check_for_link_82575;
342 /* receive address register setting */
343 mac->ops.rar_set = e1000_rar_set_generic;
344 /* read mac address */
345 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
346 /* multicast address update */
347 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
348
349 if (hw->mac.type == e1000_i350) {
350 /* writing VFTA */
351 mac->ops.write_vfta = e1000_write_vfta_i350;
352 /* clearing VFTA */
353 mac->ops.clear_vfta = e1000_clear_vfta_i350;
354 } else {
355 /* writing VFTA */
356 mac->ops.write_vfta = e1000_write_vfta_generic;
357 /* clearing VFTA */
358 mac->ops.clear_vfta = e1000_clear_vfta_generic;
359 }
360 /* setting MTA */
361 mac->ops.mta_set = e1000_mta_set_generic;
362 /* ID LED init */
363 mac->ops.id_led_init = e1000_id_led_init_generic;
364 /* blink LED */
365 mac->ops.blink_led = e1000_blink_led_generic;
366 /* setup LED */
367 mac->ops.setup_led = e1000_setup_led_generic;
368 /* cleanup LED */
369 mac->ops.cleanup_led = e1000_cleanup_led_generic;
370 /* turn on/off LED */
371 mac->ops.led_on = e1000_led_on_generic;
372 mac->ops.led_off = e1000_led_off_generic;
373 /* clear hardware counters */
374 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
375 /* link info */
376 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
377
378 /* set lan id for port to determine which phy lock to use */
379 hw->mac.ops.set_lan_id(hw);
714 /*
715 * e1000_acquire_nvm_82575 - Request for access to EEPROM
716 * @hw: pointer to the HW structure
717 *
718 * Acquire the necessary semaphores for exclusive access to the EEPROM.
719 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
720 * Return successful if access grant bit set, else clear the request for
721 * EEPROM access and return -E1000_ERR_NVM (-1).
722 */
723 static s32
724 e1000_acquire_nvm_82575(struct e1000_hw *hw)
725 {
726 s32 ret_val;
727
728 DEBUGFUNC("e1000_acquire_nvm_82575");
729
730 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
731 if (ret_val)
732 goto out;
733
734 /*
735 * Check if there is some access
736 * error this access may hook on
737 */
738 if (hw->mac.type == e1000_i350) {
739 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
740 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
741 E1000_EECD_TIMEOUT)) {
742 /* Clear all access error flags */
743 E1000_WRITE_REG(hw, E1000_EECD, eecd |
744 E1000_EECD_ERROR_CLR);
745 DEBUGOUT("Nvm bit banging access error "
746 "detected and cleared.\n");
747 }
748 }
749
750 ret_val = e1000_acquire_nvm_generic(hw);
751
752 if (ret_val)
753 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
754
755 out:
756 return (ret_val);
757 }
758
759 /*
760 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
761 * @hw: pointer to the HW structure
762 *
763 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
764 * then release the semaphores acquired.
765 */
766 static void
767 e1000_release_nvm_82575(struct e1000_hw *hw)
768 {
769 DEBUGFUNC("e1000_release_nvm_82575");
1898
1899 /*
1900 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1901 * @data: data received by reading RXPBS register
1902 *
1903 * The 82580 uses a table based approach for packet buffer allocation sizes.
1904 * This function converts the retrieved value into the correct table value
1905 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1906 * 0x0 36 72 144 1 2 4 8 16
1907 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1908 */
1909 u16
1910 e1000_rxpbs_adjust_82580(u32 data)
1911 {
1912 u16 ret_val = 0;
1913
1914 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1915 ret_val = e1000_82580_rxpbs_table[data];
1916
1917 return (ret_val);
1918 }
1919
1920 /*
1921 * Due to a hw errata, if the host tries to configure the VFTA register
1922 * while performing queries from the BMC or DMA, then the VFTA in some
1923 * cases won't be written.
1924 */
1925
1926 /*
1927 * e1000_clear_vfta_i350 - Clear VLAN filter table
1928 * @hw: pointer to the HW structure
1929 *
1930 * Clears the register array which contains the VLAN filter table by
1931 * setting all the values to 0.
1932 */
1933 void
1934 e1000_clear_vfta_i350(struct e1000_hw *hw)
1935 {
1936 u32 offset;
1937 int i;
1938
1939 DEBUGFUNC("e1000_clear_vfta_350");
1940
1941 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1942 for (i = 0; i < 10; i++)
1943 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
1944
1945 E1000_WRITE_FLUSH(hw);
1946 }
1947 }
1948
1949 /*
1950 * e1000_write_vfta_i350 - Write value to VLAN filter table
1951 * @hw: pointer to the HW structure
1952 * @offset: register offset in VLAN filter table
1953 * @value: register value written to VLAN filter table
1954 *
1955 * Writes value at the given offset in the register array which stores
1956 * the VLAN filter table.
1957 */
1958 void
1959 e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
1960 {
1961 int i;
1962
1963 DEBUGFUNC("e1000_write_vfta_350");
1964
1965 for (i = 0; i < 10; i++)
1966 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1967
1968 E1000_WRITE_FLUSH(hw);
1969 }
1970
1971 /*
1972 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
1973 * checksum
1974 * @hw: pointer to the HW structure
1975 * @offset: offset in words of the checksum protected region
1976 *
1977 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1978 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1979 */
1980 s32
1981 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
1982 {
1983 s32 ret_val = E1000_SUCCESS;
1984 u16 checksum = 0;
1985 u16 i, nvm_data;
1986
1987 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
1988
1989 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
1990 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1991 if (ret_val) {
1992 DEBUGOUT("NVM Read Error\n");
1993 goto out;
1994 }
1995 checksum += nvm_data;
1996 }
1997
1998 if (checksum != (u16) NVM_SUM) {
1999 DEBUGOUT("NVM Checksum Invalid\n");
2000 ret_val = -E1000_ERR_NVM;
2001 goto out;
2002 }
2003
2004 out:
2005 return (ret_val);
2006 }
2007
2008 /*
2009 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2010 * checksum
2011 * @hw: pointer to the HW structure
2012 * @offset: offset in words of the checksum protected region
2013 *
2014 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2015 * up to the checksum. Then calculates the EEPROM checksum and writes the
2016 * value to the EEPROM.
2017 */
2018 s32
2019 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2020 {
2021 s32 ret_val;
2022 u16 checksum = 0;
2023 u16 i, nvm_data;
2024
2025 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2026
2027 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2028 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2029 if (ret_val) {
2030 DEBUGOUT("NVM Read Error while updating checksum.\n");
2031 goto out;
2032 }
2033 checksum += nvm_data;
2034 }
2035 checksum = (u16) NVM_SUM - checksum;
2036 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2037 &checksum);
2038 if (ret_val)
2039 DEBUGOUT("NVM Write Error while updating checksum.\n");
2040
2041 out:
2042 return (ret_val);
2043 }
2044
2045 /*
2046 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2047 * @hw: pointer to the HW structure
2048 *
2049 * Calculates the EEPROM section checksum by reading/adding each word of
2050 * the EEPROM and then verifies that the sum of the EEPROM is
2051 * equal to 0xBABA.
2052 */
2053 static s32
2054 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2055 {
2056 s32 ret_val = E1000_SUCCESS;
2057 u16 j;
2058 u16 nvm_offset;
2059
2060 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2061
2062 for (j = 0; j < 4; j++) {
2063 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2064 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2065 nvm_offset);
2066 if (ret_val != E1000_SUCCESS)
2067 goto out;
2068 }
2069
2070 out:
2071 return (ret_val);
2072 }
2073
2074 /*
2075 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2076 * @hw: pointer to the HW structure
2077 *
2078 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2079 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2080 * checksum and writes the value to the EEPROM.
2081 */
2082 static s32
2083 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2084 {
2085 s32 ret_val = E1000_SUCCESS;
2086 u16 j;
2087 u16 nvm_offset;
2088
2089 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2090
2091 for (j = 0; j < 4; j++) {
2092 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2093 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2094 if (ret_val != E1000_SUCCESS)
2095 goto out;
2096 }
2097
2098 out:
2099 return (ret_val);
2100 }
2101
2102
2103
2104 /*
2105 * e1000_set_eee_i350 - Enable/disable EEE support
2106 * @hw: pointer to the HW structure
2107 *
2108 * Enable/disable EEE based on setting in dev_spec structure.
2109 *
2110 */
2111 s32
2112 e1000_set_eee_i350(struct e1000_hw *hw)
2113 {
2114
2115 s32 ret_val = E1000_SUCCESS;
2116 u32 ipcnfg, eeer;
2117
2118 DEBUGFUNC("e1000_set_eee_i350");
2119
2120 if ((hw->mac.type < e1000_i350) ||
2121 (hw->phy.media_type != e1000_media_type_copper))
2122 goto out;
2123 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2124 eeer = E1000_READ_REG(hw, E1000_EEER);
2125
2126 /* enable or disable per user setting */
2127 if (!(hw->dev_spec._82575.eee_disable)) {
2128 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2129 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2130 E1000_EEER_LPI_FC);
2131
2132 } else {
2133 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2134 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2135 E1000_EEER_LPI_FC);
2136 }
2137 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2138 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2139 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2140 eeer = E1000_READ_REG(hw, E1000_EEER);
2141 out:
2142
2143 return (ret_val);
2144 }
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