1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 /* IntelVersion: 1.146.2.2 v3_3_14_3_BHSW1 */
31
32 /*
33 * 82575EB Gigabit Network Connection
34 * 82575EB Gigabit Backplane Connection
35 * 82575GB Gigabit Network Connection
36 * 82576 Gigabit Network Connection
37 * 82576 Quad Port Gigabit Mezzanine Adapter
38 */
39
40 #include "igb_api.h"
41
42 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
45 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
46 static void e1000_release_phy_82575(struct e1000_hw *hw);
47 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
48 static void e1000_release_nvm_82575(struct e1000_hw *hw);
49 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
50 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
51 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
52 u16 *duplex);
53 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
54 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
55 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
56 u16 *data);
57 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
58 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
59 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset,
62 u16 data);
63 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
64 bool active);
65 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
66 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
67 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
68 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
69 u32 offset, u16 data);
70 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
71 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
72 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
73 u16 *speed, u16 *duplex);
74 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
75 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
76 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
77 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
78 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
80 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
81 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
82
83 static const u16 e1000_82580_rxpbs_table[] =
84 {36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140};
85 #define E1000_82580_RXPBS_TABLE_SIZE \
86 (sizeof (e1000_82580_rxpbs_table)/sizeof (u16))
87
88 /*
89 * e1000_init_phy_params_82575 - Init PHY func ptrs.
90 * @hw: pointer to the HW structure
91 */
92 static s32
93 e1000_init_phy_params_82575(struct e1000_hw *hw)
94 {
95 struct e1000_phy_info *phy = &hw->phy;
96 s32 ret_val = E1000_SUCCESS;
97
98 DEBUGFUNC("e1000_init_phy_params_82575");
99
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 goto out;
103 }
104
105 phy->ops.power_up = e1000_power_up_phy_copper;
106 phy->ops.power_down = e1000_power_down_phy_copper_82575;
107
108 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
109 phy->reset_delay_us = 100;
110
111 phy->ops.acquire = e1000_acquire_phy_82575;
112 phy->ops.check_reset_block = e1000_check_reset_block_generic;
113 phy->ops.commit = e1000_phy_sw_reset_generic;
114 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
115 phy->ops.release = e1000_release_phy_82575;
116
117 if (e1000_sgmii_active_82575(hw)) {
118 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
119 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
120 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
121 } else if (hw->mac.type == e1000_82580) {
122 phy->ops.reset = e1000_phy_hw_reset_generic;
123 phy->ops.read_reg = e1000_read_phy_reg_82580;
124 phy->ops.write_reg = e1000_write_phy_reg_82580;
125 } else {
126 phy->ops.reset = e1000_phy_hw_reset_generic;
127 phy->ops.read_reg = e1000_read_phy_reg_igp;
128 phy->ops.write_reg = e1000_write_phy_reg_igp;
129 }
130
131 /* Set phy->phy_addr and phy->id. */
132 ret_val = e1000_get_phy_id_82575(hw);
133
134 /* Verify phy id and set remaining function pointers */
135 switch (phy->id) {
136 case M88E1111_I_PHY_ID:
137 phy->type = e1000_phy_m88;
138 phy->ops.check_polarity = e1000_check_polarity_m88;
139 phy->ops.get_info = e1000_get_phy_info_m88;
140 phy->ops.get_cable_length = e1000_get_cable_length_m88;
141 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
142 break;
143 case IGP03E1000_E_PHY_ID:
144 case IGP04E1000_E_PHY_ID:
145 phy->type = e1000_phy_igp_3;
146 phy->ops.check_polarity = e1000_check_polarity_igp;
147 phy->ops.get_info = e1000_get_phy_info_igp;
148 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
149 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
150 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
151 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
152 break;
153 case I82580_I_PHY_ID:
154 phy->type = e1000_phy_82580;
155 phy->ops.check_polarity = e1000_check_polarity_82577;
156 phy->ops.force_speed_duplex =
157 e1000_phy_force_speed_duplex_82577;
158 phy->ops.get_cable_length = e1000_get_cable_length_82577;
159 phy->ops.get_info = e1000_get_phy_info_82577;
160 break;
161 default:
162 ret_val = -E1000_ERR_PHY;
163 goto out;
164 }
165
166 out:
167 return (ret_val);
168 }
169
170 /*
171 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
172 * @hw: pointer to the HW structure
173 */
174 static s32
175 e1000_init_nvm_params_82575(struct e1000_hw *hw)
176 {
177 struct e1000_nvm_info *nvm = &hw->nvm;
178 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
179 u16 size;
180
181 DEBUGFUNC("e1000_init_nvm_params_82575");
182
183 nvm->opcode_bits = 8;
184 nvm->delay_usec = 1;
185 switch (nvm->override) {
186 case e1000_nvm_override_spi_large:
187 nvm->page_size = 32;
188 nvm->address_bits = 16;
189 break;
190 case e1000_nvm_override_spi_small:
191 nvm->page_size = 8;
192 nvm->address_bits = 8;
193 break;
194 default:
195 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
196 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
197 break;
198 }
199
200 nvm->type = e1000_nvm_eeprom_spi;
201
202 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
203 E1000_EECD_SIZE_EX_SHIFT);
204
205 /*
206 * Added to a constant, "size" becomes the left-shift value
207 * for setting word_size.
208 */
209 size += NVM_WORD_SIZE_BASE_SHIFT;
210
211 /* EEPROM access above 16k is unsupported */
212 if (size > 14)
213 size = 14;
214 nvm->word_size = 1 << size;
215
216 /* Function Pointers */
217 nvm->ops.acquire = e1000_acquire_nvm_82575;
218 nvm->ops.read = e1000_read_nvm_eerd;
219 nvm->ops.release = e1000_release_nvm_82575;
220 nvm->ops.update = e1000_update_nvm_checksum_generic;
221 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
222 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
223 nvm->ops.write = e1000_write_nvm_spi;
224
225 return (E1000_SUCCESS);
226 }
227
228 /*
229 * e1000_init_mac_params_82575 - Init MAC func ptrs.
230 * @hw: pointer to the HW structure
231 */
232 static s32
233 e1000_init_mac_params_82575(struct e1000_hw *hw)
234 {
235 struct e1000_mac_info *mac = &hw->mac;
236 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
237 u32 ctrl_ext = 0;
238
239 DEBUGFUNC("e1000_init_mac_params_82575");
240
241 /* Set media type */
242 /*
243 * The 82575 uses bits 22:23 for link mode. The mode can be changed
244 * based on the EEPROM. We cannot rely upon device ID. There
245 * is no distinguishable difference between fiber and internal
246 * SerDes mode on the 82575. There can be an external PHY attached
247 * on the SGMII interface. For this, we'll set sgmii_active to true.
248 */
249 hw->phy.media_type = e1000_media_type_copper;
250 dev_spec->sgmii_active = false;
251
252 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
253 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
254 case E1000_CTRL_EXT_LINK_MODE_SGMII:
255 dev_spec->sgmii_active = true;
256 ctrl_ext |= E1000_CTRL_I2C_ENA;
257 break;
258 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
259 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
260 hw->phy.media_type = e1000_media_type_internal_serdes;
261 ctrl_ext |= E1000_CTRL_I2C_ENA;
262 break;
263 default:
264 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
265 break;
266 }
267
268 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
269
270 /*
271 * if using i2c make certain the MDICNFG register is cleared to prevent
272 * communications from being misrouted to the mdic registers
273 */
274 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580))
275 E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
276
277 /* Set mta register count */
278 mac->mta_reg_count = 128;
279 /* Set uta register count */
280 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
281 /* Set rar entry count */
282 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
283 if (mac->type == e1000_82576)
284 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
285 if (mac->type == e1000_82580)
286 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
287 /* Set if part includes ASF firmware */
288 mac->asf_firmware_present = true;
289 /* Set if manageability features are enabled. */
290 mac->arc_subsystem_valid =
291 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
292 ? true : false;
293
294 /* Function pointers */
295
296 /* bus type/speed/width */
297 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
298 /* reset */
299 if (mac->type == e1000_82580)
300 mac->ops.reset_hw = e1000_reset_hw_82580;
301 else
302 mac->ops.reset_hw = e1000_reset_hw_82575;
303 /* hw initialization */
304 mac->ops.init_hw = e1000_init_hw_82575;
305 /* link setup */
306 mac->ops.setup_link = e1000_setup_link_generic;
307 /* physical interface link setup */
308 mac->ops.setup_physical_interface =
309 (hw->phy.media_type == e1000_media_type_copper)
310 ? e1000_setup_copper_link_82575
311 : e1000_setup_serdes_link_82575;
312 /* physical interface shutdown */
313 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
314 /* check for link */
315 mac->ops.check_for_link = e1000_check_for_link_82575;
316 /* receive address register setting */
317 mac->ops.rar_set = e1000_rar_set_generic;
318 /* read mac address */
319 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
320 /* multicast address update */
321 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
322 /* writing VFTA */
323 mac->ops.write_vfta = e1000_write_vfta_generic;
324 /* clearing VFTA */
325 mac->ops.clear_vfta = e1000_clear_vfta_generic;
326 /* setting MTA */
327 mac->ops.mta_set = e1000_mta_set_generic;
328 /* ID LED init */
329 mac->ops.id_led_init = e1000_id_led_init_generic;
330 /* blink LED */
331 mac->ops.blink_led = e1000_blink_led_generic;
332 /* setup LED */
333 mac->ops.setup_led = e1000_setup_led_generic;
334 /* cleanup LED */
335 mac->ops.cleanup_led = e1000_cleanup_led_generic;
336 /* turn on/off LED */
337 mac->ops.led_on = e1000_led_on_generic;
338 mac->ops.led_off = e1000_led_off_generic;
339 /* clear hardware counters */
340 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
341 /* link info */
342 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
343
344 /* set lan id for port to determine which phy lock to use */
345 hw->mac.ops.set_lan_id(hw);
346
347 return (E1000_SUCCESS);
348 }
349
350 /*
351 * e1000_init_function_pointers_82575 - Init func ptrs.
352 * @hw: pointer to the HW structure
353 *
354 * Called to initialize all function pointers and parameters.
355 */
356 void
357 e1000_init_function_pointers_82575(struct e1000_hw *hw)
358 {
359 DEBUGFUNC("e1000_init_function_pointers_82575");
360
361 hw->mac.ops.init_params = e1000_init_mac_params_82575;
362 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
363 hw->phy.ops.init_params = e1000_init_phy_params_82575;
364 }
365
366 /*
367 * e1000_acquire_phy_82575 - Acquire rights to access PHY
368 * @hw: pointer to the HW structure
369 *
370 * Acquire access rights to the correct PHY.
371 */
372 static s32
373 e1000_acquire_phy_82575(struct e1000_hw *hw)
374 {
375 u16 mask = E1000_SWFW_PHY0_SM;
376
377 DEBUGFUNC("e1000_acquire_phy_82575");
378
379 if (hw->bus.func == E1000_FUNC_1)
380 mask = E1000_SWFW_PHY1_SM;
381 else if (hw->bus.func == E1000_FUNC_2)
382 mask = E1000_SWFW_PHY2_SM;
383 else if (hw->bus.func == E1000_FUNC_3)
384 mask = E1000_SWFW_PHY3_SM;
385
386 return (e1000_acquire_swfw_sync_82575(hw, mask));
387 }
388
389 /*
390 * e1000_release_phy_82575 - Release rights to access PHY
391 * @hw: pointer to the HW structure
392 *
393 * A wrapper to release access rights to the correct PHY.
394 */
395 static void
396 e1000_release_phy_82575(struct e1000_hw *hw)
397 {
398 u16 mask = E1000_SWFW_PHY0_SM;
399
400 DEBUGFUNC("e1000_release_phy_82575");
401
402 if (hw->bus.func == E1000_FUNC_1)
403 mask = E1000_SWFW_PHY1_SM;
404 else if (hw->bus.func == E1000_FUNC_2)
405 mask = E1000_SWFW_PHY2_SM;
406 else if (hw->bus.func == E1000_FUNC_3)
407 mask = E1000_SWFW_PHY3_SM;
408
409 e1000_release_swfw_sync_82575(hw, mask);
410 }
411
412 /*
413 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
414 * @hw: pointer to the HW structure
415 * @offset: register offset to be read
416 * @data: pointer to the read data
417 *
418 * Reads the PHY register at offset using the serial gigabit media independent
419 * interface and stores the retrieved information in data.
420 */
421 static s32
422 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data)
423 {
424 s32 ret_val = -E1000_ERR_PARAM;
425
426 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
427
428 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
429 DEBUGOUT1("PHY Address %u is out of range\n", offset);
430 goto out;
431 }
432
433 ret_val = hw->phy.ops.acquire(hw);
434 if (ret_val)
435 goto out;
436
437 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
438
439 hw->phy.ops.release(hw);
440
441 out:
442 return (ret_val);
443 }
444
445 /*
446 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
447 * @hw: pointer to the HW structure
448 * @offset: register offset to write to
449 * @data: data to write at register offset
450 *
451 * Writes the data to PHY register at the offset using the serial gigabit
452 * media independent interface.
453 */
454 static s32
455 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 data)
456 {
457 s32 ret_val = -E1000_ERR_PARAM;
458
459 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
460
461 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
462 DEBUGOUT1("PHY Address %d is out of range\n", offset);
463 goto out;
464 }
465
466 ret_val = hw->phy.ops.acquire(hw);
467 if (ret_val)
468 goto out;
469
470 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
471
472 hw->phy.ops.release(hw);
473
474 out:
475 return (ret_val);
476 }
477
478 /*
479 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
480 * @hw: pointer to the HW structure
481 *
482 * Retrieves the PHY address and ID for both PHY's which do and do not use
483 * sgmi interface.
484 */
485 static s32
486 e1000_get_phy_id_82575(struct e1000_hw *hw)
487 {
488 struct e1000_phy_info *phy = &hw->phy;
489 s32 ret_val = E1000_SUCCESS;
490 u16 phy_id;
491 u32 ctrl_ext;
492
493 DEBUGFUNC("e1000_get_phy_id_82575");
494
495 /*
496 * For SGMII PHYs, we try the list of possible addresses until
497 * we find one that works. For non-SGMII PHYs
498 * (e.g. integrated copper PHYs), an address of 1 should
499 * work. The result of this function should mean phy->phy_addr
500 * and phy->id are set correctly.
501 */
502 if (!e1000_sgmii_active_82575(hw)) {
503 phy->addr = 1;
504 ret_val = e1000_get_phy_id(hw);
505 goto out;
506 }
507
508 /* Power on sgmii phy if it is disabled */
509 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
510 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
511 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
512 E1000_WRITE_FLUSH(hw);
513 msec_delay(300);
514
515 /*
516 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
517 * Therefore, we need to test 1-7
518 */
519 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
520 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
521 if (ret_val == E1000_SUCCESS) {
522 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
523 phy_id,
524 phy->addr);
525 /*
526 * At the time of this writing, The M88 part is
527 * the only supported SGMII PHY product.
528 */
529 if (phy_id == M88_VENDOR)
530 break;
531 } else {
532 DEBUGOUT1("PHY address %u was unreadable\n",
533 phy->addr);
534 }
535 }
536
537 /* A valid PHY type couldn't be found. */
538 if (phy->addr == 8) {
539 phy->addr = 0;
540 ret_val = -E1000_ERR_PHY;
541 } else {
542 ret_val = e1000_get_phy_id(hw);
543 }
544
545 /* restore previous sfp cage power state */
546 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
547
548 out:
549 return (ret_val);
550 }
551
552 /*
553 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
554 * @hw: pointer to the HW structure
555 *
556 * Resets the PHY using the serial gigabit media independent interface.
557 */
558 static s32
559 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
560 {
561 s32 ret_val = E1000_SUCCESS;
562
563 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
564
565 /*
566 * This isn't a true "hard" reset, but is the only reset
567 * available to us at this time.
568 */
569
570 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
571
572 if (!(hw->phy.ops.write_reg))
573 goto out;
574
575 /*
576 * SFP documentation requires the following to configure the SPF module
577 * to work on SGMII. No further documentation is given.
578 */
579 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
580 if (ret_val)
581 goto out;
582
583 ret_val = hw->phy.ops.commit(hw);
584
585 out:
586 return (ret_val);
587 }
588
589 /*
590 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
591 * @hw: pointer to the HW structure
592 * @active: true to enable LPLU, false to disable
593 *
594 * Sets the LPLU D0 state according to the active flag. When
595 * activating LPLU this function also disables smart speed
596 * and vice versa. LPLU will not be activated unless the
597 * device autonegotiation advertisement meets standards of
598 * either 10 or 10/100 or 10/100/1000 at all duplexes.
599 * This is a function pointer entry point only called by
600 * PHY setup routines.
601 */
602 static s32
603 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
604 {
605 struct e1000_phy_info *phy = &hw->phy;
606 s32 ret_val = E1000_SUCCESS;
607 u16 data;
608
609 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
610
611 if (!(hw->phy.ops.read_reg))
612 goto out;
613
614 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
615 if (ret_val)
616 goto out;
617
618 if (active) {
619 data |= IGP02E1000_PM_D0_LPLU;
620 ret_val = phy->ops.write_reg(hw,
621 IGP02E1000_PHY_POWER_MGMT,
622 data);
623 if (ret_val)
624 goto out;
625
626 /* When LPLU is enabled, we should disable SmartSpeed */
627 ret_val = phy->ops.read_reg(hw,
628 IGP01E1000_PHY_PORT_CONFIG,
629 &data);
630 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
631 ret_val = phy->ops.write_reg(hw,
632 IGP01E1000_PHY_PORT_CONFIG,
633 data);
634 if (ret_val)
635 goto out;
636 } else {
637 data &= ~IGP02E1000_PM_D0_LPLU;
638 ret_val = phy->ops.write_reg(hw,
639 IGP02E1000_PHY_POWER_MGMT,
640 data);
641 /*
642 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
643 * during Dx states where the power conservation is most
644 * important. During driver activity we should enable
645 * SmartSpeed, so performance is maintained.
646 */
647 if (phy->smart_speed == e1000_smart_speed_on) {
648 ret_val = phy->ops.read_reg(hw,
649 IGP01E1000_PHY_PORT_CONFIG,
650 &data);
651 if (ret_val)
652 goto out;
653
654 data |= IGP01E1000_PSCFR_SMART_SPEED;
655 ret_val = phy->ops.write_reg(hw,
656 IGP01E1000_PHY_PORT_CONFIG,
657 data);
658 if (ret_val)
659 goto out;
660 } else if (phy->smart_speed == e1000_smart_speed_off) {
661 ret_val = phy->ops.read_reg(hw,
662 IGP01E1000_PHY_PORT_CONFIG,
663 &data);
664 if (ret_val)
665 goto out;
666
667 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
668 ret_val = phy->ops.write_reg(hw,
669 IGP01E1000_PHY_PORT_CONFIG,
670 data);
671 if (ret_val)
672 goto out;
673 }
674 }
675
676 out:
677 return (ret_val);
678 }
679
680 /*
681 * e1000_acquire_nvm_82575 - Request for access to EEPROM
682 * @hw: pointer to the HW structure
683 *
684 * Acquire the necessary semaphores for exclusive access to the EEPROM.
685 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
686 * Return successful if access grant bit set, else clear the request for
687 * EEPROM access and return -E1000_ERR_NVM (-1).
688 */
689 static s32
690 e1000_acquire_nvm_82575(struct e1000_hw *hw)
691 {
692 s32 ret_val;
693
694 DEBUGFUNC("e1000_acquire_nvm_82575");
695
696 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
697 if (ret_val)
698 goto out;
699
700 ret_val = e1000_acquire_nvm_generic(hw);
701
702 if (ret_val)
703 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
704
705 out:
706 return (ret_val);
707 }
708
709 /*
710 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
711 * @hw: pointer to the HW structure
712 *
713 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
714 * then release the semaphores acquired.
715 */
716 static void
717 e1000_release_nvm_82575(struct e1000_hw *hw)
718 {
719 DEBUGFUNC("e1000_release_nvm_82575");
720
721 e1000_release_nvm_generic(hw);
722 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
723 }
724
725 /*
726 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
727 * @hw: pointer to the HW structure
728 * @mask: specifies which semaphore to acquire
729 *
730 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
731 * will also specify which port we're acquiring the lock for.
732 */
733 static s32
734 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
735 {
736 u32 swfw_sync;
737 u32 swmask = mask;
738 u32 fwmask = mask << 16;
739 s32 ret_val = E1000_SUCCESS;
740 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
741
742 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
743
744 while (i < timeout) {
745 if (e1000_get_hw_semaphore_generic(hw)) {
746 ret_val = -E1000_ERR_SWFW_SYNC;
747 goto out;
748 }
749
750 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
751 if (!(swfw_sync & (fwmask | swmask)))
752 break;
753
754 /*
755 * Firmware currently using resource (fwmask)
756 * or other software thread using resource (swmask)
757 */
758 e1000_put_hw_semaphore_generic(hw);
759 msec_delay_irq(5);
760 i++;
761 }
762
763 if (i == timeout) {
764 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
765 ret_val = -E1000_ERR_SWFW_SYNC;
766 goto out;
767 }
768
769 swfw_sync |= swmask;
770 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
771
772 e1000_put_hw_semaphore_generic(hw);
773
774 out:
775 return (ret_val);
776 }
777
778 /*
779 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
780 * @hw: pointer to the HW structure
781 * @mask: specifies which semaphore to acquire
782 *
783 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
784 * will also specify which port we're releasing the lock for.
785 */
786 static void
787 e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
788 {
789 u32 swfw_sync;
790
791 DEBUGFUNC("e1000_release_swfw_sync_82575");
792
793 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) {
794 /* Empty */
795 }
796
797 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
798 swfw_sync &= ~mask;
799 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
800
801 e1000_put_hw_semaphore_generic(hw);
802 }
803
804 /*
805 * e1000_get_cfg_done_82575 - Read config done bit
806 * @hw: pointer to the HW structure
807 *
808 * Read the management control register for the config done bit for
809 * completion status. NOTE: silicon which is EEPROM-less will fail trying
810 * to read the config done bit, so an error is *ONLY* logged and returns
811 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
812 * would not be able to be reset or change link.
813 */
814 static s32
815 e1000_get_cfg_done_82575(struct e1000_hw *hw)
816 {
817 s32 timeout = PHY_CFG_TIMEOUT;
818 s32 ret_val = E1000_SUCCESS;
819 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
820
821 DEBUGFUNC("e1000_get_cfg_done_82575");
822
823 if (hw->bus.func == E1000_FUNC_1)
824 mask = E1000_NVM_CFG_DONE_PORT_1;
825 else if (hw->bus.func == E1000_FUNC_2)
826 mask = E1000_NVM_CFG_DONE_PORT_2;
827 else if (hw->bus.func == E1000_FUNC_3)
828 mask = E1000_NVM_CFG_DONE_PORT_3;
829
830 while (timeout) {
831 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
832 break;
833 msec_delay(1);
834 timeout--;
835 }
836 if (!timeout)
837 DEBUGOUT("MNG configuration cycle has not completed.\n");
838
839 /* If EEPROM is not marked present, init the PHY manually */
840 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
841 (hw->phy.type == e1000_phy_igp_3))
842 (void) e1000_phy_init_script_igp3(hw);
843
844 return (ret_val);
845 }
846
847 /*
848 * e1000_get_link_up_info_82575 - Get link speed/duplex info
849 * @hw: pointer to the HW structure
850 * @speed: stores the current speed
851 * @duplex: stores the current duplex
852 *
853 * This is a wrapper function, if using the serial gigabit media independent
854 * interface, use PCS to retrieve the link speed and duplex information.
855 * Otherwise, use the generic function to get the link speed and duplex info.
856 */
857 static s32
858 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, u16 *duplex)
859 {
860 s32 ret_val;
861
862 DEBUGFUNC("e1000_get_link_up_info_82575");
863
864 if (hw->phy.media_type != e1000_media_type_copper)
865 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
866 duplex);
867 else
868 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
869 duplex);
870
871 return (ret_val);
872 }
873
874 /*
875 * e1000_check_for_link_82575 - Check for link
876 * @hw: pointer to the HW structure
877 *
878 * If sgmii is enabled, then use the pcs register to determine link, otherwise
879 * use the generic interface for determining link.
880 */
881 static s32
882 e1000_check_for_link_82575(struct e1000_hw *hw)
883 {
884 s32 ret_val;
885 u16 speed, duplex;
886
887 DEBUGFUNC("e1000_check_for_link_82575");
888
889 /* SGMII link check is done through the PCS register. */
890 if (hw->phy.media_type != e1000_media_type_copper) {
891 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
892 &duplex);
893 /*
894 * Use this flag to determine if link needs to be checked or
895 * not. If we have link clear the flag so that we do not
896 * continue to check for link.
897 */
898 hw->mac.get_link_status = !hw->mac.serdes_has_link;
899 } else {
900 ret_val = e1000_check_for_copper_link_generic(hw);
901 }
902
903 return (ret_val);
904 }
905
906 /*
907 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
908 * @hw: pointer to the HW structure
909 * @speed: stores the current speed
910 * @duplex: stores the current duplex
911 *
912 * Using the physical coding sub-layer (PCS), retrieve the current speed and
913 * duplex, then store the values in the pointers provided.
914 */
915 static s32
916 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
917 u16 *speed, u16 *duplex)
918 {
919 struct e1000_mac_info *mac = &hw->mac;
920 u32 pcs;
921
922 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
923
924 /* Set up defaults for the return values of this function */
925 mac->serdes_has_link = false;
926 *speed = 0;
927 *duplex = 0;
928
929 /*
930 * Read the PCS Status register for link state. For non-copper mode,
931 * the status register is not accurate. The PCS status register is
932 * used instead.
933 */
934 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
935
936 /*
937 * The link up bit determines when link is up on autoneg. The sync ok
938 * gets set once both sides sync up and agree upon link. Stable link
939 * can be determined by checking for both link up and link sync ok
940 */
941 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
942 mac->serdes_has_link = true;
943
944 /* Detect and store PCS speed */
945 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
946 *speed = SPEED_1000;
947 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
948 *speed = SPEED_100;
949 } else {
950 *speed = SPEED_10;
951 }
952
953 /* Detect and store PCS duplex */
954 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
955 *duplex = FULL_DUPLEX;
956 } else {
957 *duplex = HALF_DUPLEX;
958 }
959 }
960
961 return (E1000_SUCCESS);
962 }
963
964 /*
965 * e1000_shutdown_serdes_link_82575 - Remove link during power down
966 * @hw: pointer to the HW structure
967 *
968 * In the case of serdes shut down sfp and PCS on driver unload
969 * when management pass thru is not enabled.
970 */
971 void
972 e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
973 {
974 u32 reg;
975 u16 eeprom_data = 0;
976
977 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
978 !e1000_sgmii_active_82575(hw))
979 return;
980
981 if (hw->bus.func == E1000_FUNC_0)
982 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
983 else if (hw->mac.type == e1000_82580)
984 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
985 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
986 &eeprom_data);
987 else if (hw->bus.func == E1000_FUNC_1)
988 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
989
990 /*
991 * If APM is not enabled in the EEPROM and management interface is
992 * not enabled, then power down.
993 */
994 if (!(eeprom_data & E1000_NVM_APME_82575) &&
995 !e1000_enable_mng_pass_thru(hw)) {
996 /* Disable PCS to turn off link */
997 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
998 reg &= ~E1000_PCS_CFG_PCS_EN;
999 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1000
1001 /* shutdown the laser */
1002 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1003 reg |= E1000_CTRL_EXT_SDP3_DATA;
1004 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1005
1006 /* flush the write to verify completion */
1007 E1000_WRITE_FLUSH(hw);
1008 msec_delay(1);
1009 }
1010 }
1011
1012 /*
1013 * e1000_reset_hw_82575 - Reset hardware
1014 * @hw: pointer to the HW structure
1015 *
1016 * This resets the hardware into a known state.
1017 */
1018 static s32
1019 e1000_reset_hw_82575(struct e1000_hw *hw)
1020 {
1021 u32 ctrl;
1022 s32 ret_val;
1023
1024 DEBUGFUNC("e1000_reset_hw_82575");
1025
1026 /*
1027 * Prevent the PCI-E bus from sticking if there is no TLP connection
1028 * on the last TLP read/write transaction when MAC is reset.
1029 */
1030 ret_val = e1000_disable_pcie_master_generic(hw);
1031 if (ret_val) {
1032 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1033 }
1034
1035 /* set the completion timeout for interface */
1036 ret_val = e1000_set_pcie_completion_timeout(hw);
1037 if (ret_val) {
1038 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1039 }
1040
1041 DEBUGOUT("Masking off all interrupts\n");
1042 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1043
1044 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1045 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1046 E1000_WRITE_FLUSH(hw);
1047
1048 msec_delay(10);
1049
1050 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1051
1052 DEBUGOUT("Issuing a global reset to MAC\n");
1053 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1054
1055 ret_val = e1000_get_auto_rd_done_generic(hw);
1056 if (ret_val) {
1057 /*
1058 * When auto config read does not complete, do not
1059 * return with an error. This can happen in situations
1060 * where there is no eeprom and prevents getting link.
1061 */
1062 DEBUGOUT("Auto Read Done did not complete\n");
1063 }
1064
1065 /* If EEPROM is not present, run manual init scripts */
1066 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1067 (void) e1000_reset_init_script_82575(hw);
1068
1069 /* Clear any pending interrupt events. */
1070 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1071 (void) E1000_READ_REG(hw, E1000_ICR);
1072
1073 /* Install any alternate MAC address into RAR0 */
1074 ret_val = e1000_check_alt_mac_addr_generic(hw);
1075
1076 return (ret_val);
1077 }
1078
1079 /*
1080 * e1000_init_hw_82575 - Initialize hardware
1081 * @hw: pointer to the HW structure
1082 *
1083 * This inits the hardware readying it for operation.
1084 */
1085 static s32
1086 e1000_init_hw_82575(struct e1000_hw *hw)
1087 {
1088 struct e1000_mac_info *mac = &hw->mac;
1089 s32 ret_val;
1090 u16 i, rar_count = mac->rar_entry_count;
1091
1092 DEBUGFUNC("e1000_init_hw_82575");
1093
1094 /* Initialize identification LED */
1095 ret_val = mac->ops.id_led_init(hw);
1096 if (ret_val) {
1097 DEBUGOUT("Error initializing identification LED\n");
1098 /* This is not fatal and we should not stop init due to this */
1099 }
1100
1101 /* Disabling VLAN filtering */
1102 DEBUGOUT("Initializing the IEEE VLAN\n");
1103 mac->ops.clear_vfta(hw);
1104
1105 /* Setup the receive address */
1106 e1000_init_rx_addrs_generic(hw, rar_count);
1107 /* Zero out the Multicast HASH table */
1108 DEBUGOUT("Zeroing the MTA\n");
1109 for (i = 0; i < mac->mta_reg_count; i++)
1110 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1111
1112 /* Zero out the Unicast HASH table */
1113 DEBUGOUT("Zeroing the UTA\n");
1114 for (i = 0; i < mac->uta_reg_count; i++)
1115 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1116
1117 /* Setup link and flow control */
1118 ret_val = mac->ops.setup_link(hw);
1119
1120 /*
1121 * Clear all of the statistics registers (clear on read). It is
1122 * important that we do this after we have tried to establish link
1123 * because the symbol error count will increment wildly if there
1124 * is no link.
1125 */
1126 e1000_clear_hw_cntrs_82575(hw);
1127
1128 return (ret_val);
1129 }
1130
1131 /*
1132 * e1000_setup_copper_link_82575 - Configure copper link settings
1133 * @hw: pointer to the HW structure
1134 *
1135 * Configures the link for auto-neg or forced speed and duplex. Then we check
1136 * for link, once link is established calls to configure collision distance
1137 * and flow control are called.
1138 */
1139 static s32
1140 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1141 {
1142 u32 ctrl;
1143 s32 ret_val;
1144
1145 DEBUGFUNC("e1000_setup_copper_link_82575");
1146
1147 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1148 ctrl |= E1000_CTRL_SLU;
1149 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1150 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1151
1152 ret_val = e1000_setup_serdes_link_82575(hw);
1153 if (ret_val)
1154 goto out;
1155
1156 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1157 /* allow time for SFP cage time to power up phy */
1158 msec_delay(300);
1159
1160 ret_val = hw->phy.ops.reset(hw);
1161 if (ret_val) {
1162 DEBUGOUT("Error resetting the PHY.\n");
1163 goto out;
1164 }
1165 }
1166 switch (hw->phy.type) {
1167 case e1000_phy_m88:
1168 ret_val = e1000_copper_link_setup_m88(hw);
1169 break;
1170 case e1000_phy_igp_3:
1171 ret_val = e1000_copper_link_setup_igp(hw);
1172 break;
1173 case e1000_phy_82580:
1174 ret_val = e1000_copper_link_setup_82577(hw);
1175 break;
1176 default:
1177 ret_val = -E1000_ERR_PHY;
1178 break;
1179 }
1180
1181 if (ret_val)
1182 goto out;
1183
1184 ret_val = e1000_setup_copper_link_generic(hw);
1185 out:
1186 return (ret_val);
1187 }
1188
1189 /*
1190 * e1000_setup_serdes_link_82575 - Setup link for serdes
1191 * @hw: pointer to the HW structure
1192 *
1193 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1194 * used on copper connections where the serialized gigabit media independent
1195 * interface (sgmii), or serdes fiber is being used. Configures the link
1196 * for auto-negotiation or forces speed/duplex.
1197 */
1198 static s32
1199 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1200 {
1201 u32 ctrl_ext, ctrl_reg, reg;
1202 bool pcs_autoneg;
1203
1204 DEBUGFUNC("e1000_setup_serdes_link_82575");
1205
1206 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1207 !e1000_sgmii_active_82575(hw))
1208 return (E1000_SUCCESS);
1209
1210 /*
1211 * On the 82575, SerDes loopback mode persists until it is
1212 * explicitly turned off or a power cycle is performed. A read to
1213 * the register does not indicate its status. Therefore, we ensure
1214 * loopback mode is disabled during initialization.
1215 */
1216 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1217
1218 /* power on the sfp cage if present */
1219 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1220 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1221 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1222
1223 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1224 ctrl_reg |= E1000_CTRL_SLU;
1225
1226 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1227 /* set both sw defined pins */
1228 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1229
1230 /* Set switch control to serdes energy detect */
1231 reg = E1000_READ_REG(hw, E1000_CONNSW);
1232 reg |= E1000_CONNSW_ENRGSRC;
1233 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1234 }
1235
1236 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1237
1238 /* default pcs_autoneg to the same setting as mac autoneg */
1239 pcs_autoneg = hw->mac.autoneg;
1240
1241 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1242 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1243 /* sgmii mode lets the phy handle forcing speed/duplex */
1244 pcs_autoneg = true;
1245 /* autoneg time out should be disabled for SGMII mode */
1246 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1247 break;
1248 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1249 /* disable PCS autoneg and support parallel detect only */
1250 pcs_autoneg = false;
1251 default:
1252 /*
1253 * non-SGMII modes only supports a speed of 1000/Full for the
1254 * link so it is best to just force the MAC and let the pcs
1255 * link either autoneg or be forced to 1000/Full
1256 */
1257 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1258 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1259
1260 /* set speed of 1000/Full if speed/duplex is forced */
1261 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1262 break;
1263 }
1264
1265 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1266
1267 /*
1268 * New SerDes mode allows for forcing speed or autonegotiating speed
1269 * at 1gb. Autoneg should be default set by most drivers. This is the
1270 * mode that will be compatible with older link partners and switches.
1271 * However, both are supported by the hardware and some drivers/tools.
1272 */
1273
1274 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1275 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1276
1277 /*
1278 * We force flow control to prevent the CTRL register values from being
1279 * overwritten by the autonegotiated flow control values
1280 */
1281 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1282
1283 if (pcs_autoneg) {
1284 /* Set PCS register for autoneg */
1285 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1286 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1287 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1288 } else {
1289 /* Set PCS register for forced link */
1290 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1291 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1292 }
1293
1294 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1295
1296 if (!e1000_sgmii_active_82575(hw))
1297 (void) e1000_force_mac_fc_generic(hw);
1298
1299 return (E1000_SUCCESS);
1300 }
1301
1302 /*
1303 * e1000_valid_led_default_82575 - Verify a valid default LED config
1304 * @hw: pointer to the HW structure
1305 * @data: pointer to the NVM (EEPROM)
1306 *
1307 * Read the EEPROM for the current default LED configuration. If the
1308 * LED configuration is not valid, set to a valid LED configuration.
1309 */
1310 static s32
1311 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1312 {
1313 s32 ret_val;
1314
1315 DEBUGFUNC("e1000_valid_led_default_82575");
1316
1317 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1318 if (ret_val) {
1319 DEBUGOUT("NVM Read Error\n");
1320 goto out;
1321 }
1322
1323 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1324 switch (hw->phy.media_type) {
1325 case e1000_media_type_internal_serdes:
1326 *data = ID_LED_DEFAULT_82575_SERDES;
1327 break;
1328 case e1000_media_type_copper:
1329 default:
1330 *data = ID_LED_DEFAULT;
1331 break;
1332 }
1333 }
1334 out:
1335 return (ret_val);
1336 }
1337
1338 /*
1339 * e1000_sgmii_active_82575 - Return sgmii state
1340 * @hw: pointer to the HW structure
1341 *
1342 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1343 * which can be enabled for use in the embedded applications. Simply
1344 * return the current state of the sgmii interface.
1345 */
1346 static bool
1347 e1000_sgmii_active_82575(struct e1000_hw *hw)
1348 {
1349 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1350 return (dev_spec->sgmii_active);
1351 }
1352
1353 /*
1354 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1355 * @hw: pointer to the HW structure
1356 *
1357 * Inits recommended HW defaults after a reset when there is no EEPROM
1358 * detected. This is only for the 82575.
1359 */
1360 static s32
1361 e1000_reset_init_script_82575(struct e1000_hw *hw)
1362 {
1363 DEBUGFUNC("e1000_reset_init_script_82575");
1364
1365 if (hw->mac.type == e1000_82575) {
1366 DEBUGOUT("Running reset init script for 82575\n");
1367 /* SerDes configuration via SERDESCTRL */
1368 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL,
1369 0x00, 0x0C);
1370 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL,
1371 0x01, 0x78);
1372 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL,
1373 0x1B, 0x23);
1374 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL,
1375 0x23, 0x15);
1376
1377 /* CCM configuration via CCMCTL register */
1378 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL,
1379 0x14, 0x00);
1380 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL,
1381 0x10, 0x00);
1382
1383 /* PCIe lanes configuration */
1384 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL,
1385 0x00, 0xEC);
1386 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL,
1387 0x61, 0xDF);
1388 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL,
1389 0x34, 0x05);
1390 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL,
1391 0x2F, 0x81);
1392
1393 /* PCIe PLL Configuration */
1394 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL,
1395 0x02, 0x47);
1396 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL,
1397 0x14, 0x00);
1398 (void) e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL,
1399 0x10, 0x00);
1400 }
1401
1402 return (E1000_SUCCESS);
1403 }
1404
1405 /*
1406 * e1000_read_mac_addr_82575 - Read device MAC address
1407 * @hw: pointer to the HW structure
1408 */
1409 static s32
1410 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1411 {
1412 s32 ret_val = E1000_SUCCESS;
1413
1414 DEBUGFUNC("e1000_read_mac_addr_82575");
1415
1416 /*
1417 * If there's an alternate MAC address place it in RAR0
1418 * so that it will override the Si installed default perm
1419 * address.
1420 */
1421 ret_val = e1000_check_alt_mac_addr_generic(hw);
1422 if (ret_val)
1423 goto out;
1424
1425 ret_val = e1000_read_mac_addr_generic(hw);
1426
1427 out:
1428 return (ret_val);
1429 }
1430
1431 /*
1432 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1433 * @hw: pointer to the HW structure
1434 *
1435 * In the case of a PHY power down to save power, or to turn off link during a
1436 * driver unload, or wake on lan is not enabled, remove the link.
1437 */
1438 static void
1439 e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1440 {
1441 struct e1000_phy_info *phy = &hw->phy;
1442 struct e1000_mac_info *mac = &hw->mac;
1443
1444 if (!(phy->ops.check_reset_block))
1445 return;
1446
1447 /* If the management interface is not enabled, then power down */
1448 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1449 e1000_power_down_phy_copper(hw);
1450 }
1451
1452 /*
1453 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1454 * @hw: pointer to the HW structure
1455 *
1456 * Clears the hardware counters by reading the counter registers.
1457 */
1458 static void
1459 e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1460 {
1461 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
1462
1463 e1000_clear_hw_cntrs_base_generic(hw);
1464
1465 (void) E1000_READ_REG(hw, E1000_PRC64);
1466 (void) E1000_READ_REG(hw, E1000_PRC127);
1467 (void) E1000_READ_REG(hw, E1000_PRC255);
1468 (void) E1000_READ_REG(hw, E1000_PRC511);
1469 (void) E1000_READ_REG(hw, E1000_PRC1023);
1470 (void) E1000_READ_REG(hw, E1000_PRC1522);
1471 (void) E1000_READ_REG(hw, E1000_PTC64);
1472 (void) E1000_READ_REG(hw, E1000_PTC127);
1473 (void) E1000_READ_REG(hw, E1000_PTC255);
1474 (void) E1000_READ_REG(hw, E1000_PTC511);
1475 (void) E1000_READ_REG(hw, E1000_PTC1023);
1476 (void) E1000_READ_REG(hw, E1000_PTC1522);
1477
1478 (void) E1000_READ_REG(hw, E1000_ALGNERRC);
1479 (void) E1000_READ_REG(hw, E1000_RXERRC);
1480 (void) E1000_READ_REG(hw, E1000_TNCRS);
1481 (void) E1000_READ_REG(hw, E1000_CEXTERR);
1482 (void) E1000_READ_REG(hw, E1000_TSCTC);
1483 (void) E1000_READ_REG(hw, E1000_TSCTFC);
1484
1485 (void) E1000_READ_REG(hw, E1000_MGTPRC);
1486 (void) E1000_READ_REG(hw, E1000_MGTPDC);
1487 (void) E1000_READ_REG(hw, E1000_MGTPTC);
1488
1489 (void) E1000_READ_REG(hw, E1000_IAC);
1490 (void) E1000_READ_REG(hw, E1000_ICRXOC);
1491
1492 (void) E1000_READ_REG(hw, E1000_ICRXPTC);
1493 (void) E1000_READ_REG(hw, E1000_ICRXATC);
1494 (void) E1000_READ_REG(hw, E1000_ICTXPTC);
1495 (void) E1000_READ_REG(hw, E1000_ICTXATC);
1496 (void) E1000_READ_REG(hw, E1000_ICTXQEC);
1497 (void) E1000_READ_REG(hw, E1000_ICTXQMTC);
1498 (void) E1000_READ_REG(hw, E1000_ICRXDMTC);
1499
1500 (void) E1000_READ_REG(hw, E1000_CBTMPC);
1501 (void) E1000_READ_REG(hw, E1000_HTDPMC);
1502 (void) E1000_READ_REG(hw, E1000_CBRMPC);
1503 (void) E1000_READ_REG(hw, E1000_RPTHC);
1504 (void) E1000_READ_REG(hw, E1000_HGPTC);
1505 (void) E1000_READ_REG(hw, E1000_HTCBDPC);
1506 (void) E1000_READ_REG(hw, E1000_HGORCL);
1507 (void) E1000_READ_REG(hw, E1000_HGORCH);
1508 (void) E1000_READ_REG(hw, E1000_HGOTCL);
1509 (void) E1000_READ_REG(hw, E1000_HGOTCH);
1510 (void) E1000_READ_REG(hw, E1000_LENERRS);
1511
1512 /* This register should not be read in copper configurations */
1513 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1514 e1000_sgmii_active_82575(hw))
1515 (void) E1000_READ_REG(hw, E1000_SCVPC);
1516 }
1517
1518 /*
1519 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1520 * @hw: pointer to the HW structure
1521 *
1522 * After rx enable if managability is enabled then there is likely some
1523 * bad data at the start of the fifo and possibly in the DMA fifo. This
1524 * function clears the fifos and flushes any packets that came in as rx was
1525 * being enabled.
1526 */
1527 void
1528 e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1529 {
1530 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1531 int i, ms_wait;
1532
1533 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1534 if (hw->mac.type != e1000_82575 ||
1535 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1536 return;
1537
1538 /* Disable all RX queues */
1539 for (i = 0; i < 4; i++) {
1540 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1541 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1542 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1543 }
1544 /* Poll all queues to verify they have shut down */
1545 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1546 msec_delay(1);
1547 rx_enabled = 0;
1548 for (i = 0; i < 4; i++)
1549 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1550 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1551 break;
1552 }
1553
1554 if (ms_wait == 10)
1555 DEBUGOUT("Queue disable timed out after 10ms\n");
1556
1557 /*
1558 * Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1559 * incoming packets are rejected. Set enable and wait 2ms so that
1560 * any packet that was coming in as RCTL.EN was set is flushed
1561 */
1562 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1563 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1564
1565 rlpml = E1000_READ_REG(hw, E1000_RLPML);
1566 E1000_WRITE_REG(hw, E1000_RLPML, 0);
1567
1568 rctl = E1000_READ_REG(hw, E1000_RCTL);
1569 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1570 temp_rctl |= E1000_RCTL_LPE;
1571
1572 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1573 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1574 E1000_WRITE_FLUSH(hw);
1575 msec_delay(2);
1576
1577 /*
1578 * Enable RX queues that were previously enabled and restore our
1579 * previous state
1580 */
1581 for (i = 0; i < 4; i++)
1582 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1583 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1584 E1000_WRITE_FLUSH(hw);
1585
1586 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1587 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1588
1589 /* Flush receive errors generated by workaround */
1590 (void) E1000_READ_REG(hw, E1000_ROC);
1591 (void) E1000_READ_REG(hw, E1000_RNBC);
1592 (void) E1000_READ_REG(hw, E1000_MPC);
1593 }
1594
1595 /*
1596 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
1597 * @hw: pointer to the HW structure
1598 *
1599 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1600 * however the hardware default for these parts is 500us to 1ms which is less
1601 * than the 10ms recommended by the pci-e spec. To address this we need to
1602 * increase the value to either 10ms to 200ms for capability version 1 config,
1603 * or 16ms to 55ms for version 2.
1604 */
1605 static s32
1606 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
1607 {
1608 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
1609 s32 ret_val = E1000_SUCCESS;
1610 u16 pcie_devctl2;
1611
1612 /* only take action if timeout value is defaulted to 0 */
1613 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1614 goto out;
1615
1616 /*
1617 * if capababilities version is type 1 we can write the
1618 * timeout of 10ms to 200ms through the GCR register
1619 */
1620 if (!(gcr & E1000_GCR_CAP_VER2)) {
1621 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1622 goto out;
1623 }
1624
1625 /*
1626 * for version 2 capabilities we need to write the config space
1627 * directly in order to set the completion timeout value for
1628 * 16ms to 55ms
1629 */
1630 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1631 &pcie_devctl2);
1632 if (ret_val)
1633 goto out;
1634
1635 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1636
1637 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1638 &pcie_devctl2);
1639 out:
1640 /* disable completion timeout resend */
1641 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1642
1643 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1644 return (ret_val);
1645 }
1646
1647 /*
1648 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1649 * @hw: pointer to the hardware struct
1650 * @enable: state to enter, either enabled or disabled
1651 *
1652 * enables/disables L2 switch loopback functionality.
1653 */
1654 void
1655 e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1656 {
1657 u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1658
1659 if (enable)
1660 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1661 else
1662 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1663
1664 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1665 }
1666
1667 /*
1668 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
1669 * @hw: pointer to the hardware struct
1670 * @enable: state to enter, either enabled or disabled
1671 *
1672 * enables/disables replication of packets across multiple pools.
1673 */
1674 void
1675 e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1676 {
1677 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1678
1679 if (enable)
1680 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1681 else
1682 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1683
1684 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1685 }
1686
1687 /*
1688 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
1689 * @hw: pointer to the HW structure
1690 * @offset: register offset to be read
1691 * @data: pointer to the read data
1692 *
1693 * Reads the MDI control register in the PHY at offset and stores the
1694 * information read to data.
1695 */
1696 static s32
1697 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1698 {
1699 u32 mdicnfg = 0;
1700 s32 ret_val;
1701
1702 DEBUGFUNC("e1000_read_phy_reg_82580");
1703
1704 ret_val = hw->phy.ops.acquire(hw);
1705 if (ret_val)
1706 goto out;
1707
1708 /*
1709 * We config the phy address in MDICNFG register now. Same bits
1710 * as before. The values in MDIC can be written but will be
1711 * ignored. This allows us to call the old function after
1712 * configuring the PHY address in the new register
1713 */
1714 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1715 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1716
1717 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
1718
1719 hw->phy.ops.release(hw);
1720
1721 out:
1722 return (ret_val);
1723 }
1724
1725 /*
1726 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
1727 * @hw: pointer to the HW structure
1728 * @offset: register offset to write to
1729 * @data: data to write to register at offset
1730 *
1731 * Writes data to MDI control register in the PHY at offset.
1732 */
1733 static s32
1734 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1735 {
1736 u32 mdicnfg = 0;
1737 s32 ret_val;
1738
1739 DEBUGFUNC("e1000_write_phy_reg_82580");
1740
1741 ret_val = hw->phy.ops.acquire(hw);
1742 if (ret_val)
1743 goto out;
1744
1745 /*
1746 * We config the phy address in MDICNFG register now. Same bits
1747 * as before. The values in MDIC can be written but will be
1748 * ignored. This allows us to call the old function after
1749 * configuring the PHY address in the new register
1750 */
1751 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1752 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1753
1754 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
1755
1756 hw->phy.ops.release(hw);
1757
1758 out:
1759 return (ret_val);
1760 }
1761
1762 /*
1763 * e1000_reset_hw_82580 - Reset hardware
1764 * @hw: pointer to the HW structure
1765 *
1766 * This resets function or entire device (all ports, etc.)
1767 * to a known state.
1768 */
1769 static s32
1770 e1000_reset_hw_82580(struct e1000_hw *hw)
1771 {
1772 s32 ret_val = E1000_SUCCESS;
1773 /* BH SW mailbox bit in SW_FW_SYNC */
1774 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1775 u32 ctrl;
1776 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1777
1778 DEBUGFUNC("e1000_reset_hw_82580");
1779
1780 hw->dev_spec._82575.global_device_reset = false;
1781
1782 /* Get current control state. */
1783 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1784
1785 /*
1786 * Prevent the PCI-E bus from sticking if there is no TLP connection
1787 * on the last TLP read/write transaction when MAC is reset.
1788 */
1789 ret_val = e1000_disable_pcie_master_generic(hw);
1790 if (ret_val)
1791 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1792
1793 DEBUGOUT("Masking off all interrupts\n");
1794 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1795 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1796 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1797 E1000_WRITE_FLUSH(hw);
1798
1799 msec_delay(10);
1800
1801 /* Determine whether or not a global dev reset is requested */
1802 if (global_device_reset &&
1803 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
1804 global_device_reset = false;
1805
1806 if (global_device_reset &&
1807 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1808 ctrl |= E1000_CTRL_DEV_RST;
1809 else
1810 ctrl |= E1000_CTRL_RST;
1811
1812 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1813
1814 /* Add delay to insure DEV_RST has time to complete */
1815 if (global_device_reset)
1816 msec_delay(5);
1817
1818 ret_val = e1000_get_auto_rd_done_generic(hw);
1819 if (ret_val) {
1820 /*
1821 * When auto config read does not complete, do not
1822 * return with an error. This can happen in situations
1823 * where there is no eeprom and prevents getting link.
1824 */
1825 DEBUGOUT("Auto Read Done did not complete\n");
1826 }
1827
1828 /* If EEPROM is not present, run manual init scripts */
1829 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1830 (void) e1000_reset_init_script_82575(hw);
1831
1832 /* clear global device reset status bit */
1833 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
1834
1835 /* Clear any pending interrupt events. */
1836 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1837 (void) E1000_READ_REG(hw, E1000_ICR);
1838
1839 /* Install any alternate MAC address into RAR0 */
1840 ret_val = e1000_check_alt_mac_addr_generic(hw);
1841
1842 /* Release semaphore */
1843 if (global_device_reset)
1844 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
1845
1846 return (ret_val);
1847 }
1848
1849 /*
1850 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1851 * @data: data received by reading RXPBS register
1852 *
1853 * The 82580 uses a table based approach for packet buffer allocation sizes.
1854 * This function converts the retrieved value into the correct table value
1855 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1856 * 0x0 36 72 144 1 2 4 8 16
1857 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1858 */
1859 u16
1860 e1000_rxpbs_adjust_82580(u32 data)
1861 {
1862 u16 ret_val = 0;
1863
1864 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1865 ret_val = e1000_82580_rxpbs_table[data];
1866
1867 return (ret_val);
1868 }