Print this page
6064 ixgbe needs X550 support
Reviewed by: Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Dan McDonald <danmcd@omniti.com>
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/ixgbe/ixgbe_sw.h
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_sw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
|
↓ open down ↓ |
18 lines elided |
↑ open up ↑ |
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 + * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
29 30 */
30 31
31 32 #ifndef _IXGBE_SW_H
32 33 #define _IXGBE_SW_H
33 34
34 35 #ifdef __cplusplus
35 36 extern "C" {
36 37 #endif
37 38
38 39 #include <sys/types.h>
39 40 #include <sys/conf.h>
40 41 #include <sys/debug.h>
41 42 #include <sys/stropts.h>
42 43 #include <sys/stream.h>
43 44 #include <sys/strsun.h>
44 45 #include <sys/strlog.h>
45 46 #include <sys/kmem.h>
46 47 #include <sys/stat.h>
47 48 #include <sys/kstat.h>
48 49 #include <sys/modctl.h>
49 50 #include <sys/errno.h>
50 51 #include <sys/dlpi.h>
51 52 #include <sys/mac_provider.h>
52 53 #include <sys/mac_ether.h>
53 54 #include <sys/vlan.h>
54 55 #include <sys/ddi.h>
55 56 #include <sys/sunddi.h>
56 57 #include <sys/pci.h>
57 58 #include <sys/pcie.h>
58 59 #include <sys/sdt.h>
59 60 #include <sys/ethernet.h>
60 61 #include <sys/pattr.h>
61 62 #include <sys/strsubr.h>
62 63 #include <sys/netlb.h>
63 64 #include <sys/random.h>
64 65 #include <inet/common.h>
65 66 #include <inet/tcp.h>
66 67 #include <inet/ip.h>
67 68 #include <inet/mi.h>
68 69 #include <inet/nd.h>
69 70 #include <sys/bitmap.h>
70 71 #include <sys/ddifm.h>
71 72 #include <sys/fm/protocol.h>
72 73 #include <sys/fm/util.h>
73 74 #include <sys/disp.h>
74 75 #include <sys/fm/io/ddi.h>
75 76 #include "ixgbe_api.h"
76 77
77 78 #define MODULE_NAME "ixgbe" /* module name */
78 79
79 80 #define IXGBE_FAILURE DDI_FAILURE
80 81
81 82 #define IXGBE_UNKNOWN 0x00
82 83 #define IXGBE_INITIALIZED 0x01
83 84 #define IXGBE_STARTED 0x02
84 85 #define IXGBE_SUSPENDED 0x04
85 86 #define IXGBE_STALL 0x08
86 87 #define IXGBE_OVERTEMP 0x20
87 88 #define IXGBE_INTR_ADJUST 0x40
88 89 #define IXGBE_ERROR 0x80
89 90
90 91 #define MAX_NUM_UNICAST_ADDRESSES 0x80
91 92 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
92 93 #define IXGBE_INTR_NONE 0
93 94 #define IXGBE_INTR_MSIX 1
94 95 #define IXGBE_INTR_MSI 2
95 96 #define IXGBE_INTR_LEGACY 3
96 97
97 98 #define IXGBE_POLL_NULL -1
98 99
99 100 #define MAX_COOKIE 18
100 101 #define MIN_NUM_TX_DESC 2
101 102
102 103 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
103 104
104 105 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
105 106
106 107 #define IXGBE_RX_STOPPED 0x1
107 108
108 109 #define IXGBE_PKG_BUF_16k 16384
109 110
110 111 /*
111 112 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
112 113 * supported silicon types.
113 114 */
114 115 #define MAX_TX_QUEUE_NUM 128
115 116 #define MAX_RX_QUEUE_NUM 128
116 117 #define MAX_INTR_VECTOR 64
117 118
118 119 /*
119 120 * Maximum values for user configurable parameters
120 121 */
121 122 #define MAX_TX_RING_SIZE 4096
122 123 #define MAX_RX_RING_SIZE 4096
123 124
124 125 #define MAX_RX_LIMIT_PER_INTR 4096
125 126
126 127 #define MAX_RX_COPY_THRESHOLD 9216
127 128 #define MAX_TX_COPY_THRESHOLD 9216
128 129 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
129 130 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
130 131 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
131 132
132 133 /*
133 134 * Minimum values for user configurable parameters
134 135 */
135 136 #define MIN_TX_RING_SIZE 64
136 137 #define MIN_RX_RING_SIZE 64
137 138
138 139 #define MIN_MTU ETHERMIN
139 140 #define MIN_RX_LIMIT_PER_INTR 16
140 141 #define MIN_TX_COPY_THRESHOLD 0
141 142 #define MIN_RX_COPY_THRESHOLD 0
142 143 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
143 144 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
144 145 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
145 146
146 147 /*
147 148 * Default values for user configurable parameters
148 149 */
149 150 #define DEFAULT_TX_RING_SIZE 1024
150 151 #define DEFAULT_RX_RING_SIZE 1024
151 152
152 153 #define DEFAULT_MTU ETHERMTU
153 154 #define DEFAULT_RX_LIMIT_PER_INTR 256
154 155 #define DEFAULT_RX_COPY_THRESHOLD 128
155 156 #define DEFAULT_TX_COPY_THRESHOLD 512
156 157 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
157 158 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
158 159 #define DEFAULT_TX_RESCHED_THRESHOLD 128
159 160 #define DEFAULT_FCRTH 0x20000
160 161 #define DEFAULT_FCRTL 0x10000
161 162 #define DEFAULT_FCPAUSE 0xFFFF
162 163
163 164 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
164 165 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
165 166 #define DEFAULT_LSO_ENABLE B_TRUE
166 167 #define DEFAULT_LRO_ENABLE B_FALSE
167 168 #define DEFAULT_MR_ENABLE B_TRUE
168 169 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
169 170 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
170 171 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
171 172
172 173 #define IXGBE_LSO_MAXLEN 65535
173 174
174 175 #define TX_DRAIN_TIME 200
175 176 #define RX_DRAIN_TIME 200
176 177
177 178 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
178 179 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
179 180
180 181 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
181 182
182 183 /*
183 184 * Extra register bit masks for 82598
184 185 */
185 186 #define IXGBE_PCS1GANA_FDC 0x20
186 187 #define IXGBE_PCS1GANLP_LPFD 0x20
187 188 #define IXGBE_PCS1GANLP_LPHD 0x40
188 189
189 190 /*
190 191 * Defined for IP header alignment.
191 192 */
192 193 #define IPHDR_ALIGN_ROOM 2
193 194
194 195 /*
195 196 * Bit flags for attach_progress
196 197 */
197 198 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
198 199 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
199 200 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
200 201 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
201 202 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
|
↓ open down ↓ |
163 lines elided |
↑ open up ↑ |
202 203 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
203 204 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
204 205 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
205 206 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
206 207 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
207 208 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
208 209 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
209 210 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
210 211 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
211 212 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
213 +#define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
212 214
213 215 #define PROP_DEFAULT_MTU "default_mtu"
214 216 #define PROP_FLOW_CONTROL "flow_control"
215 217 #define PROP_TX_QUEUE_NUM "tx_queue_number"
216 218 #define PROP_TX_RING_SIZE "tx_ring_size"
217 219 #define PROP_RX_QUEUE_NUM "rx_queue_number"
218 220 #define PROP_RX_RING_SIZE "rx_ring_size"
219 221 #define PROP_RX_GROUP_NUM "rx_group_number"
220 222
221 223 #define PROP_INTR_FORCE "intr_force"
222 224 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
223 225 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
224 226 #define PROP_LSO_ENABLE "lso_enable"
225 227 #define PROP_LRO_ENABLE "lro_enable"
226 228 #define PROP_MR_ENABLE "mr_enable"
227 229 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
228 230 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
229 231 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
230 232 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
231 233 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
232 234 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
233 235 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
234 236 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
235 237 #define PROP_INTR_THROTTLING "intr_throttling"
236 238 #define PROP_FM_CAPABLE "fm_capable"
237 239 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
238 240
239 241 #define IXGBE_LB_NONE 0
240 242 #define IXGBE_LB_EXTERNAL 1
241 243 #define IXGBE_LB_INTERNAL_MAC 2
242 244 #define IXGBE_LB_INTERNAL_PHY 3
243 245 #define IXGBE_LB_INTERNAL_SERDES 4
244 246
245 247 /*
246 248 * capability/feature flags
247 249 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
248 250 * Separately, the flag named _ENABLED is set when the feature is enabled.
249 251 */
250 252 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
251 253 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
252 254 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
253 255 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
254 256 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
255 257 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
256 258 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
257 259 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
258 260 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
259 261 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
260 262 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
261 263 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
262 264
263 265 /*
264 266 * Classification mode
265 267 */
266 268 #define IXGBE_CLASSIFY_NONE 0
267 269 #define IXGBE_CLASSIFY_RSS 1
268 270 #define IXGBE_CLASSIFY_VMDQ 2
269 271 #define IXGBE_CLASSIFY_VMDQ_RSS 3
270 272
271 273 /* adapter-specific info for each supported device type */
272 274 typedef struct adapter_info {
273 275 uint32_t max_rx_que_num; /* maximum number of rx queues */
274 276 uint32_t min_rx_que_num; /* minimum number of rx queues */
275 277 uint32_t def_rx_que_num; /* default number of rx queues */
276 278 uint32_t max_rx_grp_num; /* maximum number of rx groups */
277 279 uint32_t min_rx_grp_num; /* minimum number of rx groups */
278 280 uint32_t def_rx_grp_num; /* default number of rx groups */
279 281 uint32_t max_tx_que_num; /* maximum number of tx queues */
280 282 uint32_t min_tx_que_num; /* minimum number of tx queues */
281 283 uint32_t def_tx_que_num; /* default number of tx queues */
282 284 uint32_t max_mtu; /* maximum MTU size */
283 285 /*
284 286 * Interrupt throttling is in unit of 256 nsec
285 287 */
286 288 uint32_t max_intr_throttle; /* maximum interrupt throttle */
287 289 uint32_t min_intr_throttle; /* minimum interrupt throttle */
288 290 uint32_t def_intr_throttle; /* default interrupt throttle */
289 291
290 292 uint32_t max_msix_vect; /* maximum total msix vectors */
291 293 uint32_t max_ring_vect; /* maximum number of ring vectors */
292 294 uint32_t max_other_vect; /* maximum number of other vectors */
293 295 uint32_t other_intr; /* "other" interrupt types handled */
294 296 uint32_t other_gpie; /* "other" interrupt types enabling */
295 297 uint32_t flags; /* capability flags */
296 298 } adapter_info_t;
297 299
298 300 /* bits representing all interrupt types other than tx & rx */
299 301 #define IXGBE_OTHER_INTR 0x3ff00000
300 302 #define IXGBE_82599_OTHER_INTR 0x86100000
301 303
302 304 enum ioc_reply {
303 305 IOC_INVAL = -1, /* bad, NAK with EINVAL */
304 306 IOC_DONE, /* OK, reply sent */
305 307 IOC_ACK, /* OK, just send ACK */
306 308 IOC_REPLY /* OK, just send reply */
307 309 };
308 310
309 311 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
310 312 0, 0, (flag)))
311 313
312 314 /*
313 315 * Defined for ring index operations
314 316 * ASSERT(index < limit)
315 317 * ASSERT(step < limit)
316 318 * ASSERT(index1 < limit)
317 319 * ASSERT(index2 < limit)
318 320 */
319 321 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
320 322 (index) + (step) : (index) + (step) - (limit))
321 323 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
322 324 (index) - (step) : (index) + (limit) - (step))
323 325 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
324 326 (index2) - (index1) : (index2) + (limit) - (index1))
325 327
326 328 #define LINK_LIST_INIT(_LH) \
327 329 (_LH)->head = (_LH)->tail = NULL
328 330
329 331 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
330 332
331 333 #define LIST_POP_HEAD(_LH) \
332 334 (single_link_t *)(_LH)->head; \
333 335 { \
334 336 if ((_LH)->head != NULL) { \
335 337 (_LH)->head = (_LH)->head->link; \
336 338 if ((_LH)->head == NULL) \
337 339 (_LH)->tail = NULL; \
338 340 } \
339 341 }
340 342
341 343 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
342 344
343 345 #define LIST_PUSH_TAIL(_LH, _E) \
344 346 if ((_LH)->tail != NULL) { \
345 347 (_LH)->tail->link = (single_link_t *)(_E); \
346 348 (_LH)->tail = (single_link_t *)(_E); \
347 349 } else { \
348 350 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
349 351 } \
350 352 (_E)->link = NULL;
351 353
352 354 #define LIST_GET_NEXT(_LH, _E) \
353 355 (((_LH)->tail == (single_link_t *)(_E)) ? \
354 356 NULL : ((single_link_t *)(_E))->link)
355 357
356 358
357 359 typedef struct single_link {
358 360 struct single_link *link;
359 361 } single_link_t;
360 362
361 363 typedef struct link_list {
362 364 single_link_t *head;
363 365 single_link_t *tail;
364 366 } link_list_t;
365 367
366 368 /*
367 369 * Property lookups
368 370 */
369 371 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
370 372 DDI_PROP_DONTPASS, (n))
371 373 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
372 374 DDI_PROP_DONTPASS, (n), -1)
373 375
374 376
375 377 typedef union ixgbe_ether_addr {
376 378 struct {
377 379 uint32_t high;
378 380 uint32_t low;
379 381 } reg;
380 382 struct {
381 383 uint8_t set;
382 384 uint8_t group_index;
383 385 uint8_t addr[ETHERADDRL];
384 386 } mac;
385 387 } ixgbe_ether_addr_t;
386 388
387 389 typedef enum {
388 390 USE_NONE,
389 391 USE_COPY,
390 392 USE_DMA
391 393 } tx_type_t;
392 394
393 395 typedef struct ixgbe_tx_context {
394 396 uint32_t hcksum_flags;
395 397 uint32_t ip_hdr_len;
396 398 uint32_t mac_hdr_len;
397 399 uint32_t l4_proto;
398 400 uint32_t mss;
399 401 uint32_t l4_hdr_len;
400 402 boolean_t lso_flag;
401 403 } ixgbe_tx_context_t;
402 404
403 405 /*
404 406 * Hold address/length of each DMA segment
405 407 */
406 408 typedef struct sw_desc {
407 409 uint64_t address;
408 410 size_t length;
409 411 } sw_desc_t;
410 412
411 413 /*
412 414 * Handles and addresses of DMA buffer
413 415 */
414 416 typedef struct dma_buffer {
415 417 caddr_t address; /* Virtual address */
416 418 uint64_t dma_address; /* DMA (Hardware) address */
417 419 ddi_acc_handle_t acc_handle; /* Data access handle */
418 420 ddi_dma_handle_t dma_handle; /* DMA handle */
419 421 size_t size; /* Buffer size */
420 422 size_t len; /* Data length in the buffer */
421 423 } dma_buffer_t;
422 424
423 425 /*
424 426 * Tx Control Block
425 427 */
426 428 typedef struct tx_control_block {
427 429 single_link_t link;
428 430 uint32_t last_index; /* last descriptor of the pkt */
429 431 uint32_t frag_num;
430 432 uint32_t desc_num;
431 433 mblk_t *mp;
432 434 tx_type_t tx_type;
433 435 ddi_dma_handle_t tx_dma_handle;
434 436 dma_buffer_t tx_buf;
435 437 sw_desc_t desc[MAX_COOKIE];
436 438 } tx_control_block_t;
437 439
438 440 /*
439 441 * RX Control Block
440 442 */
441 443 typedef struct rx_control_block {
442 444 mblk_t *mp;
443 445 uint32_t ref_cnt;
444 446 dma_buffer_t rx_buf;
445 447 frtn_t free_rtn;
446 448 struct ixgbe_rx_data *rx_data;
447 449 int lro_next; /* Index of next rcb */
448 450 int lro_prev; /* Index of previous rcb */
449 451 boolean_t lro_pkt; /* Flag for LRO rcb */
450 452 } rx_control_block_t;
451 453
452 454 /*
453 455 * Software Data Structure for Tx Ring
454 456 */
455 457 typedef struct ixgbe_tx_ring {
456 458 uint32_t index; /* Ring index */
457 459 uint32_t intr_vector; /* Interrupt vector index */
458 460 uint32_t vect_bit; /* vector's bit in register */
459 461
460 462 /*
461 463 * Mutexes
462 464 */
463 465 kmutex_t tx_lock;
464 466 kmutex_t recycle_lock;
465 467 kmutex_t tcb_head_lock;
466 468 kmutex_t tcb_tail_lock;
467 469
468 470 /*
469 471 * Tx descriptor ring definitions
470 472 */
471 473 dma_buffer_t tbd_area;
472 474 union ixgbe_adv_tx_desc *tbd_ring;
473 475 uint32_t tbd_head; /* Index of next tbd to recycle */
474 476 uint32_t tbd_tail; /* Index of next tbd to transmit */
475 477 uint32_t tbd_free; /* Number of free tbd */
476 478
477 479 /*
478 480 * Tx control block list definitions
479 481 */
480 482 tx_control_block_t *tcb_area;
481 483 tx_control_block_t **work_list;
482 484 tx_control_block_t **free_list;
483 485 uint32_t tcb_head; /* Head index of free list */
484 486 uint32_t tcb_tail; /* Tail index of free list */
485 487 uint32_t tcb_free; /* Number of free tcb in free list */
486 488
487 489 uint32_t *tbd_head_wb; /* Head write-back */
488 490 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *);
489 491
490 492 /*
491 493 * s/w context structure for TCP/UDP checksum offload
492 494 * and LSO.
493 495 */
494 496 ixgbe_tx_context_t tx_context;
495 497
496 498 /*
497 499 * Tx ring settings and status
498 500 */
499 501 uint32_t ring_size; /* Tx descriptor ring size */
500 502 uint32_t free_list_size; /* Tx free list size */
501 503
502 504 boolean_t reschedule;
503 505 uint32_t recycle_fail;
504 506 uint32_t stall_watchdog;
505 507
506 508 #ifdef IXGBE_DEBUG
507 509 /*
508 510 * Debug statistics
509 511 */
510 512 uint32_t stat_overload;
511 513 uint32_t stat_fail_no_tbd;
512 514 uint32_t stat_fail_no_tcb;
513 515 uint32_t stat_fail_dma_bind;
514 516 uint32_t stat_reschedule;
515 517 uint32_t stat_break_tbd_limit;
516 518 uint32_t stat_lso_header_fail;
517 519 #endif
518 520 uint64_t stat_obytes;
519 521 uint64_t stat_opackets;
520 522
521 523 mac_ring_handle_t ring_handle;
522 524
523 525 /*
524 526 * Pointer to the ixgbe struct
525 527 */
526 528 struct ixgbe *ixgbe;
527 529 } ixgbe_tx_ring_t;
528 530
529 531 /*
530 532 * Software Receive Ring
531 533 */
532 534 typedef struct ixgbe_rx_data {
533 535 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */
534 536
535 537 /*
536 538 * Rx descriptor ring definitions
537 539 */
538 540 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */
539 541 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */
540 542 uint32_t rbd_next; /* Index of next rx desc */
541 543
542 544 /*
543 545 * Rx control block list definitions
544 546 */
545 547 rx_control_block_t *rcb_area;
546 548 rx_control_block_t **work_list; /* Work list of rcbs */
547 549 rx_control_block_t **free_list; /* Free list of rcbs */
548 550 uint32_t rcb_head; /* Index of next free rcb */
549 551 uint32_t rcb_tail; /* Index to put recycled rcb */
550 552 uint32_t rcb_free; /* Number of free rcbs */
551 553
552 554 /*
553 555 * Rx sw ring settings and status
554 556 */
555 557 uint32_t ring_size; /* Rx descriptor ring size */
556 558 uint32_t free_list_size; /* Rx free list size */
557 559
558 560 uint32_t rcb_pending;
559 561 uint32_t flag;
560 562
561 563 uint32_t lro_num; /* Number of rcbs of one LRO */
562 564 uint32_t lro_first; /* Index of first LRO rcb */
563 565
564 566 struct ixgbe_rx_ring *rx_ring; /* Pointer to rx ring */
565 567 } ixgbe_rx_data_t;
566 568
567 569 /*
568 570 * Software Data Structure for Rx Ring
569 571 */
570 572 typedef struct ixgbe_rx_ring {
571 573 uint32_t index; /* Ring index */
572 574 uint32_t group_index; /* Group index */
573 575 uint32_t hw_index; /* h/w ring index */
574 576 uint32_t intr_vector; /* Interrupt vector index */
575 577 uint32_t vect_bit; /* vector's bit in register */
576 578
577 579 ixgbe_rx_data_t *rx_data; /* Rx software ring */
578 580
579 581 kmutex_t rx_lock; /* Rx access lock */
580 582
581 583 #ifdef IXGBE_DEBUG
582 584 /*
583 585 * Debug statistics
584 586 */
585 587 uint32_t stat_frame_error;
586 588 uint32_t stat_cksum_error;
587 589 uint32_t stat_exceed_pkt;
588 590 #endif
589 591 uint64_t stat_rbytes;
590 592 uint64_t stat_ipackets;
591 593
592 594 mac_ring_handle_t ring_handle;
593 595 uint64_t ring_gen_num;
594 596
595 597 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
596 598 } ixgbe_rx_ring_t;
597 599 /*
598 600 * Software Receive Ring Group
599 601 */
600 602 typedef struct ixgbe_rx_group {
601 603 uint32_t index; /* Group index */
602 604 mac_group_handle_t group_handle; /* call back group handle */
603 605 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */
604 606 } ixgbe_rx_group_t;
605 607
606 608 /*
607 609 * structure to map interrupt cleanup to msi-x vector
608 610 */
609 611 typedef struct ixgbe_intr_vector {
610 612 struct ixgbe *ixgbe; /* point to my adapter */
611 613 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
612 614 int rxr_cnt; /* count rx rings */
613 615 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
614 616 int txr_cnt; /* count tx rings */
615 617 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */
616 618 int other_cnt; /* count other interrupt */
617 619 } ixgbe_intr_vector_t;
618 620
619 621 /*
620 622 * Software adapter state
621 623 */
|
↓ open down ↓ |
400 lines elided |
↑ open up ↑ |
622 624 typedef struct ixgbe {
623 625 int instance;
624 626 mac_handle_t mac_hdl;
625 627 dev_info_t *dip;
626 628 struct ixgbe_hw hw;
627 629 struct ixgbe_osdep osdep;
628 630
629 631 adapter_info_t *capab; /* adapter hardware capabilities */
630 632 ddi_taskq_t *sfp_taskq; /* sfp-change taskq */
631 633 ddi_taskq_t *overtemp_taskq; /* overtemp taskq */
634 + ddi_taskq_t *phy_taskq; /* external PHY taskq */
632 635 uint32_t eims; /* interrupt mask setting */
633 636 uint32_t eimc; /* interrupt mask clear */
634 637 uint32_t eicr; /* interrupt cause reg */
635 638
636 639 uint32_t ixgbe_state;
637 640 link_state_t link_state;
638 641 uint32_t link_speed;
639 642 uint32_t link_duplex;
640 643
641 644 uint32_t reset_count;
642 645 uint32_t attach_progress;
643 646 uint32_t loopback_mode;
644 647 uint32_t default_mtu;
645 648 uint32_t max_frame_size;
649 + ixgbe_link_speed speeds_supported;
646 650
647 651 uint32_t rcb_pending;
648 652
649 653 /*
650 654 * Each msi-x vector: map vector to interrupt cleanup
651 655 */
652 656 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR];
653 657
654 658 /*
655 659 * Receive Rings
656 660 */
657 661 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */
658 662 uint32_t num_rx_rings; /* Number of rx rings in use */
659 663 uint32_t rx_ring_size; /* Rx descriptor ring size */
660 664 uint32_t rx_buf_size; /* Rx buffer size */
661 665 boolean_t lro_enable; /* Large Receive Offload */
662 666 uint64_t lro_pkt_count; /* LRO packet count */
663 667 /*
664 668 * Receive Groups
665 669 */
666 670 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */
667 671 uint32_t num_rx_groups; /* Number of rx groups in use */
668 672
669 673 /*
670 674 * Transmit Rings
671 675 */
672 676 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */
673 677 uint32_t num_tx_rings; /* Number of tx rings in use */
674 678 uint32_t tx_ring_size; /* Tx descriptor ring size */
675 679 uint32_t tx_buf_size; /* Tx buffer size */
676 680
677 681 boolean_t tx_ring_init;
678 682 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */
679 683 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */
680 684 boolean_t lso_enable; /* Large Segment Offload */
681 685 boolean_t mr_enable; /* Multiple Tx and Rx Ring */
682 686 boolean_t relax_order_enable; /* Relax Order */
683 687 uint32_t classify_mode; /* Classification mode */
684 688 uint32_t tx_copy_thresh; /* Tx copy threshold */
685 689 uint32_t tx_recycle_thresh; /* Tx recycle threshold */
686 690 uint32_t tx_overload_thresh; /* Tx overload threshold */
687 691 uint32_t tx_resched_thresh; /* Tx reschedule threshold */
688 692 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */
689 693 uint32_t rx_copy_thresh; /* Rx copy threshold */
690 694 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */
691 695 uint32_t intr_throttling[MAX_INTR_VECTOR];
692 696 uint32_t intr_force;
693 697 int fm_capabilities; /* FMA capabilities */
694 698
695 699 int intr_type;
696 700 int intr_cnt;
697 701 uint32_t intr_cnt_max;
698 702 uint32_t intr_cnt_min;
699 703 int intr_cap;
700 704 size_t intr_size;
701 705 uint_t intr_pri;
702 706 ddi_intr_handle_t *htable;
703 707 uint32_t eims_mask;
704 708 ddi_cb_handle_t cb_hdl; /* Interrupt callback handle */
705 709
706 710 kmutex_t gen_lock; /* General lock for device access */
707 711 kmutex_t watchdog_lock;
708 712 kmutex_t rx_pending_lock;
709 713
710 714 boolean_t watchdog_enable;
711 715 boolean_t watchdog_start;
712 716 timeout_id_t watchdog_tid;
713 717
714 718 boolean_t unicst_init;
715 719 uint32_t unicst_avail;
716 720 uint32_t unicst_total;
717 721 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
718 722 uint32_t mcast_count;
719 723 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
720 724
721 725 ulong_t sys_page_size;
722 726
|
↓ open down ↓ |
67 lines elided |
↑ open up ↑ |
723 727 boolean_t link_check_complete;
724 728 hrtime_t link_check_hrtime;
725 729 ddi_periodic_t periodic_id; /* for link check timer func */
726 730
727 731 /*
728 732 * Kstat definitions
729 733 */
730 734 kstat_t *ixgbe_ks;
731 735
732 736 uint32_t param_en_10000fdx_cap:1,
737 + param_en_5000fdx_cap:1,
738 + param_en_2500fdx_cap:1,
733 739 param_en_1000fdx_cap:1,
734 740 param_en_100fdx_cap:1,
735 741 param_adv_10000fdx_cap:1,
742 + param_adv_5000fdx_cap:1,
743 + param_adv_2500fdx_cap:1,
736 744 param_adv_1000fdx_cap:1,
737 745 param_adv_100fdx_cap:1,
738 746 param_pause_cap:1,
739 747 param_asym_pause_cap:1,
740 748 param_rem_fault:1,
741 749 param_adv_autoneg_cap:1,
742 750 param_adv_pause_cap:1,
743 751 param_adv_asym_pause_cap:1,
744 752 param_adv_rem_fault:1,
745 753 param_lp_10000fdx_cap:1,
754 + param_lp_5000fdx_cap:1,
755 + param_lp_2500fdx_cap:1,
746 756 param_lp_1000fdx_cap:1,
747 757 param_lp_100fdx_cap:1,
748 758 param_lp_autoneg_cap:1,
749 759 param_lp_pause_cap:1,
750 760 param_lp_asym_pause_cap:1,
751 761 param_lp_rem_fault:1,
752 - param_pad_to_32:12;
762 + param_pad_to_32:6;
753 763 } ixgbe_t;
754 764
755 765 typedef struct ixgbe_stat {
756 766 kstat_named_t link_speed; /* Link Speed */
757 767
758 768 kstat_named_t reset_count; /* Reset Count */
759 769
760 770 kstat_named_t rx_frame_error; /* Rx Error in Packet */
761 771 kstat_named_t rx_cksum_error; /* Rx Checksum Error */
762 772 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
763 773
764 774 kstat_named_t tx_overload; /* Tx Desc Ring Overload */
765 775 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
766 776 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
767 777 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */
768 778 kstat_named_t tx_reschedule; /* Tx Reschedule */
769 779
770 780 kstat_named_t gprc; /* Good Packets Received Count */
771 781 kstat_named_t gptc; /* Good Packets Xmitted Count */
772 782 kstat_named_t gor; /* Good Octets Received Count */
773 783 kstat_named_t got; /* Good Octets Xmitd Count */
774 784 kstat_named_t prc64; /* Packets Received - 64b */
775 785 kstat_named_t prc127; /* Packets Received - 65-127b */
776 786 kstat_named_t prc255; /* Packets Received - 127-255b */
777 787 kstat_named_t prc511; /* Packets Received - 256-511b */
778 788 kstat_named_t prc1023; /* Packets Received - 511-1023b */
779 789 kstat_named_t prc1522; /* Packets Received - 1024-1522b */
780 790 kstat_named_t ptc64; /* Packets Xmitted (64b) */
781 791 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */
782 792 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */
783 793 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */
784 794 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */
785 795 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */
786 796 kstat_named_t qprc[16]; /* Queue Packets Received Count */
787 797 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */
788 798 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */
789 799 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */
790 800
791 801 kstat_named_t crcerrs; /* CRC Error Count */
792 802 kstat_named_t illerrc; /* Illegal Byte Error Count */
793 803 kstat_named_t errbc; /* Error Byte Count */
794 804 kstat_named_t mspdc; /* MAC Short Packet Discard Count */
795 805 kstat_named_t mpc; /* Missed Packets Count */
796 806 kstat_named_t mlfc; /* MAC Local Fault Count */
797 807 kstat_named_t mrfc; /* MAC Remote Fault Count */
798 808 kstat_named_t rlec; /* Receive Length Error Count */
799 809 kstat_named_t lxontxc; /* Link XON Transmitted Count */
800 810 kstat_named_t lxonrxc; /* Link XON Received Count */
801 811 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
802 812 kstat_named_t lxoffrxc; /* Link XOFF Received Count */
803 813 kstat_named_t bprc; /* Broadcasts Pkts Received Count */
804 814 kstat_named_t mprc; /* Multicast Pkts Received Count */
805 815 kstat_named_t rnbc; /* Receive No Buffers Count */
806 816 kstat_named_t ruc; /* Receive Undersize Count */
807 817 kstat_named_t rfc; /* Receive Frag Count */
808 818 kstat_named_t roc; /* Receive Oversize Count */
809 819 kstat_named_t rjc; /* Receive Jabber Count */
810 820 kstat_named_t tor; /* Total Octets Recvd Count */
811 821 kstat_named_t tot; /* Total Octets Xmitted Count */
812 822 kstat_named_t tpr; /* Total Packets Received */
813 823 kstat_named_t tpt; /* Total Packets Xmitted */
814 824 kstat_named_t mptc; /* Multicast Packets Xmited Count */
815 825 kstat_named_t bptc; /* Broadcast Packets Xmited Count */
816 826 kstat_named_t lroc; /* LRO Packets Received Count */
817 827 } ixgbe_stat_t;
818 828
819 829 /*
820 830 * Function prototypes in ixgbe_buf.c
821 831 */
822 832 int ixgbe_alloc_dma(ixgbe_t *);
823 833 void ixgbe_free_dma(ixgbe_t *);
824 834 void ixgbe_set_fma_flags(int);
825 835 void ixgbe_free_dma_buffer(dma_buffer_t *);
826 836 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
827 837 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
828 838
829 839 /*
830 840 * Function prototypes in ixgbe_main.c
831 841 */
832 842 int ixgbe_start(ixgbe_t *, boolean_t);
833 843 void ixgbe_stop(ixgbe_t *, boolean_t);
834 844 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
835 845 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
836 846 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
837 847 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
838 848
839 849 void ixgbe_enable_watchdog_timer(ixgbe_t *);
840 850 void ixgbe_disable_watchdog_timer(ixgbe_t *);
841 851 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
842 852
843 853 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
844 854 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
845 855 void ixgbe_fm_ereport(ixgbe_t *, char *);
846 856
847 857 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
848 858 mac_ring_info_t *, mac_ring_handle_t);
849 859 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
850 860 mac_group_info_t *, mac_group_handle_t);
851 861 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
852 862 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
853 863
854 864 /*
855 865 * Function prototypes in ixgbe_gld.c
856 866 */
857 867 int ixgbe_m_start(void *);
858 868 void ixgbe_m_stop(void *);
859 869 int ixgbe_m_promisc(void *, boolean_t);
860 870 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
861 871 void ixgbe_m_resources(void *);
862 872 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
863 873 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
864 874 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
865 875 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *);
866 876 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t,
867 877 mac_prop_info_handle_t);
868 878 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
869 879 int ixgbe_get_priv_prop(ixgbe_t *, const char *, uint_t, void *);
870 880 boolean_t ixgbe_param_locked(mac_prop_id_t);
871 881
872 882 /*
873 883 * Function prototypes in ixgbe_rx.c
874 884 */
875 885 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
876 886 void ixgbe_rx_recycle(caddr_t arg);
877 887 mblk_t *ixgbe_ring_rx_poll(void *, int);
878 888
879 889 /*
880 890 * Function prototypes in ixgbe_tx.c
881 891 */
882 892 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
883 893 void ixgbe_free_tcb(tx_control_block_t *);
884 894 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
885 895 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
886 896 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
887 897
888 898 /*
889 899 * Function prototypes in ixgbe_log.c
890 900 */
891 901 void ixgbe_notice(void *, const char *, ...);
892 902 void ixgbe_log(void *, const char *, ...);
893 903 void ixgbe_error(void *, const char *, ...);
894 904
895 905 /*
896 906 * Function prototypes in ixgbe_stat.c
897 907 */
898 908 int ixgbe_init_stats(ixgbe_t *);
899 909 int ixgbe_m_stat(void *, uint_t, uint64_t *);
900 910 int ixgbe_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
901 911 int ixgbe_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
902 912
903 913 #ifdef __cplusplus
904 914 }
905 915 #endif
906 916
907 917 #endif /* _IXGBE_SW_H */
|
↓ open down ↓ |
145 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX