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--- old/usr/src/uts/common/io/bge/bge_main2.c
+++ new/usr/src/uts/common/io/bge/bge_main2.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 +/*
27 + * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 + */
29 +
26 30 #include "bge_impl.h"
27 31 #include <sys/sdt.h>
28 32 #include <sys/mac_provider.h>
29 33 #include <sys/mac.h>
30 34 #include <sys/mac_flow.h>
31 35
32 36 /*
33 37 * This is the string displayed by modinfo, etc.
34 38 */
35 39 static char bge_ident[] = "Broadcom Gb Ethernet";
36 40
37 41 /*
38 42 * Property names
39 43 */
40 44 static char debug_propname[] = "bge-debug-flags";
41 45 static char clsize_propname[] = "cache-line-size";
42 46 static char latency_propname[] = "latency-timer";
43 47 static char localmac_boolname[] = "local-mac-address?";
44 48 static char localmac_propname[] = "local-mac-address";
45 49 static char macaddr_propname[] = "mac-address";
46 50 static char subdev_propname[] = "subsystem-id";
47 51 static char subven_propname[] = "subsystem-vendor-id";
48 52 static char rxrings_propname[] = "bge-rx-rings";
49 53 static char txrings_propname[] = "bge-tx-rings";
50 54 static char fm_cap[] = "fm-capable";
51 55 static char default_mtu[] = "default_mtu";
52 56
53 57 static int bge_add_intrs(bge_t *, int);
54 58 static void bge_rem_intrs(bge_t *);
55 59 static int bge_unicst_set(void *, const uint8_t *, int);
56 60
57 61 /*
58 62 * Describes the chip's DMA engine
59 63 */
60 64 static ddi_dma_attr_t dma_attr = {
61 65 DMA_ATTR_V0, /* dma_attr version */
62 66 0x0000000000000000ull, /* dma_attr_addr_lo */
63 67 0xFFFFFFFFFFFFFFFFull, /* dma_attr_addr_hi */
64 68 0x00000000FFFFFFFFull, /* dma_attr_count_max */
65 69 0x0000000000000001ull, /* dma_attr_align */
66 70 0x00000FFF, /* dma_attr_burstsizes */
67 71 0x00000001, /* dma_attr_minxfer */
68 72 0x000000000000FFFFull, /* dma_attr_maxxfer */
69 73 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */
70 74 1, /* dma_attr_sgllen */
71 75 0x00000001, /* dma_attr_granular */
72 76 DDI_DMA_FLAGERR /* dma_attr_flags */
73 77 };
74 78
75 79 /*
76 80 * PIO access attributes for registers
77 81 */
78 82 static ddi_device_acc_attr_t bge_reg_accattr = {
79 83 DDI_DEVICE_ATTR_V1,
80 84 DDI_NEVERSWAP_ACC,
81 85 DDI_STRICTORDER_ACC,
82 86 DDI_FLAGERR_ACC
83 87 };
84 88
85 89 /*
86 90 * DMA access attributes for descriptors: NOT to be byte swapped.
87 91 */
88 92 static ddi_device_acc_attr_t bge_desc_accattr = {
89 93 DDI_DEVICE_ATTR_V0,
90 94 DDI_NEVERSWAP_ACC,
91 95 DDI_STRICTORDER_ACC
92 96 };
93 97
94 98 /*
95 99 * DMA access attributes for data: NOT to be byte swapped.
96 100 */
97 101 static ddi_device_acc_attr_t bge_data_accattr = {
98 102 DDI_DEVICE_ATTR_V0,
99 103 DDI_NEVERSWAP_ACC,
100 104 DDI_STRICTORDER_ACC
101 105 };
102 106
103 107 static int bge_m_start(void *);
104 108 static void bge_m_stop(void *);
105 109 static int bge_m_promisc(void *, boolean_t);
106 110 static int bge_m_multicst(void *, boolean_t, const uint8_t *);
107 111 static void bge_m_ioctl(void *, queue_t *, mblk_t *);
108 112 static boolean_t bge_m_getcapab(void *, mac_capab_t, void *);
109 113 static int bge_unicst_set(void *, const uint8_t *,
110 114 int);
111 115 static int bge_m_setprop(void *, const char *, mac_prop_id_t,
112 116 uint_t, const void *);
113 117 static int bge_m_getprop(void *, const char *, mac_prop_id_t,
114 118 uint_t, void *);
115 119 static void bge_m_propinfo(void *, const char *, mac_prop_id_t,
116 120 mac_prop_info_handle_t);
117 121 static int bge_set_priv_prop(bge_t *, const char *, uint_t,
118 122 const void *);
119 123 static int bge_get_priv_prop(bge_t *, const char *, uint_t,
120 124 void *);
121 125 static void bge_priv_propinfo(const char *,
122 126 mac_prop_info_handle_t);
123 127
124 128 #define BGE_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | \
125 129 MC_GETPROP | MC_PROPINFO)
126 130
127 131 static mac_callbacks_t bge_m_callbacks = {
128 132 BGE_M_CALLBACK_FLAGS,
129 133 bge_m_stat,
130 134 bge_m_start,
131 135 bge_m_stop,
132 136 bge_m_promisc,
133 137 bge_m_multicst,
134 138 NULL,
135 139 bge_m_tx,
136 140 NULL,
137 141 bge_m_ioctl,
138 142 bge_m_getcapab,
139 143 NULL,
140 144 NULL,
141 145 bge_m_setprop,
142 146 bge_m_getprop,
143 147 bge_m_propinfo
144 148 };
145 149
146 150 char *bge_priv_prop[] = {
147 151 "_adv_asym_pause_cap",
148 152 "_adv_pause_cap",
149 153 "_drain_max",
150 154 "_msi_cnt",
151 155 "_rx_intr_coalesce_blank_time",
152 156 "_tx_intr_coalesce_blank_time",
153 157 "_rx_intr_coalesce_pkt_cnt",
154 158 "_tx_intr_coalesce_pkt_cnt",
155 159 NULL
156 160 };
157 161
158 162 uint8_t zero_addr[6] = {0, 0, 0, 0, 0, 0};
159 163 /*
160 164 * ========== Transmit and receive ring reinitialisation ==========
161 165 */
162 166
163 167 /*
164 168 * These <reinit> routines each reset the specified ring to an initial
165 169 * state, assuming that the corresponding <init> routine has already
166 170 * been called exactly once.
167 171 */
168 172
169 173 static void
170 174 bge_reinit_send_ring(send_ring_t *srp)
171 175 {
172 176 bge_queue_t *txbuf_queue;
173 177 bge_queue_item_t *txbuf_head;
174 178 sw_txbuf_t *txbuf;
175 179 sw_sbd_t *ssbdp;
176 180 uint32_t slot;
177 181
178 182 /*
179 183 * Reinitialise control variables ...
180 184 */
181 185 srp->tx_flow = 0;
182 186 srp->tx_next = 0;
183 187 srp->txfill_next = 0;
184 188 srp->tx_free = srp->desc.nslots;
185 189 ASSERT(mutex_owned(srp->tc_lock));
186 190 srp->tc_next = 0;
187 191 srp->txpkt_next = 0;
188 192 srp->tx_block = 0;
189 193 srp->tx_nobd = 0;
190 194 srp->tx_nobuf = 0;
191 195
192 196 /*
193 197 * Initialize the tx buffer push queue
194 198 */
195 199 mutex_enter(srp->freetxbuf_lock);
196 200 mutex_enter(srp->txbuf_lock);
197 201 txbuf_queue = &srp->freetxbuf_queue;
198 202 txbuf_queue->head = NULL;
199 203 txbuf_queue->count = 0;
200 204 txbuf_queue->lock = srp->freetxbuf_lock;
201 205 srp->txbuf_push_queue = txbuf_queue;
202 206
203 207 /*
204 208 * Initialize the tx buffer pop queue
205 209 */
206 210 txbuf_queue = &srp->txbuf_queue;
207 211 txbuf_queue->head = NULL;
208 212 txbuf_queue->count = 0;
209 213 txbuf_queue->lock = srp->txbuf_lock;
210 214 srp->txbuf_pop_queue = txbuf_queue;
211 215 txbuf_head = srp->txbuf_head;
212 216 txbuf = srp->txbuf;
213 217 for (slot = 0; slot < srp->tx_buffers; ++slot) {
214 218 txbuf_head->item = txbuf;
215 219 txbuf_head->next = txbuf_queue->head;
216 220 txbuf_queue->head = txbuf_head;
217 221 txbuf_queue->count++;
218 222 txbuf++;
219 223 txbuf_head++;
220 224 }
221 225 mutex_exit(srp->txbuf_lock);
222 226 mutex_exit(srp->freetxbuf_lock);
223 227
224 228 /*
225 229 * Zero and sync all the h/w Send Buffer Descriptors
226 230 */
227 231 DMA_ZERO(srp->desc);
228 232 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV);
229 233 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp));
230 234 ssbdp = srp->sw_sbds;
231 235 for (slot = 0; slot < srp->desc.nslots; ++ssbdp, ++slot)
232 236 ssbdp->pbuf = NULL;
233 237 }
234 238
235 239 static void
236 240 bge_reinit_recv_ring(recv_ring_t *rrp)
237 241 {
238 242 /*
239 243 * Reinitialise control variables ...
240 244 */
241 245 rrp->rx_next = 0;
242 246 }
243 247
244 248 static void
245 249 bge_reinit_buff_ring(buff_ring_t *brp, uint32_t ring)
246 250 {
247 251 bge_rbd_t *hw_rbd_p;
248 252 sw_rbd_t *srbdp;
249 253 uint32_t bufsize;
250 254 uint32_t nslots;
251 255 uint32_t slot;
252 256
253 257 static uint16_t ring_type_flag[BGE_BUFF_RINGS_MAX] = {
254 258 RBD_FLAG_STD_RING,
255 259 RBD_FLAG_JUMBO_RING,
256 260 RBD_FLAG_MINI_RING
257 261 };
258 262
259 263 /*
260 264 * Zero, initialise and sync all the h/w Receive Buffer Descriptors
261 265 * Note: all the remaining fields (<type>, <flags>, <ip_cksum>,
262 266 * <tcp_udp_cksum>, <error_flag>, <vlan_tag>, and <reserved>)
263 267 * should be zeroed, and so don't need to be set up specifically
264 268 * once the whole area has been cleared.
265 269 */
266 270 DMA_ZERO(brp->desc);
267 271
268 272 hw_rbd_p = DMA_VPTR(brp->desc);
269 273 nslots = brp->desc.nslots;
270 274 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT);
271 275 bufsize = brp->buf[0].size;
272 276 srbdp = brp->sw_rbds;
273 277 for (slot = 0; slot < nslots; ++hw_rbd_p, ++srbdp, ++slot) {
274 278 hw_rbd_p->host_buf_addr = srbdp->pbuf.cookie.dmac_laddress;
275 279 hw_rbd_p->index = (uint16_t)slot;
276 280 hw_rbd_p->len = (uint16_t)bufsize;
277 281 hw_rbd_p->opaque = srbdp->pbuf.token;
278 282 hw_rbd_p->flags |= ring_type_flag[ring];
279 283 }
280 284
281 285 DMA_SYNC(brp->desc, DDI_DMA_SYNC_FORDEV);
282 286
283 287 /*
284 288 * Finally, reinitialise the ring control variables ...
285 289 */
286 290 brp->rf_next = (nslots != 0) ? (nslots-1) : 0;
287 291 }
288 292
289 293 /*
290 294 * Reinitialize all rings
291 295 */
292 296 static void
293 297 bge_reinit_rings(bge_t *bgep)
294 298 {
295 299 uint32_t ring;
296 300
297 301 ASSERT(mutex_owned(bgep->genlock));
298 302
299 303 /*
300 304 * Send Rings ...
301 305 */
302 306 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring)
303 307 bge_reinit_send_ring(&bgep->send[ring]);
304 308
305 309 /*
306 310 * Receive Return Rings ...
307 311 */
308 312 for (ring = 0; ring < bgep->chipid.rx_rings; ++ring)
309 313 bge_reinit_recv_ring(&bgep->recv[ring]);
310 314
311 315 /*
312 316 * Receive Producer Rings ...
313 317 */
314 318 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
315 319 bge_reinit_buff_ring(&bgep->buff[ring], ring);
316 320 }
317 321
318 322 /*
319 323 * ========== Internal state management entry points ==========
320 324 */
321 325
322 326 #undef BGE_DBG
323 327 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */
324 328
325 329 /*
326 330 * These routines provide all the functionality required by the
327 331 * corresponding GLD entry points, but don't update the GLD state
328 332 * so they can be called internally without disturbing our record
329 333 * of what GLD thinks we should be doing ...
330 334 */
331 335
332 336 /*
333 337 * bge_reset() -- reset h/w & rings to initial state
334 338 */
335 339 static int
336 340 #ifdef BGE_IPMI_ASF
337 341 bge_reset(bge_t *bgep, uint_t asf_mode)
338 342 #else
339 343 bge_reset(bge_t *bgep)
340 344 #endif
341 345 {
342 346 uint32_t ring;
343 347 int retval;
344 348
345 349 BGE_TRACE(("bge_reset($%p)", (void *)bgep));
346 350
347 351 ASSERT(mutex_owned(bgep->genlock));
348 352
349 353 /*
350 354 * Grab all the other mutexes in the world (this should
351 355 * ensure no other threads are manipulating driver state)
352 356 */
353 357 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring)
354 358 mutex_enter(bgep->recv[ring].rx_lock);
355 359 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring)
356 360 mutex_enter(bgep->buff[ring].rf_lock);
357 361 rw_enter(bgep->errlock, RW_WRITER);
358 362 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring)
359 363 mutex_enter(bgep->send[ring].tx_lock);
360 364 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring)
361 365 mutex_enter(bgep->send[ring].tc_lock);
362 366
363 367 #ifdef BGE_IPMI_ASF
364 368 retval = bge_chip_reset(bgep, B_TRUE, asf_mode);
365 369 #else
366 370 retval = bge_chip_reset(bgep, B_TRUE);
367 371 #endif
368 372 bge_reinit_rings(bgep);
369 373
370 374 /*
371 375 * Free the world ...
372 376 */
373 377 for (ring = BGE_SEND_RINGS_MAX; ring-- > 0; )
374 378 mutex_exit(bgep->send[ring].tc_lock);
375 379 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring)
376 380 mutex_exit(bgep->send[ring].tx_lock);
377 381 rw_exit(bgep->errlock);
378 382 for (ring = BGE_BUFF_RINGS_MAX; ring-- > 0; )
379 383 mutex_exit(bgep->buff[ring].rf_lock);
380 384 for (ring = BGE_RECV_RINGS_MAX; ring-- > 0; )
381 385 mutex_exit(bgep->recv[ring].rx_lock);
382 386
383 387 BGE_DEBUG(("bge_reset($%p) done", (void *)bgep));
384 388 return (retval);
385 389 }
386 390
387 391 /*
388 392 * bge_stop() -- stop processing, don't reset h/w or rings
389 393 */
390 394 static void
391 395 bge_stop(bge_t *bgep)
392 396 {
393 397 BGE_TRACE(("bge_stop($%p)", (void *)bgep));
394 398
395 399 ASSERT(mutex_owned(bgep->genlock));
396 400
397 401 #ifdef BGE_IPMI_ASF
398 402 if (bgep->asf_enabled) {
399 403 bgep->asf_pseudostop = B_TRUE;
400 404 } else {
401 405 #endif
402 406 bge_chip_stop(bgep, B_FALSE);
403 407 #ifdef BGE_IPMI_ASF
404 408 }
405 409 #endif
406 410
407 411 BGE_DEBUG(("bge_stop($%p) done", (void *)bgep));
408 412 }
409 413
410 414 /*
411 415 * bge_start() -- start transmitting/receiving
412 416 */
413 417 static int
414 418 bge_start(bge_t *bgep, boolean_t reset_phys)
415 419 {
416 420 int retval;
417 421
418 422 BGE_TRACE(("bge_start($%p, %d)", (void *)bgep, reset_phys));
419 423
420 424 ASSERT(mutex_owned(bgep->genlock));
421 425
422 426 /*
423 427 * Start chip processing, including enabling interrupts
424 428 */
425 429 retval = bge_chip_start(bgep, reset_phys);
426 430
427 431 BGE_DEBUG(("bge_start($%p, %d) done", (void *)bgep, reset_phys));
428 432 return (retval);
429 433 }
430 434
431 435 /*
432 436 * bge_restart - restart transmitting/receiving after error or suspend
433 437 */
434 438 int
435 439 bge_restart(bge_t *bgep, boolean_t reset_phys)
436 440 {
437 441 int retval = DDI_SUCCESS;
438 442 ASSERT(mutex_owned(bgep->genlock));
439 443
440 444 #ifdef BGE_IPMI_ASF
441 445 if (bgep->asf_enabled) {
442 446 if (bge_reset(bgep, ASF_MODE_POST_INIT) != DDI_SUCCESS)
443 447 retval = DDI_FAILURE;
444 448 } else
445 449 if (bge_reset(bgep, ASF_MODE_NONE) != DDI_SUCCESS)
446 450 retval = DDI_FAILURE;
447 451 #else
448 452 if (bge_reset(bgep) != DDI_SUCCESS)
449 453 retval = DDI_FAILURE;
450 454 #endif
451 455 if (bgep->bge_mac_state == BGE_MAC_STARTED) {
452 456 if (bge_start(bgep, reset_phys) != DDI_SUCCESS)
453 457 retval = DDI_FAILURE;
454 458 bgep->watchdog = 0;
455 459 ddi_trigger_softintr(bgep->drain_id);
456 460 }
457 461
458 462 BGE_DEBUG(("bge_restart($%p, %d) done", (void *)bgep, reset_phys));
459 463 return (retval);
460 464 }
461 465
462 466
463 467 /*
464 468 * ========== Nemo-required management entry points ==========
465 469 */
466 470
467 471 #undef BGE_DBG
468 472 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */
469 473
470 474 /*
471 475 * bge_m_stop() -- stop transmitting/receiving
472 476 */
473 477 static void
474 478 bge_m_stop(void *arg)
475 479 {
476 480 bge_t *bgep = arg; /* private device info */
477 481 send_ring_t *srp;
478 482 uint32_t ring;
479 483
480 484 BGE_TRACE(("bge_m_stop($%p)", arg));
481 485
482 486 /*
483 487 * Just stop processing, then record new GLD state
484 488 */
485 489 mutex_enter(bgep->genlock);
486 490 if (!(bgep->progress & PROGRESS_INTR)) {
487 491 /* can happen during autorecovery */
488 492 bgep->bge_chip_state = BGE_CHIP_STOPPED;
489 493 } else
490 494 bge_stop(bgep);
491 495
492 496 bgep->link_update_timer = 0;
493 497 bgep->link_state = LINK_STATE_UNKNOWN;
494 498 mac_link_update(bgep->mh, bgep->link_state);
495 499
496 500 /*
497 501 * Free the possible tx buffers allocated in tx process.
498 502 */
499 503 #ifdef BGE_IPMI_ASF
500 504 if (!bgep->asf_pseudostop)
501 505 #endif
502 506 {
503 507 rw_enter(bgep->errlock, RW_WRITER);
504 508 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) {
505 509 srp = &bgep->send[ring];
506 510 mutex_enter(srp->tx_lock);
507 511 if (srp->tx_array > 1)
508 512 bge_free_txbuf_arrays(srp);
509 513 mutex_exit(srp->tx_lock);
510 514 }
511 515 rw_exit(bgep->errlock);
512 516 }
513 517 bgep->bge_mac_state = BGE_MAC_STOPPED;
514 518 BGE_DEBUG(("bge_m_stop($%p) done", arg));
515 519 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
516 520 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
517 521 mutex_exit(bgep->genlock);
518 522 }
519 523
520 524 /*
521 525 * bge_m_start() -- start transmitting/receiving
522 526 */
523 527 static int
524 528 bge_m_start(void *arg)
525 529 {
526 530 bge_t *bgep = arg; /* private device info */
527 531
528 532 BGE_TRACE(("bge_m_start($%p)", arg));
529 533
530 534 /*
531 535 * Start processing and record new GLD state
532 536 */
533 537 mutex_enter(bgep->genlock);
534 538 if (!(bgep->progress & PROGRESS_INTR)) {
535 539 /* can happen during autorecovery */
536 540 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
537 541 mutex_exit(bgep->genlock);
538 542 return (EIO);
539 543 }
540 544 #ifdef BGE_IPMI_ASF
541 545 if (bgep->asf_enabled) {
542 546 if ((bgep->asf_status == ASF_STAT_RUN) &&
543 547 (bgep->asf_pseudostop)) {
544 548 bgep->bge_mac_state = BGE_MAC_STARTED;
545 549 mutex_exit(bgep->genlock);
546 550 return (0);
547 551 }
548 552 }
549 553 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) {
550 554 #else
551 555 if (bge_reset(bgep) != DDI_SUCCESS) {
552 556 #endif
553 557 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
554 558 (void) bge_check_acc_handle(bgep, bgep->io_handle);
555 559 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
556 560 mutex_exit(bgep->genlock);
557 561 return (EIO);
558 562 }
559 563 if (bge_start(bgep, B_TRUE) != DDI_SUCCESS) {
560 564 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
561 565 (void) bge_check_acc_handle(bgep, bgep->io_handle);
562 566 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
563 567 mutex_exit(bgep->genlock);
564 568 return (EIO);
565 569 }
566 570 bgep->watchdog = 0;
567 571 bgep->bge_mac_state = BGE_MAC_STARTED;
568 572 BGE_DEBUG(("bge_m_start($%p) done", arg));
569 573
570 574 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
571 575 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
572 576 mutex_exit(bgep->genlock);
573 577 return (EIO);
574 578 }
575 579 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
576 580 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
577 581 mutex_exit(bgep->genlock);
578 582 return (EIO);
579 583 }
580 584 #ifdef BGE_IPMI_ASF
581 585 if (bgep->asf_enabled) {
582 586 if (bgep->asf_status != ASF_STAT_RUN) {
583 587 /* start ASF heart beat */
584 588 bgep->asf_timeout_id = timeout(bge_asf_heartbeat,
585 589 (void *)bgep,
586 590 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
587 591 bgep->asf_status = ASF_STAT_RUN;
588 592 }
589 593 }
590 594 #endif
591 595 mutex_exit(bgep->genlock);
592 596
593 597 return (0);
594 598 }
595 599
596 600 /*
597 601 * bge_unicst_set() -- set the physical network address
598 602 */
599 603 static int
600 604 bge_unicst_set(void *arg, const uint8_t *macaddr, int slot)
601 605 {
602 606 bge_t *bgep = arg; /* private device info */
603 607
604 608 BGE_TRACE(("bge_m_unicst_set($%p, %s)", arg,
605 609 ether_sprintf((void *)macaddr)));
606 610 /*
607 611 * Remember the new current address in the driver state
608 612 * Sync the chip's idea of the address too ...
609 613 */
610 614 mutex_enter(bgep->genlock);
611 615 if (!(bgep->progress & PROGRESS_INTR)) {
612 616 /* can happen during autorecovery */
613 617 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
614 618 mutex_exit(bgep->genlock);
615 619 return (EIO);
616 620 }
617 621 ethaddr_copy(macaddr, bgep->curr_addr[slot].addr);
618 622 #ifdef BGE_IPMI_ASF
619 623 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) {
620 624 #else
621 625 if (bge_chip_sync(bgep) == DDI_FAILURE) {
622 626 #endif
623 627 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
624 628 (void) bge_check_acc_handle(bgep, bgep->io_handle);
625 629 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
626 630 mutex_exit(bgep->genlock);
627 631 return (EIO);
628 632 }
629 633 #ifdef BGE_IPMI_ASF
630 634 if (bgep->asf_enabled) {
631 635 /*
632 636 * The above bge_chip_sync() function wrote the ethernet MAC
633 637 * addresses registers which destroyed the IPMI/ASF sideband.
634 638 * Here, we have to reset chip to make IPMI/ASF sideband work.
635 639 */
636 640 if (bgep->asf_status == ASF_STAT_RUN) {
637 641 /*
638 642 * We must stop ASF heart beat before bge_chip_stop(),
639 643 * otherwise some computers (ex. IBM HS20 blade server)
640 644 * may crash.
641 645 */
642 646 bge_asf_update_status(bgep);
643 647 bge_asf_stop_timer(bgep);
644 648 bgep->asf_status = ASF_STAT_STOP;
645 649
646 650 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
647 651 }
648 652 bge_chip_stop(bgep, B_FALSE);
649 653
650 654 if (bge_restart(bgep, B_FALSE) == DDI_FAILURE) {
651 655 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
652 656 (void) bge_check_acc_handle(bgep, bgep->io_handle);
653 657 ddi_fm_service_impact(bgep->devinfo,
654 658 DDI_SERVICE_DEGRADED);
655 659 mutex_exit(bgep->genlock);
656 660 return (EIO);
657 661 }
658 662
659 663 /*
660 664 * Start our ASF heartbeat counter as soon as possible.
661 665 */
662 666 if (bgep->asf_status != ASF_STAT_RUN) {
663 667 /* start ASF heart beat */
664 668 bgep->asf_timeout_id = timeout(bge_asf_heartbeat,
665 669 (void *)bgep,
666 670 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
667 671 bgep->asf_status = ASF_STAT_RUN;
668 672 }
669 673 }
670 674 #endif
671 675 BGE_DEBUG(("bge_m_unicst_set($%p) done", arg));
672 676 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
673 677 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
674 678 mutex_exit(bgep->genlock);
675 679 return (EIO);
676 680 }
677 681 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
678 682 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
679 683 mutex_exit(bgep->genlock);
680 684 return (EIO);
681 685 }
682 686 mutex_exit(bgep->genlock);
683 687
684 688 return (0);
685 689 }
686 690
687 691 extern void bge_wake_factotum(bge_t *);
688 692
689 693 static boolean_t
690 694 bge_param_locked(mac_prop_id_t pr_num)
691 695 {
692 696 /*
693 697 * All adv_* parameters are locked (read-only) while
694 698 * the device is in any sort of loopback mode ...
695 699 */
696 700 switch (pr_num) {
697 701 case MAC_PROP_ADV_1000FDX_CAP:
698 702 case MAC_PROP_EN_1000FDX_CAP:
699 703 case MAC_PROP_ADV_1000HDX_CAP:
700 704 case MAC_PROP_EN_1000HDX_CAP:
701 705 case MAC_PROP_ADV_100FDX_CAP:
702 706 case MAC_PROP_EN_100FDX_CAP:
703 707 case MAC_PROP_ADV_100HDX_CAP:
704 708 case MAC_PROP_EN_100HDX_CAP:
705 709 case MAC_PROP_ADV_10FDX_CAP:
706 710 case MAC_PROP_EN_10FDX_CAP:
707 711 case MAC_PROP_ADV_10HDX_CAP:
708 712 case MAC_PROP_EN_10HDX_CAP:
709 713 case MAC_PROP_AUTONEG:
710 714 case MAC_PROP_FLOWCTRL:
711 715 return (B_TRUE);
712 716 }
713 717 return (B_FALSE);
714 718 }
715 719 /*
716 720 * callback functions for set/get of properties
717 721 */
718 722 static int
719 723 bge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
720 724 uint_t pr_valsize, const void *pr_val)
721 725 {
722 726 bge_t *bgep = barg;
723 727 int err = 0;
724 728 uint32_t cur_mtu, new_mtu;
725 729 link_flowctrl_t fl;
726 730
727 731 mutex_enter(bgep->genlock);
728 732 if (bgep->param_loop_mode != BGE_LOOP_NONE &&
729 733 bge_param_locked(pr_num)) {
730 734 /*
731 735 * All adv_* parameters are locked (read-only)
732 736 * while the device is in any sort of loopback mode.
733 737 */
734 738 mutex_exit(bgep->genlock);
735 739 return (EBUSY);
736 740 }
737 741 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
738 742 ((pr_num == MAC_PROP_EN_100FDX_CAP) ||
739 743 (pr_num == MAC_PROP_EN_100HDX_CAP) ||
740 744 (pr_num == MAC_PROP_EN_10FDX_CAP) ||
741 745 (pr_num == MAC_PROP_EN_10HDX_CAP))) {
742 746 /*
743 747 * these properties are read/write on copper,
744 748 * read-only and 0 on serdes
745 749 */
746 750 mutex_exit(bgep->genlock);
747 751 return (ENOTSUP);
748 752 }
749 753 if (DEVICE_5906_SERIES_CHIPSETS(bgep) &&
750 754 ((pr_num == MAC_PROP_EN_1000FDX_CAP) ||
751 755 (pr_num == MAC_PROP_EN_1000HDX_CAP))) {
752 756 mutex_exit(bgep->genlock);
753 757 return (ENOTSUP);
754 758 }
755 759
756 760 switch (pr_num) {
757 761 case MAC_PROP_EN_1000FDX_CAP:
758 762 bgep->param_en_1000fdx = *(uint8_t *)pr_val;
759 763 bgep->param_adv_1000fdx = *(uint8_t *)pr_val;
760 764 goto reprogram;
761 765 case MAC_PROP_EN_1000HDX_CAP:
762 766 bgep->param_en_1000hdx = *(uint8_t *)pr_val;
763 767 bgep->param_adv_1000hdx = *(uint8_t *)pr_val;
764 768 goto reprogram;
765 769 case MAC_PROP_EN_100FDX_CAP:
766 770 bgep->param_en_100fdx = *(uint8_t *)pr_val;
767 771 bgep->param_adv_100fdx = *(uint8_t *)pr_val;
768 772 goto reprogram;
769 773 case MAC_PROP_EN_100HDX_CAP:
770 774 bgep->param_en_100hdx = *(uint8_t *)pr_val;
771 775 bgep->param_adv_100hdx = *(uint8_t *)pr_val;
772 776 goto reprogram;
773 777 case MAC_PROP_EN_10FDX_CAP:
774 778 bgep->param_en_10fdx = *(uint8_t *)pr_val;
775 779 bgep->param_adv_10fdx = *(uint8_t *)pr_val;
776 780 goto reprogram;
777 781 case MAC_PROP_EN_10HDX_CAP:
778 782 bgep->param_en_10hdx = *(uint8_t *)pr_val;
779 783 bgep->param_adv_10hdx = *(uint8_t *)pr_val;
780 784 reprogram:
781 785 if (err == 0 && bge_reprogram(bgep) == IOC_INVAL)
782 786 err = EINVAL;
783 787 break;
784 788 case MAC_PROP_ADV_1000FDX_CAP:
785 789 case MAC_PROP_ADV_1000HDX_CAP:
786 790 case MAC_PROP_ADV_100FDX_CAP:
787 791 case MAC_PROP_ADV_100HDX_CAP:
788 792 case MAC_PROP_ADV_10FDX_CAP:
789 793 case MAC_PROP_ADV_10HDX_CAP:
790 794 case MAC_PROP_STATUS:
791 795 case MAC_PROP_SPEED:
792 796 case MAC_PROP_DUPLEX:
793 797 err = ENOTSUP; /* read-only prop. Can't set this */
794 798 break;
795 799 case MAC_PROP_AUTONEG:
796 800 bgep->param_adv_autoneg = *(uint8_t *)pr_val;
797 801 if (bge_reprogram(bgep) == IOC_INVAL)
798 802 err = EINVAL;
799 803 break;
800 804 case MAC_PROP_MTU:
801 805 cur_mtu = bgep->chipid.default_mtu;
802 806 bcopy(pr_val, &new_mtu, sizeof (new_mtu));
803 807
804 808 if (new_mtu == cur_mtu) {
805 809 err = 0;
806 810 break;
807 811 }
808 812 if (new_mtu < BGE_DEFAULT_MTU ||
809 813 new_mtu > BGE_MAXIMUM_MTU) {
810 814 err = EINVAL;
811 815 break;
812 816 }
813 817 if ((new_mtu > BGE_DEFAULT_MTU) &&
814 818 (bgep->chipid.flags & CHIP_FLAG_NO_JUMBO)) {
815 819 err = EINVAL;
816 820 break;
817 821 }
818 822 if (bgep->bge_mac_state == BGE_MAC_STARTED) {
819 823 err = EBUSY;
820 824 break;
821 825 }
822 826 bgep->chipid.default_mtu = new_mtu;
823 827 if (bge_chip_id_init(bgep)) {
824 828 err = EINVAL;
825 829 break;
826 830 }
827 831 bgep->bge_dma_error = B_TRUE;
828 832 bgep->manual_reset = B_TRUE;
829 833 bge_chip_stop(bgep, B_TRUE);
830 834 bge_wake_factotum(bgep);
831 835 err = 0;
832 836 break;
833 837 case MAC_PROP_FLOWCTRL:
834 838 bcopy(pr_val, &fl, sizeof (fl));
835 839 switch (fl) {
836 840 default:
837 841 err = ENOTSUP;
838 842 break;
839 843 case LINK_FLOWCTRL_NONE:
840 844 bgep->param_adv_pause = 0;
841 845 bgep->param_adv_asym_pause = 0;
842 846
843 847 bgep->param_link_rx_pause = B_FALSE;
844 848 bgep->param_link_tx_pause = B_FALSE;
845 849 break;
846 850 case LINK_FLOWCTRL_RX:
847 851 bgep->param_adv_pause = 1;
848 852 bgep->param_adv_asym_pause = 1;
849 853
850 854 bgep->param_link_rx_pause = B_TRUE;
851 855 bgep->param_link_tx_pause = B_FALSE;
852 856 break;
853 857 case LINK_FLOWCTRL_TX:
854 858 bgep->param_adv_pause = 0;
855 859 bgep->param_adv_asym_pause = 1;
856 860
857 861 bgep->param_link_rx_pause = B_FALSE;
858 862 bgep->param_link_tx_pause = B_TRUE;
859 863 break;
860 864 case LINK_FLOWCTRL_BI:
861 865 bgep->param_adv_pause = 1;
862 866 bgep->param_adv_asym_pause = 0;
863 867
864 868 bgep->param_link_rx_pause = B_TRUE;
865 869 bgep->param_link_tx_pause = B_TRUE;
866 870 break;
867 871 }
868 872
869 873 if (err == 0) {
870 874 if (bge_reprogram(bgep) == IOC_INVAL)
871 875 err = EINVAL;
872 876 }
873 877
874 878 break;
875 879 case MAC_PROP_PRIVATE:
876 880 err = bge_set_priv_prop(bgep, pr_name, pr_valsize,
877 881 pr_val);
878 882 break;
879 883 default:
880 884 err = ENOTSUP;
881 885 break;
882 886 }
883 887 mutex_exit(bgep->genlock);
884 888 return (err);
885 889 }
886 890
887 891 /* ARGSUSED */
888 892 static int
889 893 bge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
890 894 uint_t pr_valsize, void *pr_val)
891 895 {
892 896 bge_t *bgep = barg;
893 897 int err = 0;
894 898
895 899 switch (pr_num) {
896 900 case MAC_PROP_DUPLEX:
897 901 ASSERT(pr_valsize >= sizeof (link_duplex_t));
898 902 bcopy(&bgep->param_link_duplex, pr_val,
899 903 sizeof (link_duplex_t));
900 904 break;
901 905 case MAC_PROP_SPEED: {
902 906 uint64_t speed = bgep->param_link_speed * 1000000ull;
903 907
904 908 ASSERT(pr_valsize >= sizeof (speed));
905 909 bcopy(&speed, pr_val, sizeof (speed));
906 910 break;
907 911 }
908 912 case MAC_PROP_STATUS:
909 913 ASSERT(pr_valsize >= sizeof (link_state_t));
910 914 bcopy(&bgep->link_state, pr_val,
911 915 sizeof (link_state_t));
912 916 break;
913 917 case MAC_PROP_AUTONEG:
914 918 *(uint8_t *)pr_val = bgep->param_adv_autoneg;
915 919 break;
916 920 case MAC_PROP_FLOWCTRL: {
917 921 link_flowctrl_t fl;
918 922
919 923 ASSERT(pr_valsize >= sizeof (fl));
920 924
921 925 if (bgep->param_link_rx_pause &&
922 926 !bgep->param_link_tx_pause)
923 927 fl = LINK_FLOWCTRL_RX;
924 928
925 929 if (!bgep->param_link_rx_pause &&
926 930 !bgep->param_link_tx_pause)
927 931 fl = LINK_FLOWCTRL_NONE;
928 932
929 933 if (!bgep->param_link_rx_pause &&
930 934 bgep->param_link_tx_pause)
931 935 fl = LINK_FLOWCTRL_TX;
932 936
933 937 if (bgep->param_link_rx_pause &&
934 938 bgep->param_link_tx_pause)
935 939 fl = LINK_FLOWCTRL_BI;
936 940 bcopy(&fl, pr_val, sizeof (fl));
937 941 break;
938 942 }
939 943 case MAC_PROP_ADV_1000FDX_CAP:
940 944 *(uint8_t *)pr_val = bgep->param_adv_1000fdx;
941 945 break;
942 946 case MAC_PROP_EN_1000FDX_CAP:
943 947 *(uint8_t *)pr_val = bgep->param_en_1000fdx;
944 948 break;
945 949 case MAC_PROP_ADV_1000HDX_CAP:
946 950 *(uint8_t *)pr_val = bgep->param_adv_1000hdx;
947 951 break;
948 952 case MAC_PROP_EN_1000HDX_CAP:
949 953 *(uint8_t *)pr_val = bgep->param_en_1000hdx;
950 954 break;
951 955 case MAC_PROP_ADV_100FDX_CAP:
952 956 *(uint8_t *)pr_val = bgep->param_adv_100fdx;
953 957 break;
954 958 case MAC_PROP_EN_100FDX_CAP:
955 959 *(uint8_t *)pr_val = bgep->param_en_100fdx;
956 960 break;
957 961 case MAC_PROP_ADV_100HDX_CAP:
958 962 *(uint8_t *)pr_val = bgep->param_adv_100hdx;
959 963 break;
960 964 case MAC_PROP_EN_100HDX_CAP:
961 965 *(uint8_t *)pr_val = bgep->param_en_100hdx;
962 966 break;
963 967 case MAC_PROP_ADV_10FDX_CAP:
964 968 *(uint8_t *)pr_val = bgep->param_adv_10fdx;
965 969 break;
966 970 case MAC_PROP_EN_10FDX_CAP:
967 971 *(uint8_t *)pr_val = bgep->param_en_10fdx;
968 972 break;
969 973 case MAC_PROP_ADV_10HDX_CAP:
970 974 *(uint8_t *)pr_val = bgep->param_adv_10hdx;
971 975 break;
972 976 case MAC_PROP_EN_10HDX_CAP:
973 977 *(uint8_t *)pr_val = bgep->param_en_10hdx;
974 978 break;
975 979 case MAC_PROP_ADV_100T4_CAP:
976 980 case MAC_PROP_EN_100T4_CAP:
977 981 *(uint8_t *)pr_val = 0;
978 982 break;
979 983 case MAC_PROP_PRIVATE:
980 984 err = bge_get_priv_prop(bgep, pr_name,
981 985 pr_valsize, pr_val);
982 986 return (err);
983 987 default:
984 988 return (ENOTSUP);
985 989 }
986 990 return (0);
987 991 }
988 992
989 993 static void
990 994 bge_m_propinfo(void *barg, const char *pr_name, mac_prop_id_t pr_num,
991 995 mac_prop_info_handle_t prh)
992 996 {
993 997 bge_t *bgep = barg;
994 998 int flags = bgep->chipid.flags;
995 999
996 1000 /*
997 1001 * By default permissions are read/write unless specified
998 1002 * otherwise by the driver.
999 1003 */
1000 1004
1001 1005 switch (pr_num) {
1002 1006 case MAC_PROP_DUPLEX:
1003 1007 case MAC_PROP_SPEED:
1004 1008 case MAC_PROP_STATUS:
1005 1009 case MAC_PROP_ADV_1000FDX_CAP:
1006 1010 case MAC_PROP_ADV_1000HDX_CAP:
1007 1011 case MAC_PROP_ADV_100FDX_CAP:
1008 1012 case MAC_PROP_ADV_100HDX_CAP:
1009 1013 case MAC_PROP_ADV_10FDX_CAP:
1010 1014 case MAC_PROP_ADV_10HDX_CAP:
1011 1015 case MAC_PROP_ADV_100T4_CAP:
1012 1016 case MAC_PROP_EN_100T4_CAP:
1013 1017 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
1014 1018 break;
1015 1019
1016 1020 case MAC_PROP_EN_1000FDX_CAP:
1017 1021 case MAC_PROP_EN_1000HDX_CAP:
1018 1022 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1019 1023 mac_prop_info_set_default_uint8(prh, 0);
1020 1024 else
1021 1025 mac_prop_info_set_default_uint8(prh, 1);
1022 1026 break;
1023 1027
1024 1028 case MAC_PROP_EN_100FDX_CAP:
1025 1029 case MAC_PROP_EN_100HDX_CAP:
1026 1030 case MAC_PROP_EN_10FDX_CAP:
1027 1031 case MAC_PROP_EN_10HDX_CAP:
1028 1032 mac_prop_info_set_default_uint8(prh,
1029 1033 (flags & CHIP_FLAG_SERDES) ? 0 : 1);
1030 1034 break;
1031 1035
1032 1036 case MAC_PROP_AUTONEG:
1033 1037 mac_prop_info_set_default_uint8(prh, 1);
1034 1038 break;
1035 1039
1036 1040 case MAC_PROP_FLOWCTRL:
1037 1041 mac_prop_info_set_default_link_flowctrl(prh,
1038 1042 LINK_FLOWCTRL_BI);
1039 1043 break;
1040 1044
1041 1045 case MAC_PROP_MTU:
1042 1046 mac_prop_info_set_range_uint32(prh, BGE_DEFAULT_MTU,
1043 1047 (flags & CHIP_FLAG_NO_JUMBO) ?
1044 1048 BGE_DEFAULT_MTU : BGE_MAXIMUM_MTU);
1045 1049 break;
1046 1050
1047 1051 case MAC_PROP_PRIVATE:
1048 1052 bge_priv_propinfo(pr_name, prh);
1049 1053 break;
1050 1054 }
1051 1055
1052 1056 mutex_enter(bgep->genlock);
1053 1057 if ((bgep->param_loop_mode != BGE_LOOP_NONE &&
1054 1058 bge_param_locked(pr_num)) ||
1055 1059 ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
1056 1060 ((pr_num == MAC_PROP_EN_100FDX_CAP) ||
1057 1061 (pr_num == MAC_PROP_EN_100HDX_CAP) ||
1058 1062 (pr_num == MAC_PROP_EN_10FDX_CAP) ||
1059 1063 (pr_num == MAC_PROP_EN_10HDX_CAP))) ||
1060 1064 (DEVICE_5906_SERIES_CHIPSETS(bgep) &&
1061 1065 ((pr_num == MAC_PROP_EN_1000FDX_CAP) ||
1062 1066 (pr_num == MAC_PROP_EN_1000HDX_CAP))))
1063 1067 mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
1064 1068 mutex_exit(bgep->genlock);
1065 1069 }
1066 1070
1067 1071 /* ARGSUSED */
1068 1072 static int
1069 1073 bge_set_priv_prop(bge_t *bgep, const char *pr_name, uint_t pr_valsize,
1070 1074 const void *pr_val)
1071 1075 {
1072 1076 int err = 0;
1073 1077 long result;
1074 1078
1075 1079 if (strcmp(pr_name, "_adv_pause_cap") == 0) {
1076 1080 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1077 1081 if (result > 1 || result < 0) {
1078 1082 err = EINVAL;
1079 1083 } else {
1080 1084 bgep->param_adv_pause = (uint32_t)result;
1081 1085 if (bge_reprogram(bgep) == IOC_INVAL)
1082 1086 err = EINVAL;
1083 1087 }
1084 1088 return (err);
1085 1089 }
1086 1090 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) {
1087 1091 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1088 1092 if (result > 1 || result < 0) {
1089 1093 err = EINVAL;
1090 1094 } else {
1091 1095 bgep->param_adv_asym_pause = (uint32_t)result;
1092 1096 if (bge_reprogram(bgep) == IOC_INVAL)
1093 1097 err = EINVAL;
1094 1098 }
1095 1099 return (err);
1096 1100 }
1097 1101 if (strcmp(pr_name, "_drain_max") == 0) {
1098 1102
1099 1103 /*
1100 1104 * on the Tx side, we need to update the h/w register for
1101 1105 * real packet transmission per packet. The drain_max parameter
1102 1106 * is used to reduce the register access. This parameter
1103 1107 * controls the max number of packets that we will hold before
1104 1108 * updating the bge h/w to trigger h/w transmit. The bge
1105 1109 * chipset usually has a max of 512 Tx descriptors, thus
1106 1110 * the upper bound on drain_max is 512.
1107 1111 */
1108 1112 if (pr_val == NULL) {
1109 1113 err = EINVAL;
1110 1114 return (err);
1111 1115 }
1112 1116 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1113 1117 if (result > 512 || result < 1)
1114 1118 err = EINVAL;
1115 1119 else {
1116 1120 bgep->param_drain_max = (uint32_t)result;
1117 1121 if (bge_reprogram(bgep) == IOC_INVAL)
1118 1122 err = EINVAL;
1119 1123 }
1120 1124 return (err);
1121 1125 }
1122 1126 if (strcmp(pr_name, "_msi_cnt") == 0) {
1123 1127
1124 1128 if (pr_val == NULL) {
1125 1129 err = EINVAL;
1126 1130 return (err);
1127 1131 }
1128 1132 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result);
1129 1133 if (result > 7 || result < 0)
1130 1134 err = EINVAL;
1131 1135 else {
1132 1136 bgep->param_msi_cnt = (uint32_t)result;
1133 1137 if (bge_reprogram(bgep) == IOC_INVAL)
1134 1138 err = EINVAL;
1135 1139 }
1136 1140 return (err);
1137 1141 }
1138 1142 if (strcmp(pr_name, "_rx_intr_coalesce_blank_time") == 0) {
1139 1143 if (ddi_strtol(pr_val, (char **)NULL, 0, &result) != 0)
1140 1144 return (EINVAL);
1141 1145 if (result < 0)
1142 1146 err = EINVAL;
1143 1147 else {
1144 1148 bgep->chipid.rx_ticks_norm = (uint32_t)result;
1145 1149 bge_chip_coalesce_update(bgep);
1146 1150 }
1147 1151 return (err);
1148 1152 }
1149 1153
1150 1154 if (strcmp(pr_name, "_rx_intr_coalesce_pkt_cnt") == 0) {
1151 1155 if (ddi_strtol(pr_val, (char **)NULL, 0, &result) != 0)
1152 1156 return (EINVAL);
1153 1157
1154 1158 if (result < 0)
1155 1159 err = EINVAL;
1156 1160 else {
1157 1161 bgep->chipid.rx_count_norm = (uint32_t)result;
1158 1162 bge_chip_coalesce_update(bgep);
1159 1163 }
1160 1164 return (err);
1161 1165 }
1162 1166 if (strcmp(pr_name, "_tx_intr_coalesce_blank_time") == 0) {
1163 1167 if (ddi_strtol(pr_val, (char **)NULL, 0, &result) != 0)
1164 1168 return (EINVAL);
1165 1169 if (result < 0)
1166 1170 err = EINVAL;
1167 1171 else {
1168 1172 bgep->chipid.tx_ticks_norm = (uint32_t)result;
1169 1173 bge_chip_coalesce_update(bgep);
1170 1174 }
1171 1175 return (err);
1172 1176 }
1173 1177
1174 1178 if (strcmp(pr_name, "_tx_intr_coalesce_pkt_cnt") == 0) {
1175 1179 if (ddi_strtol(pr_val, (char **)NULL, 0, &result) != 0)
1176 1180 return (EINVAL);
1177 1181
1178 1182 if (result < 0)
1179 1183 err = EINVAL;
1180 1184 else {
1181 1185 bgep->chipid.tx_count_norm = (uint32_t)result;
1182 1186 bge_chip_coalesce_update(bgep);
1183 1187 }
1184 1188 return (err);
1185 1189 }
1186 1190 return (ENOTSUP);
1187 1191 }
1188 1192
1189 1193 static int
1190 1194 bge_get_priv_prop(bge_t *bge, const char *pr_name, uint_t pr_valsize,
1191 1195 void *pr_val)
1192 1196 {
1193 1197 int value;
1194 1198
1195 1199 if (strcmp(pr_name, "_adv_pause_cap") == 0)
1196 1200 value = bge->param_adv_pause;
1197 1201 else if (strcmp(pr_name, "_adv_asym_pause_cap") == 0)
1198 1202 value = bge->param_adv_asym_pause;
1199 1203 else if (strcmp(pr_name, "_drain_max") == 0)
1200 1204 value = bge->param_drain_max;
1201 1205 else if (strcmp(pr_name, "_msi_cnt") == 0)
1202 1206 value = bge->param_msi_cnt;
1203 1207 else if (strcmp(pr_name, "_rx_intr_coalesce_blank_time") == 0)
1204 1208 value = bge->chipid.rx_ticks_norm;
1205 1209 else if (strcmp(pr_name, "_tx_intr_coalesce_blank_time") == 0)
1206 1210 value = bge->chipid.tx_ticks_norm;
1207 1211 else if (strcmp(pr_name, "_rx_intr_coalesce_pkt_cnt") == 0)
1208 1212 value = bge->chipid.rx_count_norm;
1209 1213 else if (strcmp(pr_name, "_tx_intr_coalesce_pkt_cnt") == 0)
1210 1214 value = bge->chipid.tx_count_norm;
1211 1215 else
1212 1216 return (ENOTSUP);
1213 1217
1214 1218 (void) snprintf(pr_val, pr_valsize, "%d", value);
1215 1219 return (0);
1216 1220 }
1217 1221
1218 1222 static void
1219 1223 bge_priv_propinfo(const char *pr_name, mac_prop_info_handle_t mph)
1220 1224 {
1221 1225 char valstr[64];
1222 1226 int value;
1223 1227
1224 1228 if (strcmp(pr_name, "_adv_pause_cap") == 0)
1225 1229 value = 1;
1226 1230 else if (strcmp(pr_name, "_adv_asym_pause_cap") == 0)
1227 1231 value = 1;
1228 1232 else if (strcmp(pr_name, "_drain_max") == 0)
1229 1233 value = 64;
1230 1234 else if (strcmp(pr_name, "_msi_cnt") == 0)
1231 1235 value = 0;
1232 1236 else if (strcmp(pr_name, "_rx_intr_coalesce_blank_time") == 0)
1233 1237 value = bge_rx_ticks_norm;
1234 1238 else if (strcmp(pr_name, "_tx_intr_coalesce_blank_time") == 0)
1235 1239 value = bge_tx_ticks_norm;
1236 1240 else if (strcmp(pr_name, "_rx_intr_coalesce_pkt_cnt") == 0)
1237 1241 value = bge_rx_count_norm;
1238 1242 else if (strcmp(pr_name, "_tx_intr_coalesce_pkt_cnt") == 0)
1239 1243 value = bge_tx_count_norm;
1240 1244 else
1241 1245 return;
1242 1246
1243 1247 (void) snprintf(valstr, sizeof (valstr), "%d", value);
1244 1248 mac_prop_info_set_default_str(mph, valstr);
1245 1249 }
1246 1250
1247 1251 /*
1248 1252 * Compute the index of the required bit in the multicast hash map.
1249 1253 * This must mirror the way the hardware actually does it!
1250 1254 * See Broadcom document 570X-PG102-R page 125.
1251 1255 */
1252 1256 static uint32_t
1253 1257 bge_hash_index(const uint8_t *mca)
1254 1258 {
1255 1259 uint32_t hash;
1256 1260
1257 1261 CRC32(hash, mca, ETHERADDRL, -1U, crc32_table);
1258 1262
1259 1263 return (hash);
1260 1264 }
1261 1265
1262 1266 /*
1263 1267 * bge_m_multicst_add() -- enable/disable a multicast address
1264 1268 */
1265 1269 static int
1266 1270 bge_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
1267 1271 {
1268 1272 bge_t *bgep = arg; /* private device info */
1269 1273 uint32_t hash;
1270 1274 uint32_t index;
1271 1275 uint32_t word;
1272 1276 uint32_t bit;
1273 1277 uint8_t *refp;
1274 1278
1275 1279 BGE_TRACE(("bge_m_multicst($%p, %s, %s)", arg,
1276 1280 (add) ? "add" : "remove", ether_sprintf((void *)mca)));
1277 1281
1278 1282 /*
1279 1283 * Precalculate all required masks, pointers etc ...
1280 1284 */
1281 1285 hash = bge_hash_index(mca);
1282 1286 index = hash % BGE_HASH_TABLE_SIZE;
1283 1287 word = index/32u;
1284 1288 bit = 1 << (index % 32u);
1285 1289 refp = &bgep->mcast_refs[index];
1286 1290
1287 1291 BGE_DEBUG(("bge_m_multicst: hash 0x%x index %d (%d:0x%x) = %d",
1288 1292 hash, index, word, bit, *refp));
1289 1293
1290 1294 /*
1291 1295 * We must set the appropriate bit in the hash map (and the
1292 1296 * corresponding h/w register) when the refcount goes from 0
1293 1297 * to >0, and clear it when the last ref goes away (refcount
1294 1298 * goes from >0 back to 0). If we change the hash map, we
1295 1299 * must also update the chip's hardware map registers.
1296 1300 */
1297 1301 mutex_enter(bgep->genlock);
1298 1302 if (!(bgep->progress & PROGRESS_INTR)) {
1299 1303 /* can happen during autorecovery */
1300 1304 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1301 1305 mutex_exit(bgep->genlock);
1302 1306 return (EIO);
1303 1307 }
1304 1308 if (add) {
1305 1309 if ((*refp)++ == 0) {
1306 1310 bgep->mcast_hash[word] |= bit;
1307 1311 #ifdef BGE_IPMI_ASF
1308 1312 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) {
1309 1313 #else
1310 1314 if (bge_chip_sync(bgep) == DDI_FAILURE) {
1311 1315 #endif
1312 1316 (void) bge_check_acc_handle(bgep,
1313 1317 bgep->cfg_handle);
1314 1318 (void) bge_check_acc_handle(bgep,
1315 1319 bgep->io_handle);
1316 1320 ddi_fm_service_impact(bgep->devinfo,
1317 1321 DDI_SERVICE_DEGRADED);
1318 1322 mutex_exit(bgep->genlock);
1319 1323 return (EIO);
1320 1324 }
1321 1325 }
1322 1326 } else {
1323 1327 if (--(*refp) == 0) {
1324 1328 bgep->mcast_hash[word] &= ~bit;
1325 1329 #ifdef BGE_IPMI_ASF
1326 1330 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) {
1327 1331 #else
1328 1332 if (bge_chip_sync(bgep) == DDI_FAILURE) {
1329 1333 #endif
1330 1334 (void) bge_check_acc_handle(bgep,
1331 1335 bgep->cfg_handle);
1332 1336 (void) bge_check_acc_handle(bgep,
1333 1337 bgep->io_handle);
1334 1338 ddi_fm_service_impact(bgep->devinfo,
1335 1339 DDI_SERVICE_DEGRADED);
1336 1340 mutex_exit(bgep->genlock);
1337 1341 return (EIO);
1338 1342 }
1339 1343 }
1340 1344 }
1341 1345 BGE_DEBUG(("bge_m_multicst($%p) done", arg));
1342 1346 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
1343 1347 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1344 1348 mutex_exit(bgep->genlock);
1345 1349 return (EIO);
1346 1350 }
1347 1351 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
1348 1352 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1349 1353 mutex_exit(bgep->genlock);
1350 1354 return (EIO);
1351 1355 }
1352 1356 mutex_exit(bgep->genlock);
1353 1357
1354 1358 return (0);
1355 1359 }
1356 1360
1357 1361 /*
1358 1362 * bge_m_promisc() -- set or reset promiscuous mode on the board
1359 1363 *
1360 1364 * Program the hardware to enable/disable promiscuous and/or
1361 1365 * receive-all-multicast modes.
1362 1366 */
1363 1367 static int
1364 1368 bge_m_promisc(void *arg, boolean_t on)
1365 1369 {
1366 1370 bge_t *bgep = arg;
1367 1371
1368 1372 BGE_TRACE(("bge_m_promisc_set($%p, %d)", arg, on));
1369 1373
1370 1374 /*
1371 1375 * Store MAC layer specified mode and pass to chip layer to update h/w
1372 1376 */
1373 1377 mutex_enter(bgep->genlock);
1374 1378 if (!(bgep->progress & PROGRESS_INTR)) {
1375 1379 /* can happen during autorecovery */
1376 1380 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1377 1381 mutex_exit(bgep->genlock);
1378 1382 return (EIO);
1379 1383 }
1380 1384 bgep->promisc = on;
1381 1385 #ifdef BGE_IPMI_ASF
1382 1386 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) {
1383 1387 #else
1384 1388 if (bge_chip_sync(bgep) == DDI_FAILURE) {
1385 1389 #endif
1386 1390 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
1387 1391 (void) bge_check_acc_handle(bgep, bgep->io_handle);
1388 1392 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1389 1393 mutex_exit(bgep->genlock);
1390 1394 return (EIO);
1391 1395 }
1392 1396 BGE_DEBUG(("bge_m_promisc_set($%p) done", arg));
1393 1397 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
1394 1398 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1395 1399 mutex_exit(bgep->genlock);
1396 1400 return (EIO);
1397 1401 }
1398 1402 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
1399 1403 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1400 1404 mutex_exit(bgep->genlock);
1401 1405 return (EIO);
1402 1406 }
1403 1407 mutex_exit(bgep->genlock);
1404 1408 return (0);
1405 1409 }
1406 1410
1407 1411 /*
1408 1412 * Find the slot for the specified unicast address
1409 1413 */
1410 1414 int
1411 1415 bge_unicst_find(bge_t *bgep, const uint8_t *mac_addr)
1412 1416 {
1413 1417 int slot;
1414 1418
1415 1419 ASSERT(mutex_owned(bgep->genlock));
1416 1420
1417 1421 for (slot = 0; slot < bgep->unicst_addr_total; slot++) {
1418 1422 if (bcmp(bgep->curr_addr[slot].addr, mac_addr, ETHERADDRL) == 0)
1419 1423 return (slot);
1420 1424 }
1421 1425
1422 1426 return (-1);
1423 1427 }
1424 1428
1425 1429 /*
1426 1430 * Programs the classifier to start steering packets matching 'mac_addr' to the
1427 1431 * specified ring 'arg'.
1428 1432 */
1429 1433 static int
1430 1434 bge_addmac(void *arg, const uint8_t *mac_addr)
1431 1435 {
1432 1436 recv_ring_t *rrp = (recv_ring_t *)arg;
1433 1437 bge_t *bgep = rrp->bgep;
1434 1438 bge_recv_rule_t *rulep = bgep->recv_rules;
1435 1439 bge_rule_info_t *rinfop = NULL;
1436 1440 uint8_t ring = (uint8_t)(rrp - bgep->recv) + 1;
1437 1441 int i;
1438 1442 uint16_t tmp16;
1439 1443 uint32_t tmp32;
1440 1444 int slot;
1441 1445 int err;
1442 1446
1443 1447 mutex_enter(bgep->genlock);
1444 1448 if (bgep->unicst_addr_avail == 0) {
1445 1449 mutex_exit(bgep->genlock);
1446 1450 return (ENOSPC);
1447 1451 }
1448 1452
1449 1453 /*
1450 1454 * First add the unicast address to a available slot.
1451 1455 */
1452 1456 slot = bge_unicst_find(bgep, mac_addr);
1453 1457 ASSERT(slot == -1);
1454 1458
1455 1459 for (slot = 0; slot < bgep->unicst_addr_total; slot++) {
1456 1460 if (!bgep->curr_addr[slot].set) {
1457 1461 bgep->curr_addr[slot].set = B_TRUE;
1458 1462 break;
1459 1463 }
1460 1464 }
1461 1465
1462 1466 ASSERT(slot < bgep->unicst_addr_total);
1463 1467 bgep->unicst_addr_avail--;
1464 1468 mutex_exit(bgep->genlock);
1465 1469
1466 1470 if ((err = bge_unicst_set(bgep, mac_addr, slot)) != 0)
1467 1471 goto fail;
1468 1472
1469 1473 /* A rule is already here. Deny this. */
1470 1474 if (rrp->mac_addr_rule != NULL) {
1471 1475 err = ether_cmp(mac_addr, rrp->mac_addr_val) ? EEXIST : EBUSY;
1472 1476 goto fail;
1473 1477 }
1474 1478
1475 1479 /*
1476 1480 * Allocate a bge_rule_info_t to keep track of which rule slots
1477 1481 * are being used.
1478 1482 */
1479 1483 rinfop = kmem_zalloc(sizeof (bge_rule_info_t), KM_NOSLEEP);
1480 1484 if (rinfop == NULL) {
1481 1485 err = ENOMEM;
1482 1486 goto fail;
1483 1487 }
1484 1488
1485 1489 /*
1486 1490 * Look for the starting slot to place the rules.
1487 1491 * The two slots we reserve must be contiguous.
1488 1492 */
1489 1493 for (i = 0; i + 1 < RECV_RULES_NUM_MAX; i++)
1490 1494 if ((rulep[i].control & RECV_RULE_CTL_ENABLE) == 0 &&
1491 1495 (rulep[i+1].control & RECV_RULE_CTL_ENABLE) == 0)
1492 1496 break;
1493 1497
1494 1498 ASSERT(i + 1 < RECV_RULES_NUM_MAX);
1495 1499
1496 1500 bcopy(mac_addr, &tmp32, sizeof (tmp32));
1497 1501 rulep[i].mask_value = ntohl(tmp32);
1498 1502 rulep[i].control = RULE_DEST_MAC_1(ring) | RECV_RULE_CTL_AND;
1499 1503 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep[i].mask_value);
1500 1504 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep[i].control);
1501 1505
1502 1506 bcopy(mac_addr + 4, &tmp16, sizeof (tmp16));
1503 1507 rulep[i+1].mask_value = 0xffff0000 | ntohs(tmp16);
1504 1508 rulep[i+1].control = RULE_DEST_MAC_2(ring);
1505 1509 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i+1), rulep[i+1].mask_value);
1506 1510 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i+1), rulep[i+1].control);
1507 1511 rinfop->start = i;
1508 1512 rinfop->count = 2;
1509 1513
1510 1514 rrp->mac_addr_rule = rinfop;
1511 1515 bcopy(mac_addr, rrp->mac_addr_val, ETHERADDRL);
1512 1516
1513 1517 return (0);
1514 1518
1515 1519 fail:
1516 1520 /* Clear the address just set */
1517 1521 (void) bge_unicst_set(bgep, zero_addr, slot);
1518 1522 mutex_enter(bgep->genlock);
1519 1523 bgep->curr_addr[slot].set = B_FALSE;
1520 1524 bgep->unicst_addr_avail++;
1521 1525 mutex_exit(bgep->genlock);
1522 1526
1523 1527 return (err);
1524 1528 }
1525 1529
1526 1530 /*
1527 1531 * Stop classifying packets matching the MAC address to the specified ring.
1528 1532 */
1529 1533 static int
1530 1534 bge_remmac(void *arg, const uint8_t *mac_addr)
1531 1535 {
1532 1536 recv_ring_t *rrp = (recv_ring_t *)arg;
1533 1537 bge_t *bgep = rrp->bgep;
1534 1538 bge_recv_rule_t *rulep = bgep->recv_rules;
1535 1539 bge_rule_info_t *rinfop = rrp->mac_addr_rule;
1536 1540 int start;
1537 1541 int slot;
1538 1542 int err;
1539 1543
1540 1544 /*
1541 1545 * Remove the MAC address from its slot.
1542 1546 */
1543 1547 mutex_enter(bgep->genlock);
1544 1548 slot = bge_unicst_find(bgep, mac_addr);
1545 1549 if (slot == -1) {
1546 1550 mutex_exit(bgep->genlock);
1547 1551 return (EINVAL);
1548 1552 }
1549 1553
1550 1554 ASSERT(bgep->curr_addr[slot].set);
1551 1555 mutex_exit(bgep->genlock);
1552 1556
1553 1557 if ((err = bge_unicst_set(bgep, zero_addr, slot)) != 0)
1554 1558 return (err);
1555 1559
1556 1560 if (rinfop == NULL || ether_cmp(mac_addr, rrp->mac_addr_val) != 0)
1557 1561 return (EINVAL);
1558 1562
1559 1563 start = rinfop->start;
1560 1564 rulep[start].mask_value = 0;
1561 1565 rulep[start].control = 0;
1562 1566 bge_reg_put32(bgep, RECV_RULE_MASK_REG(start), rulep[start].mask_value);
1563 1567 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(start), rulep[start].control);
1564 1568 start++;
1565 1569 rulep[start].mask_value = 0;
1566 1570 rulep[start].control = 0;
1567 1571 bge_reg_put32(bgep, RECV_RULE_MASK_REG(start), rulep[start].mask_value);
1568 1572 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(start), rulep[start].control);
1569 1573
1570 1574 kmem_free(rinfop, sizeof (bge_rule_info_t));
1571 1575 rrp->mac_addr_rule = NULL;
1572 1576 bzero(rrp->mac_addr_val, ETHERADDRL);
1573 1577
1574 1578 mutex_enter(bgep->genlock);
1575 1579 bgep->curr_addr[slot].set = B_FALSE;
1576 1580 bgep->unicst_addr_avail++;
1577 1581 mutex_exit(bgep->genlock);
1578 1582
1579 1583 return (0);
1580 1584 }
1581 1585
1582 1586 static int
1583 1587 bge_flag_intr_enable(mac_intr_handle_t ih)
1584 1588 {
1585 1589 recv_ring_t *rrp = (recv_ring_t *)ih;
1586 1590 bge_t *bgep = rrp->bgep;
1587 1591
1588 1592 mutex_enter(bgep->genlock);
1589 1593 rrp->poll_flag = 0;
1590 1594 mutex_exit(bgep->genlock);
1591 1595
1592 1596 return (0);
1593 1597 }
1594 1598
1595 1599 static int
1596 1600 bge_flag_intr_disable(mac_intr_handle_t ih)
1597 1601 {
1598 1602 recv_ring_t *rrp = (recv_ring_t *)ih;
1599 1603 bge_t *bgep = rrp->bgep;
1600 1604
1601 1605 mutex_enter(bgep->genlock);
1602 1606 rrp->poll_flag = 1;
1603 1607 mutex_exit(bgep->genlock);
1604 1608
1605 1609 return (0);
1606 1610 }
1607 1611
1608 1612 static int
1609 1613 bge_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
1610 1614 {
1611 1615 recv_ring_t *rx_ring;
1612 1616
1613 1617 rx_ring = (recv_ring_t *)rh;
1614 1618 mutex_enter(rx_ring->rx_lock);
1615 1619 rx_ring->ring_gen_num = mr_gen_num;
1616 1620 mutex_exit(rx_ring->rx_lock);
1617 1621 return (0);
1618 1622 }
1619 1623
1620 1624
1621 1625 /*
1622 1626 * Callback funtion for MAC layer to register all rings
1623 1627 * for given ring_group, noted by rg_index.
1624 1628 */
1625 1629 void
1626 1630 bge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index,
1627 1631 const int index, mac_ring_info_t *infop, mac_ring_handle_t rh)
1628 1632 {
1629 1633 bge_t *bgep = arg;
1630 1634 mac_intr_t *mintr;
1631 1635
1632 1636 switch (rtype) {
1633 1637 case MAC_RING_TYPE_RX: {
1634 1638 recv_ring_t *rx_ring;
1635 1639 ASSERT(rg_index >= 0 && rg_index < MIN(bgep->chipid.rx_rings,
1636 1640 MAC_ADDRESS_REGS_MAX) && index == 0);
1637 1641
1638 1642 rx_ring = &bgep->recv[rg_index];
1639 1643 rx_ring->ring_handle = rh;
1640 1644
1641 1645 infop->mri_driver = (mac_ring_driver_t)rx_ring;
1642 1646 infop->mri_start = bge_ring_start;
1643 1647 infop->mri_stop = NULL;
1644 1648 infop->mri_poll = bge_poll_ring;
1645 1649 infop->mri_stat = bge_rx_ring_stat;
1646 1650
1647 1651 mintr = &infop->mri_intr;
1648 1652 mintr->mi_handle = (mac_intr_handle_t)rx_ring;
1649 1653 mintr->mi_enable = bge_flag_intr_enable;
1650 1654 mintr->mi_disable = bge_flag_intr_disable;
1651 1655
1652 1656 break;
1653 1657 }
1654 1658 case MAC_RING_TYPE_TX:
1655 1659 default:
1656 1660 ASSERT(0);
1657 1661 break;
1658 1662 }
1659 1663 }
1660 1664
1661 1665 /*
1662 1666 * Fill infop passed as argument
1663 1667 * fill in respective ring_group info
1664 1668 * Each group has a single ring in it. We keep it simple
1665 1669 * and use the same internal handle for rings and groups.
1666 1670 */
1667 1671 void
1668 1672 bge_fill_group(void *arg, mac_ring_type_t rtype, const int rg_index,
1669 1673 mac_group_info_t *infop, mac_group_handle_t gh)
1670 1674 {
1671 1675 bge_t *bgep = arg;
1672 1676
1673 1677 switch (rtype) {
1674 1678 case MAC_RING_TYPE_RX: {
1675 1679 recv_ring_t *rx_ring;
1676 1680
1677 1681 ASSERT(rg_index >= 0 && rg_index < MIN(bgep->chipid.rx_rings,
1678 1682 MAC_ADDRESS_REGS_MAX));
1679 1683 rx_ring = &bgep->recv[rg_index];
1680 1684 rx_ring->ring_group_handle = gh;
1681 1685
1682 1686 infop->mgi_driver = (mac_group_driver_t)rx_ring;
1683 1687 infop->mgi_start = NULL;
1684 1688 infop->mgi_stop = NULL;
1685 1689 infop->mgi_addmac = bge_addmac;
1686 1690 infop->mgi_remmac = bge_remmac;
1687 1691 infop->mgi_count = 1;
1688 1692 break;
1689 1693 }
1690 1694 case MAC_RING_TYPE_TX:
1691 1695 default:
1692 1696 ASSERT(0);
1693 1697 break;
1694 1698 }
1695 1699 }
1696 1700
1697 1701 /*ARGSUSED*/
1698 1702 static boolean_t
1699 1703 bge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
1700 1704 {
1701 1705 bge_t *bgep = arg;
1702 1706
1703 1707 switch (cap) {
1704 1708 case MAC_CAPAB_HCKSUM: {
1705 1709 uint32_t *txflags = cap_data;
1706 1710
1707 1711 *txflags = HCKSUM_INET_FULL_V4 | HCKSUM_IPHDRCKSUM;
1708 1712 break;
1709 1713 }
1710 1714 case MAC_CAPAB_RINGS: {
1711 1715 mac_capab_rings_t *cap_rings = cap_data;
1712 1716
1713 1717 /* Temporarily disable multiple tx rings. */
1714 1718 if (cap_rings->mr_type != MAC_RING_TYPE_RX)
1715 1719 return (B_FALSE);
1716 1720
1717 1721 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
1718 1722 cap_rings->mr_rnum = cap_rings->mr_gnum =
1719 1723 MIN(bgep->chipid.rx_rings, MAC_ADDRESS_REGS_MAX);
1720 1724 cap_rings->mr_rget = bge_fill_ring;
1721 1725 cap_rings->mr_gget = bge_fill_group;
1722 1726 break;
1723 1727 }
1724 1728 default:
1725 1729 return (B_FALSE);
1726 1730 }
1727 1731 return (B_TRUE);
1728 1732 }
1729 1733
1730 1734 /*
1731 1735 * Loopback ioctl code
1732 1736 */
1733 1737
1734 1738 static lb_property_t loopmodes[] = {
1735 1739 { normal, "normal", BGE_LOOP_NONE },
1736 1740 { external, "1000Mbps", BGE_LOOP_EXTERNAL_1000 },
1737 1741 { external, "100Mbps", BGE_LOOP_EXTERNAL_100 },
1738 1742 { external, "10Mbps", BGE_LOOP_EXTERNAL_10 },
1739 1743 { internal, "PHY", BGE_LOOP_INTERNAL_PHY },
1740 1744 { internal, "MAC", BGE_LOOP_INTERNAL_MAC }
1741 1745 };
1742 1746
1743 1747 static enum ioc_reply
1744 1748 bge_set_loop_mode(bge_t *bgep, uint32_t mode)
1745 1749 {
1746 1750 /*
1747 1751 * If the mode isn't being changed, there's nothing to do ...
1748 1752 */
1749 1753 if (mode == bgep->param_loop_mode)
1750 1754 return (IOC_ACK);
1751 1755
1752 1756 /*
1753 1757 * Validate the requested mode and prepare a suitable message
1754 1758 * to explain the link down/up cycle that the change will
1755 1759 * probably induce ...
1756 1760 */
1757 1761 switch (mode) {
1758 1762 default:
1759 1763 return (IOC_INVAL);
1760 1764
1761 1765 case BGE_LOOP_NONE:
1762 1766 case BGE_LOOP_EXTERNAL_1000:
1763 1767 case BGE_LOOP_EXTERNAL_100:
1764 1768 case BGE_LOOP_EXTERNAL_10:
1765 1769 case BGE_LOOP_INTERNAL_PHY:
1766 1770 case BGE_LOOP_INTERNAL_MAC:
1767 1771 break;
1768 1772 }
1769 1773
1770 1774 /*
1771 1775 * All OK; tell the caller to reprogram
1772 1776 * the PHY and/or MAC for the new mode ...
1773 1777 */
1774 1778 bgep->param_loop_mode = mode;
1775 1779 return (IOC_RESTART_ACK);
1776 1780 }
1777 1781
1778 1782 static enum ioc_reply
1779 1783 bge_loop_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
1780 1784 {
1781 1785 lb_info_sz_t *lbsp;
1782 1786 lb_property_t *lbpp;
1783 1787 uint32_t *lbmp;
1784 1788 int cmd;
1785 1789
1786 1790 _NOTE(ARGUNUSED(wq))
1787 1791
1788 1792 /*
1789 1793 * Validate format of ioctl
1790 1794 */
1791 1795 if (mp->b_cont == NULL)
1792 1796 return (IOC_INVAL);
1793 1797
1794 1798 cmd = iocp->ioc_cmd;
1795 1799 switch (cmd) {
1796 1800 default:
1797 1801 /* NOTREACHED */
1798 1802 bge_error(bgep, "bge_loop_ioctl: invalid cmd 0x%x", cmd);
1799 1803 return (IOC_INVAL);
1800 1804
1801 1805 case LB_GET_INFO_SIZE:
1802 1806 if (iocp->ioc_count != sizeof (lb_info_sz_t))
1803 1807 return (IOC_INVAL);
1804 1808 lbsp = (void *)mp->b_cont->b_rptr;
1805 1809 *lbsp = sizeof (loopmodes);
1806 1810 return (IOC_REPLY);
1807 1811
1808 1812 case LB_GET_INFO:
1809 1813 if (iocp->ioc_count != sizeof (loopmodes))
1810 1814 return (IOC_INVAL);
1811 1815 lbpp = (void *)mp->b_cont->b_rptr;
1812 1816 bcopy(loopmodes, lbpp, sizeof (loopmodes));
1813 1817 return (IOC_REPLY);
1814 1818
1815 1819 case LB_GET_MODE:
1816 1820 if (iocp->ioc_count != sizeof (uint32_t))
1817 1821 return (IOC_INVAL);
1818 1822 lbmp = (void *)mp->b_cont->b_rptr;
1819 1823 *lbmp = bgep->param_loop_mode;
1820 1824 return (IOC_REPLY);
1821 1825
1822 1826 case LB_SET_MODE:
1823 1827 if (iocp->ioc_count != sizeof (uint32_t))
1824 1828 return (IOC_INVAL);
1825 1829 lbmp = (void *)mp->b_cont->b_rptr;
1826 1830 return (bge_set_loop_mode(bgep, *lbmp));
1827 1831 }
1828 1832 }
1829 1833
1830 1834 /*
1831 1835 * Specific bge IOCTLs, the gld module handles the generic ones.
1832 1836 */
1833 1837 static void
1834 1838 bge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp)
1835 1839 {
1836 1840 bge_t *bgep = arg;
1837 1841 struct iocblk *iocp;
1838 1842 enum ioc_reply status;
1839 1843 boolean_t need_privilege;
1840 1844 int err;
1841 1845 int cmd;
1842 1846
1843 1847 /*
1844 1848 * Validate the command before bothering with the mutex ...
1845 1849 */
1846 1850 iocp = (void *)mp->b_rptr;
1847 1851 iocp->ioc_error = 0;
1848 1852 need_privilege = B_TRUE;
1849 1853 cmd = iocp->ioc_cmd;
1850 1854 switch (cmd) {
1851 1855 default:
1852 1856 miocnak(wq, mp, 0, EINVAL);
1853 1857 return;
1854 1858
1855 1859 case BGE_MII_READ:
1856 1860 case BGE_MII_WRITE:
1857 1861 case BGE_SEE_READ:
1858 1862 case BGE_SEE_WRITE:
1859 1863 case BGE_FLASH_READ:
1860 1864 case BGE_FLASH_WRITE:
1861 1865 case BGE_DIAG:
1862 1866 case BGE_PEEK:
1863 1867 case BGE_POKE:
1864 1868 case BGE_PHY_RESET:
1865 1869 case BGE_SOFT_RESET:
1866 1870 case BGE_HARD_RESET:
1867 1871 break;
1868 1872
1869 1873 case LB_GET_INFO_SIZE:
1870 1874 case LB_GET_INFO:
1871 1875 case LB_GET_MODE:
1872 1876 need_privilege = B_FALSE;
1873 1877 /* FALLTHRU */
1874 1878 case LB_SET_MODE:
1875 1879 break;
1876 1880
1877 1881 }
1878 1882
1879 1883 if (need_privilege) {
1880 1884 /*
1881 1885 * Check for specific net_config privilege on Solaris 10+.
1882 1886 */
1883 1887 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE);
1884 1888 if (err != 0) {
1885 1889 miocnak(wq, mp, 0, err);
1886 1890 return;
1887 1891 }
1888 1892 }
1889 1893
1890 1894 mutex_enter(bgep->genlock);
1891 1895 if (!(bgep->progress & PROGRESS_INTR)) {
1892 1896 /* can happen during autorecovery */
1893 1897 mutex_exit(bgep->genlock);
1894 1898 miocnak(wq, mp, 0, EIO);
1895 1899 return;
1896 1900 }
1897 1901
1898 1902 switch (cmd) {
1899 1903 default:
1900 1904 _NOTE(NOTREACHED)
1901 1905 status = IOC_INVAL;
1902 1906 break;
1903 1907
1904 1908 case BGE_MII_READ:
1905 1909 case BGE_MII_WRITE:
1906 1910 case BGE_SEE_READ:
1907 1911 case BGE_SEE_WRITE:
1908 1912 case BGE_FLASH_READ:
1909 1913 case BGE_FLASH_WRITE:
1910 1914 case BGE_DIAG:
1911 1915 case BGE_PEEK:
1912 1916 case BGE_POKE:
1913 1917 case BGE_PHY_RESET:
1914 1918 case BGE_SOFT_RESET:
1915 1919 case BGE_HARD_RESET:
1916 1920 status = bge_chip_ioctl(bgep, wq, mp, iocp);
1917 1921 break;
1918 1922
1919 1923 case LB_GET_INFO_SIZE:
1920 1924 case LB_GET_INFO:
1921 1925 case LB_GET_MODE:
1922 1926 case LB_SET_MODE:
1923 1927 status = bge_loop_ioctl(bgep, wq, mp, iocp);
1924 1928 break;
1925 1929
1926 1930 }
1927 1931
1928 1932 /*
1929 1933 * Do we need to reprogram the PHY and/or the MAC?
1930 1934 * Do it now, while we still have the mutex.
1931 1935 *
1932 1936 * Note: update the PHY first, 'cos it controls the
1933 1937 * speed/duplex parameters that the MAC code uses.
1934 1938 */
1935 1939 switch (status) {
1936 1940 case IOC_RESTART_REPLY:
1937 1941 case IOC_RESTART_ACK:
1938 1942 if (bge_reprogram(bgep) == IOC_INVAL)
1939 1943 status = IOC_INVAL;
1940 1944 break;
1941 1945 }
1942 1946
1943 1947 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
1944 1948 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1945 1949 status = IOC_INVAL;
1946 1950 }
1947 1951 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
1948 1952 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
1949 1953 status = IOC_INVAL;
1950 1954 }
1951 1955 mutex_exit(bgep->genlock);
1952 1956
1953 1957 /*
1954 1958 * Finally, decide how to reply
1955 1959 */
1956 1960 switch (status) {
1957 1961 default:
1958 1962 case IOC_INVAL:
1959 1963 /*
1960 1964 * Error, reply with a NAK and EINVAL or the specified error
1961 1965 */
1962 1966 miocnak(wq, mp, 0, iocp->ioc_error == 0 ?
1963 1967 EINVAL : iocp->ioc_error);
1964 1968 break;
1965 1969
1966 1970 case IOC_DONE:
1967 1971 /*
1968 1972 * OK, reply already sent
1969 1973 */
1970 1974 break;
1971 1975
1972 1976 case IOC_RESTART_ACK:
1973 1977 case IOC_ACK:
1974 1978 /*
1975 1979 * OK, reply with an ACK
1976 1980 */
1977 1981 miocack(wq, mp, 0, 0);
1978 1982 break;
1979 1983
1980 1984 case IOC_RESTART_REPLY:
1981 1985 case IOC_REPLY:
1982 1986 /*
1983 1987 * OK, send prepared reply as ACK or NAK
1984 1988 */
1985 1989 mp->b_datap->db_type = iocp->ioc_error == 0 ?
1986 1990 M_IOCACK : M_IOCNAK;
1987 1991 qreply(wq, mp);
1988 1992 break;
1989 1993 }
1990 1994 }
1991 1995
1992 1996 /*
1993 1997 * ========== Per-instance setup/teardown code ==========
1994 1998 */
1995 1999
1996 2000 #undef BGE_DBG
1997 2001 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */
1998 2002 /*
1999 2003 * Allocate an area of memory and a DMA handle for accessing it
2000 2004 */
2001 2005 static int
2002 2006 bge_alloc_dma_mem(bge_t *bgep, size_t memsize, ddi_device_acc_attr_t *attr_p,
2003 2007 uint_t dma_flags, dma_area_t *dma_p)
2004 2008 {
2005 2009 caddr_t va;
2006 2010 int err;
2007 2011
2008 2012 BGE_TRACE(("bge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)",
2009 2013 (void *)bgep, memsize, attr_p, dma_flags, dma_p));
2010 2014
2011 2015 /*
2012 2016 * Allocate handle
2013 2017 */
2014 2018 err = ddi_dma_alloc_handle(bgep->devinfo, &dma_attr,
2015 2019 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl);
2016 2020 if (err != DDI_SUCCESS)
2017 2021 return (DDI_FAILURE);
2018 2022
2019 2023 /*
2020 2024 * Allocate memory
2021 2025 */
2022 2026 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
2023 2027 dma_flags, DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength,
2024 2028 &dma_p->acc_hdl);
2025 2029 if (err != DDI_SUCCESS)
2026 2030 return (DDI_FAILURE);
2027 2031
2028 2032 /*
2029 2033 * Bind the two together
2030 2034 */
2031 2035 dma_p->mem_va = va;
2032 2036 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
2033 2037 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL,
2034 2038 &dma_p->cookie, &dma_p->ncookies);
2035 2039
2036 2040 BGE_DEBUG(("bge_alloc_dma_mem(): bind %d bytes; err %d, %d cookies",
2037 2041 dma_p->alength, err, dma_p->ncookies));
2038 2042
2039 2043 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1)
2040 2044 return (DDI_FAILURE);
2041 2045
2042 2046 dma_p->nslots = ~0U;
2043 2047 dma_p->size = ~0U;
2044 2048 dma_p->token = ~0U;
2045 2049 dma_p->offset = 0;
2046 2050 return (DDI_SUCCESS);
2047 2051 }
2048 2052
2049 2053 /*
2050 2054 * Free one allocated area of DMAable memory
2051 2055 */
2052 2056 static void
2053 2057 bge_free_dma_mem(dma_area_t *dma_p)
2054 2058 {
2055 2059 if (dma_p->dma_hdl != NULL) {
2056 2060 if (dma_p->ncookies) {
2057 2061 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
2058 2062 dma_p->ncookies = 0;
2059 2063 }
2060 2064 ddi_dma_free_handle(&dma_p->dma_hdl);
2061 2065 dma_p->dma_hdl = NULL;
2062 2066 }
2063 2067
2064 2068 if (dma_p->acc_hdl != NULL) {
2065 2069 ddi_dma_mem_free(&dma_p->acc_hdl);
2066 2070 dma_p->acc_hdl = NULL;
2067 2071 }
2068 2072 }
2069 2073 /*
2070 2074 * Utility routine to carve a slice off a chunk of allocated memory,
2071 2075 * updating the chunk descriptor accordingly. The size of the slice
2072 2076 * is given by the product of the <qty> and <size> parameters.
2073 2077 */
2074 2078 static void
2075 2079 bge_slice_chunk(dma_area_t *slice, dma_area_t *chunk,
2076 2080 uint32_t qty, uint32_t size)
2077 2081 {
2078 2082 static uint32_t sequence = 0xbcd5704a;
2079 2083 size_t totsize;
2080 2084
2081 2085 totsize = qty*size;
2082 2086 ASSERT(totsize <= chunk->alength);
2083 2087
2084 2088 *slice = *chunk;
2085 2089 slice->nslots = qty;
2086 2090 slice->size = size;
2087 2091 slice->alength = totsize;
2088 2092 slice->token = ++sequence;
2089 2093
2090 2094 chunk->mem_va = (caddr_t)chunk->mem_va + totsize;
2091 2095 chunk->alength -= totsize;
2092 2096 chunk->offset += totsize;
2093 2097 chunk->cookie.dmac_laddress += totsize;
2094 2098 chunk->cookie.dmac_size -= totsize;
2095 2099 }
2096 2100
2097 2101 /*
2098 2102 * Initialise the specified Receive Producer (Buffer) Ring, using
2099 2103 * the information in the <dma_area> descriptors that it contains
2100 2104 * to set up all the other fields. This routine should be called
2101 2105 * only once for each ring.
2102 2106 */
2103 2107 static void
2104 2108 bge_init_buff_ring(bge_t *bgep, uint64_t ring)
2105 2109 {
2106 2110 buff_ring_t *brp;
2107 2111 bge_status_t *bsp;
2108 2112 sw_rbd_t *srbdp;
2109 2113 dma_area_t pbuf;
2110 2114 uint32_t bufsize;
2111 2115 uint32_t nslots;
2112 2116 uint32_t slot;
2113 2117 uint32_t split;
2114 2118
2115 2119 static bge_regno_t nic_ring_addrs[BGE_BUFF_RINGS_MAX] = {
2116 2120 NIC_MEM_SHADOW_BUFF_STD,
2117 2121 NIC_MEM_SHADOW_BUFF_JUMBO,
2118 2122 NIC_MEM_SHADOW_BUFF_MINI
2119 2123 };
2120 2124 static bge_regno_t mailbox_regs[BGE_BUFF_RINGS_MAX] = {
2121 2125 RECV_STD_PROD_INDEX_REG,
2122 2126 RECV_JUMBO_PROD_INDEX_REG,
2123 2127 RECV_MINI_PROD_INDEX_REG
2124 2128 };
2125 2129 static bge_regno_t buff_cons_xref[BGE_BUFF_RINGS_MAX] = {
2126 2130 STATUS_STD_BUFF_CONS_INDEX,
2127 2131 STATUS_JUMBO_BUFF_CONS_INDEX,
2128 2132 STATUS_MINI_BUFF_CONS_INDEX
2129 2133 };
2130 2134
2131 2135 BGE_TRACE(("bge_init_buff_ring($%p, %d)",
2132 2136 (void *)bgep, ring));
2133 2137
2134 2138 brp = &bgep->buff[ring];
2135 2139 nslots = brp->desc.nslots;
2136 2140 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT);
2137 2141 bufsize = brp->buf[0].size;
2138 2142
2139 2143 /*
2140 2144 * Set up the copy of the h/w RCB
2141 2145 *
2142 2146 * Note: unlike Send & Receive Return Rings, (where the max_len
2143 2147 * field holds the number of slots), in a Receive Buffer Ring
2144 2148 * this field indicates the size of each buffer in the ring.
2145 2149 */
2146 2150 brp->hw_rcb.host_ring_addr = brp->desc.cookie.dmac_laddress;
2147 2151 brp->hw_rcb.max_len = (uint16_t)bufsize;
2148 2152 brp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED;
2149 2153 brp->hw_rcb.nic_ring_addr = nic_ring_addrs[ring];
2150 2154
2151 2155 /*
2152 2156 * Other one-off initialisation of per-ring data
2153 2157 */
2154 2158 brp->bgep = bgep;
2155 2159 bsp = DMA_VPTR(bgep->status_block);
2156 2160 brp->cons_index_p = &bsp->buff_cons_index[buff_cons_xref[ring]];
2157 2161 brp->chip_mbx_reg = mailbox_regs[ring];
2158 2162 mutex_init(brp->rf_lock, NULL, MUTEX_DRIVER,
2159 2163 DDI_INTR_PRI(bgep->intr_pri));
2160 2164
2161 2165 /*
2162 2166 * Allocate the array of s/w Receive Buffer Descriptors
2163 2167 */
2164 2168 srbdp = kmem_zalloc(nslots*sizeof (*srbdp), KM_SLEEP);
2165 2169 brp->sw_rbds = srbdp;
2166 2170
2167 2171 /*
2168 2172 * Now initialise each array element once and for all
2169 2173 */
2170 2174 for (split = 0; split < BGE_SPLIT; ++split) {
2171 2175 pbuf = brp->buf[split];
2172 2176 for (slot = 0; slot < nslots/BGE_SPLIT; ++srbdp, ++slot)
2173 2177 bge_slice_chunk(&srbdp->pbuf, &pbuf, 1, bufsize);
2174 2178 ASSERT(pbuf.alength == 0);
2175 2179 }
2176 2180 }
2177 2181
2178 2182 /*
2179 2183 * Clean up initialisation done above before the memory is freed
2180 2184 */
2181 2185 static void
2182 2186 bge_fini_buff_ring(bge_t *bgep, uint64_t ring)
2183 2187 {
2184 2188 buff_ring_t *brp;
2185 2189 sw_rbd_t *srbdp;
2186 2190
2187 2191 BGE_TRACE(("bge_fini_buff_ring($%p, %d)",
2188 2192 (void *)bgep, ring));
2189 2193
2190 2194 brp = &bgep->buff[ring];
2191 2195 srbdp = brp->sw_rbds;
2192 2196 kmem_free(srbdp, brp->desc.nslots*sizeof (*srbdp));
2193 2197
2194 2198 mutex_destroy(brp->rf_lock);
2195 2199 }
2196 2200
2197 2201 /*
2198 2202 * Initialise the specified Receive (Return) Ring, using the
2199 2203 * information in the <dma_area> descriptors that it contains
2200 2204 * to set up all the other fields. This routine should be called
2201 2205 * only once for each ring.
2202 2206 */
2203 2207 static void
2204 2208 bge_init_recv_ring(bge_t *bgep, uint64_t ring)
2205 2209 {
2206 2210 recv_ring_t *rrp;
2207 2211 bge_status_t *bsp;
2208 2212 uint32_t nslots;
2209 2213
2210 2214 BGE_TRACE(("bge_init_recv_ring($%p, %d)",
2211 2215 (void *)bgep, ring));
2212 2216
2213 2217 /*
2214 2218 * The chip architecture requires that receive return rings have
2215 2219 * 512 or 1024 or 2048 elements per ring. See 570X-PG108-R page 103.
2216 2220 */
2217 2221 rrp = &bgep->recv[ring];
2218 2222 nslots = rrp->desc.nslots;
2219 2223 ASSERT(nslots == 0 || nslots == 512 ||
2220 2224 nslots == 1024 || nslots == 2048);
2221 2225
2222 2226 /*
2223 2227 * Set up the copy of the h/w RCB
2224 2228 */
2225 2229 rrp->hw_rcb.host_ring_addr = rrp->desc.cookie.dmac_laddress;
2226 2230 rrp->hw_rcb.max_len = (uint16_t)nslots;
2227 2231 rrp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED;
2228 2232 rrp->hw_rcb.nic_ring_addr = 0;
2229 2233
2230 2234 /*
2231 2235 * Other one-off initialisation of per-ring data
2232 2236 */
2233 2237 rrp->bgep = bgep;
2234 2238 bsp = DMA_VPTR(bgep->status_block);
2235 2239 rrp->prod_index_p = RECV_INDEX_P(bsp, ring);
2236 2240 rrp->chip_mbx_reg = RECV_RING_CONS_INDEX_REG(ring);
2237 2241 mutex_init(rrp->rx_lock, NULL, MUTEX_DRIVER,
2238 2242 DDI_INTR_PRI(bgep->intr_pri));
2239 2243 }
2240 2244
2241 2245
2242 2246 /*
2243 2247 * Clean up initialisation done above before the memory is freed
2244 2248 */
2245 2249 static void
2246 2250 bge_fini_recv_ring(bge_t *bgep, uint64_t ring)
2247 2251 {
2248 2252 recv_ring_t *rrp;
2249 2253
2250 2254 BGE_TRACE(("bge_fini_recv_ring($%p, %d)",
2251 2255 (void *)bgep, ring));
2252 2256
2253 2257 rrp = &bgep->recv[ring];
2254 2258 if (rrp->rx_softint)
2255 2259 ddi_remove_softintr(rrp->rx_softint);
2256 2260 mutex_destroy(rrp->rx_lock);
2257 2261 }
2258 2262
2259 2263 /*
2260 2264 * Initialise the specified Send Ring, using the information in the
2261 2265 * <dma_area> descriptors that it contains to set up all the other
2262 2266 * fields. This routine should be called only once for each ring.
2263 2267 */
2264 2268 static void
2265 2269 bge_init_send_ring(bge_t *bgep, uint64_t ring)
2266 2270 {
2267 2271 send_ring_t *srp;
2268 2272 bge_status_t *bsp;
2269 2273 sw_sbd_t *ssbdp;
2270 2274 dma_area_t desc;
2271 2275 dma_area_t pbuf;
2272 2276 uint32_t nslots;
2273 2277 uint32_t slot;
2274 2278 uint32_t split;
2275 2279 sw_txbuf_t *txbuf;
2276 2280
2277 2281 BGE_TRACE(("bge_init_send_ring($%p, %d)",
2278 2282 (void *)bgep, ring));
2279 2283
2280 2284 /*
2281 2285 * The chip architecture requires that host-based send rings
2282 2286 * have 512 elements per ring. See 570X-PG102-R page 56.
2283 2287 */
2284 2288 srp = &bgep->send[ring];
2285 2289 nslots = srp->desc.nslots;
2286 2290 ASSERT(nslots == 0 || nslots == 512);
2287 2291
2288 2292 /*
2289 2293 * Set up the copy of the h/w RCB
2290 2294 */
2291 2295 srp->hw_rcb.host_ring_addr = srp->desc.cookie.dmac_laddress;
2292 2296 srp->hw_rcb.max_len = (uint16_t)nslots;
2293 2297 srp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED;
2294 2298 srp->hw_rcb.nic_ring_addr = NIC_MEM_SHADOW_SEND_RING(ring, nslots);
2295 2299
2296 2300 /*
2297 2301 * Other one-off initialisation of per-ring data
2298 2302 */
2299 2303 srp->bgep = bgep;
2300 2304 bsp = DMA_VPTR(bgep->status_block);
2301 2305 srp->cons_index_p = SEND_INDEX_P(bsp, ring);
2302 2306 srp->chip_mbx_reg = SEND_RING_HOST_INDEX_REG(ring);
2303 2307 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER,
2304 2308 DDI_INTR_PRI(bgep->intr_pri));
2305 2309 mutex_init(srp->txbuf_lock, NULL, MUTEX_DRIVER,
2306 2310 DDI_INTR_PRI(bgep->intr_pri));
2307 2311 mutex_init(srp->freetxbuf_lock, NULL, MUTEX_DRIVER,
2308 2312 DDI_INTR_PRI(bgep->intr_pri));
2309 2313 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER,
2310 2314 DDI_INTR_PRI(bgep->intr_pri));
2311 2315 if (nslots == 0)
2312 2316 return;
2313 2317
2314 2318 /*
2315 2319 * Allocate the array of s/w Send Buffer Descriptors
2316 2320 */
2317 2321 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP);
2318 2322 txbuf = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (*txbuf), KM_SLEEP);
2319 2323 srp->txbuf_head =
2320 2324 kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (bge_queue_item_t), KM_SLEEP);
2321 2325 srp->pktp = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (send_pkt_t), KM_SLEEP);
2322 2326 srp->sw_sbds = ssbdp;
2323 2327 srp->txbuf = txbuf;
2324 2328 srp->tx_buffers = BGE_SEND_BUF_NUM;
2325 2329 srp->tx_buffers_low = srp->tx_buffers / 4;
2326 2330 if (bgep->chipid.snd_buff_size > BGE_SEND_BUFF_SIZE_DEFAULT)
2327 2331 srp->tx_array_max = BGE_SEND_BUF_ARRAY_JUMBO;
2328 2332 else
2329 2333 srp->tx_array_max = BGE_SEND_BUF_ARRAY;
2330 2334 srp->tx_array = 1;
2331 2335
2332 2336 /*
2333 2337 * Chunk tx desc area
2334 2338 */
2335 2339 desc = srp->desc;
2336 2340 for (slot = 0; slot < nslots; ++ssbdp, ++slot) {
2337 2341 bge_slice_chunk(&ssbdp->desc, &desc, 1,
2338 2342 sizeof (bge_sbd_t));
2339 2343 }
2340 2344 ASSERT(desc.alength == 0);
2341 2345
2342 2346 /*
2343 2347 * Chunk tx buffer area
2344 2348 */
2345 2349 for (split = 0; split < BGE_SPLIT; ++split) {
2346 2350 pbuf = srp->buf[0][split];
2347 2351 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) {
2348 2352 bge_slice_chunk(&txbuf->buf, &pbuf, 1,
2349 2353 bgep->chipid.snd_buff_size);
2350 2354 txbuf++;
2351 2355 }
2352 2356 ASSERT(pbuf.alength == 0);
2353 2357 }
2354 2358 }
2355 2359
2356 2360 /*
2357 2361 * Clean up initialisation done above before the memory is freed
2358 2362 */
2359 2363 static void
2360 2364 bge_fini_send_ring(bge_t *bgep, uint64_t ring)
2361 2365 {
2362 2366 send_ring_t *srp;
2363 2367 uint32_t array;
2364 2368 uint32_t split;
2365 2369 uint32_t nslots;
2366 2370
2367 2371 BGE_TRACE(("bge_fini_send_ring($%p, %d)",
2368 2372 (void *)bgep, ring));
2369 2373
2370 2374 srp = &bgep->send[ring];
2371 2375 mutex_destroy(srp->tc_lock);
2372 2376 mutex_destroy(srp->freetxbuf_lock);
2373 2377 mutex_destroy(srp->txbuf_lock);
2374 2378 mutex_destroy(srp->tx_lock);
2375 2379 nslots = srp->desc.nslots;
2376 2380 if (nslots == 0)
2377 2381 return;
2378 2382
2379 2383 for (array = 1; array < srp->tx_array; ++array)
2380 2384 for (split = 0; split < BGE_SPLIT; ++split)
2381 2385 bge_free_dma_mem(&srp->buf[array][split]);
2382 2386 kmem_free(srp->sw_sbds, nslots*sizeof (*srp->sw_sbds));
2383 2387 kmem_free(srp->txbuf_head, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf_head));
2384 2388 kmem_free(srp->txbuf, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf));
2385 2389 kmem_free(srp->pktp, BGE_SEND_BUF_MAX*sizeof (*srp->pktp));
2386 2390 srp->sw_sbds = NULL;
2387 2391 srp->txbuf_head = NULL;
2388 2392 srp->txbuf = NULL;
2389 2393 srp->pktp = NULL;
2390 2394 }
2391 2395
2392 2396 /*
2393 2397 * Initialise all transmit, receive, and buffer rings.
2394 2398 */
2395 2399 void
2396 2400 bge_init_rings(bge_t *bgep)
2397 2401 {
2398 2402 uint32_t ring;
2399 2403
2400 2404 BGE_TRACE(("bge_init_rings($%p)", (void *)bgep));
2401 2405
2402 2406 /*
2403 2407 * Perform one-off initialisation of each ring ...
2404 2408 */
2405 2409 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring)
2406 2410 bge_init_send_ring(bgep, ring);
2407 2411 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring)
2408 2412 bge_init_recv_ring(bgep, ring);
2409 2413 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring)
2410 2414 bge_init_buff_ring(bgep, ring);
2411 2415 }
2412 2416
2413 2417 /*
2414 2418 * Undo the work of bge_init_rings() above before the memory is freed
2415 2419 */
2416 2420 void
2417 2421 bge_fini_rings(bge_t *bgep)
2418 2422 {
2419 2423 uint32_t ring;
2420 2424
2421 2425 BGE_TRACE(("bge_fini_rings($%p)", (void *)bgep));
2422 2426
2423 2427 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring)
2424 2428 bge_fini_buff_ring(bgep, ring);
2425 2429 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring)
2426 2430 bge_fini_recv_ring(bgep, ring);
2427 2431 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring)
2428 2432 bge_fini_send_ring(bgep, ring);
2429 2433 }
2430 2434
2431 2435 /*
2432 2436 * Called from the bge_m_stop() to free the tx buffers which are
2433 2437 * allocated from the tx process.
2434 2438 */
2435 2439 void
2436 2440 bge_free_txbuf_arrays(send_ring_t *srp)
2437 2441 {
2438 2442 uint32_t array;
2439 2443 uint32_t split;
2440 2444
2441 2445 ASSERT(mutex_owned(srp->tx_lock));
2442 2446
2443 2447 /*
2444 2448 * Free the extra tx buffer DMA area
2445 2449 */
2446 2450 for (array = 1; array < srp->tx_array; ++array)
2447 2451 for (split = 0; split < BGE_SPLIT; ++split)
2448 2452 bge_free_dma_mem(&srp->buf[array][split]);
2449 2453
2450 2454 /*
2451 2455 * Restore initial tx buffer numbers
2452 2456 */
2453 2457 srp->tx_array = 1;
2454 2458 srp->tx_buffers = BGE_SEND_BUF_NUM;
2455 2459 srp->tx_buffers_low = srp->tx_buffers / 4;
2456 2460 srp->tx_flow = 0;
2457 2461 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp));
2458 2462 }
2459 2463
2460 2464 /*
2461 2465 * Called from tx process to allocate more tx buffers
2462 2466 */
2463 2467 bge_queue_item_t *
2464 2468 bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp)
2465 2469 {
2466 2470 bge_queue_t *txbuf_queue;
2467 2471 bge_queue_item_t *txbuf_item_last;
2468 2472 bge_queue_item_t *txbuf_item;
2469 2473 bge_queue_item_t *txbuf_item_rtn;
2470 2474 sw_txbuf_t *txbuf;
2471 2475 dma_area_t area;
2472 2476 size_t txbuffsize;
2473 2477 uint32_t slot;
2474 2478 uint32_t array;
2475 2479 uint32_t split;
2476 2480 uint32_t err;
2477 2481
2478 2482 ASSERT(mutex_owned(srp->tx_lock));
2479 2483
2480 2484 array = srp->tx_array;
2481 2485 if (array >= srp->tx_array_max)
2482 2486 return (NULL);
2483 2487
2484 2488 /*
2485 2489 * Allocate memory & handles for TX buffers
2486 2490 */
2487 2491 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size;
2488 2492 ASSERT((txbuffsize % BGE_SPLIT) == 0);
2489 2493 for (split = 0; split < BGE_SPLIT; ++split) {
2490 2494 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT,
2491 2495 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE,
2492 2496 &srp->buf[array][split]);
2493 2497 if (err != DDI_SUCCESS) {
2494 2498 /* Free the last already allocated OK chunks */
2495 2499 for (slot = 0; slot <= split; ++slot)
2496 2500 bge_free_dma_mem(&srp->buf[array][slot]);
2497 2501 srp->tx_alloc_fail++;
2498 2502 return (NULL);
2499 2503 }
2500 2504 }
2501 2505
2502 2506 /*
2503 2507 * Chunk tx buffer area
2504 2508 */
2505 2509 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM;
2506 2510 for (split = 0; split < BGE_SPLIT; ++split) {
2507 2511 area = srp->buf[array][split];
2508 2512 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) {
2509 2513 bge_slice_chunk(&txbuf->buf, &area, 1,
2510 2514 bgep->chipid.snd_buff_size);
2511 2515 txbuf++;
2512 2516 }
2513 2517 }
2514 2518
2515 2519 /*
2516 2520 * Add above buffers to the tx buffer pop queue
2517 2521 */
2518 2522 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM;
2519 2523 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM;
2520 2524 txbuf_item_last = NULL;
2521 2525 for (slot = 0; slot < BGE_SEND_BUF_NUM; ++slot) {
2522 2526 txbuf_item->item = txbuf;
2523 2527 txbuf_item->next = txbuf_item_last;
2524 2528 txbuf_item_last = txbuf_item;
2525 2529 txbuf++;
2526 2530 txbuf_item++;
2527 2531 }
2528 2532 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM;
2529 2533 txbuf_item_rtn = txbuf_item;
2530 2534 txbuf_item++;
2531 2535 txbuf_queue = srp->txbuf_pop_queue;
2532 2536 mutex_enter(txbuf_queue->lock);
2533 2537 txbuf_item->next = txbuf_queue->head;
2534 2538 txbuf_queue->head = txbuf_item_last;
2535 2539 txbuf_queue->count += BGE_SEND_BUF_NUM - 1;
2536 2540 mutex_exit(txbuf_queue->lock);
2537 2541
2538 2542 srp->tx_array++;
2539 2543 srp->tx_buffers += BGE_SEND_BUF_NUM;
2540 2544 srp->tx_buffers_low = srp->tx_buffers / 4;
2541 2545
2542 2546 return (txbuf_item_rtn);
2543 2547 }
2544 2548
2545 2549 /*
2546 2550 * This function allocates all the transmit and receive buffers
2547 2551 * and descriptors, in four chunks.
2548 2552 */
2549 2553 int
2550 2554 bge_alloc_bufs(bge_t *bgep)
2551 2555 {
2552 2556 dma_area_t area;
2553 2557 size_t rxbuffsize;
2554 2558 size_t txbuffsize;
2555 2559 size_t rxbuffdescsize;
2556 2560 size_t rxdescsize;
2557 2561 size_t txdescsize;
2558 2562 uint32_t ring;
2559 2563 uint32_t rx_rings = bgep->chipid.rx_rings;
2560 2564 uint32_t tx_rings = bgep->chipid.tx_rings;
2561 2565 int split;
2562 2566 int err;
2563 2567
2564 2568 BGE_TRACE(("bge_alloc_bufs($%p)",
2565 2569 (void *)bgep));
2566 2570
2567 2571 rxbuffsize = BGE_STD_SLOTS_USED*bgep->chipid.std_buf_size;
2568 2572 rxbuffsize += bgep->chipid.jumbo_slots*bgep->chipid.recv_jumbo_size;
2569 2573 rxbuffsize += BGE_MINI_SLOTS_USED*BGE_MINI_BUFF_SIZE;
2570 2574
2571 2575 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size;
2572 2576 txbuffsize *= tx_rings;
2573 2577
2574 2578 rxdescsize = rx_rings*bgep->chipid.recv_slots;
2575 2579 rxdescsize *= sizeof (bge_rbd_t);
2576 2580
2577 2581 rxbuffdescsize = BGE_STD_SLOTS_USED;
2578 2582 rxbuffdescsize += bgep->chipid.jumbo_slots;
2579 2583 rxbuffdescsize += BGE_MINI_SLOTS_USED;
2580 2584 rxbuffdescsize *= sizeof (bge_rbd_t);
2581 2585
2582 2586 txdescsize = tx_rings*BGE_SEND_SLOTS_USED;
2583 2587 txdescsize *= sizeof (bge_sbd_t);
2584 2588 txdescsize += sizeof (bge_statistics_t);
2585 2589 txdescsize += sizeof (bge_status_t);
2586 2590 txdescsize += BGE_STATUS_PADDING;
2587 2591
2588 2592 /*
2589 2593 * Enable PCI relaxed ordering only for RX/TX data buffers
2590 2594 */
2591 2595 if (bge_relaxed_ordering)
2592 2596 dma_attr.dma_attr_flags |= DDI_DMA_RELAXED_ORDERING;
2593 2597
2594 2598 /*
2595 2599 * Allocate memory & handles for RX buffers
2596 2600 */
2597 2601 ASSERT((rxbuffsize % BGE_SPLIT) == 0);
2598 2602 for (split = 0; split < BGE_SPLIT; ++split) {
2599 2603 err = bge_alloc_dma_mem(bgep, rxbuffsize/BGE_SPLIT,
2600 2604 &bge_data_accattr, DDI_DMA_READ | BGE_DMA_MODE,
2601 2605 &bgep->rx_buff[split]);
2602 2606 if (err != DDI_SUCCESS)
2603 2607 return (DDI_FAILURE);
2604 2608 }
2605 2609
2606 2610 /*
2607 2611 * Allocate memory & handles for TX buffers
2608 2612 */
2609 2613 ASSERT((txbuffsize % BGE_SPLIT) == 0);
2610 2614 for (split = 0; split < BGE_SPLIT; ++split) {
2611 2615 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT,
2612 2616 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE,
2613 2617 &bgep->tx_buff[split]);
2614 2618 if (err != DDI_SUCCESS)
2615 2619 return (DDI_FAILURE);
2616 2620 }
2617 2621
2618 2622 dma_attr.dma_attr_flags &= ~DDI_DMA_RELAXED_ORDERING;
2619 2623
2620 2624 /*
2621 2625 * Allocate memory & handles for receive return rings
2622 2626 */
2623 2627 ASSERT((rxdescsize % rx_rings) == 0);
2624 2628 for (split = 0; split < rx_rings; ++split) {
2625 2629 err = bge_alloc_dma_mem(bgep, rxdescsize/rx_rings,
2626 2630 &bge_desc_accattr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
2627 2631 &bgep->rx_desc[split]);
2628 2632 if (err != DDI_SUCCESS)
2629 2633 return (DDI_FAILURE);
2630 2634 }
2631 2635
2632 2636 /*
2633 2637 * Allocate memory & handles for buffer (producer) descriptor rings
2634 2638 */
2635 2639 err = bge_alloc_dma_mem(bgep, rxbuffdescsize, &bge_desc_accattr,
2636 2640 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->rx_desc[split]);
2637 2641 if (err != DDI_SUCCESS)
2638 2642 return (DDI_FAILURE);
2639 2643
2640 2644 /*
2641 2645 * Allocate memory & handles for TX descriptor rings,
2642 2646 * status block, and statistics area
2643 2647 */
2644 2648 err = bge_alloc_dma_mem(bgep, txdescsize, &bge_desc_accattr,
2645 2649 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->tx_desc);
2646 2650 if (err != DDI_SUCCESS)
2647 2651 return (DDI_FAILURE);
2648 2652
2649 2653 /*
2650 2654 * Now carve up each of the allocated areas ...
2651 2655 */
2652 2656 for (split = 0; split < BGE_SPLIT; ++split) {
2653 2657 area = bgep->rx_buff[split];
2654 2658 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].buf[split],
2655 2659 &area, BGE_STD_SLOTS_USED/BGE_SPLIT,
2656 2660 bgep->chipid.std_buf_size);
2657 2661 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].buf[split],
2658 2662 &area, bgep->chipid.jumbo_slots/BGE_SPLIT,
2659 2663 bgep->chipid.recv_jumbo_size);
2660 2664 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].buf[split],
2661 2665 &area, BGE_MINI_SLOTS_USED/BGE_SPLIT,
2662 2666 BGE_MINI_BUFF_SIZE);
2663 2667 }
2664 2668
2665 2669 for (split = 0; split < BGE_SPLIT; ++split) {
2666 2670 area = bgep->tx_buff[split];
2667 2671 for (ring = 0; ring < tx_rings; ++ring)
2668 2672 bge_slice_chunk(&bgep->send[ring].buf[0][split],
2669 2673 &area, BGE_SEND_BUF_NUM/BGE_SPLIT,
2670 2674 bgep->chipid.snd_buff_size);
2671 2675 for (; ring < BGE_SEND_RINGS_MAX; ++ring)
2672 2676 bge_slice_chunk(&bgep->send[ring].buf[0][split],
2673 2677 &area, 0, bgep->chipid.snd_buff_size);
2674 2678 }
2675 2679
2676 2680 for (ring = 0; ring < rx_rings; ++ring)
2677 2681 bge_slice_chunk(&bgep->recv[ring].desc, &bgep->rx_desc[ring],
2678 2682 bgep->chipid.recv_slots, sizeof (bge_rbd_t));
2679 2683
2680 2684 area = bgep->rx_desc[rx_rings];
2681 2685 for (; ring < BGE_RECV_RINGS_MAX; ++ring)
2682 2686 bge_slice_chunk(&bgep->recv[ring].desc, &area,
2683 2687 0, sizeof (bge_rbd_t));
2684 2688 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].desc, &area,
2685 2689 BGE_STD_SLOTS_USED, sizeof (bge_rbd_t));
2686 2690 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].desc, &area,
2687 2691 bgep->chipid.jumbo_slots, sizeof (bge_rbd_t));
2688 2692 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].desc, &area,
2689 2693 BGE_MINI_SLOTS_USED, sizeof (bge_rbd_t));
2690 2694 ASSERT(area.alength == 0);
2691 2695
2692 2696 area = bgep->tx_desc;
2693 2697 for (ring = 0; ring < tx_rings; ++ring)
2694 2698 bge_slice_chunk(&bgep->send[ring].desc, &area,
2695 2699 BGE_SEND_SLOTS_USED, sizeof (bge_sbd_t));
2696 2700 for (; ring < BGE_SEND_RINGS_MAX; ++ring)
2697 2701 bge_slice_chunk(&bgep->send[ring].desc, &area,
2698 2702 0, sizeof (bge_sbd_t));
2699 2703 bge_slice_chunk(&bgep->statistics, &area, 1, sizeof (bge_statistics_t));
2700 2704 bge_slice_chunk(&bgep->status_block, &area, 1, sizeof (bge_status_t));
2701 2705 ASSERT(area.alength == BGE_STATUS_PADDING);
2702 2706 DMA_ZERO(bgep->status_block);
2703 2707
2704 2708 return (DDI_SUCCESS);
2705 2709 }
2706 2710
2707 2711 /*
2708 2712 * This routine frees the transmit and receive buffers and descriptors.
2709 2713 * Make sure the chip is stopped before calling it!
2710 2714 */
2711 2715 void
2712 2716 bge_free_bufs(bge_t *bgep)
2713 2717 {
2714 2718 int split;
2715 2719
2716 2720 BGE_TRACE(("bge_free_bufs($%p)",
2717 2721 (void *)bgep));
2718 2722
2719 2723 bge_free_dma_mem(&bgep->tx_desc);
2720 2724 for (split = 0; split < BGE_RECV_RINGS_SPLIT; ++split)
2721 2725 bge_free_dma_mem(&bgep->rx_desc[split]);
2722 2726 for (split = 0; split < BGE_SPLIT; ++split)
2723 2727 bge_free_dma_mem(&bgep->tx_buff[split]);
2724 2728 for (split = 0; split < BGE_SPLIT; ++split)
2725 2729 bge_free_dma_mem(&bgep->rx_buff[split]);
2726 2730 }
2727 2731
2728 2732 /*
2729 2733 * Determine (initial) MAC address ("BIA") to use for this interface
2730 2734 */
2731 2735
2732 2736 static void
2733 2737 bge_find_mac_address(bge_t *bgep, chip_id_t *cidp)
2734 2738 {
2735 2739 struct ether_addr sysaddr;
2736 2740 char propbuf[8]; /* "true" or "false", plus NUL */
2737 2741 uchar_t *bytes;
2738 2742 int *ints;
2739 2743 uint_t nelts;
2740 2744 int err;
2741 2745
2742 2746 BGE_TRACE(("bge_find_mac_address($%p)",
2743 2747 (void *)bgep));
2744 2748
2745 2749 BGE_DEBUG(("bge_find_mac_address: hw_mac_addr %012llx, => %s (%sset)",
2746 2750 cidp->hw_mac_addr,
2747 2751 ether_sprintf((void *)cidp->vendor_addr.addr),
2748 2752 cidp->vendor_addr.set ? "" : "not "));
2749 2753
2750 2754 /*
2751 2755 * The "vendor's factory-set address" may already have
2752 2756 * been extracted from the chip, but if the property
2753 2757 * "local-mac-address" is set we use that instead. It
2754 2758 * will normally be set by OBP, but it could also be
2755 2759 * specified in a .conf file(!)
2756 2760 *
2757 2761 * There doesn't seem to be a way to define byte-array
2758 2762 * properties in a .conf, so we check whether it looks
2759 2763 * like an array of 6 ints instead.
2760 2764 *
2761 2765 * Then, we check whether it looks like an array of 6
2762 2766 * bytes (which it should, if OBP set it). If we can't
2763 2767 * make sense of it either way, we'll ignore it.
2764 2768 */
2765 2769 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2766 2770 DDI_PROP_DONTPASS, localmac_propname, &ints, &nelts);
2767 2771 if (err == DDI_PROP_SUCCESS) {
2768 2772 if (nelts == ETHERADDRL) {
2769 2773 while (nelts--)
2770 2774 cidp->vendor_addr.addr[nelts] = ints[nelts];
2771 2775 cidp->vendor_addr.set = B_TRUE;
2772 2776 }
2773 2777 ddi_prop_free(ints);
2774 2778 }
2775 2779
2776 2780 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo,
2777 2781 DDI_PROP_DONTPASS, localmac_propname, &bytes, &nelts);
2778 2782 if (err == DDI_PROP_SUCCESS) {
2779 2783 if (nelts == ETHERADDRL) {
2780 2784 while (nelts--)
2781 2785 cidp->vendor_addr.addr[nelts] = bytes[nelts];
2782 2786 cidp->vendor_addr.set = B_TRUE;
2783 2787 }
2784 2788 ddi_prop_free(bytes);
2785 2789 }
2786 2790
2787 2791 BGE_DEBUG(("bge_find_mac_address: +local %s (%sset)",
2788 2792 ether_sprintf((void *)cidp->vendor_addr.addr),
2789 2793 cidp->vendor_addr.set ? "" : "not "));
2790 2794
2791 2795 /*
2792 2796 * Look up the OBP property "local-mac-address?". Note that even
2793 2797 * though its value is a string (which should be "true" or "false"),
2794 2798 * it can't be decoded by ddi_prop_lookup_string(9F). So, we zero
2795 2799 * the buffer first and then fetch the property as an untyped array;
2796 2800 * this may or may not include a final NUL, but since there will
2797 2801 * always be one left at the end of the buffer we can now treat it
2798 2802 * as a string anyway.
2799 2803 */
2800 2804 nelts = sizeof (propbuf);
2801 2805 bzero(propbuf, nelts--);
2802 2806 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, bgep->devinfo,
2803 2807 DDI_PROP_CANSLEEP, localmac_boolname, propbuf, (int *)&nelts);
2804 2808
2805 2809 /*
2806 2810 * Now, if the address still isn't set from the hardware (SEEPROM)
2807 2811 * or the OBP or .conf property, OR if the user has foolishly set
2808 2812 * 'local-mac-address? = false', use "the system address" instead
2809 2813 * (but only if it's non-null i.e. has been set from the IDPROM).
2810 2814 */
2811 2815 if (cidp->vendor_addr.set == B_FALSE || strcmp(propbuf, "false") == 0)
2812 2816 if (localetheraddr(NULL, &sysaddr) != 0) {
2813 2817 ethaddr_copy(&sysaddr, cidp->vendor_addr.addr);
2814 2818 cidp->vendor_addr.set = B_TRUE;
2815 2819 }
2816 2820
2817 2821 BGE_DEBUG(("bge_find_mac_address: +system %s (%sset)",
2818 2822 ether_sprintf((void *)cidp->vendor_addr.addr),
2819 2823 cidp->vendor_addr.set ? "" : "not "));
2820 2824
2821 2825 /*
2822 2826 * Finally(!), if there's a valid "mac-address" property (created
2823 2827 * if we netbooted from this interface), we must use this instead
2824 2828 * of any of the above to ensure that the NFS/install server doesn't
2825 2829 * get confused by the address changing as Solaris takes over!
2826 2830 */
2827 2831 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo,
2828 2832 DDI_PROP_DONTPASS, macaddr_propname, &bytes, &nelts);
2829 2833 if (err == DDI_PROP_SUCCESS) {
2830 2834 if (nelts == ETHERADDRL) {
2831 2835 while (nelts--)
2832 2836 cidp->vendor_addr.addr[nelts] = bytes[nelts];
2833 2837 cidp->vendor_addr.set = B_TRUE;
2834 2838 }
2835 2839 ddi_prop_free(bytes);
2836 2840 }
2837 2841
2838 2842 BGE_DEBUG(("bge_find_mac_address: =final %s (%sset)",
2839 2843 ether_sprintf((void *)cidp->vendor_addr.addr),
2840 2844 cidp->vendor_addr.set ? "" : "not "));
2841 2845 }
2842 2846
2843 2847
2844 2848 /*ARGSUSED*/
2845 2849 int
2846 2850 bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle)
2847 2851 {
2848 2852 ddi_fm_error_t de;
2849 2853
2850 2854 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
2851 2855 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
2852 2856 return (de.fme_status);
2853 2857 }
2854 2858
2855 2859 /*ARGSUSED*/
2856 2860 int
2857 2861 bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle)
2858 2862 {
2859 2863 ddi_fm_error_t de;
2860 2864
2861 2865 ASSERT(bgep->progress & PROGRESS_BUFS);
2862 2866 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
2863 2867 return (de.fme_status);
2864 2868 }
2865 2869
2866 2870 /*
2867 2871 * The IO fault service error handling callback function
2868 2872 */
2869 2873 /*ARGSUSED*/
2870 2874 static int
2871 2875 bge_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
2872 2876 {
2873 2877 /*
2874 2878 * as the driver can always deal with an error in any dma or
2875 2879 * access handle, we can just return the fme_status value.
2876 2880 */
2877 2881 pci_ereport_post(dip, err, NULL);
2878 2882 return (err->fme_status);
2879 2883 }
2880 2884
2881 2885 static void
2882 2886 bge_fm_init(bge_t *bgep)
2883 2887 {
2884 2888 ddi_iblock_cookie_t iblk;
2885 2889
2886 2890 /* Only register with IO Fault Services if we have some capability */
2887 2891 if (bgep->fm_capabilities) {
2888 2892 bge_reg_accattr.devacc_attr_access = DDI_FLAGERR_ACC;
2889 2893 dma_attr.dma_attr_flags = DDI_DMA_FLAGERR;
2890 2894
2891 2895 /* Register capabilities with IO Fault Services */
2892 2896 ddi_fm_init(bgep->devinfo, &bgep->fm_capabilities, &iblk);
2893 2897
2894 2898 /*
2895 2899 * Initialize pci ereport capabilities if ereport capable
2896 2900 */
2897 2901 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) ||
2898 2902 DDI_FM_ERRCB_CAP(bgep->fm_capabilities))
2899 2903 pci_ereport_setup(bgep->devinfo);
2900 2904
2901 2905 /*
2902 2906 * Register error callback if error callback capable
2903 2907 */
2904 2908 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities))
2905 2909 ddi_fm_handler_register(bgep->devinfo,
2906 2910 bge_fm_error_cb, (void*) bgep);
2907 2911 } else {
2908 2912 /*
2909 2913 * These fields have to be cleared of FMA if there are no
2910 2914 * FMA capabilities at runtime.
2911 2915 */
2912 2916 bge_reg_accattr.devacc_attr_access = DDI_DEFAULT_ACC;
2913 2917 dma_attr.dma_attr_flags = 0;
2914 2918 }
2915 2919 }
2916 2920
2917 2921 static void
2918 2922 bge_fm_fini(bge_t *bgep)
2919 2923 {
2920 2924 /* Only unregister FMA capabilities if we registered some */
2921 2925 if (bgep->fm_capabilities) {
2922 2926
2923 2927 /*
2924 2928 * Release any resources allocated by pci_ereport_setup()
2925 2929 */
2926 2930 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) ||
2927 2931 DDI_FM_ERRCB_CAP(bgep->fm_capabilities))
2928 2932 pci_ereport_teardown(bgep->devinfo);
2929 2933
2930 2934 /*
2931 2935 * Un-register error callback if error callback capable
2932 2936 */
2933 2937 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities))
2934 2938 ddi_fm_handler_unregister(bgep->devinfo);
2935 2939
2936 2940 /* Unregister from IO Fault Services */
2937 2941 ddi_fm_fini(bgep->devinfo);
2938 2942 }
2939 2943 }
2940 2944
2941 2945 static void
2942 2946 #ifdef BGE_IPMI_ASF
2943 2947 bge_unattach(bge_t *bgep, uint_t asf_mode)
2944 2948 #else
2945 2949 bge_unattach(bge_t *bgep)
2946 2950 #endif
2947 2951 {
2948 2952 BGE_TRACE(("bge_unattach($%p)",
2949 2953 (void *)bgep));
2950 2954
2951 2955 /*
2952 2956 * Flag that no more activity may be initiated
2953 2957 */
2954 2958 bgep->progress &= ~PROGRESS_READY;
2955 2959
2956 2960 /*
2957 2961 * Quiesce the PHY and MAC (leave it reset but still powered).
2958 2962 * Clean up and free all BGE data structures
2959 2963 */
2960 2964 if (bgep->periodic_id != NULL) {
2961 2965 ddi_periodic_delete(bgep->periodic_id);
2962 2966 bgep->periodic_id = NULL;
2963 2967 }
2964 2968 if (bgep->progress & PROGRESS_KSTATS)
2965 2969 bge_fini_kstats(bgep);
2966 2970 if (bgep->progress & PROGRESS_PHY)
2967 2971 bge_phys_reset(bgep);
2968 2972 if (bgep->progress & PROGRESS_HWINT) {
2969 2973 mutex_enter(bgep->genlock);
2970 2974 #ifdef BGE_IPMI_ASF
2971 2975 if (bge_chip_reset(bgep, B_FALSE, asf_mode) != DDI_SUCCESS)
2972 2976 #else
2973 2977 if (bge_chip_reset(bgep, B_FALSE) != DDI_SUCCESS)
2974 2978 #endif
2975 2979 ddi_fm_service_impact(bgep->devinfo,
2976 2980 DDI_SERVICE_UNAFFECTED);
2977 2981 #ifdef BGE_IPMI_ASF
2978 2982 if (bgep->asf_enabled) {
2979 2983 /*
2980 2984 * This register has been overlaid. We restore its
2981 2985 * initial value here.
2982 2986 */
2983 2987 bge_nic_put32(bgep, BGE_NIC_DATA_SIG_ADDR,
2984 2988 BGE_NIC_DATA_SIG);
2985 2989 }
2986 2990 #endif
2987 2991 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
2988 2992 ddi_fm_service_impact(bgep->devinfo,
2989 2993 DDI_SERVICE_UNAFFECTED);
2990 2994 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2991 2995 ddi_fm_service_impact(bgep->devinfo,
2992 2996 DDI_SERVICE_UNAFFECTED);
2993 2997 mutex_exit(bgep->genlock);
2994 2998 }
2995 2999 if (bgep->progress & PROGRESS_INTR) {
2996 3000 bge_intr_disable(bgep);
2997 3001 bge_fini_rings(bgep);
2998 3002 }
2999 3003 if (bgep->progress & PROGRESS_HWINT) {
3000 3004 bge_rem_intrs(bgep);
3001 3005 rw_destroy(bgep->errlock);
3002 3006 mutex_destroy(bgep->softintrlock);
3003 3007 mutex_destroy(bgep->genlock);
3004 3008 }
3005 3009 if (bgep->progress & PROGRESS_FACTOTUM)
3006 3010 ddi_remove_softintr(bgep->factotum_id);
3007 3011 if (bgep->progress & PROGRESS_RESCHED)
3008 3012 ddi_remove_softintr(bgep->drain_id);
3009 3013 if (bgep->progress & PROGRESS_BUFS)
3010 3014 bge_free_bufs(bgep);
3011 3015 if (bgep->progress & PROGRESS_REGS)
3012 3016 ddi_regs_map_free(&bgep->io_handle);
3013 3017 if (bgep->progress & PROGRESS_CFG)
3014 3018 pci_config_teardown(&bgep->cfg_handle);
3015 3019
3016 3020 bge_fm_fini(bgep);
3017 3021
3018 3022 ddi_remove_minor_node(bgep->devinfo, NULL);
3019 3023 kmem_free(bgep->pstats, sizeof (bge_statistics_reg_t));
3020 3024 kmem_free(bgep, sizeof (*bgep));
3021 3025 }
3022 3026
3023 3027 static int
3024 3028 bge_resume(dev_info_t *devinfo)
3025 3029 {
3026 3030 bge_t *bgep; /* Our private data */
3027 3031 chip_id_t *cidp;
3028 3032 chip_id_t chipid;
3029 3033
3030 3034 bgep = ddi_get_driver_private(devinfo);
3031 3035 if (bgep == NULL)
3032 3036 return (DDI_FAILURE);
3033 3037
3034 3038 /*
3035 3039 * Refuse to resume if the data structures aren't consistent
3036 3040 */
3037 3041 if (bgep->devinfo != devinfo)
3038 3042 return (DDI_FAILURE);
3039 3043
3040 3044 #ifdef BGE_IPMI_ASF
3041 3045 /*
3042 3046 * Power management hasn't been supported in BGE now. If you
3043 3047 * want to implement it, please add the ASF/IPMI related
3044 3048 * code here.
3045 3049 */
3046 3050
3047 3051 #endif
3048 3052
3049 3053 /*
3050 3054 * Read chip ID & set up config space command register(s)
3051 3055 * Refuse to resume if the chip has changed its identity!
3052 3056 */
3053 3057 cidp = &bgep->chipid;
3054 3058 mutex_enter(bgep->genlock);
3055 3059 bge_chip_cfg_init(bgep, &chipid, B_FALSE);
3056 3060 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
3057 3061 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3058 3062 mutex_exit(bgep->genlock);
3059 3063 return (DDI_FAILURE);
3060 3064 }
3061 3065 mutex_exit(bgep->genlock);
3062 3066 if (chipid.vendor != cidp->vendor)
3063 3067 return (DDI_FAILURE);
3064 3068 if (chipid.device != cidp->device)
3065 3069 return (DDI_FAILURE);
3066 3070 if (chipid.revision != cidp->revision)
3067 3071 return (DDI_FAILURE);
3068 3072 if (chipid.asic_rev != cidp->asic_rev)
3069 3073 return (DDI_FAILURE);
3070 3074
3071 3075 /*
3072 3076 * All OK, reinitialise h/w & kick off GLD scheduling
3073 3077 */
3074 3078 mutex_enter(bgep->genlock);
3075 3079 if (bge_restart(bgep, B_TRUE) != DDI_SUCCESS) {
3076 3080 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
3077 3081 (void) bge_check_acc_handle(bgep, bgep->io_handle);
3078 3082 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3079 3083 mutex_exit(bgep->genlock);
3080 3084 return (DDI_FAILURE);
3081 3085 }
3082 3086 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
3083 3087 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3084 3088 mutex_exit(bgep->genlock);
3085 3089 return (DDI_FAILURE);
3086 3090 }
3087 3091 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
3088 3092 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3089 3093 mutex_exit(bgep->genlock);
3090 3094 return (DDI_FAILURE);
3091 3095 }
3092 3096 mutex_exit(bgep->genlock);
3093 3097 return (DDI_SUCCESS);
3094 3098 }
3095 3099
3096 3100 /*
3097 3101 * attach(9E) -- Attach a device to the system
3098 3102 *
3099 3103 * Called once for each board successfully probed.
3100 3104 */
3101 3105 static int
3102 3106 bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
3103 3107 {
3104 3108 bge_t *bgep; /* Our private data */
3105 3109 mac_register_t *macp;
3106 3110 chip_id_t *cidp;
3107 3111 caddr_t regs;
3108 3112 int instance;
3109 3113 int err;
3110 3114 int intr_types;
3111 3115 #ifdef BGE_IPMI_ASF
3112 3116 uint32_t mhcrValue;
3113 3117 #ifdef __sparc
3114 3118 uint16_t value16;
3115 3119 #endif
3116 3120 #ifdef BGE_NETCONSOLE
3117 3121 int retval;
3118 3122 #endif
3119 3123 #endif
3120 3124
3121 3125 instance = ddi_get_instance(devinfo);
3122 3126
3123 3127 BGE_GTRACE(("bge_attach($%p, %d) instance %d",
3124 3128 (void *)devinfo, cmd, instance));
3125 3129 BGE_BRKPT(NULL, "bge_attach");
3126 3130
3127 3131 switch (cmd) {
3128 3132 default:
3129 3133 return (DDI_FAILURE);
3130 3134
3131 3135 case DDI_RESUME:
3132 3136 return (bge_resume(devinfo));
3133 3137
3134 3138 case DDI_ATTACH:
3135 3139 break;
3136 3140 }
3137 3141
3138 3142 bgep = kmem_zalloc(sizeof (*bgep), KM_SLEEP);
3139 3143 bgep->pstats = kmem_zalloc(sizeof (bge_statistics_reg_t), KM_SLEEP);
3140 3144 ddi_set_driver_private(devinfo, bgep);
3141 3145 bgep->bge_guard = BGE_GUARD;
3142 3146 bgep->devinfo = devinfo;
3143 3147 bgep->param_drain_max = 64;
3144 3148 bgep->param_msi_cnt = 0;
3145 3149 bgep->param_loop_mode = 0;
3146 3150
3147 3151 /*
3148 3152 * Initialize more fields in BGE private data
3149 3153 */
3150 3154 bgep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3151 3155 DDI_PROP_DONTPASS, debug_propname, bge_debug);
3152 3156 (void) snprintf(bgep->ifname, sizeof (bgep->ifname), "%s%d",
3153 3157 BGE_DRIVER_NAME, instance);
3154 3158
3155 3159 /*
3156 3160 * Initialize for fma support
3157 3161 */
3158 3162 bgep->fm_capabilities = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3159 3163 DDI_PROP_DONTPASS, fm_cap,
3160 3164 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
3161 3165 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
3162 3166 BGE_DEBUG(("bgep->fm_capabilities = %d", bgep->fm_capabilities));
3163 3167 bge_fm_init(bgep);
3164 3168
3165 3169 /*
3166 3170 * Look up the IOMMU's page size for DVMA mappings (must be
3167 3171 * a power of 2) and convert to a mask. This can be used to
3168 3172 * determine whether a message buffer crosses a page boundary.
3169 3173 * Note: in 2s complement binary notation, if X is a power of
3170 3174 * 2, then -X has the representation "11...1100...00".
3171 3175 */
3172 3176 bgep->pagemask = dvma_pagesize(devinfo);
3173 3177 ASSERT(ddi_ffs(bgep->pagemask) == ddi_fls(bgep->pagemask));
3174 3178 bgep->pagemask = -bgep->pagemask;
3175 3179
3176 3180 /*
3177 3181 * Map config space registers
3178 3182 * Read chip ID & set up config space command register(s)
3179 3183 *
3180 3184 * Note: this leaves the chip accessible by Memory Space
3181 3185 * accesses, but with interrupts and Bus Mastering off.
3182 3186 * This should ensure that nothing untoward will happen
3183 3187 * if it has been left active by the (net-)bootloader.
3184 3188 * We'll re-enable Bus Mastering once we've reset the chip,
3185 3189 * and allow interrupts only when everything else is set up.
3186 3190 */
3187 3191 err = pci_config_setup(devinfo, &bgep->cfg_handle);
3188 3192 #ifdef BGE_IPMI_ASF
3189 3193 #ifdef __sparc
3190 3194 /*
3191 3195 * We need to determine the type of chipset for accessing some configure
3192 3196 * registers. (This information will be used by bge_ind_put32,
3193 3197 * bge_ind_get32 and bge_nic_read32)
3194 3198 */
3195 3199 bgep->chipid.device = pci_config_get16(bgep->cfg_handle,
3196 3200 PCI_CONF_DEVID);
3197 3201 value16 = pci_config_get16(bgep->cfg_handle, PCI_CONF_COMM);
3198 3202 value16 = value16 | (PCI_COMM_MAE | PCI_COMM_ME);
3199 3203 pci_config_put16(bgep->cfg_handle, PCI_CONF_COMM, value16);
3200 3204 mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS |
3201 3205 MHCR_ENABLE_TAGGED_STATUS_MODE |
3202 3206 MHCR_MASK_INTERRUPT_MODE |
3203 3207 MHCR_MASK_PCI_INT_OUTPUT |
|
↓ open down ↓ |
3168 lines elided |
↑ open up ↑ |
3204 3208 MHCR_CLEAR_INTERRUPT_INTA |
3205 3209 MHCR_ENABLE_ENDIAN_WORD_SWAP |
3206 3210 MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3207 3211 /*
3208 3212 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
3209 3213 * has been set in PCI_CONF_COMM already, we need to write the
3210 3214 * byte-swapped value to it. So we just write zero first for simplicity.
3211 3215 */
3212 3216 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3213 3217 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3218 +#else
3219 + mhcrValue = MHCR_ENABLE_INDIRECT_ACCESS |
3220 + MHCR_ENABLE_TAGGED_STATUS_MODE |
3221 + MHCR_MASK_INTERRUPT_MODE |
3222 + MHCR_MASK_PCI_INT_OUTPUT |
3223 + MHCR_CLEAR_INTERRUPT_INTA;
3224 +#endif
3214 3225 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcrValue);
3215 3226 bge_ind_put32(bgep, MEMORY_ARBITER_MODE_REG,
3216 3227 bge_ind_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3217 3228 MEMORY_ARBITER_ENABLE);
3218 -#else
3219 - mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR);
3220 -#endif
3221 3229 if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) {
3222 3230 bgep->asf_wordswapped = B_TRUE;
3223 3231 } else {
3224 3232 bgep->asf_wordswapped = B_FALSE;
3225 3233 }
3226 3234 bge_asf_get_config(bgep);
3227 3235 #endif
3228 3236 if (err != DDI_SUCCESS) {
3229 3237 bge_problem(bgep, "pci_config_setup() failed");
3230 3238 goto attach_fail;
3231 3239 }
3232 3240 bgep->progress |= PROGRESS_CFG;
3233 3241 cidp = &bgep->chipid;
3234 3242 bzero(cidp, sizeof (*cidp));
3235 3243 bge_chip_cfg_init(bgep, cidp, B_FALSE);
3236 3244 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
3237 3245 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3238 3246 goto attach_fail;
3239 3247 }
3240 3248
3241 3249 #ifdef BGE_IPMI_ASF
3242 3250 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
3243 3251 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
3244 3252 bgep->asf_newhandshake = B_TRUE;
3245 3253 } else {
3246 3254 bgep->asf_newhandshake = B_FALSE;
3247 3255 }
3248 3256 #endif
3249 3257
3250 3258 /*
3251 3259 * Update those parts of the chip ID derived from volatile
3252 3260 * registers with the values seen by OBP (in case the chip
3253 3261 * has been reset externally and therefore lost them).
3254 3262 */
3255 3263 cidp->subven = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3256 3264 DDI_PROP_DONTPASS, subven_propname, cidp->subven);
3257 3265 cidp->subdev = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3258 3266 DDI_PROP_DONTPASS, subdev_propname, cidp->subdev);
3259 3267 cidp->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3260 3268 DDI_PROP_DONTPASS, clsize_propname, cidp->clsize);
3261 3269 cidp->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3262 3270 DDI_PROP_DONTPASS, latency_propname, cidp->latency);
3263 3271 cidp->rx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3264 3272 DDI_PROP_DONTPASS, rxrings_propname, cidp->rx_rings);
3265 3273 cidp->tx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3266 3274 DDI_PROP_DONTPASS, txrings_propname, cidp->tx_rings);
3267 3275
3268 3276 cidp->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo,
3269 3277 DDI_PROP_DONTPASS, default_mtu, BGE_DEFAULT_MTU);
3270 3278 if ((cidp->default_mtu < BGE_DEFAULT_MTU) ||
3271 3279 (cidp->default_mtu > BGE_MAXIMUM_MTU)) {
3272 3280 cidp->default_mtu = BGE_DEFAULT_MTU;
3273 3281 }
3274 3282
3275 3283 /*
3276 3284 * Map operating registers
3277 3285 */
3278 3286 err = ddi_regs_map_setup(devinfo, BGE_PCI_OPREGS_RNUMBER,
3279 3287 ®s, 0, 0, &bge_reg_accattr, &bgep->io_handle);
3280 3288 if (err != DDI_SUCCESS) {
3281 3289 bge_problem(bgep, "ddi_regs_map_setup() failed");
3282 3290 goto attach_fail;
3283 3291 }
3284 3292 bgep->io_regs = regs;
3285 3293 bgep->progress |= PROGRESS_REGS;
3286 3294
3287 3295 /*
3288 3296 * Characterise the device, so we know its requirements.
3289 3297 * Then allocate the appropriate TX and RX descriptors & buffers.
3290 3298 */
3291 3299 if (bge_chip_id_init(bgep) == EIO) {
3292 3300 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3293 3301 goto attach_fail;
3294 3302 }
3295 3303
3296 3304 err = bge_alloc_bufs(bgep);
3297 3305 if (err != DDI_SUCCESS) {
3298 3306 bge_problem(bgep, "DMA buffer allocation failed");
3299 3307 goto attach_fail;
3300 3308 }
3301 3309 bgep->progress |= PROGRESS_BUFS;
3302 3310
3303 3311 /*
3304 3312 * Add the softint handlers:
3305 3313 *
3306 3314 * Both of these handlers are used to avoid restrictions on the
3307 3315 * context and/or mutexes required for some operations. In
3308 3316 * particular, the hardware interrupt handler and its subfunctions
3309 3317 * can detect a number of conditions that we don't want to handle
3310 3318 * in that context or with that set of mutexes held. So, these
3311 3319 * softints are triggered instead:
3312 3320 *
3313 3321 * the <resched> softint is triggered if we have previously
3314 3322 * had to refuse to send a packet because of resource shortage
3315 3323 * (we've run out of transmit buffers), but the send completion
3316 3324 * interrupt handler has now detected that more buffers have
3317 3325 * become available.
3318 3326 *
3319 3327 * the <factotum> is triggered if the h/w interrupt handler
3320 3328 * sees the <link state changed> or <error> bits in the status
3321 3329 * block. It's also triggered periodically to poll the link
3322 3330 * state, just in case we aren't getting link status change
3323 3331 * interrupts ...
3324 3332 */
3325 3333 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->drain_id,
3326 3334 NULL, NULL, bge_send_drain, (caddr_t)bgep);
3327 3335 if (err != DDI_SUCCESS) {
3328 3336 bge_problem(bgep, "ddi_add_softintr() failed");
3329 3337 goto attach_fail;
3330 3338 }
3331 3339 bgep->progress |= PROGRESS_RESCHED;
3332 3340 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->factotum_id,
3333 3341 NULL, NULL, bge_chip_factotum, (caddr_t)bgep);
3334 3342 if (err != DDI_SUCCESS) {
3335 3343 bge_problem(bgep, "ddi_add_softintr() failed");
3336 3344 goto attach_fail;
3337 3345 }
3338 3346 bgep->progress |= PROGRESS_FACTOTUM;
3339 3347
3340 3348 /* Get supported interrupt types */
3341 3349 if (ddi_intr_get_supported_types(devinfo, &intr_types) != DDI_SUCCESS) {
3342 3350 bge_error(bgep, "ddi_intr_get_supported_types failed\n");
3343 3351
3344 3352 goto attach_fail;
3345 3353 }
3346 3354
3347 3355 BGE_DEBUG(("%s: ddi_intr_get_supported_types() returned: %x",
3348 3356 bgep->ifname, intr_types));
3349 3357
3350 3358 if ((intr_types & DDI_INTR_TYPE_MSI) && bgep->chipid.msi_enabled) {
3351 3359 if (bge_add_intrs(bgep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) {
3352 3360 bge_error(bgep, "MSI registration failed, "
3353 3361 "trying FIXED interrupt type\n");
3354 3362 } else {
3355 3363 BGE_DEBUG(("%s: Using MSI interrupt type",
3356 3364 bgep->ifname));
3357 3365 bgep->intr_type = DDI_INTR_TYPE_MSI;
3358 3366 bgep->progress |= PROGRESS_HWINT;
3359 3367 }
3360 3368 }
3361 3369
3362 3370 if (!(bgep->progress & PROGRESS_HWINT) &&
3363 3371 (intr_types & DDI_INTR_TYPE_FIXED)) {
3364 3372 if (bge_add_intrs(bgep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) {
3365 3373 bge_error(bgep, "FIXED interrupt "
3366 3374 "registration failed\n");
3367 3375 goto attach_fail;
3368 3376 }
3369 3377
3370 3378 BGE_DEBUG(("%s: Using FIXED interrupt type", bgep->ifname));
3371 3379
3372 3380 bgep->intr_type = DDI_INTR_TYPE_FIXED;
3373 3381 bgep->progress |= PROGRESS_HWINT;
3374 3382 }
3375 3383
3376 3384 if (!(bgep->progress & PROGRESS_HWINT)) {
3377 3385 bge_error(bgep, "No interrupts registered\n");
3378 3386 goto attach_fail;
3379 3387 }
3380 3388
3381 3389 /*
3382 3390 * Note that interrupts are not enabled yet as
3383 3391 * mutex locks are not initialized. Initialize mutex locks.
3384 3392 */
3385 3393 mutex_init(bgep->genlock, NULL, MUTEX_DRIVER,
3386 3394 DDI_INTR_PRI(bgep->intr_pri));
3387 3395 mutex_init(bgep->softintrlock, NULL, MUTEX_DRIVER,
3388 3396 DDI_INTR_PRI(bgep->intr_pri));
3389 3397 rw_init(bgep->errlock, NULL, RW_DRIVER,
3390 3398 DDI_INTR_PRI(bgep->intr_pri));
3391 3399
3392 3400 /*
3393 3401 * Initialize rings.
3394 3402 */
3395 3403 bge_init_rings(bgep);
3396 3404
3397 3405 /*
3398 3406 * Now that mutex locks are initialized, enable interrupts.
3399 3407 */
3400 3408 bge_intr_enable(bgep);
3401 3409 bgep->progress |= PROGRESS_INTR;
3402 3410
3403 3411 /*
3404 3412 * Initialise link state variables
3405 3413 * Stop, reset & reinitialise the chip.
3406 3414 * Initialise the (internal) PHY.
3407 3415 */
3408 3416 bgep->link_state = LINK_STATE_UNKNOWN;
3409 3417
3410 3418 mutex_enter(bgep->genlock);
3411 3419
3412 3420 /*
3413 3421 * Reset chip & rings to initial state; also reset address
3414 3422 * filtering, promiscuity, loopback mode.
3415 3423 */
3416 3424 #ifdef BGE_IPMI_ASF
3417 3425 #ifdef BGE_NETCONSOLE
3418 3426 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) {
3419 3427 #else
3420 3428 if (bge_reset(bgep, ASF_MODE_SHUTDOWN) != DDI_SUCCESS) {
3421 3429 #endif
3422 3430 #else
3423 3431 if (bge_reset(bgep) != DDI_SUCCESS) {
3424 3432 #endif
3425 3433 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
3426 3434 (void) bge_check_acc_handle(bgep, bgep->io_handle);
3427 3435 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3428 3436 mutex_exit(bgep->genlock);
3429 3437 goto attach_fail;
3430 3438 }
3431 3439
3432 3440 #ifdef BGE_IPMI_ASF
3433 3441 if (bgep->asf_enabled) {
3434 3442 bgep->asf_status = ASF_STAT_RUN_INIT;
3435 3443 }
3436 3444 #endif
3437 3445
3438 3446 bzero(bgep->mcast_hash, sizeof (bgep->mcast_hash));
3439 3447 bzero(bgep->mcast_refs, sizeof (bgep->mcast_refs));
3440 3448 bgep->promisc = B_FALSE;
3441 3449 bgep->param_loop_mode = BGE_LOOP_NONE;
3442 3450 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) {
3443 3451 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3444 3452 mutex_exit(bgep->genlock);
3445 3453 goto attach_fail;
3446 3454 }
3447 3455 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
3448 3456 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3449 3457 mutex_exit(bgep->genlock);
3450 3458 goto attach_fail;
3451 3459 }
3452 3460
3453 3461 mutex_exit(bgep->genlock);
3454 3462
3455 3463 if (bge_phys_init(bgep) == EIO) {
3456 3464 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST);
3457 3465 goto attach_fail;
3458 3466 }
3459 3467 bgep->progress |= PROGRESS_PHY;
3460 3468
3461 3469 /*
3462 3470 * initialize NDD-tweakable parameters
3463 3471 */
3464 3472 if (bge_nd_init(bgep)) {
3465 3473 bge_problem(bgep, "bge_nd_init() failed");
3466 3474 goto attach_fail;
3467 3475 }
3468 3476 bgep->progress |= PROGRESS_NDD;
3469 3477
3470 3478 /*
3471 3479 * Create & initialise named kstats
3472 3480 */
3473 3481 bge_init_kstats(bgep, instance);
3474 3482 bgep->progress |= PROGRESS_KSTATS;
3475 3483
3476 3484 /*
3477 3485 * Determine whether to override the chip's own MAC address
3478 3486 */
3479 3487 bge_find_mac_address(bgep, cidp);
3480 3488
3481 3489 bgep->unicst_addr_total = MAC_ADDRESS_REGS_MAX;
3482 3490 bgep->unicst_addr_avail = MAC_ADDRESS_REGS_MAX;
3483 3491
3484 3492 if ((macp = mac_alloc(MAC_VERSION)) == NULL)
3485 3493 goto attach_fail;
3486 3494 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
3487 3495 macp->m_driver = bgep;
3488 3496 macp->m_dip = devinfo;
3489 3497 macp->m_src_addr = cidp->vendor_addr.addr;
3490 3498 macp->m_callbacks = &bge_m_callbacks;
3491 3499 macp->m_min_sdu = 0;
3492 3500 macp->m_max_sdu = cidp->ethmax_size - sizeof (struct ether_header);
3493 3501 macp->m_margin = VLAN_TAGSZ;
3494 3502 macp->m_priv_props = bge_priv_prop;
3495 3503 macp->m_v12n = MAC_VIRT_LEVEL1;
3496 3504
3497 3505 /*
3498 3506 * Finally, we're ready to register ourselves with the MAC layer
3499 3507 * interface; if this succeeds, we're all ready to start()
3500 3508 */
3501 3509 err = mac_register(macp, &bgep->mh);
3502 3510 mac_free(macp);
3503 3511 if (err != 0)
3504 3512 goto attach_fail;
3505 3513
3506 3514 mac_link_update(bgep->mh, LINK_STATE_UNKNOWN);
3507 3515
3508 3516 /*
3509 3517 * Register a periodical handler.
3510 3518 * bge_chip_cyclic() is invoked in kernel context.
3511 3519 */
3512 3520 bgep->periodic_id = ddi_periodic_add(bge_chip_cyclic, bgep,
3513 3521 BGE_CYCLIC_PERIOD, DDI_IPL_0);
3514 3522
3515 3523 bgep->progress |= PROGRESS_READY;
3516 3524 ASSERT(bgep->bge_guard == BGE_GUARD);
3517 3525 #ifdef BGE_IPMI_ASF
3518 3526 #ifdef BGE_NETCONSOLE
3519 3527 if (bgep->asf_enabled) {
3520 3528 mutex_enter(bgep->genlock);
3521 3529 retval = bge_chip_start(bgep, B_TRUE);
3522 3530 mutex_exit(bgep->genlock);
3523 3531 if (retval != DDI_SUCCESS)
3524 3532 goto attach_fail;
3525 3533 }
3526 3534 #endif
3527 3535 #endif
3528 3536
3529 3537 ddi_report_dev(devinfo);
3530 3538
3531 3539 return (DDI_SUCCESS);
3532 3540
3533 3541 attach_fail:
3534 3542 #ifdef BGE_IPMI_ASF
3535 3543 bge_unattach(bgep, ASF_MODE_SHUTDOWN);
3536 3544 #else
3537 3545 bge_unattach(bgep);
3538 3546 #endif
3539 3547 return (DDI_FAILURE);
3540 3548 }
3541 3549
3542 3550 /*
3543 3551 * bge_suspend() -- suspend transmit/receive for powerdown
3544 3552 */
3545 3553 static int
3546 3554 bge_suspend(bge_t *bgep)
3547 3555 {
3548 3556 /*
3549 3557 * Stop processing and idle (powerdown) the PHY ...
3550 3558 */
3551 3559 mutex_enter(bgep->genlock);
3552 3560 #ifdef BGE_IPMI_ASF
3553 3561 /*
3554 3562 * Power management hasn't been supported in BGE now. If you
3555 3563 * want to implement it, please add the ASF/IPMI related
3556 3564 * code here.
3557 3565 */
3558 3566 #endif
3559 3567 bge_stop(bgep);
3560 3568 if (bge_phys_idle(bgep) != DDI_SUCCESS) {
3561 3569 (void) bge_check_acc_handle(bgep, bgep->io_handle);
3562 3570 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
3563 3571 mutex_exit(bgep->genlock);
3564 3572 return (DDI_FAILURE);
3565 3573 }
3566 3574 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) {
3567 3575 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
3568 3576 mutex_exit(bgep->genlock);
3569 3577 return (DDI_FAILURE);
3570 3578 }
3571 3579 mutex_exit(bgep->genlock);
3572 3580
3573 3581 return (DDI_SUCCESS);
3574 3582 }
3575 3583
3576 3584 /*
3577 3585 * quiesce(9E) entry point.
3578 3586 *
3579 3587 * This function is called when the system is single-threaded at high
3580 3588 * PIL with preemption disabled. Therefore, this function must not be
3581 3589 * blocked.
3582 3590 *
3583 3591 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
3584 3592 * DDI_FAILURE indicates an error condition and should almost never happen.
3585 3593 */
3586 3594 #ifdef __sparc
3587 3595 #define bge_quiesce ddi_quiesce_not_supported
3588 3596 #else
3589 3597 static int
3590 3598 bge_quiesce(dev_info_t *devinfo)
3591 3599 {
3592 3600 bge_t *bgep = ddi_get_driver_private(devinfo);
3593 3601
3594 3602 if (bgep == NULL)
3595 3603 return (DDI_FAILURE);
3596 3604
3597 3605 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
3598 3606 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
3599 3607 MHCR_MASK_PCI_INT_OUTPUT);
3600 3608 } else {
3601 3609 bge_reg_clr32(bgep, MSI_MODE_REG, MSI_MSI_ENABLE);
3602 3610 }
3603 3611
3604 3612 /* Stop the chip */
3605 3613 bge_chip_stop_nonblocking(bgep);
3606 3614
3607 3615 return (DDI_SUCCESS);
3608 3616 }
3609 3617 #endif
3610 3618
3611 3619 /*
3612 3620 * detach(9E) -- Detach a device from the system
3613 3621 */
3614 3622 static int
3615 3623 bge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
3616 3624 {
3617 3625 bge_t *bgep;
3618 3626 #ifdef BGE_IPMI_ASF
3619 3627 uint_t asf_mode;
3620 3628 asf_mode = ASF_MODE_NONE;
3621 3629 #endif
3622 3630
3623 3631 BGE_GTRACE(("bge_detach($%p, %d)", (void *)devinfo, cmd));
3624 3632
3625 3633 bgep = ddi_get_driver_private(devinfo);
3626 3634
3627 3635 switch (cmd) {
3628 3636 default:
3629 3637 return (DDI_FAILURE);
3630 3638
3631 3639 case DDI_SUSPEND:
3632 3640 return (bge_suspend(bgep));
3633 3641
3634 3642 case DDI_DETACH:
3635 3643 break;
3636 3644 }
3637 3645
3638 3646 #ifdef BGE_IPMI_ASF
3639 3647 mutex_enter(bgep->genlock);
3640 3648 if (bgep->asf_enabled && ((bgep->asf_status == ASF_STAT_RUN) ||
3641 3649 (bgep->asf_status == ASF_STAT_RUN_INIT))) {
3642 3650
3643 3651 bge_asf_update_status(bgep);
3644 3652 if (bgep->asf_status == ASF_STAT_RUN) {
3645 3653 bge_asf_stop_timer(bgep);
3646 3654 }
3647 3655 bgep->asf_status = ASF_STAT_STOP;
3648 3656
3649 3657 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3650 3658
3651 3659 if (bgep->asf_pseudostop) {
3652 3660 bge_chip_stop(bgep, B_FALSE);
3653 3661 bgep->bge_mac_state = BGE_MAC_STOPPED;
3654 3662 bgep->asf_pseudostop = B_FALSE;
3655 3663 }
3656 3664
3657 3665 asf_mode = ASF_MODE_POST_SHUTDOWN;
3658 3666
3659 3667 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
3660 3668 ddi_fm_service_impact(bgep->devinfo,
3661 3669 DDI_SERVICE_UNAFFECTED);
3662 3670 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
3663 3671 ddi_fm_service_impact(bgep->devinfo,
3664 3672 DDI_SERVICE_UNAFFECTED);
3665 3673 }
3666 3674 mutex_exit(bgep->genlock);
3667 3675 #endif
3668 3676
3669 3677 /*
3670 3678 * Unregister from the GLD subsystem. This can fail, in
3671 3679 * particular if there are DLPI style-2 streams still open -
3672 3680 * in which case we just return failure without shutting
3673 3681 * down chip operations.
3674 3682 */
3675 3683 if (mac_unregister(bgep->mh) != 0)
3676 3684 return (DDI_FAILURE);
3677 3685
3678 3686 /*
3679 3687 * All activity stopped, so we can clean up & exit
3680 3688 */
3681 3689 #ifdef BGE_IPMI_ASF
3682 3690 bge_unattach(bgep, asf_mode);
3683 3691 #else
3684 3692 bge_unattach(bgep);
3685 3693 #endif
3686 3694 return (DDI_SUCCESS);
3687 3695 }
3688 3696
3689 3697
3690 3698 /*
3691 3699 * ========== Module Loading Data & Entry Points ==========
3692 3700 */
3693 3701
3694 3702 #undef BGE_DBG
3695 3703 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */
3696 3704
3697 3705 DDI_DEFINE_STREAM_OPS(bge_dev_ops,
3698 3706 nulldev, /* identify */
3699 3707 nulldev, /* probe */
3700 3708 bge_attach, /* attach */
3701 3709 bge_detach, /* detach */
3702 3710 nodev, /* reset */
3703 3711 NULL, /* cb_ops */
3704 3712 D_MP, /* bus_ops */
3705 3713 NULL, /* power */
3706 3714 bge_quiesce /* quiesce */
3707 3715 );
3708 3716
3709 3717 static struct modldrv bge_modldrv = {
3710 3718 &mod_driverops, /* Type of module. This one is a driver */
3711 3719 bge_ident, /* short description */
3712 3720 &bge_dev_ops /* driver specific ops */
3713 3721 };
3714 3722
3715 3723 static struct modlinkage modlinkage = {
3716 3724 MODREV_1, (void *)&bge_modldrv, NULL
3717 3725 };
3718 3726
3719 3727
3720 3728 int
3721 3729 _info(struct modinfo *modinfop)
3722 3730 {
3723 3731 return (mod_info(&modlinkage, modinfop));
3724 3732 }
3725 3733
3726 3734 int
3727 3735 _init(void)
3728 3736 {
3729 3737 int status;
3730 3738
3731 3739 mac_init_ops(&bge_dev_ops, "bge");
3732 3740 status = mod_install(&modlinkage);
3733 3741 if (status == DDI_SUCCESS)
3734 3742 mutex_init(bge_log_mutex, NULL, MUTEX_DRIVER, NULL);
3735 3743 else
3736 3744 mac_fini_ops(&bge_dev_ops);
3737 3745 return (status);
3738 3746 }
3739 3747
3740 3748 int
3741 3749 _fini(void)
3742 3750 {
3743 3751 int status;
3744 3752
3745 3753 status = mod_remove(&modlinkage);
3746 3754 if (status == DDI_SUCCESS) {
3747 3755 mac_fini_ops(&bge_dev_ops);
3748 3756 mutex_destroy(bge_log_mutex);
3749 3757 }
3750 3758 return (status);
3751 3759 }
3752 3760
3753 3761
3754 3762 /*
3755 3763 * bge_add_intrs:
3756 3764 *
3757 3765 * Register FIXED or MSI interrupts.
3758 3766 */
3759 3767 static int
3760 3768 bge_add_intrs(bge_t *bgep, int intr_type)
3761 3769 {
3762 3770 dev_info_t *dip = bgep->devinfo;
3763 3771 int avail, actual, intr_size, count = 0;
3764 3772 int i, flag, ret;
3765 3773
3766 3774 BGE_DEBUG(("bge_add_intrs($%p, 0x%x)", (void *)bgep, intr_type));
3767 3775
3768 3776 /* Get number of interrupts */
3769 3777 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
3770 3778 if ((ret != DDI_SUCCESS) || (count == 0)) {
3771 3779 bge_error(bgep, "ddi_intr_get_nintrs() failure, ret: %d, "
3772 3780 "count: %d", ret, count);
3773 3781
3774 3782 return (DDI_FAILURE);
3775 3783 }
3776 3784
3777 3785 /* Get number of available interrupts */
3778 3786 ret = ddi_intr_get_navail(dip, intr_type, &avail);
3779 3787 if ((ret != DDI_SUCCESS) || (avail == 0)) {
3780 3788 bge_error(bgep, "ddi_intr_get_navail() failure, "
3781 3789 "ret: %d, avail: %d\n", ret, avail);
3782 3790
3783 3791 return (DDI_FAILURE);
3784 3792 }
3785 3793
3786 3794 if (avail < count) {
3787 3795 BGE_DEBUG(("%s: nintrs() returned %d, navail returned %d",
3788 3796 bgep->ifname, count, avail));
3789 3797 }
3790 3798
3791 3799 /*
3792 3800 * BGE hardware generates only single MSI even though it claims
3793 3801 * to support multiple MSIs. So, hard code MSI count value to 1.
3794 3802 */
3795 3803 if (intr_type == DDI_INTR_TYPE_MSI) {
3796 3804 count = 1;
3797 3805 flag = DDI_INTR_ALLOC_STRICT;
3798 3806 } else {
3799 3807 flag = DDI_INTR_ALLOC_NORMAL;
3800 3808 }
3801 3809
3802 3810 /* Allocate an array of interrupt handles */
3803 3811 intr_size = count * sizeof (ddi_intr_handle_t);
3804 3812 bgep->htable = kmem_alloc(intr_size, KM_SLEEP);
3805 3813
3806 3814 /* Call ddi_intr_alloc() */
3807 3815 ret = ddi_intr_alloc(dip, bgep->htable, intr_type, 0,
3808 3816 count, &actual, flag);
3809 3817
3810 3818 if ((ret != DDI_SUCCESS) || (actual == 0)) {
3811 3819 bge_error(bgep, "ddi_intr_alloc() failed %d\n", ret);
3812 3820
3813 3821 kmem_free(bgep->htable, intr_size);
3814 3822 return (DDI_FAILURE);
3815 3823 }
3816 3824
3817 3825 if (actual < count) {
3818 3826 BGE_DEBUG(("%s: Requested: %d, Received: %d",
3819 3827 bgep->ifname, count, actual));
3820 3828 }
3821 3829
3822 3830 bgep->intr_cnt = actual;
3823 3831
3824 3832 /*
3825 3833 * Get priority for first msi, assume remaining are all the same
3826 3834 */
3827 3835 if ((ret = ddi_intr_get_pri(bgep->htable[0], &bgep->intr_pri)) !=
3828 3836 DDI_SUCCESS) {
3829 3837 bge_error(bgep, "ddi_intr_get_pri() failed %d\n", ret);
3830 3838
3831 3839 /* Free already allocated intr */
3832 3840 for (i = 0; i < actual; i++) {
3833 3841 (void) ddi_intr_free(bgep->htable[i]);
3834 3842 }
3835 3843
3836 3844 kmem_free(bgep->htable, intr_size);
3837 3845 return (DDI_FAILURE);
3838 3846 }
3839 3847
3840 3848 /* Call ddi_intr_add_handler() */
3841 3849 for (i = 0; i < actual; i++) {
3842 3850 if ((ret = ddi_intr_add_handler(bgep->htable[i], bge_intr,
3843 3851 (caddr_t)bgep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
3844 3852 bge_error(bgep, "ddi_intr_add_handler() "
3845 3853 "failed %d\n", ret);
3846 3854
3847 3855 /* Free already allocated intr */
3848 3856 for (i = 0; i < actual; i++) {
3849 3857 (void) ddi_intr_free(bgep->htable[i]);
3850 3858 }
3851 3859
3852 3860 kmem_free(bgep->htable, intr_size);
3853 3861 return (DDI_FAILURE);
3854 3862 }
3855 3863 }
3856 3864
3857 3865 if ((ret = ddi_intr_get_cap(bgep->htable[0], &bgep->intr_cap))
3858 3866 != DDI_SUCCESS) {
3859 3867 bge_error(bgep, "ddi_intr_get_cap() failed %d\n", ret);
3860 3868
3861 3869 for (i = 0; i < actual; i++) {
3862 3870 (void) ddi_intr_remove_handler(bgep->htable[i]);
3863 3871 (void) ddi_intr_free(bgep->htable[i]);
3864 3872 }
3865 3873
3866 3874 kmem_free(bgep->htable, intr_size);
3867 3875 return (DDI_FAILURE);
3868 3876 }
3869 3877
3870 3878 return (DDI_SUCCESS);
3871 3879 }
3872 3880
3873 3881 /*
3874 3882 * bge_rem_intrs:
3875 3883 *
3876 3884 * Unregister FIXED or MSI interrupts
3877 3885 */
3878 3886 static void
3879 3887 bge_rem_intrs(bge_t *bgep)
3880 3888 {
3881 3889 int i;
3882 3890
3883 3891 BGE_DEBUG(("bge_rem_intrs($%p)", (void *)bgep));
3884 3892
3885 3893 /* Call ddi_intr_remove_handler() */
3886 3894 for (i = 0; i < bgep->intr_cnt; i++) {
3887 3895 (void) ddi_intr_remove_handler(bgep->htable[i]);
3888 3896 (void) ddi_intr_free(bgep->htable[i]);
3889 3897 }
3890 3898
3891 3899 kmem_free(bgep->htable, bgep->intr_cnt * sizeof (ddi_intr_handle_t));
3892 3900 }
3893 3901
3894 3902
3895 3903 void
3896 3904 bge_intr_enable(bge_t *bgep)
3897 3905 {
3898 3906 int i;
3899 3907
3900 3908 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) {
3901 3909 /* Call ddi_intr_block_enable() for MSI interrupts */
3902 3910 (void) ddi_intr_block_enable(bgep->htable, bgep->intr_cnt);
3903 3911 } else {
3904 3912 /* Call ddi_intr_enable for MSI or FIXED interrupts */
3905 3913 for (i = 0; i < bgep->intr_cnt; i++) {
3906 3914 (void) ddi_intr_enable(bgep->htable[i]);
3907 3915 }
3908 3916 }
3909 3917 }
3910 3918
3911 3919
3912 3920 void
3913 3921 bge_intr_disable(bge_t *bgep)
3914 3922 {
3915 3923 int i;
3916 3924
3917 3925 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) {
3918 3926 /* Call ddi_intr_block_disable() */
3919 3927 (void) ddi_intr_block_disable(bgep->htable, bgep->intr_cnt);
3920 3928 } else {
3921 3929 for (i = 0; i < bgep->intr_cnt; i++) {
3922 3930 (void) ddi_intr_disable(bgep->htable[i]);
3923 3931 }
3924 3932 }
3925 3933 }
3926 3934
3927 3935 int
3928 3936 bge_reprogram(bge_t *bgep)
3929 3937 {
3930 3938 int status = 0;
3931 3939
3932 3940 ASSERT(mutex_owned(bgep->genlock));
3933 3941
3934 3942 if (bge_phys_update(bgep) != DDI_SUCCESS) {
3935 3943 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
3936 3944 status = IOC_INVAL;
3937 3945 }
3938 3946 #ifdef BGE_IPMI_ASF
3939 3947 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) {
3940 3948 #else
3941 3949 if (bge_chip_sync(bgep) == DDI_FAILURE) {
3942 3950 #endif
3943 3951 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
3944 3952 status = IOC_INVAL;
3945 3953 }
3946 3954 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3947 3955 bge_chip_msi_trig(bgep);
3948 3956 return (status);
3949 3957 }
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