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--- old/usr/src/uts/common/io/bge/bge_impl.h
+++ new/usr/src/uts/common/io/bge/bge_impl.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 +/*
27 + * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 + */
29 +
26 30 #ifndef _BGE_IMPL_H
27 31 #define _BGE_IMPL_H
28 32
29 33
30 34 #ifdef __cplusplus
31 35 extern "C" {
32 36 #endif
33 37
34 38 #include <sys/types.h>
35 39 #include <sys/stream.h>
36 40 #include <sys/strsun.h>
37 41 #include <sys/strsubr.h>
38 42 #include <sys/stat.h>
39 43 #include <sys/pci.h>
40 44 #include <sys/note.h>
41 45 #include <sys/modctl.h>
42 46 #include <sys/crc32.h>
43 47 #ifdef __sparcv9
44 48 #include <v9/sys/membar.h>
45 49 #endif /* __sparcv9 */
46 50 #include <sys/kstat.h>
47 51 #include <sys/ethernet.h>
48 52 #include <sys/vlan.h>
49 53 #include <sys/errno.h>
50 54 #include <sys/dlpi.h>
51 55 #include <sys/devops.h>
52 56 #include <sys/debug.h>
53 57 #include <sys/conf.h>
54 58
55 59 #include <netinet/ip6.h>
56 60
57 61 #include <inet/common.h>
58 62 #include <inet/ip.h>
59 63 #include <inet/mi.h>
60 64 #include <inet/nd.h>
61 65 #include <sys/pattr.h>
62 66
63 67 #include <sys/disp.h>
64 68 #include <sys/cmn_err.h>
65 69 #include <sys/ddi.h>
66 70 #include <sys/sunddi.h>
67 71
68 72 #include <sys/ddifm.h>
69 73 #include <sys/fm/protocol.h>
70 74 #include <sys/fm/util.h>
71 75 #include <sys/fm/io/ddi.h>
72 76
73 77 #include <sys/mac_provider.h>
74 78 #include <sys/mac_ether.h>
75 79
76 80 #ifdef __amd64
77 81 #include <sys/x86_archext.h>
78 82 #endif
79 83
80 84 /*
81 85 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t;
82 86 * but of course C doesn't provide a way to check this directly. So here
83 87 * we rely on the fact that the symbol ETHERTYPE_AT was added to the
84 88 * header file (as a #define, which we *can* test for) at the same time
85 89 * as the typedef for ether_addr_t ;-!
86 90 */
87 91 #ifndef ETHERTYPE_AT
88 92 typedef uchar_t ether_addr_t[ETHERADDRL];
89 93 #endif /* ETHERTYPE_AT */
90 94
91 95 /*
92 96 * Reconfiguring the network devices requires the net_config privilege
93 97 * in Solaris 10+.
94 98 */
95 99 extern int secpolicy_net_config(const cred_t *, boolean_t);
96 100
97 101 #include <sys/netlb.h> /* originally from cassini */
98 102 #include <sys/miiregs.h> /* by fjlite out of intel */
99 103
100 104 #include "bge.h"
101 105 #include "bge_hw.h"
102 106
103 107 /*
104 108 * Compile-time feature switches ...
105 109 */
106 110 #define BGE_DO_PPIO 0 /* peek/poke ioctls */
107 111 #define BGE_RX_SOFTINT 0 /* softint per receive ring */
108 112 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */
109 113
110 114 /*
111 115 * NOTES:
112 116 *
113 117 * #defines:
114 118 *
115 119 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the
116 120 * register-set numbers to use for the config space registers
117 121 * and the operating registers respectively. On an OBP-based
118 122 * machine, regset 0 refers to CONFIG space, and regset 1 will
119 123 * be the operating registers in MEMORY space. If an expansion
120 124 * ROM is fitted, it may appear as a further register set.
121 125 *
122 126 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used
123 127 * for the data buffers. The descriptors are always set up
124 128 * in CONSISTENT mode.
125 129 *
126 130 * BGE_HEADROOM defines how much space we'll leave in allocated
127 131 * mblks before the first valid data byte. This should be chosen
128 132 * to be 2 modulo 4, so that once the ethernet header (14 bytes)
129 133 * has been stripped off, the packet data will be 4-byte aligned.
130 134 * The remaining space can be used by upstream modules to prepend
131 135 * any headers required.
132 136 */
133 137
134 138 #define BGE_PCI_CONFIG_RNUMBER 0
135 139 #define BGE_PCI_OPREGS_RNUMBER 1
136 140 #define BGE_DMA_MODE DDI_DMA_STREAMING
137 141 #define BGE_HEADROOM 34
138 142
139 143 /*
140 144 * BGE_HALFTICK is half the period of the cyclic callback (in
141 145 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s.
142 146 * Other time values are derived as odd multiples of this value
143 147 * so that there's little chance of ambiguity w.r.t. which tick
144 148 * a timeout expires on.
145 149 *
146 150 * BGE_PHY_STABLE_TIME is the period for which the contents of the
147 151 * PHY's status register must remain unchanging before we accept
148 152 * that the link has come up. [Sometimes the link comes up, only
149 153 * to go down again within a short time as the autonegotiation
150 154 * process cycles through various options before finding the best
151 155 * compatible mode. We don't want to report repeated link up/down
152 156 * cycles, so we wait until we think it's stable.]
153 157 *
154 158 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes
155 159 * interface. It's much shorter, 'cos the SerDes doesn't show
156 160 * these effects as much as the copper PHY.
157 161 *
158 162 * BGE_LINK_SETTLE_TIME is the period during which we regard link
159 163 * up/down cycles as an normal event after resetting/reprogramming
160 164 * the PHY. During this time, link up/down messages are sent to
161 165 * the log only, not the console. At any other time, link change
162 166 * events are regarded as unexpected and sent to both console & log.
163 167 *
164 168 * These latter two values have no theoretical justification, but
165 169 * are derived from observations and heuristics - the values below
166 170 * just seem to work quite well.
167 171 */
168 172
169 173 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */
170 174 #define BGE_CYCLIC_PERIOD (4*BGE_HALFTICK) /* ~1.0s */
171 175 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */
172 176 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */
173 177 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */
174 178
175 179 /*
176 180 * Indices used to identify the different buffer rings internally
177 181 */
178 182 #define BGE_STD_BUFF_RING 0
179 183 #define BGE_JUMBO_BUFF_RING 1
180 184 #define BGE_MINI_BUFF_RING 2
181 185
182 186 /*
183 187 * Current implementation limits
184 188 */
185 189 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */
186 190 /* for now */
187 191 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */
188 192 /* for now */
189 193 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */
190 194 /* for now */
191 195 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */
192 196
193 197 /*
194 198 * Ring/buffer size parameters
195 199 *
196 200 * All of the (up to) 16 TX rings & and the corresponding buffers are the
197 201 * same size.
198 202 *
199 203 * Each of the (up to) 3 receive producer (aka buffer) rings is a different
200 204 * size and has different sized buffers associated with it too.
201 205 *
202 206 * The (up to) 16 receive return rings have no buffers associated with them.
203 207 * The number of slots per receive return ring must be 2048 if the mini
204 208 * ring is enabled, otherwise it may be 1024. See Broadcom document
205 209 * 570X-PG102-R page 56.
206 210 *
207 211 * Note: only the 5700 supported external memory (and therefore the mini
208 212 * ring); the 5702/3/4 don't. This driver doesn't support the original
209 213 * 5700, so we won't ever use the mini ring capability.
210 214 */
211 215
212 216 #define BGE_SEND_RINGS_DEFAULT 1
213 217 #define BGE_RECV_RINGS_DEFAULT 1
214 218
215 219 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536
216 220 #define BGE_SEND_BUFF_SIZE_JUMBO 9022
217 221 #define BGE_SEND_SLOTS_USED 512
218 222
219 223 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */
220 224 #define BGE_STD_SLOTS_USED 512
221 225
222 226 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */
223 227 #define BGE_JUMBO_SLOTS_USED 256
224 228
225 229 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */
226 230 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */
227 231
228 232 #define BGE_RECV_BUFF_SIZE 0
229 233 #if BGE_MINI_SLOTS_USED > 0
230 234 #define BGE_RECV_SLOTS_USED 2048 /* required */
231 235 #else
232 236 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */
233 237 #endif
234 238
235 239 #define BGE_SEND_BUF_NUM 512
236 240 #define BGE_SEND_BUF_ARRAY 16
237 241 #define BGE_SEND_BUF_ARRAY_JUMBO 3
238 242 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY)
239 243
240 244 /*
241 245 * PCI type. PCI-Express or PCI/PCIX
242 246 */
243 247 #define BGE_PCI 0
244 248 #define BGE_PCI_E 1
245 249 #define BGE_PCI_X 2
246 250
247 251 /*
248 252 * Statistic type. There are two type of statistic:
249 253 * statistic block and statistic registers
250 254 */
251 255 #define BGE_STAT_BLK 1
252 256 #define BGE_STAT_REG 2
253 257
254 258 /*
255 259 * MTU.for all chipsets ,the default is 1500 ,and some chipsets
256 260 * support 9k jumbo frames size
257 261 */
258 262 #define BGE_DEFAULT_MTU 1500
259 263 #define BGE_MAXIMUM_MTU 9000
260 264
261 265 /*
262 266 * Pad the h/w defined status block (which can be up to 80 bytes long)
263 267 * to a power-of-two boundary
264 268 */
265 269 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t))
266 270
267 271 /*
268 272 * On platforms which support DVMA, we can simply allocate one big piece
269 273 * of memory for all the Tx buffers and another for the Rx buffers, and
270 274 * then carve them up as required. It doesn't matter if they aren't just
271 275 * one physically contiguous piece each, because both the CPU *and* the
272 276 * I/O device can see them *as though they were*.
273 277 *
274 278 * However, if only physically-addressed DMA is possible, this doesn't
275 279 * work; we can't expect to get enough contiguously-addressed memory for
276 280 * all the buffers of each type, so in this case we request a number of
277 281 * smaller pieces, each still large enough for several buffers but small
278 282 * enough to fit within "an I/O page" (e.g. 64K).
279 283 *
280 284 * The #define below specifies how many pieces of memory are to be used;
281 285 * 16 has been shown to work on an i86pc architecture but this could be
282 286 * different on other non-DVMA platforms ...
283 287 */
284 288 #ifdef _DMA_USES_VIRTADDR
285 289 #define BGE_SPLIT 1 /* no split required */
286 290 #else
287 291 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \
288 292 (BGE_RECV_RINGS_USED > 1))
289 293 #define BGE_SPLIT 128 /* split 128 ways */
290 294 #else
291 295 #define BGE_SPLIT 16 /* split 16 ways */
292 296 #endif
293 297 #endif /* _DMA_USES_VIRTADDR */
294 298
295 299 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1)
296 300
297 301 /*
298 302 * STREAMS parameters
299 303 */
300 304 #define BGE_IDNUM 0 /* zero seems to work */
301 305 #define BGE_LOWAT (256)
302 306 #define BGE_HIWAT (256*1024)
303 307
304 308
305 309 /*
306 310 * Basic data types, for clarity in distinguishing 'numbers'
307 311 * used for different purposes ...
308 312 *
309 313 * A <bge_regno_t> is a register 'address' (offset) in any one of
310 314 * various address spaces (PCI config space, PCI memory-mapped I/O
311 315 * register space, MII registers, etc). None of these exceeds 64K,
312 316 * so we could use a 16-bit representation but pointer-sized objects
313 317 * are more "natural" in most architectures; they seem to be handled
314 318 * more efficiently on SPARC and no worse on x86.
315 319 *
316 320 * BGE_REGNO_NONE represents the non-existent value in this space.
317 321 */
318 322 typedef uintptr_t bge_regno_t; /* register # (offset) */
319 323 #define BGE_REGNO_NONE (~(uintptr_t)0u)
320 324
321 325 /*
322 326 * Describes one chunk of allocated DMA-able memory
323 327 *
324 328 * In some cases, this is a single chunk as allocated from the system;
325 329 * but we also use this structure to represent slices carved off such
326 330 * a chunk. Even when we don't really need all the information, we
327 331 * use this structure as a convenient way of correlating the various
328 332 * ways of looking at a piece of memory (kernel VA, IO space DVMA,
329 333 * handle+offset, etc).
330 334 */
331 335 typedef struct {
332 336 ddi_acc_handle_t acc_hdl; /* handle for memory */
333 337 void *mem_va; /* CPU VA of memory */
334 338 uint32_t nslots; /* number of slots */
335 339 uint32_t size; /* size per slot */
336 340 size_t alength; /* allocated size */
337 341 /* >= product of above */
338 342
339 343 ddi_dma_handle_t dma_hdl; /* DMA handle */
340 344 offset_t offset; /* relative to handle */
341 345 ddi_dma_cookie_t cookie; /* associated cookie */
342 346 uint32_t ncookies; /* must be 1 */
343 347 uint32_t token; /* arbitrary identifier */
344 348 } dma_area_t; /* 0x50 (80) bytes */
345 349
346 350 typedef struct bge_queue_item {
347 351 struct bge_queue_item *next;
348 352 void *item;
349 353 } bge_queue_item_t;
350 354
351 355 typedef struct bge_queue {
352 356 bge_queue_item_t *head;
353 357 uint32_t count;
354 358 kmutex_t *lock;
355 359 } bge_queue_t;
356 360 /*
357 361 * Software version of the Receive Buffer Descriptor
358 362 * There's one of these for each receive buffer (up to 256/512/1024 per ring).
359 363 */
360 364 typedef struct sw_rbd {
361 365 dma_area_t pbuf; /* (const) related */
362 366 /* buffer area */
363 367 } sw_rbd_t; /* 0x50 (80) bytes */
364 368
365 369 /*
366 370 * Software Receive Buffer (Producer) Ring Control Block
367 371 * There's one of these for each receiver producer ring (up to 3),
368 372 * but each holds buffers of a different size.
369 373 */
370 374 typedef struct buff_ring {
371 375 dma_area_t desc; /* (const) related h/w */
372 376 /* descriptor area */
373 377 dma_area_t buf[BGE_SPLIT]; /* (const) related */
374 378 /* buffer area(s) */
375 379 bge_rcb_t hw_rcb; /* (const) image of h/w */
376 380 /* RCB, and used to */
377 381 struct bge *bgep; /* (const) containing */
378 382 /* driver soft state */
379 383 /* initialise same */
380 384 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
381 385 /* "consumer index" */
382 386 /* (in status block) */
383 387
384 388 /*
385 389 * The rf_lock must be held when updating the h/w producer index
386 390 * mailbox register (*chip_mbox_reg), or the s/w producer index
387 391 * (rf_next).
388 392 */
389 393 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
390 394 /* index mailbox offset */
391 395 kmutex_t rf_lock[1]; /* serialize refill */
392 396 uint64_t rf_next; /* next slot to refill */
393 397 /* ("producer index") */
394 398
395 399 sw_rbd_t *sw_rbds; /* software descriptors */
396 400 void *spare[4]; /* padding */
397 401 } buff_ring_t; /* 0x100 (256) bytes */
398 402
399 403 typedef struct bge_multi_mac {
400 404 int naddr; /* total supported addresses */
401 405 int naddrfree; /* free addresses slots */
402 406 ether_addr_t mac_addr[MAC_ADDRESS_REGS_MAX];
403 407 boolean_t mac_addr_set[MAC_ADDRESS_REGS_MAX];
404 408 } bge_multi_mac_t;
405 409
406 410 /*
407 411 * Software Receive (Return) Ring Control Block
408 412 * There's one of these for each receiver return ring (up to 16).
409 413 */
410 414 typedef struct recv_ring {
411 415 /*
412 416 * The elements flagged (const) in the comments below are
413 417 * set up once during initialiation and thereafter unchanged.
414 418 */
415 419 dma_area_t desc; /* (const) related h/w */
416 420 /* descriptor area */
417 421 bge_rcb_t hw_rcb; /* (const) image of h/w */
418 422 /* RCB, and used to */
419 423 /* initialise same */
420 424 struct bge *bgep; /* (const) containing */
421 425 /* driver soft state */
422 426 ddi_softintr_t rx_softint; /* (const) per-ring */
423 427 /* receive callback */
424 428 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */
425 429 /* "producer index" */
426 430 /* (in status block) */
427 431 /*
428 432 * The rx_lock must be held when updating the h/w consumer index
429 433 * mailbox register (*chip_mbox_reg), or the s/w consumer index
430 434 * (rx_next).
431 435 */
432 436 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */
433 437 /* index mailbox offset */
434 438 kmutex_t rx_lock[1]; /* serialize receive */
435 439 uint64_t rx_next; /* next slot to examine */
436 440
437 441 mac_ring_handle_t ring_handle;
438 442 mac_group_handle_t ring_group_handle;
439 443 uint64_t ring_gen_num;
440 444 bge_rule_info_t *mac_addr_rule;
441 445 uint8_t mac_addr_val[ETHERADDRL];
442 446 int poll_flag; /* Polling flag */
443 447
444 448 /* Per-ring statistics */
445 449 uint64_t rx_pkts; /* Received Packets Count */
446 450 uint64_t rx_bytes; /* Received Bytes Count */
447 451 } recv_ring_t;
448 452
449 453
450 454 /*
451 455 * Send packet structure
452 456 */
453 457 typedef struct send_pkt {
454 458 uint16_t vlan_tci;
455 459 uint32_t pflags;
456 460 boolean_t tx_ready;
457 461 bge_queue_item_t *txbuf_item;
458 462 } send_pkt_t;
459 463
460 464 /*
461 465 * Software version of tx buffer structure
462 466 */
463 467 typedef struct sw_txbuf {
464 468 dma_area_t buf;
465 469 uint32_t copy_len;
466 470 } sw_txbuf_t;
467 471
468 472 /*
469 473 * Software version of the Send Buffer Descriptor
470 474 * There's one of these for each send buffer (up to 512 per ring)
471 475 */
472 476 typedef struct sw_sbd {
473 477 dma_area_t desc; /* (const) related h/w */
474 478 /* descriptor area */
475 479 bge_queue_item_t *pbuf; /* (const) related */
476 480 /* buffer area */
477 481 } sw_sbd_t;
478 482
479 483 /*
480 484 * Software Send Ring Control Block
481 485 * There's one of these for each of (up to) 16 send rings
482 486 */
483 487 typedef struct send_ring {
484 488 /*
485 489 * The elements flagged (const) in the comments below are
486 490 * set up once during initialiation and thereafter unchanged.
487 491 */
488 492 dma_area_t desc; /* (const) related h/w */
489 493 /* descriptor area */
490 494 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT];
491 495 /* buffer area(s) */
492 496 bge_rcb_t hw_rcb; /* (const) image of h/w */
493 497 /* RCB, and used to */
494 498 /* initialise same */
495 499 struct bge *bgep; /* (const) containing */
496 500 /* driver soft state */
497 501 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
498 502 /* "consumer index" */
499 503 /* (in status block) */
500 504
501 505 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
502 506 /* index mailbox offset */
503 507 /*
504 508 * Tx buffer queue
505 509 */
506 510 bge_queue_t txbuf_queue;
507 511 bge_queue_t freetxbuf_queue;
508 512 bge_queue_t *txbuf_push_queue;
509 513 bge_queue_t *txbuf_pop_queue;
510 514 kmutex_t txbuf_lock[1];
511 515 kmutex_t freetxbuf_lock[1];
512 516 bge_queue_item_t *txbuf_head;
513 517 send_pkt_t *pktp;
514 518 uint64_t txpkt_next;
515 519 uint64_t txfill_next;
516 520 sw_txbuf_t *txbuf;
517 521 uint32_t tx_buffers;
518 522 uint32_t tx_buffers_low;
519 523 uint32_t tx_array_max;
520 524 uint32_t tx_array;
521 525 kmutex_t tx_lock[1]; /* serialize h/w update */
522 526 /* ("producer index") */
523 527 uint64_t tx_next; /* next slot to use */
524 528 uint64_t tx_flow; /* # concurrent sends */
525 529 uint64_t tx_block;
526 530 uint64_t tx_nobd;
527 531 uint64_t tx_nobuf;
528 532 uint64_t tx_alloc_fail;
529 533
530 534 /*
531 535 * These counters/indexes are manipulated in the transmit
532 536 * path using atomics rather than mutexes for speed
533 537 */
534 538 uint64_t tx_free; /* # of slots available */
535 539
536 540 /*
537 541 * The tc_lock must be held while manipulating the s/w consumer
538 542 * index (tc_next).
539 543 */
540 544 kmutex_t tc_lock[1]; /* serialize recycle */
541 545 uint64_t tc_next; /* next slot to recycle */
542 546 /* ("consumer index") */
543 547
544 548 sw_sbd_t *sw_sbds; /* software descriptors */
545 549 uint64_t mac_resid; /* special per resource id */
546 550 uint64_t pushed_bytes;
547 551 } send_ring_t; /* 0x100 (256) bytes */
548 552
549 553 typedef struct {
550 554 ether_addr_t addr; /* in canonical form */
551 555 uint8_t spare;
552 556 boolean_t set; /* B_TRUE => valid */
553 557 } bge_mac_addr_t;
554 558
555 559 /*
556 560 * The original 5700/01 supported only SEEPROMs. Later chips (5702+)
557 561 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for
558 562 * the hardware and a backwards-compatible software access method), and
559 563 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus
560 564 * and using a new software access method.
561 565 *
562 566 * The access methods for SEEPROM and Flash are generally similar, with
563 567 * the chip handling the serialisation/deserialisation and handshaking,
564 568 * but the registers used are different, as are a few details of the
565 569 * protocol, and the timing, so we have to determine which (if any) is
566 570 * fitted.
567 571 *
568 572 * The value UNKNOWN means just that; we haven't yet tried to determine
569 573 * the device type.
570 574 *
571 575 * The value NONE can indicate either that a real and definite absence of
572 576 * any NVmem has been detected, or that there may be NVmem but we can't
573 577 * determine its type, perhaps because the NVconfig pins on the chip have
574 578 * been wired up incorrectly. In either case, access to the NVmem (if any)
575 579 * is not supported.
576 580 */
577 581 enum bge_nvmem_type {
578 582 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */
579 583 BGE_NVTYPE_UNKNOWN, /* not yet checked */
580 584 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */
581 585 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */
582 586 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */
583 587 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */
584 588 };
585 589
586 590 /*
587 591 * Describes the characteristics of a specific chip
588 592 *
589 593 * Note: elements from <businfo> to <latency> are filled in by during
590 594 * the first phase of chip initialisation (see bge_chip_cfg_init()).
591 595 * The remaining ones are determined just after the first RESET, in
592 596 * bge_poll_firmware(). Thereafter, the entire structure is readonly.
593 597 */
594 598 typedef struct {
595 599 uint32_t asic_rev; /* masked from MHCR */
596 600 uint32_t businfo; /* from private reg */
597 601 uint16_t command; /* saved during attach */
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598 602
599 603 uint16_t vendor; /* vendor-id */
600 604 uint16_t device; /* device-id */
601 605 uint16_t subven; /* subsystem-vendor-id */
602 606 uint16_t subdev; /* subsystem-id */
603 607 uint8_t revision; /* revision-id */
604 608 uint8_t clsize; /* cache-line-size */
605 609 uint8_t latency; /* latency-timer */
606 610
607 611 uint8_t flags;
612 + uint32_t chip_type; /* see CHIP_TYPE_ in bge_hw.h */
608 613 uint16_t chip_label; /* numeric part only */
609 614 /* (e.g. 5703/5794/etc) */
610 615 uint32_t mbuf_base; /* Mbuf pool parameters */
611 616 uint32_t mbuf_length; /* depend on chiptype */
612 617 uint32_t pci_type;
613 618 uint32_t statistic_type;
614 619 uint32_t bge_dma_rwctrl;
615 620 uint32_t bge_mlcr_default;
616 621 uint32_t recv_slots; /* receive ring size */
617 622 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */
618 623
619 624 uint16_t jumbo_slots;
620 625 uint16_t ethmax_size;
621 626 uint16_t snd_buff_size;
622 627 uint16_t recv_jumbo_size;
623 628 uint16_t std_buf_size;
624 629 uint32_t mbuf_hi_water;
625 630 uint32_t mbuf_lo_water_rmac;
626 631 uint32_t mbuf_lo_water_rdma;
627 632
628 633 uint32_t rx_rings; /* from bge.conf */
629 634 uint32_t tx_rings; /* from bge.conf */
630 635 uint32_t default_mtu; /* from bge.conf */
631 636
632 637 uint64_t hw_mac_addr; /* from chip register */
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633 638 bge_mac_addr_t vendor_addr; /* transform of same */
634 639 boolean_t msi_enabled; /* default to true */
635 640
636 641 uint32_t rx_ticks_norm;
637 642 uint32_t rx_count_norm;
638 643 uint32_t tx_ticks_norm;
639 644 uint32_t tx_count_norm;
640 645 uint32_t mask_pci_int;
641 646 } chip_id_t;
642 647
643 -#define CHIP_FLAG_SUPPORTED 0x80
644 -#define CHIP_FLAG_SERDES 0x40
645 -#define CHIP_FLAG_PARTIAL_CSUM 0x20
646 -#define CHIP_FLAG_NO_JUMBO 0x1
648 +#define CHIP_FLAG_SUPPORTED 0x80
649 +#define CHIP_FLAG_SERDES 0x40
650 +#define CHIP_FLAG_PARTIAL_CSUM 0x20
651 +#define CHIP_FLAG_NO_CHECK_RESET 0x2
652 +#define CHIP_FLAG_NO_JUMBO 0x1
647 653
648 654 /*
649 655 * Collection of physical-layer functions to:
650 656 * (re)initialise the physical layer
651 657 * update it to match software settings
652 658 * check for link status change
653 659 */
654 660 typedef struct {
655 661 int (*phys_restart)(struct bge *, boolean_t);
656 662 int (*phys_update)(struct bge *);
657 663 boolean_t (*phys_check)(struct bge *, boolean_t);
658 664 } phys_ops_t;
659 665
660 666
661 667 /*
662 668 * Actual state of the BCM570x chip
663 669 */
664 670 enum bge_chip_state {
665 671 BGE_CHIP_FAULT = -2, /* fault, need reset */
666 672 BGE_CHIP_ERROR, /* error, want reset */
667 673 BGE_CHIP_INITIAL, /* Initial state only */
668 674 BGE_CHIP_RESET, /* reset, need init */
669 675 BGE_CHIP_STOPPED, /* Tx/Rx stopped */
670 676 BGE_CHIP_RUNNING /* with interrupts */
671 677 };
672 678
673 679 enum bge_mac_state {
674 680 BGE_MAC_STOPPED = 0,
675 681 BGE_MAC_STARTED
676 682 };
677 683
678 684 /*
679 685 * (Internal) return values from ioctl subroutines
680 686 */
681 687 enum ioc_reply {
682 688 IOC_INVAL = -1, /* bad, NAK with EINVAL */
683 689 IOC_DONE, /* OK, reply sent */
684 690 IOC_ACK, /* OK, just send ACK */
685 691 IOC_REPLY, /* OK, just send reply */
686 692 IOC_RESTART_ACK, /* OK, restart & ACK */
687 693 IOC_RESTART_REPLY /* OK, restart & reply */
688 694 };
689 695
690 696 /*
691 697 * (Internal) return values from send_msg subroutines
692 698 */
693 699 enum send_status {
694 700 SEND_FAIL = -1, /* Not OK */
695 701 SEND_KEEP, /* OK, msg queued */
696 702 SEND_FREE /* OK, free msg */
697 703 };
698 704
699 705 /*
700 706 * (Internal) enumeration of this driver's kstats
701 707 */
702 708 enum {
703 709 BGE_KSTAT_RAW = 0,
704 710 BGE_KSTAT_STATS,
705 711 BGE_KSTAT_CHIPID,
706 712 BGE_KSTAT_DRIVER,
707 713 BGE_KSTAT_PHYS,
708 714
709 715 BGE_KSTAT_COUNT
710 716 };
711 717
712 718 #define BGE_MAX_RESOURCES 255
713 719
714 720 /*
715 721 * Per-instance soft-state structure
716 722 */
717 723 typedef struct bge {
718 724 /*
719 725 * These fields are set by attach() and unchanged thereafter ...
720 726 */
721 727 dev_info_t *devinfo; /* device instance */
722 728 mac_handle_t mh; /* mac module handle */
723 729 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */
724 730 ddi_acc_handle_t io_handle; /* DDI I/O handle */
725 731 void *io_regs; /* mapped registers */
726 732 ddi_periodic_t periodic_id; /* periodical callback */
727 733 ddi_softintr_t factotum_id; /* factotum callback */
728 734 ddi_softintr_t drain_id; /* reschedule callback */
729 735
730 736 ddi_intr_handle_t *htable; /* For array of interrupts */
731 737 int intr_type; /* What type of interrupt */
732 738 int intr_cnt; /* # of intrs count returned */
733 739 uint_t intr_pri; /* Interrupt priority */
734 740 int intr_cap; /* Interrupt capabilities */
735 741 uint32_t progress; /* attach tracking */
736 742 uint32_t debug; /* per-instance debug */
737 743 chip_id_t chipid;
738 744 const phys_ops_t *physops;
739 745 char ifname[8]; /* "bge0" ... "bge999" */
740 746
741 747 int fm_capabilities; /* FMA capabilities */
742 748
743 749 /*
744 750 * These structures describe the blocks of memory allocated during
745 751 * attach(). They remain unchanged thereafter, although the memory
746 752 * they describe is carved up into various separate regions and may
747 753 * therefore be described by other structures as well.
748 754 */
749 755 dma_area_t tx_desc; /* transmit descriptors */
750 756 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT];
751 757 /* receive descriptors */
752 758 dma_area_t tx_buff[BGE_SPLIT];
753 759 dma_area_t rx_buff[BGE_SPLIT];
754 760
755 761 /*
756 762 * The memory described by the <dma_area> structures above
757 763 * is carved up into various pieces, which are described by
758 764 * the structures below.
759 765 */
760 766 dma_area_t statistics; /* describes hardware */
761 767 /* statistics area */
762 768 dma_area_t status_block; /* describes hardware */
763 769 /* status block */
764 770 /*
765 771 * For the BCM5705/5788/5721/5751/5752/5714 and 5715,
766 772 * the statistic block is not available,the statistic counter must
767 773 * be gotten from statistic registers.And bge_statistics_reg_t record
768 774 * the statistic registers value
769 775 */
770 776 bge_statistics_reg_t *pstats;
771 777
772 778 /*
773 779 * Runtime read-write data starts here ...
774 780 *
775 781 * 3 Buffer Rings (std/jumbo/mini)
776 782 * 16 Receive (Return) Rings
777 783 * 16 Send Rings
778 784 *
779 785 * Note: they're not necessarily all used.
780 786 */
781 787 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */
782 788
783 789 /* may be obsoleted */
784 790 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */
785 791 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */
786 792
787 793 /*
788 794 * Locks:
789 795 *
790 796 * Each buffer ring contains its own <rf_lock> which regulates
791 797 * ring refilling.
792 798 *
793 799 * Each receive (return) ring contains its own <rx_lock> which
794 800 * protects the critical cyclic counters etc.
795 801 *
796 802 * Each send ring contains two locks: <tx_lock> for the send-path
797 803 * protocol data and <tc_lock> for send-buffer recycling.
798 804 *
799 805 * Finally <genlock> is a general lock, protecting most other
800 806 * operational data in the state structure and chip register
801 807 * accesses. It is acquired by the interrupt handler and
802 808 * most "mode-control" routines.
803 809 *
804 810 * Any of the locks can be acquired singly, but where multiple
805 811 * locks are acquired, they *must* be in the order:
806 812 *
807 813 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock.
808 814 *
809 815 * and within any one class of lock the rings must be locked in
810 816 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc.
811 817 *
812 818 * Note: actually I don't believe there's any need to acquire
813 819 * locks on multiple rings, or even locks of all these classes
814 820 * concurrently; but I've set out the above order so there is a
815 821 * clear definition of lock hierarchy in case it's ever needed.
816 822 *
817 823 * Note: the combinations of locks that are actually held
818 824 * concurrently are:
819 825 *
820 826 * genlock >>> (bge_chip_interrupt())
821 827 * rx_lock[i] >>> (bge_receive())
822 828 * rf_lock[n] (bge_refill())
823 829 * tc_lock[i] (bge_recycle())
824 830 */
825 831 kmutex_t genlock[1];
826 832 krwlock_t errlock[1];
827 833 kmutex_t softintrlock[1];
828 834
829 835 /*
830 836 * Current Ethernet addresses and multicast hash (bitmap) and
831 837 * refcount tables, protected by <genlock>
832 838 */
833 839 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX];
834 840 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32];
835 841 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE];
836 842 uint32_t unicst_addr_total; /* total unicst addresses */
837 843 uint32_t unicst_addr_avail;
838 844 /* unused unicst addr slots */
839 845
840 846 /*
841 847 * Link state data (protected by genlock)
842 848 */
843 849 link_state_t link_state;
844 850
845 851 /*
846 852 * Physical layer: copper only
847 853 */
848 854 bge_regno_t phy_mii_addr; /* should be (const) 1! */
849 855 uint16_t phy_gen_status;
850 856 uint16_t phy_aux_status;
851 857
852 858 /*
853 859 * Physical layer: serdes only
854 860 */
855 861 uint32_t serdes_status;
856 862 uint32_t serdes_advert;
857 863 uint32_t serdes_lpadv;
858 864
859 865 /*
860 866 * Driver kstats, protected by <genlock> where necessary
861 867 */
862 868 kstat_t *bge_kstats[BGE_KSTAT_COUNT];
863 869
864 870 /*
865 871 * Miscellaneous operating variables (protected by genlock)
866 872 */
867 873 uint64_t chip_resets; /* # of chip RESETs */
868 874 uint64_t missed_dmas; /* # of missed DMAs */
869 875 uint64_t missed_updates; /* # of missed updates */
870 876 enum bge_mac_state bge_mac_state; /* definitions above */
871 877 enum bge_chip_state bge_chip_state; /* definitions above */
872 878 boolean_t send_hw_tcp_csum;
873 879 boolean_t recv_hw_tcp_csum;
874 880 boolean_t promisc;
875 881 boolean_t manual_reset;
876 882
877 883 /*
878 884 * Miscellaneous operating variables (not synchronised)
879 885 */
880 886 uint32_t watchdog; /* watches for Tx stall */
881 887 boolean_t bge_intr_running;
882 888 boolean_t bge_dma_error;
883 889 boolean_t tx_resched_needed;
884 890 uint64_t tx_resched;
885 891 uint32_t factotum_flag; /* softint pending */
886 892 uintptr_t pagemask;
887 893
888 894 /*
889 895 * NDD parameters (protected by genlock)
890 896 */
891 897 caddr_t nd_data_p;
892 898
893 899 /*
894 900 * A flag to prevent excessive config space accesses
895 901 * on platforms having BCM5714C/15C
896 902 */
897 903 boolean_t lastWriteZeroData;
898 904
899 905 /*
900 906 * Spare space, plus guard element used to check data integrity
901 907 */
902 908 uint64_t spare[5];
903 909 uint64_t bge_guard;
904 910
905 911 /*
906 912 * Receive rules configure
907 913 */
908 914 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX];
909 915
910 916 #ifdef BGE_IPMI_ASF
911 917 boolean_t asf_enabled;
912 918 boolean_t asf_wordswapped;
913 919 boolean_t asf_newhandshake;
914 920 boolean_t asf_pseudostop;
915 921
916 922 uint32_t asf_status;
917 923 timeout_id_t asf_timeout_id;
918 924 #endif
919 925 uint32_t param_en_pause:1,
920 926 param_en_asym_pause:1,
921 927 param_en_1000hdx:1,
922 928 param_en_1000fdx:1,
923 929 param_en_100fdx:1,
924 930 param_en_100hdx:1,
925 931 param_en_10fdx:1,
926 932 param_en_10hdx:1,
927 933 param_adv_autoneg:1,
928 934 param_adv_1000fdx:1,
929 935 param_adv_1000hdx:1,
930 936 param_adv_100fdx:1,
931 937 param_adv_100hdx:1,
932 938 param_adv_10fdx:1,
933 939 param_adv_10hdx:1,
934 940 param_lp_autoneg:1,
935 941 param_lp_pause:1,
936 942 param_lp_asym_pause:1,
937 943 param_lp_1000fdx:1,
938 944 param_lp_1000hdx:1,
939 945 param_lp_100fdx:1,
940 946 param_lp_100hdx:1,
941 947 param_lp_10fdx:1,
942 948 param_lp_10hdx:1,
943 949 param_link_up:1,
944 950 param_link_autoneg:1,
945 951 param_adv_pause:1,
946 952 param_adv_asym_pause:1,
947 953 param_link_rx_pause:1,
948 954 param_link_tx_pause:1,
949 955 param_pad_to_32:2;
950 956
951 957 uint32_t param_loop_mode;
952 958 uint32_t param_msi_cnt;
953 959 uint32_t param_drain_max;
954 960 uint64_t param_link_speed;
955 961 link_duplex_t param_link_duplex;
956 962
957 963
958 964 uint32_t link_update_timer;
959 965 uint64_t timestamp;
960 966 } bge_t;
961 967
962 968 /*
963 969 * 'Progress' bit flags ...
964 970 */
965 971 #define PROGRESS_CFG 0x0001 /* config space mapped */
966 972 #define PROGRESS_REGS 0x0002 /* registers mapped */
967 973 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */
968 974 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */
969 975 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */
970 976 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */
971 977 /* and mutexen initialised */
972 978 #define PROGRESS_INTR 0x0080 /* Intrs enabled */
973 979 #define PROGRESS_PHY 0x0100 /* PHY initialised */
974 980 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */
975 981 #define PROGRESS_KSTATS 0x2000 /* kstats created */
976 982 #define PROGRESS_READY 0x8000 /* ready for work */
977 983
978 984
979 985 /*
980 986 * Sync a DMA area described by a dma_area_t
981 987 */
982 988 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \
983 989 (area).offset, (area).alength, (flag)))
984 990
985 991 /*
986 992 * Find the (kernel virtual) address of block of memory
987 993 * described by a dma_area_t
988 994 */
989 995 #define DMA_VPTR(area) ((area).mem_va)
990 996
991 997 /*
992 998 * Zero a block of memory described by a dma_area_t
993 999 */
994 1000 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength)
995 1001
996 1002 /*
997 1003 * Next value of a cyclic index
998 1004 */
999 1005 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0)
1000 1006
1001 1007 /*
1002 1008 * Property lookups
1003 1009 */
1004 1010 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
1005 1011 DDI_PROP_DONTPASS, (n))
1006 1012 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
1007 1013 DDI_PROP_DONTPASS, (n), -1)
1008 1014
1009 1015 /*
1010 1016 * Copy an ethernet address
1011 1017 */
1012 1018 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL)
1013 1019
1014 1020 /*
1015 1021 * Endian swap
1016 1022 */
1017 1023 /* BEGIN CSTYLED */
1018 1024 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \
1019 1025 (((x) & 0x00ff0000) >> 8) | \
1020 1026 (((x) & 0x0000ff00) << 8) | \
1021 1027 (((x) & 0x000000ff) << 24))
1022 1028 /* END CSTYLED */
1023 1029
1024 1030 /*
1025 1031 * Marker value placed at the end of the driver's state
1026 1032 */
1027 1033 #define BGE_GUARD 0x1919306009031802
1028 1034
1029 1035 /*
1030 1036 * Bit flags in the 'debug' word ...
1031 1037 */
1032 1038 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */
1033 1039 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */
1034 1040
1035 1041 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */
1036 1042 #define BGE_DBG_MII 0x00000020 /* low-level MII access */
1037 1043 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */
1038 1044 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */
1039 1045
1040 1046 #define BGE_DBG_RECV 0x00000100 /* receive-side code */
1041 1047 #define BGE_DBG_SEND 0x00000200 /* packet-send code */
1042 1048
1043 1049 #define BGE_DBG_INT 0x00001000 /* interrupt handler */
1044 1050 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */
1045 1051
1046 1052 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */
1047 1053 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */
1048 1054 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */
1049 1055 #define BGE_DBG_LINK 0x00080000 /* Link status check */
1050 1056
1051 1057 #define BGE_DBG_INIT 0x00100000 /* initialisation */
1052 1058 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */
1053 1059 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */
1054 1060 #define BGE_DBG_STATS 0x00800000 /* statistics */
1055 1061
1056 1062 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */
1057 1063 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */
1058 1064 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */
1059 1065 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */
1060 1066
1061 1067 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */
1062 1068 #define BGE_DBG_NDD 0x20000000 /* NDD operations */
1063 1069
1064 1070 /*
1065 1071 * Debugging ...
1066 1072 */
1067 1073 #ifdef DEBUG
1068 1074 #define BGE_DEBUGGING 1
1069 1075 #else
1070 1076 #define BGE_DEBUGGING 0
1071 1077 #endif /* DEBUG */
1072 1078
1073 1079
1074 1080 /*
1075 1081 * 'Do-if-debugging' macro. The parameter <command> should be one or more
1076 1082 * C statements (but without the *final* semicolon), which will either be
1077 1083 * compiled inline or completely ignored, depending on the BGE_DEBUGGING
1078 1084 * compile-time flag.
1079 1085 *
1080 1086 * You should get a compile-time error (at least on a DEBUG build) if
1081 1087 * your statement isn't actually a statement, rather than unexpected
1082 1088 * run-time behaviour caused by unintended matching of if-then-elses etc.
1083 1089 *
1084 1090 * Note that the BGE_DDB() macro itself can only be used as a statement,
1085 1091 * not an expression, and should always be followed by a semicolon.
1086 1092 */
1087 1093 #if BGE_DEBUGGING
1088 1094 #define BGE_DDB(command) do { \
1089 1095 { command; } \
1090 1096 _NOTE(CONSTANTCONDITION) \
1091 1097 } while (0)
1092 1098 #else /* BGE_DEBUGGING */
1093 1099 #define BGE_DDB(command) do { \
1094 1100 { _NOTE(EMPTY); } \
1095 1101 _NOTE(CONSTANTCONDITION) \
1096 1102 } while (0)
1097 1103 #endif /* BGE_DEBUGGING */
1098 1104
1099 1105 /*
1100 1106 * 'Internal' macros used to construct the TRACE/DEBUG macros below.
1101 1107 * These provide the primitive conditional-call capability required.
1102 1108 * Note: the parameter <args> is a parenthesised list of the actual
1103 1109 * printf-style arguments to be passed to the debug function ...
1104 1110 */
1105 1111 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args)
1106 1112 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args)
1107 1113 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args)
1108 1114 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args)
1109 1115
1110 1116 /*
1111 1117 * Conditional-print macros.
1112 1118 *
1113 1119 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values
1114 1120 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G'
1115 1121 * versions look at the Global debug flag word (bge_debug); the non-G
1116 1122 * versions look in the per-instance data (bgep->debug) and so require a
1117 1123 * variable called 'bgep' to be in scope (and initialised!) before use.
1118 1124 *
1119 1125 * You could redefine BGE_TRC too if you really need two different
1120 1126 * flavours of debugging output in the same area of code, but I don't
1121 1127 * really recommend it.
1122 1128 *
1123 1129 * Note: the parameter <args> is a parenthesised list of the actual
1124 1130 * arguments to be passed to the debug function, usually a printf-style
1125 1131 * format string and corresponding values to be formatted.
1126 1132 */
1127 1133
1128 1134 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */
1129 1135 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args)
1130 1136 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args)
1131 1137 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args)
1132 1138 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args)
1133 1139
1134 1140 /*
1135 1141 * Debug-only action macros
1136 1142 */
1137 1143 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s))
1138 1144 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep))
1139 1145 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep))
1140 1146 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args)
1141 1147 #define BGE_REPORT(args) BGE_DDB(bge_log args)
1142 1148
1143 1149 /*
1144 1150 * Inter-source-file linkage ...
1145 1151 */
1146 1152
1147 1153 /* bge_chip.c */
1148 1154 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1149 1155 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value);
1150 1156 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
1151 1157 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value);
1152 1158 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1153 1159 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1154 1160 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value);
1155 1161 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
1156 1162 int bge_chip_id_init(bge_t *bgep);
1157 1163 void bge_chip_coalesce_update(bge_t *bgep);
1158 1164 int bge_chip_start(bge_t *bgep, boolean_t reset_phy);
1159 1165 void bge_chip_stop(bge_t *bgep, boolean_t fault);
1160 1166 #ifndef __sparc
1161 1167 void bge_chip_stop_nonblocking(bge_t *bgep);
1162 1168 #endif
1163 1169 #ifdef BGE_IPMI_ASF
1164 1170 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
1165 1171 #pragma inline(bge_nic_put32)
1166 1172 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr);
1167 1173 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
1168 1174 #pragma inline(bge_ind_put32)
1169 1175 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
1170 1176 #pragma inline(bge_ind_get32)
1171 1177 void bge_asf_update_status(bge_t *bgep);
1172 1178 void bge_asf_heartbeat(void *bgep);
1173 1179 void bge_asf_stop_timer(bge_t *bgep);
1174 1180 void bge_asf_get_config(bge_t *bgep);
1175 1181 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode);
1176 1182 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode);
1177 1183 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode);
1178 1184 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
1179 1185 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
1180 1186 #else
1181 1187 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
1182 1188 int bge_chip_sync(bge_t *bgep);
1183 1189 #endif
1184 1190 void bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag);
1185 1191 extern mblk_t *bge_poll_ring(void *, int);
1186 1192 uint_t bge_chip_factotum(caddr_t arg);
1187 1193 void bge_chip_cyclic(void *arg);
1188 1194 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
1189 1195 struct iocblk *iocp);
1190 1196 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
1191 1197 void bge_sync_mac_modes(bge_t *);
1192 1198 extern uint32_t bge_rx_ticks_norm;
1193 1199 extern uint32_t bge_tx_ticks_norm;
1194 1200 extern uint32_t bge_rx_count_norm;
1195 1201 extern uint32_t bge_tx_count_norm;
1196 1202 extern boolean_t bge_relaxed_ordering;
1197 1203
1198 1204 void bge_chip_msi_trig(bge_t *bgep);
1199 1205
1200 1206 /* bge_kstats.c */
1201 1207 void bge_init_kstats(bge_t *bgep, int instance);
1202 1208 void bge_fini_kstats(bge_t *bgep);
1203 1209 int bge_m_stat(void *arg, uint_t stat, uint64_t *val);
1204 1210 int bge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1205 1211
1206 1212 /* bge_log.c */
1207 1213 #if BGE_DEBUGGING
1208 1214 void (*bge_db(bge_t *bgep))(const char *fmt, ...);
1209 1215 void (*bge_gdb(void))(const char *fmt, ...);
1210 1216 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg);
1211 1217 void bge_dbg_enter(bge_t *bgep, const char *msg);
1212 1218 #endif /* BGE_DEBUGGING */
1213 1219 void bge_problem(bge_t *bgep, const char *fmt, ...);
1214 1220 void bge_log(bge_t *bgep, const char *fmt, ...);
1215 1221 void bge_error(bge_t *bgep, const char *fmt, ...);
1216 1222 void bge_fm_ereport(bge_t *bgep, char *detail);
1217 1223 extern kmutex_t bge_log_mutex[1];
1218 1224 extern uint32_t bge_debug;
1219 1225
1220 1226 /* bge_main.c */
1221 1227 int bge_restart(bge_t *bgep, boolean_t reset_phy);
1222 1228 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle);
1223 1229 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle);
1224 1230 void bge_init_rings(bge_t *bgep);
1225 1231 void bge_fini_rings(bge_t *bgep);
1226 1232 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp);
1227 1233 void bge_free_txbuf_arrays(send_ring_t *srp);
1228 1234 int bge_alloc_bufs(bge_t *bgep);
1229 1235 void bge_free_bufs(bge_t *bgep);
1230 1236 void bge_intr_enable(bge_t *bgep);
1231 1237 void bge_intr_disable(bge_t *bgep);
1232 1238 int bge_reprogram(bge_t *);
1233 1239
1234 1240 /* bge_phys.c */
1235 1241 int bge_phys_init(bge_t *bgep);
1236 1242 void bge_phys_reset(bge_t *bgep);
1237 1243 int bge_phys_idle(bge_t *bgep);
1238 1244 int bge_phys_update(bge_t *bgep);
1239 1245 boolean_t bge_phys_check(bge_t *bgep);
1240 1246
1241 1247 /* bge_ndd.c */
1242 1248 int bge_nd_init(bge_t *bgep);
1243 1249
1244 1250 /* bge_recv.c */
1245 1251 void bge_receive(bge_t *bgep, bge_status_t *bsp);
1246 1252
1247 1253 /* bge_send.c */
1248 1254 mblk_t *bge_m_tx(void *arg, mblk_t *mp);
1249 1255 mblk_t *bge_ring_tx(void *arg, mblk_t *mp);
1250 1256 boolean_t bge_recycle(bge_t *bgep, bge_status_t *bsp);
1251 1257 uint_t bge_send_drain(caddr_t arg);
1252 1258
1253 1259 /* bge_atomic.c */
1254 1260 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n);
1255 1261 void bge_atomic_renounce(uint64_t *count_p, uint64_t n);
1256 1262 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit);
1257 1263 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit);
1258 1264 void bge_atomic_sub64(uint64_t *count_p, uint64_t n);
1259 1265 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits);
1260 1266 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count);
1261 1267
1262 1268 /* bge_mii_5906.c */
1263 1269 void bge_adj_volt_5906(bge_t *bgep);
1264 1270
1265 1271 /*
1266 1272 * Reset type
1267 1273 */
1268 1274 #define BGE_SHUTDOWN_RESET 0
1269 1275 #define BGE_INIT_RESET 1
1270 1276 #define BGE_SUSPEND_RESET 2
1271 1277
1272 1278 /* For asf_status */
1273 1279 #define ASF_STAT_NONE 0
1274 1280 #define ASF_STAT_STOP 1
1275 1281 #define ASF_STAT_RUN 2
1276 1282 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */
1277 1283
1278 1284 /* ASF modes for bge_reset() and bge_chip_reset() */
1279 1285 #define ASF_MODE_NONE 0 /* don't launch asf */
1280 1286 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */
1281 1287 #define ASF_MODE_INIT 2 /* asf init mode */
1282 1288 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */
1283 1289 #define ASF_MODE_POST_INIT 4 /* only do post-init */
1284 1290
1285 1291 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000
1286 1292
1287 1293 #define BGE_LINK_UPDATE_TIMEOUT 10 /* ~ 5 sec */
1288 1294 #define BGE_LINK_UPDATE_DONE (BGE_LINK_UPDATE_TIMEOUT+1)
1289 1295
1290 1296 #ifdef __cplusplus
1291 1297 }
1292 1298 #endif
1293 1299
1294 1300 #endif /* _BGE_IMPL_H */
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