1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #ifndef _BGE_IMPL_H
31 #define _BGE_IMPL_H
32
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 #include <sys/types.h>
39 #include <sys/stream.h>
40 #include <sys/strsun.h>
41 #include <sys/strsubr.h>
42 #include <sys/stat.h>
43 #include <sys/pci.h>
44 #include <sys/note.h>
45 #include <sys/modctl.h>
46 #include <sys/crc32.h>
47 #ifdef __sparcv9
48 #include <v9/sys/membar.h>
49 #endif /* __sparcv9 */
50 #include <sys/kstat.h>
51 #include <sys/ethernet.h>
52 #include <sys/vlan.h>
53 #include <sys/errno.h>
54 #include <sys/dlpi.h>
55 #include <sys/devops.h>
56 #include <sys/debug.h>
57 #include <sys/conf.h>
58
59 #include <netinet/ip6.h>
60
61 #include <inet/common.h>
62 #include <inet/ip.h>
63 #include <inet/mi.h>
64 #include <inet/nd.h>
65 #include <sys/pattr.h>
66
67 #include <sys/disp.h>
68 #include <sys/cmn_err.h>
69 #include <sys/ddi.h>
70 #include <sys/sunddi.h>
71
72 #include <sys/ddifm.h>
73 #include <sys/fm/protocol.h>
74 #include <sys/fm/util.h>
75 #include <sys/fm/io/ddi.h>
76
77 #include <sys/mac_provider.h>
78 #include <sys/mac_ether.h>
79
80 #ifdef __amd64
81 #include <sys/x86_archext.h>
82 #endif
83
84 /*
85 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t;
86 * but of course C doesn't provide a way to check this directly. So here
87 * we rely on the fact that the symbol ETHERTYPE_AT was added to the
88 * header file (as a #define, which we *can* test for) at the same time
89 * as the typedef for ether_addr_t ;-!
90 */
91 #ifndef ETHERTYPE_AT
92 typedef uchar_t ether_addr_t[ETHERADDRL];
93 #endif /* ETHERTYPE_AT */
94
95 /*
96 * Reconfiguring the network devices requires the net_config privilege
97 * in Solaris 10+.
98 */
99 extern int secpolicy_net_config(const cred_t *, boolean_t);
100
101 #include <sys/netlb.h> /* originally from cassini */
102 #include <sys/miiregs.h> /* by fjlite out of intel */
103
104 #include "bge.h"
105 #include "bge_hw.h"
106
107 /*
108 * Compile-time feature switches ...
109 */
110 #define BGE_DO_PPIO 0 /* peek/poke ioctls */
111 #define BGE_RX_SOFTINT 0 /* softint per receive ring */
112 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */
113
114 /*
115 * NOTES:
116 *
117 * #defines:
118 *
119 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the
120 * register-set numbers to use for the config space registers
121 * and the operating registers respectively. On an OBP-based
122 * machine, regset 0 refers to CONFIG space, and regset 1 will
123 * be the operating registers in MEMORY space. If an expansion
124 * ROM is fitted, it may appear as a further register set.
125 *
126 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used
127 * for the data buffers. The descriptors are always set up
128 * in CONSISTENT mode.
129 *
130 * BGE_HEADROOM defines how much space we'll leave in allocated
131 * mblks before the first valid data byte. This should be chosen
132 * to be 2 modulo 4, so that once the ethernet header (14 bytes)
133 * has been stripped off, the packet data will be 4-byte aligned.
134 * The remaining space can be used by upstream modules to prepend
135 * any headers required.
136 */
137
138 #define BGE_PCI_CONFIG_RNUMBER 0
139 #define BGE_PCI_OPREGS_RNUMBER 1
140 #define BGE_DMA_MODE DDI_DMA_STREAMING
141 #define BGE_HEADROOM 34
142
143 /*
144 * BGE_HALFTICK is half the period of the cyclic callback (in
145 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s.
146 * Other time values are derived as odd multiples of this value
147 * so that there's little chance of ambiguity w.r.t. which tick
148 * a timeout expires on.
149 *
150 * BGE_PHY_STABLE_TIME is the period for which the contents of the
151 * PHY's status register must remain unchanging before we accept
152 * that the link has come up. [Sometimes the link comes up, only
153 * to go down again within a short time as the autonegotiation
154 * process cycles through various options before finding the best
155 * compatible mode. We don't want to report repeated link up/down
156 * cycles, so we wait until we think it's stable.]
157 *
158 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes
159 * interface. It's much shorter, 'cos the SerDes doesn't show
160 * these effects as much as the copper PHY.
161 *
162 * BGE_LINK_SETTLE_TIME is the period during which we regard link
163 * up/down cycles as an normal event after resetting/reprogramming
164 * the PHY. During this time, link up/down messages are sent to
165 * the log only, not the console. At any other time, link change
166 * events are regarded as unexpected and sent to both console & log.
167 *
168 * These latter two values have no theoretical justification, but
169 * are derived from observations and heuristics - the values below
170 * just seem to work quite well.
171 */
172
173 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */
174 #define BGE_CYCLIC_PERIOD (4*BGE_HALFTICK) /* ~1.0s */
175 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */
176 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */
177 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */
178
179 /*
180 * Indices used to identify the different buffer rings internally
181 */
182 #define BGE_STD_BUFF_RING 0
183 #define BGE_JUMBO_BUFF_RING 1
184 #define BGE_MINI_BUFF_RING 2
185
186 /*
187 * Current implementation limits
188 */
189 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */
190 /* for now */
191 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */
192 /* for now */
193 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */
194 /* for now */
195 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */
196
197 /*
198 * Ring/buffer size parameters
199 *
200 * All of the (up to) 16 TX rings & and the corresponding buffers are the
201 * same size.
202 *
203 * Each of the (up to) 3 receive producer (aka buffer) rings is a different
204 * size and has different sized buffers associated with it too.
205 *
206 * The (up to) 16 receive return rings have no buffers associated with them.
207 * The number of slots per receive return ring must be 2048 if the mini
208 * ring is enabled, otherwise it may be 1024. See Broadcom document
209 * 570X-PG102-R page 56.
210 *
211 * Note: only the 5700 supported external memory (and therefore the mini
212 * ring); the 5702/3/4 don't. This driver doesn't support the original
213 * 5700, so we won't ever use the mini ring capability.
214 */
215
216 #define BGE_SEND_RINGS_DEFAULT 1
217 #define BGE_RECV_RINGS_DEFAULT 1
218
219 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536
220 #define BGE_SEND_BUFF_SIZE_JUMBO 9022
221 #define BGE_SEND_SLOTS_USED 512
222
223 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */
224 #define BGE_STD_SLOTS_USED 512
225
226 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */
227 #define BGE_JUMBO_SLOTS_USED 256
228
229 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */
230 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */
231
232 #define BGE_RECV_BUFF_SIZE 0
233 #if BGE_MINI_SLOTS_USED > 0
234 #define BGE_RECV_SLOTS_USED 2048 /* required */
235 #else
236 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */
237 #endif
238
239 #define BGE_SEND_BUF_NUM 512
240 #define BGE_SEND_BUF_ARRAY 16
241 #define BGE_SEND_BUF_ARRAY_JUMBO 3
242 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY)
243
244 /*
245 * PCI type. PCI-Express or PCI/PCIX
246 */
247 #define BGE_PCI 0
248 #define BGE_PCI_E 1
249 #define BGE_PCI_X 2
250
251 /*
252 * Statistic type. There are two type of statistic:
253 * statistic block and statistic registers
254 */
255 #define BGE_STAT_BLK 1
256 #define BGE_STAT_REG 2
257
258 /*
259 * MTU.for all chipsets ,the default is 1500 ,and some chipsets
260 * support 9k jumbo frames size
261 */
262 #define BGE_DEFAULT_MTU 1500
263 #define BGE_MAXIMUM_MTU 9000
264
265 /*
266 * Pad the h/w defined status block (which can be up to 80 bytes long)
267 * to a power-of-two boundary
268 */
269 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t))
270
271 /*
272 * On platforms which support DVMA, we can simply allocate one big piece
273 * of memory for all the Tx buffers and another for the Rx buffers, and
274 * then carve them up as required. It doesn't matter if they aren't just
275 * one physically contiguous piece each, because both the CPU *and* the
276 * I/O device can see them *as though they were*.
277 *
278 * However, if only physically-addressed DMA is possible, this doesn't
279 * work; we can't expect to get enough contiguously-addressed memory for
280 * all the buffers of each type, so in this case we request a number of
281 * smaller pieces, each still large enough for several buffers but small
282 * enough to fit within "an I/O page" (e.g. 64K).
283 *
284 * The #define below specifies how many pieces of memory are to be used;
285 * 16 has been shown to work on an i86pc architecture but this could be
286 * different on other non-DVMA platforms ...
287 */
288 #ifdef _DMA_USES_VIRTADDR
289 #define BGE_SPLIT 1 /* no split required */
290 #else
291 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \
292 (BGE_RECV_RINGS_USED > 1))
293 #define BGE_SPLIT 128 /* split 128 ways */
294 #else
295 #define BGE_SPLIT 16 /* split 16 ways */
296 #endif
297 #endif /* _DMA_USES_VIRTADDR */
298
299 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1)
300
301 /*
302 * STREAMS parameters
303 */
304 #define BGE_IDNUM 0 /* zero seems to work */
305 #define BGE_LOWAT (256)
306 #define BGE_HIWAT (256*1024)
307
308
309 /*
310 * Basic data types, for clarity in distinguishing 'numbers'
311 * used for different purposes ...
312 *
313 * A <bge_regno_t> is a register 'address' (offset) in any one of
314 * various address spaces (PCI config space, PCI memory-mapped I/O
315 * register space, MII registers, etc). None of these exceeds 64K,
316 * so we could use a 16-bit representation but pointer-sized objects
317 * are more "natural" in most architectures; they seem to be handled
318 * more efficiently on SPARC and no worse on x86.
319 *
320 * BGE_REGNO_NONE represents the non-existent value in this space.
321 */
322 typedef uintptr_t bge_regno_t; /* register # (offset) */
323 #define BGE_REGNO_NONE (~(uintptr_t)0u)
324
325 /*
326 * Describes one chunk of allocated DMA-able memory
327 *
328 * In some cases, this is a single chunk as allocated from the system;
329 * but we also use this structure to represent slices carved off such
330 * a chunk. Even when we don't really need all the information, we
331 * use this structure as a convenient way of correlating the various
332 * ways of looking at a piece of memory (kernel VA, IO space DVMA,
333 * handle+offset, etc).
334 */
335 typedef struct {
336 ddi_acc_handle_t acc_hdl; /* handle for memory */
337 void *mem_va; /* CPU VA of memory */
338 uint32_t nslots; /* number of slots */
339 uint32_t size; /* size per slot */
340 size_t alength; /* allocated size */
341 /* >= product of above */
342
343 ddi_dma_handle_t dma_hdl; /* DMA handle */
344 offset_t offset; /* relative to handle */
345 ddi_dma_cookie_t cookie; /* associated cookie */
346 uint32_t ncookies; /* must be 1 */
347 uint32_t token; /* arbitrary identifier */
348 } dma_area_t; /* 0x50 (80) bytes */
349
350 typedef struct bge_queue_item {
351 struct bge_queue_item *next;
352 void *item;
353 } bge_queue_item_t;
354
355 typedef struct bge_queue {
356 bge_queue_item_t *head;
357 uint32_t count;
358 kmutex_t *lock;
359 } bge_queue_t;
360 /*
361 * Software version of the Receive Buffer Descriptor
362 * There's one of these for each receive buffer (up to 256/512/1024 per ring).
363 */
364 typedef struct sw_rbd {
365 dma_area_t pbuf; /* (const) related */
366 /* buffer area */
367 } sw_rbd_t; /* 0x50 (80) bytes */
368
369 /*
370 * Software Receive Buffer (Producer) Ring Control Block
371 * There's one of these for each receiver producer ring (up to 3),
372 * but each holds buffers of a different size.
373 */
374 typedef struct buff_ring {
375 dma_area_t desc; /* (const) related h/w */
376 /* descriptor area */
377 dma_area_t buf[BGE_SPLIT]; /* (const) related */
378 /* buffer area(s) */
379 bge_rcb_t hw_rcb; /* (const) image of h/w */
380 /* RCB, and used to */
381 struct bge *bgep; /* (const) containing */
382 /* driver soft state */
383 /* initialise same */
384 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
385 /* "consumer index" */
386 /* (in status block) */
387
388 /*
389 * The rf_lock must be held when updating the h/w producer index
390 * mailbox register (*chip_mbox_reg), or the s/w producer index
391 * (rf_next).
392 */
393 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
394 /* index mailbox offset */
395 kmutex_t rf_lock[1]; /* serialize refill */
396 uint64_t rf_next; /* next slot to refill */
397 /* ("producer index") */
398
399 sw_rbd_t *sw_rbds; /* software descriptors */
400 void *spare[4]; /* padding */
401 } buff_ring_t; /* 0x100 (256) bytes */
402
403 typedef struct bge_multi_mac {
404 int naddr; /* total supported addresses */
405 int naddrfree; /* free addresses slots */
406 ether_addr_t mac_addr[MAC_ADDRESS_REGS_MAX];
407 boolean_t mac_addr_set[MAC_ADDRESS_REGS_MAX];
408 } bge_multi_mac_t;
409
410 /*
411 * Software Receive (Return) Ring Control Block
412 * There's one of these for each receiver return ring (up to 16).
413 */
414 typedef struct recv_ring {
415 /*
416 * The elements flagged (const) in the comments below are
417 * set up once during initialiation and thereafter unchanged.
418 */
419 dma_area_t desc; /* (const) related h/w */
420 /* descriptor area */
421 bge_rcb_t hw_rcb; /* (const) image of h/w */
422 /* RCB, and used to */
423 /* initialise same */
424 struct bge *bgep; /* (const) containing */
425 /* driver soft state */
426 ddi_softintr_t rx_softint; /* (const) per-ring */
427 /* receive callback */
428 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */
429 /* "producer index" */
430 /* (in status block) */
431 /*
432 * The rx_lock must be held when updating the h/w consumer index
433 * mailbox register (*chip_mbox_reg), or the s/w consumer index
434 * (rx_next).
435 */
436 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */
437 /* index mailbox offset */
438 kmutex_t rx_lock[1]; /* serialize receive */
439 uint64_t rx_next; /* next slot to examine */
440
441 mac_ring_handle_t ring_handle;
442 mac_group_handle_t ring_group_handle;
443 uint64_t ring_gen_num;
444 bge_rule_info_t *mac_addr_rule;
445 uint8_t mac_addr_val[ETHERADDRL];
446 int poll_flag; /* Polling flag */
447
448 /* Per-ring statistics */
449 uint64_t rx_pkts; /* Received Packets Count */
450 uint64_t rx_bytes; /* Received Bytes Count */
451 } recv_ring_t;
452
453
454 /*
455 * Send packet structure
456 */
457 typedef struct send_pkt {
458 uint16_t vlan_tci;
459 uint32_t pflags;
460 boolean_t tx_ready;
461 bge_queue_item_t *txbuf_item;
462 } send_pkt_t;
463
464 /*
465 * Software version of tx buffer structure
466 */
467 typedef struct sw_txbuf {
468 dma_area_t buf;
469 uint32_t copy_len;
470 } sw_txbuf_t;
471
472 /*
473 * Software version of the Send Buffer Descriptor
474 * There's one of these for each send buffer (up to 512 per ring)
475 */
476 typedef struct sw_sbd {
477 dma_area_t desc; /* (const) related h/w */
478 /* descriptor area */
479 bge_queue_item_t *pbuf; /* (const) related */
480 /* buffer area */
481 } sw_sbd_t;
482
483 /*
484 * Software Send Ring Control Block
485 * There's one of these for each of (up to) 16 send rings
486 */
487 typedef struct send_ring {
488 /*
489 * The elements flagged (const) in the comments below are
490 * set up once during initialiation and thereafter unchanged.
491 */
492 dma_area_t desc; /* (const) related h/w */
493 /* descriptor area */
494 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT];
495 /* buffer area(s) */
496 bge_rcb_t hw_rcb; /* (const) image of h/w */
497 /* RCB, and used to */
498 /* initialise same */
499 struct bge *bgep; /* (const) containing */
500 /* driver soft state */
501 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
502 /* "consumer index" */
503 /* (in status block) */
504
505 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
506 /* index mailbox offset */
507 /*
508 * Tx buffer queue
509 */
510 bge_queue_t txbuf_queue;
511 bge_queue_t freetxbuf_queue;
512 bge_queue_t *txbuf_push_queue;
513 bge_queue_t *txbuf_pop_queue;
514 kmutex_t txbuf_lock[1];
515 kmutex_t freetxbuf_lock[1];
516 bge_queue_item_t *txbuf_head;
517 send_pkt_t *pktp;
518 uint64_t txpkt_next;
519 uint64_t txfill_next;
520 sw_txbuf_t *txbuf;
521 uint32_t tx_buffers;
522 uint32_t tx_buffers_low;
523 uint32_t tx_array_max;
524 uint32_t tx_array;
525 kmutex_t tx_lock[1]; /* serialize h/w update */
526 /* ("producer index") */
527 uint64_t tx_next; /* next slot to use */
528 uint64_t tx_flow; /* # concurrent sends */
529 uint64_t tx_block;
530 uint64_t tx_nobd;
531 uint64_t tx_nobuf;
532 uint64_t tx_alloc_fail;
533
534 /*
535 * These counters/indexes are manipulated in the transmit
536 * path using atomics rather than mutexes for speed
537 */
538 uint64_t tx_free; /* # of slots available */
539
540 /*
541 * The tc_lock must be held while manipulating the s/w consumer
542 * index (tc_next).
543 */
544 kmutex_t tc_lock[1]; /* serialize recycle */
545 uint64_t tc_next; /* next slot to recycle */
546 /* ("consumer index") */
547
548 sw_sbd_t *sw_sbds; /* software descriptors */
549 uint64_t mac_resid; /* special per resource id */
550 uint64_t pushed_bytes;
551 } send_ring_t; /* 0x100 (256) bytes */
552
553 typedef struct {
554 ether_addr_t addr; /* in canonical form */
555 uint8_t spare;
556 boolean_t set; /* B_TRUE => valid */
557 } bge_mac_addr_t;
558
559 /*
560 * The original 5700/01 supported only SEEPROMs. Later chips (5702+)
561 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for
562 * the hardware and a backwards-compatible software access method), and
563 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus
564 * and using a new software access method.
565 *
566 * The access methods for SEEPROM and Flash are generally similar, with
567 * the chip handling the serialisation/deserialisation and handshaking,
568 * but the registers used are different, as are a few details of the
569 * protocol, and the timing, so we have to determine which (if any) is
570 * fitted.
571 *
572 * The value UNKNOWN means just that; we haven't yet tried to determine
573 * the device type.
574 *
575 * The value NONE can indicate either that a real and definite absence of
576 * any NVmem has been detected, or that there may be NVmem but we can't
577 * determine its type, perhaps because the NVconfig pins on the chip have
578 * been wired up incorrectly. In either case, access to the NVmem (if any)
579 * is not supported.
580 */
581 enum bge_nvmem_type {
582 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */
583 BGE_NVTYPE_UNKNOWN, /* not yet checked */
584 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */
585 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */
586 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */
587 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */
588 };
589
590 /*
591 * Describes the characteristics of a specific chip
592 *
593 * Note: elements from <businfo> to <latency> are filled in by during
594 * the first phase of chip initialisation (see bge_chip_cfg_init()).
595 * The remaining ones are determined just after the first RESET, in
596 * bge_poll_firmware(). Thereafter, the entire structure is readonly.
597 */
598 typedef struct {
599 uint32_t asic_rev; /* masked from MHCR */
600 uint32_t businfo; /* from private reg */
601 uint16_t command; /* saved during attach */
602
603 uint16_t vendor; /* vendor-id */
604 uint16_t device; /* device-id */
605 uint16_t subven; /* subsystem-vendor-id */
606 uint16_t subdev; /* subsystem-id */
607 uint8_t revision; /* revision-id */
608 uint8_t clsize; /* cache-line-size */
609 uint8_t latency; /* latency-timer */
610
611 uint8_t flags;
612 uint32_t chip_type; /* see CHIP_TYPE_ in bge_hw.h */
613 uint16_t chip_label; /* numeric part only */
614 /* (e.g. 5703/5794/etc) */
615 uint32_t mbuf_base; /* Mbuf pool parameters */
616 uint32_t mbuf_length; /* depend on chiptype */
617 uint32_t pci_type;
618 uint32_t statistic_type;
619 uint32_t bge_dma_rwctrl;
620 uint32_t bge_mlcr_default;
621 uint32_t recv_slots; /* receive ring size */
622 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */
623
624 uint16_t jumbo_slots;
625 uint16_t ethmax_size;
626 uint16_t snd_buff_size;
627 uint16_t recv_jumbo_size;
628 uint16_t std_buf_size;
629 uint32_t mbuf_hi_water;
630 uint32_t mbuf_lo_water_rmac;
631 uint32_t mbuf_lo_water_rdma;
632
633 uint32_t rx_rings; /* from bge.conf */
634 uint32_t tx_rings; /* from bge.conf */
635 uint32_t default_mtu; /* from bge.conf */
636
637 uint64_t hw_mac_addr; /* from chip register */
638 bge_mac_addr_t vendor_addr; /* transform of same */
639 boolean_t msi_enabled; /* default to true */
640
641 uint32_t rx_ticks_norm;
642 uint32_t rx_count_norm;
643 uint32_t tx_ticks_norm;
644 uint32_t tx_count_norm;
645 uint32_t mask_pci_int;
646 } chip_id_t;
647
648 #define CHIP_FLAG_SUPPORTED 0x80
649 #define CHIP_FLAG_SERDES 0x40
650 #define CHIP_FLAG_PARTIAL_CSUM 0x20
651 #define CHIP_FLAG_NO_CHECK_RESET 0x2
652 #define CHIP_FLAG_NO_JUMBO 0x1
653
654 /*
655 * Collection of physical-layer functions to:
656 * (re)initialise the physical layer
657 * update it to match software settings
658 * check for link status change
659 */
660 typedef struct {
661 int (*phys_restart)(struct bge *, boolean_t);
662 int (*phys_update)(struct bge *);
663 boolean_t (*phys_check)(struct bge *, boolean_t);
664 } phys_ops_t;
665
666
667 /*
668 * Actual state of the BCM570x chip
669 */
670 enum bge_chip_state {
671 BGE_CHIP_FAULT = -2, /* fault, need reset */
672 BGE_CHIP_ERROR, /* error, want reset */
673 BGE_CHIP_INITIAL, /* Initial state only */
674 BGE_CHIP_RESET, /* reset, need init */
675 BGE_CHIP_STOPPED, /* Tx/Rx stopped */
676 BGE_CHIP_RUNNING /* with interrupts */
677 };
678
679 enum bge_mac_state {
680 BGE_MAC_STOPPED = 0,
681 BGE_MAC_STARTED
682 };
683
684 /*
685 * (Internal) return values from ioctl subroutines
686 */
687 enum ioc_reply {
688 IOC_INVAL = -1, /* bad, NAK with EINVAL */
689 IOC_DONE, /* OK, reply sent */
690 IOC_ACK, /* OK, just send ACK */
691 IOC_REPLY, /* OK, just send reply */
692 IOC_RESTART_ACK, /* OK, restart & ACK */
693 IOC_RESTART_REPLY /* OK, restart & reply */
694 };
695
696 /*
697 * (Internal) return values from send_msg subroutines
698 */
699 enum send_status {
700 SEND_FAIL = -1, /* Not OK */
701 SEND_KEEP, /* OK, msg queued */
702 SEND_FREE /* OK, free msg */
703 };
704
705 /*
706 * (Internal) enumeration of this driver's kstats
707 */
708 enum {
709 BGE_KSTAT_RAW = 0,
710 BGE_KSTAT_STATS,
711 BGE_KSTAT_CHIPID,
712 BGE_KSTAT_DRIVER,
713 BGE_KSTAT_PHYS,
714
715 BGE_KSTAT_COUNT
716 };
717
718 #define BGE_MAX_RESOURCES 255
719
720 /*
721 * Per-instance soft-state structure
722 */
723 typedef struct bge {
724 /*
725 * These fields are set by attach() and unchanged thereafter ...
726 */
727 dev_info_t *devinfo; /* device instance */
728 mac_handle_t mh; /* mac module handle */
729 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */
730 ddi_acc_handle_t io_handle; /* DDI I/O handle */
731 void *io_regs; /* mapped registers */
732 ddi_periodic_t periodic_id; /* periodical callback */
733 ddi_softintr_t factotum_id; /* factotum callback */
734 ddi_softintr_t drain_id; /* reschedule callback */
735
736 ddi_intr_handle_t *htable; /* For array of interrupts */
737 int intr_type; /* What type of interrupt */
738 int intr_cnt; /* # of intrs count returned */
739 uint_t intr_pri; /* Interrupt priority */
740 int intr_cap; /* Interrupt capabilities */
741 uint32_t progress; /* attach tracking */
742 uint32_t debug; /* per-instance debug */
743 chip_id_t chipid;
744 const phys_ops_t *physops;
745 char ifname[8]; /* "bge0" ... "bge999" */
746
747 int fm_capabilities; /* FMA capabilities */
748
749 /*
750 * These structures describe the blocks of memory allocated during
751 * attach(). They remain unchanged thereafter, although the memory
752 * they describe is carved up into various separate regions and may
753 * therefore be described by other structures as well.
754 */
755 dma_area_t tx_desc; /* transmit descriptors */
756 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT];
757 /* receive descriptors */
758 dma_area_t tx_buff[BGE_SPLIT];
759 dma_area_t rx_buff[BGE_SPLIT];
760
761 /*
762 * The memory described by the <dma_area> structures above
763 * is carved up into various pieces, which are described by
764 * the structures below.
765 */
766 dma_area_t statistics; /* describes hardware */
767 /* statistics area */
768 dma_area_t status_block; /* describes hardware */
769 /* status block */
770 /*
771 * For the BCM5705/5788/5721/5751/5752/5714 and 5715,
772 * the statistic block is not available,the statistic counter must
773 * be gotten from statistic registers.And bge_statistics_reg_t record
774 * the statistic registers value
775 */
776 bge_statistics_reg_t *pstats;
777
778 /*
779 * Runtime read-write data starts here ...
780 *
781 * 3 Buffer Rings (std/jumbo/mini)
782 * 16 Receive (Return) Rings
783 * 16 Send Rings
784 *
785 * Note: they're not necessarily all used.
786 */
787 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */
788
789 /* may be obsoleted */
790 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */
791 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */
792
793 /*
794 * Locks:
795 *
796 * Each buffer ring contains its own <rf_lock> which regulates
797 * ring refilling.
798 *
799 * Each receive (return) ring contains its own <rx_lock> which
800 * protects the critical cyclic counters etc.
801 *
802 * Each send ring contains two locks: <tx_lock> for the send-path
803 * protocol data and <tc_lock> for send-buffer recycling.
804 *
805 * Finally <genlock> is a general lock, protecting most other
806 * operational data in the state structure and chip register
807 * accesses. It is acquired by the interrupt handler and
808 * most "mode-control" routines.
809 *
810 * Any of the locks can be acquired singly, but where multiple
811 * locks are acquired, they *must* be in the order:
812 *
813 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock.
814 *
815 * and within any one class of lock the rings must be locked in
816 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc.
817 *
818 * Note: actually I don't believe there's any need to acquire
819 * locks on multiple rings, or even locks of all these classes
820 * concurrently; but I've set out the above order so there is a
821 * clear definition of lock hierarchy in case it's ever needed.
822 *
823 * Note: the combinations of locks that are actually held
824 * concurrently are:
825 *
826 * genlock >>> (bge_chip_interrupt())
827 * rx_lock[i] >>> (bge_receive())
828 * rf_lock[n] (bge_refill())
829 * tc_lock[i] (bge_recycle())
830 */
831 kmutex_t genlock[1];
832 krwlock_t errlock[1];
833 kmutex_t softintrlock[1];
834
835 /*
836 * Current Ethernet addresses and multicast hash (bitmap) and
837 * refcount tables, protected by <genlock>
838 */
839 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX];
840 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32];
841 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE];
842 uint32_t unicst_addr_total; /* total unicst addresses */
843 uint32_t unicst_addr_avail;
844 /* unused unicst addr slots */
845
846 /*
847 * Link state data (protected by genlock)
848 */
849 link_state_t link_state;
850
851 /*
852 * Physical layer: copper only
853 */
854 bge_regno_t phy_mii_addr; /* should be (const) 1! */
855 uint16_t phy_gen_status;
856 uint16_t phy_aux_status;
857
858 /*
859 * Physical layer: serdes only
860 */
861 uint32_t serdes_status;
862 uint32_t serdes_advert;
863 uint32_t serdes_lpadv;
864
865 /*
866 * Driver kstats, protected by <genlock> where necessary
867 */
868 kstat_t *bge_kstats[BGE_KSTAT_COUNT];
869
870 /*
871 * Miscellaneous operating variables (protected by genlock)
872 */
873 uint64_t chip_resets; /* # of chip RESETs */
874 uint64_t missed_dmas; /* # of missed DMAs */
875 uint64_t missed_updates; /* # of missed updates */
876 enum bge_mac_state bge_mac_state; /* definitions above */
877 enum bge_chip_state bge_chip_state; /* definitions above */
878 boolean_t send_hw_tcp_csum;
879 boolean_t recv_hw_tcp_csum;
880 boolean_t promisc;
881 boolean_t manual_reset;
882
883 /*
884 * Miscellaneous operating variables (not synchronised)
885 */
886 uint32_t watchdog; /* watches for Tx stall */
887 boolean_t bge_intr_running;
888 boolean_t bge_dma_error;
889 boolean_t tx_resched_needed;
890 uint64_t tx_resched;
891 uint32_t factotum_flag; /* softint pending */
892 uintptr_t pagemask;
893
894 /*
895 * NDD parameters (protected by genlock)
896 */
897 caddr_t nd_data_p;
898
899 /*
900 * A flag to prevent excessive config space accesses
901 * on platforms having BCM5714C/15C
902 */
903 boolean_t lastWriteZeroData;
904
905 /*
906 * Spare space, plus guard element used to check data integrity
907 */
908 uint64_t spare[5];
909 uint64_t bge_guard;
910
911 /*
912 * Receive rules configure
913 */
914 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX];
915
916 #ifdef BGE_IPMI_ASF
917 boolean_t asf_enabled;
918 boolean_t asf_wordswapped;
919 boolean_t asf_newhandshake;
920 boolean_t asf_pseudostop;
921
922 uint32_t asf_status;
923 timeout_id_t asf_timeout_id;
924 #endif
925 uint32_t param_en_pause:1,
926 param_en_asym_pause:1,
927 param_en_1000hdx:1,
928 param_en_1000fdx:1,
929 param_en_100fdx:1,
930 param_en_100hdx:1,
931 param_en_10fdx:1,
932 param_en_10hdx:1,
933 param_adv_autoneg:1,
934 param_adv_1000fdx:1,
935 param_adv_1000hdx:1,
936 param_adv_100fdx:1,
937 param_adv_100hdx:1,
938 param_adv_10fdx:1,
939 param_adv_10hdx:1,
940 param_lp_autoneg:1,
941 param_lp_pause:1,
942 param_lp_asym_pause:1,
943 param_lp_1000fdx:1,
944 param_lp_1000hdx:1,
945 param_lp_100fdx:1,
946 param_lp_100hdx:1,
947 param_lp_10fdx:1,
948 param_lp_10hdx:1,
949 param_link_up:1,
950 param_link_autoneg:1,
951 param_adv_pause:1,
952 param_adv_asym_pause:1,
953 param_link_rx_pause:1,
954 param_link_tx_pause:1,
955 param_pad_to_32:2;
956
957 uint32_t param_loop_mode;
958 uint32_t param_msi_cnt;
959 uint32_t param_drain_max;
960 uint64_t param_link_speed;
961 link_duplex_t param_link_duplex;
962
963
964 uint32_t link_update_timer;
965 uint64_t timestamp;
966 } bge_t;
967
968 /*
969 * 'Progress' bit flags ...
970 */
971 #define PROGRESS_CFG 0x0001 /* config space mapped */
972 #define PROGRESS_REGS 0x0002 /* registers mapped */
973 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */
974 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */
975 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */
976 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */
977 /* and mutexen initialised */
978 #define PROGRESS_INTR 0x0080 /* Intrs enabled */
979 #define PROGRESS_PHY 0x0100 /* PHY initialised */
980 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */
981 #define PROGRESS_KSTATS 0x2000 /* kstats created */
982 #define PROGRESS_READY 0x8000 /* ready for work */
983
984
985 /*
986 * Sync a DMA area described by a dma_area_t
987 */
988 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \
989 (area).offset, (area).alength, (flag)))
990
991 /*
992 * Find the (kernel virtual) address of block of memory
993 * described by a dma_area_t
994 */
995 #define DMA_VPTR(area) ((area).mem_va)
996
997 /*
998 * Zero a block of memory described by a dma_area_t
999 */
1000 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength)
1001
1002 /*
1003 * Next value of a cyclic index
1004 */
1005 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0)
1006
1007 /*
1008 * Property lookups
1009 */
1010 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
1011 DDI_PROP_DONTPASS, (n))
1012 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
1013 DDI_PROP_DONTPASS, (n), -1)
1014
1015 /*
1016 * Copy an ethernet address
1017 */
1018 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL)
1019
1020 /*
1021 * Endian swap
1022 */
1023 /* BEGIN CSTYLED */
1024 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \
1025 (((x) & 0x00ff0000) >> 8) | \
1026 (((x) & 0x0000ff00) << 8) | \
1027 (((x) & 0x000000ff) << 24))
1028 /* END CSTYLED */
1029
1030 /*
1031 * Marker value placed at the end of the driver's state
1032 */
1033 #define BGE_GUARD 0x1919306009031802
1034
1035 /*
1036 * Bit flags in the 'debug' word ...
1037 */
1038 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */
1039 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */
1040
1041 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */
1042 #define BGE_DBG_MII 0x00000020 /* low-level MII access */
1043 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */
1044 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */
1045
1046 #define BGE_DBG_RECV 0x00000100 /* receive-side code */
1047 #define BGE_DBG_SEND 0x00000200 /* packet-send code */
1048
1049 #define BGE_DBG_INT 0x00001000 /* interrupt handler */
1050 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */
1051
1052 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */
1053 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */
1054 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */
1055 #define BGE_DBG_LINK 0x00080000 /* Link status check */
1056
1057 #define BGE_DBG_INIT 0x00100000 /* initialisation */
1058 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */
1059 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */
1060 #define BGE_DBG_STATS 0x00800000 /* statistics */
1061
1062 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */
1063 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */
1064 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */
1065 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */
1066
1067 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */
1068 #define BGE_DBG_NDD 0x20000000 /* NDD operations */
1069
1070 /*
1071 * Debugging ...
1072 */
1073 #ifdef DEBUG
1074 #define BGE_DEBUGGING 1
1075 #else
1076 #define BGE_DEBUGGING 0
1077 #endif /* DEBUG */
1078
1079
1080 /*
1081 * 'Do-if-debugging' macro. The parameter <command> should be one or more
1082 * C statements (but without the *final* semicolon), which will either be
1083 * compiled inline or completely ignored, depending on the BGE_DEBUGGING
1084 * compile-time flag.
1085 *
1086 * You should get a compile-time error (at least on a DEBUG build) if
1087 * your statement isn't actually a statement, rather than unexpected
1088 * run-time behaviour caused by unintended matching of if-then-elses etc.
1089 *
1090 * Note that the BGE_DDB() macro itself can only be used as a statement,
1091 * not an expression, and should always be followed by a semicolon.
1092 */
1093 #if BGE_DEBUGGING
1094 #define BGE_DDB(command) do { \
1095 { command; } \
1096 _NOTE(CONSTANTCONDITION) \
1097 } while (0)
1098 #else /* BGE_DEBUGGING */
1099 #define BGE_DDB(command) do { \
1100 { _NOTE(EMPTY); } \
1101 _NOTE(CONSTANTCONDITION) \
1102 } while (0)
1103 #endif /* BGE_DEBUGGING */
1104
1105 /*
1106 * 'Internal' macros used to construct the TRACE/DEBUG macros below.
1107 * These provide the primitive conditional-call capability required.
1108 * Note: the parameter <args> is a parenthesised list of the actual
1109 * printf-style arguments to be passed to the debug function ...
1110 */
1111 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args)
1112 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args)
1113 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args)
1114 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args)
1115
1116 /*
1117 * Conditional-print macros.
1118 *
1119 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values
1120 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G'
1121 * versions look at the Global debug flag word (bge_debug); the non-G
1122 * versions look in the per-instance data (bgep->debug) and so require a
1123 * variable called 'bgep' to be in scope (and initialised!) before use.
1124 *
1125 * You could redefine BGE_TRC too if you really need two different
1126 * flavours of debugging output in the same area of code, but I don't
1127 * really recommend it.
1128 *
1129 * Note: the parameter <args> is a parenthesised list of the actual
1130 * arguments to be passed to the debug function, usually a printf-style
1131 * format string and corresponding values to be formatted.
1132 */
1133
1134 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */
1135 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args)
1136 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args)
1137 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args)
1138 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args)
1139
1140 /*
1141 * Debug-only action macros
1142 */
1143 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s))
1144 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep))
1145 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep))
1146 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args)
1147 #define BGE_REPORT(args) BGE_DDB(bge_log args)
1148
1149 /*
1150 * Inter-source-file linkage ...
1151 */
1152
1153 /* bge_chip.c */
1154 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1155 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value);
1156 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
1157 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value);
1158 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1159 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1160 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value);
1161 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
1162 int bge_chip_id_init(bge_t *bgep);
1163 void bge_chip_coalesce_update(bge_t *bgep);
1164 int bge_chip_start(bge_t *bgep, boolean_t reset_phy);
1165 void bge_chip_stop(bge_t *bgep, boolean_t fault);
1166 #ifndef __sparc
1167 void bge_chip_stop_nonblocking(bge_t *bgep);
1168 #endif
1169 #ifdef BGE_IPMI_ASF
1170 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
1171 #pragma inline(bge_nic_put32)
1172 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr);
1173 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
1174 #pragma inline(bge_ind_put32)
1175 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
1176 #pragma inline(bge_ind_get32)
1177 void bge_asf_update_status(bge_t *bgep);
1178 void bge_asf_heartbeat(void *bgep);
1179 void bge_asf_stop_timer(bge_t *bgep);
1180 void bge_asf_get_config(bge_t *bgep);
1181 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode);
1182 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode);
1183 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode);
1184 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
1185 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
1186 #else
1187 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
1188 int bge_chip_sync(bge_t *bgep);
1189 #endif
1190 void bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag);
1191 extern mblk_t *bge_poll_ring(void *, int);
1192 uint_t bge_chip_factotum(caddr_t arg);
1193 void bge_chip_cyclic(void *arg);
1194 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
1195 struct iocblk *iocp);
1196 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
1197 void bge_sync_mac_modes(bge_t *);
1198 extern uint32_t bge_rx_ticks_norm;
1199 extern uint32_t bge_tx_ticks_norm;
1200 extern uint32_t bge_rx_count_norm;
1201 extern uint32_t bge_tx_count_norm;
1202 extern boolean_t bge_relaxed_ordering;
1203
1204 void bge_chip_msi_trig(bge_t *bgep);
1205
1206 /* bge_kstats.c */
1207 void bge_init_kstats(bge_t *bgep, int instance);
1208 void bge_fini_kstats(bge_t *bgep);
1209 int bge_m_stat(void *arg, uint_t stat, uint64_t *val);
1210 int bge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1211
1212 /* bge_log.c */
1213 #if BGE_DEBUGGING
1214 void (*bge_db(bge_t *bgep))(const char *fmt, ...);
1215 void (*bge_gdb(void))(const char *fmt, ...);
1216 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg);
1217 void bge_dbg_enter(bge_t *bgep, const char *msg);
1218 #endif /* BGE_DEBUGGING */
1219 void bge_problem(bge_t *bgep, const char *fmt, ...);
1220 void bge_log(bge_t *bgep, const char *fmt, ...);
1221 void bge_error(bge_t *bgep, const char *fmt, ...);
1222 void bge_fm_ereport(bge_t *bgep, char *detail);
1223 extern kmutex_t bge_log_mutex[1];
1224 extern uint32_t bge_debug;
1225
1226 /* bge_main.c */
1227 int bge_restart(bge_t *bgep, boolean_t reset_phy);
1228 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle);
1229 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle);
1230 void bge_init_rings(bge_t *bgep);
1231 void bge_fini_rings(bge_t *bgep);
1232 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp);
1233 void bge_free_txbuf_arrays(send_ring_t *srp);
1234 int bge_alloc_bufs(bge_t *bgep);
1235 void bge_free_bufs(bge_t *bgep);
1236 void bge_intr_enable(bge_t *bgep);
1237 void bge_intr_disable(bge_t *bgep);
1238 int bge_reprogram(bge_t *);
1239
1240 /* bge_phys.c */
1241 int bge_phys_init(bge_t *bgep);
1242 void bge_phys_reset(bge_t *bgep);
1243 int bge_phys_idle(bge_t *bgep);
1244 int bge_phys_update(bge_t *bgep);
1245 boolean_t bge_phys_check(bge_t *bgep);
1246
1247 /* bge_ndd.c */
1248 int bge_nd_init(bge_t *bgep);
1249
1250 /* bge_recv.c */
1251 void bge_receive(bge_t *bgep, bge_status_t *bsp);
1252
1253 /* bge_send.c */
1254 mblk_t *bge_m_tx(void *arg, mblk_t *mp);
1255 mblk_t *bge_ring_tx(void *arg, mblk_t *mp);
1256 boolean_t bge_recycle(bge_t *bgep, bge_status_t *bsp);
1257 uint_t bge_send_drain(caddr_t arg);
1258
1259 /* bge_atomic.c */
1260 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n);
1261 void bge_atomic_renounce(uint64_t *count_p, uint64_t n);
1262 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit);
1263 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit);
1264 void bge_atomic_sub64(uint64_t *count_p, uint64_t n);
1265 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits);
1266 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count);
1267
1268 /* bge_mii_5906.c */
1269 void bge_adj_volt_5906(bge_t *bgep);
1270
1271 /*
1272 * Reset type
1273 */
1274 #define BGE_SHUTDOWN_RESET 0
1275 #define BGE_INIT_RESET 1
1276 #define BGE_SUSPEND_RESET 2
1277
1278 /* For asf_status */
1279 #define ASF_STAT_NONE 0
1280 #define ASF_STAT_STOP 1
1281 #define ASF_STAT_RUN 2
1282 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */
1283
1284 /* ASF modes for bge_reset() and bge_chip_reset() */
1285 #define ASF_MODE_NONE 0 /* don't launch asf */
1286 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */
1287 #define ASF_MODE_INIT 2 /* asf init mode */
1288 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */
1289 #define ASF_MODE_POST_INIT 4 /* only do post-init */
1290
1291 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000
1292
1293 #define BGE_LINK_UPDATE_TIMEOUT 10 /* ~ 5 sec */
1294 #define BGE_LINK_UPDATE_DONE (BGE_LINK_UPDATE_TIMEOUT+1)
1295
1296 #ifdef __cplusplus
1297 }
1298 #endif
1299
1300 #endif /* _BGE_IMPL_H */