1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #ifndef _BGE_IMPL_H
27 #define _BGE_IMPL_H
28
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 #include <sys/types.h>
35 #include <sys/stream.h>
36 #include <sys/strsun.h>
37 #include <sys/strsubr.h>
38 #include <sys/stat.h>
39 #include <sys/pci.h>
40 #include <sys/note.h>
41 #include <sys/modctl.h>
42 #include <sys/crc32.h>
43 #ifdef __sparcv9
44 #include <v9/sys/membar.h>
45 #endif /* __sparcv9 */
46 #include <sys/kstat.h>
47 #include <sys/ethernet.h>
48 #include <sys/vlan.h>
49 #include <sys/errno.h>
50 #include <sys/dlpi.h>
51 #include <sys/devops.h>
52 #include <sys/debug.h>
53 #include <sys/conf.h>
54
55 #include <netinet/ip6.h>
56
57 #include <inet/common.h>
58 #include <inet/ip.h>
59 #include <inet/mi.h>
60 #include <inet/nd.h>
61 #include <sys/pattr.h>
62
63 #include <sys/disp.h>
64 #include <sys/cmn_err.h>
65 #include <sys/ddi.h>
66 #include <sys/sunddi.h>
67
68 #include <sys/ddifm.h>
69 #include <sys/fm/protocol.h>
70 #include <sys/fm/util.h>
71 #include <sys/fm/io/ddi.h>
72
73 #include <sys/mac_provider.h>
74 #include <sys/mac_ether.h>
75
76 #ifdef __amd64
77 #include <sys/x86_archext.h>
78 #endif
79
80 /*
81 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t;
82 * but of course C doesn't provide a way to check this directly. So here
83 * we rely on the fact that the symbol ETHERTYPE_AT was added to the
84 * header file (as a #define, which we *can* test for) at the same time
85 * as the typedef for ether_addr_t ;-!
86 */
87 #ifndef ETHERTYPE_AT
88 typedef uchar_t ether_addr_t[ETHERADDRL];
89 #endif /* ETHERTYPE_AT */
90
91 /*
92 * Reconfiguring the network devices requires the net_config privilege
93 * in Solaris 10+.
94 */
95 extern int secpolicy_net_config(const cred_t *, boolean_t);
96
97 #include <sys/netlb.h> /* originally from cassini */
98 #include <sys/miiregs.h> /* by fjlite out of intel */
99
100 #include "bge.h"
101 #include "bge_hw.h"
102
103 /*
104 * Compile-time feature switches ...
105 */
106 #define BGE_DO_PPIO 0 /* peek/poke ioctls */
107 #define BGE_RX_SOFTINT 0 /* softint per receive ring */
108 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */
109
110 /*
111 * NOTES:
112 *
113 * #defines:
114 *
115 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the
116 * register-set numbers to use for the config space registers
117 * and the operating registers respectively. On an OBP-based
118 * machine, regset 0 refers to CONFIG space, and regset 1 will
119 * be the operating registers in MEMORY space. If an expansion
120 * ROM is fitted, it may appear as a further register set.
121 *
122 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used
123 * for the data buffers. The descriptors are always set up
124 * in CONSISTENT mode.
125 *
126 * BGE_HEADROOM defines how much space we'll leave in allocated
127 * mblks before the first valid data byte. This should be chosen
128 * to be 2 modulo 4, so that once the ethernet header (14 bytes)
129 * has been stripped off, the packet data will be 4-byte aligned.
130 * The remaining space can be used by upstream modules to prepend
131 * any headers required.
132 */
133
134 #define BGE_PCI_CONFIG_RNUMBER 0
135 #define BGE_PCI_OPREGS_RNUMBER 1
136 #define BGE_DMA_MODE DDI_DMA_STREAMING
137 #define BGE_HEADROOM 34
138
139 /*
140 * BGE_HALFTICK is half the period of the cyclic callback (in
141 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s.
142 * Other time values are derived as odd multiples of this value
143 * so that there's little chance of ambiguity w.r.t. which tick
144 * a timeout expires on.
145 *
146 * BGE_PHY_STABLE_TIME is the period for which the contents of the
147 * PHY's status register must remain unchanging before we accept
148 * that the link has come up. [Sometimes the link comes up, only
149 * to go down again within a short time as the autonegotiation
150 * process cycles through various options before finding the best
151 * compatible mode. We don't want to report repeated link up/down
152 * cycles, so we wait until we think it's stable.]
153 *
154 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes
155 * interface. It's much shorter, 'cos the SerDes doesn't show
156 * these effects as much as the copper PHY.
157 *
158 * BGE_LINK_SETTLE_TIME is the period during which we regard link
159 * up/down cycles as an normal event after resetting/reprogramming
160 * the PHY. During this time, link up/down messages are sent to
161 * the log only, not the console. At any other time, link change
162 * events are regarded as unexpected and sent to both console & log.
163 *
164 * These latter two values have no theoretical justification, but
165 * are derived from observations and heuristics - the values below
166 * just seem to work quite well.
167 */
168
169 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */
170 #define BGE_CYCLIC_PERIOD (4*BGE_HALFTICK) /* ~1.0s */
171 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */
172 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */
173 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */
174
175 /*
176 * Indices used to identify the different buffer rings internally
177 */
178 #define BGE_STD_BUFF_RING 0
179 #define BGE_JUMBO_BUFF_RING 1
180 #define BGE_MINI_BUFF_RING 2
181
182 /*
183 * Current implementation limits
184 */
185 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */
186 /* for now */
187 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */
188 /* for now */
189 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */
190 /* for now */
191 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */
192
193 /*
194 * Ring/buffer size parameters
195 *
196 * All of the (up to) 16 TX rings & and the corresponding buffers are the
197 * same size.
198 *
199 * Each of the (up to) 3 receive producer (aka buffer) rings is a different
200 * size and has different sized buffers associated with it too.
201 *
202 * The (up to) 16 receive return rings have no buffers associated with them.
203 * The number of slots per receive return ring must be 2048 if the mini
204 * ring is enabled, otherwise it may be 1024. See Broadcom document
205 * 570X-PG102-R page 56.
206 *
207 * Note: only the 5700 supported external memory (and therefore the mini
208 * ring); the 5702/3/4 don't. This driver doesn't support the original
209 * 5700, so we won't ever use the mini ring capability.
210 */
211
212 #define BGE_SEND_RINGS_DEFAULT 1
213 #define BGE_RECV_RINGS_DEFAULT 1
214
215 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536
216 #define BGE_SEND_BUFF_SIZE_JUMBO 9022
217 #define BGE_SEND_SLOTS_USED 512
218
219 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */
220 #define BGE_STD_SLOTS_USED 512
221
222 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */
223 #define BGE_JUMBO_SLOTS_USED 256
224
225 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */
226 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */
227
228 #define BGE_RECV_BUFF_SIZE 0
229 #if BGE_MINI_SLOTS_USED > 0
230 #define BGE_RECV_SLOTS_USED 2048 /* required */
231 #else
232 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */
233 #endif
234
235 #define BGE_SEND_BUF_NUM 512
236 #define BGE_SEND_BUF_ARRAY 16
237 #define BGE_SEND_BUF_ARRAY_JUMBO 3
238 #define BGE_SEND_BUF_MAX (BGE_SEND_BUF_NUM*BGE_SEND_BUF_ARRAY)
239
240 /*
241 * PCI type. PCI-Express or PCI/PCIX
242 */
243 #define BGE_PCI 0
244 #define BGE_PCI_E 1
245 #define BGE_PCI_X 2
246
247 /*
248 * Statistic type. There are two type of statistic:
249 * statistic block and statistic registers
250 */
251 #define BGE_STAT_BLK 1
252 #define BGE_STAT_REG 2
253
254 /*
255 * MTU.for all chipsets ,the default is 1500 ,and some chipsets
256 * support 9k jumbo frames size
257 */
258 #define BGE_DEFAULT_MTU 1500
259 #define BGE_MAXIMUM_MTU 9000
260
261 /*
262 * Pad the h/w defined status block (which can be up to 80 bytes long)
263 * to a power-of-two boundary
264 */
265 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t))
266
267 /*
268 * On platforms which support DVMA, we can simply allocate one big piece
269 * of memory for all the Tx buffers and another for the Rx buffers, and
270 * then carve them up as required. It doesn't matter if they aren't just
271 * one physically contiguous piece each, because both the CPU *and* the
272 * I/O device can see them *as though they were*.
273 *
274 * However, if only physically-addressed DMA is possible, this doesn't
275 * work; we can't expect to get enough contiguously-addressed memory for
276 * all the buffers of each type, so in this case we request a number of
277 * smaller pieces, each still large enough for several buffers but small
278 * enough to fit within "an I/O page" (e.g. 64K).
279 *
280 * The #define below specifies how many pieces of memory are to be used;
281 * 16 has been shown to work on an i86pc architecture but this could be
282 * different on other non-DVMA platforms ...
283 */
284 #ifdef _DMA_USES_VIRTADDR
285 #define BGE_SPLIT 1 /* no split required */
286 #else
287 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \
288 (BGE_RECV_RINGS_USED > 1))
289 #define BGE_SPLIT 128 /* split 128 ways */
290 #else
291 #define BGE_SPLIT 16 /* split 16 ways */
292 #endif
293 #endif /* _DMA_USES_VIRTADDR */
294
295 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1)
296
297 /*
298 * STREAMS parameters
299 */
300 #define BGE_IDNUM 0 /* zero seems to work */
301 #define BGE_LOWAT (256)
302 #define BGE_HIWAT (256*1024)
303
304
305 /*
306 * Basic data types, for clarity in distinguishing 'numbers'
307 * used for different purposes ...
308 *
309 * A <bge_regno_t> is a register 'address' (offset) in any one of
310 * various address spaces (PCI config space, PCI memory-mapped I/O
311 * register space, MII registers, etc). None of these exceeds 64K,
312 * so we could use a 16-bit representation but pointer-sized objects
313 * are more "natural" in most architectures; they seem to be handled
314 * more efficiently on SPARC and no worse on x86.
315 *
316 * BGE_REGNO_NONE represents the non-existent value in this space.
317 */
318 typedef uintptr_t bge_regno_t; /* register # (offset) */
319 #define BGE_REGNO_NONE (~(uintptr_t)0u)
320
321 /*
322 * Describes one chunk of allocated DMA-able memory
323 *
324 * In some cases, this is a single chunk as allocated from the system;
325 * but we also use this structure to represent slices carved off such
326 * a chunk. Even when we don't really need all the information, we
327 * use this structure as a convenient way of correlating the various
328 * ways of looking at a piece of memory (kernel VA, IO space DVMA,
329 * handle+offset, etc).
330 */
331 typedef struct {
332 ddi_acc_handle_t acc_hdl; /* handle for memory */
333 void *mem_va; /* CPU VA of memory */
334 uint32_t nslots; /* number of slots */
335 uint32_t size; /* size per slot */
336 size_t alength; /* allocated size */
337 /* >= product of above */
338
339 ddi_dma_handle_t dma_hdl; /* DMA handle */
340 offset_t offset; /* relative to handle */
341 ddi_dma_cookie_t cookie; /* associated cookie */
342 uint32_t ncookies; /* must be 1 */
343 uint32_t token; /* arbitrary identifier */
344 } dma_area_t; /* 0x50 (80) bytes */
345
346 typedef struct bge_queue_item {
347 struct bge_queue_item *next;
348 void *item;
349 } bge_queue_item_t;
350
351 typedef struct bge_queue {
352 bge_queue_item_t *head;
353 uint32_t count;
354 kmutex_t *lock;
355 } bge_queue_t;
356 /*
357 * Software version of the Receive Buffer Descriptor
358 * There's one of these for each receive buffer (up to 256/512/1024 per ring).
359 */
360 typedef struct sw_rbd {
361 dma_area_t pbuf; /* (const) related */
362 /* buffer area */
363 } sw_rbd_t; /* 0x50 (80) bytes */
364
365 /*
366 * Software Receive Buffer (Producer) Ring Control Block
367 * There's one of these for each receiver producer ring (up to 3),
368 * but each holds buffers of a different size.
369 */
370 typedef struct buff_ring {
371 dma_area_t desc; /* (const) related h/w */
372 /* descriptor area */
373 dma_area_t buf[BGE_SPLIT]; /* (const) related */
374 /* buffer area(s) */
375 bge_rcb_t hw_rcb; /* (const) image of h/w */
376 /* RCB, and used to */
377 struct bge *bgep; /* (const) containing */
378 /* driver soft state */
379 /* initialise same */
380 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
381 /* "consumer index" */
382 /* (in status block) */
383
384 /*
385 * The rf_lock must be held when updating the h/w producer index
386 * mailbox register (*chip_mbox_reg), or the s/w producer index
387 * (rf_next).
388 */
389 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
390 /* index mailbox offset */
391 kmutex_t rf_lock[1]; /* serialize refill */
392 uint64_t rf_next; /* next slot to refill */
393 /* ("producer index") */
394
395 sw_rbd_t *sw_rbds; /* software descriptors */
396 void *spare[4]; /* padding */
397 } buff_ring_t; /* 0x100 (256) bytes */
398
399 typedef struct bge_multi_mac {
400 int naddr; /* total supported addresses */
401 int naddrfree; /* free addresses slots */
402 ether_addr_t mac_addr[MAC_ADDRESS_REGS_MAX];
403 boolean_t mac_addr_set[MAC_ADDRESS_REGS_MAX];
404 } bge_multi_mac_t;
405
406 /*
407 * Software Receive (Return) Ring Control Block
408 * There's one of these for each receiver return ring (up to 16).
409 */
410 typedef struct recv_ring {
411 /*
412 * The elements flagged (const) in the comments below are
413 * set up once during initialiation and thereafter unchanged.
414 */
415 dma_area_t desc; /* (const) related h/w */
416 /* descriptor area */
417 bge_rcb_t hw_rcb; /* (const) image of h/w */
418 /* RCB, and used to */
419 /* initialise same */
420 struct bge *bgep; /* (const) containing */
421 /* driver soft state */
422 ddi_softintr_t rx_softint; /* (const) per-ring */
423 /* receive callback */
424 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */
425 /* "producer index" */
426 /* (in status block) */
427 /*
428 * The rx_lock must be held when updating the h/w consumer index
429 * mailbox register (*chip_mbox_reg), or the s/w consumer index
430 * (rx_next).
431 */
432 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */
433 /* index mailbox offset */
434 kmutex_t rx_lock[1]; /* serialize receive */
435 uint64_t rx_next; /* next slot to examine */
436
437 mac_ring_handle_t ring_handle;
438 mac_group_handle_t ring_group_handle;
439 uint64_t ring_gen_num;
440 bge_rule_info_t *mac_addr_rule;
441 uint8_t mac_addr_val[ETHERADDRL];
442 int poll_flag; /* Polling flag */
443
444 /* Per-ring statistics */
445 uint64_t rx_pkts; /* Received Packets Count */
446 uint64_t rx_bytes; /* Received Bytes Count */
447 } recv_ring_t;
448
449
450 /*
451 * Send packet structure
452 */
453 typedef struct send_pkt {
454 uint16_t vlan_tci;
455 uint32_t pflags;
456 boolean_t tx_ready;
457 bge_queue_item_t *txbuf_item;
458 } send_pkt_t;
459
460 /*
461 * Software version of tx buffer structure
462 */
463 typedef struct sw_txbuf {
464 dma_area_t buf;
465 uint32_t copy_len;
466 } sw_txbuf_t;
467
468 /*
469 * Software version of the Send Buffer Descriptor
470 * There's one of these for each send buffer (up to 512 per ring)
471 */
472 typedef struct sw_sbd {
473 dma_area_t desc; /* (const) related h/w */
474 /* descriptor area */
475 bge_queue_item_t *pbuf; /* (const) related */
476 /* buffer area */
477 } sw_sbd_t;
478
479 /*
480 * Software Send Ring Control Block
481 * There's one of these for each of (up to) 16 send rings
482 */
483 typedef struct send_ring {
484 /*
485 * The elements flagged (const) in the comments below are
486 * set up once during initialiation and thereafter unchanged.
487 */
488 dma_area_t desc; /* (const) related h/w */
489 /* descriptor area */
490 dma_area_t buf[BGE_SEND_BUF_ARRAY][BGE_SPLIT];
491 /* buffer area(s) */
492 bge_rcb_t hw_rcb; /* (const) image of h/w */
493 /* RCB, and used to */
494 /* initialise same */
495 struct bge *bgep; /* (const) containing */
496 /* driver soft state */
497 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */
498 /* "consumer index" */
499 /* (in status block) */
500
501 bge_regno_t chip_mbx_reg; /* (const) h/w producer */
502 /* index mailbox offset */
503 /*
504 * Tx buffer queue
505 */
506 bge_queue_t txbuf_queue;
507 bge_queue_t freetxbuf_queue;
508 bge_queue_t *txbuf_push_queue;
509 bge_queue_t *txbuf_pop_queue;
510 kmutex_t txbuf_lock[1];
511 kmutex_t freetxbuf_lock[1];
512 bge_queue_item_t *txbuf_head;
513 send_pkt_t *pktp;
514 uint64_t txpkt_next;
515 uint64_t txfill_next;
516 sw_txbuf_t *txbuf;
517 uint32_t tx_buffers;
518 uint32_t tx_buffers_low;
519 uint32_t tx_array_max;
520 uint32_t tx_array;
521 kmutex_t tx_lock[1]; /* serialize h/w update */
522 /* ("producer index") */
523 uint64_t tx_next; /* next slot to use */
524 uint64_t tx_flow; /* # concurrent sends */
525 uint64_t tx_block;
526 uint64_t tx_nobd;
527 uint64_t tx_nobuf;
528 uint64_t tx_alloc_fail;
529
530 /*
531 * These counters/indexes are manipulated in the transmit
532 * path using atomics rather than mutexes for speed
533 */
534 uint64_t tx_free; /* # of slots available */
535
536 /*
537 * The tc_lock must be held while manipulating the s/w consumer
538 * index (tc_next).
539 */
540 kmutex_t tc_lock[1]; /* serialize recycle */
541 uint64_t tc_next; /* next slot to recycle */
542 /* ("consumer index") */
543
544 sw_sbd_t *sw_sbds; /* software descriptors */
545 uint64_t mac_resid; /* special per resource id */
546 uint64_t pushed_bytes;
547 } send_ring_t; /* 0x100 (256) bytes */
548
549 typedef struct {
550 ether_addr_t addr; /* in canonical form */
551 uint8_t spare;
552 boolean_t set; /* B_TRUE => valid */
553 } bge_mac_addr_t;
554
555 /*
556 * The original 5700/01 supported only SEEPROMs. Later chips (5702+)
557 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for
558 * the hardware and a backwards-compatible software access method), and
559 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus
560 * and using a new software access method.
561 *
562 * The access methods for SEEPROM and Flash are generally similar, with
563 * the chip handling the serialisation/deserialisation and handshaking,
564 * but the registers used are different, as are a few details of the
565 * protocol, and the timing, so we have to determine which (if any) is
566 * fitted.
567 *
568 * The value UNKNOWN means just that; we haven't yet tried to determine
569 * the device type.
570 *
571 * The value NONE can indicate either that a real and definite absence of
572 * any NVmem has been detected, or that there may be NVmem but we can't
573 * determine its type, perhaps because the NVconfig pins on the chip have
574 * been wired up incorrectly. In either case, access to the NVmem (if any)
575 * is not supported.
576 */
577 enum bge_nvmem_type {
578 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */
579 BGE_NVTYPE_UNKNOWN, /* not yet checked */
580 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */
581 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */
582 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */
583 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */
584 };
585
586 /*
587 * Describes the characteristics of a specific chip
588 *
589 * Note: elements from <businfo> to <latency> are filled in by during
590 * the first phase of chip initialisation (see bge_chip_cfg_init()).
591 * The remaining ones are determined just after the first RESET, in
592 * bge_poll_firmware(). Thereafter, the entire structure is readonly.
593 */
594 typedef struct {
595 uint32_t asic_rev; /* masked from MHCR */
596 uint32_t businfo; /* from private reg */
597 uint16_t command; /* saved during attach */
598
599 uint16_t vendor; /* vendor-id */
600 uint16_t device; /* device-id */
601 uint16_t subven; /* subsystem-vendor-id */
602 uint16_t subdev; /* subsystem-id */
603 uint8_t revision; /* revision-id */
604 uint8_t clsize; /* cache-line-size */
605 uint8_t latency; /* latency-timer */
606
607 uint8_t flags;
608 uint16_t chip_label; /* numeric part only */
609 /* (e.g. 5703/5794/etc) */
610 uint32_t mbuf_base; /* Mbuf pool parameters */
611 uint32_t mbuf_length; /* depend on chiptype */
612 uint32_t pci_type;
613 uint32_t statistic_type;
614 uint32_t bge_dma_rwctrl;
615 uint32_t bge_mlcr_default;
616 uint32_t recv_slots; /* receive ring size */
617 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */
618
619 uint16_t jumbo_slots;
620 uint16_t ethmax_size;
621 uint16_t snd_buff_size;
622 uint16_t recv_jumbo_size;
623 uint16_t std_buf_size;
624 uint32_t mbuf_hi_water;
625 uint32_t mbuf_lo_water_rmac;
626 uint32_t mbuf_lo_water_rdma;
627
628 uint32_t rx_rings; /* from bge.conf */
629 uint32_t tx_rings; /* from bge.conf */
630 uint32_t default_mtu; /* from bge.conf */
631
632 uint64_t hw_mac_addr; /* from chip register */
633 bge_mac_addr_t vendor_addr; /* transform of same */
634 boolean_t msi_enabled; /* default to true */
635
636 uint32_t rx_ticks_norm;
637 uint32_t rx_count_norm;
638 uint32_t tx_ticks_norm;
639 uint32_t tx_count_norm;
640 uint32_t mask_pci_int;
641 } chip_id_t;
642
643 #define CHIP_FLAG_SUPPORTED 0x80
644 #define CHIP_FLAG_SERDES 0x40
645 #define CHIP_FLAG_PARTIAL_CSUM 0x20
646 #define CHIP_FLAG_NO_JUMBO 0x1
647
648 /*
649 * Collection of physical-layer functions to:
650 * (re)initialise the physical layer
651 * update it to match software settings
652 * check for link status change
653 */
654 typedef struct {
655 int (*phys_restart)(struct bge *, boolean_t);
656 int (*phys_update)(struct bge *);
657 boolean_t (*phys_check)(struct bge *, boolean_t);
658 } phys_ops_t;
659
660
661 /*
662 * Actual state of the BCM570x chip
663 */
664 enum bge_chip_state {
665 BGE_CHIP_FAULT = -2, /* fault, need reset */
666 BGE_CHIP_ERROR, /* error, want reset */
667 BGE_CHIP_INITIAL, /* Initial state only */
668 BGE_CHIP_RESET, /* reset, need init */
669 BGE_CHIP_STOPPED, /* Tx/Rx stopped */
670 BGE_CHIP_RUNNING /* with interrupts */
671 };
672
673 enum bge_mac_state {
674 BGE_MAC_STOPPED = 0,
675 BGE_MAC_STARTED
676 };
677
678 /*
679 * (Internal) return values from ioctl subroutines
680 */
681 enum ioc_reply {
682 IOC_INVAL = -1, /* bad, NAK with EINVAL */
683 IOC_DONE, /* OK, reply sent */
684 IOC_ACK, /* OK, just send ACK */
685 IOC_REPLY, /* OK, just send reply */
686 IOC_RESTART_ACK, /* OK, restart & ACK */
687 IOC_RESTART_REPLY /* OK, restart & reply */
688 };
689
690 /*
691 * (Internal) return values from send_msg subroutines
692 */
693 enum send_status {
694 SEND_FAIL = -1, /* Not OK */
695 SEND_KEEP, /* OK, msg queued */
696 SEND_FREE /* OK, free msg */
697 };
698
699 /*
700 * (Internal) enumeration of this driver's kstats
701 */
702 enum {
703 BGE_KSTAT_RAW = 0,
704 BGE_KSTAT_STATS,
705 BGE_KSTAT_CHIPID,
706 BGE_KSTAT_DRIVER,
707 BGE_KSTAT_PHYS,
708
709 BGE_KSTAT_COUNT
710 };
711
712 #define BGE_MAX_RESOURCES 255
713
714 /*
715 * Per-instance soft-state structure
716 */
717 typedef struct bge {
718 /*
719 * These fields are set by attach() and unchanged thereafter ...
720 */
721 dev_info_t *devinfo; /* device instance */
722 mac_handle_t mh; /* mac module handle */
723 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */
724 ddi_acc_handle_t io_handle; /* DDI I/O handle */
725 void *io_regs; /* mapped registers */
726 ddi_periodic_t periodic_id; /* periodical callback */
727 ddi_softintr_t factotum_id; /* factotum callback */
728 ddi_softintr_t drain_id; /* reschedule callback */
729
730 ddi_intr_handle_t *htable; /* For array of interrupts */
731 int intr_type; /* What type of interrupt */
732 int intr_cnt; /* # of intrs count returned */
733 uint_t intr_pri; /* Interrupt priority */
734 int intr_cap; /* Interrupt capabilities */
735 uint32_t progress; /* attach tracking */
736 uint32_t debug; /* per-instance debug */
737 chip_id_t chipid;
738 const phys_ops_t *physops;
739 char ifname[8]; /* "bge0" ... "bge999" */
740
741 int fm_capabilities; /* FMA capabilities */
742
743 /*
744 * These structures describe the blocks of memory allocated during
745 * attach(). They remain unchanged thereafter, although the memory
746 * they describe is carved up into various separate regions and may
747 * therefore be described by other structures as well.
748 */
749 dma_area_t tx_desc; /* transmit descriptors */
750 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT];
751 /* receive descriptors */
752 dma_area_t tx_buff[BGE_SPLIT];
753 dma_area_t rx_buff[BGE_SPLIT];
754
755 /*
756 * The memory described by the <dma_area> structures above
757 * is carved up into various pieces, which are described by
758 * the structures below.
759 */
760 dma_area_t statistics; /* describes hardware */
761 /* statistics area */
762 dma_area_t status_block; /* describes hardware */
763 /* status block */
764 /*
765 * For the BCM5705/5788/5721/5751/5752/5714 and 5715,
766 * the statistic block is not available,the statistic counter must
767 * be gotten from statistic registers.And bge_statistics_reg_t record
768 * the statistic registers value
769 */
770 bge_statistics_reg_t *pstats;
771
772 /*
773 * Runtime read-write data starts here ...
774 *
775 * 3 Buffer Rings (std/jumbo/mini)
776 * 16 Receive (Return) Rings
777 * 16 Send Rings
778 *
779 * Note: they're not necessarily all used.
780 */
781 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */
782
783 /* may be obsoleted */
784 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */
785 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */
786
787 /*
788 * Locks:
789 *
790 * Each buffer ring contains its own <rf_lock> which regulates
791 * ring refilling.
792 *
793 * Each receive (return) ring contains its own <rx_lock> which
794 * protects the critical cyclic counters etc.
795 *
796 * Each send ring contains two locks: <tx_lock> for the send-path
797 * protocol data and <tc_lock> for send-buffer recycling.
798 *
799 * Finally <genlock> is a general lock, protecting most other
800 * operational data in the state structure and chip register
801 * accesses. It is acquired by the interrupt handler and
802 * most "mode-control" routines.
803 *
804 * Any of the locks can be acquired singly, but where multiple
805 * locks are acquired, they *must* be in the order:
806 *
807 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock.
808 *
809 * and within any one class of lock the rings must be locked in
810 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc.
811 *
812 * Note: actually I don't believe there's any need to acquire
813 * locks on multiple rings, or even locks of all these classes
814 * concurrently; but I've set out the above order so there is a
815 * clear definition of lock hierarchy in case it's ever needed.
816 *
817 * Note: the combinations of locks that are actually held
818 * concurrently are:
819 *
820 * genlock >>> (bge_chip_interrupt())
821 * rx_lock[i] >>> (bge_receive())
822 * rf_lock[n] (bge_refill())
823 * tc_lock[i] (bge_recycle())
824 */
825 kmutex_t genlock[1];
826 krwlock_t errlock[1];
827 kmutex_t softintrlock[1];
828
829 /*
830 * Current Ethernet addresses and multicast hash (bitmap) and
831 * refcount tables, protected by <genlock>
832 */
833 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX];
834 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32];
835 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE];
836 uint32_t unicst_addr_total; /* total unicst addresses */
837 uint32_t unicst_addr_avail;
838 /* unused unicst addr slots */
839
840 /*
841 * Link state data (protected by genlock)
842 */
843 link_state_t link_state;
844
845 /*
846 * Physical layer: copper only
847 */
848 bge_regno_t phy_mii_addr; /* should be (const) 1! */
849 uint16_t phy_gen_status;
850 uint16_t phy_aux_status;
851
852 /*
853 * Physical layer: serdes only
854 */
855 uint32_t serdes_status;
856 uint32_t serdes_advert;
857 uint32_t serdes_lpadv;
858
859 /*
860 * Driver kstats, protected by <genlock> where necessary
861 */
862 kstat_t *bge_kstats[BGE_KSTAT_COUNT];
863
864 /*
865 * Miscellaneous operating variables (protected by genlock)
866 */
867 uint64_t chip_resets; /* # of chip RESETs */
868 uint64_t missed_dmas; /* # of missed DMAs */
869 uint64_t missed_updates; /* # of missed updates */
870 enum bge_mac_state bge_mac_state; /* definitions above */
871 enum bge_chip_state bge_chip_state; /* definitions above */
872 boolean_t send_hw_tcp_csum;
873 boolean_t recv_hw_tcp_csum;
874 boolean_t promisc;
875 boolean_t manual_reset;
876
877 /*
878 * Miscellaneous operating variables (not synchronised)
879 */
880 uint32_t watchdog; /* watches for Tx stall */
881 boolean_t bge_intr_running;
882 boolean_t bge_dma_error;
883 boolean_t tx_resched_needed;
884 uint64_t tx_resched;
885 uint32_t factotum_flag; /* softint pending */
886 uintptr_t pagemask;
887
888 /*
889 * NDD parameters (protected by genlock)
890 */
891 caddr_t nd_data_p;
892
893 /*
894 * A flag to prevent excessive config space accesses
895 * on platforms having BCM5714C/15C
896 */
897 boolean_t lastWriteZeroData;
898
899 /*
900 * Spare space, plus guard element used to check data integrity
901 */
902 uint64_t spare[5];
903 uint64_t bge_guard;
904
905 /*
906 * Receive rules configure
907 */
908 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX];
909
910 #ifdef BGE_IPMI_ASF
911 boolean_t asf_enabled;
912 boolean_t asf_wordswapped;
913 boolean_t asf_newhandshake;
914 boolean_t asf_pseudostop;
915
916 uint32_t asf_status;
917 timeout_id_t asf_timeout_id;
918 #endif
919 uint32_t param_en_pause:1,
920 param_en_asym_pause:1,
921 param_en_1000hdx:1,
922 param_en_1000fdx:1,
923 param_en_100fdx:1,
924 param_en_100hdx:1,
925 param_en_10fdx:1,
926 param_en_10hdx:1,
927 param_adv_autoneg:1,
928 param_adv_1000fdx:1,
929 param_adv_1000hdx:1,
930 param_adv_100fdx:1,
931 param_adv_100hdx:1,
932 param_adv_10fdx:1,
933 param_adv_10hdx:1,
934 param_lp_autoneg:1,
935 param_lp_pause:1,
936 param_lp_asym_pause:1,
937 param_lp_1000fdx:1,
938 param_lp_1000hdx:1,
939 param_lp_100fdx:1,
940 param_lp_100hdx:1,
941 param_lp_10fdx:1,
942 param_lp_10hdx:1,
943 param_link_up:1,
944 param_link_autoneg:1,
945 param_adv_pause:1,
946 param_adv_asym_pause:1,
947 param_link_rx_pause:1,
948 param_link_tx_pause:1,
949 param_pad_to_32:2;
950
951 uint32_t param_loop_mode;
952 uint32_t param_msi_cnt;
953 uint32_t param_drain_max;
954 uint64_t param_link_speed;
955 link_duplex_t param_link_duplex;
956
957
958 uint32_t link_update_timer;
959 uint64_t timestamp;
960 } bge_t;
961
962 /*
963 * 'Progress' bit flags ...
964 */
965 #define PROGRESS_CFG 0x0001 /* config space mapped */
966 #define PROGRESS_REGS 0x0002 /* registers mapped */
967 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */
968 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */
969 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */
970 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */
971 /* and mutexen initialised */
972 #define PROGRESS_INTR 0x0080 /* Intrs enabled */
973 #define PROGRESS_PHY 0x0100 /* PHY initialised */
974 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */
975 #define PROGRESS_KSTATS 0x2000 /* kstats created */
976 #define PROGRESS_READY 0x8000 /* ready for work */
977
978
979 /*
980 * Sync a DMA area described by a dma_area_t
981 */
982 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \
983 (area).offset, (area).alength, (flag)))
984
985 /*
986 * Find the (kernel virtual) address of block of memory
987 * described by a dma_area_t
988 */
989 #define DMA_VPTR(area) ((area).mem_va)
990
991 /*
992 * Zero a block of memory described by a dma_area_t
993 */
994 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength)
995
996 /*
997 * Next value of a cyclic index
998 */
999 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0)
1000
1001 /*
1002 * Property lookups
1003 */
1004 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
1005 DDI_PROP_DONTPASS, (n))
1006 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
1007 DDI_PROP_DONTPASS, (n), -1)
1008
1009 /*
1010 * Copy an ethernet address
1011 */
1012 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL)
1013
1014 /*
1015 * Endian swap
1016 */
1017 /* BEGIN CSTYLED */
1018 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \
1019 (((x) & 0x00ff0000) >> 8) | \
1020 (((x) & 0x0000ff00) << 8) | \
1021 (((x) & 0x000000ff) << 24))
1022 /* END CSTYLED */
1023
1024 /*
1025 * Marker value placed at the end of the driver's state
1026 */
1027 #define BGE_GUARD 0x1919306009031802
1028
1029 /*
1030 * Bit flags in the 'debug' word ...
1031 */
1032 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */
1033 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */
1034
1035 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */
1036 #define BGE_DBG_MII 0x00000020 /* low-level MII access */
1037 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */
1038 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */
1039
1040 #define BGE_DBG_RECV 0x00000100 /* receive-side code */
1041 #define BGE_DBG_SEND 0x00000200 /* packet-send code */
1042
1043 #define BGE_DBG_INT 0x00001000 /* interrupt handler */
1044 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */
1045
1046 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */
1047 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */
1048 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */
1049 #define BGE_DBG_LINK 0x00080000 /* Link status check */
1050
1051 #define BGE_DBG_INIT 0x00100000 /* initialisation */
1052 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */
1053 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */
1054 #define BGE_DBG_STATS 0x00800000 /* statistics */
1055
1056 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */
1057 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */
1058 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */
1059 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */
1060
1061 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */
1062 #define BGE_DBG_NDD 0x20000000 /* NDD operations */
1063
1064 /*
1065 * Debugging ...
1066 */
1067 #ifdef DEBUG
1068 #define BGE_DEBUGGING 1
1069 #else
1070 #define BGE_DEBUGGING 0
1071 #endif /* DEBUG */
1072
1073
1074 /*
1075 * 'Do-if-debugging' macro. The parameter <command> should be one or more
1076 * C statements (but without the *final* semicolon), which will either be
1077 * compiled inline or completely ignored, depending on the BGE_DEBUGGING
1078 * compile-time flag.
1079 *
1080 * You should get a compile-time error (at least on a DEBUG build) if
1081 * your statement isn't actually a statement, rather than unexpected
1082 * run-time behaviour caused by unintended matching of if-then-elses etc.
1083 *
1084 * Note that the BGE_DDB() macro itself can only be used as a statement,
1085 * not an expression, and should always be followed by a semicolon.
1086 */
1087 #if BGE_DEBUGGING
1088 #define BGE_DDB(command) do { \
1089 { command; } \
1090 _NOTE(CONSTANTCONDITION) \
1091 } while (0)
1092 #else /* BGE_DEBUGGING */
1093 #define BGE_DDB(command) do { \
1094 { _NOTE(EMPTY); } \
1095 _NOTE(CONSTANTCONDITION) \
1096 } while (0)
1097 #endif /* BGE_DEBUGGING */
1098
1099 /*
1100 * 'Internal' macros used to construct the TRACE/DEBUG macros below.
1101 * These provide the primitive conditional-call capability required.
1102 * Note: the parameter <args> is a parenthesised list of the actual
1103 * printf-style arguments to be passed to the debug function ...
1104 */
1105 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args)
1106 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args)
1107 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args)
1108 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args)
1109
1110 /*
1111 * Conditional-print macros.
1112 *
1113 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values
1114 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G'
1115 * versions look at the Global debug flag word (bge_debug); the non-G
1116 * versions look in the per-instance data (bgep->debug) and so require a
1117 * variable called 'bgep' to be in scope (and initialised!) before use.
1118 *
1119 * You could redefine BGE_TRC too if you really need two different
1120 * flavours of debugging output in the same area of code, but I don't
1121 * really recommend it.
1122 *
1123 * Note: the parameter <args> is a parenthesised list of the actual
1124 * arguments to be passed to the debug function, usually a printf-style
1125 * format string and corresponding values to be formatted.
1126 */
1127
1128 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */
1129 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args)
1130 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args)
1131 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args)
1132 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args)
1133
1134 /*
1135 * Debug-only action macros
1136 */
1137 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s))
1138 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep))
1139 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep))
1140 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args)
1141 #define BGE_REPORT(args) BGE_DDB(bge_log args)
1142
1143 /*
1144 * Inter-source-file linkage ...
1145 */
1146
1147 /* bge_chip.c */
1148 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1149 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value);
1150 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
1151 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value);
1152 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1153 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
1154 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value);
1155 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
1156 int bge_chip_id_init(bge_t *bgep);
1157 void bge_chip_coalesce_update(bge_t *bgep);
1158 int bge_chip_start(bge_t *bgep, boolean_t reset_phy);
1159 void bge_chip_stop(bge_t *bgep, boolean_t fault);
1160 #ifndef __sparc
1161 void bge_chip_stop_nonblocking(bge_t *bgep);
1162 #endif
1163 #ifdef BGE_IPMI_ASF
1164 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
1165 #pragma inline(bge_nic_put32)
1166 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr);
1167 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
1168 #pragma inline(bge_ind_put32)
1169 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
1170 #pragma inline(bge_ind_get32)
1171 void bge_asf_update_status(bge_t *bgep);
1172 void bge_asf_heartbeat(void *bgep);
1173 void bge_asf_stop_timer(bge_t *bgep);
1174 void bge_asf_get_config(bge_t *bgep);
1175 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode);
1176 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode);
1177 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode);
1178 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
1179 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
1180 #else
1181 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
1182 int bge_chip_sync(bge_t *bgep);
1183 #endif
1184 void bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag);
1185 extern mblk_t *bge_poll_ring(void *, int);
1186 uint_t bge_chip_factotum(caddr_t arg);
1187 void bge_chip_cyclic(void *arg);
1188 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
1189 struct iocblk *iocp);
1190 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
1191 void bge_sync_mac_modes(bge_t *);
1192 extern uint32_t bge_rx_ticks_norm;
1193 extern uint32_t bge_tx_ticks_norm;
1194 extern uint32_t bge_rx_count_norm;
1195 extern uint32_t bge_tx_count_norm;
1196 extern boolean_t bge_relaxed_ordering;
1197
1198 void bge_chip_msi_trig(bge_t *bgep);
1199
1200 /* bge_kstats.c */
1201 void bge_init_kstats(bge_t *bgep, int instance);
1202 void bge_fini_kstats(bge_t *bgep);
1203 int bge_m_stat(void *arg, uint_t stat, uint64_t *val);
1204 int bge_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
1205
1206 /* bge_log.c */
1207 #if BGE_DEBUGGING
1208 void (*bge_db(bge_t *bgep))(const char *fmt, ...);
1209 void (*bge_gdb(void))(const char *fmt, ...);
1210 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg);
1211 void bge_dbg_enter(bge_t *bgep, const char *msg);
1212 #endif /* BGE_DEBUGGING */
1213 void bge_problem(bge_t *bgep, const char *fmt, ...);
1214 void bge_log(bge_t *bgep, const char *fmt, ...);
1215 void bge_error(bge_t *bgep, const char *fmt, ...);
1216 void bge_fm_ereport(bge_t *bgep, char *detail);
1217 extern kmutex_t bge_log_mutex[1];
1218 extern uint32_t bge_debug;
1219
1220 /* bge_main.c */
1221 int bge_restart(bge_t *bgep, boolean_t reset_phy);
1222 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle);
1223 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle);
1224 void bge_init_rings(bge_t *bgep);
1225 void bge_fini_rings(bge_t *bgep);
1226 bge_queue_item_t *bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp);
1227 void bge_free_txbuf_arrays(send_ring_t *srp);
1228 int bge_alloc_bufs(bge_t *bgep);
1229 void bge_free_bufs(bge_t *bgep);
1230 void bge_intr_enable(bge_t *bgep);
1231 void bge_intr_disable(bge_t *bgep);
1232 int bge_reprogram(bge_t *);
1233
1234 /* bge_phys.c */
1235 int bge_phys_init(bge_t *bgep);
1236 void bge_phys_reset(bge_t *bgep);
1237 int bge_phys_idle(bge_t *bgep);
1238 int bge_phys_update(bge_t *bgep);
1239 boolean_t bge_phys_check(bge_t *bgep);
1240
1241 /* bge_ndd.c */
1242 int bge_nd_init(bge_t *bgep);
1243
1244 /* bge_recv.c */
1245 void bge_receive(bge_t *bgep, bge_status_t *bsp);
1246
1247 /* bge_send.c */
1248 mblk_t *bge_m_tx(void *arg, mblk_t *mp);
1249 mblk_t *bge_ring_tx(void *arg, mblk_t *mp);
1250 boolean_t bge_recycle(bge_t *bgep, bge_status_t *bsp);
1251 uint_t bge_send_drain(caddr_t arg);
1252
1253 /* bge_atomic.c */
1254 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n);
1255 void bge_atomic_renounce(uint64_t *count_p, uint64_t n);
1256 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit);
1257 uint64_t bge_atomic_next(uint64_t *sp, uint64_t limit);
1258 void bge_atomic_sub64(uint64_t *count_p, uint64_t n);
1259 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits);
1260 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count);
1261
1262 /* bge_mii_5906.c */
1263 void bge_adj_volt_5906(bge_t *bgep);
1264
1265 /*
1266 * Reset type
1267 */
1268 #define BGE_SHUTDOWN_RESET 0
1269 #define BGE_INIT_RESET 1
1270 #define BGE_SUSPEND_RESET 2
1271
1272 /* For asf_status */
1273 #define ASF_STAT_NONE 0
1274 #define ASF_STAT_STOP 1
1275 #define ASF_STAT_RUN 2
1276 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */
1277
1278 /* ASF modes for bge_reset() and bge_chip_reset() */
1279 #define ASF_MODE_NONE 0 /* don't launch asf */
1280 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */
1281 #define ASF_MODE_INIT 2 /* asf init mode */
1282 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */
1283 #define ASF_MODE_POST_INIT 4 /* only do post-init */
1284
1285 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000
1286
1287 #define BGE_LINK_UPDATE_TIMEOUT 10 /* ~ 5 sec */
1288 #define BGE_LINK_UPDATE_DONE (BGE_LINK_UPDATE_TIMEOUT+1)
1289
1290 #ifdef __cplusplus
1291 }
1292 #endif
1293
1294 #endif /* _BGE_IMPL_H */