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--- old/usr/src/uts/common/io/bge/bge_hw.h
+++ new/usr/src/uts/common/io/bge/bge_hw.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 +/*
27 + * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 + */
29 +
26 30 #ifndef _BGE_HW_H
27 31 #define _BGE_HW_H
28 32
29 33 #ifdef __cplusplus
30 34 extern "C" {
31 35 #endif
32 36
33 37 #include <sys/types.h>
34 38
35 39
36 40 /*
37 41 * First section:
38 42 * Identification of the various Broadcom chips
39 43 *
40 44 * Note: the various ID values are *not* all unique ;-(
41 45 *
42 46 * Note: the presence of an ID here does *not* imply that the chip is
43 47 * supported. At this time, only the 5703C, 5704C, and 5704S devices
44 48 * used on the motherboards of certain Sun products are supported.
45 49 *
46 50 * Note: the revision-id values in the PCI revision ID register are
47 51 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead.
48 52 */
49 53
50 54 #define VENDOR_ID_BROADCOM 0x14e4
51 55 #define VENDOR_ID_SUN 0x108e
52 56
53 57 #define DEVICE_ID_5700 0x1644
54 58 #define DEVICE_ID_5700x 0x0003
55 59 #define DEVICE_ID_5701 0x1645
56 60 #define DEVICE_ID_5702 0x16a6
57 61 #define DEVICE_ID_5702fe 0x164d
58 62 #define DEVICE_ID_5703C 0x16a7
59 63 #define DEVICE_ID_5703S 0x1647
60 64 #define DEVICE_ID_5703 0x16c7
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61 65 #define DEVICE_ID_5704C 0x1648
62 66 #define DEVICE_ID_5704S 0x16a8
63 67 #define DEVICE_ID_5704 0x1649
64 68 #define DEVICE_ID_5705C 0x1653
65 69 #define DEVICE_ID_5705_2 0x1654
66 70 #define DEVICE_ID_5717 0x1655
67 71 #define DEVICE_ID_5718 0x1656
68 72 #define DEVICE_ID_5724 0x165c
69 73 #define DEVICE_ID_5705M 0x165d
70 74 #define DEVICE_ID_5705MA3 0x165e
75 +#define DEVICE_ID_5719 0x1657
76 +#define DEVICE_ID_5720 0x165f
71 77 #define DEVICE_ID_5705F 0x166e
72 78 #define DEVICE_ID_5780 0x166a
73 79 #define DEVICE_ID_5782 0x1696
74 80 #define DEVICE_ID_5784M 0x1698
75 81 #define DEVICE_ID_5785 0x1699
76 82 #define DEVICE_ID_5787 0x169b
77 83 #define DEVICE_ID_5787M 0x1693
78 84 #define DEVICE_ID_5788 0x169c
79 85 #define DEVICE_ID_5789 0x169d
80 86 #define DEVICE_ID_5751 0x1677
81 87 #define DEVICE_ID_5751M 0x167d
82 88 #define DEVICE_ID_5752 0x1600
83 89 #define DEVICE_ID_5752M 0x1601
84 90 #define DEVICE_ID_5753 0x16fd
85 91 #define DEVICE_ID_5754 0x167a
86 92 #define DEVICE_ID_5755 0x167b
87 93 #define DEVICE_ID_5755M 0x1673
88 94 #define DEVICE_ID_5756M 0x1674
89 95 #define DEVICE_ID_5721 0x1659
90 96 #define DEVICE_ID_5722 0x165a
91 97 #define DEVICE_ID_5723 0x165b
92 98 #define DEVICE_ID_5714C 0x1668
93 99 #define DEVICE_ID_5714S 0x1669
94 100 #define DEVICE_ID_5715C 0x1678
95 101 #define DEVICE_ID_5715S 0x1679
96 102 #define DEVICE_ID_5761 0x1681
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97 103 #define DEVICE_ID_5761E 0x1680
98 104 #define DEVICE_ID_5761S 0x1688
99 105 #define DEVICE_ID_5761SE 0x1689
100 106 #define DEVICE_ID_5764 0x1684
101 107 #define DEVICE_ID_5906 0x1712
102 108 #define DEVICE_ID_5906M 0x1713
103 109 #define DEVICE_ID_57760 0x1690
104 110 #define DEVICE_ID_57780 0x1692
105 111 #define DEVICE_ID_57788 0x1691
106 112 #define DEVICE_ID_57790 0x1694
113 +#define DEVICE_ID_57781 0x16b1
114 +#define DEVICE_ID_57785 0x16b5
115 +#define DEVICE_ID_57761 0x16b0
116 +#define DEVICE_ID_57765 0x16b4
117 +#define DEVICE_ID_57791 0x16b2
118 +#define DEVICE_ID_57795 0x16b6
119 +#define DEVICE_ID_57762 0x1682
120 +#define DEVICE_ID_57766 0x1686
121 +#define DEVICE_ID_57786 0x16b3
122 +#define DEVICE_ID_57782 0x16b7
107 123
108 124 #define REVISION_ID_5700_B0 0x10
109 125 #define REVISION_ID_5700_B2 0x12
110 126 #define REVISION_ID_5700_B3 0x13
111 127 #define REVISION_ID_5700_C0 0x20
112 128 #define REVISION_ID_5700_C1 0x21
113 129 #define REVISION_ID_5700_C2 0x22
114 130
115 131 #define REVISION_ID_5701_A0 0x08
116 132 #define REVISION_ID_5701_A2 0x12
117 133 #define REVISION_ID_5701_A3 0x15
118 134
119 135 #define REVISION_ID_5702_A0 0x00
120 136
121 137 #define REVISION_ID_5703_A0 0x00
122 138 #define REVISION_ID_5703_A1 0x01
123 139 #define REVISION_ID_5703_A2 0x02
124 140
125 141 #define REVISION_ID_5704_A0 0x00
126 142 #define REVISION_ID_5704_A1 0x01
127 143 #define REVISION_ID_5704_A2 0x02
128 144 #define REVISION_ID_5704_A3 0x03
129 145 #define REVISION_ID_5704_B0 0x10
130 146
131 147 #define REVISION_ID_5705_A0 0x00
132 148 #define REVISION_ID_5705_A1 0x01
133 149 #define REVISION_ID_5705_A2 0x02
134 150 #define REVISION_ID_5705_A3 0x03
135 151
136 152 #define REVISION_ID_5721_A0 0x00
137 153 #define REVISION_ID_5721_A1 0x01
138 154
139 155 #define REVISION_ID_5751_A0 0x00
140 156 #define REVISION_ID_5751_A1 0x01
141 157
142 158 #define REVISION_ID_5714_A0 0x00
143 159 #define REVISION_ID_5714_A1 0x01
144 160 #define REVISION_ID_5714_A2 0xA2
145 161 #define REVISION_ID_5714_A3 0xA3
146 162
147 163 #define REVISION_ID_5715_A0 0x00
148 164 #define REVISION_ID_5715_A1 0x01
149 165 #define REVISION_ID_5715_A2 0xA2
150 166
151 167 #define REVISION_ID_5715S_A0 0x00
152 168 #define REVISION_ID_5715S_A1 0x01
153 169
154 170 #define REVISION_ID_5754_A0 0x00
155 171 #define REVISION_ID_5754_A1 0x01
156 172
157 173 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\
158 174 ((bgep->chipid.device == DEVICE_ID_5700) ||\
159 175 (bgep->chipid.device == DEVICE_ID_5701) ||\
160 176 (bgep->chipid.device == DEVICE_ID_5702) ||\
161 177 (bgep->chipid.device == DEVICE_ID_5702fe)||\
162 178 (bgep->chipid.device == DEVICE_ID_5703C) ||\
163 179 (bgep->chipid.device == DEVICE_ID_5703S) ||\
164 180 (bgep->chipid.device == DEVICE_ID_5703) ||\
165 181 (bgep->chipid.device == DEVICE_ID_5704C) ||\
166 182 (bgep->chipid.device == DEVICE_ID_5704S) ||\
167 183 (bgep->chipid.device == DEVICE_ID_5704))
168 184
169 185 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \
170 186 ((bgep->chipid.device == DEVICE_ID_5702) ||\
171 187 (bgep->chipid.device == DEVICE_ID_5702fe))
172 188
173 189 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \
174 190 ((bgep->chipid.device == DEVICE_ID_5705C) ||\
175 191 (bgep->chipid.device == DEVICE_ID_5705M) ||\
176 192 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\
177 193 (bgep->chipid.device == DEVICE_ID_5705F) ||\
178 194 (bgep->chipid.device == DEVICE_ID_5780) ||\
179 195 (bgep->chipid.device == DEVICE_ID_5782) ||\
180 196 (bgep->chipid.device == DEVICE_ID_5788) ||\
181 197 (bgep->chipid.device == DEVICE_ID_5705_2) ||\
182 198 (bgep->chipid.device == DEVICE_ID_5754) ||\
183 199 (bgep->chipid.device == DEVICE_ID_5755) ||\
184 200 (bgep->chipid.device == DEVICE_ID_5756M) ||\
185 201 (bgep->chipid.device == DEVICE_ID_5753))
186 202
187 203 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \
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188 204 ((bgep->chipid.device == DEVICE_ID_5721) ||\
189 205 (bgep->chipid.device == DEVICE_ID_5751) ||\
190 206 (bgep->chipid.device == DEVICE_ID_5751M) ||\
191 207 (bgep->chipid.device == DEVICE_ID_5752) ||\
192 208 (bgep->chipid.device == DEVICE_ID_5752M) ||\
193 209 (bgep->chipid.device == DEVICE_ID_5789))
194 210
195 211 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \
196 212 (bgep->chipid.device == DEVICE_ID_5717) ||\
197 213 (bgep->chipid.device == DEVICE_ID_5718) ||\
214 + (bgep->chipid.device == DEVICE_ID_5719) ||\
215 + (bgep->chipid.device == DEVICE_ID_5720) ||\
198 216 (bgep->chipid.device == DEVICE_ID_5724)
199 217
200 218 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \
201 219 ((bgep->chipid.device == DEVICE_ID_5723) ||\
202 220 (bgep->chipid.device == DEVICE_ID_5761) ||\
203 221 (bgep->chipid.device == DEVICE_ID_5761E) ||\
204 222 (bgep->chipid.device == DEVICE_ID_5761S) ||\
205 223 (bgep->chipid.device == DEVICE_ID_5761SE) ||\
206 224 (bgep->chipid.device == DEVICE_ID_5764) ||\
207 225 (bgep->chipid.device == DEVICE_ID_5784M) ||\
208 226 (bgep->chipid.device == DEVICE_ID_5785) ||\
209 227 (bgep->chipid.device == DEVICE_ID_57760) ||\
210 228 (bgep->chipid.device == DEVICE_ID_57780) ||\
211 229 (bgep->chipid.device == DEVICE_ID_57788) ||\
212 230 (bgep->chipid.device == DEVICE_ID_57790))
213 231
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214 232 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \
215 233 ((bgep->chipid.device == DEVICE_ID_5714C) ||\
216 234 (bgep->chipid.device == DEVICE_ID_5714S) ||\
217 235 (bgep->chipid.device == DEVICE_ID_5715C) ||\
218 236 (bgep->chipid.device == DEVICE_ID_5715S))
219 237
220 238 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \
221 239 ((bgep->chipid.device == DEVICE_ID_5906) ||\
222 240 (bgep->chipid.device == DEVICE_ID_5906M))
223 241
242 +
243 +#define CHIP_TYPE_5705_PLUS (1 << 0)
244 +#define CHIP_TYPE_5750_PLUS (1 << 1)
245 +#define CHIP_TYPE_5780_CLASS (1 << 2)
246 +#define CHIP_TYPE_5755_PLUS (1 << 3)
247 +#define CHIP_TYPE_57765_CLASS (1 << 4)
248 +#define CHIP_TYPE_57765_PLUS (1 << 5)
249 +#define CHIP_TYPE_5717_PLUS (1 << 6)
250 +
251 +#define DEVICE_IS_57765_PLUS(bgep) \
252 + (bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
253 +#define DEVICE_IS_5755_PLUS(bgep) \
254 + (bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)
255 +
224 256 /*
225 257 * Second section:
226 258 * Offsets of important registers & definitions for bits therein
227 259 */
228 260
229 261 /*
230 262 * PCI-X registers & bits
231 263 */
232 264 #define PCIX_CONF_COMM 0x42
233 265 #define PCIX_COMM_RELAXED 0x0002
234 266
235 267 /*
236 268 * Miscellaneous Host Control Register, in PCI config space
237 269 */
238 270 #define PCI_CONF_BGE_MHCR 0x68
239 271 #define MHCR_CHIP_REV_MASK 0xffff0000
272 +#define MHCR_CHIP_REV_SHIFT 16
240 273 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
241 274 #define MHCR_MASK_INTERRUPT_MODE 0x00000100
242 275 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
243 276 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040
244 277 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020
245 278 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010
246 279 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008
247 280 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004
248 281 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
249 282 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001
250 283
251 -#define MHCR_CHIP_REV_5700_B0 0x71000000
252 -#define MHCR_CHIP_REV_5700_B2 0x71020000
253 -#define MHCR_CHIP_REV_5700_B3 0x71030000
254 -#define MHCR_CHIP_REV_5700_C0 0x72000000
255 -#define MHCR_CHIP_REV_5700_C1 0x72010000
256 -#define MHCR_CHIP_REV_5700_C2 0x72020000
284 +#define MHCR_CHIP_REV_5703_A0 0x1000
285 +#define MHCR_CHIP_REV_5704_A0 0x2000
286 +#define MHCR_CHIP_REV_5751_A0 0x4000
287 +#define MHCR_CHIP_REV_5721_A0 0x4100
288 +#define MHCR_CHIP_REV_5755_A0 0xa000
289 +#define MHCR_CHIP_REV_5755_A1 0xa001
290 +#define MHCR_CHIP_REV_5719_A0 0x05719000
291 +#define MHCR_CHIP_REV_5720_A0 0x05720000
257 292
258 -#define MHCR_CHIP_REV_5701_A0 0x00000000
259 -#define MHCR_CHIP_REV_5701_A2 0x00020000
260 -#define MHCR_CHIP_REV_5701_A3 0x00030000
261 -#define MHCR_CHIP_REV_5701_A5 0x01050000
293 +#define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) >> 12)
294 +#define MHCR_CHIP_ASIC_REV_5700 0x07
295 +#define MHCR_CHIP_ASIC_REV_5701 0x00
296 +#define MHCR_CHIP_ASIC_REV_5703 0x01
297 +#define MHCR_CHIP_ASIC_REV_5704 0x02
298 +#define MHCR_CHIP_ASIC_REV_5705 0x03
299 +#define MHCR_CHIP_ASIC_REV_5750 0x04
300 +#define MHCR_CHIP_ASIC_REV_5752 0x06
301 +#define MHCR_CHIP_ASIC_REV_5780 0x08
302 +#define MHCR_CHIP_ASIC_REV_5714 0x09
303 +#define MHCR_CHIP_ASIC_REV_5755 0x0a
304 +#define MHCR_CHIP_ASIC_REV_5787 0x0b
305 +#define MHCR_CHIP_ASIC_REV_5906 0x0c
306 +#define MHCR_CHIP_ASIC_REV_PRODID 0x0f
307 +#define MHCR_CHIP_ASIC_REV_5784 0x5784
308 +#define MHCR_CHIP_ASIC_REV_5761 0x5761
309 +#define MHCR_CHIP_ASIC_REV_5785 0x5785
310 +#define MHCR_CHIP_ASIC_REV_5717 0x5717
311 +#define MHCR_CHIP_ASIC_REV_5719 0x5719
312 +#define MHCR_CHIP_ASIC_REV_5720 0x5720
313 +#define MHCR_CHIP_ASIC_REV_57780 0x57780
314 +#define MHCR_CHIP_ASIC_REV_57765 0x57785
315 +#define MHCR_CHIP_ASIC_REV_57766 0x57766
262 316
263 -#define MHCR_CHIP_REV_5702_A0 0x10000000
264 -#define MHCR_CHIP_REV_5702_A1 0x10010000
265 -#define MHCR_CHIP_REV_5702_A2 0x10020000
266 -
267 -#define MHCR_CHIP_REV_5703_A0 0x10000000
268 -#define MHCR_CHIP_REV_5703_A1 0x10010000
269 -#define MHCR_CHIP_REV_5703_A2 0x10020000
270 -#define MHCR_CHIP_REV_5703_B0 0x11000000
271 -#define MHCR_CHIP_REV_5703_B1 0x11010000
272 -
273 -#define MHCR_CHIP_REV_5704_A0 0x20000000
274 -#define MHCR_CHIP_REV_5704_A1 0x20010000
275 -#define MHCR_CHIP_REV_5704_A2 0x20020000
276 -#define MHCR_CHIP_REV_5704_A3 0x20030000
277 -#define MHCR_CHIP_REV_5704_B0 0x21000000
278 -
279 -#define MHCR_CHIP_REV_5705_A0 0x30000000
280 -#define MHCR_CHIP_REV_5705_A1 0x30010000
281 -#define MHCR_CHIP_REV_5705_A2 0x30020000
282 -#define MHCR_CHIP_REV_5705_A3 0x30030000
283 -#define MHCR_CHIP_REV_5705_A5 0x30050000
284 -
285 -#define MHCR_CHIP_REV_5782_A0 0x30030000
286 -#define MHCR_CHIP_REV_5782_A1 0x30030088
287 -
288 -#define MHCR_CHIP_REV_5788_A1 0x30050000
289 -
290 -#define MHCR_CHIP_REV_5751_A0 0x40000000
291 -#define MHCR_CHIP_REV_5751_A1 0x40010000
292 -
293 -#define MHCR_CHIP_REV_5721_A0 0x41000000
294 -#define MHCR_CHIP_REV_5721_A1 0x41010000
295 -
296 -#define MHCR_CHIP_REV_5714_A0 0x50000000
297 -#define MHCR_CHIP_REV_5714_A1 0x90010000
298 -
299 -#define MHCR_CHIP_REV_5715_A0 0x50000000
300 -#define MHCR_CHIP_REV_5715_A1 0x90010000
301 -
302 -#define MHCR_CHIP_REV_5715S_A0 0x50000000
303 -#define MHCR_CHIP_REV_5715S_A1 0x90010000
304 -
305 -#define MHCR_CHIP_REV_5754_A0 0xb0000000
306 -#define MHCR_CHIP_REV_5754_A1 0xb0010000
307 -
308 -#define MHCR_CHIP_REV_5787_A0 0xb0000000
309 -#define MHCR_CHIP_REV_5787_A1 0xb0010000
310 -#define MHCR_CHIP_REV_5787_A2 0xb0020000
311 -
312 -#define MHCR_CHIP_REV_5755_A0 0xa0000000
313 -#define MHCR_CHIP_REV_5755_A1 0xa0010000
314 -
315 -#define MHCR_CHIP_REV_5906_A0 0xc0000000
316 -#define MHCR_CHIP_REV_5906_A1 0xc0010000
317 -#define MHCR_CHIP_REV_5906_A2 0xc0020000
318 -
319 -#define MHCR_CHIP_REV_5723_A0 0xf0000000
320 -#define MHCR_CHIP_REV_5723_A1 0xf0010000
321 -#define MHCR_CHIP_REV_5723_A2 0xf0020000
322 -#define MHCR_CHIP_REV_5723_B0 0xf1000000
323 -
324 -#define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000)
325 -#define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28)
326 -#define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28)
327 -#define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28)
328 -#define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28)
329 -#define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28)
330 -#define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28)
331 -#define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28)
332 -#define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28)
333 -#define MHCR_CHIP_ASIC_REV_5754 (0xb << 28)
334 -#define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28)
335 -#define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28)
336 -#define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28)
337 -#define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28)
338 -#define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28)
339 -
340 -
341 317 /*
342 318 * PCI DMA read/write Control Register, in PCI config space
343 319 *
344 320 * Note that several fields previously defined here have been deleted
345 321 * as they are not implemented in the 5703/4.
346 322 *
347 323 * Note: the value of this register is critical. It is possible to
348 324 * cause various unpleasant effects (DTOs, transaction deadlock, etc)
349 325 * by programming the wrong value. The value #defined below has been
350 326 * tested and shown to avoid all known problems. If it is to be changed,
351 327 * correct operation must be reverified on all supported platforms.
352 328 *
353 329 * In particular, we set both watermark fields to 2xCacheLineSize (128)
354 330 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
355 331 * with Tomatillo's internal pipelines, that otherwise result in stalls,
356 332 * repeated retries, and DTOs.
357 333 */
358 334 #define PCI_CONF_BGE_PDRWCR 0x6c
359 335 #define PDRWCR_RWCMD_MASK 0xFF000000
360 336 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000
361 337 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000
362 338 #define PDRWCR_READ_WATERMARK_MASK 0x00070000
363 339 #define PDRWCR_CONCURRENCY_MASK 0x0000c000
364 340 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000
365 341 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000
366 342 #define PDRWCR_MIN_BEAT_MASK 0x000000ff
367 343
368 344 /*
369 345 * These are the actual values to be put into the fields shown above
370 346 */
371 347 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */
372 348 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */
373 349 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */
374 350 #define PDRWCR_MIN_BEATS 0x00000000
375 351
376 352 #define PDRWCR_VAR_DEFAULT 0x761b0000
377 353 #define PDRWCR_VAR_5721 0x76180000
378 354 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */
379 355 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */
380 356 #define PDRWCR_VAR_5717 0x00380000
381 357
382 358 /*
383 359 * PCI State Register, in PCI config space
384 360 *
385 361 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
386 362 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
387 363 */
388 364 #define PCI_CONF_BGE_PCISTATE 0x70
389 365 #define PCISTATE_RETRY_SAME_DMA 0x00002000
390 366 #define PCISTATE_FLAT_VIEW 0x00000100
391 367 #define PCISTATE_EXT_ROM_RETRY 0x00000040
392 368 #define PCISTATE_EXT_ROM_ENABLE 0x00000020
393 369 #define PCISTATE_BUS_IS_32_BIT 0x00000010
394 370 #define PCISTATE_BUS_IS_FAST 0x00000008
395 371 #define PCISTATE_BUS_IS_PCI 0x00000004
396 372 #define PCISTATE_INTA_STATE 0x00000002
397 373 #define PCISTATE_FORCE_RESET 0x00000001
398 374
399 375 /*
400 376 * PCI Clock Control Register, in PCI config space
401 377 */
402 378 #define PCI_CONF_BGE_CLKCTL 0x74
403 379 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000
404 380 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000
405 381 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000
406 382 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000
407 383 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000
408 384 #define CLKCTL_PCIE_A0_FIX 0x00101000
409 385
410 386 /*
411 387 * Dual MAC Control Register, in PCI config space
412 388 */
413 389 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8
414 390 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */
415 391 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */
416 392
417 393 /*
418 394 * Register Indirect Access Address Register, 0x78 in PCI config
419 395 * space. Once this is set, accesses to the Register Indirect
420 396 * Access Data Register (0x80) refer to the register whose address
421 397 * is given by *this* register. This allows access to all the
422 398 * operating registers, while using only config space accesses.
423 399 *
424 400 * Note that the address written to the RIIAR should lie in one
425 401 * of the following ranges:
426 402 * 0x00000000 <= address < 0x00008000 (regular registers)
427 403 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
428 404 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
429 405 * 0x00038000 <= address < 0x00038800 (RxRISC ROM)
430 406 */
431 407 #define PCI_CONF_BGE_RIAAR 0x78
432 408 #define PCI_CONF_BGE_RIADR 0x80
433 409
434 410 #define RIAAR_REGISTER_MIN 0x00000000
435 411 #define RIAAR_REGISTER_MAX 0x00008000
436 412 #define RIAAR_RX_SCRATCH_MIN 0x00030000
437 413 #define RIAAR_RX_SCRATCH_MAX 0x00034000
438 414 #define RIAAR_TX_SCRATCH_MIN 0x00034000
439 415 #define RIAAR_TX_SCRATCH_MAX 0x00038000
440 416 #define RIAAR_RXROM_MIN 0x00038000
441 417 #define RIAAR_RXROM_MAX 0x00038800
442 418
443 419 /*
444 420 * Memory Window Base Address Register, 0x7c in PCI config space
445 421 * Once this is set, accesses to the Memory Window Data Access Register
446 422 * (0x84) refer to the word of NIC-local memory whose address is given
447 423 * by this register. When used in this way, the whole of the address
448 424 * written to this register is significant.
449 425 *
450 426 * This register also provides the 32K-aligned base address for a 32K
451 427 * region of NIC-local memory that the host can directly address in
452 428 * the upper 32K of the 64K of PCI memory space allocated to the chip.
453 429 * In this case, the bottom 15 bits of the register are ignored.
454 430 *
455 431 * Note that the address written to the MWBAR should lie in the range
456 432 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M
457 433 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
458 434 * memory were present, but it's only supported on the 5700, not the
459 435 * 5701/5703/5704.
460 436 */
461 437 #define PCI_CONF_BGE_MWBAR 0x7c
462 438 #define PCI_CONF_BGE_MWDAR 0x84
463 439 #define MWBAR_GRANULARITY 0x00008000 /* 32k */
464 440 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1)
465 441 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */
466 442
467 443 /*
468 444 * The PCI express device control register and device status register
469 445 * which are only applicable on BCM5751 and BCM5721.
470 446 */
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471 447 #define PCI_CONF_DEV_CTRL 0xd8
472 448 #define PCI_CONF_DEV_CTRL_5723 0xd4
473 449 #define READ_REQ_SIZE_MAX 0x5000
474 450 #define DEV_CTRL_NO_SNOOP 0x0800
475 451 #define DEV_CTRL_RELAXED 0x0010
476 452
477 453 #define PCI_CONF_DEV_STUS 0xda
478 454 #define PCI_CONF_DEV_STUS_5723 0xd6
479 455 #define DEVICE_ERROR_STUS 0xf
480 456
457 +#define PCI_CONF_PRODID_ASICREV 0x000000bc
458 +#define PCI_CONF_GEN2_PRODID_ASICREV 0x000000f4
459 +#define PCI_CONF_GEN15_PRODID_ASICREV 0x000000fc
460 +
481 461 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */
482 462
483 463 /*
484 464 * Where to find things in NIC-local (on-chip) memory
485 465 */
486 466 #define NIC_MEM_SEND_RINGS 0x0100
487 467 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring))
488 468 #define NIC_MEM_RECV_RINGS 0x0200
489 469 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring))
490 470 #define NIC_MEM_STATISTICS 0x0300
491 471 #define NIC_MEM_STATISTICS_SIZE 0x0800
492 472 #define NIC_MEM_STATUS_BLOCK 0x0b00
493 473 #define NIC_MEM_STATUS_SIZE 0x0050
494 474 #define NIC_MEM_GENCOMM 0x0b50
495 475
496 476
497 477 /*
498 478 * Note: the (non-bogus) values below are appropriate for systems
499 479 * without external memory. They would be different on a 5700 with
500 480 * external memory.
501 481 *
502 482 * Note: The higher send ring addresses and the mini ring shadow
503 483 * buffer address are dummies - systems without external memory
504 484 * are limited to 4 send rings and no mini receive ring.
505 485 */
506 486 #define NIC_MEM_SHADOW_DMA 0x2000
507 487 #define NIC_MEM_SHADOW_SEND_1_4 0x4000
508 488 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */
509 489 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */
510 490 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */
511 491 #define NIC_MEM_SHADOW_BUFF_STD 0x6000
512 492 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000
513 493 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000
514 494 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */
515 495 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots))
516 496
517 497 /*
518 498 * Put this in the GENCOMM port to tell the firmware not to run PXE
519 499 */
520 500 #define T3_MAGIC_NUMBER 0x4b657654u
521 501
522 502 /*
523 503 * The remaining registers appear in the low 32K of regular
524 504 * PCI Memory Address Space
525 505 */
526 506
527 507 /*
528 508 * All the state machine control registers below have at least a
529 509 * <RESET> bit and an <ENABLE> bit as defined below. Some also
530 510 * have an <ATTN_ENABLE> bit.
531 511 */
532 512 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004
533 513 #define STATE_MACHINE_ENABLE_BIT 0x00000002
534 514 #define STATE_MACHINE_RESET_BIT 0x00000001
535 515
536 516 #define TRANSMIT_MAC_MODE_REG 0x045c
537 517 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00
538 518 #define SEND_DATA_COMPLETION_MODE_REG 0x1000
539 519 #define SEND_BD_SELECTOR_MODE_REG 0x1400
540 520 #define SEND_BD_INITIATOR_MODE_REG 0x1800
541 521 #define SEND_BD_COMPLETION_MODE_REG 0x1c00
542 522
543 523 #define RECEIVE_MAC_MODE_REG 0x0468
544 524 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000
545 525 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400
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546 526 #define RCV_DATA_COMPLETION_MODE_REG 0x2800
547 527 #define RCV_BD_INITIATOR_MODE_REG 0x2c00
548 528 #define RCV_BD_COMPLETION_MODE_REG 0x3000
549 529 #define RCV_LIST_SELECTOR_MODE_REG 0x3400
550 530
551 531 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800
552 532 #define HOST_COALESCE_MODE_REG 0x3c00
553 533 #define MEMORY_ARBITER_MODE_REG 0x4000
554 534 #define BUFFER_MANAGER_MODE_REG 0x4400
555 535 #define READ_DMA_MODE_REG 0x4800
536 +#define READ_DMA_RESERVED_CONTROL_REG 0x4900
556 537 #define WRITE_DMA_MODE_REG 0x4c00
557 538 #define DMA_COMPLETION_MODE_REG 0x6400
558 539
559 540 /*
560 541 * Other bits in some of the above state machine control registers
561 542 */
562 543
563 544 /*
564 545 * Transmit MAC Mode Register
565 546 * (TRANSMIT_MAC_MODE_REG, 0x045c)
566 547 */
548 +#define TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
549 +#define TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
550 +#define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100
567 551 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040
568 552 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
569 553 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
570 554
571 555 /*
572 556 * Receive MAC Mode Register
573 557 * (RECEIVE_MAC_MODE_REG, 0x0468)
574 558 */
575 559 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400
576 560 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200
577 561 #define RECEIVE_MODE_PROMISCUOUS 0x00000100
578 562 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080
579 563 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040
580 564 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020
581 565 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010
582 566 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004
583 567
584 568 /*
585 569 * Receive BD Initiator Mode Register
586 570 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
587 571 *
588 572 * Each of these bits controls whether ATTN is asserted
589 573 * on a particular condition
590 574 */
591 575 #define RCV_BD_DISABLED_RING_ATTN 0x00000004
592 576
593 577 /*
594 578 * Receive Data & Receive BD Initiator Mode Register
595 579 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
596 580 *
597 581 * Each of these bits controls whether ATTN is asserted
598 582 * on a particular condition
599 583 */
600 584 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010
601 585 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008
602 586 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004
603 587
604 588 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c
605 589
606 590 /*
607 591 * Host Coalescing Mode Control Register
608 592 * (HOST_COALESCE_MODE_REG, 0x3c00)
609 593 */
610 594 #define COALESCE_64_BYTE_RINGS 12
611 595 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000
612 596 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800
613 597 #define COALESCE_CLR_TICKS_TX 0x00000400
614 598 #define COALESCE_CLR_TICKS_RX 0x00000200
615 599 #define COALESCE_32_BYTE_STATUS 0x00000100
616 600 #define COALESCE_64_BYTE_STATUS 0x00000080
617 601 #define COALESCE_NOW 0x00000008
618 602
619 603 /*
620 604 * Memory Arbiter Mode Register
621 605 * (MEMORY_ARBITER_MODE_REG, 0x4000)
622 606 */
623 607 #define MEMORY_ARBITER_ENABLE 0x00000002
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624 608
625 609 /*
626 610 * Buffer Manager Mode Register
627 611 * (BUFFER_MANAGER_MODE_REG, 0x4400)
628 612 *
629 613 * In addition to the usual error-attn common to most state machines
630 614 * this register has a separate bit for attn on running-low-on-mbufs
631 615 */
632 616 #define BUFF_MGR_TEST_MODE 0x00000008
633 617 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
618 +#define BUFF_MGR_NO_TX_UNDERRUN 0x80000000
634 619
635 620 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014
636 621
637 622 /*
638 623 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
639 - * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
624 + * 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
625 + * WRITE_DMA_MODE_REG, 0x4c00)
640 626 *
641 627 * These registers each contain a 2-bit priority field, which controls
642 628 * the relative priority of that type of DMA (read vs. write vs. MSI),
643 629 * and a set of bits that control whether ATTN is asserted on each
644 630 * particular condition
645 631 */
646 632 #define DMA_PRIORITY_MASK 0xc0000000
647 633 #define DMA_PRIORITY_SHIFT 30
648 634 #define ALL_DMA_ATTN_BITS 0x000003fc
649 635
636 +#define RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
637 +#define RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
638 +#define RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
639 +#define RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
640 +#define RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
641 +#define RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
642 +#define RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
643 +
644 +
650 645 /*
651 646 * BCM5755, 5755M, 5906, 5906M only
652 647 * 1 - Enable Fix. Device will send out the status block before
653 648 * the interrupt message
654 649 * 0 - Disable fix. Device will send out the interrupt message
655 650 * before the status block
656 651 */
657 652 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000
658 653
654 +/* 5720 only */
655 +#define DMA_H2BNC_VLAN_DET 0x20000000
656 +
657 +
659 658 /*
660 659 * End of state machine control register definitions
661 660 */
662 661
663 662
664 663 /*
665 664 * High priority mailbox registers.
666 665 * Mailbox Registers (8 bytes each, but high half unused)
667 666 */
668 667 #define INTERRUPT_MBOX_0_REG 0x0200
669 668 #define INTERRUPT_MBOX_1_REG 0x0208
670 669 #define INTERRUPT_MBOX_2_REG 0x0210
671 670 #define INTERRUPT_MBOX_3_REG 0x0218
672 671 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n))
673 672
674 673 /*
675 674 * Low priority mailbox registers, for BCM5906, BCM5906M.
676 675 */
677 676 #define INTERRUPT_LP_MBOX_0_REG 0x5800
678 677
679 678 /*
680 679 * Ring Producer/Consumer Index (Mailbox) Registers
681 680 */
682 681 #define RECV_STD_PROD_INDEX_REG 0x0268
683 682 #define RECV_JUMBO_PROD_INDEX_REG 0x0270
684 683 #define RECV_MINI_PROD_INDEX_REG 0x0278
685 684 #define RECV_RING_CONS_INDEX_REGS 0x0280
686 685 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300
687 686 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380
688 687
689 688 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring))
690 689 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring))
691 690 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring))
692 691
693 692 /*
694 693 * Ethernet MAC Mode Register
695 694 */
696 695 #define ETHERNET_MAC_MODE_REG 0x0400
697 696 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000
698 697 #define ETHERNET_MODE_ENABLE_RDE 0x00400000
699 698 #define ETHERNET_MODE_ENABLE_TDE 0x00200000
700 699 #define ETHERNET_MODE_ENABLE_MIP 0x00100000
701 700 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000
702 701 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000
703 702 #define ETHERNET_MODE_SEND_CFGS 0x00020000
704 703 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000
705 704 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000
706 705 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000
707 706 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000
708 707 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000
709 708 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800
710 709 #define ETHERNET_MODE_LINK_POLARITY 0x00000400
711 710 #define ETHERNET_MODE_MAX_DEFER 0x00000200
712 711 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100
713 712 #define ETHERNET_MODE_TAGGED_MODE 0x00000080
714 713 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010
715 714 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c
716 715 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c
717 716 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008
718 717 #define ETHERNET_MODE_PORTMODE_MII 0x00000004
719 718 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000
720 719 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002
721 720 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001
722 721
723 722 /*
724 723 * Ethernet MAC Status & Event Registers
725 724 */
726 725 #define ETHERNET_MAC_STATUS_REG 0x0404
727 726 #define ETHERNET_STATUS_MI_INT 0x00800000
728 727 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000
729 728 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000
730 729 #define ETHERNET_STATUS_PCS_ERROR 0x00000400
731 730 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010
732 731 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008
733 732 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004
734 733 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002
735 734 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001
736 735
737 736 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408
738 737 #define ETHERNET_EVENT_MI_INT 0x00800000
739 738 #define ETHERNET_EVENT_LINK_INT 0x00001000
740 739 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400
741 740
742 741 /*
743 742 * Ethernet MAC LED Control Register
744 743 *
745 744 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and
746 745 * the external LED driver circuitry is wired up to assume that this mode
747 746 * will always be selected. Software must not change it!
748 747 */
749 748 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c
750 749 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000
751 750 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000
752 751 #define LED_CONTROL_LED_MODE_MASK 0x00001800
753 752 #define LED_CONTROL_LED_MODE_5700 0x00000000
754 753 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */
755 754 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000
756 755 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800
757 756 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400
758 757 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200
759 758 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100
760 759 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080
761 760 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040
762 761 #define LED_CONTROL_TRAFFIC_LED 0x00000020
763 762 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010
764 763 #define LED_CONTROL_10MBPS_LED 0x00000008
765 764 #define LED_CONTROL_100MBPS_LED 0x00000004
766 765 #define LED_CONTROL_1000MBPS_LED 0x00000002
767 766 #define LED_CONTROL_OVERRIDE_LINK 0x00000001
768 767 #define LED_CONTROL_DEFAULT 0x02000800
769 768
770 769 /*
771 770 * MAC Address registers
772 771 *
773 772 * These four eight-byte registers each hold one unicast address
774 773 * (six bytes), right justified & zero-filled on the left.
775 774 * They will normally all be set to the same value, as a station
776 775 * usually only has one h/w address. The value in register 0 is
777 776 * used for pause packets; any of the four can be specified for
778 777 * substitution into other transmitted packets if required.
779 778 */
780 779 #define MAC_ADDRESS_0_REG 0x0410
781 780 #define MAC_ADDRESS_1_REG 0x0418
782 781 #define MAC_ADDRESS_2_REG 0x0420
783 782 #define MAC_ADDRESS_3_REG 0x0428
784 783
785 784 #define MAC_ADDRESS_REG(n) (0x0410+8*(n))
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786 785 #define MAC_ADDRESS_REGS_MAX 4
787 786
788 787 /*
789 788 * More MAC Registers ...
790 789 */
791 790 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438
792 791 #define MAC_RX_MTU_SIZE_REG 0x043c
793 792 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
794 793 #define MAC_TX_LENGTHS_REG 0x0464
795 794 #define MAC_TX_LENGTHS_DEFAULT 0x00002620
795 +#define MAC_TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
796 +#define MAC_TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
796 797
797 798 /*
798 799 * MII access registers
799 800 */
800 801 #define MI_COMMS_REG 0x044c
801 802 #define MI_COMMS_START 0x20000000
802 803 #define MI_COMMS_READ_FAILED 0x10000000
803 804 #define MI_COMMS_COMMAND_MASK 0x0c000000
804 805 #define MI_COMMS_COMMAND_READ 0x08000000
805 806 #define MI_COMMS_COMMAND_WRITE 0x04000000
806 807 #define MI_COMMS_ADDRESS_MASK 0x03e00000
807 808 #define MI_COMMS_ADDRESS_SHIFT 21
808 809 #define MI_COMMS_REGISTER_MASK 0x001f0000
809 810 #define MI_COMMS_REGISTER_SHIFT 16
810 811 #define MI_COMMS_DATA_MASK 0x0000ffff
811 812 #define MI_COMMS_DATA_SHIFT 0
812 813
813 814 #define MI_STATUS_REG 0x0450
814 815 #define MI_STATUS_10MBPS 0x00000002
815 816 #define MI_STATUS_LINK 0x00000001
816 817
817 818 #define MI_MODE_REG 0x0454
818 819 #define MI_MODE_CLOCK_MASK 0x001f0000
819 820 #define MI_MODE_AUTOPOLL 0x00000010
820 821 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002
821 822 #define MI_MODE_DEFAULT 0x000c0000
822 823
823 824 #define MI_AUTOPOLL_STATUS_REG 0x0458
824 825 #define MI_AUTOPOLL_ERROR 0x00000001
825 826
826 827 #define TRANSMIT_MAC_STATUS_REG 0x0460
827 828 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020
828 829 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010
829 830 #define TRANSMIT_STATUS_LINK_UP 0x00000008
830 831 #define TRANSMIT_STATUS_SENT_XON 0x00000004
831 832 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002
832 833 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001
833 834
834 835 #define RECEIVE_MAC_STATUS_REG 0x046c
835 836 #define RECEIVE_STATUS_RCVD_XON 0x00000004
836 837 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002
837 838 #define RECEIVE_STATUS_SENT_XOFF 0x00000001
838 839
839 840 /*
840 841 * These four-byte registers constitute a hash table for deciding
841 842 * whether to accept incoming multicast packets. The bits are
842 843 * numbered in big-endian fashion, from hash 0 => the MSB of
843 844 * register 0 to hash 127 => the LSB of the highest-numbered
844 845 * register.
845 846 *
846 847 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if
847 848 * enabled by setting the appropriate bit in the Rx MAC mode
848 849 * register. Otherwise, and on all earlier chips, the table
849 850 * is only 128 bits (registers 0-3).
850 851 */
851 852 #define MAC_HASH_0_REG 0x0470
852 853 #define MAC_HASH_1_REG 0x0474
853 854 #define MAC_HASH_2_REG 0x0478
854 855 #define MAC_HASH_3_REG 0x047c
855 856 #define MAC_HASH_4_REG 0x????
856 857 #define MAC_HASH_5_REG 0x????
857 858 #define MAC_HASH_6_REG 0x????
858 859 #define MAC_HASH_7_REG 0x????
859 860 #define MAC_HASH_REG(n) (0x470+4*(n))
860 861
861 862 /*
862 863 * Receive Rules Registers: 16 pairs of control+mask/value pairs
863 864 */
864 865 #define RCV_RULES_CONTROL_0_REG 0x0480
865 866 #define RCV_RULES_MASK_0_REG 0x0484
866 867 #define RCV_RULES_CONTROL_15_REG 0x04f8
867 868 #define RCV_RULES_MASK_15_REG 0x04fc
868 869 #define RCV_RULES_CONFIG_REG 0x0500
869 870 #define RCV_RULES_CONFIG_DEFAULT 0x00000008
870 871
871 872 #define RECV_RULES_NUM_MAX 16
872 873 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule))
873 874 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule))
874 875
875 876 #define RECV_RULE_CTL_ENABLE 0x80000000
876 877 #define RECV_RULE_CTL_AND 0x40000000
877 878 #define RECV_RULE_CTL_P1 0x20000000
878 879 #define RECV_RULE_CTL_P2 0x10000000
879 880 #define RECV_RULE_CTL_P3 0x08000000
880 881 #define RECV_RULE_CTL_MASK 0x04000000
881 882 #define RECV_RULE_CTL_DISCARD 0x02000000
882 883 #define RECV_RULE_CTL_MAP 0x01000000
883 884 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000
884 885 #define RECV_RULE_CTL_OP 0x00030000
885 886 #define RECV_RULE_CTL_OP_EQ 0x00000000
886 887 #define RECV_RULE_CTL_OP_NEQ 0x00010000
887 888 #define RECV_RULE_CTL_OP_GREAT 0x00020000
888 889 #define RECV_RULE_CTL_OP_LESS 0x00030000
889 890 #define RECV_RULE_CTL_HEADER 0x0000e000
890 891 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000
891 892 #define RECV_RULE_CTL_HEADER_IP 0x00002000
892 893 #define RECV_RULE_CTL_HEADER_TCP 0x00004000
893 894 #define RECV_RULE_CTL_HEADER_UDP 0x00006000
894 895 #define RECV_RULE_CTL_HEADER_DATA 0x00008000
895 896 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00
896 897 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \
897 898 RECV_RULE_CTL_CLASS_BITS)
898 899 #define RECV_RULE_CTL_OFFSET 0x000000ff
899 900
900 901 /*
901 902 * Receive Rules definition
902 903 */
903 904 #define ETHERHEADER_DEST_OFFSET 0x00
904 905 #define IPHEADER_PROTO_OFFSET 0x08
905 906 #define IPHEADER_SIP_OFFSET 0x0c
906 907 #define IPHEADER_DIP_OFFSET 0x10
907 908 #define TCPHEADER_SPORT_OFFSET 0x00
908 909 #define TCPHEADER_DPORT_OFFSET 0x02
909 910 #define UDPHEADER_SPORT_OFFSET 0x00
910 911 #define UDPHEADER_DPORT_OFFSET 0x02
911 912
912 913 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \
913 914 RECV_RULE_CTL_CLASS((ring)))
914 915
915 916 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK)
916 917
917 918 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \
918 919 RECV_RULE_CTL_HEADER_FRAME | \
919 920 ETHERHEADER_DEST_OFFSET)
920 921
921 922 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \
922 923 RECV_RULE_CTL_HEADER_FRAME | \
923 924 ETHERHEADER_DEST_OFFSET + 4)
924 925
925 926 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
926 927 IPHEADER_DIP_OFFSET)
927 928
928 929 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
929 930 IPHEADER_SIP_OFFSET)
930 931
931 932 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \
932 933 RECV_RULE_CTL_HEADER_IP | \
933 934 IPHEADER_PROTO_OFFSET)
934 935
935 936 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
936 937 RECV_RULE_CTL_HEADER_TCP | \
937 938 TCPHEADER_SPORT_OFFSET)
938 939
939 940 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
940 941 RECV_RULE_CTL_HEADER_TCP | \
941 942 TCPHEADER_DPORT_OFFSET)
942 943
943 944 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
944 945 RECV_RULE_CTL_HEADER_UDP | \
945 946 UDPHEADER_SPORT_OFFSET)
946 947
947 948 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
948 949 RECV_RULE_CTL_HEADER_UDP | \
949 950 UDPHEADER_DPORT_OFFSET)
950 951
951 952 /*
952 953 * 1000BaseX low-level access registers
953 954 */
954 955 #define MAC_GIGABIT_PCS_TEST_REG 0x0440
955 956 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000
956 957 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff
957 958 #define TX_1000BASEX_AUTONEG_REG 0x0444
958 959 #define RX_1000BASEX_AUTONEG_REG 0x0448
959 960
960 961 /*
961 962 * Autoneg code bits for the 1000BASE-X AUTONEG registers
962 963 */
963 964 #define AUTONEG_CODE_PAUSE 0x00008000
964 965 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000
965 966 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000
966 967 #define AUTONEG_CODE_NEXT_PAGE 0x00000080
967 968 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040
968 969 #define AUTONEG_CODE_FAULT_MASK 0x00000030
969 970 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030
970 971 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020
971 972 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010
972 973 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001
973 974
974 975 /*
975 976 * SerDes Registers (5703S/5704S only)
976 977 */
977 978 #define SERDES_CONTROL_REG 0x0590
978 979 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000
979 980 #define SERDES_CONTROL_COMMA_DETECT 0x00010000
980 981 #define SERDES_CONTROL_TX_DISABLE 0x00004000
981 982 #define SERDES_STATUS_REG 0x0594
982 983 #define SERDES_STATUS_COMMA_DETECTED 0x00000100
983 984 #define SERDES_STATUS_RXSTAT 0x000000ff
984 985
985 986 /*
986 987 * SGMII Status Register (5717/5718 only)
987 988 */
988 989 #define SGMII_STATUS_REG 0x5B4
989 990 #define MEDIA_SELECTION_MODE 0x00000100
990 991
991 992 /*
992 993 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only)
993 994 */
994 995 #define STAT_IFHCOUT_OCTETS_REG 0x0800
995 996 #define STAT_ETHER_COLLIS_REG 0x0808
996 997 #define STAT_OUTXON_SENT_REG 0x080c
997 998 #define STAT_OUTXOFF_SENT_REG 0x0810
998 999 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818
999 1000 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c
1000 1001 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820
1001 1002 #define STAT_DOT3_DEFERED_TX_REG 0x0824
1002 1003 #define STAT_DOT3_EXCE_COLLI_REG 0x082c
1003 1004 #define STAT_DOT3_LATE_COLLI_REG 0x0830
1004 1005 #define STAT_IFHCOUT_UPKGS_REG 0x086c
1005 1006 #define STAT_IFHCOUT_MPKGS_REG 0x0870
1006 1007 #define STAT_IFHCOUT_BPKGS_REG 0x0874
1007 1008
1008 1009 #define STAT_IFHCIN_OCTETS_REG 0x0880
1009 1010 #define STAT_ETHER_FRAGMENT_REG 0x0888
1010 1011 #define STAT_IFHCIN_UPKGS_REG 0x088c
1011 1012 #define STAT_IFHCIN_MPKGS_REG 0x0890
1012 1013 #define STAT_IFHCIN_BPKGS_REG 0x0894
1013 1014
1014 1015 #define STAT_DOT3_FCS_ERR_REG 0x0898
1015 1016 #define STAT_DOT3_ALIGN_ERR_REG 0x089c
1016 1017 #define STAT_XON_PAUSE_RX_REG 0x08a0
1017 1018 #define STAT_XOFF_PAUSE_RX_REG 0x08a4
1018 1019 #define STAT_MAC_CTRL_RX_REG 0x08a8
1019 1020 #define STAT_XOFF_STATE_ENTER_REG 0x08ac
1020 1021 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0
1021 1022 #define STAT_ETHER_JABBERS_REG 0x08b4
1022 1023 #define STAT_ETHER_UNDERSIZE_REG 0x08b8
1023 1024 #define SIZE_OF_STATISTIC_REG 0x1B
1024 1025 /*
1025 1026 * Send Data Initiator Registers
1026 1027 */
1027 1028 #define SEND_INIT_STATS_CONTROL_REG 0x0c08
1028 1029 #define SEND_INIT_STATS_ZERO 0x00000010
1029 1030 #define SEND_INIT_STATS_FLUSH 0x00000008
1030 1031 #define SEND_INIT_STATS_CLEAR 0x00000004
1031 1032 #define SEND_INIT_STATS_FASTER 0x00000002
1032 1033 #define SEND_INIT_STATS_ENABLE 0x00000001
1033 1034
1034 1035 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c
1035 1036
1036 1037 /*
1037 1038 * Send Buffer Descriptor Selector Control Registers
1038 1039 */
1039 1040 #define SEND_BD_SELECTOR_STATUS_REG 0x1404
1040 1041 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408
1041 1042 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n))
1042 1043
1043 1044 /*
1044 1045 * Receive List Placement Registers
1045 1046 */
1046 1047 #define RCV_LP_CONFIG_REG 0x2010
1047 1048 #define RCV_LP_CONFIG_DEFAULT 0x00000009
1048 1049 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1)
1049 1050
1050 1051 #define RCV_LP_STATS_CONTROL_REG 0x2014
1051 1052 #define RCV_LP_STATS_ZERO 0x00000010
1052 1053 #define RCV_LP_STATS_FLUSH 0x00000008
1053 1054 #define RCV_LP_STATS_CLEAR 0x00000004
1054 1055 #define RCV_LP_STATS_FASTER 0x00000002
1055 1056 #define RCV_LP_STATS_ENABLE 0x00000001
1056 1057
1057 1058 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018
1058 1059 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000
1059 1060
1060 1061 /*
1061 1062 * Receive Data & BD Initiator Registers
1062 1063 */
1063 1064 #define RCV_INITIATOR_STATUS_REG 0x2404
1064 1065
1065 1066 /*
1066 1067 * Receive Buffer Descriptor Ring Control Block Registers
1067 1068 * NB: sixteen bytes (128 bits) each
1068 1069 */
1069 1070 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440
1070 1071 #define STD_RCV_BD_RING_RCB_REG 0x2450
1071 1072 #define MINI_RCV_BD_RING_RCB_REG 0x2460
1072 1073
1073 1074 /*
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1074 1075 * Receive Buffer Descriptor Ring Replenish Threshold Registers
1075 1076 */
1076 1077 #define MINI_RCV_BD_REPLENISH_REG 0x2c14
1077 1078 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */
1078 1079 #define STD_RCV_BD_REPLENISH_REG 0x2c18
1079 1080 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */
1080 1081 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c
1081 1082 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */
1082 1083
1083 1084 /*
1084 - * CPMU registers (5717/5718 only)
1085 + * CPMU registers (5717/5718/5719/5720 only)
1085 1086 */
1086 -#define CPMU_STATUS_REG 0x362c
1087 -#define CPMU_STATUS_FUN_NUM 0x20000000
1087 +#define CPMU_CLCK_ORIDE_REG 0x3624
1088 +#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1088 1089
1090 +#define CPMU_STATUS_REG 0x362c
1091 +#define CPMU_STATUS_FUN_NUM_5717 0x20000000
1092 +#define CPMU_STATUS_FUN_NUM_5719 0xc0000000
1093 +#define CPMU_STATUS_FUN_NUM_5719_SHIFT 30
1094 +
1095 +
1089 1096 /*
1090 1097 * Host Coalescing Engine Control Registers
1091 1098 */
1092 1099 #define RCV_COALESCE_TICKS_REG 0x3c08
1093 1100 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1094 1101 #define SEND_COALESCE_TICKS_REG 0x3c0c
1095 1102 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1096 1103 #define RCV_COALESCE_MAX_BD_REG 0x3c10
1097 1104 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1098 1105 #define SEND_COALESCE_MAX_BD_REG 0x3c14
1099 1106 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1100 1107 #define RCV_COALESCE_INT_TICKS_REG 0x3c18
1101 1108 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1102 1109 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c
1103 1110 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1104 1111 #define RCV_COALESCE_INT_BD_REG 0x3c20
1105 1112 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1106 1113 #define SEND_COALESCE_INT_BD_REG 0x3c24
1107 1114 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1108 1115 #define STATISTICS_TICKS_REG 0x3c28
1109 1116 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */
1110 1117 #define STATISTICS_HOST_ADDR_REG 0x3c30
1111 1118 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38
1112 1119 #define STATISTICS_BASE_ADDR_REG 0x3c40
1113 1120 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44
1114 1121 #define FLOW_ATTN_REG 0x3c48
1115 1122
1116 1123 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50
1117 1124 #define NIC_STD_RECV_INDEX_REG 0x3c54
1118 1125 #define NIC_MINI_RECV_INDEX_REG 0x3c58
1119 1126 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n))
1120 1127 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n))
1121 1128
1122 1129 /*
1123 1130 * Mbuf Pool Initialisation & Watermark Registers
1124 1131 *
1125 1132 * There are some conflicts in the PRM; compare the recommendations
1126 1133 * on pp. 115, 236, and 339. The values here were recommended by
1127 1134 * dkim@broadcom.com (and the PRM should be corrected soon ;-)
1128 1135 */
1129 1136 #define BUFFER_MANAGER_STATUS_REG 0x4404
1130 1137 #define MBUF_POOL_BASE_REG 0x4408
1131 1138 #define MBUF_POOL_BASE_DEFAULT 0x00008000
1132 1139 #define MBUF_POOL_BASE_5721 0x00010000
1133 1140 #define MBUF_POOL_BASE_5704 0x00010000
1134 1141 #define MBUF_POOL_BASE_5705 0x00010000
1135 1142 #define MBUF_POOL_LENGTH_REG 0x440c
1136 1143 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000
1137 1144 #define MBUF_POOL_LENGTH_5704 0x00010000
1138 1145 #define MBUF_POOL_LENGTH_5705 0x00008000
1139 1146 #define MBUF_POOL_LENGTH_5721 0x00008000
1140 1147 #define RDMA_MBUF_LOWAT_REG 0x4410
1141 1148 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050
1142 1149 #define RDMA_MBUF_LOWAT_5705 0x00000000
1143 1150 #define RDMA_MBUF_LOWAT_5906 0x00000000
1144 1151 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130
1145 1152 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000
1146 1153 #define MAC_RX_MBUF_LOWAT_REG 0x4414
1147 1154 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020
1148 1155 #define MAC_RX_MBUF_LOWAT_5705 0x00000010
1149 1156 #define MAC_RX_MBUF_LOWAT_5906 0x00000004
1150 1157 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a
1151 1158 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098
1152 1159 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b
1153 1160 #define MBUF_HIWAT_REG 0x4418
1154 1161 #define MBUF_HIWAT_DEFAULT 0x00000060
1155 1162 #define MBUF_HIWAT_5705 0x00000060
1156 1163 #define MBUF_HIWAT_5906 0x00000010
1157 1164 #define MBUF_HIWAT_5717 0x000000a0
1158 1165 #define MBUF_HIWAT_JUMBO 0x0000017c
1159 1166 #define MBUF_HIWAT_5714_JUMBO 0x00000096
1160 1167
1161 1168 /*
1162 1169 * DMA Descriptor Pool Initialisation & Watermark Registers
1163 1170 */
1164 1171 #define DMAD_POOL_BASE_REG 0x442c
1165 1172 #define DMAD_POOL_BASE_DEFAULT 0x00002000
1166 1173 #define DMAD_POOL_LENGTH_REG 0x4430
1167 1174 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000
1168 1175 #define DMAD_POOL_LOWAT_REG 0x4434
1169 1176 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */
1170 1177 #define DMAD_POOL_HIWAT_REG 0x4438
1171 1178 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */
1172 1179
1173 1180 /*
1174 1181 * More threshold/watermark registers ...
1175 1182 */
1176 1183 #define RECV_FLOW_THRESHOLD_REG 0x4458
1177 1184 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504
1178 1185 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002
1179 1186
1180 1187 /*
1181 1188 * Read/Write DMA Status Registers
1182 1189 */
1183 1190 #define READ_DMA_STATUS_REG 0x4804
1184 1191 #define WRITE_DMA_STATUS_REG 0x4c04
1185 1192
1186 1193 /*
1187 1194 * RX/TX RISC Registers
1188 1195 */
1189 1196 #define RX_RISC_MODE_REG 0x5000
1190 1197 #define RX_RISC_STATE_REG 0x5004
1191 1198 #define RX_RISC_PC_REG 0x501c
1192 1199 #define TX_RISC_MODE_REG 0x5400
1193 1200 #define TX_RISC_STATE_REG 0x5404
1194 1201 #define TX_RISC_PC_REG 0x541c
1195 1202
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1196 1203 /*
1197 1204 * V? RISC Registerss
1198 1205 */
1199 1206 #define VCPU_STATUS_REG 0x5100
1200 1207 #define VCPU_INIT_DONE 0x04000000
1201 1208 #define VCPU_DRV_RESET 0x08000000
1202 1209
1203 1210 #define VCPU_EXT_CTL 0x6890
1204 1211 #define VCPU_EXT_CTL_HALF 0x00400000
1205 1212
1213 +#define GRC_FASTBOOT_PC 0x6894
1214 +
1206 1215 #define FTQ_RESET_REG 0x5c00
1207 1216
1208 1217 #define MSI_MODE_REG 0x6000
1209 1218 #define MSI_PRI_HIGHEST 0xc0000000
1210 1219 #define MSI_MSI_ENABLE 0x00000002
1211 1220 #define MSI_ERROR_ATTENTION 0x0000001c
1212 1221
1213 1222 #define MSI_STATUS_REG 0x6004
1214 1223
1215 1224 #define MODE_CONTROL_REG 0x6800
1216 1225 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000
1217 1226 #define MODE_4X_NIC_SEND_RINGS 0x20000000
1218 1227 #define MODE_INT_ON_FLOW_ATTN 0x10000000
1219 1228 #define MODE_INT_ON_DMA_ATTN 0x08000000
1220 1229 #define MODE_INT_ON_MAC_ATTN 0x04000000
1221 1230 #define MODE_INT_ON_RXRISC_ATTN 0x02000000
1222 1231 #define MODE_INT_ON_TXRISC_ATTN 0x01000000
1223 1232 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
1224 1233 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
1234 +#define MODE_HTX2B_ENABLE 0x00040000
1225 1235 #define MODE_HOST_SEND_BDS 0x00020000
1226 1236 #define MODE_HOST_STACK_UP 0x00010000
1227 1237 #define MODE_FORCE_32_BIT_PCI 0x00008000
1238 +#define MODE_B2HRX_ENABLE 0x00008000
1228 1239 #define MODE_NO_INT_ON_RECV 0x00004000
1229 1240 #define MODE_NO_INT_ON_SEND 0x00002000
1230 1241 #define MODE_ALLOW_BAD_FRAMES 0x00000800
1231 1242 #define MODE_NO_CRC 0x00000400
1232 1243 #define MODE_NO_FRAME_CRACKING 0x00000200
1244 +#define MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1245 +#define MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1233 1246 #define MODE_WORD_SWAP_FRAME 0x00000020
1234 1247 #define MODE_BYTE_SWAP_FRAME 0x00000010
1235 1248 #define MODE_WORD_SWAP_NONFRAME 0x00000004
1236 1249 #define MODE_BYTE_SWAP_NONFRAME 0x00000002
1237 1250 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001
1238 1251
1239 1252 /*
1240 1253 * Miscellaneous Configuration Register
1241 1254 *
1242 1255 * This contains various bits relating to power control (which differ
1243 1256 * among different members of the chip family), but the important bits
1244 1257 * for our purposes are the RESET bit and the Timer Prescaler field.
1245 1258 *
1246 1259 * The RESET bit in this register serves to reset the whole chip, even
1247 1260 * including the PCI interface(!) Once it's set, the chip will not
1248 1261 * respond to ANY accesses -- not even CONFIG space -- until the reset
1249 1262 * completes internally. According to the PRM, this should take less
1250 1263 * than 100us. Any access during this period will get a bus error.
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1251 1264 *
1252 1265 * The Timer Prescaler field must be programmed so that the timer period
1253 1266 * is as near as possible to 1us. The value in this field should be
1254 1267 * the Core Clock frequency in MHz minus 1. From my reading of the PRM,
1255 1268 * the Core Clock should always be 66MHz (independently of the bus speed,
1256 1269 * at least for PCI rather than PCI-X), so this register must be set to
1257 1270 * the value 0x82 ((66-1) << 1).
1258 1271 */
1259 1272 #define CORE_CLOCK_MHZ 66
1260 1273 #define MISC_CONFIG_REG 0x6804
1261 -#define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
1274 +#define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
1262 1275 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
1263 1276 #define MISC_CONFIG_POWERDOWN 0x00100000
1264 1277 #define MISC_CONFIG_POWER_STATE 0x00060000
1265 1278 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe
1266 1279 #define MISC_CONFIG_RESET_BIT 0x00000001
1267 1280 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1)
1268 1281 #define MISC_CONFIG_EPHY_IDDQ 0x00200000
1269 1282
1270 1283 /*
1271 1284 * Miscellaneous Local Control Register (MLCR)
1272 1285 */
1273 1286 #define MISC_LOCAL_CONTROL_REG 0x6808
1274 1287 #define MLCR_PCI_CTRL_SELECT 0x10000000
1275 1288 #define MLCR_LEGACY_PCI_MODE 0x08000000
1276 1289 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000
1277 1290 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000
1278 1291 #define MLCR_SSRAM_TYPE 0x00400000
1279 1292 #define MLCR_BANK_SELECT 0x00200000
1280 1293 #define MLCR_SRAM_SIZE_MASK 0x001c0000
1281 1294 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000
1282 1295
1283 1296 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000
1284 1297 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000
1285 1298 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000
1286 1299 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000
1287 1300 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000
1288 1301 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800
1289 1302 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */
1290 1303 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */
1291 1304 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */
1292 1305
1293 1306 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */
1294 1307 #define MLCR_SET_INT 0x00000004 /* W/O */
1295 1308 #define MLCR_CLR_INT 0x00000002 /* W/O */
1296 1309 #define MLCR_INTA_STATE 0x00000001 /* R/O */
1297 1310
1298 1311 /*
1299 1312 * This value defines all GPIO bits as INPUTS, but sets their default
1300 1313 * values as outputs to HIGH, on the assumption that external circuits
1301 1314 * (if any) will probably be active-LOW with passive pullups.
1302 1315 *
1303 1316 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in
1304 1317 * just this fashion. It has to be set as an OUTPUT and driven LOW to
1305 1318 * enable writing. Otherwise, the SEEPROM is protected.
1306 1319 */
1307 1320 #define MLCR_DEFAULT 0x0101c000
1308 1321 #define MLCR_DEFAULT_5714 0x1901c000
1309 1322 #define MLCR_DEFAULT_5717 0x01000000
1310 1323
1311 1324 /*
1312 1325 * Serial EEPROM Data/Address Registers (auto-access mode)
1313 1326 */
1314 1327 #define SERIAL_EEPROM_DATA_REG 0x683c
1315 1328 #define SERIAL_EEPROM_ADDRESS_REG 0x6838
1316 1329 #define SEEPROM_ACCESS_READ 0x80000000
1317 1330 #define SEEPROM_ACCESS_WRITE 0x00000000
1318 1331 #define SEEPROM_ACCESS_COMPLETE 0x40000000
1319 1332 #define SEEPROM_ACCESS_RESET 0x20000000
1320 1333 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000
1321 1334 #define SEEPROM_ACCESS_START 0x02000000
1322 1335 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000
1323 1336 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc
1324 1337
1325 1338 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */
1326 1339 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */
1327 1340 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */
1328 1341
1329 1342 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */
1330 1343 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */
1331 1344
1332 1345 /*
1333 1346 * "Linearised" address mask, treating multiple devices as consecutive
1334 1347 */
1335 1348 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */
1336 1349
1337 1350 /*
1338 1351 * Non-Volatile Memory Interface Registers
1339 1352 * Note: on chips that support the flash interface (5702+), flash is the
1340 1353 * default and the legacy seeprom interface must be explicitly enabled
1341 1354 * if required. On older chips (5700/01), SEEPROM is the default (and
1342 1355 * only) non-volatile memory available, and these registers don't exist!
1343 1356 */
1344 1357 #define NVM_FLASH_CMD_REG 0x7000
1345 1358 #define NVM_FLASH_CMD_LAST 0x00000100
1346 1359 #define NVM_FLASH_CMD_FIRST 0x00000080
1347 1360 #define NVM_FLASH_CMD_RD 0x00000000
1348 1361 #define NVM_FLASH_CMD_WR 0x00000020
1349 1362 #define NVM_FLASH_CMD_DOIT 0x00000010
1350 1363 #define NVM_FLASH_CMD_DONE 0x00000008
1351 1364
1352 1365 #define NVM_FLASH_WRITE_REG 0x7008
1353 1366 #define NVM_FLASH_READ_REG 0x7010
1354 1367
1355 1368 #define NVM_FLASH_ADDR_REG 0x700c
1356 1369 #define NVM_FLASH_ADDR_MASK 0x00fffffc
1357 1370
1358 1371 #define NVM_CONFIG1_REG 0x7014
1359 1372 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000
1360 1373 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800
1361 1374 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780
1362 1375 #define NVM_CFG1_BUFFERED_MODE 0x00000002
1363 1376 #define NVM_CFG1_FLASH_MODE 0x00000001
1364 1377
1365 1378 #define NVM_SW_ARBITRATION_REG 0x7020
1366 1379 #define NVM_READ_REQ3 0X00008000
1367 1380 #define NVM_READ_REQ2 0X00004000
1368 1381 #define NVM_READ_REQ1 0X00002000
1369 1382 #define NVM_READ_REQ0 0X00001000
1370 1383 #define NVM_WON_REQ3 0X00000800
1371 1384 #define NVM_WON_REQ2 0X00000400
1372 1385 #define NVM_WON_REQ1 0X00000200
1373 1386 #define NVM_WON_REQ0 0X00000100
1374 1387 #define NVM_RESET_REQ3 0X00000080
1375 1388 #define NVM_RESET_REQ2 0X00000040
1376 1389 #define NVM_RESET_REQ1 0X00000020
1377 1390 #define NVM_RESET_REQ0 0X00000010
1378 1391 #define NVM_SET_REQ3 0X00000008
1379 1392 #define NVM_SET_REQ2 0X00000004
1380 1393 #define NVM_SET_REQ1 0X00000002
1381 1394 #define NVM_SET_REQ0 0X00000001
1382 1395
1383 1396 /*
1384 1397 * NVM access register
1385 1398 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
1386 1399 * and BCM5715 only.
1387 1400 */
1388 1401 #define NVM_ACCESS_REG 0X7024
1389 1402 #define NVM_WRITE_ENABLE 0X00000002
1390 1403 #define NVM_ACCESS_ENABLE 0X00000001
1391 1404
1392 1405 /*
1393 1406 * TLP Control Register
1394 1407 * Applicable to BCM5721 and BCM5751 only
1395 1408 */
1396 1409 #define TLP_CONTROL_REG 0x7c00
1397 1410 #define TLP_DATA_FIFO_PROTECT 0x02000000
1398 1411
1399 1412 /*
1400 1413 * PHY Test Control Register
1401 1414 * Applicable to BCM5721 and BCM5751 only
1402 1415 */
1403 1416 #define PHY_TEST_CTRL_REG 0x7e2c
1404 1417 #define PHY_PCIE_SCRAM_MODE 0x20
1405 1418 #define PHY_PCIE_LTASS_MODE 0x40
1406 1419
1407 1420 /*
1408 1421 * The internal firmware expects a certain layout of the non-volatile
1409 1422 * memory (if fitted), and will check for it during startup, and use the
1410 1423 * contents to initialise various internal parameters if it looks good.
1411 1424 *
1412 1425 * The offsets and field definitions below refer to where to find some
1413 1426 * important values, and how to interpret them ...
1414 1427 */
1415 1428 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */
1416 1429 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */
1417 1430
1418 1431 /*
1419 1432 * Vendor-specific MII registers
1420 1433 */
1421 1434 #define MII_EXT_CONTROL MII_VENDOR(0)
1422 1435 #define MII_EXT_STATUS MII_VENDOR(1)
1423 1436 #define MII_RCV_ERR_COUNT MII_VENDOR(2)
1424 1437 #define MII_FALSE_CARR_COUNT MII_VENDOR(3)
1425 1438 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4)
1426 1439 #define MII_AUX_CONTROL MII_VENDOR(8)
1427 1440 #define MII_AUX_STATUS MII_VENDOR(9)
1428 1441 #define MII_INTR_STATUS MII_VENDOR(10)
1429 1442 #define MII_INTR_MASK MII_VENDOR(11)
1430 1443 #define MII_HCD_STATUS MII_VENDOR(13)
1431 1444
1432 1445 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */
1433 1446
1434 1447 /*
1435 1448 * Bits in the MII_EXT_CONTROL register
1436 1449 */
1437 1450 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000
1438 1451 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000
1439 1452 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000
1440 1453 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000
1441 1454 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800
1442 1455 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400
1443 1456 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200
1444 1457 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100
1445 1458 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080
1446 1459 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040
1447 1460 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020
1448 1461 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010
1449 1462 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008
1450 1463 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004
1451 1464 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002
1452 1465 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001
1453 1466
1454 1467 /*
1455 1468 * Bits in the MII_EXT_STATUS register
1456 1469 */
1457 1470 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000
1458 1471 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000
1459 1472 #define MII_EXT_STAT_MDIX_STATE 0x2000
1460 1473 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000
1461 1474 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800
1462 1475 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400
1463 1476 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200
1464 1477 #define MII_EXT_STAT_LINK_STATUS 0x0100
1465 1478 #define MII_EXT_STAT_CRC_ERROR 0x0080
1466 1479 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040
1467 1480 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020
1468 1481 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010
1469 1482 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008
1470 1483 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004
1471 1484 #define MII_EXT_STAT_LOCK_ERROR 0x0002
1472 1485 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001
1473 1486
1474 1487 /*
1475 1488 * The AUX CONTROL register is seriously weird!
1476 1489 *
1477 1490 * It hides (up to) eight 'shadow' registers. When writing, which one
1478 1491 * of them is written is determined by the low-order bits of the data
1479 1492 * written(!), but when reading, which one is read is determined by the
1480 1493 * value previously written to (part of) one of the shadow registers!!!
1481 1494 */
1482 1495
1483 1496 /*
1484 1497 * Shadow register numbers
1485 1498 */
1486 1499 #define MII_AUX_CTRL_NORMAL 0
1487 1500 #define MII_AUX_CTRL_10BASE_T 1
1488 1501 #define MII_AUX_CTRL_POWER 2
1489 1502 #define MII_AUX_CTRL_TEST_1 4
1490 1503 #define MII_AUX_CTRL_MISC 7
1491 1504
1492 1505 /*
1493 1506 * Selected bits in some of the shadow registers ...
1494 1507 */
1495 1508 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000
1496 1509 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000
1497 1510 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000
1498 1511 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400
1499 1512 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008
1500 1513
1501 1514 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008
1502 1515
1503 1516 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000
1504 1517 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010
1505 1518
1506 1519 /*
1507 1520 * Write this value to the AUX control register
1508 1521 * to select which shadow register will be read
1509 1522 */
1510 1523 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC)
1511 1524
1512 1525 /*
1513 1526 * Bits in the MII_AUX_STATUS register
1514 1527 */
1515 1528 #define MII_AUX_STATUS_MODE_MASK 0x0700
1516 1529 #define MII_AUX_STATUS_MODE_1000_F 0x0700
1517 1530 #define MII_AUX_STATUS_MODE_1000_H 0x0600
1518 1531 #define MII_AUX_STATUS_MODE_100_F 0x0500
1519 1532 #define MII_AUX_STATUS_MODE_100_4 0x0400
1520 1533 #define MII_AUX_STATUS_MODE_100_H 0x0300
1521 1534 #define MII_AUX_STATUS_MODE_10_F 0x0200
1522 1535 #define MII_AUX_STATUS_MODE_10_H 0x0100
1523 1536 #define MII_AUX_STATUS_MODE_NONE 0x0000
1524 1537 #define MII_AUX_STATUS_MODE_SHIFT 8
1525 1538
1526 1539 #define MII_AUX_STATUS_PAR_FAULT 0x0080
1527 1540 #define MII_AUX_STATUS_REM_FAULT 0x0040
1528 1541 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010
1529 1542 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008
1530 1543
1531 1544 #define MII_AUX_STATUS_LINKUP 0x0004
1532 1545 #define MII_AUX_STATUS_RX_PAUSE 0x0002
1533 1546 #define MII_AUX_STATUS_TX_PAUSE 0x0001
1534 1547
1535 1548 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008
1536 1549 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002
1537 1550 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001
1538 1551
1539 1552 /*
1540 1553 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers
1541 1554 */
1542 1555 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020
1543 1556 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010
1544 1557 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008
1545 1558 #define MII_INTR_LINK_SPEED_CHANGE 0x0004
1546 1559 #define MII_INTR_LINK_STATUS_CHANGE 0x0002
1547 1560
1548 1561
1549 1562 /*
1550 1563 * Third section:
1551 1564 * Hardware-defined data structures
1552 1565 *
1553 1566 * Note that the chip is naturally BIG-endian, so, for a big-endian
1554 1567 * host, the structures defined below match those described in the PRM.
1555 1568 * For little-endian hosts, some structures have to be swapped around.
1556 1569 */
1557 1570
1558 1571 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
1559 1572 #error Host endianness not defined
1560 1573 #endif
1561 1574
1562 1575 /*
1563 1576 * Architectural constants: absolute maximum numbers of each type of ring
1564 1577 */
1565 1578 #ifdef BGE_EXT_MEM
1566 1579 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */
1567 1580 #else
1568 1581 #define BGE_SEND_RINGS_MAX 4
1569 1582 #endif
1570 1583 #define BGE_SEND_RINGS_MAX_5705 1
1571 1584 #define BGE_RECV_RINGS_MAX 16
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1572 1585 #define BGE_RECV_RINGS_MAX_5705 1
1573 1586 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */
1574 1587 /* only with ext mem) */
1575 1588
1576 1589 #define BGE_SEND_SLOTS_MAX 512
1577 1590 #define BGE_STD_SLOTS_MAX 512
1578 1591 #define BGE_JUMBO_SLOTS_MAX 256
1579 1592 #define BGE_MINI_SLOTS_MAX 1024
1580 1593 #define BGE_RECV_SLOTS_MAX 2048
1581 1594 #define BGE_RECV_SLOTS_5705 512
1595 +#define BGE_RECV_SLOTS_5717 1024
1582 1596 #define BGE_RECV_SLOTS_5782 512
1583 1597 #define BGE_RECV_SLOTS_5721 512
1584 1598
1585 1599 /*
1586 1600 * Hardware-defined Ring Control Block
1587 1601 */
1588 1602 typedef struct {
1589 1603 uint64_t host_ring_addr;
1590 1604 #ifdef _BIG_ENDIAN
1591 1605 uint16_t max_len;
1592 1606 uint16_t flags;
1593 1607 uint32_t nic_ring_addr;
1594 1608 #else
1595 1609 uint32_t nic_ring_addr;
1596 1610 uint16_t flags;
1597 1611 uint16_t max_len;
1598 1612 #endif /* _BIG_ENDIAN */
1599 1613 } bge_rcb_t;
1600 1614
1601 1615 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001
1602 1616 #define RCB_FLAG_RING_DISABLED 0x0002
1603 1617
1604 1618 /*
1605 1619 * Hardware-defined Send Buffer Descriptor
1606 1620 */
1607 1621 typedef struct {
1608 1622 uint64_t host_buf_addr;
1609 1623 #ifdef _BIG_ENDIAN
1610 1624 uint16_t len;
1611 1625 uint16_t flags;
1612 1626 uint16_t reserved;
1613 1627 uint16_t vlan_tci;
1614 1628 #else
1615 1629 uint16_t vlan_tci;
1616 1630 uint16_t reserved;
1617 1631 uint16_t flags;
1618 1632 uint16_t len;
1619 1633 #endif /* _BIG_ENDIAN */
1620 1634 } bge_sbd_t;
1621 1635
1622 1636 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001
1623 1637 #define SBD_FLAG_IP_CKSUM 0x0002
1624 1638 #define SBD_FLAG_PACKET_END 0x0004
1625 1639 #define SBD_FLAG_IP_FRAG 0x0008
1626 1640 #define SBD_FLAG_IP_FRAG_END 0x0010
1627 1641
1628 1642 #define SBD_FLAG_VLAN_TAG 0x0040
1629 1643 #define SBD_FLAG_COAL_NOW 0x0080
1630 1644 #define SBD_FLAG_CPU_PRE_DMA 0x0100
1631 1645 #define SBD_FLAG_CPU_POST_DMA 0x0200
1632 1646
1633 1647 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000
1634 1648 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000
1635 1649 #define SBD_FLAG_DONT_GEN_CRC 0x8000
1636 1650
1637 1651 /*
1638 1652 * Hardware-defined Receive Buffer Descriptor
1639 1653 */
1640 1654 typedef struct {
1641 1655 uint64_t host_buf_addr;
1642 1656 #ifdef _BIG_ENDIAN
1643 1657 uint16_t index;
1644 1658 uint16_t len;
1645 1659 uint16_t type;
1646 1660 uint16_t flags;
1647 1661 uint16_t ip_cksum;
1648 1662 uint16_t tcp_udp_cksum;
1649 1663 uint16_t error_flag;
1650 1664 uint16_t vlan_tci;
1651 1665 uint32_t reserved;
1652 1666 uint32_t opaque;
1653 1667 #else
1654 1668 uint16_t flags;
1655 1669 uint16_t type;
1656 1670 uint16_t len;
1657 1671 uint16_t index;
1658 1672 uint16_t vlan_tci;
1659 1673 uint16_t error_flag;
1660 1674 uint16_t tcp_udp_cksum;
1661 1675 uint16_t ip_cksum;
1662 1676 uint32_t opaque;
1663 1677 uint32_t reserved;
1664 1678 #endif /* _BIG_ENDIAN */
1665 1679 } bge_rbd_t;
1666 1680
1667 1681 #define RBD_FLAG_STD_RING 0x0000
1668 1682 #define RBD_FLAG_PACKET_END 0x0004
1669 1683
1670 1684 #define RBD_FLAG_JUMBO_RING 0x0020
1671 1685 #define RBD_FLAG_VLAN_TAG 0x0040
1672 1686
1673 1687 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400
1674 1688 #define RBD_FLAG_MINI_RING 0x0800
1675 1689 #define RBD_FLAG_IP_CHECKSUM 0x1000
1676 1690 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000
1677 1691 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000
1678 1692
1679 1693 #define RBD_FLAG_DEFAULT 0x0000
1680 1694
1681 1695 #define RBD_ERROR_BAD_CRC 0x00010000
1682 1696 #define RBD_ERROR_COLL_DETECT 0x00020000
1683 1697 #define RBD_ERROR_LINK_LOST 0x00040000
1684 1698 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000
1685 1699 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000
1686 1700 #define RBD_ERROR_MAC_ABORT 0x00200000
1687 1701 #define RBD_ERROR_LEN_LESS_64 0x00400000
1688 1702 #define RBD_ERROR_TRUNC_NO_RES 0x00800000
1689 1703 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000
1690 1704
1691 1705 /*
1692 1706 * Hardware-defined Status Block,Size of status block
1693 1707 * is actually 0x50 bytes.Use 0x80 bytes for cache line
1694 1708 * alignment.For BCM5705/5788/5721/5751/5752/5714
1695 1709 * and 5715,there is only 1 recv and send ring index,but
1696 1710 * driver defined 16 indexs here,please pay attention only
1697 1711 * one ring is enabled in these chipsets.
1698 1712 */
1699 1713 typedef struct {
1700 1714 uint64_t flags_n_tag;
1701 1715 uint16_t buff_cons_index[4];
1702 1716 struct {
1703 1717 #ifdef _BIG_ENDIAN
1704 1718 uint16_t send_cons_index;
1705 1719 uint16_t recv_prod_index;
1706 1720 #else
1707 1721 uint16_t recv_prod_index;
1708 1722 uint16_t send_cons_index;
1709 1723 #endif /* _BIG_ENDIAN */
1710 1724 } index[16];
1711 1725 } bge_status_t;
1712 1726
1713 1727 /*
1714 1728 * Hardware-defined Receive BD Rule
1715 1729 */
1716 1730 typedef struct {
1717 1731 uint32_t control;
1718 1732 uint32_t mask_value;
1719 1733 } bge_recv_rule_t;
1720 1734
1721 1735 /*
1722 1736 * This describes which sub-rule slots are used by a particular rule.
1723 1737 */
1724 1738 typedef struct {
1725 1739 int start;
1726 1740 int count;
1727 1741 } bge_rule_info_t;
1728 1742
1729 1743 /*
1730 1744 * Indexes into the <buff_cons_index> array
1731 1745 */
1732 1746 #ifdef _BIG_ENDIAN
1733 1747 #define STATUS_STD_BUFF_CONS_INDEX 0
1734 1748 #define STATUS_JUMBO_BUFF_CONS_INDEX 1
1735 1749 #define STATUS_MINI_BUFF_CONS_INDEX 3
1736 1750 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index)
1737 1751 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index)
1738 1752 #else
1739 1753 #define STATUS_STD_BUFF_CONS_INDEX 3
1740 1754 #define STATUS_JUMBO_BUFF_CONS_INDEX 2
1741 1755 #define STATUS_MINI_BUFF_CONS_INDEX 0
1742 1756 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index)
1743 1757 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index)
1744 1758 #endif /* _BIG_ENDIAN */
1745 1759
1746 1760 /*
1747 1761 * Bits in the <flags_n_tag> word
1748 1762 */
1749 1763 #define STATUS_FLAG_UPDATED 0x0000000100000000ull
1750 1764 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull
1751 1765 #define STATUS_FLAG_ERROR 0x0000000400000000ull
1752 1766 #define STATUS_TAG_MASK 0x00000000000000FFull
1753 1767
1754 1768 /*
1755 1769 * The tag from the status block is fed back to Interrupt Mailbox 0
1756 1770 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This
1757 1771 * lets the chip know what updates have been processed, so it can
1758 1772 * reassert its interrupt if more updates have occurred since.
1759 1773 *
1760 1774 * These macros extract the tag from the <flags_n_tag> word, shift
1761 1775 * it to the proper position in the Mailbox register, and provide
1762 1776 * the complete values to write to INTERRUPT_MBOX_0_REG to disable
1763 1777 * or enable interrupts
1764 1778 */
1765 1779 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK)
1766 1780 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24)
1767 1781 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1)
1768 1782 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0)
1769 1783
1770 1784 /*
1771 1785 * Hardware-defined Statistics Block Offsets
1772 1786 *
1773 1787 * These are given in the manual as addresses in NIC memory, starting
1774 1788 * from the NIC statistics area base address of 0x300; but here we
1775 1789 * convert them into indexes into an array of (uint64_t)s, so we can
1776 1790 * use them directly for accessing the copy of the statistics block
1777 1791 * that the chip DMAs into main memory ...
1778 1792 */
1779 1793
1780 1794 #define KS_BASE 0x300
1781 1795 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t))
1782 1796
1783 1797 typedef enum {
1784 1798 KS_ifHCInOctets = KS_ADDR(0x400),
1785 1799 KS_etherStatsFragments = KS_ADDR(0x410),
1786 1800 KS_ifHCInUcastPkts,
1787 1801 KS_ifHCInMulticastPkts,
1788 1802 KS_ifHCInBroadcastPkts,
1789 1803 KS_dot3StatsFCSErrors,
1790 1804 KS_dot3StatsAlignmentErrors,
1791 1805 KS_xonPauseFramesReceived,
1792 1806 KS_xoffPauseFramesReceived,
1793 1807 KS_macControlFramesReceived,
1794 1808 KS_xoffStateEntered,
1795 1809 KS_dot3StatsFrameTooLongs,
1796 1810 KS_etherStatsJabbers,
1797 1811 KS_etherStatsUndersizePkts,
1798 1812 KS_inRangeLengthError,
1799 1813 KS_outRangeLengthError,
1800 1814 KS_etherStatsPkts64Octets,
1801 1815 KS_etherStatsPkts65to127Octets,
1802 1816 KS_etherStatsPkts128to255Octets,
1803 1817 KS_etherStatsPkts256to511Octets,
1804 1818 KS_etherStatsPkts512to1023Octets,
1805 1819 KS_etherStatsPkts1024to1518Octets,
1806 1820 KS_etherStatsPkts1519to2047Octets,
1807 1821 KS_etherStatsPkts2048to4095Octets,
1808 1822 KS_etherStatsPkts4096to8191Octets,
1809 1823 KS_etherStatsPkts8192to9022Octets,
1810 1824
1811 1825 KS_ifHCOutOctets = KS_ADDR(0x600),
1812 1826 KS_etherStatsCollisions = KS_ADDR(0x610),
1813 1827 KS_outXonSent,
1814 1828 KS_outXoffSent,
1815 1829 KS_flowControlDone,
1816 1830 KS_dot3StatsInternalMacTransmitErrors,
1817 1831 KS_dot3StatsSingleCollisionFrames,
1818 1832 KS_dot3StatsMultipleCollisionFrames,
1819 1833 KS_dot3StatsDeferredTransmissions,
1820 1834 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658),
1821 1835 KS_dot3StatsLateCollisions,
1822 1836 KS_dot3Collided2Times,
1823 1837 KS_dot3Collided3Times,
1824 1838 KS_dot3Collided4Times,
1825 1839 KS_dot3Collided5Times,
1826 1840 KS_dot3Collided6Times,
1827 1841 KS_dot3Collided7Times,
1828 1842 KS_dot3Collided8Times,
1829 1843 KS_dot3Collided9Times,
1830 1844 KS_dot3Collided10Times,
1831 1845 KS_dot3Collided11Times,
1832 1846 KS_dot3Collided12Times,
1833 1847 KS_dot3Collided13Times,
1834 1848 KS_dot3Collided14Times,
1835 1849 KS_dot3Collided15Times,
1836 1850 KS_ifHCOutUcastPkts,
1837 1851 KS_ifHCOutMulticastPkts,
1838 1852 KS_ifHCOutBroadcastPkts,
1839 1853 KS_dot3StatsCarrierSenseErrors,
1840 1854 KS_ifOutDiscards,
1841 1855 KS_ifOutErrors,
1842 1856
1843 1857 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */
1844 1858 KS_COSIfHCInPkts_2,
1845 1859 KS_COSIfHCInPkts_3,
1846 1860 KS_COSIfHCInPkts_4,
1847 1861 KS_COSIfHCInPkts_5,
1848 1862 KS_COSIfHCInPkts_6,
1849 1863 KS_COSIfHCInPkts_7,
1850 1864 KS_COSIfHCInPkts_8,
1851 1865 KS_COSIfHCInPkts_9,
1852 1866 KS_COSIfHCInPkts_10,
1853 1867 KS_COSIfHCInPkts_11,
1854 1868 KS_COSIfHCInPkts_12,
1855 1869 KS_COSIfHCInPkts_13,
1856 1870 KS_COSIfHCInPkts_14,
1857 1871 KS_COSIfHCInPkts_15,
1858 1872 KS_COSIfHCInPkts_16,
1859 1873 KS_COSFramesDroppedDueToFilters,
1860 1874 KS_nicDmaWriteQueueFull,
1861 1875 KS_nicDmaWriteHighPriQueueFull,
1862 1876 KS_nicNoMoreRxBDs,
1863 1877 KS_ifInDiscards,
1864 1878 KS_ifInErrors,
1865 1879 KS_nicRecvThresholdHit,
1866 1880
1867 1881 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */
1868 1882 KS_COSIfHCOutPkts_2,
1869 1883 KS_COSIfHCOutPkts_3,
1870 1884 KS_COSIfHCOutPkts_4,
1871 1885 KS_COSIfHCOutPkts_5,
1872 1886 KS_COSIfHCOutPkts_6,
1873 1887 KS_COSIfHCOutPkts_7,
1874 1888 KS_COSIfHCOutPkts_8,
1875 1889 KS_COSIfHCOutPkts_9,
1876 1890 KS_COSIfHCOutPkts_10,
1877 1891 KS_COSIfHCOutPkts_11,
1878 1892 KS_COSIfHCOutPkts_12,
1879 1893 KS_COSIfHCOutPkts_13,
1880 1894 KS_COSIfHCOutPkts_14,
1881 1895 KS_COSIfHCOutPkts_15,
1882 1896 KS_COSIfHCOutPkts_16,
1883 1897 KS_nicDmaReadQueueFull,
1884 1898 KS_nicDmaReadHighPriQueueFull,
1885 1899 KS_nicSendDataCompQueueFull,
1886 1900 KS_nicRingSetSendProdIndex,
1887 1901 KS_nicRingStatusUpdate,
1888 1902 KS_nicInterrupts,
1889 1903 KS_nicAvoidedInterrupts,
1890 1904 KS_nicSendThresholdHit,
1891 1905
1892 1906 KS_STATS_SIZE = KS_ADDR(0xb00)
1893 1907 } bge_stats_offset_t;
1894 1908
1895 1909 /*
1896 1910 * Hardware-defined Statistics Block
1897 1911 *
1898 1912 * Another view of the statistic block, as a array and a structure ...
1899 1913 */
1900 1914
1901 1915 typedef union {
1902 1916 uint64_t a[KS_STATS_SIZE];
1903 1917 struct {
1904 1918 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)];
1905 1919
1906 1920 uint64_t ifHCInOctets; /* 0x0400 */
1907 1921 uint64_t spare2[1];
1908 1922 uint64_t etherStatsFragments;
1909 1923 uint64_t ifHCInUcastPkts;
1910 1924 uint64_t ifHCInMulticastPkts;
1911 1925 uint64_t ifHCInBroadcastPkts;
1912 1926 uint64_t dot3StatsFCSErrors;
1913 1927 uint64_t dot3StatsAlignmentErrors;
1914 1928 uint64_t xonPauseFramesReceived;
1915 1929 uint64_t xoffPauseFramesReceived;
1916 1930 uint64_t macControlFramesReceived;
1917 1931 uint64_t xoffStateEntered;
1918 1932 uint64_t dot3StatsFrameTooLongs;
1919 1933 uint64_t etherStatsJabbers;
1920 1934 uint64_t etherStatsUndersizePkts;
1921 1935 uint64_t inRangeLengthError;
1922 1936 uint64_t outRangeLengthError;
1923 1937 uint64_t etherStatsPkts64Octets;
1924 1938 uint64_t etherStatsPkts65to127Octets;
1925 1939 uint64_t etherStatsPkts128to255Octets;
1926 1940 uint64_t etherStatsPkts256to511Octets;
1927 1941 uint64_t etherStatsPkts512to1023Octets;
1928 1942 uint64_t etherStatsPkts1024to1518Octets;
1929 1943 uint64_t etherStatsPkts1519to2047Octets;
1930 1944 uint64_t etherStatsPkts2048to4095Octets;
1931 1945 uint64_t etherStatsPkts4096to8191Octets;
1932 1946 uint64_t etherStatsPkts8192to9022Octets;
1933 1947 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)];
1934 1948
1935 1949 uint64_t ifHCOutOctets; /* 0x0600 */
1936 1950 uint64_t spare4[1];
1937 1951 uint64_t etherStatsCollisions;
1938 1952 uint64_t outXonSent;
1939 1953 uint64_t outXoffSent;
1940 1954 uint64_t flowControlDone;
1941 1955 uint64_t dot3StatsInternalMacTransmitErrors;
1942 1956 uint64_t dot3StatsSingleCollisionFrames;
1943 1957 uint64_t dot3StatsMultipleCollisionFrames;
1944 1958 uint64_t dot3StatsDeferredTransmissions;
1945 1959 uint64_t spare5[1];
1946 1960 uint64_t dot3StatsExcessiveCollisions;
1947 1961 uint64_t dot3StatsLateCollisions;
1948 1962 uint64_t dot3Collided2Times;
1949 1963 uint64_t dot3Collided3Times;
1950 1964 uint64_t dot3Collided4Times;
1951 1965 uint64_t dot3Collided5Times;
1952 1966 uint64_t dot3Collided6Times;
1953 1967 uint64_t dot3Collided7Times;
1954 1968 uint64_t dot3Collided8Times;
1955 1969 uint64_t dot3Collided9Times;
1956 1970 uint64_t dot3Collided10Times;
1957 1971 uint64_t dot3Collided11Times;
1958 1972 uint64_t dot3Collided12Times;
1959 1973 uint64_t dot3Collided13Times;
1960 1974 uint64_t dot3Collided14Times;
1961 1975 uint64_t dot3Collided15Times;
1962 1976 uint64_t ifHCOutUcastPkts;
1963 1977 uint64_t ifHCOutMulticastPkts;
1964 1978 uint64_t ifHCOutBroadcastPkts;
1965 1979 uint64_t dot3StatsCarrierSenseErrors;
1966 1980 uint64_t ifOutDiscards;
1967 1981 uint64_t ifOutErrors;
1968 1982 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)];
1969 1983
1970 1984 uint64_t COSIfHCInPkts[16]; /* 0x0800 */
1971 1985 uint64_t COSFramesDroppedDueToFilters;
1972 1986 uint64_t nicDmaWriteQueueFull;
1973 1987 uint64_t nicDmaWriteHighPriQueueFull;
1974 1988 uint64_t nicNoMoreRxBDs;
1975 1989 uint64_t ifInDiscards;
1976 1990 uint64_t ifInErrors;
1977 1991 uint64_t nicRecvThresholdHit;
1978 1992 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)];
1979 1993
1980 1994 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */
1981 1995 uint64_t nicDmaReadQueueFull;
1982 1996 uint64_t nicDmaReadHighPriQueueFull;
1983 1997 uint64_t nicSendDataCompQueueFull;
1984 1998 uint64_t nicRingSetSendProdIndex;
1985 1999 uint64_t nicRingStatusUpdate;
1986 2000 uint64_t nicInterrupts;
1987 2001 uint64_t nicAvoidedInterrupts;
1988 2002 uint64_t nicSendThresholdHit;
1989 2003 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)];
1990 2004 } s;
1991 2005 } bge_statistics_t;
1992 2006
1993 2007 #define KS_STAT_REG_SIZE (0x1B)
1994 2008 #define KS_STAT_REG_BASE (0x800)
1995 2009
1996 2010 typedef struct {
1997 2011 uint32_t ifHCOutOctets;
1998 2012 uint32_t etherStatsCollisions;
1999 2013 uint32_t outXonSent;
2000 2014 uint32_t outXoffSent;
2001 2015 uint32_t dot3StatsInternalMacTransmitErrors;
2002 2016 uint32_t dot3StatsSingleCollisionFrames;
2003 2017 uint32_t dot3StatsMultipleCollisionFrames;
2004 2018 uint32_t dot3StatsDeferredTransmissions;
2005 2019 uint32_t dot3StatsExcessiveCollisions;
2006 2020 uint32_t dot3StatsLateCollisions;
2007 2021 uint32_t ifHCOutUcastPkts;
2008 2022 uint32_t ifHCOutMulticastPkts;
2009 2023 uint32_t ifHCOutBroadcastPkts;
2010 2024 uint32_t ifHCInOctets;
2011 2025 uint32_t etherStatsFragments;
2012 2026 uint32_t ifHCInUcastPkts;
2013 2027 uint32_t ifHCInMulticastPkts;
2014 2028 uint32_t ifHCInBroadcastPkts;
2015 2029 uint32_t dot3StatsFCSErrors;
2016 2030 uint32_t dot3StatsAlignmentErrors;
2017 2031 uint32_t xonPauseFramesReceived;
2018 2032 uint32_t xoffPauseFramesReceived;
2019 2033 uint32_t macControlFramesReceived;
2020 2034 uint32_t xoffStateEntered;
2021 2035 uint32_t dot3StatsFrameTooLongs;
2022 2036 uint32_t etherStatsJabbers;
2023 2037 uint32_t etherStatsUndersizePkts;
2024 2038 } bge_statistics_reg_t;
2025 2039
2026 2040
2027 2041 #ifdef BGE_IPMI_ASF
2028 2042
2029 2043 /*
2030 2044 * Device internal memory entries
2031 2045 */
2032 2046
2033 2047 #define BGE_FIRMWARE_MAILBOX 0x0b50
2034 2048 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654
2035 2049 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
2036 2050
2037 2051
2038 2052 #define BGE_NIC_DATA_SIG_ADDR 0x0b54
2039 2053 #define BGE_NIC_DATA_SIG 0x4b657654
2040 2054
2041 2055
2042 2056 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58
2043 2057
2044 2058 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004
2045 2059 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008
2046 2060 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004
2047 2061 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008
2048 2062 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c
2049 2063
2050 2064 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000
2051 2065 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010
2052 2066 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020
2053 2067 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030
2054 2068
2055 2069 #define BGE_NIC_CFG_ENABLE_WOL 0x000040
2056 2070 #define BGE_NIC_CFG_ENABLE_ASF 0x000080
2057 2071 #define BGE_NIC_CFG_EEPROM_WP 0x000100
2058 2072 #define BGE_NIC_CFG_POWER_SAVING 0x000200
2059 2073 #define BGE_NIC_CFG_SWAP_PORT 0x000800
2060 2074 #define BGE_NIC_CFG_MINI_PCI 0x001000
2061 2075 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000
2062 2076 #define BGE_NIC_CFG_5753_12x12 0x100000
2063 2077
2064 2078
2065 2079 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c
2066 2080
2067 2081
2068 2082 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74
2069 2083 #define BGE_NIC_PHY_ID1_MASK 0xffff0000
2070 2084 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff
2071 2085
2072 2086
2073 2087 #define BGE_CMD_MAILBOX 0x0b78
2074 2088 #define BGE_CMD_NICDRV_ALIVE 0x00000001
2075 2089 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002
2076 2090 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003
2077 2091 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004
2078 2092
2079 2093
2080 2094 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c
2081 2095 #define BGE_CMD_DATA_MAILBOX 0x0b80
2082 2096 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00
2083 2097
2084 2098 #define BGE_DRV_STATE_MAILBOX 0x0c04
2085 2099 #define BGE_DRV_STATE_START 0x00000001
2086 2100 #define BGE_DRV_STATE_START_DONE 0x80000001
2087 2101 #define BGE_DRV_STATE_UNLOAD 0x00000002
2088 2102 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002
2089 2103 #define BGE_DRV_STATE_WOL 0x00000003
2090 2104 #define BGE_DRV_STATE_SUSPEND 0x00000004
2091 2105
2092 2106
2093 2107 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08
2094 2108 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001
2095 2109 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002
2096 2110
2097 2111
2098 2112 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14
2099 2113 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18
2100 2114
2101 2115
2102 2116 /*
2103 2117 * RX-RISC event register
2104 2118 */
2105 2119 #define RX_RISC_EVENT_REG 0x6810
2106 2120 #define RRER_ASF_EVENT 0x4000
2107 2121
2108 2122 #endif /* BGE_IPMI_ASF */
2109 2123
2110 2124 #ifdef __cplusplus
2111 2125 }
2112 2126 #endif
2113 2127
2114 2128 #endif /* _BGE_HW_H */
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