6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #ifndef _BGE_HW_H
27 #define _BGE_HW_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <sys/types.h>
34
35
36 /*
37 * First section:
38 * Identification of the various Broadcom chips
39 *
40 * Note: the various ID values are *not* all unique ;-(
41 *
42 * Note: the presence of an ID here does *not* imply that the chip is
43 * supported. At this time, only the 5703C, 5704C, and 5704S devices
44 * used on the motherboards of certain Sun products are supported.
45 *
51 #define VENDOR_ID_SUN 0x108e
52
53 #define DEVICE_ID_5700 0x1644
54 #define DEVICE_ID_5700x 0x0003
55 #define DEVICE_ID_5701 0x1645
56 #define DEVICE_ID_5702 0x16a6
57 #define DEVICE_ID_5702fe 0x164d
58 #define DEVICE_ID_5703C 0x16a7
59 #define DEVICE_ID_5703S 0x1647
60 #define DEVICE_ID_5703 0x16c7
61 #define DEVICE_ID_5704C 0x1648
62 #define DEVICE_ID_5704S 0x16a8
63 #define DEVICE_ID_5704 0x1649
64 #define DEVICE_ID_5705C 0x1653
65 #define DEVICE_ID_5705_2 0x1654
66 #define DEVICE_ID_5717 0x1655
67 #define DEVICE_ID_5718 0x1656
68 #define DEVICE_ID_5724 0x165c
69 #define DEVICE_ID_5705M 0x165d
70 #define DEVICE_ID_5705MA3 0x165e
71 #define DEVICE_ID_5705F 0x166e
72 #define DEVICE_ID_5780 0x166a
73 #define DEVICE_ID_5782 0x1696
74 #define DEVICE_ID_5784M 0x1698
75 #define DEVICE_ID_5785 0x1699
76 #define DEVICE_ID_5787 0x169b
77 #define DEVICE_ID_5787M 0x1693
78 #define DEVICE_ID_5788 0x169c
79 #define DEVICE_ID_5789 0x169d
80 #define DEVICE_ID_5751 0x1677
81 #define DEVICE_ID_5751M 0x167d
82 #define DEVICE_ID_5752 0x1600
83 #define DEVICE_ID_5752M 0x1601
84 #define DEVICE_ID_5753 0x16fd
85 #define DEVICE_ID_5754 0x167a
86 #define DEVICE_ID_5755 0x167b
87 #define DEVICE_ID_5755M 0x1673
88 #define DEVICE_ID_5756M 0x1674
89 #define DEVICE_ID_5721 0x1659
90 #define DEVICE_ID_5722 0x165a
91 #define DEVICE_ID_5723 0x165b
92 #define DEVICE_ID_5714C 0x1668
93 #define DEVICE_ID_5714S 0x1669
94 #define DEVICE_ID_5715C 0x1678
95 #define DEVICE_ID_5715S 0x1679
96 #define DEVICE_ID_5761 0x1681
97 #define DEVICE_ID_5761E 0x1680
98 #define DEVICE_ID_5761S 0x1688
99 #define DEVICE_ID_5761SE 0x1689
100 #define DEVICE_ID_5764 0x1684
101 #define DEVICE_ID_5906 0x1712
102 #define DEVICE_ID_5906M 0x1713
103 #define DEVICE_ID_57760 0x1690
104 #define DEVICE_ID_57780 0x1692
105 #define DEVICE_ID_57788 0x1691
106 #define DEVICE_ID_57790 0x1694
107
108 #define REVISION_ID_5700_B0 0x10
109 #define REVISION_ID_5700_B2 0x12
110 #define REVISION_ID_5700_B3 0x13
111 #define REVISION_ID_5700_C0 0x20
112 #define REVISION_ID_5700_C1 0x21
113 #define REVISION_ID_5700_C2 0x22
114
115 #define REVISION_ID_5701_A0 0x08
116 #define REVISION_ID_5701_A2 0x12
117 #define REVISION_ID_5701_A3 0x15
118
119 #define REVISION_ID_5702_A0 0x00
120
121 #define REVISION_ID_5703_A0 0x00
122 #define REVISION_ID_5703_A1 0x01
123 #define REVISION_ID_5703_A2 0x02
124
125 #define REVISION_ID_5704_A0 0x00
126 #define REVISION_ID_5704_A1 0x01
178 (bgep->chipid.device == DEVICE_ID_5780) ||\
179 (bgep->chipid.device == DEVICE_ID_5782) ||\
180 (bgep->chipid.device == DEVICE_ID_5788) ||\
181 (bgep->chipid.device == DEVICE_ID_5705_2) ||\
182 (bgep->chipid.device == DEVICE_ID_5754) ||\
183 (bgep->chipid.device == DEVICE_ID_5755) ||\
184 (bgep->chipid.device == DEVICE_ID_5756M) ||\
185 (bgep->chipid.device == DEVICE_ID_5753))
186
187 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \
188 ((bgep->chipid.device == DEVICE_ID_5721) ||\
189 (bgep->chipid.device == DEVICE_ID_5751) ||\
190 (bgep->chipid.device == DEVICE_ID_5751M) ||\
191 (bgep->chipid.device == DEVICE_ID_5752) ||\
192 (bgep->chipid.device == DEVICE_ID_5752M) ||\
193 (bgep->chipid.device == DEVICE_ID_5789))
194
195 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \
196 (bgep->chipid.device == DEVICE_ID_5717) ||\
197 (bgep->chipid.device == DEVICE_ID_5718) ||\
198 (bgep->chipid.device == DEVICE_ID_5724)
199
200 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \
201 ((bgep->chipid.device == DEVICE_ID_5723) ||\
202 (bgep->chipid.device == DEVICE_ID_5761) ||\
203 (bgep->chipid.device == DEVICE_ID_5761E) ||\
204 (bgep->chipid.device == DEVICE_ID_5761S) ||\
205 (bgep->chipid.device == DEVICE_ID_5761SE) ||\
206 (bgep->chipid.device == DEVICE_ID_5764) ||\
207 (bgep->chipid.device == DEVICE_ID_5784M) ||\
208 (bgep->chipid.device == DEVICE_ID_5785) ||\
209 (bgep->chipid.device == DEVICE_ID_57760) ||\
210 (bgep->chipid.device == DEVICE_ID_57780) ||\
211 (bgep->chipid.device == DEVICE_ID_57788) ||\
212 (bgep->chipid.device == DEVICE_ID_57790))
213
214 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \
215 ((bgep->chipid.device == DEVICE_ID_5714C) ||\
216 (bgep->chipid.device == DEVICE_ID_5714S) ||\
217 (bgep->chipid.device == DEVICE_ID_5715C) ||\
218 (bgep->chipid.device == DEVICE_ID_5715S))
219
220 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \
221 ((bgep->chipid.device == DEVICE_ID_5906) ||\
222 (bgep->chipid.device == DEVICE_ID_5906M))
223
224 /*
225 * Second section:
226 * Offsets of important registers & definitions for bits therein
227 */
228
229 /*
230 * PCI-X registers & bits
231 */
232 #define PCIX_CONF_COMM 0x42
233 #define PCIX_COMM_RELAXED 0x0002
234
235 /*
236 * Miscellaneous Host Control Register, in PCI config space
237 */
238 #define PCI_CONF_BGE_MHCR 0x68
239 #define MHCR_CHIP_REV_MASK 0xffff0000
240 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
241 #define MHCR_MASK_INTERRUPT_MODE 0x00000100
242 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
243 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040
244 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020
245 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010
246 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008
247 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004
248 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
249 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001
250
251 #define MHCR_CHIP_REV_5700_B0 0x71000000
252 #define MHCR_CHIP_REV_5700_B2 0x71020000
253 #define MHCR_CHIP_REV_5700_B3 0x71030000
254 #define MHCR_CHIP_REV_5700_C0 0x72000000
255 #define MHCR_CHIP_REV_5700_C1 0x72010000
256 #define MHCR_CHIP_REV_5700_C2 0x72020000
257
258 #define MHCR_CHIP_REV_5701_A0 0x00000000
259 #define MHCR_CHIP_REV_5701_A2 0x00020000
260 #define MHCR_CHIP_REV_5701_A3 0x00030000
261 #define MHCR_CHIP_REV_5701_A5 0x01050000
262
263 #define MHCR_CHIP_REV_5702_A0 0x10000000
264 #define MHCR_CHIP_REV_5702_A1 0x10010000
265 #define MHCR_CHIP_REV_5702_A2 0x10020000
266
267 #define MHCR_CHIP_REV_5703_A0 0x10000000
268 #define MHCR_CHIP_REV_5703_A1 0x10010000
269 #define MHCR_CHIP_REV_5703_A2 0x10020000
270 #define MHCR_CHIP_REV_5703_B0 0x11000000
271 #define MHCR_CHIP_REV_5703_B1 0x11010000
272
273 #define MHCR_CHIP_REV_5704_A0 0x20000000
274 #define MHCR_CHIP_REV_5704_A1 0x20010000
275 #define MHCR_CHIP_REV_5704_A2 0x20020000
276 #define MHCR_CHIP_REV_5704_A3 0x20030000
277 #define MHCR_CHIP_REV_5704_B0 0x21000000
278
279 #define MHCR_CHIP_REV_5705_A0 0x30000000
280 #define MHCR_CHIP_REV_5705_A1 0x30010000
281 #define MHCR_CHIP_REV_5705_A2 0x30020000
282 #define MHCR_CHIP_REV_5705_A3 0x30030000
283 #define MHCR_CHIP_REV_5705_A5 0x30050000
284
285 #define MHCR_CHIP_REV_5782_A0 0x30030000
286 #define MHCR_CHIP_REV_5782_A1 0x30030088
287
288 #define MHCR_CHIP_REV_5788_A1 0x30050000
289
290 #define MHCR_CHIP_REV_5751_A0 0x40000000
291 #define MHCR_CHIP_REV_5751_A1 0x40010000
292
293 #define MHCR_CHIP_REV_5721_A0 0x41000000
294 #define MHCR_CHIP_REV_5721_A1 0x41010000
295
296 #define MHCR_CHIP_REV_5714_A0 0x50000000
297 #define MHCR_CHIP_REV_5714_A1 0x90010000
298
299 #define MHCR_CHIP_REV_5715_A0 0x50000000
300 #define MHCR_CHIP_REV_5715_A1 0x90010000
301
302 #define MHCR_CHIP_REV_5715S_A0 0x50000000
303 #define MHCR_CHIP_REV_5715S_A1 0x90010000
304
305 #define MHCR_CHIP_REV_5754_A0 0xb0000000
306 #define MHCR_CHIP_REV_5754_A1 0xb0010000
307
308 #define MHCR_CHIP_REV_5787_A0 0xb0000000
309 #define MHCR_CHIP_REV_5787_A1 0xb0010000
310 #define MHCR_CHIP_REV_5787_A2 0xb0020000
311
312 #define MHCR_CHIP_REV_5755_A0 0xa0000000
313 #define MHCR_CHIP_REV_5755_A1 0xa0010000
314
315 #define MHCR_CHIP_REV_5906_A0 0xc0000000
316 #define MHCR_CHIP_REV_5906_A1 0xc0010000
317 #define MHCR_CHIP_REV_5906_A2 0xc0020000
318
319 #define MHCR_CHIP_REV_5723_A0 0xf0000000
320 #define MHCR_CHIP_REV_5723_A1 0xf0010000
321 #define MHCR_CHIP_REV_5723_A2 0xf0020000
322 #define MHCR_CHIP_REV_5723_B0 0xf1000000
323
324 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000)
325 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28)
326 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28)
327 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28)
328 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28)
329 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28)
330 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28)
331 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28)
332 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28)
333 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28)
334 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28)
335 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28)
336 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28)
337 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28)
338 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28)
339
340
341 /*
342 * PCI DMA read/write Control Register, in PCI config space
343 *
344 * Note that several fields previously defined here have been deleted
345 * as they are not implemented in the 5703/4.
346 *
347 * Note: the value of this register is critical. It is possible to
348 * cause various unpleasant effects (DTOs, transaction deadlock, etc)
349 * by programming the wrong value. The value #defined below has been
350 * tested and shown to avoid all known problems. If it is to be changed,
351 * correct operation must be reverified on all supported platforms.
352 *
353 * In particular, we set both watermark fields to 2xCacheLineSize (128)
354 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
355 * with Tomatillo's internal pipelines, that otherwise result in stalls,
356 * repeated retries, and DTOs.
357 */
358 #define PCI_CONF_BGE_PDRWCR 0x6c
359 #define PDRWCR_RWCMD_MASK 0xFF000000
360 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000
461 #define PCI_CONF_BGE_MWBAR 0x7c
462 #define PCI_CONF_BGE_MWDAR 0x84
463 #define MWBAR_GRANULARITY 0x00008000 /* 32k */
464 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1)
465 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */
466
467 /*
468 * The PCI express device control register and device status register
469 * which are only applicable on BCM5751 and BCM5721.
470 */
471 #define PCI_CONF_DEV_CTRL 0xd8
472 #define PCI_CONF_DEV_CTRL_5723 0xd4
473 #define READ_REQ_SIZE_MAX 0x5000
474 #define DEV_CTRL_NO_SNOOP 0x0800
475 #define DEV_CTRL_RELAXED 0x0010
476
477 #define PCI_CONF_DEV_STUS 0xda
478 #define PCI_CONF_DEV_STUS_5723 0xd6
479 #define DEVICE_ERROR_STUS 0xf
480
481 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */
482
483 /*
484 * Where to find things in NIC-local (on-chip) memory
485 */
486 #define NIC_MEM_SEND_RINGS 0x0100
487 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring))
488 #define NIC_MEM_RECV_RINGS 0x0200
489 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring))
490 #define NIC_MEM_STATISTICS 0x0300
491 #define NIC_MEM_STATISTICS_SIZE 0x0800
492 #define NIC_MEM_STATUS_BLOCK 0x0b00
493 #define NIC_MEM_STATUS_SIZE 0x0050
494 #define NIC_MEM_GENCOMM 0x0b50
495
496
497 /*
498 * Note: the (non-bogus) values below are appropriate for systems
499 * without external memory. They would be different on a 5700 with
500 * external memory.
536 #define TRANSMIT_MAC_MODE_REG 0x045c
537 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00
538 #define SEND_DATA_COMPLETION_MODE_REG 0x1000
539 #define SEND_BD_SELECTOR_MODE_REG 0x1400
540 #define SEND_BD_INITIATOR_MODE_REG 0x1800
541 #define SEND_BD_COMPLETION_MODE_REG 0x1c00
542
543 #define RECEIVE_MAC_MODE_REG 0x0468
544 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000
545 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400
546 #define RCV_DATA_COMPLETION_MODE_REG 0x2800
547 #define RCV_BD_INITIATOR_MODE_REG 0x2c00
548 #define RCV_BD_COMPLETION_MODE_REG 0x3000
549 #define RCV_LIST_SELECTOR_MODE_REG 0x3400
550
551 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800
552 #define HOST_COALESCE_MODE_REG 0x3c00
553 #define MEMORY_ARBITER_MODE_REG 0x4000
554 #define BUFFER_MANAGER_MODE_REG 0x4400
555 #define READ_DMA_MODE_REG 0x4800
556 #define WRITE_DMA_MODE_REG 0x4c00
557 #define DMA_COMPLETION_MODE_REG 0x6400
558
559 /*
560 * Other bits in some of the above state machine control registers
561 */
562
563 /*
564 * Transmit MAC Mode Register
565 * (TRANSMIT_MAC_MODE_REG, 0x045c)
566 */
567 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040
568 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
569 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
570
571 /*
572 * Receive MAC Mode Register
573 * (RECEIVE_MAC_MODE_REG, 0x0468)
574 */
575 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400
576 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200
577 #define RECEIVE_MODE_PROMISCUOUS 0x00000100
578 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080
579 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040
580 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020
581 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010
582 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004
583
584 /*
585 * Receive BD Initiator Mode Register
586 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
614 #define COALESCE_CLR_TICKS_RX 0x00000200
615 #define COALESCE_32_BYTE_STATUS 0x00000100
616 #define COALESCE_64_BYTE_STATUS 0x00000080
617 #define COALESCE_NOW 0x00000008
618
619 /*
620 * Memory Arbiter Mode Register
621 * (MEMORY_ARBITER_MODE_REG, 0x4000)
622 */
623 #define MEMORY_ARBITER_ENABLE 0x00000002
624
625 /*
626 * Buffer Manager Mode Register
627 * (BUFFER_MANAGER_MODE_REG, 0x4400)
628 *
629 * In addition to the usual error-attn common to most state machines
630 * this register has a separate bit for attn on running-low-on-mbufs
631 */
632 #define BUFF_MGR_TEST_MODE 0x00000008
633 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
634
635 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014
636
637 /*
638 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
639 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
640 *
641 * These registers each contain a 2-bit priority field, which controls
642 * the relative priority of that type of DMA (read vs. write vs. MSI),
643 * and a set of bits that control whether ATTN is asserted on each
644 * particular condition
645 */
646 #define DMA_PRIORITY_MASK 0xc0000000
647 #define DMA_PRIORITY_SHIFT 30
648 #define ALL_DMA_ATTN_BITS 0x000003fc
649
650 /*
651 * BCM5755, 5755M, 5906, 5906M only
652 * 1 - Enable Fix. Device will send out the status block before
653 * the interrupt message
654 * 0 - Disable fix. Device will send out the interrupt message
655 * before the status block
656 */
657 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000
658
659 /*
660 * End of state machine control register definitions
661 */
662
663
664 /*
665 * High priority mailbox registers.
666 * Mailbox Registers (8 bytes each, but high half unused)
667 */
668 #define INTERRUPT_MBOX_0_REG 0x0200
669 #define INTERRUPT_MBOX_1_REG 0x0208
670 #define INTERRUPT_MBOX_2_REG 0x0210
671 #define INTERRUPT_MBOX_3_REG 0x0218
672 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n))
673
674 /*
675 * Low priority mailbox registers, for BCM5906, BCM5906M.
676 */
677 #define INTERRUPT_LP_MBOX_0_REG 0x5800
678
776 * usually only has one h/w address. The value in register 0 is
777 * used for pause packets; any of the four can be specified for
778 * substitution into other transmitted packets if required.
779 */
780 #define MAC_ADDRESS_0_REG 0x0410
781 #define MAC_ADDRESS_1_REG 0x0418
782 #define MAC_ADDRESS_2_REG 0x0420
783 #define MAC_ADDRESS_3_REG 0x0428
784
785 #define MAC_ADDRESS_REG(n) (0x0410+8*(n))
786 #define MAC_ADDRESS_REGS_MAX 4
787
788 /*
789 * More MAC Registers ...
790 */
791 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438
792 #define MAC_RX_MTU_SIZE_REG 0x043c
793 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
794 #define MAC_TX_LENGTHS_REG 0x0464
795 #define MAC_TX_LENGTHS_DEFAULT 0x00002620
796
797 /*
798 * MII access registers
799 */
800 #define MI_COMMS_REG 0x044c
801 #define MI_COMMS_START 0x20000000
802 #define MI_COMMS_READ_FAILED 0x10000000
803 #define MI_COMMS_COMMAND_MASK 0x0c000000
804 #define MI_COMMS_COMMAND_READ 0x08000000
805 #define MI_COMMS_COMMAND_WRITE 0x04000000
806 #define MI_COMMS_ADDRESS_MASK 0x03e00000
807 #define MI_COMMS_ADDRESS_SHIFT 21
808 #define MI_COMMS_REGISTER_MASK 0x001f0000
809 #define MI_COMMS_REGISTER_SHIFT 16
810 #define MI_COMMS_DATA_MASK 0x0000ffff
811 #define MI_COMMS_DATA_SHIFT 0
812
813 #define MI_STATUS_REG 0x0450
814 #define MI_STATUS_10MBPS 0x00000002
815 #define MI_STATUS_LINK 0x00000001
1064
1065 /*
1066 * Receive Buffer Descriptor Ring Control Block Registers
1067 * NB: sixteen bytes (128 bits) each
1068 */
1069 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440
1070 #define STD_RCV_BD_RING_RCB_REG 0x2450
1071 #define MINI_RCV_BD_RING_RCB_REG 0x2460
1072
1073 /*
1074 * Receive Buffer Descriptor Ring Replenish Threshold Registers
1075 */
1076 #define MINI_RCV_BD_REPLENISH_REG 0x2c14
1077 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */
1078 #define STD_RCV_BD_REPLENISH_REG 0x2c18
1079 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */
1080 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c
1081 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */
1082
1083 /*
1084 * CPMU registers (5717/5718 only)
1085 */
1086 #define CPMU_STATUS_REG 0x362c
1087 #define CPMU_STATUS_FUN_NUM 0x20000000
1088
1089 /*
1090 * Host Coalescing Engine Control Registers
1091 */
1092 #define RCV_COALESCE_TICKS_REG 0x3c08
1093 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1094 #define SEND_COALESCE_TICKS_REG 0x3c0c
1095 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1096 #define RCV_COALESCE_MAX_BD_REG 0x3c10
1097 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1098 #define SEND_COALESCE_MAX_BD_REG 0x3c14
1099 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1100 #define RCV_COALESCE_INT_TICKS_REG 0x3c18
1101 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1102 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c
1103 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1104 #define RCV_COALESCE_INT_BD_REG 0x3c20
1105 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1106 #define SEND_COALESCE_INT_BD_REG 0x3c24
1107 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1108 #define STATISTICS_TICKS_REG 0x3c28
1186 /*
1187 * RX/TX RISC Registers
1188 */
1189 #define RX_RISC_MODE_REG 0x5000
1190 #define RX_RISC_STATE_REG 0x5004
1191 #define RX_RISC_PC_REG 0x501c
1192 #define TX_RISC_MODE_REG 0x5400
1193 #define TX_RISC_STATE_REG 0x5404
1194 #define TX_RISC_PC_REG 0x541c
1195
1196 /*
1197 * V? RISC Registerss
1198 */
1199 #define VCPU_STATUS_REG 0x5100
1200 #define VCPU_INIT_DONE 0x04000000
1201 #define VCPU_DRV_RESET 0x08000000
1202
1203 #define VCPU_EXT_CTL 0x6890
1204 #define VCPU_EXT_CTL_HALF 0x00400000
1205
1206 #define FTQ_RESET_REG 0x5c00
1207
1208 #define MSI_MODE_REG 0x6000
1209 #define MSI_PRI_HIGHEST 0xc0000000
1210 #define MSI_MSI_ENABLE 0x00000002
1211 #define MSI_ERROR_ATTENTION 0x0000001c
1212
1213 #define MSI_STATUS_REG 0x6004
1214
1215 #define MODE_CONTROL_REG 0x6800
1216 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000
1217 #define MODE_4X_NIC_SEND_RINGS 0x20000000
1218 #define MODE_INT_ON_FLOW_ATTN 0x10000000
1219 #define MODE_INT_ON_DMA_ATTN 0x08000000
1220 #define MODE_INT_ON_MAC_ATTN 0x04000000
1221 #define MODE_INT_ON_RXRISC_ATTN 0x02000000
1222 #define MODE_INT_ON_TXRISC_ATTN 0x01000000
1223 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
1224 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
1225 #define MODE_HOST_SEND_BDS 0x00020000
1226 #define MODE_HOST_STACK_UP 0x00010000
1227 #define MODE_FORCE_32_BIT_PCI 0x00008000
1228 #define MODE_NO_INT_ON_RECV 0x00004000
1229 #define MODE_NO_INT_ON_SEND 0x00002000
1230 #define MODE_ALLOW_BAD_FRAMES 0x00000800
1231 #define MODE_NO_CRC 0x00000400
1232 #define MODE_NO_FRAME_CRACKING 0x00000200
1233 #define MODE_WORD_SWAP_FRAME 0x00000020
1234 #define MODE_BYTE_SWAP_FRAME 0x00000010
1235 #define MODE_WORD_SWAP_NONFRAME 0x00000004
1236 #define MODE_BYTE_SWAP_NONFRAME 0x00000002
1237 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001
1238
1239 /*
1240 * Miscellaneous Configuration Register
1241 *
1242 * This contains various bits relating to power control (which differ
1243 * among different members of the chip family), but the important bits
1244 * for our purposes are the RESET bit and the Timer Prescaler field.
1245 *
1246 * The RESET bit in this register serves to reset the whole chip, even
1247 * including the PCI interface(!) Once it's set, the chip will not
1248 * respond to ANY accesses -- not even CONFIG space -- until the reset
1249 * completes internally. According to the PRM, this should take less
1250 * than 100us. Any access during this period will get a bus error.
1251 *
1252 * The Timer Prescaler field must be programmed so that the timer period
1562 /*
1563 * Architectural constants: absolute maximum numbers of each type of ring
1564 */
1565 #ifdef BGE_EXT_MEM
1566 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */
1567 #else
1568 #define BGE_SEND_RINGS_MAX 4
1569 #endif
1570 #define BGE_SEND_RINGS_MAX_5705 1
1571 #define BGE_RECV_RINGS_MAX 16
1572 #define BGE_RECV_RINGS_MAX_5705 1
1573 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */
1574 /* only with ext mem) */
1575
1576 #define BGE_SEND_SLOTS_MAX 512
1577 #define BGE_STD_SLOTS_MAX 512
1578 #define BGE_JUMBO_SLOTS_MAX 256
1579 #define BGE_MINI_SLOTS_MAX 1024
1580 #define BGE_RECV_SLOTS_MAX 2048
1581 #define BGE_RECV_SLOTS_5705 512
1582 #define BGE_RECV_SLOTS_5782 512
1583 #define BGE_RECV_SLOTS_5721 512
1584
1585 /*
1586 * Hardware-defined Ring Control Block
1587 */
1588 typedef struct {
1589 uint64_t host_ring_addr;
1590 #ifdef _BIG_ENDIAN
1591 uint16_t max_len;
1592 uint16_t flags;
1593 uint32_t nic_ring_addr;
1594 #else
1595 uint32_t nic_ring_addr;
1596 uint16_t flags;
1597 uint16_t max_len;
1598 #endif /* _BIG_ENDIAN */
1599 } bge_rcb_t;
1600
1601 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001
|
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #ifndef _BGE_HW_H
31 #define _BGE_HW_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 #include <sys/types.h>
38
39
40 /*
41 * First section:
42 * Identification of the various Broadcom chips
43 *
44 * Note: the various ID values are *not* all unique ;-(
45 *
46 * Note: the presence of an ID here does *not* imply that the chip is
47 * supported. At this time, only the 5703C, 5704C, and 5704S devices
48 * used on the motherboards of certain Sun products are supported.
49 *
55 #define VENDOR_ID_SUN 0x108e
56
57 #define DEVICE_ID_5700 0x1644
58 #define DEVICE_ID_5700x 0x0003
59 #define DEVICE_ID_5701 0x1645
60 #define DEVICE_ID_5702 0x16a6
61 #define DEVICE_ID_5702fe 0x164d
62 #define DEVICE_ID_5703C 0x16a7
63 #define DEVICE_ID_5703S 0x1647
64 #define DEVICE_ID_5703 0x16c7
65 #define DEVICE_ID_5704C 0x1648
66 #define DEVICE_ID_5704S 0x16a8
67 #define DEVICE_ID_5704 0x1649
68 #define DEVICE_ID_5705C 0x1653
69 #define DEVICE_ID_5705_2 0x1654
70 #define DEVICE_ID_5717 0x1655
71 #define DEVICE_ID_5718 0x1656
72 #define DEVICE_ID_5724 0x165c
73 #define DEVICE_ID_5705M 0x165d
74 #define DEVICE_ID_5705MA3 0x165e
75 #define DEVICE_ID_5719 0x1657
76 #define DEVICE_ID_5720 0x165f
77 #define DEVICE_ID_5705F 0x166e
78 #define DEVICE_ID_5780 0x166a
79 #define DEVICE_ID_5782 0x1696
80 #define DEVICE_ID_5784M 0x1698
81 #define DEVICE_ID_5785 0x1699
82 #define DEVICE_ID_5787 0x169b
83 #define DEVICE_ID_5787M 0x1693
84 #define DEVICE_ID_5788 0x169c
85 #define DEVICE_ID_5789 0x169d
86 #define DEVICE_ID_5751 0x1677
87 #define DEVICE_ID_5751M 0x167d
88 #define DEVICE_ID_5752 0x1600
89 #define DEVICE_ID_5752M 0x1601
90 #define DEVICE_ID_5753 0x16fd
91 #define DEVICE_ID_5754 0x167a
92 #define DEVICE_ID_5755 0x167b
93 #define DEVICE_ID_5755M 0x1673
94 #define DEVICE_ID_5756M 0x1674
95 #define DEVICE_ID_5721 0x1659
96 #define DEVICE_ID_5722 0x165a
97 #define DEVICE_ID_5723 0x165b
98 #define DEVICE_ID_5714C 0x1668
99 #define DEVICE_ID_5714S 0x1669
100 #define DEVICE_ID_5715C 0x1678
101 #define DEVICE_ID_5715S 0x1679
102 #define DEVICE_ID_5761 0x1681
103 #define DEVICE_ID_5761E 0x1680
104 #define DEVICE_ID_5761S 0x1688
105 #define DEVICE_ID_5761SE 0x1689
106 #define DEVICE_ID_5764 0x1684
107 #define DEVICE_ID_5906 0x1712
108 #define DEVICE_ID_5906M 0x1713
109 #define DEVICE_ID_57760 0x1690
110 #define DEVICE_ID_57780 0x1692
111 #define DEVICE_ID_57788 0x1691
112 #define DEVICE_ID_57790 0x1694
113 #define DEVICE_ID_57781 0x16b1
114 #define DEVICE_ID_57785 0x16b5
115 #define DEVICE_ID_57761 0x16b0
116 #define DEVICE_ID_57765 0x16b4
117 #define DEVICE_ID_57791 0x16b2
118 #define DEVICE_ID_57795 0x16b6
119 #define DEVICE_ID_57762 0x1682
120 #define DEVICE_ID_57766 0x1686
121 #define DEVICE_ID_57786 0x16b3
122 #define DEVICE_ID_57782 0x16b7
123
124 #define REVISION_ID_5700_B0 0x10
125 #define REVISION_ID_5700_B2 0x12
126 #define REVISION_ID_5700_B3 0x13
127 #define REVISION_ID_5700_C0 0x20
128 #define REVISION_ID_5700_C1 0x21
129 #define REVISION_ID_5700_C2 0x22
130
131 #define REVISION_ID_5701_A0 0x08
132 #define REVISION_ID_5701_A2 0x12
133 #define REVISION_ID_5701_A3 0x15
134
135 #define REVISION_ID_5702_A0 0x00
136
137 #define REVISION_ID_5703_A0 0x00
138 #define REVISION_ID_5703_A1 0x01
139 #define REVISION_ID_5703_A2 0x02
140
141 #define REVISION_ID_5704_A0 0x00
142 #define REVISION_ID_5704_A1 0x01
194 (bgep->chipid.device == DEVICE_ID_5780) ||\
195 (bgep->chipid.device == DEVICE_ID_5782) ||\
196 (bgep->chipid.device == DEVICE_ID_5788) ||\
197 (bgep->chipid.device == DEVICE_ID_5705_2) ||\
198 (bgep->chipid.device == DEVICE_ID_5754) ||\
199 (bgep->chipid.device == DEVICE_ID_5755) ||\
200 (bgep->chipid.device == DEVICE_ID_5756M) ||\
201 (bgep->chipid.device == DEVICE_ID_5753))
202
203 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \
204 ((bgep->chipid.device == DEVICE_ID_5721) ||\
205 (bgep->chipid.device == DEVICE_ID_5751) ||\
206 (bgep->chipid.device == DEVICE_ID_5751M) ||\
207 (bgep->chipid.device == DEVICE_ID_5752) ||\
208 (bgep->chipid.device == DEVICE_ID_5752M) ||\
209 (bgep->chipid.device == DEVICE_ID_5789))
210
211 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \
212 (bgep->chipid.device == DEVICE_ID_5717) ||\
213 (bgep->chipid.device == DEVICE_ID_5718) ||\
214 (bgep->chipid.device == DEVICE_ID_5719) ||\
215 (bgep->chipid.device == DEVICE_ID_5720) ||\
216 (bgep->chipid.device == DEVICE_ID_5724)
217
218 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \
219 ((bgep->chipid.device == DEVICE_ID_5723) ||\
220 (bgep->chipid.device == DEVICE_ID_5761) ||\
221 (bgep->chipid.device == DEVICE_ID_5761E) ||\
222 (bgep->chipid.device == DEVICE_ID_5761S) ||\
223 (bgep->chipid.device == DEVICE_ID_5761SE) ||\
224 (bgep->chipid.device == DEVICE_ID_5764) ||\
225 (bgep->chipid.device == DEVICE_ID_5784M) ||\
226 (bgep->chipid.device == DEVICE_ID_5785) ||\
227 (bgep->chipid.device == DEVICE_ID_57760) ||\
228 (bgep->chipid.device == DEVICE_ID_57780) ||\
229 (bgep->chipid.device == DEVICE_ID_57788) ||\
230 (bgep->chipid.device == DEVICE_ID_57790))
231
232 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \
233 ((bgep->chipid.device == DEVICE_ID_5714C) ||\
234 (bgep->chipid.device == DEVICE_ID_5714S) ||\
235 (bgep->chipid.device == DEVICE_ID_5715C) ||\
236 (bgep->chipid.device == DEVICE_ID_5715S))
237
238 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \
239 ((bgep->chipid.device == DEVICE_ID_5906) ||\
240 (bgep->chipid.device == DEVICE_ID_5906M))
241
242
243 #define CHIP_TYPE_5705_PLUS (1 << 0)
244 #define CHIP_TYPE_5750_PLUS (1 << 1)
245 #define CHIP_TYPE_5780_CLASS (1 << 2)
246 #define CHIP_TYPE_5755_PLUS (1 << 3)
247 #define CHIP_TYPE_57765_CLASS (1 << 4)
248 #define CHIP_TYPE_57765_PLUS (1 << 5)
249 #define CHIP_TYPE_5717_PLUS (1 << 6)
250
251 #define DEVICE_IS_57765_PLUS(bgep) \
252 (bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
253 #define DEVICE_IS_5755_PLUS(bgep) \
254 (bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)
255
256 /*
257 * Second section:
258 * Offsets of important registers & definitions for bits therein
259 */
260
261 /*
262 * PCI-X registers & bits
263 */
264 #define PCIX_CONF_COMM 0x42
265 #define PCIX_COMM_RELAXED 0x0002
266
267 /*
268 * Miscellaneous Host Control Register, in PCI config space
269 */
270 #define PCI_CONF_BGE_MHCR 0x68
271 #define MHCR_CHIP_REV_MASK 0xffff0000
272 #define MHCR_CHIP_REV_SHIFT 16
273 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
274 #define MHCR_MASK_INTERRUPT_MODE 0x00000100
275 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
276 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040
277 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020
278 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010
279 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008
280 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004
281 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
282 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001
283
284 #define MHCR_CHIP_REV_5703_A0 0x1000
285 #define MHCR_CHIP_REV_5704_A0 0x2000
286 #define MHCR_CHIP_REV_5751_A0 0x4000
287 #define MHCR_CHIP_REV_5721_A0 0x4100
288 #define MHCR_CHIP_REV_5755_A0 0xa000
289 #define MHCR_CHIP_REV_5755_A1 0xa001
290 #define MHCR_CHIP_REV_5719_A0 0x05719000
291 #define MHCR_CHIP_REV_5720_A0 0x05720000
292
293 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) >> 12)
294 #define MHCR_CHIP_ASIC_REV_5700 0x07
295 #define MHCR_CHIP_ASIC_REV_5701 0x00
296 #define MHCR_CHIP_ASIC_REV_5703 0x01
297 #define MHCR_CHIP_ASIC_REV_5704 0x02
298 #define MHCR_CHIP_ASIC_REV_5705 0x03
299 #define MHCR_CHIP_ASIC_REV_5750 0x04
300 #define MHCR_CHIP_ASIC_REV_5752 0x06
301 #define MHCR_CHIP_ASIC_REV_5780 0x08
302 #define MHCR_CHIP_ASIC_REV_5714 0x09
303 #define MHCR_CHIP_ASIC_REV_5755 0x0a
304 #define MHCR_CHIP_ASIC_REV_5787 0x0b
305 #define MHCR_CHIP_ASIC_REV_5906 0x0c
306 #define MHCR_CHIP_ASIC_REV_PRODID 0x0f
307 #define MHCR_CHIP_ASIC_REV_5784 0x5784
308 #define MHCR_CHIP_ASIC_REV_5761 0x5761
309 #define MHCR_CHIP_ASIC_REV_5785 0x5785
310 #define MHCR_CHIP_ASIC_REV_5717 0x5717
311 #define MHCR_CHIP_ASIC_REV_5719 0x5719
312 #define MHCR_CHIP_ASIC_REV_5720 0x5720
313 #define MHCR_CHIP_ASIC_REV_57780 0x57780
314 #define MHCR_CHIP_ASIC_REV_57765 0x57785
315 #define MHCR_CHIP_ASIC_REV_57766 0x57766
316
317 /*
318 * PCI DMA read/write Control Register, in PCI config space
319 *
320 * Note that several fields previously defined here have been deleted
321 * as they are not implemented in the 5703/4.
322 *
323 * Note: the value of this register is critical. It is possible to
324 * cause various unpleasant effects (DTOs, transaction deadlock, etc)
325 * by programming the wrong value. The value #defined below has been
326 * tested and shown to avoid all known problems. If it is to be changed,
327 * correct operation must be reverified on all supported platforms.
328 *
329 * In particular, we set both watermark fields to 2xCacheLineSize (128)
330 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
331 * with Tomatillo's internal pipelines, that otherwise result in stalls,
332 * repeated retries, and DTOs.
333 */
334 #define PCI_CONF_BGE_PDRWCR 0x6c
335 #define PDRWCR_RWCMD_MASK 0xFF000000
336 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000
437 #define PCI_CONF_BGE_MWBAR 0x7c
438 #define PCI_CONF_BGE_MWDAR 0x84
439 #define MWBAR_GRANULARITY 0x00008000 /* 32k */
440 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1)
441 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */
442
443 /*
444 * The PCI express device control register and device status register
445 * which are only applicable on BCM5751 and BCM5721.
446 */
447 #define PCI_CONF_DEV_CTRL 0xd8
448 #define PCI_CONF_DEV_CTRL_5723 0xd4
449 #define READ_REQ_SIZE_MAX 0x5000
450 #define DEV_CTRL_NO_SNOOP 0x0800
451 #define DEV_CTRL_RELAXED 0x0010
452
453 #define PCI_CONF_DEV_STUS 0xda
454 #define PCI_CONF_DEV_STUS_5723 0xd6
455 #define DEVICE_ERROR_STUS 0xf
456
457 #define PCI_CONF_PRODID_ASICREV 0x000000bc
458 #define PCI_CONF_GEN2_PRODID_ASICREV 0x000000f4
459 #define PCI_CONF_GEN15_PRODID_ASICREV 0x000000fc
460
461 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */
462
463 /*
464 * Where to find things in NIC-local (on-chip) memory
465 */
466 #define NIC_MEM_SEND_RINGS 0x0100
467 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring))
468 #define NIC_MEM_RECV_RINGS 0x0200
469 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring))
470 #define NIC_MEM_STATISTICS 0x0300
471 #define NIC_MEM_STATISTICS_SIZE 0x0800
472 #define NIC_MEM_STATUS_BLOCK 0x0b00
473 #define NIC_MEM_STATUS_SIZE 0x0050
474 #define NIC_MEM_GENCOMM 0x0b50
475
476
477 /*
478 * Note: the (non-bogus) values below are appropriate for systems
479 * without external memory. They would be different on a 5700 with
480 * external memory.
516 #define TRANSMIT_MAC_MODE_REG 0x045c
517 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00
518 #define SEND_DATA_COMPLETION_MODE_REG 0x1000
519 #define SEND_BD_SELECTOR_MODE_REG 0x1400
520 #define SEND_BD_INITIATOR_MODE_REG 0x1800
521 #define SEND_BD_COMPLETION_MODE_REG 0x1c00
522
523 #define RECEIVE_MAC_MODE_REG 0x0468
524 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000
525 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400
526 #define RCV_DATA_COMPLETION_MODE_REG 0x2800
527 #define RCV_BD_INITIATOR_MODE_REG 0x2c00
528 #define RCV_BD_COMPLETION_MODE_REG 0x3000
529 #define RCV_LIST_SELECTOR_MODE_REG 0x3400
530
531 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800
532 #define HOST_COALESCE_MODE_REG 0x3c00
533 #define MEMORY_ARBITER_MODE_REG 0x4000
534 #define BUFFER_MANAGER_MODE_REG 0x4400
535 #define READ_DMA_MODE_REG 0x4800
536 #define READ_DMA_RESERVED_CONTROL_REG 0x4900
537 #define WRITE_DMA_MODE_REG 0x4c00
538 #define DMA_COMPLETION_MODE_REG 0x6400
539
540 /*
541 * Other bits in some of the above state machine control registers
542 */
543
544 /*
545 * Transmit MAC Mode Register
546 * (TRANSMIT_MAC_MODE_REG, 0x045c)
547 */
548 #define TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
549 #define TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
550 #define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100
551 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040
552 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
553 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
554
555 /*
556 * Receive MAC Mode Register
557 * (RECEIVE_MAC_MODE_REG, 0x0468)
558 */
559 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400
560 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200
561 #define RECEIVE_MODE_PROMISCUOUS 0x00000100
562 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080
563 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040
564 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020
565 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010
566 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004
567
568 /*
569 * Receive BD Initiator Mode Register
570 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
598 #define COALESCE_CLR_TICKS_RX 0x00000200
599 #define COALESCE_32_BYTE_STATUS 0x00000100
600 #define COALESCE_64_BYTE_STATUS 0x00000080
601 #define COALESCE_NOW 0x00000008
602
603 /*
604 * Memory Arbiter Mode Register
605 * (MEMORY_ARBITER_MODE_REG, 0x4000)
606 */
607 #define MEMORY_ARBITER_ENABLE 0x00000002
608
609 /*
610 * Buffer Manager Mode Register
611 * (BUFFER_MANAGER_MODE_REG, 0x4400)
612 *
613 * In addition to the usual error-attn common to most state machines
614 * this register has a separate bit for attn on running-low-on-mbufs
615 */
616 #define BUFF_MGR_TEST_MODE 0x00000008
617 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
618 #define BUFF_MGR_NO_TX_UNDERRUN 0x80000000
619
620 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014
621
622 /*
623 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
624 * 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
625 * WRITE_DMA_MODE_REG, 0x4c00)
626 *
627 * These registers each contain a 2-bit priority field, which controls
628 * the relative priority of that type of DMA (read vs. write vs. MSI),
629 * and a set of bits that control whether ATTN is asserted on each
630 * particular condition
631 */
632 #define DMA_PRIORITY_MASK 0xc0000000
633 #define DMA_PRIORITY_SHIFT 30
634 #define ALL_DMA_ATTN_BITS 0x000003fc
635
636 #define RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
637 #define RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
638 #define RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
639 #define RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
640 #define RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
641 #define RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
642 #define RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
643
644
645 /*
646 * BCM5755, 5755M, 5906, 5906M only
647 * 1 - Enable Fix. Device will send out the status block before
648 * the interrupt message
649 * 0 - Disable fix. Device will send out the interrupt message
650 * before the status block
651 */
652 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000
653
654 /* 5720 only */
655 #define DMA_H2BNC_VLAN_DET 0x20000000
656
657
658 /*
659 * End of state machine control register definitions
660 */
661
662
663 /*
664 * High priority mailbox registers.
665 * Mailbox Registers (8 bytes each, but high half unused)
666 */
667 #define INTERRUPT_MBOX_0_REG 0x0200
668 #define INTERRUPT_MBOX_1_REG 0x0208
669 #define INTERRUPT_MBOX_2_REG 0x0210
670 #define INTERRUPT_MBOX_3_REG 0x0218
671 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n))
672
673 /*
674 * Low priority mailbox registers, for BCM5906, BCM5906M.
675 */
676 #define INTERRUPT_LP_MBOX_0_REG 0x5800
677
775 * usually only has one h/w address. The value in register 0 is
776 * used for pause packets; any of the four can be specified for
777 * substitution into other transmitted packets if required.
778 */
779 #define MAC_ADDRESS_0_REG 0x0410
780 #define MAC_ADDRESS_1_REG 0x0418
781 #define MAC_ADDRESS_2_REG 0x0420
782 #define MAC_ADDRESS_3_REG 0x0428
783
784 #define MAC_ADDRESS_REG(n) (0x0410+8*(n))
785 #define MAC_ADDRESS_REGS_MAX 4
786
787 /*
788 * More MAC Registers ...
789 */
790 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438
791 #define MAC_RX_MTU_SIZE_REG 0x043c
792 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
793 #define MAC_TX_LENGTHS_REG 0x0464
794 #define MAC_TX_LENGTHS_DEFAULT 0x00002620
795 #define MAC_TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
796 #define MAC_TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
797
798 /*
799 * MII access registers
800 */
801 #define MI_COMMS_REG 0x044c
802 #define MI_COMMS_START 0x20000000
803 #define MI_COMMS_READ_FAILED 0x10000000
804 #define MI_COMMS_COMMAND_MASK 0x0c000000
805 #define MI_COMMS_COMMAND_READ 0x08000000
806 #define MI_COMMS_COMMAND_WRITE 0x04000000
807 #define MI_COMMS_ADDRESS_MASK 0x03e00000
808 #define MI_COMMS_ADDRESS_SHIFT 21
809 #define MI_COMMS_REGISTER_MASK 0x001f0000
810 #define MI_COMMS_REGISTER_SHIFT 16
811 #define MI_COMMS_DATA_MASK 0x0000ffff
812 #define MI_COMMS_DATA_SHIFT 0
813
814 #define MI_STATUS_REG 0x0450
815 #define MI_STATUS_10MBPS 0x00000002
816 #define MI_STATUS_LINK 0x00000001
1065
1066 /*
1067 * Receive Buffer Descriptor Ring Control Block Registers
1068 * NB: sixteen bytes (128 bits) each
1069 */
1070 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440
1071 #define STD_RCV_BD_RING_RCB_REG 0x2450
1072 #define MINI_RCV_BD_RING_RCB_REG 0x2460
1073
1074 /*
1075 * Receive Buffer Descriptor Ring Replenish Threshold Registers
1076 */
1077 #define MINI_RCV_BD_REPLENISH_REG 0x2c14
1078 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */
1079 #define STD_RCV_BD_REPLENISH_REG 0x2c18
1080 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */
1081 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c
1082 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */
1083
1084 /*
1085 * CPMU registers (5717/5718/5719/5720 only)
1086 */
1087 #define CPMU_CLCK_ORIDE_REG 0x3624
1088 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1089
1090 #define CPMU_STATUS_REG 0x362c
1091 #define CPMU_STATUS_FUN_NUM_5717 0x20000000
1092 #define CPMU_STATUS_FUN_NUM_5719 0xc0000000
1093 #define CPMU_STATUS_FUN_NUM_5719_SHIFT 30
1094
1095
1096 /*
1097 * Host Coalescing Engine Control Registers
1098 */
1099 #define RCV_COALESCE_TICKS_REG 0x3c08
1100 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1101 #define SEND_COALESCE_TICKS_REG 0x3c0c
1102 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1103 #define RCV_COALESCE_MAX_BD_REG 0x3c10
1104 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1105 #define SEND_COALESCE_MAX_BD_REG 0x3c14
1106 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1107 #define RCV_COALESCE_INT_TICKS_REG 0x3c18
1108 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1109 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c
1110 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1111 #define RCV_COALESCE_INT_BD_REG 0x3c20
1112 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1113 #define SEND_COALESCE_INT_BD_REG 0x3c24
1114 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1115 #define STATISTICS_TICKS_REG 0x3c28
1193 /*
1194 * RX/TX RISC Registers
1195 */
1196 #define RX_RISC_MODE_REG 0x5000
1197 #define RX_RISC_STATE_REG 0x5004
1198 #define RX_RISC_PC_REG 0x501c
1199 #define TX_RISC_MODE_REG 0x5400
1200 #define TX_RISC_STATE_REG 0x5404
1201 #define TX_RISC_PC_REG 0x541c
1202
1203 /*
1204 * V? RISC Registerss
1205 */
1206 #define VCPU_STATUS_REG 0x5100
1207 #define VCPU_INIT_DONE 0x04000000
1208 #define VCPU_DRV_RESET 0x08000000
1209
1210 #define VCPU_EXT_CTL 0x6890
1211 #define VCPU_EXT_CTL_HALF 0x00400000
1212
1213 #define GRC_FASTBOOT_PC 0x6894
1214
1215 #define FTQ_RESET_REG 0x5c00
1216
1217 #define MSI_MODE_REG 0x6000
1218 #define MSI_PRI_HIGHEST 0xc0000000
1219 #define MSI_MSI_ENABLE 0x00000002
1220 #define MSI_ERROR_ATTENTION 0x0000001c
1221
1222 #define MSI_STATUS_REG 0x6004
1223
1224 #define MODE_CONTROL_REG 0x6800
1225 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000
1226 #define MODE_4X_NIC_SEND_RINGS 0x20000000
1227 #define MODE_INT_ON_FLOW_ATTN 0x10000000
1228 #define MODE_INT_ON_DMA_ATTN 0x08000000
1229 #define MODE_INT_ON_MAC_ATTN 0x04000000
1230 #define MODE_INT_ON_RXRISC_ATTN 0x02000000
1231 #define MODE_INT_ON_TXRISC_ATTN 0x01000000
1232 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
1233 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
1234 #define MODE_HTX2B_ENABLE 0x00040000
1235 #define MODE_HOST_SEND_BDS 0x00020000
1236 #define MODE_HOST_STACK_UP 0x00010000
1237 #define MODE_FORCE_32_BIT_PCI 0x00008000
1238 #define MODE_B2HRX_ENABLE 0x00008000
1239 #define MODE_NO_INT_ON_RECV 0x00004000
1240 #define MODE_NO_INT_ON_SEND 0x00002000
1241 #define MODE_ALLOW_BAD_FRAMES 0x00000800
1242 #define MODE_NO_CRC 0x00000400
1243 #define MODE_NO_FRAME_CRACKING 0x00000200
1244 #define MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1245 #define MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1246 #define MODE_WORD_SWAP_FRAME 0x00000020
1247 #define MODE_BYTE_SWAP_FRAME 0x00000010
1248 #define MODE_WORD_SWAP_NONFRAME 0x00000004
1249 #define MODE_BYTE_SWAP_NONFRAME 0x00000002
1250 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001
1251
1252 /*
1253 * Miscellaneous Configuration Register
1254 *
1255 * This contains various bits relating to power control (which differ
1256 * among different members of the chip family), but the important bits
1257 * for our purposes are the RESET bit and the Timer Prescaler field.
1258 *
1259 * The RESET bit in this register serves to reset the whole chip, even
1260 * including the PCI interface(!) Once it's set, the chip will not
1261 * respond to ANY accesses -- not even CONFIG space -- until the reset
1262 * completes internally. According to the PRM, this should take less
1263 * than 100us. Any access during this period will get a bus error.
1264 *
1265 * The Timer Prescaler field must be programmed so that the timer period
1575 /*
1576 * Architectural constants: absolute maximum numbers of each type of ring
1577 */
1578 #ifdef BGE_EXT_MEM
1579 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */
1580 #else
1581 #define BGE_SEND_RINGS_MAX 4
1582 #endif
1583 #define BGE_SEND_RINGS_MAX_5705 1
1584 #define BGE_RECV_RINGS_MAX 16
1585 #define BGE_RECV_RINGS_MAX_5705 1
1586 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */
1587 /* only with ext mem) */
1588
1589 #define BGE_SEND_SLOTS_MAX 512
1590 #define BGE_STD_SLOTS_MAX 512
1591 #define BGE_JUMBO_SLOTS_MAX 256
1592 #define BGE_MINI_SLOTS_MAX 1024
1593 #define BGE_RECV_SLOTS_MAX 2048
1594 #define BGE_RECV_SLOTS_5705 512
1595 #define BGE_RECV_SLOTS_5717 1024
1596 #define BGE_RECV_SLOTS_5782 512
1597 #define BGE_RECV_SLOTS_5721 512
1598
1599 /*
1600 * Hardware-defined Ring Control Block
1601 */
1602 typedef struct {
1603 uint64_t host_ring_addr;
1604 #ifdef _BIG_ENDIAN
1605 uint16_t max_len;
1606 uint16_t flags;
1607 uint32_t nic_ring_addr;
1608 #else
1609 uint32_t nic_ring_addr;
1610 uint16_t flags;
1611 uint16_t max_len;
1612 #endif /* _BIG_ENDIAN */
1613 } bge_rcb_t;
1614
1615 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001
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