--- old/usr/src/uts/common/io/bge/bge_hw.h	Fri Jan 11 13:34:55 2013
+++ new/usr/src/uts/common/io/bge/bge_hw.h	Fri Jan 11 13:34:55 2013
@@ -23,6 +23,10 @@
  * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
  */
 
+/*
+ * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
+ */
+
 #ifndef _BGE_HW_H
 #define	_BGE_HW_H
 
@@ -68,6 +72,8 @@
 #define	DEVICE_ID_5724			0x165c
 #define	DEVICE_ID_5705M			0x165d
 #define	DEVICE_ID_5705MA3		0x165e
+#define	DEVICE_ID_5719			0x1657
+#define	DEVICE_ID_5720			0x165f
 #define	DEVICE_ID_5705F			0x166e
 #define	DEVICE_ID_5780			0x166a
 #define	DEVICE_ID_5782			0x1696
@@ -104,6 +110,16 @@
 #define	DEVICE_ID_57780			0x1692
 #define	DEVICE_ID_57788			0x1691
 #define	DEVICE_ID_57790			0x1694
+#define	DEVICE_ID_57781			0x16b1
+#define	DEVICE_ID_57785			0x16b5
+#define	DEVICE_ID_57761			0x16b0
+#define	DEVICE_ID_57765			0x16b4
+#define	DEVICE_ID_57791			0x16b2
+#define	DEVICE_ID_57795			0x16b6
+#define	DEVICE_ID_57762			0x1682
+#define	DEVICE_ID_57766			0x1686
+#define	DEVICE_ID_57786			0x16b3
+#define	DEVICE_ID_57782			0x16b7
 
 #define	REVISION_ID_5700_B0		0x10
 #define	REVISION_ID_5700_B2		0x12
@@ -195,6 +211,8 @@
 #define	DEVICE_5717_SERIES_CHIPSETS(bgep) \
 		(bgep->chipid.device == DEVICE_ID_5717) ||\
 		(bgep->chipid.device == DEVICE_ID_5718) ||\
+		(bgep->chipid.device == DEVICE_ID_5719) ||\
+		(bgep->chipid.device == DEVICE_ID_5720) ||\
 		(bgep->chipid.device == DEVICE_ID_5724)
 
 #define	DEVICE_5723_SERIES_CHIPSETS(bgep) \
@@ -221,6 +239,20 @@
 		((bgep->chipid.device == DEVICE_ID_5906) ||\
 		(bgep->chipid.device == DEVICE_ID_5906M))
 
+
+#define	CHIP_TYPE_5705_PLUS   (1 << 0)
+#define	CHIP_TYPE_5750_PLUS   (1 << 1)
+#define	CHIP_TYPE_5780_CLASS  (1 << 2)
+#define	CHIP_TYPE_5755_PLUS   (1 << 3)
+#define	CHIP_TYPE_57765_CLASS (1 << 4)
+#define	CHIP_TYPE_57765_PLUS  (1 << 5)
+#define	CHIP_TYPE_5717_PLUS   (1 << 6)
+
+#define	DEVICE_IS_57765_PLUS(bgep) \
+	(bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
+#define	DEVICE_IS_5755_PLUS(bgep) \
+	(bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)
+
 /*
  * Second section:
  *	Offsets of important registers & definitions for bits therein
@@ -237,6 +269,7 @@
  */
 #define	PCI_CONF_BGE_MHCR		0x68
 #define	MHCR_CHIP_REV_MASK		0xffff0000
+#define	MHCR_CHIP_REV_SHIFT		16
 #define	MHCR_ENABLE_TAGGED_STATUS_MODE	0x00000200
 #define	MHCR_MASK_INTERRUPT_MODE	0x00000100
 #define	MHCR_ENABLE_INDIRECT_ACCESS	0x00000080
@@ -248,96 +281,39 @@
 #define	MHCR_MASK_PCI_INT_OUTPUT	0x00000002
 #define	MHCR_CLEAR_INTERRUPT_INTA	0x00000001
 
-#define	MHCR_CHIP_REV_5700_B0		0x71000000
-#define	MHCR_CHIP_REV_5700_B2		0x71020000
-#define	MHCR_CHIP_REV_5700_B3		0x71030000
-#define	MHCR_CHIP_REV_5700_C0		0x72000000
-#define	MHCR_CHIP_REV_5700_C1		0x72010000
-#define	MHCR_CHIP_REV_5700_C2		0x72020000
+#define	MHCR_CHIP_REV_5703_A0		0x1000
+#define	MHCR_CHIP_REV_5704_A0		0x2000
+#define	MHCR_CHIP_REV_5751_A0		0x4000
+#define	MHCR_CHIP_REV_5721_A0		0x4100
+#define	MHCR_CHIP_REV_5755_A0		0xa000
+#define	MHCR_CHIP_REV_5755_A1		0xa001
+#define	MHCR_CHIP_REV_5719_A0		0x05719000
+#define	MHCR_CHIP_REV_5720_A0		0x05720000
 
-#define	MHCR_CHIP_REV_5701_A0		0x00000000
-#define	MHCR_CHIP_REV_5701_A2		0x00020000
-#define	MHCR_CHIP_REV_5701_A3		0x00030000
-#define	MHCR_CHIP_REV_5701_A5		0x01050000
+#define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) >> 12)
+#define	MHCR_CHIP_ASIC_REV_5700		0x07
+#define	MHCR_CHIP_ASIC_REV_5701		0x00
+#define	MHCR_CHIP_ASIC_REV_5703		0x01
+#define	MHCR_CHIP_ASIC_REV_5704		0x02
+#define	MHCR_CHIP_ASIC_REV_5705		0x03
+#define	MHCR_CHIP_ASIC_REV_5750		0x04
+#define	MHCR_CHIP_ASIC_REV_5752		0x06
+#define	MHCR_CHIP_ASIC_REV_5780		0x08
+#define	MHCR_CHIP_ASIC_REV_5714		0x09
+#define	MHCR_CHIP_ASIC_REV_5755		0x0a
+#define	MHCR_CHIP_ASIC_REV_5787		0x0b
+#define	MHCR_CHIP_ASIC_REV_5906		0x0c
+#define	MHCR_CHIP_ASIC_REV_PRODID	0x0f
+#define	MHCR_CHIP_ASIC_REV_5784		0x5784
+#define	MHCR_CHIP_ASIC_REV_5761		0x5761
+#define	MHCR_CHIP_ASIC_REV_5785		0x5785
+#define	MHCR_CHIP_ASIC_REV_5717		0x5717
+#define	MHCR_CHIP_ASIC_REV_5719		0x5719
+#define	MHCR_CHIP_ASIC_REV_5720		0x5720
+#define	MHCR_CHIP_ASIC_REV_57780	0x57780
+#define	MHCR_CHIP_ASIC_REV_57765	0x57785
+#define	MHCR_CHIP_ASIC_REV_57766	0x57766
 
-#define	MHCR_CHIP_REV_5702_A0		0x10000000
-#define	MHCR_CHIP_REV_5702_A1		0x10010000
-#define	MHCR_CHIP_REV_5702_A2		0x10020000
-
-#define	MHCR_CHIP_REV_5703_A0		0x10000000
-#define	MHCR_CHIP_REV_5703_A1		0x10010000
-#define	MHCR_CHIP_REV_5703_A2		0x10020000
-#define	MHCR_CHIP_REV_5703_B0		0x11000000
-#define	MHCR_CHIP_REV_5703_B1		0x11010000
-
-#define	MHCR_CHIP_REV_5704_A0		0x20000000
-#define	MHCR_CHIP_REV_5704_A1		0x20010000
-#define	MHCR_CHIP_REV_5704_A2		0x20020000
-#define	MHCR_CHIP_REV_5704_A3		0x20030000
-#define	MHCR_CHIP_REV_5704_B0		0x21000000
-
-#define	MHCR_CHIP_REV_5705_A0		0x30000000
-#define	MHCR_CHIP_REV_5705_A1		0x30010000
-#define	MHCR_CHIP_REV_5705_A2		0x30020000
-#define	MHCR_CHIP_REV_5705_A3		0x30030000
-#define	MHCR_CHIP_REV_5705_A5		0x30050000
-
-#define	MHCR_CHIP_REV_5782_A0		0x30030000
-#define	MHCR_CHIP_REV_5782_A1		0x30030088
-
-#define	MHCR_CHIP_REV_5788_A1		0x30050000
-
-#define	MHCR_CHIP_REV_5751_A0		0x40000000
-#define	MHCR_CHIP_REV_5751_A1		0x40010000
-
-#define	MHCR_CHIP_REV_5721_A0		0x41000000
-#define	MHCR_CHIP_REV_5721_A1		0x41010000
-
-#define	MHCR_CHIP_REV_5714_A0		0x50000000
-#define	MHCR_CHIP_REV_5714_A1		0x90010000
-
-#define	MHCR_CHIP_REV_5715_A0		0x50000000
-#define	MHCR_CHIP_REV_5715_A1		0x90010000
-
-#define	MHCR_CHIP_REV_5715S_A0		0x50000000
-#define	MHCR_CHIP_REV_5715S_A1		0x90010000
-
-#define	MHCR_CHIP_REV_5754_A0		0xb0000000
-#define	MHCR_CHIP_REV_5754_A1		0xb0010000
-
-#define	MHCR_CHIP_REV_5787_A0		0xb0000000
-#define	MHCR_CHIP_REV_5787_A1		0xb0010000
-#define	MHCR_CHIP_REV_5787_A2		0xb0020000
-
-#define	MHCR_CHIP_REV_5755_A0		0xa0000000
-#define	MHCR_CHIP_REV_5755_A1		0xa0010000
-
-#define	MHCR_CHIP_REV_5906_A0		0xc0000000
-#define	MHCR_CHIP_REV_5906_A1		0xc0010000
-#define	MHCR_CHIP_REV_5906_A2		0xc0020000
-
-#define	MHCR_CHIP_REV_5723_A0		0xf0000000
-#define	MHCR_CHIP_REV_5723_A1		0xf0010000
-#define	MHCR_CHIP_REV_5723_A2		0xf0020000
-#define	MHCR_CHIP_REV_5723_B0		0xf1000000
-
-#define	MHCR_CHIP_ASIC_REV(ChipRevId)	((ChipRevId) & 0xf0000000)
-#define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
-#define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
-#define	MHCR_CHIP_ASIC_REV_5703		(0x1 << 28)
-#define	MHCR_CHIP_ASIC_REV_5704		(0x2 << 28)
-#define	MHCR_CHIP_ASIC_REV_5705		(0x3 << 28)
-#define	MHCR_CHIP_ASIC_REV_5721_5751	(0x4 << 28)
-#define	MHCR_CHIP_ASIC_REV_5714 	(0x5 << 28)
-#define	MHCR_CHIP_ASIC_REV_5752		(0x6 << 28)
-#define	MHCR_CHIP_ASIC_REV_5754		(0xb << 28)
-#define	MHCR_CHIP_ASIC_REV_5787		((uint32_t)0xb << 28)
-#define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
-#define	MHCR_CHIP_ASIC_REV_5715 	((uint32_t)0x9 << 28)
-#define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
-#define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
-
-
 /*
  * PCI DMA read/write Control Register, in PCI config space
  *
@@ -478,6 +454,10 @@
 #define	PCI_CONF_DEV_STUS_5723		0xd6
 #define	DEVICE_ERROR_STUS		0xf
 
+#define	PCI_CONF_PRODID_ASICREV		0x000000bc
+#define	PCI_CONF_GEN2_PRODID_ASICREV	0x000000f4
+#define	PCI_CONF_GEN15_PRODID_ASICREV	0x000000fc
+
 #define	NIC_MEM_WINDOW_OFFSET		0x00008000	/* 32k	*/
 
 /*
@@ -553,6 +533,7 @@
 #define	MEMORY_ARBITER_MODE_REG		0x4000
 #define	BUFFER_MANAGER_MODE_REG		0x4400
 #define	READ_DMA_MODE_REG		0x4800
+#define	READ_DMA_RESERVED_CONTROL_REG	0x4900
 #define	WRITE_DMA_MODE_REG		0x4c00
 #define	DMA_COMPLETION_MODE_REG		0x6400
 
@@ -564,6 +545,9 @@
  * Transmit MAC Mode Register
  * (TRANSMIT_MAC_MODE_REG, 0x045c)
  */
+#define	TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
+#define	TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
+#define	TRANSMIT_MODE_MBUF_LOCKUP_FIX	0x00000100
 #define	TRANSMIT_MODE_LONG_PAUSE	0x00000040
 #define	TRANSMIT_MODE_BIG_BACKOFF	0x00000020
 #define	TRANSMIT_MODE_FLOW_CONTROL	0x00000010
@@ -631,12 +615,14 @@
  */
 #define	BUFF_MGR_TEST_MODE		0x00000008
 #define	BUFF_MGR_MBUF_LOW_ATTN_ENABLE	0x00000010
+#define	BUFF_MGR_NO_TX_UNDERRUN		0x80000000
 
 #define	BUFF_MGR_ALL_ATTN_BITS		0x00000014
 
 /*
  * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
- * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
+ * 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
+ * WRITE_DMA_MODE_REG, 0x4c00)
  *
  * These registers each contain a 2-bit priority field, which controls
  * the relative priority of that type of DMA (read vs. write vs. MSI),
@@ -647,6 +633,15 @@
 #define	DMA_PRIORITY_SHIFT		30
 #define	ALL_DMA_ATTN_BITS		0x000003fc
 
+#define	RDMA_RSRVCTRL_FIFO_OFLW_FIX	 0x00000004
+#define	RDMA_RSRVCTRL_FIFO_LWM_1_5K	 0x00000c00
+#define	RDMA_RSRVCTRL_FIFO_LWM_MASK	 0x00000ff0
+#define	RDMA_RSRVCTRL_FIFO_HWM_1_5K	 0x000c0000
+#define	RDMA_RSRVCTRL_FIFO_HWM_MASK	 0x000ff000
+#define	RDMA_RSRVCTRL_TXMRGN_320B	 0x28000000
+#define	RDMA_RSRVCTRL_TXMRGN_MASK	 0xffe00000
+
+
 /*
  * BCM5755, 5755M, 5906, 5906M only
  * 1 - Enable Fix. Device will send out the status block before
@@ -656,6 +651,10 @@
  */
 #define	DMA_STATUS_TAG_FIX_CQ12384	0x20000000
 
+/* 5720 only */
+#define	DMA_H2BNC_VLAN_DET		0x20000000
+
+
 /*
  * End of state machine control register definitions
  */
@@ -793,6 +792,8 @@
 #define	MAC_RX_MTU_DEFAULT		0x000005f2	/* 1522	*/
 #define	MAC_TX_LENGTHS_REG		0x0464
 #define	MAC_TX_LENGTHS_DEFAULT		0x00002620
+#define	MAC_TX_LENGTHS_JMB_FRM_LEN_MSK	 0x00ff0000
+#define	MAC_TX_LENGTHS_CNT_DWN_VAL_MSK	 0xff000000
 
 /*
  * MII access registers
@@ -1081,11 +1082,17 @@
 #define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
 
 /*
- * CPMU registers (5717/5718 only)
+ * CPMU registers (5717/5718/5719/5720 only)
  */
-#define	CPMU_STATUS_REG	0x362c
-#define	CPMU_STATUS_FUN_NUM	0x20000000
+#define	CPMU_CLCK_ORIDE_REG		0x3624
+#define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
 
+#define	CPMU_STATUS_REG			0x362c
+#define	CPMU_STATUS_FUN_NUM_5717	0x20000000
+#define	CPMU_STATUS_FUN_NUM_5719	0xc0000000
+#define	CPMU_STATUS_FUN_NUM_5719_SHIFT	30
+
+
 /*
  * Host Coalescing Engine Control Registers
  */
@@ -1203,6 +1210,8 @@
 #define	VCPU_EXT_CTL			0x6890
 #define	VCPU_EXT_CTL_HALF		0x00400000
 
+#define	GRC_FASTBOOT_PC			0x6894
+
 #define	FTQ_RESET_REG			0x5c00
 
 #define	MSI_MODE_REG			0x6000
@@ -1222,14 +1231,18 @@
 #define	MODE_INT_ON_TXRISC_ATTN		0x01000000
 #define	MODE_RECV_NO_PSEUDO_HDR_CSUM	0x00800000
 #define	MODE_SEND_NO_PSEUDO_HDR_CSUM	0x00100000
+#define	MODE_HTX2B_ENABLE		0x00040000
 #define	MODE_HOST_SEND_BDS		0x00020000
 #define	MODE_HOST_STACK_UP		0x00010000
 #define	MODE_FORCE_32_BIT_PCI		0x00008000
+#define	MODE_B2HRX_ENABLE		0x00008000
 #define	MODE_NO_INT_ON_RECV		0x00004000
 #define	MODE_NO_INT_ON_SEND		0x00002000
 #define	MODE_ALLOW_BAD_FRAMES		0x00000800
 #define	MODE_NO_CRC			0x00000400
 #define	MODE_NO_FRAME_CRACKING		0x00000200
+#define	MODE_WORD_SWAP_B2HRX_DATA	0x00000080
+#define	MODE_BYTE_SWAP_B2HRX_DATA	0x00000040
 #define	MODE_WORD_SWAP_FRAME		0x00000020
 #define	MODE_BYTE_SWAP_FRAME		0x00000010
 #define	MODE_WORD_SWAP_NONFRAME		0x00000004
@@ -1258,7 +1271,7 @@
  */
 #define	CORE_CLOCK_MHZ			66
 #define	MISC_CONFIG_REG			0x6804
-#define	MISC_CONFIG_GRC_RESET_DISABLE   0x20000000
+#define	MISC_CONFIG_GRC_RESET_DISABLE	0x20000000
 #define	MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
 #define	MISC_CONFIG_POWERDOWN		0x00100000
 #define	MISC_CONFIG_POWER_STATE		0x00060000
@@ -1579,6 +1592,7 @@
 #define	BGE_MINI_SLOTS_MAX		1024
 #define	BGE_RECV_SLOTS_MAX		2048
 #define	BGE_RECV_SLOTS_5705		512
+#define	BGE_RECV_SLOTS_5717		1024
 #define	BGE_RECV_SLOTS_5782		512
 #define	BGE_RECV_SLOTS_5721		512
 
