1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #ifndef _BGE_HW_H
31 #define _BGE_HW_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 #include <sys/types.h>
38
39
40 /*
41 * First section:
42 * Identification of the various Broadcom chips
43 *
44 * Note: the various ID values are *not* all unique ;-(
45 *
46 * Note: the presence of an ID here does *not* imply that the chip is
47 * supported. At this time, only the 5703C, 5704C, and 5704S devices
48 * used on the motherboards of certain Sun products are supported.
49 *
50 * Note: the revision-id values in the PCI revision ID register are
51 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead.
52 */
53
54 #define VENDOR_ID_BROADCOM 0x14e4
55 #define VENDOR_ID_SUN 0x108e
56
57 #define DEVICE_ID_5700 0x1644
58 #define DEVICE_ID_5700x 0x0003
59 #define DEVICE_ID_5701 0x1645
60 #define DEVICE_ID_5702 0x16a6
61 #define DEVICE_ID_5702fe 0x164d
62 #define DEVICE_ID_5703C 0x16a7
63 #define DEVICE_ID_5703S 0x1647
64 #define DEVICE_ID_5703 0x16c7
65 #define DEVICE_ID_5704C 0x1648
66 #define DEVICE_ID_5704S 0x16a8
67 #define DEVICE_ID_5704 0x1649
68 #define DEVICE_ID_5705C 0x1653
69 #define DEVICE_ID_5705_2 0x1654
70 #define DEVICE_ID_5717 0x1655
71 #define DEVICE_ID_5718 0x1656
72 #define DEVICE_ID_5724 0x165c
73 #define DEVICE_ID_5705M 0x165d
74 #define DEVICE_ID_5705MA3 0x165e
75 #define DEVICE_ID_5719 0x1657
76 #define DEVICE_ID_5720 0x165f
77 #define DEVICE_ID_5705F 0x166e
78 #define DEVICE_ID_5780 0x166a
79 #define DEVICE_ID_5782 0x1696
80 #define DEVICE_ID_5784M 0x1698
81 #define DEVICE_ID_5785 0x1699
82 #define DEVICE_ID_5787 0x169b
83 #define DEVICE_ID_5787M 0x1693
84 #define DEVICE_ID_5788 0x169c
85 #define DEVICE_ID_5789 0x169d
86 #define DEVICE_ID_5751 0x1677
87 #define DEVICE_ID_5751M 0x167d
88 #define DEVICE_ID_5752 0x1600
89 #define DEVICE_ID_5752M 0x1601
90 #define DEVICE_ID_5753 0x16fd
91 #define DEVICE_ID_5754 0x167a
92 #define DEVICE_ID_5755 0x167b
93 #define DEVICE_ID_5755M 0x1673
94 #define DEVICE_ID_5756M 0x1674
95 #define DEVICE_ID_5721 0x1659
96 #define DEVICE_ID_5722 0x165a
97 #define DEVICE_ID_5723 0x165b
98 #define DEVICE_ID_5714C 0x1668
99 #define DEVICE_ID_5714S 0x1669
100 #define DEVICE_ID_5715C 0x1678
101 #define DEVICE_ID_5715S 0x1679
102 #define DEVICE_ID_5761 0x1681
103 #define DEVICE_ID_5761E 0x1680
104 #define DEVICE_ID_5761S 0x1688
105 #define DEVICE_ID_5761SE 0x1689
106 #define DEVICE_ID_5764 0x1684
107 #define DEVICE_ID_5906 0x1712
108 #define DEVICE_ID_5906M 0x1713
109 #define DEVICE_ID_57760 0x1690
110 #define DEVICE_ID_57780 0x1692
111 #define DEVICE_ID_57788 0x1691
112 #define DEVICE_ID_57790 0x1694
113 #define DEVICE_ID_57781 0x16b1
114 #define DEVICE_ID_57785 0x16b5
115 #define DEVICE_ID_57761 0x16b0
116 #define DEVICE_ID_57765 0x16b4
117 #define DEVICE_ID_57791 0x16b2
118 #define DEVICE_ID_57795 0x16b6
119 #define DEVICE_ID_57762 0x1682
120 #define DEVICE_ID_57766 0x1686
121 #define DEVICE_ID_57786 0x16b3
122 #define DEVICE_ID_57782 0x16b7
123
124 #define REVISION_ID_5700_B0 0x10
125 #define REVISION_ID_5700_B2 0x12
126 #define REVISION_ID_5700_B3 0x13
127 #define REVISION_ID_5700_C0 0x20
128 #define REVISION_ID_5700_C1 0x21
129 #define REVISION_ID_5700_C2 0x22
130
131 #define REVISION_ID_5701_A0 0x08
132 #define REVISION_ID_5701_A2 0x12
133 #define REVISION_ID_5701_A3 0x15
134
135 #define REVISION_ID_5702_A0 0x00
136
137 #define REVISION_ID_5703_A0 0x00
138 #define REVISION_ID_5703_A1 0x01
139 #define REVISION_ID_5703_A2 0x02
140
141 #define REVISION_ID_5704_A0 0x00
142 #define REVISION_ID_5704_A1 0x01
143 #define REVISION_ID_5704_A2 0x02
144 #define REVISION_ID_5704_A3 0x03
145 #define REVISION_ID_5704_B0 0x10
146
147 #define REVISION_ID_5705_A0 0x00
148 #define REVISION_ID_5705_A1 0x01
149 #define REVISION_ID_5705_A2 0x02
150 #define REVISION_ID_5705_A3 0x03
151
152 #define REVISION_ID_5721_A0 0x00
153 #define REVISION_ID_5721_A1 0x01
154
155 #define REVISION_ID_5751_A0 0x00
156 #define REVISION_ID_5751_A1 0x01
157
158 #define REVISION_ID_5714_A0 0x00
159 #define REVISION_ID_5714_A1 0x01
160 #define REVISION_ID_5714_A2 0xA2
161 #define REVISION_ID_5714_A3 0xA3
162
163 #define REVISION_ID_5715_A0 0x00
164 #define REVISION_ID_5715_A1 0x01
165 #define REVISION_ID_5715_A2 0xA2
166
167 #define REVISION_ID_5715S_A0 0x00
168 #define REVISION_ID_5715S_A1 0x01
169
170 #define REVISION_ID_5754_A0 0x00
171 #define REVISION_ID_5754_A1 0x01
172
173 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\
174 ((bgep->chipid.device == DEVICE_ID_5700) ||\
175 (bgep->chipid.device == DEVICE_ID_5701) ||\
176 (bgep->chipid.device == DEVICE_ID_5702) ||\
177 (bgep->chipid.device == DEVICE_ID_5702fe)||\
178 (bgep->chipid.device == DEVICE_ID_5703C) ||\
179 (bgep->chipid.device == DEVICE_ID_5703S) ||\
180 (bgep->chipid.device == DEVICE_ID_5703) ||\
181 (bgep->chipid.device == DEVICE_ID_5704C) ||\
182 (bgep->chipid.device == DEVICE_ID_5704S) ||\
183 (bgep->chipid.device == DEVICE_ID_5704))
184
185 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \
186 ((bgep->chipid.device == DEVICE_ID_5702) ||\
187 (bgep->chipid.device == DEVICE_ID_5702fe))
188
189 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \
190 ((bgep->chipid.device == DEVICE_ID_5705C) ||\
191 (bgep->chipid.device == DEVICE_ID_5705M) ||\
192 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\
193 (bgep->chipid.device == DEVICE_ID_5705F) ||\
194 (bgep->chipid.device == DEVICE_ID_5780) ||\
195 (bgep->chipid.device == DEVICE_ID_5782) ||\
196 (bgep->chipid.device == DEVICE_ID_5788) ||\
197 (bgep->chipid.device == DEVICE_ID_5705_2) ||\
198 (bgep->chipid.device == DEVICE_ID_5754) ||\
199 (bgep->chipid.device == DEVICE_ID_5755) ||\
200 (bgep->chipid.device == DEVICE_ID_5756M) ||\
201 (bgep->chipid.device == DEVICE_ID_5753))
202
203 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \
204 ((bgep->chipid.device == DEVICE_ID_5721) ||\
205 (bgep->chipid.device == DEVICE_ID_5751) ||\
206 (bgep->chipid.device == DEVICE_ID_5751M) ||\
207 (bgep->chipid.device == DEVICE_ID_5752) ||\
208 (bgep->chipid.device == DEVICE_ID_5752M) ||\
209 (bgep->chipid.device == DEVICE_ID_5789))
210
211 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \
212 (bgep->chipid.device == DEVICE_ID_5717) ||\
213 (bgep->chipid.device == DEVICE_ID_5718) ||\
214 (bgep->chipid.device == DEVICE_ID_5719) ||\
215 (bgep->chipid.device == DEVICE_ID_5720) ||\
216 (bgep->chipid.device == DEVICE_ID_5724)
217
218 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \
219 ((bgep->chipid.device == DEVICE_ID_5723) ||\
220 (bgep->chipid.device == DEVICE_ID_5761) ||\
221 (bgep->chipid.device == DEVICE_ID_5761E) ||\
222 (bgep->chipid.device == DEVICE_ID_5761S) ||\
223 (bgep->chipid.device == DEVICE_ID_5761SE) ||\
224 (bgep->chipid.device == DEVICE_ID_5764) ||\
225 (bgep->chipid.device == DEVICE_ID_5784M) ||\
226 (bgep->chipid.device == DEVICE_ID_5785) ||\
227 (bgep->chipid.device == DEVICE_ID_57760) ||\
228 (bgep->chipid.device == DEVICE_ID_57780) ||\
229 (bgep->chipid.device == DEVICE_ID_57788) ||\
230 (bgep->chipid.device == DEVICE_ID_57790))
231
232 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \
233 ((bgep->chipid.device == DEVICE_ID_5714C) ||\
234 (bgep->chipid.device == DEVICE_ID_5714S) ||\
235 (bgep->chipid.device == DEVICE_ID_5715C) ||\
236 (bgep->chipid.device == DEVICE_ID_5715S))
237
238 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \
239 ((bgep->chipid.device == DEVICE_ID_5906) ||\
240 (bgep->chipid.device == DEVICE_ID_5906M))
241
242
243 #define CHIP_TYPE_5705_PLUS (1 << 0)
244 #define CHIP_TYPE_5750_PLUS (1 << 1)
245 #define CHIP_TYPE_5780_CLASS (1 << 2)
246 #define CHIP_TYPE_5755_PLUS (1 << 3)
247 #define CHIP_TYPE_57765_CLASS (1 << 4)
248 #define CHIP_TYPE_57765_PLUS (1 << 5)
249 #define CHIP_TYPE_5717_PLUS (1 << 6)
250
251 #define DEVICE_IS_57765_PLUS(bgep) \
252 (bgep->chipid.chip_type & CHIP_TYPE_57765_PLUS)
253 #define DEVICE_IS_5755_PLUS(bgep) \
254 (bgep->chipid.chip_type & CHIP_TYPE_5755_PLUS)
255
256 /*
257 * Second section:
258 * Offsets of important registers & definitions for bits therein
259 */
260
261 /*
262 * PCI-X registers & bits
263 */
264 #define PCIX_CONF_COMM 0x42
265 #define PCIX_COMM_RELAXED 0x0002
266
267 /*
268 * Miscellaneous Host Control Register, in PCI config space
269 */
270 #define PCI_CONF_BGE_MHCR 0x68
271 #define MHCR_CHIP_REV_MASK 0xffff0000
272 #define MHCR_CHIP_REV_SHIFT 16
273 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
274 #define MHCR_MASK_INTERRUPT_MODE 0x00000100
275 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
276 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040
277 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020
278 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010
279 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008
280 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004
281 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
282 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001
283
284 #define MHCR_CHIP_REV_5703_A0 0x1000
285 #define MHCR_CHIP_REV_5704_A0 0x2000
286 #define MHCR_CHIP_REV_5751_A0 0x4000
287 #define MHCR_CHIP_REV_5721_A0 0x4100
288 #define MHCR_CHIP_REV_5755_A0 0xa000
289 #define MHCR_CHIP_REV_5755_A1 0xa001
290 #define MHCR_CHIP_REV_5719_A0 0x05719000
291 #define MHCR_CHIP_REV_5720_A0 0x05720000
292
293 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) >> 12)
294 #define MHCR_CHIP_ASIC_REV_5700 0x07
295 #define MHCR_CHIP_ASIC_REV_5701 0x00
296 #define MHCR_CHIP_ASIC_REV_5703 0x01
297 #define MHCR_CHIP_ASIC_REV_5704 0x02
298 #define MHCR_CHIP_ASIC_REV_5705 0x03
299 #define MHCR_CHIP_ASIC_REV_5750 0x04
300 #define MHCR_CHIP_ASIC_REV_5752 0x06
301 #define MHCR_CHIP_ASIC_REV_5780 0x08
302 #define MHCR_CHIP_ASIC_REV_5714 0x09
303 #define MHCR_CHIP_ASIC_REV_5755 0x0a
304 #define MHCR_CHIP_ASIC_REV_5787 0x0b
305 #define MHCR_CHIP_ASIC_REV_5906 0x0c
306 #define MHCR_CHIP_ASIC_REV_PRODID 0x0f
307 #define MHCR_CHIP_ASIC_REV_5784 0x5784
308 #define MHCR_CHIP_ASIC_REV_5761 0x5761
309 #define MHCR_CHIP_ASIC_REV_5785 0x5785
310 #define MHCR_CHIP_ASIC_REV_5717 0x5717
311 #define MHCR_CHIP_ASIC_REV_5719 0x5719
312 #define MHCR_CHIP_ASIC_REV_5720 0x5720
313 #define MHCR_CHIP_ASIC_REV_57780 0x57780
314 #define MHCR_CHIP_ASIC_REV_57765 0x57785
315 #define MHCR_CHIP_ASIC_REV_57766 0x57766
316
317 /*
318 * PCI DMA read/write Control Register, in PCI config space
319 *
320 * Note that several fields previously defined here have been deleted
321 * as they are not implemented in the 5703/4.
322 *
323 * Note: the value of this register is critical. It is possible to
324 * cause various unpleasant effects (DTOs, transaction deadlock, etc)
325 * by programming the wrong value. The value #defined below has been
326 * tested and shown to avoid all known problems. If it is to be changed,
327 * correct operation must be reverified on all supported platforms.
328 *
329 * In particular, we set both watermark fields to 2xCacheLineSize (128)
330 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
331 * with Tomatillo's internal pipelines, that otherwise result in stalls,
332 * repeated retries, and DTOs.
333 */
334 #define PCI_CONF_BGE_PDRWCR 0x6c
335 #define PDRWCR_RWCMD_MASK 0xFF000000
336 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000
337 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000
338 #define PDRWCR_READ_WATERMARK_MASK 0x00070000
339 #define PDRWCR_CONCURRENCY_MASK 0x0000c000
340 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000
341 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000
342 #define PDRWCR_MIN_BEAT_MASK 0x000000ff
343
344 /*
345 * These are the actual values to be put into the fields shown above
346 */
347 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */
348 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */
349 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */
350 #define PDRWCR_MIN_BEATS 0x00000000
351
352 #define PDRWCR_VAR_DEFAULT 0x761b0000
353 #define PDRWCR_VAR_5721 0x76180000
354 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */
355 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */
356 #define PDRWCR_VAR_5717 0x00380000
357
358 /*
359 * PCI State Register, in PCI config space
360 *
361 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
362 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
363 */
364 #define PCI_CONF_BGE_PCISTATE 0x70
365 #define PCISTATE_RETRY_SAME_DMA 0x00002000
366 #define PCISTATE_FLAT_VIEW 0x00000100
367 #define PCISTATE_EXT_ROM_RETRY 0x00000040
368 #define PCISTATE_EXT_ROM_ENABLE 0x00000020
369 #define PCISTATE_BUS_IS_32_BIT 0x00000010
370 #define PCISTATE_BUS_IS_FAST 0x00000008
371 #define PCISTATE_BUS_IS_PCI 0x00000004
372 #define PCISTATE_INTA_STATE 0x00000002
373 #define PCISTATE_FORCE_RESET 0x00000001
374
375 /*
376 * PCI Clock Control Register, in PCI config space
377 */
378 #define PCI_CONF_BGE_CLKCTL 0x74
379 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000
380 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000
381 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000
382 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000
383 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000
384 #define CLKCTL_PCIE_A0_FIX 0x00101000
385
386 /*
387 * Dual MAC Control Register, in PCI config space
388 */
389 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8
390 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */
391 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */
392
393 /*
394 * Register Indirect Access Address Register, 0x78 in PCI config
395 * space. Once this is set, accesses to the Register Indirect
396 * Access Data Register (0x80) refer to the register whose address
397 * is given by *this* register. This allows access to all the
398 * operating registers, while using only config space accesses.
399 *
400 * Note that the address written to the RIIAR should lie in one
401 * of the following ranges:
402 * 0x00000000 <= address < 0x00008000 (regular registers)
403 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
404 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
405 * 0x00038000 <= address < 0x00038800 (RxRISC ROM)
406 */
407 #define PCI_CONF_BGE_RIAAR 0x78
408 #define PCI_CONF_BGE_RIADR 0x80
409
410 #define RIAAR_REGISTER_MIN 0x00000000
411 #define RIAAR_REGISTER_MAX 0x00008000
412 #define RIAAR_RX_SCRATCH_MIN 0x00030000
413 #define RIAAR_RX_SCRATCH_MAX 0x00034000
414 #define RIAAR_TX_SCRATCH_MIN 0x00034000
415 #define RIAAR_TX_SCRATCH_MAX 0x00038000
416 #define RIAAR_RXROM_MIN 0x00038000
417 #define RIAAR_RXROM_MAX 0x00038800
418
419 /*
420 * Memory Window Base Address Register, 0x7c in PCI config space
421 * Once this is set, accesses to the Memory Window Data Access Register
422 * (0x84) refer to the word of NIC-local memory whose address is given
423 * by this register. When used in this way, the whole of the address
424 * written to this register is significant.
425 *
426 * This register also provides the 32K-aligned base address for a 32K
427 * region of NIC-local memory that the host can directly address in
428 * the upper 32K of the 64K of PCI memory space allocated to the chip.
429 * In this case, the bottom 15 bits of the register are ignored.
430 *
431 * Note that the address written to the MWBAR should lie in the range
432 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M
433 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
434 * memory were present, but it's only supported on the 5700, not the
435 * 5701/5703/5704.
436 */
437 #define PCI_CONF_BGE_MWBAR 0x7c
438 #define PCI_CONF_BGE_MWDAR 0x84
439 #define MWBAR_GRANULARITY 0x00008000 /* 32k */
440 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1)
441 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */
442
443 /*
444 * The PCI express device control register and device status register
445 * which are only applicable on BCM5751 and BCM5721.
446 */
447 #define PCI_CONF_DEV_CTRL 0xd8
448 #define PCI_CONF_DEV_CTRL_5723 0xd4
449 #define READ_REQ_SIZE_MAX 0x5000
450 #define DEV_CTRL_NO_SNOOP 0x0800
451 #define DEV_CTRL_RELAXED 0x0010
452
453 #define PCI_CONF_DEV_STUS 0xda
454 #define PCI_CONF_DEV_STUS_5723 0xd6
455 #define DEVICE_ERROR_STUS 0xf
456
457 #define PCI_CONF_PRODID_ASICREV 0x000000bc
458 #define PCI_CONF_GEN2_PRODID_ASICREV 0x000000f4
459 #define PCI_CONF_GEN15_PRODID_ASICREV 0x000000fc
460
461 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */
462
463 /*
464 * Where to find things in NIC-local (on-chip) memory
465 */
466 #define NIC_MEM_SEND_RINGS 0x0100
467 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring))
468 #define NIC_MEM_RECV_RINGS 0x0200
469 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring))
470 #define NIC_MEM_STATISTICS 0x0300
471 #define NIC_MEM_STATISTICS_SIZE 0x0800
472 #define NIC_MEM_STATUS_BLOCK 0x0b00
473 #define NIC_MEM_STATUS_SIZE 0x0050
474 #define NIC_MEM_GENCOMM 0x0b50
475
476
477 /*
478 * Note: the (non-bogus) values below are appropriate for systems
479 * without external memory. They would be different on a 5700 with
480 * external memory.
481 *
482 * Note: The higher send ring addresses and the mini ring shadow
483 * buffer address are dummies - systems without external memory
484 * are limited to 4 send rings and no mini receive ring.
485 */
486 #define NIC_MEM_SHADOW_DMA 0x2000
487 #define NIC_MEM_SHADOW_SEND_1_4 0x4000
488 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */
489 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */
490 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */
491 #define NIC_MEM_SHADOW_BUFF_STD 0x6000
492 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000
493 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000
494 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */
495 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots))
496
497 /*
498 * Put this in the GENCOMM port to tell the firmware not to run PXE
499 */
500 #define T3_MAGIC_NUMBER 0x4b657654u
501
502 /*
503 * The remaining registers appear in the low 32K of regular
504 * PCI Memory Address Space
505 */
506
507 /*
508 * All the state machine control registers below have at least a
509 * <RESET> bit and an <ENABLE> bit as defined below. Some also
510 * have an <ATTN_ENABLE> bit.
511 */
512 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004
513 #define STATE_MACHINE_ENABLE_BIT 0x00000002
514 #define STATE_MACHINE_RESET_BIT 0x00000001
515
516 #define TRANSMIT_MAC_MODE_REG 0x045c
517 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00
518 #define SEND_DATA_COMPLETION_MODE_REG 0x1000
519 #define SEND_BD_SELECTOR_MODE_REG 0x1400
520 #define SEND_BD_INITIATOR_MODE_REG 0x1800
521 #define SEND_BD_COMPLETION_MODE_REG 0x1c00
522
523 #define RECEIVE_MAC_MODE_REG 0x0468
524 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000
525 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400
526 #define RCV_DATA_COMPLETION_MODE_REG 0x2800
527 #define RCV_BD_INITIATOR_MODE_REG 0x2c00
528 #define RCV_BD_COMPLETION_MODE_REG 0x3000
529 #define RCV_LIST_SELECTOR_MODE_REG 0x3400
530
531 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800
532 #define HOST_COALESCE_MODE_REG 0x3c00
533 #define MEMORY_ARBITER_MODE_REG 0x4000
534 #define BUFFER_MANAGER_MODE_REG 0x4400
535 #define READ_DMA_MODE_REG 0x4800
536 #define READ_DMA_RESERVED_CONTROL_REG 0x4900
537 #define WRITE_DMA_MODE_REG 0x4c00
538 #define DMA_COMPLETION_MODE_REG 0x6400
539
540 /*
541 * Other bits in some of the above state machine control registers
542 */
543
544 /*
545 * Transmit MAC Mode Register
546 * (TRANSMIT_MAC_MODE_REG, 0x045c)
547 */
548 #define TRANSMIT_MODE_HTX2B_CNT_DN_MODE 0x00800000
549 #define TRANSMIT_MODE_HTX2B_JMB_FRM_LEN 0x00400000
550 #define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100
551 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040
552 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
553 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
554
555 /*
556 * Receive MAC Mode Register
557 * (RECEIVE_MAC_MODE_REG, 0x0468)
558 */
559 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400
560 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200
561 #define RECEIVE_MODE_PROMISCUOUS 0x00000100
562 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080
563 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040
564 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020
565 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010
566 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004
567
568 /*
569 * Receive BD Initiator Mode Register
570 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
571 *
572 * Each of these bits controls whether ATTN is asserted
573 * on a particular condition
574 */
575 #define RCV_BD_DISABLED_RING_ATTN 0x00000004
576
577 /*
578 * Receive Data & Receive BD Initiator Mode Register
579 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
580 *
581 * Each of these bits controls whether ATTN is asserted
582 * on a particular condition
583 */
584 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010
585 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008
586 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004
587
588 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c
589
590 /*
591 * Host Coalescing Mode Control Register
592 * (HOST_COALESCE_MODE_REG, 0x3c00)
593 */
594 #define COALESCE_64_BYTE_RINGS 12
595 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000
596 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800
597 #define COALESCE_CLR_TICKS_TX 0x00000400
598 #define COALESCE_CLR_TICKS_RX 0x00000200
599 #define COALESCE_32_BYTE_STATUS 0x00000100
600 #define COALESCE_64_BYTE_STATUS 0x00000080
601 #define COALESCE_NOW 0x00000008
602
603 /*
604 * Memory Arbiter Mode Register
605 * (MEMORY_ARBITER_MODE_REG, 0x4000)
606 */
607 #define MEMORY_ARBITER_ENABLE 0x00000002
608
609 /*
610 * Buffer Manager Mode Register
611 * (BUFFER_MANAGER_MODE_REG, 0x4400)
612 *
613 * In addition to the usual error-attn common to most state machines
614 * this register has a separate bit for attn on running-low-on-mbufs
615 */
616 #define BUFF_MGR_TEST_MODE 0x00000008
617 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
618 #define BUFF_MGR_NO_TX_UNDERRUN 0x80000000
619
620 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014
621
622 /*
623 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
624 * 0x4800, READ_DMA_RESERVED_CONTROL_REG, 0x4900,
625 * WRITE_DMA_MODE_REG, 0x4c00)
626 *
627 * These registers each contain a 2-bit priority field, which controls
628 * the relative priority of that type of DMA (read vs. write vs. MSI),
629 * and a set of bits that control whether ATTN is asserted on each
630 * particular condition
631 */
632 #define DMA_PRIORITY_MASK 0xc0000000
633 #define DMA_PRIORITY_SHIFT 30
634 #define ALL_DMA_ATTN_BITS 0x000003fc
635
636 #define RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
637 #define RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
638 #define RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
639 #define RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
640 #define RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
641 #define RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
642 #define RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
643
644
645 /*
646 * BCM5755, 5755M, 5906, 5906M only
647 * 1 - Enable Fix. Device will send out the status block before
648 * the interrupt message
649 * 0 - Disable fix. Device will send out the interrupt message
650 * before the status block
651 */
652 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000
653
654 /* 5720 only */
655 #define DMA_H2BNC_VLAN_DET 0x20000000
656
657
658 /*
659 * End of state machine control register definitions
660 */
661
662
663 /*
664 * High priority mailbox registers.
665 * Mailbox Registers (8 bytes each, but high half unused)
666 */
667 #define INTERRUPT_MBOX_0_REG 0x0200
668 #define INTERRUPT_MBOX_1_REG 0x0208
669 #define INTERRUPT_MBOX_2_REG 0x0210
670 #define INTERRUPT_MBOX_3_REG 0x0218
671 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n))
672
673 /*
674 * Low priority mailbox registers, for BCM5906, BCM5906M.
675 */
676 #define INTERRUPT_LP_MBOX_0_REG 0x5800
677
678 /*
679 * Ring Producer/Consumer Index (Mailbox) Registers
680 */
681 #define RECV_STD_PROD_INDEX_REG 0x0268
682 #define RECV_JUMBO_PROD_INDEX_REG 0x0270
683 #define RECV_MINI_PROD_INDEX_REG 0x0278
684 #define RECV_RING_CONS_INDEX_REGS 0x0280
685 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300
686 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380
687
688 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring))
689 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring))
690 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring))
691
692 /*
693 * Ethernet MAC Mode Register
694 */
695 #define ETHERNET_MAC_MODE_REG 0x0400
696 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000
697 #define ETHERNET_MODE_ENABLE_RDE 0x00400000
698 #define ETHERNET_MODE_ENABLE_TDE 0x00200000
699 #define ETHERNET_MODE_ENABLE_MIP 0x00100000
700 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000
701 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000
702 #define ETHERNET_MODE_SEND_CFGS 0x00020000
703 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000
704 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000
705 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000
706 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000
707 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000
708 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800
709 #define ETHERNET_MODE_LINK_POLARITY 0x00000400
710 #define ETHERNET_MODE_MAX_DEFER 0x00000200
711 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100
712 #define ETHERNET_MODE_TAGGED_MODE 0x00000080
713 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010
714 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c
715 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c
716 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008
717 #define ETHERNET_MODE_PORTMODE_MII 0x00000004
718 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000
719 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002
720 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001
721
722 /*
723 * Ethernet MAC Status & Event Registers
724 */
725 #define ETHERNET_MAC_STATUS_REG 0x0404
726 #define ETHERNET_STATUS_MI_INT 0x00800000
727 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000
728 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000
729 #define ETHERNET_STATUS_PCS_ERROR 0x00000400
730 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010
731 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008
732 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004
733 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002
734 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001
735
736 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408
737 #define ETHERNET_EVENT_MI_INT 0x00800000
738 #define ETHERNET_EVENT_LINK_INT 0x00001000
739 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400
740
741 /*
742 * Ethernet MAC LED Control Register
743 *
744 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and
745 * the external LED driver circuitry is wired up to assume that this mode
746 * will always be selected. Software must not change it!
747 */
748 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c
749 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000
750 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000
751 #define LED_CONTROL_LED_MODE_MASK 0x00001800
752 #define LED_CONTROL_LED_MODE_5700 0x00000000
753 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */
754 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000
755 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800
756 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400
757 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200
758 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100
759 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080
760 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040
761 #define LED_CONTROL_TRAFFIC_LED 0x00000020
762 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010
763 #define LED_CONTROL_10MBPS_LED 0x00000008
764 #define LED_CONTROL_100MBPS_LED 0x00000004
765 #define LED_CONTROL_1000MBPS_LED 0x00000002
766 #define LED_CONTROL_OVERRIDE_LINK 0x00000001
767 #define LED_CONTROL_DEFAULT 0x02000800
768
769 /*
770 * MAC Address registers
771 *
772 * These four eight-byte registers each hold one unicast address
773 * (six bytes), right justified & zero-filled on the left.
774 * They will normally all be set to the same value, as a station
775 * usually only has one h/w address. The value in register 0 is
776 * used for pause packets; any of the four can be specified for
777 * substitution into other transmitted packets if required.
778 */
779 #define MAC_ADDRESS_0_REG 0x0410
780 #define MAC_ADDRESS_1_REG 0x0418
781 #define MAC_ADDRESS_2_REG 0x0420
782 #define MAC_ADDRESS_3_REG 0x0428
783
784 #define MAC_ADDRESS_REG(n) (0x0410+8*(n))
785 #define MAC_ADDRESS_REGS_MAX 4
786
787 /*
788 * More MAC Registers ...
789 */
790 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438
791 #define MAC_RX_MTU_SIZE_REG 0x043c
792 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
793 #define MAC_TX_LENGTHS_REG 0x0464
794 #define MAC_TX_LENGTHS_DEFAULT 0x00002620
795 #define MAC_TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
796 #define MAC_TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
797
798 /*
799 * MII access registers
800 */
801 #define MI_COMMS_REG 0x044c
802 #define MI_COMMS_START 0x20000000
803 #define MI_COMMS_READ_FAILED 0x10000000
804 #define MI_COMMS_COMMAND_MASK 0x0c000000
805 #define MI_COMMS_COMMAND_READ 0x08000000
806 #define MI_COMMS_COMMAND_WRITE 0x04000000
807 #define MI_COMMS_ADDRESS_MASK 0x03e00000
808 #define MI_COMMS_ADDRESS_SHIFT 21
809 #define MI_COMMS_REGISTER_MASK 0x001f0000
810 #define MI_COMMS_REGISTER_SHIFT 16
811 #define MI_COMMS_DATA_MASK 0x0000ffff
812 #define MI_COMMS_DATA_SHIFT 0
813
814 #define MI_STATUS_REG 0x0450
815 #define MI_STATUS_10MBPS 0x00000002
816 #define MI_STATUS_LINK 0x00000001
817
818 #define MI_MODE_REG 0x0454
819 #define MI_MODE_CLOCK_MASK 0x001f0000
820 #define MI_MODE_AUTOPOLL 0x00000010
821 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002
822 #define MI_MODE_DEFAULT 0x000c0000
823
824 #define MI_AUTOPOLL_STATUS_REG 0x0458
825 #define MI_AUTOPOLL_ERROR 0x00000001
826
827 #define TRANSMIT_MAC_STATUS_REG 0x0460
828 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020
829 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010
830 #define TRANSMIT_STATUS_LINK_UP 0x00000008
831 #define TRANSMIT_STATUS_SENT_XON 0x00000004
832 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002
833 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001
834
835 #define RECEIVE_MAC_STATUS_REG 0x046c
836 #define RECEIVE_STATUS_RCVD_XON 0x00000004
837 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002
838 #define RECEIVE_STATUS_SENT_XOFF 0x00000001
839
840 /*
841 * These four-byte registers constitute a hash table for deciding
842 * whether to accept incoming multicast packets. The bits are
843 * numbered in big-endian fashion, from hash 0 => the MSB of
844 * register 0 to hash 127 => the LSB of the highest-numbered
845 * register.
846 *
847 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if
848 * enabled by setting the appropriate bit in the Rx MAC mode
849 * register. Otherwise, and on all earlier chips, the table
850 * is only 128 bits (registers 0-3).
851 */
852 #define MAC_HASH_0_REG 0x0470
853 #define MAC_HASH_1_REG 0x0474
854 #define MAC_HASH_2_REG 0x0478
855 #define MAC_HASH_3_REG 0x047c
856 #define MAC_HASH_4_REG 0x????
857 #define MAC_HASH_5_REG 0x????
858 #define MAC_HASH_6_REG 0x????
859 #define MAC_HASH_7_REG 0x????
860 #define MAC_HASH_REG(n) (0x470+4*(n))
861
862 /*
863 * Receive Rules Registers: 16 pairs of control+mask/value pairs
864 */
865 #define RCV_RULES_CONTROL_0_REG 0x0480
866 #define RCV_RULES_MASK_0_REG 0x0484
867 #define RCV_RULES_CONTROL_15_REG 0x04f8
868 #define RCV_RULES_MASK_15_REG 0x04fc
869 #define RCV_RULES_CONFIG_REG 0x0500
870 #define RCV_RULES_CONFIG_DEFAULT 0x00000008
871
872 #define RECV_RULES_NUM_MAX 16
873 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule))
874 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule))
875
876 #define RECV_RULE_CTL_ENABLE 0x80000000
877 #define RECV_RULE_CTL_AND 0x40000000
878 #define RECV_RULE_CTL_P1 0x20000000
879 #define RECV_RULE_CTL_P2 0x10000000
880 #define RECV_RULE_CTL_P3 0x08000000
881 #define RECV_RULE_CTL_MASK 0x04000000
882 #define RECV_RULE_CTL_DISCARD 0x02000000
883 #define RECV_RULE_CTL_MAP 0x01000000
884 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000
885 #define RECV_RULE_CTL_OP 0x00030000
886 #define RECV_RULE_CTL_OP_EQ 0x00000000
887 #define RECV_RULE_CTL_OP_NEQ 0x00010000
888 #define RECV_RULE_CTL_OP_GREAT 0x00020000
889 #define RECV_RULE_CTL_OP_LESS 0x00030000
890 #define RECV_RULE_CTL_HEADER 0x0000e000
891 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000
892 #define RECV_RULE_CTL_HEADER_IP 0x00002000
893 #define RECV_RULE_CTL_HEADER_TCP 0x00004000
894 #define RECV_RULE_CTL_HEADER_UDP 0x00006000
895 #define RECV_RULE_CTL_HEADER_DATA 0x00008000
896 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00
897 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \
898 RECV_RULE_CTL_CLASS_BITS)
899 #define RECV_RULE_CTL_OFFSET 0x000000ff
900
901 /*
902 * Receive Rules definition
903 */
904 #define ETHERHEADER_DEST_OFFSET 0x00
905 #define IPHEADER_PROTO_OFFSET 0x08
906 #define IPHEADER_SIP_OFFSET 0x0c
907 #define IPHEADER_DIP_OFFSET 0x10
908 #define TCPHEADER_SPORT_OFFSET 0x00
909 #define TCPHEADER_DPORT_OFFSET 0x02
910 #define UDPHEADER_SPORT_OFFSET 0x00
911 #define UDPHEADER_DPORT_OFFSET 0x02
912
913 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \
914 RECV_RULE_CTL_CLASS((ring)))
915
916 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK)
917
918 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \
919 RECV_RULE_CTL_HEADER_FRAME | \
920 ETHERHEADER_DEST_OFFSET)
921
922 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \
923 RECV_RULE_CTL_HEADER_FRAME | \
924 ETHERHEADER_DEST_OFFSET + 4)
925
926 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
927 IPHEADER_DIP_OFFSET)
928
929 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
930 IPHEADER_SIP_OFFSET)
931
932 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \
933 RECV_RULE_CTL_HEADER_IP | \
934 IPHEADER_PROTO_OFFSET)
935
936 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
937 RECV_RULE_CTL_HEADER_TCP | \
938 TCPHEADER_SPORT_OFFSET)
939
940 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
941 RECV_RULE_CTL_HEADER_TCP | \
942 TCPHEADER_DPORT_OFFSET)
943
944 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
945 RECV_RULE_CTL_HEADER_UDP | \
946 UDPHEADER_SPORT_OFFSET)
947
948 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
949 RECV_RULE_CTL_HEADER_UDP | \
950 UDPHEADER_DPORT_OFFSET)
951
952 /*
953 * 1000BaseX low-level access registers
954 */
955 #define MAC_GIGABIT_PCS_TEST_REG 0x0440
956 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000
957 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff
958 #define TX_1000BASEX_AUTONEG_REG 0x0444
959 #define RX_1000BASEX_AUTONEG_REG 0x0448
960
961 /*
962 * Autoneg code bits for the 1000BASE-X AUTONEG registers
963 */
964 #define AUTONEG_CODE_PAUSE 0x00008000
965 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000
966 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000
967 #define AUTONEG_CODE_NEXT_PAGE 0x00000080
968 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040
969 #define AUTONEG_CODE_FAULT_MASK 0x00000030
970 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030
971 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020
972 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010
973 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001
974
975 /*
976 * SerDes Registers (5703S/5704S only)
977 */
978 #define SERDES_CONTROL_REG 0x0590
979 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000
980 #define SERDES_CONTROL_COMMA_DETECT 0x00010000
981 #define SERDES_CONTROL_TX_DISABLE 0x00004000
982 #define SERDES_STATUS_REG 0x0594
983 #define SERDES_STATUS_COMMA_DETECTED 0x00000100
984 #define SERDES_STATUS_RXSTAT 0x000000ff
985
986 /*
987 * SGMII Status Register (5717/5718 only)
988 */
989 #define SGMII_STATUS_REG 0x5B4
990 #define MEDIA_SELECTION_MODE 0x00000100
991
992 /*
993 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only)
994 */
995 #define STAT_IFHCOUT_OCTETS_REG 0x0800
996 #define STAT_ETHER_COLLIS_REG 0x0808
997 #define STAT_OUTXON_SENT_REG 0x080c
998 #define STAT_OUTXOFF_SENT_REG 0x0810
999 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818
1000 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c
1001 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820
1002 #define STAT_DOT3_DEFERED_TX_REG 0x0824
1003 #define STAT_DOT3_EXCE_COLLI_REG 0x082c
1004 #define STAT_DOT3_LATE_COLLI_REG 0x0830
1005 #define STAT_IFHCOUT_UPKGS_REG 0x086c
1006 #define STAT_IFHCOUT_MPKGS_REG 0x0870
1007 #define STAT_IFHCOUT_BPKGS_REG 0x0874
1008
1009 #define STAT_IFHCIN_OCTETS_REG 0x0880
1010 #define STAT_ETHER_FRAGMENT_REG 0x0888
1011 #define STAT_IFHCIN_UPKGS_REG 0x088c
1012 #define STAT_IFHCIN_MPKGS_REG 0x0890
1013 #define STAT_IFHCIN_BPKGS_REG 0x0894
1014
1015 #define STAT_DOT3_FCS_ERR_REG 0x0898
1016 #define STAT_DOT3_ALIGN_ERR_REG 0x089c
1017 #define STAT_XON_PAUSE_RX_REG 0x08a0
1018 #define STAT_XOFF_PAUSE_RX_REG 0x08a4
1019 #define STAT_MAC_CTRL_RX_REG 0x08a8
1020 #define STAT_XOFF_STATE_ENTER_REG 0x08ac
1021 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0
1022 #define STAT_ETHER_JABBERS_REG 0x08b4
1023 #define STAT_ETHER_UNDERSIZE_REG 0x08b8
1024 #define SIZE_OF_STATISTIC_REG 0x1B
1025 /*
1026 * Send Data Initiator Registers
1027 */
1028 #define SEND_INIT_STATS_CONTROL_REG 0x0c08
1029 #define SEND_INIT_STATS_ZERO 0x00000010
1030 #define SEND_INIT_STATS_FLUSH 0x00000008
1031 #define SEND_INIT_STATS_CLEAR 0x00000004
1032 #define SEND_INIT_STATS_FASTER 0x00000002
1033 #define SEND_INIT_STATS_ENABLE 0x00000001
1034
1035 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c
1036
1037 /*
1038 * Send Buffer Descriptor Selector Control Registers
1039 */
1040 #define SEND_BD_SELECTOR_STATUS_REG 0x1404
1041 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408
1042 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n))
1043
1044 /*
1045 * Receive List Placement Registers
1046 */
1047 #define RCV_LP_CONFIG_REG 0x2010
1048 #define RCV_LP_CONFIG_DEFAULT 0x00000009
1049 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1)
1050
1051 #define RCV_LP_STATS_CONTROL_REG 0x2014
1052 #define RCV_LP_STATS_ZERO 0x00000010
1053 #define RCV_LP_STATS_FLUSH 0x00000008
1054 #define RCV_LP_STATS_CLEAR 0x00000004
1055 #define RCV_LP_STATS_FASTER 0x00000002
1056 #define RCV_LP_STATS_ENABLE 0x00000001
1057
1058 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018
1059 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000
1060
1061 /*
1062 * Receive Data & BD Initiator Registers
1063 */
1064 #define RCV_INITIATOR_STATUS_REG 0x2404
1065
1066 /*
1067 * Receive Buffer Descriptor Ring Control Block Registers
1068 * NB: sixteen bytes (128 bits) each
1069 */
1070 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440
1071 #define STD_RCV_BD_RING_RCB_REG 0x2450
1072 #define MINI_RCV_BD_RING_RCB_REG 0x2460
1073
1074 /*
1075 * Receive Buffer Descriptor Ring Replenish Threshold Registers
1076 */
1077 #define MINI_RCV_BD_REPLENISH_REG 0x2c14
1078 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */
1079 #define STD_RCV_BD_REPLENISH_REG 0x2c18
1080 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */
1081 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c
1082 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */
1083
1084 /*
1085 * CPMU registers (5717/5718/5719/5720 only)
1086 */
1087 #define CPMU_CLCK_ORIDE_REG 0x3624
1088 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1089
1090 #define CPMU_STATUS_REG 0x362c
1091 #define CPMU_STATUS_FUN_NUM_5717 0x20000000
1092 #define CPMU_STATUS_FUN_NUM_5719 0xc0000000
1093 #define CPMU_STATUS_FUN_NUM_5719_SHIFT 30
1094
1095
1096 /*
1097 * Host Coalescing Engine Control Registers
1098 */
1099 #define RCV_COALESCE_TICKS_REG 0x3c08
1100 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1101 #define SEND_COALESCE_TICKS_REG 0x3c0c
1102 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1103 #define RCV_COALESCE_MAX_BD_REG 0x3c10
1104 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1105 #define SEND_COALESCE_MAX_BD_REG 0x3c14
1106 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1107 #define RCV_COALESCE_INT_TICKS_REG 0x3c18
1108 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1109 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c
1110 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1111 #define RCV_COALESCE_INT_BD_REG 0x3c20
1112 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1113 #define SEND_COALESCE_INT_BD_REG 0x3c24
1114 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1115 #define STATISTICS_TICKS_REG 0x3c28
1116 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */
1117 #define STATISTICS_HOST_ADDR_REG 0x3c30
1118 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38
1119 #define STATISTICS_BASE_ADDR_REG 0x3c40
1120 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44
1121 #define FLOW_ATTN_REG 0x3c48
1122
1123 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50
1124 #define NIC_STD_RECV_INDEX_REG 0x3c54
1125 #define NIC_MINI_RECV_INDEX_REG 0x3c58
1126 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n))
1127 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n))
1128
1129 /*
1130 * Mbuf Pool Initialisation & Watermark Registers
1131 *
1132 * There are some conflicts in the PRM; compare the recommendations
1133 * on pp. 115, 236, and 339. The values here were recommended by
1134 * dkim@broadcom.com (and the PRM should be corrected soon ;-)
1135 */
1136 #define BUFFER_MANAGER_STATUS_REG 0x4404
1137 #define MBUF_POOL_BASE_REG 0x4408
1138 #define MBUF_POOL_BASE_DEFAULT 0x00008000
1139 #define MBUF_POOL_BASE_5721 0x00010000
1140 #define MBUF_POOL_BASE_5704 0x00010000
1141 #define MBUF_POOL_BASE_5705 0x00010000
1142 #define MBUF_POOL_LENGTH_REG 0x440c
1143 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000
1144 #define MBUF_POOL_LENGTH_5704 0x00010000
1145 #define MBUF_POOL_LENGTH_5705 0x00008000
1146 #define MBUF_POOL_LENGTH_5721 0x00008000
1147 #define RDMA_MBUF_LOWAT_REG 0x4410
1148 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050
1149 #define RDMA_MBUF_LOWAT_5705 0x00000000
1150 #define RDMA_MBUF_LOWAT_5906 0x00000000
1151 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130
1152 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000
1153 #define MAC_RX_MBUF_LOWAT_REG 0x4414
1154 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020
1155 #define MAC_RX_MBUF_LOWAT_5705 0x00000010
1156 #define MAC_RX_MBUF_LOWAT_5906 0x00000004
1157 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a
1158 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098
1159 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b
1160 #define MBUF_HIWAT_REG 0x4418
1161 #define MBUF_HIWAT_DEFAULT 0x00000060
1162 #define MBUF_HIWAT_5705 0x00000060
1163 #define MBUF_HIWAT_5906 0x00000010
1164 #define MBUF_HIWAT_5717 0x000000a0
1165 #define MBUF_HIWAT_JUMBO 0x0000017c
1166 #define MBUF_HIWAT_5714_JUMBO 0x00000096
1167
1168 /*
1169 * DMA Descriptor Pool Initialisation & Watermark Registers
1170 */
1171 #define DMAD_POOL_BASE_REG 0x442c
1172 #define DMAD_POOL_BASE_DEFAULT 0x00002000
1173 #define DMAD_POOL_LENGTH_REG 0x4430
1174 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000
1175 #define DMAD_POOL_LOWAT_REG 0x4434
1176 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */
1177 #define DMAD_POOL_HIWAT_REG 0x4438
1178 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */
1179
1180 /*
1181 * More threshold/watermark registers ...
1182 */
1183 #define RECV_FLOW_THRESHOLD_REG 0x4458
1184 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504
1185 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002
1186
1187 /*
1188 * Read/Write DMA Status Registers
1189 */
1190 #define READ_DMA_STATUS_REG 0x4804
1191 #define WRITE_DMA_STATUS_REG 0x4c04
1192
1193 /*
1194 * RX/TX RISC Registers
1195 */
1196 #define RX_RISC_MODE_REG 0x5000
1197 #define RX_RISC_STATE_REG 0x5004
1198 #define RX_RISC_PC_REG 0x501c
1199 #define TX_RISC_MODE_REG 0x5400
1200 #define TX_RISC_STATE_REG 0x5404
1201 #define TX_RISC_PC_REG 0x541c
1202
1203 /*
1204 * V? RISC Registerss
1205 */
1206 #define VCPU_STATUS_REG 0x5100
1207 #define VCPU_INIT_DONE 0x04000000
1208 #define VCPU_DRV_RESET 0x08000000
1209
1210 #define VCPU_EXT_CTL 0x6890
1211 #define VCPU_EXT_CTL_HALF 0x00400000
1212
1213 #define GRC_FASTBOOT_PC 0x6894
1214
1215 #define FTQ_RESET_REG 0x5c00
1216
1217 #define MSI_MODE_REG 0x6000
1218 #define MSI_PRI_HIGHEST 0xc0000000
1219 #define MSI_MSI_ENABLE 0x00000002
1220 #define MSI_ERROR_ATTENTION 0x0000001c
1221
1222 #define MSI_STATUS_REG 0x6004
1223
1224 #define MODE_CONTROL_REG 0x6800
1225 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000
1226 #define MODE_4X_NIC_SEND_RINGS 0x20000000
1227 #define MODE_INT_ON_FLOW_ATTN 0x10000000
1228 #define MODE_INT_ON_DMA_ATTN 0x08000000
1229 #define MODE_INT_ON_MAC_ATTN 0x04000000
1230 #define MODE_INT_ON_RXRISC_ATTN 0x02000000
1231 #define MODE_INT_ON_TXRISC_ATTN 0x01000000
1232 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
1233 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
1234 #define MODE_HTX2B_ENABLE 0x00040000
1235 #define MODE_HOST_SEND_BDS 0x00020000
1236 #define MODE_HOST_STACK_UP 0x00010000
1237 #define MODE_FORCE_32_BIT_PCI 0x00008000
1238 #define MODE_B2HRX_ENABLE 0x00008000
1239 #define MODE_NO_INT_ON_RECV 0x00004000
1240 #define MODE_NO_INT_ON_SEND 0x00002000
1241 #define MODE_ALLOW_BAD_FRAMES 0x00000800
1242 #define MODE_NO_CRC 0x00000400
1243 #define MODE_NO_FRAME_CRACKING 0x00000200
1244 #define MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1245 #define MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1246 #define MODE_WORD_SWAP_FRAME 0x00000020
1247 #define MODE_BYTE_SWAP_FRAME 0x00000010
1248 #define MODE_WORD_SWAP_NONFRAME 0x00000004
1249 #define MODE_BYTE_SWAP_NONFRAME 0x00000002
1250 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001
1251
1252 /*
1253 * Miscellaneous Configuration Register
1254 *
1255 * This contains various bits relating to power control (which differ
1256 * among different members of the chip family), but the important bits
1257 * for our purposes are the RESET bit and the Timer Prescaler field.
1258 *
1259 * The RESET bit in this register serves to reset the whole chip, even
1260 * including the PCI interface(!) Once it's set, the chip will not
1261 * respond to ANY accesses -- not even CONFIG space -- until the reset
1262 * completes internally. According to the PRM, this should take less
1263 * than 100us. Any access during this period will get a bus error.
1264 *
1265 * The Timer Prescaler field must be programmed so that the timer period
1266 * is as near as possible to 1us. The value in this field should be
1267 * the Core Clock frequency in MHz minus 1. From my reading of the PRM,
1268 * the Core Clock should always be 66MHz (independently of the bus speed,
1269 * at least for PCI rather than PCI-X), so this register must be set to
1270 * the value 0x82 ((66-1) << 1).
1271 */
1272 #define CORE_CLOCK_MHZ 66
1273 #define MISC_CONFIG_REG 0x6804
1274 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
1275 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
1276 #define MISC_CONFIG_POWERDOWN 0x00100000
1277 #define MISC_CONFIG_POWER_STATE 0x00060000
1278 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe
1279 #define MISC_CONFIG_RESET_BIT 0x00000001
1280 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1)
1281 #define MISC_CONFIG_EPHY_IDDQ 0x00200000
1282
1283 /*
1284 * Miscellaneous Local Control Register (MLCR)
1285 */
1286 #define MISC_LOCAL_CONTROL_REG 0x6808
1287 #define MLCR_PCI_CTRL_SELECT 0x10000000
1288 #define MLCR_LEGACY_PCI_MODE 0x08000000
1289 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000
1290 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000
1291 #define MLCR_SSRAM_TYPE 0x00400000
1292 #define MLCR_BANK_SELECT 0x00200000
1293 #define MLCR_SRAM_SIZE_MASK 0x001c0000
1294 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000
1295
1296 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000
1297 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000
1298 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000
1299 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000
1300 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000
1301 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800
1302 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */
1303 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */
1304 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */
1305
1306 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */
1307 #define MLCR_SET_INT 0x00000004 /* W/O */
1308 #define MLCR_CLR_INT 0x00000002 /* W/O */
1309 #define MLCR_INTA_STATE 0x00000001 /* R/O */
1310
1311 /*
1312 * This value defines all GPIO bits as INPUTS, but sets their default
1313 * values as outputs to HIGH, on the assumption that external circuits
1314 * (if any) will probably be active-LOW with passive pullups.
1315 *
1316 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in
1317 * just this fashion. It has to be set as an OUTPUT and driven LOW to
1318 * enable writing. Otherwise, the SEEPROM is protected.
1319 */
1320 #define MLCR_DEFAULT 0x0101c000
1321 #define MLCR_DEFAULT_5714 0x1901c000
1322 #define MLCR_DEFAULT_5717 0x01000000
1323
1324 /*
1325 * Serial EEPROM Data/Address Registers (auto-access mode)
1326 */
1327 #define SERIAL_EEPROM_DATA_REG 0x683c
1328 #define SERIAL_EEPROM_ADDRESS_REG 0x6838
1329 #define SEEPROM_ACCESS_READ 0x80000000
1330 #define SEEPROM_ACCESS_WRITE 0x00000000
1331 #define SEEPROM_ACCESS_COMPLETE 0x40000000
1332 #define SEEPROM_ACCESS_RESET 0x20000000
1333 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000
1334 #define SEEPROM_ACCESS_START 0x02000000
1335 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000
1336 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc
1337
1338 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */
1339 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */
1340 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */
1341
1342 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */
1343 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */
1344
1345 /*
1346 * "Linearised" address mask, treating multiple devices as consecutive
1347 */
1348 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */
1349
1350 /*
1351 * Non-Volatile Memory Interface Registers
1352 * Note: on chips that support the flash interface (5702+), flash is the
1353 * default and the legacy seeprom interface must be explicitly enabled
1354 * if required. On older chips (5700/01), SEEPROM is the default (and
1355 * only) non-volatile memory available, and these registers don't exist!
1356 */
1357 #define NVM_FLASH_CMD_REG 0x7000
1358 #define NVM_FLASH_CMD_LAST 0x00000100
1359 #define NVM_FLASH_CMD_FIRST 0x00000080
1360 #define NVM_FLASH_CMD_RD 0x00000000
1361 #define NVM_FLASH_CMD_WR 0x00000020
1362 #define NVM_FLASH_CMD_DOIT 0x00000010
1363 #define NVM_FLASH_CMD_DONE 0x00000008
1364
1365 #define NVM_FLASH_WRITE_REG 0x7008
1366 #define NVM_FLASH_READ_REG 0x7010
1367
1368 #define NVM_FLASH_ADDR_REG 0x700c
1369 #define NVM_FLASH_ADDR_MASK 0x00fffffc
1370
1371 #define NVM_CONFIG1_REG 0x7014
1372 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000
1373 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800
1374 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780
1375 #define NVM_CFG1_BUFFERED_MODE 0x00000002
1376 #define NVM_CFG1_FLASH_MODE 0x00000001
1377
1378 #define NVM_SW_ARBITRATION_REG 0x7020
1379 #define NVM_READ_REQ3 0X00008000
1380 #define NVM_READ_REQ2 0X00004000
1381 #define NVM_READ_REQ1 0X00002000
1382 #define NVM_READ_REQ0 0X00001000
1383 #define NVM_WON_REQ3 0X00000800
1384 #define NVM_WON_REQ2 0X00000400
1385 #define NVM_WON_REQ1 0X00000200
1386 #define NVM_WON_REQ0 0X00000100
1387 #define NVM_RESET_REQ3 0X00000080
1388 #define NVM_RESET_REQ2 0X00000040
1389 #define NVM_RESET_REQ1 0X00000020
1390 #define NVM_RESET_REQ0 0X00000010
1391 #define NVM_SET_REQ3 0X00000008
1392 #define NVM_SET_REQ2 0X00000004
1393 #define NVM_SET_REQ1 0X00000002
1394 #define NVM_SET_REQ0 0X00000001
1395
1396 /*
1397 * NVM access register
1398 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
1399 * and BCM5715 only.
1400 */
1401 #define NVM_ACCESS_REG 0X7024
1402 #define NVM_WRITE_ENABLE 0X00000002
1403 #define NVM_ACCESS_ENABLE 0X00000001
1404
1405 /*
1406 * TLP Control Register
1407 * Applicable to BCM5721 and BCM5751 only
1408 */
1409 #define TLP_CONTROL_REG 0x7c00
1410 #define TLP_DATA_FIFO_PROTECT 0x02000000
1411
1412 /*
1413 * PHY Test Control Register
1414 * Applicable to BCM5721 and BCM5751 only
1415 */
1416 #define PHY_TEST_CTRL_REG 0x7e2c
1417 #define PHY_PCIE_SCRAM_MODE 0x20
1418 #define PHY_PCIE_LTASS_MODE 0x40
1419
1420 /*
1421 * The internal firmware expects a certain layout of the non-volatile
1422 * memory (if fitted), and will check for it during startup, and use the
1423 * contents to initialise various internal parameters if it looks good.
1424 *
1425 * The offsets and field definitions below refer to where to find some
1426 * important values, and how to interpret them ...
1427 */
1428 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */
1429 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */
1430
1431 /*
1432 * Vendor-specific MII registers
1433 */
1434 #define MII_EXT_CONTROL MII_VENDOR(0)
1435 #define MII_EXT_STATUS MII_VENDOR(1)
1436 #define MII_RCV_ERR_COUNT MII_VENDOR(2)
1437 #define MII_FALSE_CARR_COUNT MII_VENDOR(3)
1438 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4)
1439 #define MII_AUX_CONTROL MII_VENDOR(8)
1440 #define MII_AUX_STATUS MII_VENDOR(9)
1441 #define MII_INTR_STATUS MII_VENDOR(10)
1442 #define MII_INTR_MASK MII_VENDOR(11)
1443 #define MII_HCD_STATUS MII_VENDOR(13)
1444
1445 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */
1446
1447 /*
1448 * Bits in the MII_EXT_CONTROL register
1449 */
1450 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000
1451 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000
1452 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000
1453 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000
1454 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800
1455 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400
1456 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200
1457 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100
1458 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080
1459 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040
1460 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020
1461 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010
1462 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008
1463 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004
1464 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002
1465 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001
1466
1467 /*
1468 * Bits in the MII_EXT_STATUS register
1469 */
1470 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000
1471 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000
1472 #define MII_EXT_STAT_MDIX_STATE 0x2000
1473 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000
1474 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800
1475 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400
1476 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200
1477 #define MII_EXT_STAT_LINK_STATUS 0x0100
1478 #define MII_EXT_STAT_CRC_ERROR 0x0080
1479 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040
1480 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020
1481 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010
1482 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008
1483 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004
1484 #define MII_EXT_STAT_LOCK_ERROR 0x0002
1485 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001
1486
1487 /*
1488 * The AUX CONTROL register is seriously weird!
1489 *
1490 * It hides (up to) eight 'shadow' registers. When writing, which one
1491 * of them is written is determined by the low-order bits of the data
1492 * written(!), but when reading, which one is read is determined by the
1493 * value previously written to (part of) one of the shadow registers!!!
1494 */
1495
1496 /*
1497 * Shadow register numbers
1498 */
1499 #define MII_AUX_CTRL_NORMAL 0
1500 #define MII_AUX_CTRL_10BASE_T 1
1501 #define MII_AUX_CTRL_POWER 2
1502 #define MII_AUX_CTRL_TEST_1 4
1503 #define MII_AUX_CTRL_MISC 7
1504
1505 /*
1506 * Selected bits in some of the shadow registers ...
1507 */
1508 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000
1509 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000
1510 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000
1511 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400
1512 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008
1513
1514 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008
1515
1516 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000
1517 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010
1518
1519 /*
1520 * Write this value to the AUX control register
1521 * to select which shadow register will be read
1522 */
1523 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC)
1524
1525 /*
1526 * Bits in the MII_AUX_STATUS register
1527 */
1528 #define MII_AUX_STATUS_MODE_MASK 0x0700
1529 #define MII_AUX_STATUS_MODE_1000_F 0x0700
1530 #define MII_AUX_STATUS_MODE_1000_H 0x0600
1531 #define MII_AUX_STATUS_MODE_100_F 0x0500
1532 #define MII_AUX_STATUS_MODE_100_4 0x0400
1533 #define MII_AUX_STATUS_MODE_100_H 0x0300
1534 #define MII_AUX_STATUS_MODE_10_F 0x0200
1535 #define MII_AUX_STATUS_MODE_10_H 0x0100
1536 #define MII_AUX_STATUS_MODE_NONE 0x0000
1537 #define MII_AUX_STATUS_MODE_SHIFT 8
1538
1539 #define MII_AUX_STATUS_PAR_FAULT 0x0080
1540 #define MII_AUX_STATUS_REM_FAULT 0x0040
1541 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010
1542 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008
1543
1544 #define MII_AUX_STATUS_LINKUP 0x0004
1545 #define MII_AUX_STATUS_RX_PAUSE 0x0002
1546 #define MII_AUX_STATUS_TX_PAUSE 0x0001
1547
1548 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008
1549 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002
1550 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001
1551
1552 /*
1553 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers
1554 */
1555 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020
1556 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010
1557 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008
1558 #define MII_INTR_LINK_SPEED_CHANGE 0x0004
1559 #define MII_INTR_LINK_STATUS_CHANGE 0x0002
1560
1561
1562 /*
1563 * Third section:
1564 * Hardware-defined data structures
1565 *
1566 * Note that the chip is naturally BIG-endian, so, for a big-endian
1567 * host, the structures defined below match those described in the PRM.
1568 * For little-endian hosts, some structures have to be swapped around.
1569 */
1570
1571 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
1572 #error Host endianness not defined
1573 #endif
1574
1575 /*
1576 * Architectural constants: absolute maximum numbers of each type of ring
1577 */
1578 #ifdef BGE_EXT_MEM
1579 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */
1580 #else
1581 #define BGE_SEND_RINGS_MAX 4
1582 #endif
1583 #define BGE_SEND_RINGS_MAX_5705 1
1584 #define BGE_RECV_RINGS_MAX 16
1585 #define BGE_RECV_RINGS_MAX_5705 1
1586 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */
1587 /* only with ext mem) */
1588
1589 #define BGE_SEND_SLOTS_MAX 512
1590 #define BGE_STD_SLOTS_MAX 512
1591 #define BGE_JUMBO_SLOTS_MAX 256
1592 #define BGE_MINI_SLOTS_MAX 1024
1593 #define BGE_RECV_SLOTS_MAX 2048
1594 #define BGE_RECV_SLOTS_5705 512
1595 #define BGE_RECV_SLOTS_5717 1024
1596 #define BGE_RECV_SLOTS_5782 512
1597 #define BGE_RECV_SLOTS_5721 512
1598
1599 /*
1600 * Hardware-defined Ring Control Block
1601 */
1602 typedef struct {
1603 uint64_t host_ring_addr;
1604 #ifdef _BIG_ENDIAN
1605 uint16_t max_len;
1606 uint16_t flags;
1607 uint32_t nic_ring_addr;
1608 #else
1609 uint32_t nic_ring_addr;
1610 uint16_t flags;
1611 uint16_t max_len;
1612 #endif /* _BIG_ENDIAN */
1613 } bge_rcb_t;
1614
1615 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001
1616 #define RCB_FLAG_RING_DISABLED 0x0002
1617
1618 /*
1619 * Hardware-defined Send Buffer Descriptor
1620 */
1621 typedef struct {
1622 uint64_t host_buf_addr;
1623 #ifdef _BIG_ENDIAN
1624 uint16_t len;
1625 uint16_t flags;
1626 uint16_t reserved;
1627 uint16_t vlan_tci;
1628 #else
1629 uint16_t vlan_tci;
1630 uint16_t reserved;
1631 uint16_t flags;
1632 uint16_t len;
1633 #endif /* _BIG_ENDIAN */
1634 } bge_sbd_t;
1635
1636 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001
1637 #define SBD_FLAG_IP_CKSUM 0x0002
1638 #define SBD_FLAG_PACKET_END 0x0004
1639 #define SBD_FLAG_IP_FRAG 0x0008
1640 #define SBD_FLAG_IP_FRAG_END 0x0010
1641
1642 #define SBD_FLAG_VLAN_TAG 0x0040
1643 #define SBD_FLAG_COAL_NOW 0x0080
1644 #define SBD_FLAG_CPU_PRE_DMA 0x0100
1645 #define SBD_FLAG_CPU_POST_DMA 0x0200
1646
1647 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000
1648 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000
1649 #define SBD_FLAG_DONT_GEN_CRC 0x8000
1650
1651 /*
1652 * Hardware-defined Receive Buffer Descriptor
1653 */
1654 typedef struct {
1655 uint64_t host_buf_addr;
1656 #ifdef _BIG_ENDIAN
1657 uint16_t index;
1658 uint16_t len;
1659 uint16_t type;
1660 uint16_t flags;
1661 uint16_t ip_cksum;
1662 uint16_t tcp_udp_cksum;
1663 uint16_t error_flag;
1664 uint16_t vlan_tci;
1665 uint32_t reserved;
1666 uint32_t opaque;
1667 #else
1668 uint16_t flags;
1669 uint16_t type;
1670 uint16_t len;
1671 uint16_t index;
1672 uint16_t vlan_tci;
1673 uint16_t error_flag;
1674 uint16_t tcp_udp_cksum;
1675 uint16_t ip_cksum;
1676 uint32_t opaque;
1677 uint32_t reserved;
1678 #endif /* _BIG_ENDIAN */
1679 } bge_rbd_t;
1680
1681 #define RBD_FLAG_STD_RING 0x0000
1682 #define RBD_FLAG_PACKET_END 0x0004
1683
1684 #define RBD_FLAG_JUMBO_RING 0x0020
1685 #define RBD_FLAG_VLAN_TAG 0x0040
1686
1687 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400
1688 #define RBD_FLAG_MINI_RING 0x0800
1689 #define RBD_FLAG_IP_CHECKSUM 0x1000
1690 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000
1691 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000
1692
1693 #define RBD_FLAG_DEFAULT 0x0000
1694
1695 #define RBD_ERROR_BAD_CRC 0x00010000
1696 #define RBD_ERROR_COLL_DETECT 0x00020000
1697 #define RBD_ERROR_LINK_LOST 0x00040000
1698 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000
1699 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000
1700 #define RBD_ERROR_MAC_ABORT 0x00200000
1701 #define RBD_ERROR_LEN_LESS_64 0x00400000
1702 #define RBD_ERROR_TRUNC_NO_RES 0x00800000
1703 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000
1704
1705 /*
1706 * Hardware-defined Status Block,Size of status block
1707 * is actually 0x50 bytes.Use 0x80 bytes for cache line
1708 * alignment.For BCM5705/5788/5721/5751/5752/5714
1709 * and 5715,there is only 1 recv and send ring index,but
1710 * driver defined 16 indexs here,please pay attention only
1711 * one ring is enabled in these chipsets.
1712 */
1713 typedef struct {
1714 uint64_t flags_n_tag;
1715 uint16_t buff_cons_index[4];
1716 struct {
1717 #ifdef _BIG_ENDIAN
1718 uint16_t send_cons_index;
1719 uint16_t recv_prod_index;
1720 #else
1721 uint16_t recv_prod_index;
1722 uint16_t send_cons_index;
1723 #endif /* _BIG_ENDIAN */
1724 } index[16];
1725 } bge_status_t;
1726
1727 /*
1728 * Hardware-defined Receive BD Rule
1729 */
1730 typedef struct {
1731 uint32_t control;
1732 uint32_t mask_value;
1733 } bge_recv_rule_t;
1734
1735 /*
1736 * This describes which sub-rule slots are used by a particular rule.
1737 */
1738 typedef struct {
1739 int start;
1740 int count;
1741 } bge_rule_info_t;
1742
1743 /*
1744 * Indexes into the <buff_cons_index> array
1745 */
1746 #ifdef _BIG_ENDIAN
1747 #define STATUS_STD_BUFF_CONS_INDEX 0
1748 #define STATUS_JUMBO_BUFF_CONS_INDEX 1
1749 #define STATUS_MINI_BUFF_CONS_INDEX 3
1750 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index)
1751 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index)
1752 #else
1753 #define STATUS_STD_BUFF_CONS_INDEX 3
1754 #define STATUS_JUMBO_BUFF_CONS_INDEX 2
1755 #define STATUS_MINI_BUFF_CONS_INDEX 0
1756 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index)
1757 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index)
1758 #endif /* _BIG_ENDIAN */
1759
1760 /*
1761 * Bits in the <flags_n_tag> word
1762 */
1763 #define STATUS_FLAG_UPDATED 0x0000000100000000ull
1764 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull
1765 #define STATUS_FLAG_ERROR 0x0000000400000000ull
1766 #define STATUS_TAG_MASK 0x00000000000000FFull
1767
1768 /*
1769 * The tag from the status block is fed back to Interrupt Mailbox 0
1770 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This
1771 * lets the chip know what updates have been processed, so it can
1772 * reassert its interrupt if more updates have occurred since.
1773 *
1774 * These macros extract the tag from the <flags_n_tag> word, shift
1775 * it to the proper position in the Mailbox register, and provide
1776 * the complete values to write to INTERRUPT_MBOX_0_REG to disable
1777 * or enable interrupts
1778 */
1779 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK)
1780 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24)
1781 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1)
1782 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0)
1783
1784 /*
1785 * Hardware-defined Statistics Block Offsets
1786 *
1787 * These are given in the manual as addresses in NIC memory, starting
1788 * from the NIC statistics area base address of 0x300; but here we
1789 * convert them into indexes into an array of (uint64_t)s, so we can
1790 * use them directly for accessing the copy of the statistics block
1791 * that the chip DMAs into main memory ...
1792 */
1793
1794 #define KS_BASE 0x300
1795 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t))
1796
1797 typedef enum {
1798 KS_ifHCInOctets = KS_ADDR(0x400),
1799 KS_etherStatsFragments = KS_ADDR(0x410),
1800 KS_ifHCInUcastPkts,
1801 KS_ifHCInMulticastPkts,
1802 KS_ifHCInBroadcastPkts,
1803 KS_dot3StatsFCSErrors,
1804 KS_dot3StatsAlignmentErrors,
1805 KS_xonPauseFramesReceived,
1806 KS_xoffPauseFramesReceived,
1807 KS_macControlFramesReceived,
1808 KS_xoffStateEntered,
1809 KS_dot3StatsFrameTooLongs,
1810 KS_etherStatsJabbers,
1811 KS_etherStatsUndersizePkts,
1812 KS_inRangeLengthError,
1813 KS_outRangeLengthError,
1814 KS_etherStatsPkts64Octets,
1815 KS_etherStatsPkts65to127Octets,
1816 KS_etherStatsPkts128to255Octets,
1817 KS_etherStatsPkts256to511Octets,
1818 KS_etherStatsPkts512to1023Octets,
1819 KS_etherStatsPkts1024to1518Octets,
1820 KS_etherStatsPkts1519to2047Octets,
1821 KS_etherStatsPkts2048to4095Octets,
1822 KS_etherStatsPkts4096to8191Octets,
1823 KS_etherStatsPkts8192to9022Octets,
1824
1825 KS_ifHCOutOctets = KS_ADDR(0x600),
1826 KS_etherStatsCollisions = KS_ADDR(0x610),
1827 KS_outXonSent,
1828 KS_outXoffSent,
1829 KS_flowControlDone,
1830 KS_dot3StatsInternalMacTransmitErrors,
1831 KS_dot3StatsSingleCollisionFrames,
1832 KS_dot3StatsMultipleCollisionFrames,
1833 KS_dot3StatsDeferredTransmissions,
1834 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658),
1835 KS_dot3StatsLateCollisions,
1836 KS_dot3Collided2Times,
1837 KS_dot3Collided3Times,
1838 KS_dot3Collided4Times,
1839 KS_dot3Collided5Times,
1840 KS_dot3Collided6Times,
1841 KS_dot3Collided7Times,
1842 KS_dot3Collided8Times,
1843 KS_dot3Collided9Times,
1844 KS_dot3Collided10Times,
1845 KS_dot3Collided11Times,
1846 KS_dot3Collided12Times,
1847 KS_dot3Collided13Times,
1848 KS_dot3Collided14Times,
1849 KS_dot3Collided15Times,
1850 KS_ifHCOutUcastPkts,
1851 KS_ifHCOutMulticastPkts,
1852 KS_ifHCOutBroadcastPkts,
1853 KS_dot3StatsCarrierSenseErrors,
1854 KS_ifOutDiscards,
1855 KS_ifOutErrors,
1856
1857 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */
1858 KS_COSIfHCInPkts_2,
1859 KS_COSIfHCInPkts_3,
1860 KS_COSIfHCInPkts_4,
1861 KS_COSIfHCInPkts_5,
1862 KS_COSIfHCInPkts_6,
1863 KS_COSIfHCInPkts_7,
1864 KS_COSIfHCInPkts_8,
1865 KS_COSIfHCInPkts_9,
1866 KS_COSIfHCInPkts_10,
1867 KS_COSIfHCInPkts_11,
1868 KS_COSIfHCInPkts_12,
1869 KS_COSIfHCInPkts_13,
1870 KS_COSIfHCInPkts_14,
1871 KS_COSIfHCInPkts_15,
1872 KS_COSIfHCInPkts_16,
1873 KS_COSFramesDroppedDueToFilters,
1874 KS_nicDmaWriteQueueFull,
1875 KS_nicDmaWriteHighPriQueueFull,
1876 KS_nicNoMoreRxBDs,
1877 KS_ifInDiscards,
1878 KS_ifInErrors,
1879 KS_nicRecvThresholdHit,
1880
1881 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */
1882 KS_COSIfHCOutPkts_2,
1883 KS_COSIfHCOutPkts_3,
1884 KS_COSIfHCOutPkts_4,
1885 KS_COSIfHCOutPkts_5,
1886 KS_COSIfHCOutPkts_6,
1887 KS_COSIfHCOutPkts_7,
1888 KS_COSIfHCOutPkts_8,
1889 KS_COSIfHCOutPkts_9,
1890 KS_COSIfHCOutPkts_10,
1891 KS_COSIfHCOutPkts_11,
1892 KS_COSIfHCOutPkts_12,
1893 KS_COSIfHCOutPkts_13,
1894 KS_COSIfHCOutPkts_14,
1895 KS_COSIfHCOutPkts_15,
1896 KS_COSIfHCOutPkts_16,
1897 KS_nicDmaReadQueueFull,
1898 KS_nicDmaReadHighPriQueueFull,
1899 KS_nicSendDataCompQueueFull,
1900 KS_nicRingSetSendProdIndex,
1901 KS_nicRingStatusUpdate,
1902 KS_nicInterrupts,
1903 KS_nicAvoidedInterrupts,
1904 KS_nicSendThresholdHit,
1905
1906 KS_STATS_SIZE = KS_ADDR(0xb00)
1907 } bge_stats_offset_t;
1908
1909 /*
1910 * Hardware-defined Statistics Block
1911 *
1912 * Another view of the statistic block, as a array and a structure ...
1913 */
1914
1915 typedef union {
1916 uint64_t a[KS_STATS_SIZE];
1917 struct {
1918 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)];
1919
1920 uint64_t ifHCInOctets; /* 0x0400 */
1921 uint64_t spare2[1];
1922 uint64_t etherStatsFragments;
1923 uint64_t ifHCInUcastPkts;
1924 uint64_t ifHCInMulticastPkts;
1925 uint64_t ifHCInBroadcastPkts;
1926 uint64_t dot3StatsFCSErrors;
1927 uint64_t dot3StatsAlignmentErrors;
1928 uint64_t xonPauseFramesReceived;
1929 uint64_t xoffPauseFramesReceived;
1930 uint64_t macControlFramesReceived;
1931 uint64_t xoffStateEntered;
1932 uint64_t dot3StatsFrameTooLongs;
1933 uint64_t etherStatsJabbers;
1934 uint64_t etherStatsUndersizePkts;
1935 uint64_t inRangeLengthError;
1936 uint64_t outRangeLengthError;
1937 uint64_t etherStatsPkts64Octets;
1938 uint64_t etherStatsPkts65to127Octets;
1939 uint64_t etherStatsPkts128to255Octets;
1940 uint64_t etherStatsPkts256to511Octets;
1941 uint64_t etherStatsPkts512to1023Octets;
1942 uint64_t etherStatsPkts1024to1518Octets;
1943 uint64_t etherStatsPkts1519to2047Octets;
1944 uint64_t etherStatsPkts2048to4095Octets;
1945 uint64_t etherStatsPkts4096to8191Octets;
1946 uint64_t etherStatsPkts8192to9022Octets;
1947 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)];
1948
1949 uint64_t ifHCOutOctets; /* 0x0600 */
1950 uint64_t spare4[1];
1951 uint64_t etherStatsCollisions;
1952 uint64_t outXonSent;
1953 uint64_t outXoffSent;
1954 uint64_t flowControlDone;
1955 uint64_t dot3StatsInternalMacTransmitErrors;
1956 uint64_t dot3StatsSingleCollisionFrames;
1957 uint64_t dot3StatsMultipleCollisionFrames;
1958 uint64_t dot3StatsDeferredTransmissions;
1959 uint64_t spare5[1];
1960 uint64_t dot3StatsExcessiveCollisions;
1961 uint64_t dot3StatsLateCollisions;
1962 uint64_t dot3Collided2Times;
1963 uint64_t dot3Collided3Times;
1964 uint64_t dot3Collided4Times;
1965 uint64_t dot3Collided5Times;
1966 uint64_t dot3Collided6Times;
1967 uint64_t dot3Collided7Times;
1968 uint64_t dot3Collided8Times;
1969 uint64_t dot3Collided9Times;
1970 uint64_t dot3Collided10Times;
1971 uint64_t dot3Collided11Times;
1972 uint64_t dot3Collided12Times;
1973 uint64_t dot3Collided13Times;
1974 uint64_t dot3Collided14Times;
1975 uint64_t dot3Collided15Times;
1976 uint64_t ifHCOutUcastPkts;
1977 uint64_t ifHCOutMulticastPkts;
1978 uint64_t ifHCOutBroadcastPkts;
1979 uint64_t dot3StatsCarrierSenseErrors;
1980 uint64_t ifOutDiscards;
1981 uint64_t ifOutErrors;
1982 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)];
1983
1984 uint64_t COSIfHCInPkts[16]; /* 0x0800 */
1985 uint64_t COSFramesDroppedDueToFilters;
1986 uint64_t nicDmaWriteQueueFull;
1987 uint64_t nicDmaWriteHighPriQueueFull;
1988 uint64_t nicNoMoreRxBDs;
1989 uint64_t ifInDiscards;
1990 uint64_t ifInErrors;
1991 uint64_t nicRecvThresholdHit;
1992 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)];
1993
1994 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */
1995 uint64_t nicDmaReadQueueFull;
1996 uint64_t nicDmaReadHighPriQueueFull;
1997 uint64_t nicSendDataCompQueueFull;
1998 uint64_t nicRingSetSendProdIndex;
1999 uint64_t nicRingStatusUpdate;
2000 uint64_t nicInterrupts;
2001 uint64_t nicAvoidedInterrupts;
2002 uint64_t nicSendThresholdHit;
2003 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)];
2004 } s;
2005 } bge_statistics_t;
2006
2007 #define KS_STAT_REG_SIZE (0x1B)
2008 #define KS_STAT_REG_BASE (0x800)
2009
2010 typedef struct {
2011 uint32_t ifHCOutOctets;
2012 uint32_t etherStatsCollisions;
2013 uint32_t outXonSent;
2014 uint32_t outXoffSent;
2015 uint32_t dot3StatsInternalMacTransmitErrors;
2016 uint32_t dot3StatsSingleCollisionFrames;
2017 uint32_t dot3StatsMultipleCollisionFrames;
2018 uint32_t dot3StatsDeferredTransmissions;
2019 uint32_t dot3StatsExcessiveCollisions;
2020 uint32_t dot3StatsLateCollisions;
2021 uint32_t ifHCOutUcastPkts;
2022 uint32_t ifHCOutMulticastPkts;
2023 uint32_t ifHCOutBroadcastPkts;
2024 uint32_t ifHCInOctets;
2025 uint32_t etherStatsFragments;
2026 uint32_t ifHCInUcastPkts;
2027 uint32_t ifHCInMulticastPkts;
2028 uint32_t ifHCInBroadcastPkts;
2029 uint32_t dot3StatsFCSErrors;
2030 uint32_t dot3StatsAlignmentErrors;
2031 uint32_t xonPauseFramesReceived;
2032 uint32_t xoffPauseFramesReceived;
2033 uint32_t macControlFramesReceived;
2034 uint32_t xoffStateEntered;
2035 uint32_t dot3StatsFrameTooLongs;
2036 uint32_t etherStatsJabbers;
2037 uint32_t etherStatsUndersizePkts;
2038 } bge_statistics_reg_t;
2039
2040
2041 #ifdef BGE_IPMI_ASF
2042
2043 /*
2044 * Device internal memory entries
2045 */
2046
2047 #define BGE_FIRMWARE_MAILBOX 0x0b50
2048 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654
2049 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
2050
2051
2052 #define BGE_NIC_DATA_SIG_ADDR 0x0b54
2053 #define BGE_NIC_DATA_SIG 0x4b657654
2054
2055
2056 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58
2057
2058 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004
2059 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008
2060 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004
2061 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008
2062 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c
2063
2064 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000
2065 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010
2066 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020
2067 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030
2068
2069 #define BGE_NIC_CFG_ENABLE_WOL 0x000040
2070 #define BGE_NIC_CFG_ENABLE_ASF 0x000080
2071 #define BGE_NIC_CFG_EEPROM_WP 0x000100
2072 #define BGE_NIC_CFG_POWER_SAVING 0x000200
2073 #define BGE_NIC_CFG_SWAP_PORT 0x000800
2074 #define BGE_NIC_CFG_MINI_PCI 0x001000
2075 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000
2076 #define BGE_NIC_CFG_5753_12x12 0x100000
2077
2078
2079 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c
2080
2081
2082 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74
2083 #define BGE_NIC_PHY_ID1_MASK 0xffff0000
2084 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff
2085
2086
2087 #define BGE_CMD_MAILBOX 0x0b78
2088 #define BGE_CMD_NICDRV_ALIVE 0x00000001
2089 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002
2090 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003
2091 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004
2092
2093
2094 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c
2095 #define BGE_CMD_DATA_MAILBOX 0x0b80
2096 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00
2097
2098 #define BGE_DRV_STATE_MAILBOX 0x0c04
2099 #define BGE_DRV_STATE_START 0x00000001
2100 #define BGE_DRV_STATE_START_DONE 0x80000001
2101 #define BGE_DRV_STATE_UNLOAD 0x00000002
2102 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002
2103 #define BGE_DRV_STATE_WOL 0x00000003
2104 #define BGE_DRV_STATE_SUSPEND 0x00000004
2105
2106
2107 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08
2108 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001
2109 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002
2110
2111
2112 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14
2113 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18
2114
2115
2116 /*
2117 * RX-RISC event register
2118 */
2119 #define RX_RISC_EVENT_REG 0x6810
2120 #define RRER_ASF_EVENT 0x4000
2121
2122 #endif /* BGE_IPMI_ASF */
2123
2124 #ifdef __cplusplus
2125 }
2126 #endif
2127
2128 #endif /* _BGE_HW_H */