1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #ifndef _BGE_HW_H
27 #define _BGE_HW_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <sys/types.h>
34
35
36 /*
37 * First section:
38 * Identification of the various Broadcom chips
39 *
40 * Note: the various ID values are *not* all unique ;-(
41 *
42 * Note: the presence of an ID here does *not* imply that the chip is
43 * supported. At this time, only the 5703C, 5704C, and 5704S devices
44 * used on the motherboards of certain Sun products are supported.
45 *
46 * Note: the revision-id values in the PCI revision ID register are
47 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead.
48 */
49
50 #define VENDOR_ID_BROADCOM 0x14e4
51 #define VENDOR_ID_SUN 0x108e
52
53 #define DEVICE_ID_5700 0x1644
54 #define DEVICE_ID_5700x 0x0003
55 #define DEVICE_ID_5701 0x1645
56 #define DEVICE_ID_5702 0x16a6
57 #define DEVICE_ID_5702fe 0x164d
58 #define DEVICE_ID_5703C 0x16a7
59 #define DEVICE_ID_5703S 0x1647
60 #define DEVICE_ID_5703 0x16c7
61 #define DEVICE_ID_5704C 0x1648
62 #define DEVICE_ID_5704S 0x16a8
63 #define DEVICE_ID_5704 0x1649
64 #define DEVICE_ID_5705C 0x1653
65 #define DEVICE_ID_5705_2 0x1654
66 #define DEVICE_ID_5717 0x1655
67 #define DEVICE_ID_5718 0x1656
68 #define DEVICE_ID_5724 0x165c
69 #define DEVICE_ID_5705M 0x165d
70 #define DEVICE_ID_5705MA3 0x165e
71 #define DEVICE_ID_5705F 0x166e
72 #define DEVICE_ID_5780 0x166a
73 #define DEVICE_ID_5782 0x1696
74 #define DEVICE_ID_5784M 0x1698
75 #define DEVICE_ID_5785 0x1699
76 #define DEVICE_ID_5787 0x169b
77 #define DEVICE_ID_5787M 0x1693
78 #define DEVICE_ID_5788 0x169c
79 #define DEVICE_ID_5789 0x169d
80 #define DEVICE_ID_5751 0x1677
81 #define DEVICE_ID_5751M 0x167d
82 #define DEVICE_ID_5752 0x1600
83 #define DEVICE_ID_5752M 0x1601
84 #define DEVICE_ID_5753 0x16fd
85 #define DEVICE_ID_5754 0x167a
86 #define DEVICE_ID_5755 0x167b
87 #define DEVICE_ID_5755M 0x1673
88 #define DEVICE_ID_5756M 0x1674
89 #define DEVICE_ID_5721 0x1659
90 #define DEVICE_ID_5722 0x165a
91 #define DEVICE_ID_5723 0x165b
92 #define DEVICE_ID_5714C 0x1668
93 #define DEVICE_ID_5714S 0x1669
94 #define DEVICE_ID_5715C 0x1678
95 #define DEVICE_ID_5715S 0x1679
96 #define DEVICE_ID_5761 0x1681
97 #define DEVICE_ID_5761E 0x1680
98 #define DEVICE_ID_5761S 0x1688
99 #define DEVICE_ID_5761SE 0x1689
100 #define DEVICE_ID_5764 0x1684
101 #define DEVICE_ID_5906 0x1712
102 #define DEVICE_ID_5906M 0x1713
103 #define DEVICE_ID_57760 0x1690
104 #define DEVICE_ID_57780 0x1692
105 #define DEVICE_ID_57788 0x1691
106 #define DEVICE_ID_57790 0x1694
107
108 #define REVISION_ID_5700_B0 0x10
109 #define REVISION_ID_5700_B2 0x12
110 #define REVISION_ID_5700_B3 0x13
111 #define REVISION_ID_5700_C0 0x20
112 #define REVISION_ID_5700_C1 0x21
113 #define REVISION_ID_5700_C2 0x22
114
115 #define REVISION_ID_5701_A0 0x08
116 #define REVISION_ID_5701_A2 0x12
117 #define REVISION_ID_5701_A3 0x15
118
119 #define REVISION_ID_5702_A0 0x00
120
121 #define REVISION_ID_5703_A0 0x00
122 #define REVISION_ID_5703_A1 0x01
123 #define REVISION_ID_5703_A2 0x02
124
125 #define REVISION_ID_5704_A0 0x00
126 #define REVISION_ID_5704_A1 0x01
127 #define REVISION_ID_5704_A2 0x02
128 #define REVISION_ID_5704_A3 0x03
129 #define REVISION_ID_5704_B0 0x10
130
131 #define REVISION_ID_5705_A0 0x00
132 #define REVISION_ID_5705_A1 0x01
133 #define REVISION_ID_5705_A2 0x02
134 #define REVISION_ID_5705_A3 0x03
135
136 #define REVISION_ID_5721_A0 0x00
137 #define REVISION_ID_5721_A1 0x01
138
139 #define REVISION_ID_5751_A0 0x00
140 #define REVISION_ID_5751_A1 0x01
141
142 #define REVISION_ID_5714_A0 0x00
143 #define REVISION_ID_5714_A1 0x01
144 #define REVISION_ID_5714_A2 0xA2
145 #define REVISION_ID_5714_A3 0xA3
146
147 #define REVISION_ID_5715_A0 0x00
148 #define REVISION_ID_5715_A1 0x01
149 #define REVISION_ID_5715_A2 0xA2
150
151 #define REVISION_ID_5715S_A0 0x00
152 #define REVISION_ID_5715S_A1 0x01
153
154 #define REVISION_ID_5754_A0 0x00
155 #define REVISION_ID_5754_A1 0x01
156
157 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\
158 ((bgep->chipid.device == DEVICE_ID_5700) ||\
159 (bgep->chipid.device == DEVICE_ID_5701) ||\
160 (bgep->chipid.device == DEVICE_ID_5702) ||\
161 (bgep->chipid.device == DEVICE_ID_5702fe)||\
162 (bgep->chipid.device == DEVICE_ID_5703C) ||\
163 (bgep->chipid.device == DEVICE_ID_5703S) ||\
164 (bgep->chipid.device == DEVICE_ID_5703) ||\
165 (bgep->chipid.device == DEVICE_ID_5704C) ||\
166 (bgep->chipid.device == DEVICE_ID_5704S) ||\
167 (bgep->chipid.device == DEVICE_ID_5704))
168
169 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \
170 ((bgep->chipid.device == DEVICE_ID_5702) ||\
171 (bgep->chipid.device == DEVICE_ID_5702fe))
172
173 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \
174 ((bgep->chipid.device == DEVICE_ID_5705C) ||\
175 (bgep->chipid.device == DEVICE_ID_5705M) ||\
176 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\
177 (bgep->chipid.device == DEVICE_ID_5705F) ||\
178 (bgep->chipid.device == DEVICE_ID_5780) ||\
179 (bgep->chipid.device == DEVICE_ID_5782) ||\
180 (bgep->chipid.device == DEVICE_ID_5788) ||\
181 (bgep->chipid.device == DEVICE_ID_5705_2) ||\
182 (bgep->chipid.device == DEVICE_ID_5754) ||\
183 (bgep->chipid.device == DEVICE_ID_5755) ||\
184 (bgep->chipid.device == DEVICE_ID_5756M) ||\
185 (bgep->chipid.device == DEVICE_ID_5753))
186
187 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \
188 ((bgep->chipid.device == DEVICE_ID_5721) ||\
189 (bgep->chipid.device == DEVICE_ID_5751) ||\
190 (bgep->chipid.device == DEVICE_ID_5751M) ||\
191 (bgep->chipid.device == DEVICE_ID_5752) ||\
192 (bgep->chipid.device == DEVICE_ID_5752M) ||\
193 (bgep->chipid.device == DEVICE_ID_5789))
194
195 #define DEVICE_5717_SERIES_CHIPSETS(bgep) \
196 (bgep->chipid.device == DEVICE_ID_5717) ||\
197 (bgep->chipid.device == DEVICE_ID_5718) ||\
198 (bgep->chipid.device == DEVICE_ID_5724)
199
200 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \
201 ((bgep->chipid.device == DEVICE_ID_5723) ||\
202 (bgep->chipid.device == DEVICE_ID_5761) ||\
203 (bgep->chipid.device == DEVICE_ID_5761E) ||\
204 (bgep->chipid.device == DEVICE_ID_5761S) ||\
205 (bgep->chipid.device == DEVICE_ID_5761SE) ||\
206 (bgep->chipid.device == DEVICE_ID_5764) ||\
207 (bgep->chipid.device == DEVICE_ID_5784M) ||\
208 (bgep->chipid.device == DEVICE_ID_5785) ||\
209 (bgep->chipid.device == DEVICE_ID_57760) ||\
210 (bgep->chipid.device == DEVICE_ID_57780) ||\
211 (bgep->chipid.device == DEVICE_ID_57788) ||\
212 (bgep->chipid.device == DEVICE_ID_57790))
213
214 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \
215 ((bgep->chipid.device == DEVICE_ID_5714C) ||\
216 (bgep->chipid.device == DEVICE_ID_5714S) ||\
217 (bgep->chipid.device == DEVICE_ID_5715C) ||\
218 (bgep->chipid.device == DEVICE_ID_5715S))
219
220 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \
221 ((bgep->chipid.device == DEVICE_ID_5906) ||\
222 (bgep->chipid.device == DEVICE_ID_5906M))
223
224 /*
225 * Second section:
226 * Offsets of important registers & definitions for bits therein
227 */
228
229 /*
230 * PCI-X registers & bits
231 */
232 #define PCIX_CONF_COMM 0x42
233 #define PCIX_COMM_RELAXED 0x0002
234
235 /*
236 * Miscellaneous Host Control Register, in PCI config space
237 */
238 #define PCI_CONF_BGE_MHCR 0x68
239 #define MHCR_CHIP_REV_MASK 0xffff0000
240 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200
241 #define MHCR_MASK_INTERRUPT_MODE 0x00000100
242 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080
243 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040
244 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020
245 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010
246 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008
247 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004
248 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002
249 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001
250
251 #define MHCR_CHIP_REV_5700_B0 0x71000000
252 #define MHCR_CHIP_REV_5700_B2 0x71020000
253 #define MHCR_CHIP_REV_5700_B3 0x71030000
254 #define MHCR_CHIP_REV_5700_C0 0x72000000
255 #define MHCR_CHIP_REV_5700_C1 0x72010000
256 #define MHCR_CHIP_REV_5700_C2 0x72020000
257
258 #define MHCR_CHIP_REV_5701_A0 0x00000000
259 #define MHCR_CHIP_REV_5701_A2 0x00020000
260 #define MHCR_CHIP_REV_5701_A3 0x00030000
261 #define MHCR_CHIP_REV_5701_A5 0x01050000
262
263 #define MHCR_CHIP_REV_5702_A0 0x10000000
264 #define MHCR_CHIP_REV_5702_A1 0x10010000
265 #define MHCR_CHIP_REV_5702_A2 0x10020000
266
267 #define MHCR_CHIP_REV_5703_A0 0x10000000
268 #define MHCR_CHIP_REV_5703_A1 0x10010000
269 #define MHCR_CHIP_REV_5703_A2 0x10020000
270 #define MHCR_CHIP_REV_5703_B0 0x11000000
271 #define MHCR_CHIP_REV_5703_B1 0x11010000
272
273 #define MHCR_CHIP_REV_5704_A0 0x20000000
274 #define MHCR_CHIP_REV_5704_A1 0x20010000
275 #define MHCR_CHIP_REV_5704_A2 0x20020000
276 #define MHCR_CHIP_REV_5704_A3 0x20030000
277 #define MHCR_CHIP_REV_5704_B0 0x21000000
278
279 #define MHCR_CHIP_REV_5705_A0 0x30000000
280 #define MHCR_CHIP_REV_5705_A1 0x30010000
281 #define MHCR_CHIP_REV_5705_A2 0x30020000
282 #define MHCR_CHIP_REV_5705_A3 0x30030000
283 #define MHCR_CHIP_REV_5705_A5 0x30050000
284
285 #define MHCR_CHIP_REV_5782_A0 0x30030000
286 #define MHCR_CHIP_REV_5782_A1 0x30030088
287
288 #define MHCR_CHIP_REV_5788_A1 0x30050000
289
290 #define MHCR_CHIP_REV_5751_A0 0x40000000
291 #define MHCR_CHIP_REV_5751_A1 0x40010000
292
293 #define MHCR_CHIP_REV_5721_A0 0x41000000
294 #define MHCR_CHIP_REV_5721_A1 0x41010000
295
296 #define MHCR_CHIP_REV_5714_A0 0x50000000
297 #define MHCR_CHIP_REV_5714_A1 0x90010000
298
299 #define MHCR_CHIP_REV_5715_A0 0x50000000
300 #define MHCR_CHIP_REV_5715_A1 0x90010000
301
302 #define MHCR_CHIP_REV_5715S_A0 0x50000000
303 #define MHCR_CHIP_REV_5715S_A1 0x90010000
304
305 #define MHCR_CHIP_REV_5754_A0 0xb0000000
306 #define MHCR_CHIP_REV_5754_A1 0xb0010000
307
308 #define MHCR_CHIP_REV_5787_A0 0xb0000000
309 #define MHCR_CHIP_REV_5787_A1 0xb0010000
310 #define MHCR_CHIP_REV_5787_A2 0xb0020000
311
312 #define MHCR_CHIP_REV_5755_A0 0xa0000000
313 #define MHCR_CHIP_REV_5755_A1 0xa0010000
314
315 #define MHCR_CHIP_REV_5906_A0 0xc0000000
316 #define MHCR_CHIP_REV_5906_A1 0xc0010000
317 #define MHCR_CHIP_REV_5906_A2 0xc0020000
318
319 #define MHCR_CHIP_REV_5723_A0 0xf0000000
320 #define MHCR_CHIP_REV_5723_A1 0xf0010000
321 #define MHCR_CHIP_REV_5723_A2 0xf0020000
322 #define MHCR_CHIP_REV_5723_B0 0xf1000000
323
324 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000)
325 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28)
326 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28)
327 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28)
328 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28)
329 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28)
330 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28)
331 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28)
332 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28)
333 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28)
334 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28)
335 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28)
336 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28)
337 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28)
338 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28)
339
340
341 /*
342 * PCI DMA read/write Control Register, in PCI config space
343 *
344 * Note that several fields previously defined here have been deleted
345 * as they are not implemented in the 5703/4.
346 *
347 * Note: the value of this register is critical. It is possible to
348 * cause various unpleasant effects (DTOs, transaction deadlock, etc)
349 * by programming the wrong value. The value #defined below has been
350 * tested and shown to avoid all known problems. If it is to be changed,
351 * correct operation must be reverified on all supported platforms.
352 *
353 * In particular, we set both watermark fields to 2xCacheLineSize (128)
354 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
355 * with Tomatillo's internal pipelines, that otherwise result in stalls,
356 * repeated retries, and DTOs.
357 */
358 #define PCI_CONF_BGE_PDRWCR 0x6c
359 #define PDRWCR_RWCMD_MASK 0xFF000000
360 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000
361 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000
362 #define PDRWCR_READ_WATERMARK_MASK 0x00070000
363 #define PDRWCR_CONCURRENCY_MASK 0x0000c000
364 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000
365 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000
366 #define PDRWCR_MIN_BEAT_MASK 0x000000ff
367
368 /*
369 * These are the actual values to be put into the fields shown above
370 */
371 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */
372 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */
373 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */
374 #define PDRWCR_MIN_BEATS 0x00000000
375
376 #define PDRWCR_VAR_DEFAULT 0x761b0000
377 #define PDRWCR_VAR_5721 0x76180000
378 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */
379 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */
380 #define PDRWCR_VAR_5717 0x00380000
381
382 /*
383 * PCI State Register, in PCI config space
384 *
385 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
386 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
387 */
388 #define PCI_CONF_BGE_PCISTATE 0x70
389 #define PCISTATE_RETRY_SAME_DMA 0x00002000
390 #define PCISTATE_FLAT_VIEW 0x00000100
391 #define PCISTATE_EXT_ROM_RETRY 0x00000040
392 #define PCISTATE_EXT_ROM_ENABLE 0x00000020
393 #define PCISTATE_BUS_IS_32_BIT 0x00000010
394 #define PCISTATE_BUS_IS_FAST 0x00000008
395 #define PCISTATE_BUS_IS_PCI 0x00000004
396 #define PCISTATE_INTA_STATE 0x00000002
397 #define PCISTATE_FORCE_RESET 0x00000001
398
399 /*
400 * PCI Clock Control Register, in PCI config space
401 */
402 #define PCI_CONF_BGE_CLKCTL 0x74
403 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000
404 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000
405 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000
406 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000
407 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000
408 #define CLKCTL_PCIE_A0_FIX 0x00101000
409
410 /*
411 * Dual MAC Control Register, in PCI config space
412 */
413 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8
414 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */
415 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */
416
417 /*
418 * Register Indirect Access Address Register, 0x78 in PCI config
419 * space. Once this is set, accesses to the Register Indirect
420 * Access Data Register (0x80) refer to the register whose address
421 * is given by *this* register. This allows access to all the
422 * operating registers, while using only config space accesses.
423 *
424 * Note that the address written to the RIIAR should lie in one
425 * of the following ranges:
426 * 0x00000000 <= address < 0x00008000 (regular registers)
427 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
428 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
429 * 0x00038000 <= address < 0x00038800 (RxRISC ROM)
430 */
431 #define PCI_CONF_BGE_RIAAR 0x78
432 #define PCI_CONF_BGE_RIADR 0x80
433
434 #define RIAAR_REGISTER_MIN 0x00000000
435 #define RIAAR_REGISTER_MAX 0x00008000
436 #define RIAAR_RX_SCRATCH_MIN 0x00030000
437 #define RIAAR_RX_SCRATCH_MAX 0x00034000
438 #define RIAAR_TX_SCRATCH_MIN 0x00034000
439 #define RIAAR_TX_SCRATCH_MAX 0x00038000
440 #define RIAAR_RXROM_MIN 0x00038000
441 #define RIAAR_RXROM_MAX 0x00038800
442
443 /*
444 * Memory Window Base Address Register, 0x7c in PCI config space
445 * Once this is set, accesses to the Memory Window Data Access Register
446 * (0x84) refer to the word of NIC-local memory whose address is given
447 * by this register. When used in this way, the whole of the address
448 * written to this register is significant.
449 *
450 * This register also provides the 32K-aligned base address for a 32K
451 * region of NIC-local memory that the host can directly address in
452 * the upper 32K of the 64K of PCI memory space allocated to the chip.
453 * In this case, the bottom 15 bits of the register are ignored.
454 *
455 * Note that the address written to the MWBAR should lie in the range
456 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M
457 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
458 * memory were present, but it's only supported on the 5700, not the
459 * 5701/5703/5704.
460 */
461 #define PCI_CONF_BGE_MWBAR 0x7c
462 #define PCI_CONF_BGE_MWDAR 0x84
463 #define MWBAR_GRANULARITY 0x00008000 /* 32k */
464 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1)
465 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */
466
467 /*
468 * The PCI express device control register and device status register
469 * which are only applicable on BCM5751 and BCM5721.
470 */
471 #define PCI_CONF_DEV_CTRL 0xd8
472 #define PCI_CONF_DEV_CTRL_5723 0xd4
473 #define READ_REQ_SIZE_MAX 0x5000
474 #define DEV_CTRL_NO_SNOOP 0x0800
475 #define DEV_CTRL_RELAXED 0x0010
476
477 #define PCI_CONF_DEV_STUS 0xda
478 #define PCI_CONF_DEV_STUS_5723 0xd6
479 #define DEVICE_ERROR_STUS 0xf
480
481 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */
482
483 /*
484 * Where to find things in NIC-local (on-chip) memory
485 */
486 #define NIC_MEM_SEND_RINGS 0x0100
487 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring))
488 #define NIC_MEM_RECV_RINGS 0x0200
489 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring))
490 #define NIC_MEM_STATISTICS 0x0300
491 #define NIC_MEM_STATISTICS_SIZE 0x0800
492 #define NIC_MEM_STATUS_BLOCK 0x0b00
493 #define NIC_MEM_STATUS_SIZE 0x0050
494 #define NIC_MEM_GENCOMM 0x0b50
495
496
497 /*
498 * Note: the (non-bogus) values below are appropriate for systems
499 * without external memory. They would be different on a 5700 with
500 * external memory.
501 *
502 * Note: The higher send ring addresses and the mini ring shadow
503 * buffer address are dummies - systems without external memory
504 * are limited to 4 send rings and no mini receive ring.
505 */
506 #define NIC_MEM_SHADOW_DMA 0x2000
507 #define NIC_MEM_SHADOW_SEND_1_4 0x4000
508 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */
509 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */
510 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */
511 #define NIC_MEM_SHADOW_BUFF_STD 0x6000
512 #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000
513 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000
514 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */
515 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots))
516
517 /*
518 * Put this in the GENCOMM port to tell the firmware not to run PXE
519 */
520 #define T3_MAGIC_NUMBER 0x4b657654u
521
522 /*
523 * The remaining registers appear in the low 32K of regular
524 * PCI Memory Address Space
525 */
526
527 /*
528 * All the state machine control registers below have at least a
529 * <RESET> bit and an <ENABLE> bit as defined below. Some also
530 * have an <ATTN_ENABLE> bit.
531 */
532 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004
533 #define STATE_MACHINE_ENABLE_BIT 0x00000002
534 #define STATE_MACHINE_RESET_BIT 0x00000001
535
536 #define TRANSMIT_MAC_MODE_REG 0x045c
537 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00
538 #define SEND_DATA_COMPLETION_MODE_REG 0x1000
539 #define SEND_BD_SELECTOR_MODE_REG 0x1400
540 #define SEND_BD_INITIATOR_MODE_REG 0x1800
541 #define SEND_BD_COMPLETION_MODE_REG 0x1c00
542
543 #define RECEIVE_MAC_MODE_REG 0x0468
544 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000
545 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400
546 #define RCV_DATA_COMPLETION_MODE_REG 0x2800
547 #define RCV_BD_INITIATOR_MODE_REG 0x2c00
548 #define RCV_BD_COMPLETION_MODE_REG 0x3000
549 #define RCV_LIST_SELECTOR_MODE_REG 0x3400
550
551 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800
552 #define HOST_COALESCE_MODE_REG 0x3c00
553 #define MEMORY_ARBITER_MODE_REG 0x4000
554 #define BUFFER_MANAGER_MODE_REG 0x4400
555 #define READ_DMA_MODE_REG 0x4800
556 #define WRITE_DMA_MODE_REG 0x4c00
557 #define DMA_COMPLETION_MODE_REG 0x6400
558
559 /*
560 * Other bits in some of the above state machine control registers
561 */
562
563 /*
564 * Transmit MAC Mode Register
565 * (TRANSMIT_MAC_MODE_REG, 0x045c)
566 */
567 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040
568 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020
569 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010
570
571 /*
572 * Receive MAC Mode Register
573 * (RECEIVE_MAC_MODE_REG, 0x0468)
574 */
575 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400
576 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200
577 #define RECEIVE_MODE_PROMISCUOUS 0x00000100
578 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080
579 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040
580 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020
581 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010
582 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004
583
584 /*
585 * Receive BD Initiator Mode Register
586 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
587 *
588 * Each of these bits controls whether ATTN is asserted
589 * on a particular condition
590 */
591 #define RCV_BD_DISABLED_RING_ATTN 0x00000004
592
593 /*
594 * Receive Data & Receive BD Initiator Mode Register
595 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
596 *
597 * Each of these bits controls whether ATTN is asserted
598 * on a particular condition
599 */
600 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010
601 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008
602 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004
603
604 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c
605
606 /*
607 * Host Coalescing Mode Control Register
608 * (HOST_COALESCE_MODE_REG, 0x3c00)
609 */
610 #define COALESCE_64_BYTE_RINGS 12
611 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000
612 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800
613 #define COALESCE_CLR_TICKS_TX 0x00000400
614 #define COALESCE_CLR_TICKS_RX 0x00000200
615 #define COALESCE_32_BYTE_STATUS 0x00000100
616 #define COALESCE_64_BYTE_STATUS 0x00000080
617 #define COALESCE_NOW 0x00000008
618
619 /*
620 * Memory Arbiter Mode Register
621 * (MEMORY_ARBITER_MODE_REG, 0x4000)
622 */
623 #define MEMORY_ARBITER_ENABLE 0x00000002
624
625 /*
626 * Buffer Manager Mode Register
627 * (BUFFER_MANAGER_MODE_REG, 0x4400)
628 *
629 * In addition to the usual error-attn common to most state machines
630 * this register has a separate bit for attn on running-low-on-mbufs
631 */
632 #define BUFF_MGR_TEST_MODE 0x00000008
633 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010
634
635 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014
636
637 /*
638 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
639 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
640 *
641 * These registers each contain a 2-bit priority field, which controls
642 * the relative priority of that type of DMA (read vs. write vs. MSI),
643 * and a set of bits that control whether ATTN is asserted on each
644 * particular condition
645 */
646 #define DMA_PRIORITY_MASK 0xc0000000
647 #define DMA_PRIORITY_SHIFT 30
648 #define ALL_DMA_ATTN_BITS 0x000003fc
649
650 /*
651 * BCM5755, 5755M, 5906, 5906M only
652 * 1 - Enable Fix. Device will send out the status block before
653 * the interrupt message
654 * 0 - Disable fix. Device will send out the interrupt message
655 * before the status block
656 */
657 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000
658
659 /*
660 * End of state machine control register definitions
661 */
662
663
664 /*
665 * High priority mailbox registers.
666 * Mailbox Registers (8 bytes each, but high half unused)
667 */
668 #define INTERRUPT_MBOX_0_REG 0x0200
669 #define INTERRUPT_MBOX_1_REG 0x0208
670 #define INTERRUPT_MBOX_2_REG 0x0210
671 #define INTERRUPT_MBOX_3_REG 0x0218
672 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n))
673
674 /*
675 * Low priority mailbox registers, for BCM5906, BCM5906M.
676 */
677 #define INTERRUPT_LP_MBOX_0_REG 0x5800
678
679 /*
680 * Ring Producer/Consumer Index (Mailbox) Registers
681 */
682 #define RECV_STD_PROD_INDEX_REG 0x0268
683 #define RECV_JUMBO_PROD_INDEX_REG 0x0270
684 #define RECV_MINI_PROD_INDEX_REG 0x0278
685 #define RECV_RING_CONS_INDEX_REGS 0x0280
686 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300
687 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380
688
689 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring))
690 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring))
691 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring))
692
693 /*
694 * Ethernet MAC Mode Register
695 */
696 #define ETHERNET_MAC_MODE_REG 0x0400
697 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000
698 #define ETHERNET_MODE_ENABLE_RDE 0x00400000
699 #define ETHERNET_MODE_ENABLE_TDE 0x00200000
700 #define ETHERNET_MODE_ENABLE_MIP 0x00100000
701 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000
702 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000
703 #define ETHERNET_MODE_SEND_CFGS 0x00020000
704 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000
705 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000
706 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000
707 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000
708 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000
709 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800
710 #define ETHERNET_MODE_LINK_POLARITY 0x00000400
711 #define ETHERNET_MODE_MAX_DEFER 0x00000200
712 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100
713 #define ETHERNET_MODE_TAGGED_MODE 0x00000080
714 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010
715 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c
716 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c
717 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008
718 #define ETHERNET_MODE_PORTMODE_MII 0x00000004
719 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000
720 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002
721 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001
722
723 /*
724 * Ethernet MAC Status & Event Registers
725 */
726 #define ETHERNET_MAC_STATUS_REG 0x0404
727 #define ETHERNET_STATUS_MI_INT 0x00800000
728 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000
729 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000
730 #define ETHERNET_STATUS_PCS_ERROR 0x00000400
731 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010
732 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008
733 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004
734 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002
735 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001
736
737 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408
738 #define ETHERNET_EVENT_MI_INT 0x00800000
739 #define ETHERNET_EVENT_LINK_INT 0x00001000
740 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400
741
742 /*
743 * Ethernet MAC LED Control Register
744 *
745 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and
746 * the external LED driver circuitry is wired up to assume that this mode
747 * will always be selected. Software must not change it!
748 */
749 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c
750 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000
751 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000
752 #define LED_CONTROL_LED_MODE_MASK 0x00001800
753 #define LED_CONTROL_LED_MODE_5700 0x00000000
754 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */
755 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000
756 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800
757 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400
758 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200
759 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100
760 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080
761 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040
762 #define LED_CONTROL_TRAFFIC_LED 0x00000020
763 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010
764 #define LED_CONTROL_10MBPS_LED 0x00000008
765 #define LED_CONTROL_100MBPS_LED 0x00000004
766 #define LED_CONTROL_1000MBPS_LED 0x00000002
767 #define LED_CONTROL_OVERRIDE_LINK 0x00000001
768 #define LED_CONTROL_DEFAULT 0x02000800
769
770 /*
771 * MAC Address registers
772 *
773 * These four eight-byte registers each hold one unicast address
774 * (six bytes), right justified & zero-filled on the left.
775 * They will normally all be set to the same value, as a station
776 * usually only has one h/w address. The value in register 0 is
777 * used for pause packets; any of the four can be specified for
778 * substitution into other transmitted packets if required.
779 */
780 #define MAC_ADDRESS_0_REG 0x0410
781 #define MAC_ADDRESS_1_REG 0x0418
782 #define MAC_ADDRESS_2_REG 0x0420
783 #define MAC_ADDRESS_3_REG 0x0428
784
785 #define MAC_ADDRESS_REG(n) (0x0410+8*(n))
786 #define MAC_ADDRESS_REGS_MAX 4
787
788 /*
789 * More MAC Registers ...
790 */
791 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438
792 #define MAC_RX_MTU_SIZE_REG 0x043c
793 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */
794 #define MAC_TX_LENGTHS_REG 0x0464
795 #define MAC_TX_LENGTHS_DEFAULT 0x00002620
796
797 /*
798 * MII access registers
799 */
800 #define MI_COMMS_REG 0x044c
801 #define MI_COMMS_START 0x20000000
802 #define MI_COMMS_READ_FAILED 0x10000000
803 #define MI_COMMS_COMMAND_MASK 0x0c000000
804 #define MI_COMMS_COMMAND_READ 0x08000000
805 #define MI_COMMS_COMMAND_WRITE 0x04000000
806 #define MI_COMMS_ADDRESS_MASK 0x03e00000
807 #define MI_COMMS_ADDRESS_SHIFT 21
808 #define MI_COMMS_REGISTER_MASK 0x001f0000
809 #define MI_COMMS_REGISTER_SHIFT 16
810 #define MI_COMMS_DATA_MASK 0x0000ffff
811 #define MI_COMMS_DATA_SHIFT 0
812
813 #define MI_STATUS_REG 0x0450
814 #define MI_STATUS_10MBPS 0x00000002
815 #define MI_STATUS_LINK 0x00000001
816
817 #define MI_MODE_REG 0x0454
818 #define MI_MODE_CLOCK_MASK 0x001f0000
819 #define MI_MODE_AUTOPOLL 0x00000010
820 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002
821 #define MI_MODE_DEFAULT 0x000c0000
822
823 #define MI_AUTOPOLL_STATUS_REG 0x0458
824 #define MI_AUTOPOLL_ERROR 0x00000001
825
826 #define TRANSMIT_MAC_STATUS_REG 0x0460
827 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020
828 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010
829 #define TRANSMIT_STATUS_LINK_UP 0x00000008
830 #define TRANSMIT_STATUS_SENT_XON 0x00000004
831 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002
832 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001
833
834 #define RECEIVE_MAC_STATUS_REG 0x046c
835 #define RECEIVE_STATUS_RCVD_XON 0x00000004
836 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002
837 #define RECEIVE_STATUS_SENT_XOFF 0x00000001
838
839 /*
840 * These four-byte registers constitute a hash table for deciding
841 * whether to accept incoming multicast packets. The bits are
842 * numbered in big-endian fashion, from hash 0 => the MSB of
843 * register 0 to hash 127 => the LSB of the highest-numbered
844 * register.
845 *
846 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if
847 * enabled by setting the appropriate bit in the Rx MAC mode
848 * register. Otherwise, and on all earlier chips, the table
849 * is only 128 bits (registers 0-3).
850 */
851 #define MAC_HASH_0_REG 0x0470
852 #define MAC_HASH_1_REG 0x0474
853 #define MAC_HASH_2_REG 0x0478
854 #define MAC_HASH_3_REG 0x047c
855 #define MAC_HASH_4_REG 0x????
856 #define MAC_HASH_5_REG 0x????
857 #define MAC_HASH_6_REG 0x????
858 #define MAC_HASH_7_REG 0x????
859 #define MAC_HASH_REG(n) (0x470+4*(n))
860
861 /*
862 * Receive Rules Registers: 16 pairs of control+mask/value pairs
863 */
864 #define RCV_RULES_CONTROL_0_REG 0x0480
865 #define RCV_RULES_MASK_0_REG 0x0484
866 #define RCV_RULES_CONTROL_15_REG 0x04f8
867 #define RCV_RULES_MASK_15_REG 0x04fc
868 #define RCV_RULES_CONFIG_REG 0x0500
869 #define RCV_RULES_CONFIG_DEFAULT 0x00000008
870
871 #define RECV_RULES_NUM_MAX 16
872 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule))
873 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule))
874
875 #define RECV_RULE_CTL_ENABLE 0x80000000
876 #define RECV_RULE_CTL_AND 0x40000000
877 #define RECV_RULE_CTL_P1 0x20000000
878 #define RECV_RULE_CTL_P2 0x10000000
879 #define RECV_RULE_CTL_P3 0x08000000
880 #define RECV_RULE_CTL_MASK 0x04000000
881 #define RECV_RULE_CTL_DISCARD 0x02000000
882 #define RECV_RULE_CTL_MAP 0x01000000
883 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000
884 #define RECV_RULE_CTL_OP 0x00030000
885 #define RECV_RULE_CTL_OP_EQ 0x00000000
886 #define RECV_RULE_CTL_OP_NEQ 0x00010000
887 #define RECV_RULE_CTL_OP_GREAT 0x00020000
888 #define RECV_RULE_CTL_OP_LESS 0x00030000
889 #define RECV_RULE_CTL_HEADER 0x0000e000
890 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000
891 #define RECV_RULE_CTL_HEADER_IP 0x00002000
892 #define RECV_RULE_CTL_HEADER_TCP 0x00004000
893 #define RECV_RULE_CTL_HEADER_UDP 0x00006000
894 #define RECV_RULE_CTL_HEADER_DATA 0x00008000
895 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00
896 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \
897 RECV_RULE_CTL_CLASS_BITS)
898 #define RECV_RULE_CTL_OFFSET 0x000000ff
899
900 /*
901 * Receive Rules definition
902 */
903 #define ETHERHEADER_DEST_OFFSET 0x00
904 #define IPHEADER_PROTO_OFFSET 0x08
905 #define IPHEADER_SIP_OFFSET 0x0c
906 #define IPHEADER_DIP_OFFSET 0x10
907 #define TCPHEADER_SPORT_OFFSET 0x00
908 #define TCPHEADER_DPORT_OFFSET 0x02
909 #define UDPHEADER_SPORT_OFFSET 0x00
910 #define UDPHEADER_DPORT_OFFSET 0x02
911
912 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \
913 RECV_RULE_CTL_CLASS((ring)))
914
915 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK)
916
917 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \
918 RECV_RULE_CTL_HEADER_FRAME | \
919 ETHERHEADER_DEST_OFFSET)
920
921 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \
922 RECV_RULE_CTL_HEADER_FRAME | \
923 ETHERHEADER_DEST_OFFSET + 4)
924
925 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
926 IPHEADER_DIP_OFFSET)
927
928 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
929 IPHEADER_SIP_OFFSET)
930
931 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \
932 RECV_RULE_CTL_HEADER_IP | \
933 IPHEADER_PROTO_OFFSET)
934
935 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
936 RECV_RULE_CTL_HEADER_TCP | \
937 TCPHEADER_SPORT_OFFSET)
938
939 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
940 RECV_RULE_CTL_HEADER_TCP | \
941 TCPHEADER_DPORT_OFFSET)
942
943 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \
944 RECV_RULE_CTL_HEADER_UDP | \
945 UDPHEADER_SPORT_OFFSET)
946
947 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \
948 RECV_RULE_CTL_HEADER_UDP | \
949 UDPHEADER_DPORT_OFFSET)
950
951 /*
952 * 1000BaseX low-level access registers
953 */
954 #define MAC_GIGABIT_PCS_TEST_REG 0x0440
955 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000
956 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff
957 #define TX_1000BASEX_AUTONEG_REG 0x0444
958 #define RX_1000BASEX_AUTONEG_REG 0x0448
959
960 /*
961 * Autoneg code bits for the 1000BASE-X AUTONEG registers
962 */
963 #define AUTONEG_CODE_PAUSE 0x00008000
964 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000
965 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000
966 #define AUTONEG_CODE_NEXT_PAGE 0x00000080
967 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040
968 #define AUTONEG_CODE_FAULT_MASK 0x00000030
969 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030
970 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020
971 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010
972 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001
973
974 /*
975 * SerDes Registers (5703S/5704S only)
976 */
977 #define SERDES_CONTROL_REG 0x0590
978 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000
979 #define SERDES_CONTROL_COMMA_DETECT 0x00010000
980 #define SERDES_CONTROL_TX_DISABLE 0x00004000
981 #define SERDES_STATUS_REG 0x0594
982 #define SERDES_STATUS_COMMA_DETECTED 0x00000100
983 #define SERDES_STATUS_RXSTAT 0x000000ff
984
985 /*
986 * SGMII Status Register (5717/5718 only)
987 */
988 #define SGMII_STATUS_REG 0x5B4
989 #define MEDIA_SELECTION_MODE 0x00000100
990
991 /*
992 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only)
993 */
994 #define STAT_IFHCOUT_OCTETS_REG 0x0800
995 #define STAT_ETHER_COLLIS_REG 0x0808
996 #define STAT_OUTXON_SENT_REG 0x080c
997 #define STAT_OUTXOFF_SENT_REG 0x0810
998 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818
999 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c
1000 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820
1001 #define STAT_DOT3_DEFERED_TX_REG 0x0824
1002 #define STAT_DOT3_EXCE_COLLI_REG 0x082c
1003 #define STAT_DOT3_LATE_COLLI_REG 0x0830
1004 #define STAT_IFHCOUT_UPKGS_REG 0x086c
1005 #define STAT_IFHCOUT_MPKGS_REG 0x0870
1006 #define STAT_IFHCOUT_BPKGS_REG 0x0874
1007
1008 #define STAT_IFHCIN_OCTETS_REG 0x0880
1009 #define STAT_ETHER_FRAGMENT_REG 0x0888
1010 #define STAT_IFHCIN_UPKGS_REG 0x088c
1011 #define STAT_IFHCIN_MPKGS_REG 0x0890
1012 #define STAT_IFHCIN_BPKGS_REG 0x0894
1013
1014 #define STAT_DOT3_FCS_ERR_REG 0x0898
1015 #define STAT_DOT3_ALIGN_ERR_REG 0x089c
1016 #define STAT_XON_PAUSE_RX_REG 0x08a0
1017 #define STAT_XOFF_PAUSE_RX_REG 0x08a4
1018 #define STAT_MAC_CTRL_RX_REG 0x08a8
1019 #define STAT_XOFF_STATE_ENTER_REG 0x08ac
1020 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0
1021 #define STAT_ETHER_JABBERS_REG 0x08b4
1022 #define STAT_ETHER_UNDERSIZE_REG 0x08b8
1023 #define SIZE_OF_STATISTIC_REG 0x1B
1024 /*
1025 * Send Data Initiator Registers
1026 */
1027 #define SEND_INIT_STATS_CONTROL_REG 0x0c08
1028 #define SEND_INIT_STATS_ZERO 0x00000010
1029 #define SEND_INIT_STATS_FLUSH 0x00000008
1030 #define SEND_INIT_STATS_CLEAR 0x00000004
1031 #define SEND_INIT_STATS_FASTER 0x00000002
1032 #define SEND_INIT_STATS_ENABLE 0x00000001
1033
1034 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c
1035
1036 /*
1037 * Send Buffer Descriptor Selector Control Registers
1038 */
1039 #define SEND_BD_SELECTOR_STATUS_REG 0x1404
1040 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408
1041 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n))
1042
1043 /*
1044 * Receive List Placement Registers
1045 */
1046 #define RCV_LP_CONFIG_REG 0x2010
1047 #define RCV_LP_CONFIG_DEFAULT 0x00000009
1048 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1)
1049
1050 #define RCV_LP_STATS_CONTROL_REG 0x2014
1051 #define RCV_LP_STATS_ZERO 0x00000010
1052 #define RCV_LP_STATS_FLUSH 0x00000008
1053 #define RCV_LP_STATS_CLEAR 0x00000004
1054 #define RCV_LP_STATS_FASTER 0x00000002
1055 #define RCV_LP_STATS_ENABLE 0x00000001
1056
1057 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018
1058 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000
1059
1060 /*
1061 * Receive Data & BD Initiator Registers
1062 */
1063 #define RCV_INITIATOR_STATUS_REG 0x2404
1064
1065 /*
1066 * Receive Buffer Descriptor Ring Control Block Registers
1067 * NB: sixteen bytes (128 bits) each
1068 */
1069 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440
1070 #define STD_RCV_BD_RING_RCB_REG 0x2450
1071 #define MINI_RCV_BD_RING_RCB_REG 0x2460
1072
1073 /*
1074 * Receive Buffer Descriptor Ring Replenish Threshold Registers
1075 */
1076 #define MINI_RCV_BD_REPLENISH_REG 0x2c14
1077 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */
1078 #define STD_RCV_BD_REPLENISH_REG 0x2c18
1079 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */
1080 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c
1081 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */
1082
1083 /*
1084 * CPMU registers (5717/5718 only)
1085 */
1086 #define CPMU_STATUS_REG 0x362c
1087 #define CPMU_STATUS_FUN_NUM 0x20000000
1088
1089 /*
1090 * Host Coalescing Engine Control Registers
1091 */
1092 #define RCV_COALESCE_TICKS_REG 0x3c08
1093 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1094 #define SEND_COALESCE_TICKS_REG 0x3c0c
1095 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */
1096 #define RCV_COALESCE_MAX_BD_REG 0x3c10
1097 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1098 #define SEND_COALESCE_MAX_BD_REG 0x3c14
1099 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */
1100 #define RCV_COALESCE_INT_TICKS_REG 0x3c18
1101 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1102 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c
1103 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */
1104 #define RCV_COALESCE_INT_BD_REG 0x3c20
1105 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1106 #define SEND_COALESCE_INT_BD_REG 0x3c24
1107 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */
1108 #define STATISTICS_TICKS_REG 0x3c28
1109 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */
1110 #define STATISTICS_HOST_ADDR_REG 0x3c30
1111 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38
1112 #define STATISTICS_BASE_ADDR_REG 0x3c40
1113 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44
1114 #define FLOW_ATTN_REG 0x3c48
1115
1116 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50
1117 #define NIC_STD_RECV_INDEX_REG 0x3c54
1118 #define NIC_MINI_RECV_INDEX_REG 0x3c58
1119 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n))
1120 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n))
1121
1122 /*
1123 * Mbuf Pool Initialisation & Watermark Registers
1124 *
1125 * There are some conflicts in the PRM; compare the recommendations
1126 * on pp. 115, 236, and 339. The values here were recommended by
1127 * dkim@broadcom.com (and the PRM should be corrected soon ;-)
1128 */
1129 #define BUFFER_MANAGER_STATUS_REG 0x4404
1130 #define MBUF_POOL_BASE_REG 0x4408
1131 #define MBUF_POOL_BASE_DEFAULT 0x00008000
1132 #define MBUF_POOL_BASE_5721 0x00010000
1133 #define MBUF_POOL_BASE_5704 0x00010000
1134 #define MBUF_POOL_BASE_5705 0x00010000
1135 #define MBUF_POOL_LENGTH_REG 0x440c
1136 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000
1137 #define MBUF_POOL_LENGTH_5704 0x00010000
1138 #define MBUF_POOL_LENGTH_5705 0x00008000
1139 #define MBUF_POOL_LENGTH_5721 0x00008000
1140 #define RDMA_MBUF_LOWAT_REG 0x4410
1141 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050
1142 #define RDMA_MBUF_LOWAT_5705 0x00000000
1143 #define RDMA_MBUF_LOWAT_5906 0x00000000
1144 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130
1145 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000
1146 #define MAC_RX_MBUF_LOWAT_REG 0x4414
1147 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020
1148 #define MAC_RX_MBUF_LOWAT_5705 0x00000010
1149 #define MAC_RX_MBUF_LOWAT_5906 0x00000004
1150 #define MAC_RX_MBUF_LOWAT_5717 0x0000002a
1151 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098
1152 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b
1153 #define MBUF_HIWAT_REG 0x4418
1154 #define MBUF_HIWAT_DEFAULT 0x00000060
1155 #define MBUF_HIWAT_5705 0x00000060
1156 #define MBUF_HIWAT_5906 0x00000010
1157 #define MBUF_HIWAT_5717 0x000000a0
1158 #define MBUF_HIWAT_JUMBO 0x0000017c
1159 #define MBUF_HIWAT_5714_JUMBO 0x00000096
1160
1161 /*
1162 * DMA Descriptor Pool Initialisation & Watermark Registers
1163 */
1164 #define DMAD_POOL_BASE_REG 0x442c
1165 #define DMAD_POOL_BASE_DEFAULT 0x00002000
1166 #define DMAD_POOL_LENGTH_REG 0x4430
1167 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000
1168 #define DMAD_POOL_LOWAT_REG 0x4434
1169 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */
1170 #define DMAD_POOL_HIWAT_REG 0x4438
1171 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */
1172
1173 /*
1174 * More threshold/watermark registers ...
1175 */
1176 #define RECV_FLOW_THRESHOLD_REG 0x4458
1177 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504
1178 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002
1179
1180 /*
1181 * Read/Write DMA Status Registers
1182 */
1183 #define READ_DMA_STATUS_REG 0x4804
1184 #define WRITE_DMA_STATUS_REG 0x4c04
1185
1186 /*
1187 * RX/TX RISC Registers
1188 */
1189 #define RX_RISC_MODE_REG 0x5000
1190 #define RX_RISC_STATE_REG 0x5004
1191 #define RX_RISC_PC_REG 0x501c
1192 #define TX_RISC_MODE_REG 0x5400
1193 #define TX_RISC_STATE_REG 0x5404
1194 #define TX_RISC_PC_REG 0x541c
1195
1196 /*
1197 * V? RISC Registerss
1198 */
1199 #define VCPU_STATUS_REG 0x5100
1200 #define VCPU_INIT_DONE 0x04000000
1201 #define VCPU_DRV_RESET 0x08000000
1202
1203 #define VCPU_EXT_CTL 0x6890
1204 #define VCPU_EXT_CTL_HALF 0x00400000
1205
1206 #define FTQ_RESET_REG 0x5c00
1207
1208 #define MSI_MODE_REG 0x6000
1209 #define MSI_PRI_HIGHEST 0xc0000000
1210 #define MSI_MSI_ENABLE 0x00000002
1211 #define MSI_ERROR_ATTENTION 0x0000001c
1212
1213 #define MSI_STATUS_REG 0x6004
1214
1215 #define MODE_CONTROL_REG 0x6800
1216 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000
1217 #define MODE_4X_NIC_SEND_RINGS 0x20000000
1218 #define MODE_INT_ON_FLOW_ATTN 0x10000000
1219 #define MODE_INT_ON_DMA_ATTN 0x08000000
1220 #define MODE_INT_ON_MAC_ATTN 0x04000000
1221 #define MODE_INT_ON_RXRISC_ATTN 0x02000000
1222 #define MODE_INT_ON_TXRISC_ATTN 0x01000000
1223 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000
1224 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000
1225 #define MODE_HOST_SEND_BDS 0x00020000
1226 #define MODE_HOST_STACK_UP 0x00010000
1227 #define MODE_FORCE_32_BIT_PCI 0x00008000
1228 #define MODE_NO_INT_ON_RECV 0x00004000
1229 #define MODE_NO_INT_ON_SEND 0x00002000
1230 #define MODE_ALLOW_BAD_FRAMES 0x00000800
1231 #define MODE_NO_CRC 0x00000400
1232 #define MODE_NO_FRAME_CRACKING 0x00000200
1233 #define MODE_WORD_SWAP_FRAME 0x00000020
1234 #define MODE_BYTE_SWAP_FRAME 0x00000010
1235 #define MODE_WORD_SWAP_NONFRAME 0x00000004
1236 #define MODE_BYTE_SWAP_NONFRAME 0x00000002
1237 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001
1238
1239 /*
1240 * Miscellaneous Configuration Register
1241 *
1242 * This contains various bits relating to power control (which differ
1243 * among different members of the chip family), but the important bits
1244 * for our purposes are the RESET bit and the Timer Prescaler field.
1245 *
1246 * The RESET bit in this register serves to reset the whole chip, even
1247 * including the PCI interface(!) Once it's set, the chip will not
1248 * respond to ANY accesses -- not even CONFIG space -- until the reset
1249 * completes internally. According to the PRM, this should take less
1250 * than 100us. Any access during this period will get a bus error.
1251 *
1252 * The Timer Prescaler field must be programmed so that the timer period
1253 * is as near as possible to 1us. The value in this field should be
1254 * the Core Clock frequency in MHz minus 1. From my reading of the PRM,
1255 * the Core Clock should always be 66MHz (independently of the bus speed,
1256 * at least for PCI rather than PCI-X), so this register must be set to
1257 * the value 0x82 ((66-1) << 1).
1258 */
1259 #define CORE_CLOCK_MHZ 66
1260 #define MISC_CONFIG_REG 0x6804
1261 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000
1262 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
1263 #define MISC_CONFIG_POWERDOWN 0x00100000
1264 #define MISC_CONFIG_POWER_STATE 0x00060000
1265 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe
1266 #define MISC_CONFIG_RESET_BIT 0x00000001
1267 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1)
1268 #define MISC_CONFIG_EPHY_IDDQ 0x00200000
1269
1270 /*
1271 * Miscellaneous Local Control Register (MLCR)
1272 */
1273 #define MISC_LOCAL_CONTROL_REG 0x6808
1274 #define MLCR_PCI_CTRL_SELECT 0x10000000
1275 #define MLCR_LEGACY_PCI_MODE 0x08000000
1276 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000
1277 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000
1278 #define MLCR_SSRAM_TYPE 0x00400000
1279 #define MLCR_BANK_SELECT 0x00200000
1280 #define MLCR_SRAM_SIZE_MASK 0x001c0000
1281 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000
1282
1283 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000
1284 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000
1285 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000
1286 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000
1287 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000
1288 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800
1289 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */
1290 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */
1291 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */
1292
1293 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */
1294 #define MLCR_SET_INT 0x00000004 /* W/O */
1295 #define MLCR_CLR_INT 0x00000002 /* W/O */
1296 #define MLCR_INTA_STATE 0x00000001 /* R/O */
1297
1298 /*
1299 * This value defines all GPIO bits as INPUTS, but sets their default
1300 * values as outputs to HIGH, on the assumption that external circuits
1301 * (if any) will probably be active-LOW with passive pullups.
1302 *
1303 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in
1304 * just this fashion. It has to be set as an OUTPUT and driven LOW to
1305 * enable writing. Otherwise, the SEEPROM is protected.
1306 */
1307 #define MLCR_DEFAULT 0x0101c000
1308 #define MLCR_DEFAULT_5714 0x1901c000
1309 #define MLCR_DEFAULT_5717 0x01000000
1310
1311 /*
1312 * Serial EEPROM Data/Address Registers (auto-access mode)
1313 */
1314 #define SERIAL_EEPROM_DATA_REG 0x683c
1315 #define SERIAL_EEPROM_ADDRESS_REG 0x6838
1316 #define SEEPROM_ACCESS_READ 0x80000000
1317 #define SEEPROM_ACCESS_WRITE 0x00000000
1318 #define SEEPROM_ACCESS_COMPLETE 0x40000000
1319 #define SEEPROM_ACCESS_RESET 0x20000000
1320 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000
1321 #define SEEPROM_ACCESS_START 0x02000000
1322 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000
1323 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc
1324
1325 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */
1326 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */
1327 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */
1328
1329 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */
1330 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */
1331
1332 /*
1333 * "Linearised" address mask, treating multiple devices as consecutive
1334 */
1335 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */
1336
1337 /*
1338 * Non-Volatile Memory Interface Registers
1339 * Note: on chips that support the flash interface (5702+), flash is the
1340 * default and the legacy seeprom interface must be explicitly enabled
1341 * if required. On older chips (5700/01), SEEPROM is the default (and
1342 * only) non-volatile memory available, and these registers don't exist!
1343 */
1344 #define NVM_FLASH_CMD_REG 0x7000
1345 #define NVM_FLASH_CMD_LAST 0x00000100
1346 #define NVM_FLASH_CMD_FIRST 0x00000080
1347 #define NVM_FLASH_CMD_RD 0x00000000
1348 #define NVM_FLASH_CMD_WR 0x00000020
1349 #define NVM_FLASH_CMD_DOIT 0x00000010
1350 #define NVM_FLASH_CMD_DONE 0x00000008
1351
1352 #define NVM_FLASH_WRITE_REG 0x7008
1353 #define NVM_FLASH_READ_REG 0x7010
1354
1355 #define NVM_FLASH_ADDR_REG 0x700c
1356 #define NVM_FLASH_ADDR_MASK 0x00fffffc
1357
1358 #define NVM_CONFIG1_REG 0x7014
1359 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000
1360 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800
1361 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780
1362 #define NVM_CFG1_BUFFERED_MODE 0x00000002
1363 #define NVM_CFG1_FLASH_MODE 0x00000001
1364
1365 #define NVM_SW_ARBITRATION_REG 0x7020
1366 #define NVM_READ_REQ3 0X00008000
1367 #define NVM_READ_REQ2 0X00004000
1368 #define NVM_READ_REQ1 0X00002000
1369 #define NVM_READ_REQ0 0X00001000
1370 #define NVM_WON_REQ3 0X00000800
1371 #define NVM_WON_REQ2 0X00000400
1372 #define NVM_WON_REQ1 0X00000200
1373 #define NVM_WON_REQ0 0X00000100
1374 #define NVM_RESET_REQ3 0X00000080
1375 #define NVM_RESET_REQ2 0X00000040
1376 #define NVM_RESET_REQ1 0X00000020
1377 #define NVM_RESET_REQ0 0X00000010
1378 #define NVM_SET_REQ3 0X00000008
1379 #define NVM_SET_REQ2 0X00000004
1380 #define NVM_SET_REQ1 0X00000002
1381 #define NVM_SET_REQ0 0X00000001
1382
1383 /*
1384 * NVM access register
1385 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714
1386 * and BCM5715 only.
1387 */
1388 #define NVM_ACCESS_REG 0X7024
1389 #define NVM_WRITE_ENABLE 0X00000002
1390 #define NVM_ACCESS_ENABLE 0X00000001
1391
1392 /*
1393 * TLP Control Register
1394 * Applicable to BCM5721 and BCM5751 only
1395 */
1396 #define TLP_CONTROL_REG 0x7c00
1397 #define TLP_DATA_FIFO_PROTECT 0x02000000
1398
1399 /*
1400 * PHY Test Control Register
1401 * Applicable to BCM5721 and BCM5751 only
1402 */
1403 #define PHY_TEST_CTRL_REG 0x7e2c
1404 #define PHY_PCIE_SCRAM_MODE 0x20
1405 #define PHY_PCIE_LTASS_MODE 0x40
1406
1407 /*
1408 * The internal firmware expects a certain layout of the non-volatile
1409 * memory (if fitted), and will check for it during startup, and use the
1410 * contents to initialise various internal parameters if it looks good.
1411 *
1412 * The offsets and field definitions below refer to where to find some
1413 * important values, and how to interpret them ...
1414 */
1415 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */
1416 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */
1417
1418 /*
1419 * Vendor-specific MII registers
1420 */
1421 #define MII_EXT_CONTROL MII_VENDOR(0)
1422 #define MII_EXT_STATUS MII_VENDOR(1)
1423 #define MII_RCV_ERR_COUNT MII_VENDOR(2)
1424 #define MII_FALSE_CARR_COUNT MII_VENDOR(3)
1425 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4)
1426 #define MII_AUX_CONTROL MII_VENDOR(8)
1427 #define MII_AUX_STATUS MII_VENDOR(9)
1428 #define MII_INTR_STATUS MII_VENDOR(10)
1429 #define MII_INTR_MASK MII_VENDOR(11)
1430 #define MII_HCD_STATUS MII_VENDOR(13)
1431
1432 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */
1433
1434 /*
1435 * Bits in the MII_EXT_CONTROL register
1436 */
1437 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000
1438 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000
1439 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000
1440 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000
1441 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800
1442 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400
1443 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200
1444 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100
1445 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080
1446 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040
1447 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020
1448 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010
1449 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008
1450 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004
1451 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002
1452 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001
1453
1454 /*
1455 * Bits in the MII_EXT_STATUS register
1456 */
1457 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000
1458 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000
1459 #define MII_EXT_STAT_MDIX_STATE 0x2000
1460 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000
1461 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800
1462 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400
1463 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200
1464 #define MII_EXT_STAT_LINK_STATUS 0x0100
1465 #define MII_EXT_STAT_CRC_ERROR 0x0080
1466 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040
1467 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020
1468 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010
1469 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008
1470 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004
1471 #define MII_EXT_STAT_LOCK_ERROR 0x0002
1472 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001
1473
1474 /*
1475 * The AUX CONTROL register is seriously weird!
1476 *
1477 * It hides (up to) eight 'shadow' registers. When writing, which one
1478 * of them is written is determined by the low-order bits of the data
1479 * written(!), but when reading, which one is read is determined by the
1480 * value previously written to (part of) one of the shadow registers!!!
1481 */
1482
1483 /*
1484 * Shadow register numbers
1485 */
1486 #define MII_AUX_CTRL_NORMAL 0
1487 #define MII_AUX_CTRL_10BASE_T 1
1488 #define MII_AUX_CTRL_POWER 2
1489 #define MII_AUX_CTRL_TEST_1 4
1490 #define MII_AUX_CTRL_MISC 7
1491
1492 /*
1493 * Selected bits in some of the shadow registers ...
1494 */
1495 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000
1496 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000
1497 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000
1498 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400
1499 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008
1500
1501 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008
1502
1503 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000
1504 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010
1505
1506 /*
1507 * Write this value to the AUX control register
1508 * to select which shadow register will be read
1509 */
1510 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC)
1511
1512 /*
1513 * Bits in the MII_AUX_STATUS register
1514 */
1515 #define MII_AUX_STATUS_MODE_MASK 0x0700
1516 #define MII_AUX_STATUS_MODE_1000_F 0x0700
1517 #define MII_AUX_STATUS_MODE_1000_H 0x0600
1518 #define MII_AUX_STATUS_MODE_100_F 0x0500
1519 #define MII_AUX_STATUS_MODE_100_4 0x0400
1520 #define MII_AUX_STATUS_MODE_100_H 0x0300
1521 #define MII_AUX_STATUS_MODE_10_F 0x0200
1522 #define MII_AUX_STATUS_MODE_10_H 0x0100
1523 #define MII_AUX_STATUS_MODE_NONE 0x0000
1524 #define MII_AUX_STATUS_MODE_SHIFT 8
1525
1526 #define MII_AUX_STATUS_PAR_FAULT 0x0080
1527 #define MII_AUX_STATUS_REM_FAULT 0x0040
1528 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010
1529 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008
1530
1531 #define MII_AUX_STATUS_LINKUP 0x0004
1532 #define MII_AUX_STATUS_RX_PAUSE 0x0002
1533 #define MII_AUX_STATUS_TX_PAUSE 0x0001
1534
1535 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008
1536 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002
1537 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001
1538
1539 /*
1540 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers
1541 */
1542 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020
1543 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010
1544 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008
1545 #define MII_INTR_LINK_SPEED_CHANGE 0x0004
1546 #define MII_INTR_LINK_STATUS_CHANGE 0x0002
1547
1548
1549 /*
1550 * Third section:
1551 * Hardware-defined data structures
1552 *
1553 * Note that the chip is naturally BIG-endian, so, for a big-endian
1554 * host, the structures defined below match those described in the PRM.
1555 * For little-endian hosts, some structures have to be swapped around.
1556 */
1557
1558 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
1559 #error Host endianness not defined
1560 #endif
1561
1562 /*
1563 * Architectural constants: absolute maximum numbers of each type of ring
1564 */
1565 #ifdef BGE_EXT_MEM
1566 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */
1567 #else
1568 #define BGE_SEND_RINGS_MAX 4
1569 #endif
1570 #define BGE_SEND_RINGS_MAX_5705 1
1571 #define BGE_RECV_RINGS_MAX 16
1572 #define BGE_RECV_RINGS_MAX_5705 1
1573 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */
1574 /* only with ext mem) */
1575
1576 #define BGE_SEND_SLOTS_MAX 512
1577 #define BGE_STD_SLOTS_MAX 512
1578 #define BGE_JUMBO_SLOTS_MAX 256
1579 #define BGE_MINI_SLOTS_MAX 1024
1580 #define BGE_RECV_SLOTS_MAX 2048
1581 #define BGE_RECV_SLOTS_5705 512
1582 #define BGE_RECV_SLOTS_5782 512
1583 #define BGE_RECV_SLOTS_5721 512
1584
1585 /*
1586 * Hardware-defined Ring Control Block
1587 */
1588 typedef struct {
1589 uint64_t host_ring_addr;
1590 #ifdef _BIG_ENDIAN
1591 uint16_t max_len;
1592 uint16_t flags;
1593 uint32_t nic_ring_addr;
1594 #else
1595 uint32_t nic_ring_addr;
1596 uint16_t flags;
1597 uint16_t max_len;
1598 #endif /* _BIG_ENDIAN */
1599 } bge_rcb_t;
1600
1601 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001
1602 #define RCB_FLAG_RING_DISABLED 0x0002
1603
1604 /*
1605 * Hardware-defined Send Buffer Descriptor
1606 */
1607 typedef struct {
1608 uint64_t host_buf_addr;
1609 #ifdef _BIG_ENDIAN
1610 uint16_t len;
1611 uint16_t flags;
1612 uint16_t reserved;
1613 uint16_t vlan_tci;
1614 #else
1615 uint16_t vlan_tci;
1616 uint16_t reserved;
1617 uint16_t flags;
1618 uint16_t len;
1619 #endif /* _BIG_ENDIAN */
1620 } bge_sbd_t;
1621
1622 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001
1623 #define SBD_FLAG_IP_CKSUM 0x0002
1624 #define SBD_FLAG_PACKET_END 0x0004
1625 #define SBD_FLAG_IP_FRAG 0x0008
1626 #define SBD_FLAG_IP_FRAG_END 0x0010
1627
1628 #define SBD_FLAG_VLAN_TAG 0x0040
1629 #define SBD_FLAG_COAL_NOW 0x0080
1630 #define SBD_FLAG_CPU_PRE_DMA 0x0100
1631 #define SBD_FLAG_CPU_POST_DMA 0x0200
1632
1633 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000
1634 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000
1635 #define SBD_FLAG_DONT_GEN_CRC 0x8000
1636
1637 /*
1638 * Hardware-defined Receive Buffer Descriptor
1639 */
1640 typedef struct {
1641 uint64_t host_buf_addr;
1642 #ifdef _BIG_ENDIAN
1643 uint16_t index;
1644 uint16_t len;
1645 uint16_t type;
1646 uint16_t flags;
1647 uint16_t ip_cksum;
1648 uint16_t tcp_udp_cksum;
1649 uint16_t error_flag;
1650 uint16_t vlan_tci;
1651 uint32_t reserved;
1652 uint32_t opaque;
1653 #else
1654 uint16_t flags;
1655 uint16_t type;
1656 uint16_t len;
1657 uint16_t index;
1658 uint16_t vlan_tci;
1659 uint16_t error_flag;
1660 uint16_t tcp_udp_cksum;
1661 uint16_t ip_cksum;
1662 uint32_t opaque;
1663 uint32_t reserved;
1664 #endif /* _BIG_ENDIAN */
1665 } bge_rbd_t;
1666
1667 #define RBD_FLAG_STD_RING 0x0000
1668 #define RBD_FLAG_PACKET_END 0x0004
1669
1670 #define RBD_FLAG_JUMBO_RING 0x0020
1671 #define RBD_FLAG_VLAN_TAG 0x0040
1672
1673 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400
1674 #define RBD_FLAG_MINI_RING 0x0800
1675 #define RBD_FLAG_IP_CHECKSUM 0x1000
1676 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000
1677 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000
1678
1679 #define RBD_FLAG_DEFAULT 0x0000
1680
1681 #define RBD_ERROR_BAD_CRC 0x00010000
1682 #define RBD_ERROR_COLL_DETECT 0x00020000
1683 #define RBD_ERROR_LINK_LOST 0x00040000
1684 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000
1685 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000
1686 #define RBD_ERROR_MAC_ABORT 0x00200000
1687 #define RBD_ERROR_LEN_LESS_64 0x00400000
1688 #define RBD_ERROR_TRUNC_NO_RES 0x00800000
1689 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000
1690
1691 /*
1692 * Hardware-defined Status Block,Size of status block
1693 * is actually 0x50 bytes.Use 0x80 bytes for cache line
1694 * alignment.For BCM5705/5788/5721/5751/5752/5714
1695 * and 5715,there is only 1 recv and send ring index,but
1696 * driver defined 16 indexs here,please pay attention only
1697 * one ring is enabled in these chipsets.
1698 */
1699 typedef struct {
1700 uint64_t flags_n_tag;
1701 uint16_t buff_cons_index[4];
1702 struct {
1703 #ifdef _BIG_ENDIAN
1704 uint16_t send_cons_index;
1705 uint16_t recv_prod_index;
1706 #else
1707 uint16_t recv_prod_index;
1708 uint16_t send_cons_index;
1709 #endif /* _BIG_ENDIAN */
1710 } index[16];
1711 } bge_status_t;
1712
1713 /*
1714 * Hardware-defined Receive BD Rule
1715 */
1716 typedef struct {
1717 uint32_t control;
1718 uint32_t mask_value;
1719 } bge_recv_rule_t;
1720
1721 /*
1722 * This describes which sub-rule slots are used by a particular rule.
1723 */
1724 typedef struct {
1725 int start;
1726 int count;
1727 } bge_rule_info_t;
1728
1729 /*
1730 * Indexes into the <buff_cons_index> array
1731 */
1732 #ifdef _BIG_ENDIAN
1733 #define STATUS_STD_BUFF_CONS_INDEX 0
1734 #define STATUS_JUMBO_BUFF_CONS_INDEX 1
1735 #define STATUS_MINI_BUFF_CONS_INDEX 3
1736 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index)
1737 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index)
1738 #else
1739 #define STATUS_STD_BUFF_CONS_INDEX 3
1740 #define STATUS_JUMBO_BUFF_CONS_INDEX 2
1741 #define STATUS_MINI_BUFF_CONS_INDEX 0
1742 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index)
1743 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index)
1744 #endif /* _BIG_ENDIAN */
1745
1746 /*
1747 * Bits in the <flags_n_tag> word
1748 */
1749 #define STATUS_FLAG_UPDATED 0x0000000100000000ull
1750 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull
1751 #define STATUS_FLAG_ERROR 0x0000000400000000ull
1752 #define STATUS_TAG_MASK 0x00000000000000FFull
1753
1754 /*
1755 * The tag from the status block is fed back to Interrupt Mailbox 0
1756 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This
1757 * lets the chip know what updates have been processed, so it can
1758 * reassert its interrupt if more updates have occurred since.
1759 *
1760 * These macros extract the tag from the <flags_n_tag> word, shift
1761 * it to the proper position in the Mailbox register, and provide
1762 * the complete values to write to INTERRUPT_MBOX_0_REG to disable
1763 * or enable interrupts
1764 */
1765 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK)
1766 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24)
1767 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1)
1768 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0)
1769
1770 /*
1771 * Hardware-defined Statistics Block Offsets
1772 *
1773 * These are given in the manual as addresses in NIC memory, starting
1774 * from the NIC statistics area base address of 0x300; but here we
1775 * convert them into indexes into an array of (uint64_t)s, so we can
1776 * use them directly for accessing the copy of the statistics block
1777 * that the chip DMAs into main memory ...
1778 */
1779
1780 #define KS_BASE 0x300
1781 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t))
1782
1783 typedef enum {
1784 KS_ifHCInOctets = KS_ADDR(0x400),
1785 KS_etherStatsFragments = KS_ADDR(0x410),
1786 KS_ifHCInUcastPkts,
1787 KS_ifHCInMulticastPkts,
1788 KS_ifHCInBroadcastPkts,
1789 KS_dot3StatsFCSErrors,
1790 KS_dot3StatsAlignmentErrors,
1791 KS_xonPauseFramesReceived,
1792 KS_xoffPauseFramesReceived,
1793 KS_macControlFramesReceived,
1794 KS_xoffStateEntered,
1795 KS_dot3StatsFrameTooLongs,
1796 KS_etherStatsJabbers,
1797 KS_etherStatsUndersizePkts,
1798 KS_inRangeLengthError,
1799 KS_outRangeLengthError,
1800 KS_etherStatsPkts64Octets,
1801 KS_etherStatsPkts65to127Octets,
1802 KS_etherStatsPkts128to255Octets,
1803 KS_etherStatsPkts256to511Octets,
1804 KS_etherStatsPkts512to1023Octets,
1805 KS_etherStatsPkts1024to1518Octets,
1806 KS_etherStatsPkts1519to2047Octets,
1807 KS_etherStatsPkts2048to4095Octets,
1808 KS_etherStatsPkts4096to8191Octets,
1809 KS_etherStatsPkts8192to9022Octets,
1810
1811 KS_ifHCOutOctets = KS_ADDR(0x600),
1812 KS_etherStatsCollisions = KS_ADDR(0x610),
1813 KS_outXonSent,
1814 KS_outXoffSent,
1815 KS_flowControlDone,
1816 KS_dot3StatsInternalMacTransmitErrors,
1817 KS_dot3StatsSingleCollisionFrames,
1818 KS_dot3StatsMultipleCollisionFrames,
1819 KS_dot3StatsDeferredTransmissions,
1820 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658),
1821 KS_dot3StatsLateCollisions,
1822 KS_dot3Collided2Times,
1823 KS_dot3Collided3Times,
1824 KS_dot3Collided4Times,
1825 KS_dot3Collided5Times,
1826 KS_dot3Collided6Times,
1827 KS_dot3Collided7Times,
1828 KS_dot3Collided8Times,
1829 KS_dot3Collided9Times,
1830 KS_dot3Collided10Times,
1831 KS_dot3Collided11Times,
1832 KS_dot3Collided12Times,
1833 KS_dot3Collided13Times,
1834 KS_dot3Collided14Times,
1835 KS_dot3Collided15Times,
1836 KS_ifHCOutUcastPkts,
1837 KS_ifHCOutMulticastPkts,
1838 KS_ifHCOutBroadcastPkts,
1839 KS_dot3StatsCarrierSenseErrors,
1840 KS_ifOutDiscards,
1841 KS_ifOutErrors,
1842
1843 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */
1844 KS_COSIfHCInPkts_2,
1845 KS_COSIfHCInPkts_3,
1846 KS_COSIfHCInPkts_4,
1847 KS_COSIfHCInPkts_5,
1848 KS_COSIfHCInPkts_6,
1849 KS_COSIfHCInPkts_7,
1850 KS_COSIfHCInPkts_8,
1851 KS_COSIfHCInPkts_9,
1852 KS_COSIfHCInPkts_10,
1853 KS_COSIfHCInPkts_11,
1854 KS_COSIfHCInPkts_12,
1855 KS_COSIfHCInPkts_13,
1856 KS_COSIfHCInPkts_14,
1857 KS_COSIfHCInPkts_15,
1858 KS_COSIfHCInPkts_16,
1859 KS_COSFramesDroppedDueToFilters,
1860 KS_nicDmaWriteQueueFull,
1861 KS_nicDmaWriteHighPriQueueFull,
1862 KS_nicNoMoreRxBDs,
1863 KS_ifInDiscards,
1864 KS_ifInErrors,
1865 KS_nicRecvThresholdHit,
1866
1867 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */
1868 KS_COSIfHCOutPkts_2,
1869 KS_COSIfHCOutPkts_3,
1870 KS_COSIfHCOutPkts_4,
1871 KS_COSIfHCOutPkts_5,
1872 KS_COSIfHCOutPkts_6,
1873 KS_COSIfHCOutPkts_7,
1874 KS_COSIfHCOutPkts_8,
1875 KS_COSIfHCOutPkts_9,
1876 KS_COSIfHCOutPkts_10,
1877 KS_COSIfHCOutPkts_11,
1878 KS_COSIfHCOutPkts_12,
1879 KS_COSIfHCOutPkts_13,
1880 KS_COSIfHCOutPkts_14,
1881 KS_COSIfHCOutPkts_15,
1882 KS_COSIfHCOutPkts_16,
1883 KS_nicDmaReadQueueFull,
1884 KS_nicDmaReadHighPriQueueFull,
1885 KS_nicSendDataCompQueueFull,
1886 KS_nicRingSetSendProdIndex,
1887 KS_nicRingStatusUpdate,
1888 KS_nicInterrupts,
1889 KS_nicAvoidedInterrupts,
1890 KS_nicSendThresholdHit,
1891
1892 KS_STATS_SIZE = KS_ADDR(0xb00)
1893 } bge_stats_offset_t;
1894
1895 /*
1896 * Hardware-defined Statistics Block
1897 *
1898 * Another view of the statistic block, as a array and a structure ...
1899 */
1900
1901 typedef union {
1902 uint64_t a[KS_STATS_SIZE];
1903 struct {
1904 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)];
1905
1906 uint64_t ifHCInOctets; /* 0x0400 */
1907 uint64_t spare2[1];
1908 uint64_t etherStatsFragments;
1909 uint64_t ifHCInUcastPkts;
1910 uint64_t ifHCInMulticastPkts;
1911 uint64_t ifHCInBroadcastPkts;
1912 uint64_t dot3StatsFCSErrors;
1913 uint64_t dot3StatsAlignmentErrors;
1914 uint64_t xonPauseFramesReceived;
1915 uint64_t xoffPauseFramesReceived;
1916 uint64_t macControlFramesReceived;
1917 uint64_t xoffStateEntered;
1918 uint64_t dot3StatsFrameTooLongs;
1919 uint64_t etherStatsJabbers;
1920 uint64_t etherStatsUndersizePkts;
1921 uint64_t inRangeLengthError;
1922 uint64_t outRangeLengthError;
1923 uint64_t etherStatsPkts64Octets;
1924 uint64_t etherStatsPkts65to127Octets;
1925 uint64_t etherStatsPkts128to255Octets;
1926 uint64_t etherStatsPkts256to511Octets;
1927 uint64_t etherStatsPkts512to1023Octets;
1928 uint64_t etherStatsPkts1024to1518Octets;
1929 uint64_t etherStatsPkts1519to2047Octets;
1930 uint64_t etherStatsPkts2048to4095Octets;
1931 uint64_t etherStatsPkts4096to8191Octets;
1932 uint64_t etherStatsPkts8192to9022Octets;
1933 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)];
1934
1935 uint64_t ifHCOutOctets; /* 0x0600 */
1936 uint64_t spare4[1];
1937 uint64_t etherStatsCollisions;
1938 uint64_t outXonSent;
1939 uint64_t outXoffSent;
1940 uint64_t flowControlDone;
1941 uint64_t dot3StatsInternalMacTransmitErrors;
1942 uint64_t dot3StatsSingleCollisionFrames;
1943 uint64_t dot3StatsMultipleCollisionFrames;
1944 uint64_t dot3StatsDeferredTransmissions;
1945 uint64_t spare5[1];
1946 uint64_t dot3StatsExcessiveCollisions;
1947 uint64_t dot3StatsLateCollisions;
1948 uint64_t dot3Collided2Times;
1949 uint64_t dot3Collided3Times;
1950 uint64_t dot3Collided4Times;
1951 uint64_t dot3Collided5Times;
1952 uint64_t dot3Collided6Times;
1953 uint64_t dot3Collided7Times;
1954 uint64_t dot3Collided8Times;
1955 uint64_t dot3Collided9Times;
1956 uint64_t dot3Collided10Times;
1957 uint64_t dot3Collided11Times;
1958 uint64_t dot3Collided12Times;
1959 uint64_t dot3Collided13Times;
1960 uint64_t dot3Collided14Times;
1961 uint64_t dot3Collided15Times;
1962 uint64_t ifHCOutUcastPkts;
1963 uint64_t ifHCOutMulticastPkts;
1964 uint64_t ifHCOutBroadcastPkts;
1965 uint64_t dot3StatsCarrierSenseErrors;
1966 uint64_t ifOutDiscards;
1967 uint64_t ifOutErrors;
1968 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)];
1969
1970 uint64_t COSIfHCInPkts[16]; /* 0x0800 */
1971 uint64_t COSFramesDroppedDueToFilters;
1972 uint64_t nicDmaWriteQueueFull;
1973 uint64_t nicDmaWriteHighPriQueueFull;
1974 uint64_t nicNoMoreRxBDs;
1975 uint64_t ifInDiscards;
1976 uint64_t ifInErrors;
1977 uint64_t nicRecvThresholdHit;
1978 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)];
1979
1980 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */
1981 uint64_t nicDmaReadQueueFull;
1982 uint64_t nicDmaReadHighPriQueueFull;
1983 uint64_t nicSendDataCompQueueFull;
1984 uint64_t nicRingSetSendProdIndex;
1985 uint64_t nicRingStatusUpdate;
1986 uint64_t nicInterrupts;
1987 uint64_t nicAvoidedInterrupts;
1988 uint64_t nicSendThresholdHit;
1989 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)];
1990 } s;
1991 } bge_statistics_t;
1992
1993 #define KS_STAT_REG_SIZE (0x1B)
1994 #define KS_STAT_REG_BASE (0x800)
1995
1996 typedef struct {
1997 uint32_t ifHCOutOctets;
1998 uint32_t etherStatsCollisions;
1999 uint32_t outXonSent;
2000 uint32_t outXoffSent;
2001 uint32_t dot3StatsInternalMacTransmitErrors;
2002 uint32_t dot3StatsSingleCollisionFrames;
2003 uint32_t dot3StatsMultipleCollisionFrames;
2004 uint32_t dot3StatsDeferredTransmissions;
2005 uint32_t dot3StatsExcessiveCollisions;
2006 uint32_t dot3StatsLateCollisions;
2007 uint32_t ifHCOutUcastPkts;
2008 uint32_t ifHCOutMulticastPkts;
2009 uint32_t ifHCOutBroadcastPkts;
2010 uint32_t ifHCInOctets;
2011 uint32_t etherStatsFragments;
2012 uint32_t ifHCInUcastPkts;
2013 uint32_t ifHCInMulticastPkts;
2014 uint32_t ifHCInBroadcastPkts;
2015 uint32_t dot3StatsFCSErrors;
2016 uint32_t dot3StatsAlignmentErrors;
2017 uint32_t xonPauseFramesReceived;
2018 uint32_t xoffPauseFramesReceived;
2019 uint32_t macControlFramesReceived;
2020 uint32_t xoffStateEntered;
2021 uint32_t dot3StatsFrameTooLongs;
2022 uint32_t etherStatsJabbers;
2023 uint32_t etherStatsUndersizePkts;
2024 } bge_statistics_reg_t;
2025
2026
2027 #ifdef BGE_IPMI_ASF
2028
2029 /*
2030 * Device internal memory entries
2031 */
2032
2033 #define BGE_FIRMWARE_MAILBOX 0x0b50
2034 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654
2035 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
2036
2037
2038 #define BGE_NIC_DATA_SIG_ADDR 0x0b54
2039 #define BGE_NIC_DATA_SIG 0x4b657654
2040
2041
2042 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58
2043
2044 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004
2045 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008
2046 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004
2047 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008
2048 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c
2049
2050 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000
2051 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010
2052 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020
2053 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030
2054
2055 #define BGE_NIC_CFG_ENABLE_WOL 0x000040
2056 #define BGE_NIC_CFG_ENABLE_ASF 0x000080
2057 #define BGE_NIC_CFG_EEPROM_WP 0x000100
2058 #define BGE_NIC_CFG_POWER_SAVING 0x000200
2059 #define BGE_NIC_CFG_SWAP_PORT 0x000800
2060 #define BGE_NIC_CFG_MINI_PCI 0x001000
2061 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000
2062 #define BGE_NIC_CFG_5753_12x12 0x100000
2063
2064
2065 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c
2066
2067
2068 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74
2069 #define BGE_NIC_PHY_ID1_MASK 0xffff0000
2070 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff
2071
2072
2073 #define BGE_CMD_MAILBOX 0x0b78
2074 #define BGE_CMD_NICDRV_ALIVE 0x00000001
2075 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002
2076 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003
2077 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004
2078
2079
2080 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c
2081 #define BGE_CMD_DATA_MAILBOX 0x0b80
2082 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00
2083
2084 #define BGE_DRV_STATE_MAILBOX 0x0c04
2085 #define BGE_DRV_STATE_START 0x00000001
2086 #define BGE_DRV_STATE_START_DONE 0x80000001
2087 #define BGE_DRV_STATE_UNLOAD 0x00000002
2088 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002
2089 #define BGE_DRV_STATE_WOL 0x00000003
2090 #define BGE_DRV_STATE_SUSPEND 0x00000004
2091
2092
2093 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08
2094 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001
2095 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002
2096
2097
2098 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14
2099 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18
2100
2101
2102 /*
2103 * RX-RISC event register
2104 */
2105 #define RX_RISC_EVENT_REG 0x6810
2106 #define RRER_ASF_EVENT 0x4000
2107
2108 #endif /* BGE_IPMI_ASF */
2109
2110 #ifdef __cplusplus
2111 }
2112 #endif
2113
2114 #endif /* _BGE_HW_H */