1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2011, 2012 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #include "bge_impl.h"
31
32 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset)))
33
34 /*
35 * Future features ... ?
36 */
37 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */
38 #define BGE_IND_IO32 1 /* indirect access code */
39 #define BGE_SEE_IO32 1 /* SEEPROM access code */
40 #define BGE_FLASH_IO32 1 /* FLASH access code */
41
42 /*
43 * BGE MSI tunable:
44 *
45 * By default MSI is enabled on all supported platforms but it is disabled
46 * for some Broadcom chips due to known MSI hardware issues. Currently MSI
47 * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
48 */
49 boolean_t bge_enable_msi = B_TRUE;
50
51 /*
52 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
53 */
54 boolean_t bge_relaxed_ordering = B_TRUE;
55
56 /*
57 * Property names
58 */
59 static char knownids_propname[] = "bge-known-subsystems";
60
61 /*
62 * Patchable globals:
63 *
64 * bge_autorecover
65 * Enables/disables automatic recovery after fault detection
66 *
67 * bge_mlcr_default
68 * Value to program into the MLCR; controls the chip's GPIO pins
69 *
70 * bge_dma_{rd,wr}prio
71 * Relative priorities of DMA reads & DMA writes respectively.
72 * These may each be patched to any value 0-3. Equal values
73 * will give "fair" (round-robin) arbitration for PCI access.
74 * Unequal values will give one or the other function priority.
75 *
76 * bge_dma_rwctrl
77 * Value to put in the Read/Write DMA control register. See
78 * the Broadcom PRM for things you can fiddle with in this
79 * register ...
80 *
81 * bge_{tx,rx}_{count,ticks}_{norm,intr}
82 * Send/receive interrupt coalescing parameters. Counts are
83 * #s of descriptors, ticks are in microseconds. *norm* values
84 * apply between status updates/interrupts; the *intr* values
85 * refer to the 'during-interrupt' versions - see the PRM.
86 *
87 * NOTE: these values have been determined by measurement. They
88 * differ significantly from the values recommended in the PRM.
89 */
90 static uint32_t bge_autorecover = 1;
91 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
92
93 static uint32_t bge_dma_rdprio = 1;
94 static uint32_t bge_dma_wrprio = 0;
95 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
96 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
97 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
98 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
99
100 uint32_t bge_rx_ticks_norm = 128;
101 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */
102 uint32_t bge_rx_count_norm = 8;
103 uint32_t bge_tx_count_norm = 128;
104
105 static uint32_t bge_rx_ticks_intr = 128;
106 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */
107 static uint32_t bge_rx_count_intr = 2;
108 static uint32_t bge_tx_count_intr = 0;
109
110 /*
111 * Memory pool configuration parameters.
112 *
113 * These are generally specific to each member of the chip family, since
114 * each one may have a different memory size/configuration.
115 *
116 * Setting the mbuf pool length for a specific type of chip to 0 inhibits
117 * the driver from programming the various registers; instead they are left
118 * at their hardware defaults. This is the preferred option for later chips
119 * (5705+), whereas the older chips *required* these registers to be set,
120 * since the h/w default was 0 ;-(
121 */
122 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT;
123 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704;
124 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705;
125 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
126 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT;
127 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704;
128 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */
129 static uint32_t bge_mbuf_pool_len_5721 = 0;
130
131 /*
132 * Various high and low water marks, thresholds, etc ...
133 *
134 * Note: these are taken from revision 7 of the PRM, and some are different
135 * from both the values in earlier PRMs *and* those determined experimentally
136 * and used in earlier versions of this driver ...
137 */
138 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT;
139 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT;
140 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT;
141
142 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT;
143 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT;
144 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT;
145
146 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT;
147 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT;
148 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT;
149
150 static uint32_t bge_watchdog_count = 1 << 16;
151 static uint16_t bge_dma_miss_limit = 20;
152
153 static uint32_t bge_stop_start_on_sync = 0;
154
155 /*
156 * bge_intr_max_loop controls the maximum loop number within bge_intr.
157 * When loading NIC with heavy network traffic, it is useful.
158 * Increasing this value could have positive effect to throughput,
159 * but it might also increase ticks of a bge ISR stick on CPU, which might
160 * lead to bad UI interactive experience. So tune this with caution.
161 */
162 static int bge_intr_max_loop = 1;
163
164 /*
165 * ========== Low-level chip & ring buffer manipulation ==========
166 */
167
168 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */
169
170
171 /*
172 * Config space read-modify-write routines
173 */
174
175 #if BGE_CFG_IO8
176
177 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
178 #pragma inline(bge_cfg_clr16)
179
180 static void
181 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
182 {
183 uint16_t regval;
184
185 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
186 (void *)bgep, regno, bits));
187
188 regval = pci_config_get16(bgep->cfg_handle, regno);
189
190 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
191 (void *)bgep, regno, bits, regval, regval & ~bits));
192
193 regval &= ~bits;
194 pci_config_put16(bgep->cfg_handle, regno, regval);
195 }
196
197 #endif /* BGE_CFG_IO8 */
198
199 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
200 #pragma inline(bge_cfg_clr32)
201
202 static void
203 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
204 {
205 uint32_t regval;
206
207 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
208 (void *)bgep, regno, bits));
209
210 regval = pci_config_get32(bgep->cfg_handle, regno);
211
212 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
213 (void *)bgep, regno, bits, regval, regval & ~bits));
214
215 regval &= ~bits;
216 pci_config_put32(bgep->cfg_handle, regno, regval);
217 }
218
219 #if BGE_IND_IO32
220
221 /*
222 * Indirect access to registers & RISC scratchpads, using config space
223 * accesses only.
224 *
225 * This isn't currently used, but someday we might want to use it for
226 * restoring the Subsystem Device/Vendor registers (which aren't directly
227 * writable in Config Space), or for downloading firmware into the RISCs
228 *
229 * In any case there are endian issues to be resolved before this code is
230 * enabled; the bizarre way that bytes get twisted by this chip AND by
231 * the PCI bridge in SPARC systems mean that we shouldn't enable it until
232 * it's been thoroughly tested for all access sizes on all supported
233 * architectures (SPARC *and* x86!).
234 */
235 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
236 #pragma inline(bge_ind_get32)
237
238 uint32_t
239 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
240 {
241 uint32_t val;
242
243 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
244
245 #ifdef __sparc
246 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
247 regno = LE_32(regno);
248 #endif
249 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
250 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
251
252 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
253 (void *)bgep, regno, val));
254
255 val = LE_32(val);
256
257 return (val);
258 }
259
260 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
261 #pragma inline(bge_ind_put32)
262
263 void
264 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
265 {
266 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
267 (void *)bgep, regno, val));
268
269 val = LE_32(val);
270 #ifdef __sparc
271 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
272 regno = LE_32(regno);
273 #endif
274 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
275 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
276 }
277
278 #endif /* BGE_IND_IO32 */
279
280 #if BGE_DEBUGGING
281
282 static void bge_pci_check(bge_t *bgep);
283 #pragma no_inline(bge_pci_check)
284
285 static void
286 bge_pci_check(bge_t *bgep)
287 {
288 uint16_t pcistatus;
289
290 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
291 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
292 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
293 (void *)bgep, pcistatus));
294 }
295
296 #endif /* BGE_DEBUGGING */
297
298 /*
299 * Perform first-stage chip (re-)initialisation, using only config-space
300 * accesses:
301 *
302 * + Read the vendor/device/revision/subsystem/cache-line-size registers,
303 * returning the data in the structure pointed to by <idp>.
304 * + Configure the target-mode endianness (swap) options.
305 * + Disable interrupts and enable Memory Space accesses.
306 * + Enable or disable Bus Mastering according to the <enable_dma> flag.
307 *
308 * This sequence is adapted from Broadcom document 570X-PG102-R,
309 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence
310 * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
311 *
312 * This function MUST be called before any non-config-space accesses
313 * are made; on this first call <enable_dma> is B_FALSE, and it
314 * effectively performs steps 3-1(!) of the initialisation sequence
315 * (the rest are not required but should be harmless).
316 *
317 * It MUST also be called after a chip reset, as this disables
318 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and
319 * it is effectively performing steps 6-8.
320 */
321 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
322 #pragma no_inline(bge_chip_cfg_init)
323
324 void
325 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
326 {
327 ddi_acc_handle_t handle;
328 uint16_t command;
329 uint32_t mhcr;
330 uint16_t value16;
331 int i;
332
333 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
334 (void *)bgep, (void *)cidp, enable_dma));
335
336 /*
337 * Step 3: save PCI cache line size and subsystem vendor ID
338 *
339 * Read all the config-space registers that characterise the
340 * chip, specifically vendor/device/revision/subsystem vendor
341 * and subsystem device id. We expect (but don't check) that
342 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
343 *
344 * Also save all bus-transaction related registers (cache-line
345 * size, bus-grant/latency parameters, etc). Some of these are
346 * cleared by reset, so we'll have to restore them later. This
347 * comes from the Broadcom document 570X-PG102-R ...
348 *
349 * Note: Broadcom document 570X-PG102-R seems to be in error
350 * here w.r.t. the offsets of the Subsystem Vendor ID and
351 * Subsystem (Device) ID registers, which are the opposite way
352 * round according to the PCI standard. For good measure, we
353 * save/restore both anyway.
354 */
355 handle = bgep->cfg_handle;
356
357 /*
358 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
359 * has been set in PCI_CONF_COMM already, we need to write the
360 * byte-swapped value to it. So we just write zero first for simplicity.
361 */
362 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
363 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
364 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
365 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
366 cidp->asic_rev = (mhcr & MHCR_CHIP_REV_MASK) >> MHCR_CHIP_REV_SHIFT;
367 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_PRODID) {
368 uint32_t reg;
369 switch (cidp->device) {
370 case DEVICE_ID_5717:
371 case DEVICE_ID_5718:
372 case DEVICE_ID_5719:
373 case DEVICE_ID_5720:
374 reg = PCI_CONF_GEN2_PRODID_ASICREV;
375 break;
376 case DEVICE_ID_57781:
377 case DEVICE_ID_57785:
378 case DEVICE_ID_57761:
379 case DEVICE_ID_57765:
380 case DEVICE_ID_57791:
381 case DEVICE_ID_57795:
382 case DEVICE_ID_57762:
383 case DEVICE_ID_57766:
384 case DEVICE_ID_57782:
385 case DEVICE_ID_57786:
386 reg = PCI_CONF_GEN15_PRODID_ASICREV;
387 break;
388 default:
389 reg = PCI_CONF_PRODID_ASICREV;
390 break;
391 }
392 cidp->asic_rev = pci_config_get32(handle, reg);
393 }
394 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
395 cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
396
397 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
398 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
399 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
400 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
401 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
402 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
403
404 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
405 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
406 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
407 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
408 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
409 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
410 cidp->vendor, cidp->device, cidp->revision));
411 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
412 cidp->subven, cidp->subdev, cidp->asic_rev));
413 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
414 cidp->clsize, cidp->latency, cidp->command));
415
416 cidp->chip_type = 0;
417 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5717 ||
418 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5719 ||
419 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5720)
420 cidp->chip_type |= CHIP_TYPE_5717_PLUS;
421
422 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57765 ||
423 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57766)
424 cidp->chip_type |= CHIP_TYPE_57765_CLASS;
425
426 if (cidp->chip_type & CHIP_TYPE_57765_CLASS ||
427 cidp->chip_type & CHIP_TYPE_5717_PLUS)
428 cidp->chip_type |= CHIP_TYPE_57765_PLUS;
429
430 /* Intentionally exclude ASIC_REV_5906 */
431 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5755 ||
432 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5787 ||
433 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5784 ||
434 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5761 ||
435 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5785 ||
436 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_57780 ||
437 cidp->chip_type & CHIP_TYPE_57765_PLUS)
438 cidp->chip_type |= CHIP_TYPE_5755_PLUS;
439
440 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5780 ||
441 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5714)
442 cidp->chip_type |= CHIP_TYPE_5780_CLASS;
443
444 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5750 ||
445 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5752 ||
446 MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5906 ||
447 cidp->chip_type & CHIP_TYPE_5755_PLUS ||
448 cidp->chip_type & CHIP_TYPE_5780_CLASS)
449 cidp->chip_type |= CHIP_TYPE_5750_PLUS;
450
451 if (MHCR_CHIP_ASIC_REV(cidp->asic_rev) == MHCR_CHIP_ASIC_REV_5705 ||
452 cidp->chip_type & CHIP_TYPE_5750_PLUS)
453 cidp->chip_type |= CHIP_TYPE_5705_PLUS;
454
455 /*
456 * Step 2 (also step 6): disable and clear interrupts.
457 * Steps 11-13: configure PIO endianness options, and enable
458 * indirect register access. We'll also select any other
459 * options controlled by the MHCR (e.g. tagged status, mask
460 * interrupt mode) at this stage ...
461 *
462 * Note: internally, the chip is 64-bit and BIG-endian, but
463 * since it talks to the host over a (LITTLE-endian) PCI bus,
464 * it normally swaps bytes around at the PCI interface.
465 * However, the PCI host bridge on SPARC systems normally
466 * swaps the byte lanes around too, since SPARCs are also
467 * BIG-endian. So it turns out that on SPARC, the right
468 * option is to tell the chip to swap (and the host bridge
469 * will swap back again), whereas on x86 we ask the chip
470 * NOT to swap, so the natural little-endianness of the
471 * PCI bus is assumed. Then the only thing that doesn't
472 * automatically work right is access to an 8-byte register
473 * by a little-endian host; but we don't want to set the
474 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
475 * accesses don't go where expected ;-( So we live with
476 * that, and perform word-swaps in software in the few cases
477 * where a chip register is defined as an 8-byte value --
478 * see the code below for details ...
479 *
480 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
481 * very clear in the register description in the PRM, but
482 * Broadcom document 570X-PG104-R page 248 explains a little
483 * more (under "Broadcom Mask Mode"). The bit changes the way
484 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
485 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
486 * way as the 5700 did, which isn't very convenient. Setting
487 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
488 * bit do just what its name says -- MASK the PCI #INTA output
489 * (i.e. deassert the signal at the pin) leaving all internal
490 * state unchanged. This is much more convenient for our
491 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
492 *
493 * Note: the inconvenient semantics of the interrupt mailbox
494 * (nonzero disables and acknowledges/clears the interrupt,
495 * zero enables AND CLEARS it) would make race conditions
496 * likely in the interrupt handler:
497 *
498 * (1) acknowledge & disable interrupts
499 * (2) while (more to do)
500 * process packets
501 * (3) enable interrupts -- also clears pending
502 *
503 * If the chip received more packets and internally generated
504 * an interrupt between the check at (2) and the mbox write
505 * at (3), this interrupt would be lost :-(
506 *
507 * The best way to avoid this is to use TAGGED STATUS mode,
508 * where the chip includes a unique tag in each status block
509 * update, and the host, when re-enabling interrupts, passes
510 * the last tag it saw back to the chip; then the chip can
511 * see whether the host is truly up to date, and regenerate
512 * its interrupt if not.
513 */
514 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
515 MHCR_ENABLE_TAGGED_STATUS_MODE |
516 MHCR_ENABLE_PCI_STATE_WRITE |
517 MHCR_MASK_INTERRUPT_MODE |
518 MHCR_CLEAR_INTERRUPT_INTA;
519
520 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
521 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
522
523 #ifdef _BIG_ENDIAN
524 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
525 #endif /* _BIG_ENDIAN */
526
527 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
528 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
529 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
530
531 #ifdef BGE_IPMI_ASF
532 bgep->asf_wordswapped = B_FALSE;
533 #endif
534 /*
535 * Step 1 (also step 7): Enable PCI Memory Space accesses
536 * Disable Memory Write/Invalidate
537 * Enable or disable Bus Mastering
538 *
539 * Note that all other bits are taken from the original value saved
540 * the first time through here, rather than from the current register
541 * value, 'cos that will have been cleared by a soft RESET since.
542 * In this way we preserve the OBP/nexus-parent's preferred settings
543 * of the parity-error and system-error enable bits across multiple
544 * chip RESETs.
545 */
546 command = bgep->chipid.command | PCI_COMM_MAE;
547 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
548 if (enable_dma)
549 command |= PCI_COMM_ME;
550 /*
551 * on BCM5714 revision A0, false parity error gets generated
552 * due to a logic bug. Provide a workaround by disabling parity
553 * error.
554 */
555 if (((cidp->device == DEVICE_ID_5714C) ||
556 (cidp->device == DEVICE_ID_5714S)) &&
557 (cidp->revision == REVISION_ID_5714_A0)) {
558 command &= ~PCI_COMM_PARITY_DETECT;
559 }
560 pci_config_put16(handle, PCI_CONF_COMM, command);
561
562 /*
563 * On some PCI-E device, there were instances when
564 * the device was still link training.
565 */
566 if (bgep->chipid.pci_type == BGE_PCI_E) {
567 i = 0;
568 value16 = pci_config_get16(handle, PCI_CONF_COMM);
569 while ((value16 != command) && (i < 100)) {
570 drv_usecwait(200);
571 value16 = pci_config_get16(handle, PCI_CONF_COMM);
572 ++i;
573 }
574 }
575
576 /*
577 * Clear any remaining error status bits
578 */
579 pci_config_put16(handle, PCI_CONF_STAT, ~0);
580
581 /*
582 * Do following if and only if the device is NOT BCM5714C OR
583 * BCM5715C
584 */
585 if (!((cidp->device == DEVICE_ID_5714C) ||
586 (cidp->device == DEVICE_ID_5715C))) {
587 /*
588 * Make sure these indirect-access registers are sane
589 * rather than random after power-up or reset
590 */
591 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
592 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
593 }
594 /*
595 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
596 */
597 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
598
599 if (cidp->pci_type == BGE_PCI_E) {
600 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
601 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
602 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
603 } else
604 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
605 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
606 }
607 }
608
609 #ifdef __amd64
610 /*
611 * Distinguish CPU types
612 *
613 * These use to distinguish AMD64 or Intel EM64T of CPU running mode.
614 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
615 * for PCI-Express based network interface card. This is the work-around
616 * for those nics.
617 */
618 static boolean_t bge_get_em64t_type(void);
619 #pragma inline(bge_get_em64t_type)
620
621 static boolean_t
622 bge_get_em64t_type(void)
623 {
624
625 return (x86_vendor == X86_VENDOR_Intel);
626 }
627 #endif
628
629 /*
630 * Operating register get/set access routines
631 */
632
633 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
634 #pragma inline(bge_reg_get32)
635
636 uint32_t
637 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
638 {
639 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
640 (void *)bgep, regno));
641
642 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
643 }
644
645 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
646 #pragma inline(bge_reg_put32)
647
648 void
649 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
650 {
651 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
652 (void *)bgep, regno, data));
653
654 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
655 BGE_PCICHK(bgep);
656 }
657
658 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
659 #pragma inline(bge_reg_set32)
660
661 void
662 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
663 {
664 uint32_t regval;
665
666 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
667 (void *)bgep, regno, bits));
668
669 regval = bge_reg_get32(bgep, regno);
670 regval |= bits;
671 bge_reg_put32(bgep, regno, regval);
672 }
673
674 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
675 #pragma inline(bge_reg_clr32)
676
677 void
678 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
679 {
680 uint32_t regval;
681
682 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
683 (void *)bgep, regno, bits));
684
685 regval = bge_reg_get32(bgep, regno);
686 regval &= ~bits;
687 bge_reg_put32(bgep, regno, regval);
688 }
689
690 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
691 #pragma inline(bge_reg_get64)
692
693 static uint64_t
694 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
695 {
696 uint64_t regval;
697
698 #ifdef __amd64
699 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
700 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
701 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
702 regval <<= 32;
703 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
704 } else {
705 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
706 }
707 #elif defined(__sparc)
708 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
709 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
710 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
711 regval <<= 32;
712 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
713 } else {
714 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
715 }
716 #else
717 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
718 #endif
719
720 #ifdef _LITTLE_ENDIAN
721 regval = (regval >> 32) | (regval << 32);
722 #endif /* _LITTLE_ENDIAN */
723
724 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
725 (void *)bgep, regno, regval));
726
727 return (regval);
728 }
729
730 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
731 #pragma inline(bge_reg_put64)
732
733 static void
734 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
735 {
736 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
737 (void *)bgep, regno, data));
738
739 #ifdef _LITTLE_ENDIAN
740 data = ((data >> 32) | (data << 32));
741 #endif /* _LITTLE_ENDIAN */
742
743 #ifdef __amd64
744 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
745 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
746 ddi_put32(bgep->io_handle,
747 PIO_ADDR(bgep, regno), (uint32_t)data);
748 BGE_PCICHK(bgep);
749 ddi_put32(bgep->io_handle,
750 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
751
752 } else {
753 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
754 }
755 #elif defined(__sparc)
756 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
757 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
758 ddi_put32(bgep->io_handle,
759 PIO_ADDR(bgep, regno + 4), (uint32_t)data);
760 BGE_PCICHK(bgep);
761 ddi_put32(bgep->io_handle,
762 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
763 } else {
764 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
765 }
766 #else
767 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
768 #endif
769
770 BGE_PCICHK(bgep);
771 }
772
773 /*
774 * The DDI doesn't provide get/put functions for 128 bit data
775 * so we put RCBs out as two 64-bit chunks instead.
776 */
777 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
778 #pragma inline(bge_reg_putrcb)
779
780 static void
781 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
782 {
783 uint64_t *p;
784
785 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
786 (void *)bgep, addr, rcbp->host_ring_addr,
787 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
788
789 ASSERT((addr % sizeof (*rcbp)) == 0);
790
791 p = (void *)rcbp;
792 bge_reg_put64(bgep, addr, *p++);
793 bge_reg_put64(bgep, addr+8, *p);
794 }
795
796 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
797 #pragma inline(bge_mbx_put)
798
799 void
800 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
801 {
802 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
803 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
804
805 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
806 (void *)bgep, regno, data));
807
808 /*
809 * Mailbox registers are nominally 64 bits on the 5701, but
810 * the MSW isn't used. On the 5703, they're only 32 bits
811 * anyway. So here we just write the lower(!) 32 bits -
812 * remembering that the chip is big-endian, even though the
813 * PCI bus is little-endian ...
814 */
815 #ifdef _BIG_ENDIAN
816 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
817 #else
818 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
819 #endif /* _BIG_ENDIAN */
820 BGE_PCICHK(bgep);
821 }
822
823 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
824 #pragma inline(bge_mbx_get)
825
826 uint32_t
827 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
828 {
829 uint32_t val32;
830
831 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
832 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
833
834 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
835 (void *)bgep, regno));
836
837 #ifdef _BIG_ENDIAN
838 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
839 #else
840 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
841 #endif /* _BIG_ENDIAN */
842 BGE_PCICHK(bgep);
843
844 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
845 (void *)bgep, regno, val32));
846
847 return (val32);
848 }
849
850
851 #if BGE_DEBUGGING
852
853 void bge_led_mark(bge_t *bgep);
854 #pragma no_inline(bge_led_mark)
855
856 void
857 bge_led_mark(bge_t *bgep)
858 {
859 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
860 LED_CONTROL_1000MBPS_LED |
861 LED_CONTROL_100MBPS_LED |
862 LED_CONTROL_10MBPS_LED;
863
864 /*
865 * Blink all three LINK LEDs on simultaneously, then all off,
866 * then restore to automatic hardware control. This is used
867 * in laboratory testing to trigger a logic analyser or scope.
868 */
869 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
870 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
871 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
872 led_ctrl = LED_CONTROL_OVERRIDE_LINK;
873 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
874 }
875
876 #endif /* BGE_DEBUGGING */
877
878 /*
879 * NIC on-chip memory access routines
880 *
881 * Only 32K of NIC memory is visible at a time, controlled by the
882 * Memory Window Base Address Register (in PCI config space). Once
883 * this is set, the 32K region of NIC-local memory that it refers
884 * to can be directly addressed in the upper 32K of the 64K of PCI
885 * memory space used for the device.
886 */
887
888 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
889 #pragma inline(bge_nic_setwin)
890
891 static void
892 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
893 {
894 chip_id_t *cidp;
895
896 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
897 (void *)bgep, base));
898
899 ASSERT((base & MWBAR_GRANULE_MASK) == 0);
900
901 /*
902 * Don't do repeated zero data writes,
903 * if the device is BCM5714C/15C.
904 */
905 cidp = &bgep->chipid;
906 if ((cidp->device == DEVICE_ID_5714C) ||
907 (cidp->device == DEVICE_ID_5715C)) {
908 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
909 return;
910 /* Adjust lastWriteZeroData */
911 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
912 B_TRUE : B_FALSE);
913 }
914 #ifdef __sparc
915 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
916 base = LE_32(base);
917 #endif
918 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
919 }
920
921 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
922 #pragma inline(bge_nic_get32)
923
924 static uint32_t
925 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
926 {
927 uint32_t data;
928
929 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
930 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
931 /* workaround for word swap error */
932 if (addr & 4)
933 addr = addr - 4;
934 else
935 addr = addr + 4;
936 }
937 #endif
938
939 #ifdef __sparc
940 data = bge_nic_read32(bgep, addr);
941 #else
942 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
943 addr &= MWBAR_GRANULE_MASK;
944 addr += NIC_MEM_WINDOW_OFFSET;
945
946 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
947 #endif
948
949 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
950 (void *)bgep, addr, data));
951
952 return (data);
953 }
954
955 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
956 #pragma inline(bge_nic_put32)
957
958 void
959 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
960 {
961 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
962 (void *)bgep, addr, data));
963
964 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
965 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
966 /* workaround for word swap error */
967 if (addr & 4)
968 addr = addr - 4;
969 else
970 addr = addr + 4;
971 }
972 #endif
973
974 #ifdef __sparc
975 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
976 addr = LE_32(addr);
977 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
978 data = LE_32(data);
979 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
980 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
981 #else
982 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
983 addr &= MWBAR_GRANULE_MASK;
984 addr += NIC_MEM_WINDOW_OFFSET;
985 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
986 BGE_PCICHK(bgep);
987 #endif
988 }
989
990 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
991 #pragma inline(bge_nic_get64)
992
993 static uint64_t
994 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
995 {
996 uint64_t data;
997
998 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
999 addr &= MWBAR_GRANULE_MASK;
1000 addr += NIC_MEM_WINDOW_OFFSET;
1001
1002 #ifdef __amd64
1003 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1004 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1005 data = ddi_get32(bgep->io_handle,
1006 PIO_ADDR(bgep, addr + 4));
1007 data <<= 32;
1008 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
1009 } else {
1010 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1011 }
1012 #elif defined(__sparc)
1013 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1014 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1015 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
1016 data <<= 32;
1017 data |= ddi_get32(bgep->io_handle,
1018 PIO_ADDR(bgep, addr + 4));
1019 } else {
1020 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1021 }
1022 #else
1023 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
1024 #endif
1025
1026 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
1027 (void *)bgep, addr, data));
1028
1029 return (data);
1030 }
1031
1032 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
1033 #pragma inline(bge_nic_put64)
1034
1035 static void
1036 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
1037 {
1038 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
1039 (void *)bgep, addr, data));
1040
1041 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1042 addr &= MWBAR_GRANULE_MASK;
1043 addr += NIC_MEM_WINDOW_OFFSET;
1044
1045 #ifdef __amd64
1046 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1047 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1048 ddi_put32(bgep->io_handle,
1049 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1050 BGE_PCICHK(bgep);
1051 ddi_put32(bgep->io_handle,
1052 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1053 } else {
1054 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1055 }
1056 #elif defined(__sparc)
1057 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1058 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1059 ddi_put32(bgep->io_handle,
1060 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
1061 BGE_PCICHK(bgep);
1062 ddi_put32(bgep->io_handle,
1063 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
1064 } else {
1065 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1066 }
1067 #else
1068 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1069 #endif
1070
1071 BGE_PCICHK(bgep);
1072 }
1073
1074 /*
1075 * The DDI doesn't provide get/put functions for 128 bit data
1076 * so we put RCBs out as two 64-bit chunks instead.
1077 */
1078 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1079 #pragma inline(bge_nic_putrcb)
1080
1081 static void
1082 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1083 {
1084 uint64_t *p;
1085
1086 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1087 (void *)bgep, addr, rcbp->host_ring_addr,
1088 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
1089
1090 ASSERT((addr % sizeof (*rcbp)) == 0);
1091
1092 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1093 addr &= MWBAR_GRANULE_MASK;
1094 addr += NIC_MEM_WINDOW_OFFSET;
1095
1096 p = (void *)rcbp;
1097 #ifdef __amd64
1098 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1099 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1100 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1101 (uint32_t)(*p));
1102 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1103 (uint32_t)(*p++ >> 32));
1104 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1105 (uint32_t)(*p));
1106 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1107 (uint32_t)(*p >> 32));
1108
1109 } else {
1110 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1111 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1112 }
1113 #elif defined(__sparc)
1114 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1115 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1116 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1117 (uint32_t)(*p));
1118 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1119 (uint32_t)(*p++ >> 32));
1120 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1121 (uint32_t)(*p));
1122 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1123 (uint32_t)(*p >> 32));
1124 } else {
1125 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1126 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1127 }
1128 #else
1129 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1130 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1131 #endif
1132
1133 BGE_PCICHK(bgep);
1134 }
1135
1136 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1137 #pragma inline(bge_nic_zero)
1138
1139 static void
1140 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1141 {
1142 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1143 (void *)bgep, addr, nbytes));
1144
1145 ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1146 ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1147
1148 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1149 addr &= MWBAR_GRANULE_MASK;
1150 addr += NIC_MEM_WINDOW_OFFSET;
1151
1152 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1153 nbytes, 1, DDI_DATA_SZ08_ACC);
1154 BGE_PCICHK(bgep);
1155 }
1156
1157 /*
1158 * MII (PHY) register get/set access routines
1159 *
1160 * These use the chip's MII auto-access method, controlled by the
1161 * MII Communication register at 0x044c, so the CPU doesn't have
1162 * to fiddle with the individual bits.
1163 */
1164
1165 #undef BGE_DBG
1166 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */
1167
1168 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1169 uint16_t data, uint32_t cmd);
1170 #pragma no_inline(bge_mii_access)
1171
1172 static uint16_t
1173 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1174 {
1175 uint32_t timeout;
1176 uint32_t regval1;
1177 uint32_t regval2;
1178
1179 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1180 (void *)bgep, regno, data, cmd));
1181
1182 ASSERT(mutex_owned(bgep->genlock));
1183
1184 /*
1185 * Assemble the command ...
1186 */
1187 cmd |= data << MI_COMMS_DATA_SHIFT;
1188 cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1189 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1190 cmd |= MI_COMMS_START;
1191
1192 /*
1193 * Wait for any command already in progress ...
1194 *
1195 * Note: this *shouldn't* ever find that there is a command
1196 * in progress, because we already hold the <genlock> mutex.
1197 * Nonetheless, we have sometimes seen the MI_COMMS_START
1198 * bit set here -- it seems that the chip can initiate MII
1199 * accesses internally, even with polling OFF.
1200 */
1201 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1202 for (timeout = 100; ; ) {
1203 if ((regval2 & MI_COMMS_START) == 0) {
1204 bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1205 break;
1206 }
1207 if (--timeout == 0)
1208 break;
1209 drv_usecwait(10);
1210 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1211 }
1212
1213 if (timeout == 0)
1214 return ((uint16_t)~0u);
1215
1216 if (timeout != 100)
1217 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1218 "MI_COMMS_START set for %d us; 0x%x->0x%x",
1219 cmd, 10*(100-timeout), regval1, regval2));
1220
1221 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1222 for (timeout = 1000; ; ) {
1223 if ((regval1 & MI_COMMS_START) == 0)
1224 break;
1225 if (--timeout == 0)
1226 break;
1227 drv_usecwait(10);
1228 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1229 }
1230
1231 /*
1232 * Drop out early if the READ FAILED bit is set -- this chip
1233 * could be a 5703/4S, with a SerDes instead of a PHY!
1234 */
1235 if (regval2 & MI_COMMS_READ_FAILED)
1236 return ((uint16_t)~0u);
1237
1238 if (timeout == 0)
1239 return ((uint16_t)~0u);
1240
1241 /*
1242 * The PRM says to wait 5us after seeing the START bit clear
1243 * and then re-read the register to get the final value of the
1244 * data field, in order to avoid a race condition where the
1245 * START bit is clear but the data field isn't yet valid.
1246 *
1247 * Note: we don't actually seem to be encounter this race;
1248 * except when the START bit is seen set again (see below),
1249 * the data field doesn't change during this 5us interval.
1250 */
1251 drv_usecwait(5);
1252 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1253
1254 /*
1255 * Unfortunately, when following the PRMs instructions above,
1256 * we have occasionally seen the START bit set again(!) in the
1257 * value read after the 5us delay. This seems to be due to the
1258 * chip autonomously starting another MII access internally.
1259 * In such cases, the command/data/etc fields relate to the
1260 * internal command, rather than the one that we thought had
1261 * just finished. So in this case, we fall back to returning
1262 * the data from the original read that showed START clear.
1263 */
1264 if (regval2 & MI_COMMS_START) {
1265 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1266 "MI_COMMS_START set after transaction; 0x%x->0x%x",
1267 cmd, regval1, regval2));
1268 regval2 = regval1;
1269 }
1270
1271 if (regval2 & MI_COMMS_START)
1272 return ((uint16_t)~0u);
1273
1274 if (regval2 & MI_COMMS_READ_FAILED)
1275 return ((uint16_t)~0u);
1276
1277 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1278 }
1279
1280 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1281 #pragma no_inline(bge_mii_get16)
1282
1283 uint16_t
1284 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1285 {
1286 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1287 (void *)bgep, regno));
1288
1289 ASSERT(mutex_owned(bgep->genlock));
1290
1291 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1292 (regno == MII_MSCONTROL)))
1293 return (0);
1294
1295 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1296 }
1297
1298 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1299 #pragma no_inline(bge_mii_put16)
1300
1301 void
1302 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1303 {
1304 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1305 (void *)bgep, regno, data));
1306
1307 ASSERT(mutex_owned(bgep->genlock));
1308
1309 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1310 (regno == MII_MSCONTROL)))
1311 return;
1312
1313 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1314 }
1315
1316 #undef BGE_DBG
1317 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */
1318
1319 #if BGE_SEE_IO32 || BGE_FLASH_IO32
1320
1321 /*
1322 * Basic SEEPROM get/set access routine
1323 *
1324 * This uses the chip's SEEPROM auto-access method, controlled by the
1325 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1326 * doesn't have to fiddle with the individual bits.
1327 *
1328 * The caller should hold <genlock> and *also* have already acquired
1329 * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1330 *
1331 * Return value:
1332 * 0 on success,
1333 * ENODATA on access timeout (maybe retryable: device may just be busy)
1334 * EPROTO on other h/w or s/w errors.
1335 *
1336 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1337 * from a (successful) SEEPROM_ACCESS_READ.
1338 */
1339 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1340 uint32_t *dp);
1341 #pragma no_inline(bge_seeprom_access)
1342
1343 static int
1344 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1345 {
1346 uint32_t tries;
1347 uint32_t regval;
1348
1349 ASSERT(mutex_owned(bgep->genlock));
1350
1351 /*
1352 * On the newer chips that support both SEEPROM & Flash, we need
1353 * to specifically enable SEEPROM access (Flash is the default).
1354 * On older chips, we don't; SEEPROM is the only NVtype supported,
1355 * and the NVM control registers don't exist ...
1356 */
1357 switch (bgep->chipid.nvtype) {
1358 case BGE_NVTYPE_NONE:
1359 case BGE_NVTYPE_UNKNOWN:
1360 _NOTE(NOTREACHED)
1361 case BGE_NVTYPE_SEEPROM:
1362 break;
1363
1364 case BGE_NVTYPE_LEGACY_SEEPROM:
1365 case BGE_NVTYPE_UNBUFFERED_FLASH:
1366 case BGE_NVTYPE_BUFFERED_FLASH:
1367 default:
1368 bge_reg_set32(bgep, NVM_CONFIG1_REG,
1369 NVM_CFG1_LEGACY_SEEPROM_MODE);
1370 break;
1371 }
1372
1373 /*
1374 * Check there's no command in progress.
1375 *
1376 * Note: this *shouldn't* ever find that there is a command
1377 * in progress, because we already hold the <genlock> mutex.
1378 * Also, to ensure we don't have a conflict with the chip's
1379 * internal firmware or a process accessing the same (shared)
1380 * SEEPROM through the other port of a 5704, we've already
1381 * been through the "software arbitration" protocol.
1382 * So this is just a final consistency check: we shouldn't
1383 * see EITHER the START bit (command started but not complete)
1384 * OR the COMPLETE bit (command completed but not cleared).
1385 */
1386 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1387 if (regval & SEEPROM_ACCESS_START)
1388 return (EPROTO);
1389 if (regval & SEEPROM_ACCESS_COMPLETE)
1390 return (EPROTO);
1391
1392 /*
1393 * Assemble the command ...
1394 */
1395 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1396 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1397 addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1398 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1399 cmd |= SEEPROM_ACCESS_START;
1400 cmd |= SEEPROM_ACCESS_COMPLETE;
1401 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1402
1403 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1404 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1405
1406 /*
1407 * By observation, a successful access takes ~20us on a 5703/4,
1408 * but apparently much longer (up to 1000us) on the obsolescent
1409 * BCM5700/BCM5701. We want to be sure we don't get any false
1410 * timeouts here; but OTOH, we don't want a bogus access to lock
1411 * out interrupts for longer than necessary. So we'll allow up
1412 * to 1000us ...
1413 */
1414 for (tries = 0; tries < 1000; ++tries) {
1415 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1416 if (regval & SEEPROM_ACCESS_COMPLETE)
1417 break;
1418 drv_usecwait(1);
1419 }
1420
1421 if (regval & SEEPROM_ACCESS_COMPLETE) {
1422 /*
1423 * All OK; read the SEEPROM data register, then write back
1424 * the value read from the address register in order to
1425 * clear the <complete> bit and leave the SEEPROM access
1426 * state machine idle, ready for the next access ...
1427 */
1428 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1429 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1430 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1431 return (0);
1432 }
1433
1434 /*
1435 * Hmm ... what happened here?
1436 *
1437 * Most likely, the user addressed a non-existent SEEPROM. Or
1438 * maybe the SEEPROM was busy internally (e.g. processing a write)
1439 * and didn't respond to being addressed. Either way, it's left
1440 * the SEEPROM access state machine wedged. So we'll reset it
1441 * before we leave, so it's ready for next time ...
1442 */
1443 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1444 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1445 return (ENODATA);
1446 }
1447
1448 /*
1449 * Basic Flash get/set access routine
1450 *
1451 * These use the chip's Flash auto-access method, controlled by the
1452 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1453 * fiddle with the individual bits.
1454 *
1455 * The caller should hold <genlock> and *also* have already acquired
1456 * the right to access the Flash, via bge_nvmem_acquire() above.
1457 *
1458 * Return value:
1459 * 0 on success,
1460 * ENODATA on access timeout (maybe retryable: device may just be busy)
1461 * ENODEV if the NVmem device is missing or otherwise unusable
1462 *
1463 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1464 * from a (successful) NVM_FLASH_CMD_RD.
1465 */
1466 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1467 uint32_t *dp);
1468 #pragma no_inline(bge_flash_access)
1469
1470 static int
1471 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1472 {
1473 uint32_t tries;
1474 uint32_t regval;
1475
1476 ASSERT(mutex_owned(bgep->genlock));
1477
1478 /*
1479 * On the newer chips that support both SEEPROM & Flash, we need
1480 * to specifically disable SEEPROM access while accessing Flash.
1481 * The older chips don't support Flash, and the NVM registers don't
1482 * exist, so we shouldn't be here at all!
1483 */
1484 switch (bgep->chipid.nvtype) {
1485 case BGE_NVTYPE_NONE:
1486 case BGE_NVTYPE_UNKNOWN:
1487 _NOTE(NOTREACHED)
1488 case BGE_NVTYPE_SEEPROM:
1489 return (ENODEV);
1490
1491 case BGE_NVTYPE_LEGACY_SEEPROM:
1492 case BGE_NVTYPE_UNBUFFERED_FLASH:
1493 case BGE_NVTYPE_BUFFERED_FLASH:
1494 default:
1495 bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1496 NVM_CFG1_LEGACY_SEEPROM_MODE);
1497 break;
1498 }
1499
1500 /*
1501 * Assemble the command ...
1502 */
1503 addr &= NVM_FLASH_ADDR_MASK;
1504 cmd |= NVM_FLASH_CMD_DOIT;
1505 cmd |= NVM_FLASH_CMD_FIRST;
1506 cmd |= NVM_FLASH_CMD_LAST;
1507 cmd |= NVM_FLASH_CMD_DONE;
1508
1509 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1510 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1511 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1512
1513 /*
1514 * Allow up to 1000ms ...
1515 */
1516 for (tries = 0; tries < 1000; ++tries) {
1517 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1518 if (regval & NVM_FLASH_CMD_DONE)
1519 break;
1520 drv_usecwait(1);
1521 }
1522
1523 if (regval & NVM_FLASH_CMD_DONE) {
1524 /*
1525 * All OK; read the data from the Flash read register
1526 */
1527 BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1528 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1529 return (0);
1530 }
1531
1532 /*
1533 * Hmm ... what happened here?
1534 *
1535 * Most likely, the user addressed a non-existent Flash. Or
1536 * maybe the Flash was busy internally (e.g. processing a write)
1537 * and didn't respond to being addressed. Either way, there's
1538 * nothing we can here ...
1539 */
1540 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1541 return (ENODATA);
1542 }
1543
1544 /*
1545 * The next two functions regulate access to the NVram (if fitted).
1546 *
1547 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1548 * (SPI) interface, but they can be accessed through either port. These
1549 * are managed by different instance of this driver and have no software
1550 * state in common.
1551 *
1552 * In addition (and even on a single core chip) the chip's internal
1553 * firmware can access the SEEPROM/Flash, most notably after a RESET
1554 * when it may download code to run internally.
1555 *
1556 * So we need to arbitrate between these various software agents. For
1557 * this purpose, the chip provides the Software Arbitration Register,
1558 * which implements hardware(!) arbitration.
1559 *
1560 * This functionality didn't exist on older (5700/5701) chips, so there's
1561 * nothing we can do by way of arbitration on those; also, if there's no
1562 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1563 * nothing to do.
1564 *
1565 * The internal firmware appears to use Request 0, which is the highest
1566 * priority. So we'd like to use Request 2, leaving one higher and one
1567 * lower for any future developments ... but apparently this doesn't
1568 * always work. So for now, the code uses Request 1 ;-(
1569 */
1570
1571 #define NVM_READ_REQ NVM_READ_REQ1
1572 #define NVM_RESET_REQ NVM_RESET_REQ1
1573 #define NVM_SET_REQ NVM_SET_REQ1
1574
1575 static void bge_nvmem_relinquish(bge_t *bgep);
1576 #pragma no_inline(bge_nvmem_relinquish)
1577
1578 static void
1579 bge_nvmem_relinquish(bge_t *bgep)
1580 {
1581 ASSERT(mutex_owned(bgep->genlock));
1582
1583 switch (bgep->chipid.nvtype) {
1584 case BGE_NVTYPE_NONE:
1585 case BGE_NVTYPE_UNKNOWN:
1586 _NOTE(NOTREACHED)
1587 return;
1588
1589 case BGE_NVTYPE_SEEPROM:
1590 /*
1591 * No arbitration performed, no release needed
1592 */
1593 return;
1594
1595 case BGE_NVTYPE_LEGACY_SEEPROM:
1596 case BGE_NVTYPE_UNBUFFERED_FLASH:
1597 case BGE_NVTYPE_BUFFERED_FLASH:
1598 default:
1599 break;
1600 }
1601
1602 /*
1603 * Our own request should be present (whether or not granted) ...
1604 */
1605 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1606
1607 /*
1608 * ... this will make it go away.
1609 */
1610 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1611 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1612 }
1613
1614 /*
1615 * Arbitrate for access to the NVmem, if necessary
1616 *
1617 * Return value:
1618 * 0 on success
1619 * EAGAIN if the device is in use (retryable)
1620 * ENODEV if the NVmem device is missing or otherwise unusable
1621 */
1622 static int bge_nvmem_acquire(bge_t *bgep);
1623 #pragma no_inline(bge_nvmem_acquire)
1624
1625 static int
1626 bge_nvmem_acquire(bge_t *bgep)
1627 {
1628 uint32_t regval;
1629 uint32_t tries;
1630
1631 ASSERT(mutex_owned(bgep->genlock));
1632
1633 switch (bgep->chipid.nvtype) {
1634 case BGE_NVTYPE_NONE:
1635 case BGE_NVTYPE_UNKNOWN:
1636 /*
1637 * Access denied: no (recognisable) device fitted
1638 */
1639 return (ENODEV);
1640
1641 case BGE_NVTYPE_SEEPROM:
1642 /*
1643 * Access granted: no arbitration needed (or possible)
1644 */
1645 return (0);
1646
1647 case BGE_NVTYPE_LEGACY_SEEPROM:
1648 case BGE_NVTYPE_UNBUFFERED_FLASH:
1649 case BGE_NVTYPE_BUFFERED_FLASH:
1650 default:
1651 /*
1652 * Access conditional: conduct arbitration protocol
1653 */
1654 break;
1655 }
1656
1657 /*
1658 * We're holding the per-port mutex <genlock>, so no-one other
1659 * thread can be attempting to access the NVmem through *this*
1660 * port. But it could be in use by the *other* port (of a 5704),
1661 * or by the chip's internal firmware, so we have to go through
1662 * the full (hardware) arbitration protocol ...
1663 *
1664 * Note that *because* we're holding <genlock>, the interrupt handler
1665 * won't be able to progress. So we're only willing to spin for a
1666 * fairly short time. Specifically:
1667 *
1668 * We *must* wait long enough for the hardware to resolve all
1669 * requests and determine the winner. Fortunately, this is
1670 * "almost instantaneous", even as observed by GHz CPUs.
1671 *
1672 * A successful access by another Solaris thread (via either
1673 * port) typically takes ~20us. So waiting a bit longer than
1674 * that will give a good chance of success, if the other user
1675 * *is* another thread on the other port.
1676 *
1677 * However, the internal firmware can hold on to the NVmem
1678 * for *much* longer: at least 10 milliseconds just after a
1679 * RESET, and maybe even longer if the NVmem actually contains
1680 * code to download and run on the internal CPUs.
1681 *
1682 * So, we'll allow 50us; if that's not enough then it's up to the
1683 * caller to retry later (hence the choice of return code EAGAIN).
1684 */
1685 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1686 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1687
1688 for (tries = 0; tries < 50; ++tries) {
1689 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1690 if (regval & NVM_WON_REQ1)
1691 break;
1692 drv_usecwait(1);
1693 }
1694
1695 if (regval & NVM_WON_REQ1) {
1696 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1697 return (0);
1698 }
1699
1700 /*
1701 * Somebody else must be accessing the NVmem, so abandon our
1702 * attempt take control of it. The caller can try again later ...
1703 */
1704 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1705 bge_nvmem_relinquish(bgep);
1706 return (EAGAIN);
1707 }
1708
1709 /*
1710 * This code assumes that the GPIO1 bit has been wired up to the NVmem
1711 * write protect line in such a way that the NVmem is protected when
1712 * GPIO1 is an input, or is an output but driven high. Thus, to make the
1713 * NVmem writable we have to change GPIO1 to an output AND drive it low.
1714 *
1715 * Note: there's only one set of GPIO pins on a 5704, even though they
1716 * can be accessed through either port. So the chip has to resolve what
1717 * happens if the two ports program a single pin differently ... the rule
1718 * it uses is that if the ports disagree about the *direction* of a pin,
1719 * "output" wins over "input", but if they disagree about its *value* as
1720 * an output, then the pin is TRISTATED instead! In such a case, no-one
1721 * wins, and the external signal does whatever the external circuitry
1722 * defines as the default -- which we've assumed is the PROTECTED state.
1723 * So, we always change GPIO1 back to being an *input* whenever we're not
1724 * specifically using it to unprotect the NVmem. This allows either port
1725 * to update the NVmem, although obviously only one at a time!
1726 *
1727 * The caller should hold <genlock> and *also* have already acquired the
1728 * right to access the NVmem, via bge_nvmem_acquire() above.
1729 */
1730 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1731 #pragma inline(bge_nvmem_protect)
1732
1733 static void
1734 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1735 {
1736 uint32_t regval;
1737
1738 ASSERT(mutex_owned(bgep->genlock));
1739
1740 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1741 if (protect) {
1742 regval |= MLCR_MISC_PINS_OUTPUT_1;
1743 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1744 } else {
1745 regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1746 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1747 }
1748 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1749 }
1750
1751 /*
1752 * Now put it all together ...
1753 *
1754 * Try to acquire control of the NVmem; if successful, then:
1755 * unprotect it (if we want to write to it)
1756 * perform the requested access
1757 * reprotect it (after a write)
1758 * relinquish control
1759 *
1760 * Return value:
1761 * 0 on success,
1762 * EAGAIN if the device is in use (retryable)
1763 * ENODATA on access timeout (maybe retryable: device may just be busy)
1764 * ENODEV if the NVmem device is missing or otherwise unusable
1765 * EPROTO on other h/w or s/w errors.
1766 */
1767 static int
1768 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1769 {
1770 int err;
1771
1772 if ((err = bge_nvmem_acquire(bgep)) == 0) {
1773 switch (cmd) {
1774 case BGE_SEE_READ:
1775 err = bge_seeprom_access(bgep,
1776 SEEPROM_ACCESS_READ, addr, dp);
1777 break;
1778
1779 case BGE_SEE_WRITE:
1780 bge_nvmem_protect(bgep, B_FALSE);
1781 err = bge_seeprom_access(bgep,
1782 SEEPROM_ACCESS_WRITE, addr, dp);
1783 bge_nvmem_protect(bgep, B_TRUE);
1784 break;
1785
1786 case BGE_FLASH_READ:
1787 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1788 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1789 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1790 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1791 bge_reg_set32(bgep, NVM_ACCESS_REG,
1792 NVM_ACCESS_ENABLE);
1793 }
1794 err = bge_flash_access(bgep,
1795 NVM_FLASH_CMD_RD, addr, dp);
1796 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1797 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1798 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1799 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1800 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1801 NVM_ACCESS_ENABLE);
1802 }
1803 break;
1804
1805 case BGE_FLASH_WRITE:
1806 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1807 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1808 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1809 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1810 bge_reg_set32(bgep, NVM_ACCESS_REG,
1811 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1812 }
1813 bge_nvmem_protect(bgep, B_FALSE);
1814 err = bge_flash_access(bgep,
1815 NVM_FLASH_CMD_WR, addr, dp);
1816 bge_nvmem_protect(bgep, B_TRUE);
1817 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1818 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1819 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1820 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1821 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1822 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1823 }
1824
1825 break;
1826
1827 default:
1828 _NOTE(NOTREACHED)
1829 break;
1830 }
1831 bge_nvmem_relinquish(bgep);
1832 }
1833
1834 BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1835 return (err);
1836 }
1837
1838 /*
1839 * Attempt to get a MAC address from the SEEPROM or Flash, if any
1840 */
1841 static uint64_t bge_get_nvmac(bge_t *bgep);
1842 #pragma no_inline(bge_get_nvmac)
1843
1844 static uint64_t
1845 bge_get_nvmac(bge_t *bgep)
1846 {
1847 uint32_t mac_high;
1848 uint32_t mac_low;
1849 uint32_t addr;
1850 uint32_t cmd;
1851 uint64_t mac;
1852
1853 BGE_TRACE(("bge_get_nvmac($%p)",
1854 (void *)bgep));
1855
1856 switch (bgep->chipid.nvtype) {
1857 case BGE_NVTYPE_NONE:
1858 case BGE_NVTYPE_UNKNOWN:
1859 default:
1860 return (0ULL);
1861
1862 case BGE_NVTYPE_SEEPROM:
1863 case BGE_NVTYPE_LEGACY_SEEPROM:
1864 cmd = BGE_SEE_READ;
1865 break;
1866
1867 case BGE_NVTYPE_UNBUFFERED_FLASH:
1868 case BGE_NVTYPE_BUFFERED_FLASH:
1869 cmd = BGE_FLASH_READ;
1870 break;
1871 }
1872
1873 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1874 addr = NVMEM_DATA_MAC_ADDRESS_5906;
1875 else
1876 addr = NVMEM_DATA_MAC_ADDRESS;
1877
1878 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1879 return (0ULL);
1880 addr += 4;
1881 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1882 return (0ULL);
1883
1884 /*
1885 * The Broadcom chip is natively BIG-endian, so that's how the
1886 * MAC address is represented in NVmem. We may need to swap it
1887 * around on a little-endian host ...
1888 */
1889 #ifdef _BIG_ENDIAN
1890 mac = mac_high;
1891 mac = mac << 32;
1892 mac |= mac_low;
1893 #else
1894 mac = BGE_BSWAP_32(mac_high);
1895 mac = mac << 32;
1896 mac |= BGE_BSWAP_32(mac_low);
1897 #endif /* _BIG_ENDIAN */
1898
1899 return (mac);
1900 }
1901
1902 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1903
1904 /*
1905 * Dummy version for when we're not supporting NVmem access
1906 */
1907 static uint64_t bge_get_nvmac(bge_t *bgep);
1908 #pragma inline(bge_get_nvmac)
1909
1910 static uint64_t
1911 bge_get_nvmac(bge_t *bgep)
1912 {
1913 _NOTE(ARGUNUSED(bgep))
1914 return (0ULL);
1915 }
1916
1917 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1918
1919 /*
1920 * Determine the type of NVmem that is (or may be) attached to this chip,
1921 */
1922 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1923 #pragma no_inline(bge_nvmem_id)
1924
1925 static enum bge_nvmem_type
1926 bge_nvmem_id(bge_t *bgep)
1927 {
1928 enum bge_nvmem_type nvtype;
1929 uint32_t config1;
1930
1931 BGE_TRACE(("bge_nvmem_id($%p)",
1932 (void *)bgep));
1933
1934 switch (bgep->chipid.device) {
1935 default:
1936 /*
1937 * We shouldn't get here; it means we don't recognise
1938 * the chip, which means we don't know how to determine
1939 * what sort of NVmem (if any) it has. So we'll say
1940 * NONE, to disable the NVmem access code ...
1941 */
1942 nvtype = BGE_NVTYPE_NONE;
1943 break;
1944
1945 case DEVICE_ID_5700:
1946 case DEVICE_ID_5700x:
1947 case DEVICE_ID_5701:
1948 /*
1949 * These devices support *only* SEEPROMs
1950 */
1951 nvtype = BGE_NVTYPE_SEEPROM;
1952 break;
1953
1954 case DEVICE_ID_5702:
1955 case DEVICE_ID_5702fe:
1956 case DEVICE_ID_5703C:
1957 case DEVICE_ID_5703S:
1958 case DEVICE_ID_5704C:
1959 case DEVICE_ID_5704S:
1960 case DEVICE_ID_5704:
1961 case DEVICE_ID_5705M:
1962 case DEVICE_ID_5705C:
1963 case DEVICE_ID_5705_2:
1964 case DEVICE_ID_5717:
1965 case DEVICE_ID_5718:
1966 case DEVICE_ID_5719:
1967 case DEVICE_ID_5720:
1968 case DEVICE_ID_5724:
1969 case DEVICE_ID_57760:
1970 case DEVICE_ID_57780:
1971 case DEVICE_ID_57788:
1972 case DEVICE_ID_57790:
1973 case DEVICE_ID_5780:
1974 case DEVICE_ID_5782:
1975 case DEVICE_ID_5784M:
1976 case DEVICE_ID_5785:
1977 case DEVICE_ID_5787:
1978 case DEVICE_ID_5787M:
1979 case DEVICE_ID_5788:
1980 case DEVICE_ID_5789:
1981 case DEVICE_ID_5751:
1982 case DEVICE_ID_5751M:
1983 case DEVICE_ID_5752:
1984 case DEVICE_ID_5752M:
1985 case DEVICE_ID_5754:
1986 case DEVICE_ID_5755:
1987 case DEVICE_ID_5755M:
1988 case DEVICE_ID_5756M:
1989 case DEVICE_ID_5721:
1990 case DEVICE_ID_5722:
1991 case DEVICE_ID_5723:
1992 case DEVICE_ID_5761:
1993 case DEVICE_ID_5761E:
1994 case DEVICE_ID_5761S:
1995 case DEVICE_ID_5761SE:
1996 case DEVICE_ID_5764:
1997 case DEVICE_ID_5714C:
1998 case DEVICE_ID_5714S:
1999 case DEVICE_ID_5715C:
2000 case DEVICE_ID_5715S:
2001 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
2002 if (config1 & NVM_CFG1_FLASH_MODE)
2003 if (config1 & NVM_CFG1_BUFFERED_MODE)
2004 nvtype = BGE_NVTYPE_BUFFERED_FLASH;
2005 else
2006 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
2007 else
2008 nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
2009 break;
2010 case DEVICE_ID_5906:
2011 case DEVICE_ID_5906M:
2012 nvtype = BGE_NVTYPE_BUFFERED_FLASH;
2013 break;
2014 }
2015
2016 return (nvtype);
2017 }
2018
2019 #undef BGE_DBG
2020 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */
2021
2022 static void
2023 bge_init_recv_rule(bge_t *bgep)
2024 {
2025 bge_recv_rule_t *rulep = bgep->recv_rules;
2026 uint32_t i;
2027
2028 /*
2029 * Initialize receive rule registers.
2030 * Note that rules may persist across each bge_m_start/stop() call.
2031 */
2032 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
2033 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
2034 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
2035 }
2036 }
2037
2038 /*
2039 * Using the values captured by bge_chip_cfg_init(), and additional probes
2040 * as required, characterise the chip fully: determine the label by which
2041 * to refer to this chip, the correct settings for various registers, and
2042 * of course whether the device and/or subsystem are supported!
2043 */
2044 int bge_chip_id_init(bge_t *bgep);
2045 #pragma no_inline(bge_chip_id_init)
2046
2047 int
2048 bge_chip_id_init(bge_t *bgep)
2049 {
2050 char buf[MAXPATHLEN]; /* any risk of stack overflow? */
2051 boolean_t sys_ok;
2052 boolean_t dev_ok;
2053 chip_id_t *cidp;
2054 uint32_t subid;
2055 char *devname;
2056 char *sysname;
2057 int *ids;
2058 int err;
2059 uint_t i;
2060
2061 sys_ok = dev_ok = B_FALSE;
2062 cidp = &bgep->chipid;
2063
2064 /*
2065 * Check the PCI device ID to determine the generic chip type and
2066 * select parameters that depend on this.
2067 *
2068 * Note: because the SPARC platforms in general don't fit the
2069 * SEEPROM 'behind' the chip, the PCI revision ID register reads
2070 * as zero - which is why we use <asic_rev> rather than <revision>
2071 * below ...
2072 *
2073 * Note: in general we can't distinguish between the Copper/SerDes
2074 * versions by ID alone, as some Copper devices (e.g. some but not
2075 * all 5703Cs) have the same ID as the SerDes equivalents. So we
2076 * treat them the same here, and the MII code works out the media
2077 * type later on ...
2078 */
2079 cidp->mbuf_base = bge_mbuf_pool_base;
2080 cidp->mbuf_length = bge_mbuf_pool_len;
2081 cidp->recv_slots = BGE_RECV_SLOTS_USED;
2082 cidp->bge_dma_rwctrl = bge_dma_rwctrl;
2083 cidp->pci_type = BGE_PCI_X;
2084 cidp->statistic_type = BGE_STAT_BLK;
2085 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
2086 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
2087 cidp->mbuf_hi_water = bge_mbuf_hi_water;
2088 cidp->rx_ticks_norm = bge_rx_ticks_norm;
2089 cidp->rx_count_norm = bge_rx_count_norm;
2090 cidp->tx_ticks_norm = bge_tx_ticks_norm;
2091 cidp->tx_count_norm = bge_tx_count_norm;
2092 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT;
2093
2094 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
2095 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
2096 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
2097 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
2098
2099 cidp->msi_enabled = B_FALSE;
2100
2101 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) >
2102 MHCR_CHIP_ASIC_REV_PRODID ||
2103 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2104 MHCR_CHIP_ASIC_REV_5906 ||
2105 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2106 MHCR_CHIP_ASIC_REV_5700 ||
2107 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2108 MHCR_CHIP_ASIC_REV_5701 ||
2109 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
2110 MHCR_CHIP_ASIC_REV_5750)
2111 /*
2112 * Just a plain reset; the "check" code breaks these chips
2113 */
2114 cidp->flags |= CHIP_FLAG_NO_CHECK_RESET;
2115
2116 switch (cidp->device) {
2117 case DEVICE_ID_5717:
2118 case DEVICE_ID_5718:
2119 case DEVICE_ID_5719:
2120 case DEVICE_ID_5720:
2121 case DEVICE_ID_5724:
2122 if (cidp->device == DEVICE_ID_5717)
2123 cidp->chip_label = 5717;
2124 else if (cidp->device == DEVICE_ID_5718)
2125 cidp->chip_label = 5718;
2126 else if (cidp->device == DEVICE_ID_5719)
2127 cidp->chip_label = 5719;
2128 else if (cidp->device == DEVICE_ID_5720)
2129 cidp->chip_label = 5720;
2130 else
2131 cidp->chip_label = 5724;
2132 cidp->msi_enabled = bge_enable_msi;
2133 #ifdef __sparc
2134 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
2135 #endif
2136 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717);
2137 cidp->pci_type = BGE_PCI_E;
2138 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2139 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717;
2140 cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2141 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2142 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2143 cidp->recv_slots = BGE_RECV_SLOTS_5717;
2144 cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2145 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2146 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2147 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2148 cidp->statistic_type = BGE_STAT_REG;
2149 dev_ok = B_TRUE;
2150 break;
2151
2152 case DEVICE_ID_5700:
2153 case DEVICE_ID_5700x:
2154 cidp->chip_label = 5700;
2155 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2156 break;
2157
2158 case DEVICE_ID_5701:
2159 cidp->chip_label = 5701;
2160 dev_ok = B_TRUE;
2161 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2162 break;
2163
2164 case DEVICE_ID_5702:
2165 case DEVICE_ID_5702fe:
2166 cidp->chip_label = 5702;
2167 dev_ok = B_TRUE;
2168 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2169 cidp->pci_type = BGE_PCI;
2170 break;
2171
2172 case DEVICE_ID_5703C:
2173 case DEVICE_ID_5703S:
2174 case DEVICE_ID_5703:
2175 /*
2176 * Revision A0 of the 5703/5793 had various errata
2177 * that we can't or don't work around, so it's not
2178 * supported, but all later versions are
2179 */
2180 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2181 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2182 dev_ok = B_TRUE;
2183 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2184 break;
2185
2186 case DEVICE_ID_5704C:
2187 case DEVICE_ID_5704S:
2188 case DEVICE_ID_5704:
2189 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2190 cidp->mbuf_base = bge_mbuf_pool_base_5704;
2191 cidp->mbuf_length = bge_mbuf_pool_len_5704;
2192 dev_ok = B_TRUE;
2193 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2194 break;
2195
2196 case DEVICE_ID_5705C:
2197 case DEVICE_ID_5705M:
2198 case DEVICE_ID_5705MA3:
2199 case DEVICE_ID_5705F:
2200 case DEVICE_ID_5705_2:
2201 case DEVICE_ID_5754:
2202 if (cidp->device == DEVICE_ID_5754) {
2203 cidp->chip_label = 5754;
2204 cidp->pci_type = BGE_PCI_E;
2205 } else {
2206 cidp->chip_label = 5705;
2207 cidp->pci_type = BGE_PCI;
2208 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2209 }
2210 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2211 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2212 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2213 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2214 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2215 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2216 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2217 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2218 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2219 cidp->statistic_type = BGE_STAT_REG;
2220 dev_ok = B_TRUE;
2221 break;
2222
2223 case DEVICE_ID_5906:
2224 case DEVICE_ID_5906M:
2225 cidp->chip_label = 5906;
2226 cidp->pci_type = BGE_PCI_E;
2227 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2228 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2229 cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2230 cidp->mbuf_base = bge_mbuf_pool_base;
2231 cidp->mbuf_length = bge_mbuf_pool_len;
2232 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2233 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2234 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2235 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2236 cidp->statistic_type = BGE_STAT_REG;
2237 dev_ok = B_TRUE;
2238 break;
2239
2240 case DEVICE_ID_5753:
2241 cidp->chip_label = 5753;
2242 cidp->pci_type = BGE_PCI_E;
2243 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2244 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2245 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2246 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2247 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2248 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2249 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2250 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2251 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2252 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2253 cidp->statistic_type = BGE_STAT_REG;
2254 dev_ok = B_TRUE;
2255 break;
2256
2257 case DEVICE_ID_5755:
2258 case DEVICE_ID_5755M:
2259 cidp->chip_label = 5755;
2260 cidp->pci_type = BGE_PCI_E;
2261 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2262 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2263 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2264 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2265 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2266 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2267 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2268 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2269 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2270 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2271 if (cidp->device == DEVICE_ID_5755M)
2272 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2273 cidp->statistic_type = BGE_STAT_REG;
2274 dev_ok = B_TRUE;
2275 break;
2276
2277 case DEVICE_ID_5756M:
2278 /*
2279 * This is nearly identical to the 5755M.
2280 * (Actually reports the 5755 chip ID.)
2281 */
2282 cidp->chip_label = 5756;
2283 cidp->pci_type = BGE_PCI_E;
2284 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2285 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2286 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2287 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2288 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2289 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2290 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2291 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2292 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2293 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2294 cidp->statistic_type = BGE_STAT_REG;
2295 dev_ok = B_TRUE;
2296 break;
2297
2298 case DEVICE_ID_5787:
2299 case DEVICE_ID_5787M:
2300 cidp->chip_label = 5787;
2301 cidp->pci_type = BGE_PCI_E;
2302 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2303 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2304 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2305 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2306 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2307 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2308 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2309 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2310 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2311 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2312 cidp->statistic_type = BGE_STAT_REG;
2313 dev_ok = B_TRUE;
2314 break;
2315
2316 case DEVICE_ID_5723:
2317 case DEVICE_ID_5761:
2318 case DEVICE_ID_5761E:
2319 case DEVICE_ID_5761S:
2320 case DEVICE_ID_5761SE:
2321 case DEVICE_ID_5784M:
2322 case DEVICE_ID_57760:
2323 case DEVICE_ID_57780:
2324 case DEVICE_ID_57788:
2325 case DEVICE_ID_57790:
2326 cidp->msi_enabled = bge_enable_msi;
2327 /*
2328 * We don't use MSI for BCM5764 and BCM5785, as the
2329 * status block may fail to update when the network
2330 * traffic is heavy.
2331 */
2332 /* FALLTHRU */
2333 case DEVICE_ID_5785:
2334 case DEVICE_ID_5764:
2335 if (cidp->device == DEVICE_ID_5723)
2336 cidp->chip_label = 5723;
2337 else if (cidp->device == DEVICE_ID_5764)
2338 cidp->chip_label = 5764;
2339 else if (cidp->device == DEVICE_ID_5784M)
2340 cidp->chip_label = 5784;
2341 else if (cidp->device == DEVICE_ID_5785)
2342 cidp->chip_label = 5785;
2343 else if (cidp->device == DEVICE_ID_57760)
2344 cidp->chip_label = 57760;
2345 else if (cidp->device == DEVICE_ID_57780)
2346 cidp->chip_label = 57780;
2347 else if (cidp->device == DEVICE_ID_57788)
2348 cidp->chip_label = 57788;
2349 else if (cidp->device == DEVICE_ID_57790)
2350 cidp->chip_label = 57790;
2351 else
2352 cidp->chip_label = 5761;
2353 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2354 cidp->pci_type = BGE_PCI_E;
2355 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2356 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2357 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2358 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2359 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2360 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2361 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2362 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2363 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2364 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2365 cidp->statistic_type = BGE_STAT_REG;
2366 dev_ok = B_TRUE;
2367 break;
2368
2369 /* PCI-X device, identical to 5714 */
2370 case DEVICE_ID_5780:
2371 cidp->chip_label = 5780;
2372 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2373 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2374 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2375 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2376 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2377 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2378 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2379 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2380 cidp->statistic_type = BGE_STAT_REG;
2381 dev_ok = B_TRUE;
2382 break;
2383
2384 case DEVICE_ID_5782:
2385 /*
2386 * Apart from the label, we treat this as a 5705(?)
2387 */
2388 cidp->chip_label = 5782;
2389 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2390 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2391 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2392 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2393 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2394 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2395 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2396 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2397 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2398 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2399 cidp->statistic_type = BGE_STAT_REG;
2400 dev_ok = B_TRUE;
2401 break;
2402
2403 case DEVICE_ID_5788:
2404 /*
2405 * Apart from the label, we treat this as a 5705(?)
2406 */
2407 cidp->chip_label = 5788;
2408 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2409 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2410 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2411 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2412 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2413 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2414 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2415 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2416 cidp->statistic_type = BGE_STAT_REG;
2417 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2418 dev_ok = B_TRUE;
2419 break;
2420
2421 case DEVICE_ID_5714C:
2422 if (cidp->revision >= REVISION_ID_5714_A2)
2423 cidp->msi_enabled = bge_enable_msi;
2424 /* FALLTHRU */
2425 case DEVICE_ID_5714S:
2426 cidp->chip_label = 5714;
2427 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2428 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2429 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2430 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2431 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2432 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2433 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2434 cidp->bge_mlcr_default = bge_mlcr_default_5714;
2435 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2436 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2437 cidp->pci_type = BGE_PCI_E;
2438 cidp->statistic_type = BGE_STAT_REG;
2439 dev_ok = B_TRUE;
2440 break;
2441
2442 case DEVICE_ID_5715C:
2443 case DEVICE_ID_5715S:
2444 cidp->chip_label = 5715;
2445 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2446 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2447 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2448 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2449 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2450 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2451 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2452 cidp->bge_mlcr_default = bge_mlcr_default_5714;
2453 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2454 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2455 cidp->pci_type = BGE_PCI_E;
2456 cidp->statistic_type = BGE_STAT_REG;
2457 if (cidp->revision >= REVISION_ID_5715_A2)
2458 cidp->msi_enabled = bge_enable_msi;
2459 dev_ok = B_TRUE;
2460 break;
2461
2462 case DEVICE_ID_5721:
2463 cidp->chip_label = 5721;
2464 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2465 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2466 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2467 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2468 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2469 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2470 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2471 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2472 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2473 cidp->pci_type = BGE_PCI_E;
2474 cidp->statistic_type = BGE_STAT_REG;
2475 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2476 dev_ok = B_TRUE;
2477 break;
2478
2479 case DEVICE_ID_5722:
2480 cidp->chip_label = 5722;
2481 cidp->pci_type = BGE_PCI_E;
2482 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2483 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2484 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2485 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2486 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2487 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2488 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2489 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2490 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2491 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2492 cidp->statistic_type = BGE_STAT_REG;
2493 dev_ok = B_TRUE;
2494 break;
2495
2496 case DEVICE_ID_5751:
2497 case DEVICE_ID_5751M:
2498 cidp->chip_label = 5751;
2499 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2500 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2501 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2502 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2503 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2504 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2505 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2506 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2507 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2508 cidp->pci_type = BGE_PCI_E;
2509 cidp->statistic_type = BGE_STAT_REG;
2510 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2511 dev_ok = B_TRUE;
2512 break;
2513
2514 case DEVICE_ID_5752:
2515 case DEVICE_ID_5752M:
2516 cidp->chip_label = 5752;
2517 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2518 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2519 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2520 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2521 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2522 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2523 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2524 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2525 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2526 cidp->pci_type = BGE_PCI_E;
2527 cidp->statistic_type = BGE_STAT_REG;
2528 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2529 dev_ok = B_TRUE;
2530 break;
2531
2532 case DEVICE_ID_5789:
2533 cidp->chip_label = 5789;
2534 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2535 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2536 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2537 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2538 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2539 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2540 cidp->pci_type = BGE_PCI_E;
2541 cidp->statistic_type = BGE_STAT_REG;
2542 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2543 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2544 cidp->msi_enabled = B_TRUE;
2545 dev_ok = B_TRUE;
2546 break;
2547
2548 }
2549
2550 /*
2551 * Setup the default jumbo parameter.
2552 */
2553 cidp->ethmax_size = ETHERMAX;
2554 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2555 cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2556
2557 /*
2558 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2559 * setup below jumbo specific parameters.
2560 *
2561 * For BCM5714/5715, there is only one standard receive ring. So the
2562 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2563 * feature is enabled.
2564 */
2565 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2566 (cidp->default_mtu > BGE_DEFAULT_MTU)) {
2567 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2568 cidp->mbuf_lo_water_rdma =
2569 RDMA_MBUF_LOWAT_5714_JUMBO;
2570 cidp->mbuf_lo_water_rmac =
2571 MAC_RX_MBUF_LOWAT_5714_JUMBO;
2572 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2573 cidp->jumbo_slots = 0;
2574 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2575 } else {
2576 cidp->mbuf_lo_water_rdma =
2577 RDMA_MBUF_LOWAT_JUMBO;
2578 cidp->mbuf_lo_water_rmac =
2579 MAC_RX_MBUF_LOWAT_JUMBO;
2580 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2581 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2582 }
2583 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2584 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2585 cidp->ethmax_size = cidp->default_mtu +
2586 sizeof (struct ether_header);
2587 }
2588
2589 /*
2590 * Identify the NV memory type: SEEPROM or Flash?
2591 */
2592 cidp->nvtype = bge_nvmem_id(bgep);
2593
2594 /*
2595 * Now, we want to check whether this device is part of a
2596 * supported subsystem (e.g., on the motherboard of a Sun
2597 * branded platform).
2598 *
2599 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2600 */
2601 if (cidp->subven == VENDOR_ID_SUN)
2602 sys_ok = B_TRUE;
2603
2604 /*
2605 * Rule 2: If it's on the list on known subsystems, then it's OK.
2606 * Note: 0x14e41647 should *not* appear in the list, but the code
2607 * doesn't enforce that.
2608 */
2609 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2610 DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2611 if (err == DDI_PROP_SUCCESS) {
2612 /*
2613 * Got the list; scan for a matching subsystem vendor/device
2614 */
2615 subid = (cidp->subven << 16) | cidp->subdev;
2616 while (i--)
2617 if (ids[i] == subid)
2618 sys_ok = B_TRUE;
2619 ddi_prop_free(ids);
2620 }
2621
2622 /*
2623 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2624 *
2625 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2626 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore,
2627 * we have to check specially for the exact device paths to the
2628 * motherboard devices on those platforms ;-(
2629 *
2630 * Note: we can't just use the "supported-subsystems" mechanism
2631 * above, because the entry would have to be 0x14e41647 -- which
2632 * would then accept *any* plugin card that *didn't* contain a
2633 * (valid) SEEPROM ;-(
2634 */
2635 sysname = ddi_node_name(ddi_root_node());
2636 devname = ddi_pathname(bgep->devinfo, buf);
2637 ASSERT(strlen(devname) > 0);
2638 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */
2639 if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2640 sys_ok = B_TRUE;
2641 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */
2642 if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2643 sys_ok = B_TRUE;
2644
2645 /*
2646 * Now check what we've discovered: is this truly a supported
2647 * chip on (the motherboard of) a supported platform?
2648 *
2649 * Possible problems here:
2650 * 1) it's a completely unheard-of chip
2651 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2652 * 3) it's a chip we would support if it were on the motherboard
2653 * of a Sun platform, but this one isn't ;-(
2654 */
2655 if (cidp->chip_label == 0)
2656 bge_problem(bgep,
2657 "Device 'pci%04x,%04x' not recognized (%d?)",
2658 cidp->vendor, cidp->device, cidp->device);
2659 else if (!dev_ok)
2660 bge_problem(bgep,
2661 "Device 'pci%04x,%04x' (%d) revision %d not supported",
2662 cidp->vendor, cidp->device, cidp->chip_label,
2663 cidp->revision);
2664 #if BGE_DEBUGGING
2665 else if (!sys_ok)
2666 bge_problem(bgep,
2667 "%d-based subsystem 'pci%04x,%04x' not validated",
2668 cidp->chip_label, cidp->subven, cidp->subdev);
2669 #endif
2670 else
2671 cidp->flags |= CHIP_FLAG_SUPPORTED;
2672 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2673 return (EIO);
2674 return (0);
2675 }
2676
2677 void
2678 bge_chip_msi_trig(bge_t *bgep)
2679 {
2680 uint32_t regval;
2681
2682 regval = bgep->param_msi_cnt<<4;
2683 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2684 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2685 }
2686
2687 /*
2688 * Various registers that control the chip's internal engines (state
2689 * machines) have a <reset> and <enable> bits (fortunately, in the
2690 * same place in each such register :-).
2691 *
2692 * To reset the state machine, the <reset> bit must be written with 1;
2693 * it will then read back as 1 while the reset is in progress, but
2694 * self-clear to 0 when the reset completes.
2695 *
2696 * To enable a state machine, one must set the <enable> bit, which
2697 * will continue to read back as 0 until the state machine is running.
2698 *
2699 * To disable a state machine, the <enable> bit must be cleared, but
2700 * it will continue to read back as 1 until the state machine actually
2701 * stops.
2702 *
2703 * This routine implements polling for completion of a reset, enable
2704 * or disable operation, returning B_TRUE on success (bit reached the
2705 * required state) or B_FALSE on timeout (200*100us == 20ms).
2706 */
2707 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2708 uint32_t mask, uint32_t val);
2709 #pragma no_inline(bge_chip_poll_engine)
2710
2711 static boolean_t
2712 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2713 uint32_t mask, uint32_t val)
2714 {
2715 uint32_t regval;
2716 uint32_t n;
2717
2718 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2719 (void *)bgep, regno, mask, val));
2720
2721 for (n = 200; n; --n) {
2722 regval = bge_reg_get32(bgep, regno);
2723 if ((regval & mask) == val)
2724 return (B_TRUE);
2725 drv_usecwait(100);
2726 }
2727
2728 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno);
2729 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2730 return (B_FALSE);
2731 }
2732
2733 /*
2734 * Various registers that control the chip's internal engines (state
2735 * machines) have a <reset> bit (fortunately, in the same place in
2736 * each such register :-). To reset the state machine, this bit must
2737 * be written with 1; it will then read back as 1 while the reset is
2738 * in progress, but self-clear to 0 when the reset completes.
2739 *
2740 * This code sets the bit, then polls for it to read back as zero.
2741 * The return value is B_TRUE on success (reset bit cleared itself),
2742 * or B_FALSE if the state machine didn't recover :(
2743 *
2744 * NOTE: the Core reset is similar to other resets, except that we
2745 * can't poll for completion, since the Core reset disables memory
2746 * access! So we just have to assume that it will all complete in
2747 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5.
2748 */
2749 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2750 #pragma no_inline(bge_chip_reset_engine)
2751
2752 static boolean_t
2753 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2754 {
2755 uint32_t regval;
2756 uint32_t val32;
2757
2758 regval = bge_reg_get32(bgep, regno);
2759
2760 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2761 (void *)bgep, regno));
2762 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2763 regno, regval));
2764
2765 regval |= STATE_MACHINE_RESET_BIT;
2766
2767 switch (regno) {
2768 case MISC_CONFIG_REG:
2769 /*
2770 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2771 * resetting PCIE block and bringing PCIE link down, bit 29
2772 * in the register needs to be set first, and then set it again
2773 * while the reset bit is written.
2774 * See:P500 of 57xx-PG102-RDS.pdf.
2775 */
2776 if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2777 DEVICE_5717_SERIES_CHIPSETS(bgep)||
2778 DEVICE_5721_SERIES_CHIPSETS(bgep)||
2779 DEVICE_5723_SERIES_CHIPSETS(bgep)||
2780 DEVICE_5714_SERIES_CHIPSETS(bgep)||
2781 DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2782 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2783 if (bgep->chipid.pci_type == BGE_PCI_E) {
2784 if (bgep->chipid.asic_rev ==
2785 MHCR_CHIP_REV_5751_A0 ||
2786 bgep->chipid.asic_rev ==
2787 MHCR_CHIP_REV_5721_A0 ||
2788 bgep->chipid.asic_rev ==
2789 MHCR_CHIP_REV_5755_A0) {
2790 val32 = bge_reg_get32(bgep,
2791 PHY_TEST_CTRL_REG);
2792 if (val32 == (PHY_PCIE_SCRAM_MODE |
2793 PHY_PCIE_LTASS_MODE))
2794 bge_reg_put32(bgep,
2795 PHY_TEST_CTRL_REG,
2796 PHY_PCIE_SCRAM_MODE);
2797 val32 = pci_config_get32
2798 (bgep->cfg_handle,
2799 PCI_CONF_BGE_CLKCTL);
2800 val32 |= CLKCTL_PCIE_A0_FIX;
2801 pci_config_put32(bgep->cfg_handle,
2802 PCI_CONF_BGE_CLKCTL, val32);
2803 }
2804 bge_reg_set32(bgep, regno,
2805 MISC_CONFIG_GRC_RESET_DISABLE);
2806 regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2807 }
2808 }
2809
2810 /*
2811 * Special case - causes Core reset
2812 *
2813 * On SPARC v9 we want to ensure that we don't start
2814 * timing until the I/O access has actually reached
2815 * the chip, otherwise we might make the next access
2816 * too early. And we can't just force the write out
2817 * by following it with a read (even to config space)
2818 * because that would cause the fault we're trying
2819 * to avoid. Hence the need for membar_sync() here.
2820 */
2821 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2822 #ifdef __sparcv9
2823 membar_sync();
2824 #endif /* __sparcv9 */
2825 /*
2826 * On some platforms,system need about 300us for
2827 * link setup.
2828 */
2829 drv_usecwait(300);
2830 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2831 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
2832 bge_reg_clr32(
2833 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
2834 }
2835
2836 if (bgep->chipid.pci_type == BGE_PCI_E) {
2837 /* PCI-E device need more reset time */
2838 drv_usecwait(120000);
2839
2840 /* Set PCIE max payload size and clear error status. */
2841 if ((bgep->chipid.chip_label == 5721) ||
2842 (bgep->chipid.chip_label == 5751) ||
2843 (bgep->chipid.chip_label == 5752) ||
2844 (bgep->chipid.chip_label == 5789) ||
2845 (bgep->chipid.chip_label == 5906)) {
2846 pci_config_put16(bgep->cfg_handle,
2847 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2848 pci_config_put16(bgep->cfg_handle,
2849 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2850 }
2851
2852 if ((bgep->chipid.chip_label == 5723) ||
2853 (bgep->chipid.chip_label == 5761)) {
2854 pci_config_put16(bgep->cfg_handle,
2855 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
2856 pci_config_put16(bgep->cfg_handle,
2857 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
2858 }
2859 }
2860
2861 BGE_PCICHK(bgep);
2862 return (B_TRUE);
2863
2864 default:
2865 bge_reg_put32(bgep, regno, regval);
2866 return (bge_chip_poll_engine(bgep, regno,
2867 STATE_MACHINE_RESET_BIT, 0));
2868 }
2869 }
2870
2871 /*
2872 * Various registers that control the chip's internal engines (state
2873 * machines) have an <enable> bit (fortunately, in the same place in
2874 * each such register :-). To stop the state machine, this bit must
2875 * be written with 0, then polled to see when the state machine has
2876 * actually stopped.
2877 *
2878 * The return value is B_TRUE on success (enable bit cleared), or
2879 * B_FALSE if the state machine didn't stop :(
2880 */
2881 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2882 uint32_t morebits);
2883 #pragma no_inline(bge_chip_disable_engine)
2884
2885 static boolean_t
2886 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2887 {
2888 uint32_t regval;
2889
2890 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2891 (void *)bgep, regno, morebits));
2892
2893 switch (regno) {
2894 case FTQ_RESET_REG:
2895 /*
2896 * For Schumacher's bugfix CR6490108
2897 */
2898 #ifdef BGE_IPMI_ASF
2899 #ifdef BGE_NETCONSOLE
2900 if (bgep->asf_enabled)
2901 return (B_TRUE);
2902 #endif
2903 #endif
2904 /*
2905 * Not quite like the others; it doesn't
2906 * have an <enable> bit, but instead we
2907 * have to set and then clear all the bits
2908 */
2909 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2910 drv_usecwait(100);
2911 bge_reg_put32(bgep, regno, 0);
2912 return (B_TRUE);
2913
2914 default:
2915 regval = bge_reg_get32(bgep, regno);
2916 regval &= ~STATE_MACHINE_ENABLE_BIT;
2917 regval &= ~morebits;
2918 bge_reg_put32(bgep, regno, regval);
2919 return (bge_chip_poll_engine(bgep, regno,
2920 STATE_MACHINE_ENABLE_BIT, 0));
2921 }
2922 }
2923
2924 /*
2925 * Various registers that control the chip's internal engines (state
2926 * machines) have an <enable> bit (fortunately, in the same place in
2927 * each such register :-). To start the state machine, this bit must
2928 * be written with 1, then polled to see when the state machine has
2929 * actually started.
2930 *
2931 * The return value is B_TRUE on success (enable bit set), or
2932 * B_FALSE if the state machine didn't start :(
2933 */
2934 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2935 uint32_t morebits);
2936 #pragma no_inline(bge_chip_enable_engine)
2937
2938 static boolean_t
2939 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2940 {
2941 uint32_t regval;
2942
2943 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2944 (void *)bgep, regno, morebits));
2945
2946 switch (regno) {
2947 case FTQ_RESET_REG:
2948 #ifdef BGE_IPMI_ASF
2949 #ifdef BGE_NETCONSOLE
2950 if (bgep->asf_enabled)
2951 return (B_TRUE);
2952 #endif
2953 #endif
2954 /*
2955 * Not quite like the others; it doesn't
2956 * have an <enable> bit, but instead we
2957 * have to set and then clear all the bits
2958 */
2959 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2960 drv_usecwait(100);
2961 bge_reg_put32(bgep, regno, 0);
2962 return (B_TRUE);
2963
2964 default:
2965 regval = bge_reg_get32(bgep, regno);
2966 regval |= STATE_MACHINE_ENABLE_BIT;
2967 regval |= morebits;
2968 bge_reg_put32(bgep, regno, regval);
2969 return (bge_chip_poll_engine(bgep, regno,
2970 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2971 }
2972 }
2973
2974 /*
2975 * Reprogram the Ethernet, Transmit, and Receive MAC
2976 * modes to match the param_* variables
2977 */
2978 void bge_sync_mac_modes(bge_t *bgep);
2979 #pragma no_inline(bge_sync_mac_modes)
2980
2981 void
2982 bge_sync_mac_modes(bge_t *bgep)
2983 {
2984 uint32_t macmode;
2985 uint32_t regval;
2986
2987 ASSERT(mutex_owned(bgep->genlock));
2988
2989 /*
2990 * Reprogram the Ethernet MAC mode ...
2991 */
2992 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2993 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2994 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2995 if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2996 macmode |= ETHERNET_MODE_LINK_POLARITY;
2997 else
2998 macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2999 else
3000 macmode |= ETHERNET_MODE_LINK_POLARITY;
3001 macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
3002 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
3003 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
3004 if (DEVICE_5714_SERIES_CHIPSETS(bgep))
3005 macmode |= ETHERNET_MODE_PORTMODE_GMII;
3006 else
3007 macmode |= ETHERNET_MODE_PORTMODE_TBI;
3008 } else if (bgep->param_link_speed == 10 ||
3009 bgep->param_link_speed == 100)
3010 macmode |= ETHERNET_MODE_PORTMODE_MII;
3011 else
3012 macmode |= ETHERNET_MODE_PORTMODE_GMII;
3013 if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
3014 macmode |= ETHERNET_MODE_HALF_DUPLEX;
3015 else
3016 macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
3017 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
3018 macmode |= ETHERNET_MODE_MAC_LOOPBACK;
3019 else
3020 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
3021 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
3022 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
3023 (void *)bgep, regval, macmode));
3024
3025 /*
3026 * ... the Transmit MAC mode ...
3027 */
3028 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
3029 if (bgep->param_link_tx_pause)
3030 macmode |= TRANSMIT_MODE_FLOW_CONTROL;
3031 else
3032 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
3033 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
3034 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
3035 (void *)bgep, regval, macmode));
3036
3037 /*
3038 * ... and the Receive MAC mode
3039 */
3040 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
3041 if (bgep->param_link_rx_pause)
3042 macmode |= RECEIVE_MODE_FLOW_CONTROL;
3043 else
3044 macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
3045 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
3046 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
3047 (void *)bgep, regval, macmode));
3048
3049 /*
3050 * For BCM5785, we need to configure the link status in the MI Status
3051 * register with a write command when auto-polling is disabled.
3052 */
3053 if (bgep->chipid.device == DEVICE_ID_5785)
3054 if (bgep->param_link_speed == 10)
3055 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
3056 | MI_STATUS_10MBPS);
3057 else
3058 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
3059 }
3060
3061 /*
3062 * bge_chip_sync() -- program the chip with the unicast MAC address,
3063 * the multicast hash table, the required level of promiscuity, and
3064 * the current loopback mode ...
3065 */
3066 #ifdef BGE_IPMI_ASF
3067 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
3068 #else
3069 int bge_chip_sync(bge_t *bgep);
3070 #endif
3071 #pragma no_inline(bge_chip_sync)
3072
3073 int
3074 #ifdef BGE_IPMI_ASF
3075 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
3076 #else
3077 bge_chip_sync(bge_t *bgep)
3078 #endif
3079 {
3080 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
3081 boolean_t promisc;
3082 uint64_t macaddr;
3083 uint32_t fill = 0;
3084 int i, j;
3085 int retval = DDI_SUCCESS;
3086
3087 BGE_TRACE(("bge_chip_sync($%p)",
3088 (void *)bgep));
3089
3090 ASSERT(mutex_owned(bgep->genlock));
3091
3092 promisc = B_FALSE;
3093 fill = ~(uint32_t)0;
3094
3095 if (bgep->promisc)
3096 promisc = B_TRUE;
3097 else
3098 fill = (uint32_t)0;
3099
3100 /*
3101 * If the TX/RX MAC engines are already running, we should stop
3102 * them (and reset the RX engine) before changing the parameters.
3103 * If they're not running, this will have no effect ...
3104 *
3105 * NOTE: this is currently disabled by default because stopping
3106 * and restarting the Tx engine may cause an outgoing packet in
3107 * transit to be truncated. Also, stopping and restarting the
3108 * Rx engine seems to not work correctly on the 5705. Testing
3109 * has not (yet!) revealed any problems with NOT stopping and
3110 * restarting these engines (and Broadcom say their drivers don't
3111 * do this), but if it is found to cause problems, this variable
3112 * can be patched to re-enable the old behaviour ...
3113 */
3114 if (bge_stop_start_on_sync) {
3115 #ifdef BGE_IPMI_ASF
3116 if (!bgep->asf_enabled) {
3117 if (!bge_chip_disable_engine(bgep,
3118 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3119 retval = DDI_FAILURE;
3120 } else {
3121 if (!bge_chip_disable_engine(bgep,
3122 RECEIVE_MAC_MODE_REG, 0))
3123 retval = DDI_FAILURE;
3124 }
3125 #else
3126 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
3127 RECEIVE_MODE_KEEP_VLAN_TAG))
3128 retval = DDI_FAILURE;
3129 #endif
3130 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3131 retval = DDI_FAILURE;
3132 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3133 retval = DDI_FAILURE;
3134 }
3135
3136 /*
3137 * Reprogram the hashed multicast address table ...
3138 */
3139 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3140 bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3141
3142 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3143 bge_reg_put32(bgep, MAC_HASH_REG(i),
3144 bgep->mcast_hash[i] | fill);
3145
3146 #ifdef BGE_IPMI_ASF
3147 if (!bgep->asf_enabled || !asf_keeplive) {
3148 #endif
3149 /*
3150 * Transform the MAC address(es) from host to chip format, then
3151 * reprogram the transmit random backoff seed and the unicast
3152 * MAC address(es) ...
3153 */
3154 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
3155 for (i = 0, macaddr = 0ull;
3156 i < ETHERADDRL; ++i) {
3157 macaddr <<= 8;
3158 macaddr |= bgep->curr_addr[j].addr[i];
3159 }
3160 fill += (macaddr >> 16) + (macaddr & 0xffffffff);
3161 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3162
3163 BGE_DEBUG(("bge_chip_sync($%p) "
3164 "setting MAC address %012llx",
3165 (void *)bgep, macaddr));
3166 }
3167 #ifdef BGE_IPMI_ASF
3168 }
3169 #endif
3170 /*
3171 * Set random seed of backoff interval
3172 * - Writing zero means no backoff interval
3173 */
3174 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
3175 if (fill == 0)
3176 fill = 1;
3177 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3178
3179 /*
3180 * Set or clear the PROMISCUOUS mode bit
3181 */
3182 opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3183 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3184
3185 /*
3186 * Sync the rest of the MAC modes too ...
3187 */
3188 bge_sync_mac_modes(bgep);
3189
3190 /*
3191 * Restart RX/TX MAC engines if required ...
3192 */
3193 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3194 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3195 retval = DDI_FAILURE;
3196 #ifdef BGE_IPMI_ASF
3197 if (!bgep->asf_enabled) {
3198 if (!bge_chip_enable_engine(bgep,
3199 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3200 retval = DDI_FAILURE;
3201 } else {
3202 if (!bge_chip_enable_engine(bgep,
3203 RECEIVE_MAC_MODE_REG, 0))
3204 retval = DDI_FAILURE;
3205 }
3206 #else
3207 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3208 RECEIVE_MODE_KEEP_VLAN_TAG))
3209 retval = DDI_FAILURE;
3210 #endif
3211 }
3212 return (retval);
3213 }
3214
3215 /*
3216 * This array defines the sequence of state machine control registers
3217 * in which the <enable> bit must be cleared to bring the chip to a
3218 * clean stop. Taken from Broadcom document 570X-PG102-R, p116.
3219 */
3220 static bge_regno_t shutdown_engine_regs[] = {
3221 RECEIVE_MAC_MODE_REG,
3222 RCV_BD_INITIATOR_MODE_REG,
3223 RCV_LIST_PLACEMENT_MODE_REG,
3224 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */
3225 RCV_DATA_BD_INITIATOR_MODE_REG,
3226 RCV_DATA_COMPLETION_MODE_REG,
3227 RCV_BD_COMPLETION_MODE_REG,
3228
3229 SEND_BD_SELECTOR_MODE_REG,
3230 SEND_BD_INITIATOR_MODE_REG,
3231 SEND_DATA_INITIATOR_MODE_REG,
3232 READ_DMA_MODE_REG,
3233 SEND_DATA_COMPLETION_MODE_REG,
3234 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */
3235 SEND_BD_COMPLETION_MODE_REG,
3236 TRANSMIT_MAC_MODE_REG,
3237
3238 HOST_COALESCE_MODE_REG,
3239 WRITE_DMA_MODE_REG,
3240 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */
3241 FTQ_RESET_REG, /* special - see code */
3242 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */
3243 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */
3244 BGE_REGNO_NONE /* terminator */
3245 };
3246
3247 #ifndef __sparc
3248 static bge_regno_t quiesce_regs[] = {
3249 READ_DMA_MODE_REG,
3250 DMA_COMPLETION_MODE_REG,
3251 WRITE_DMA_MODE_REG,
3252 BGE_REGNO_NONE
3253 };
3254
3255 void bge_chip_stop_nonblocking(bge_t *bgep);
3256 #pragma no_inline(bge_chip_stop_nonblocking)
3257
3258 /*
3259 * This function is called by bge_quiesce(). We
3260 * turn off all the DMA engines here.
3261 */
3262 void
3263 bge_chip_stop_nonblocking(bge_t *bgep)
3264 {
3265 bge_regno_t *rbp;
3266
3267 /*
3268 * Flag that no more activity may be initiated
3269 */
3270 bgep->progress &= ~PROGRESS_READY;
3271
3272 rbp = quiesce_regs;
3273 while (*rbp != BGE_REGNO_NONE) {
3274 (void) bge_chip_disable_engine(bgep, *rbp, 0);
3275 ++rbp;
3276 }
3277
3278 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3279 }
3280
3281 #endif
3282
3283 /*
3284 * bge_chip_stop() -- stop all chip processing
3285 *
3286 * If the <fault> parameter is B_TRUE, we're stopping the chip because
3287 * we've detected a problem internally; otherwise, this is a normal
3288 * (clean) stop (at user request i.e. the last STREAM has been closed).
3289 */
3290 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3291 #pragma no_inline(bge_chip_stop)
3292
3293 void
3294 bge_chip_stop(bge_t *bgep, boolean_t fault)
3295 {
3296 bge_regno_t regno;
3297 bge_regno_t *rbp;
3298 boolean_t ok;
3299
3300 BGE_TRACE(("bge_chip_stop($%p)",
3301 (void *)bgep));
3302
3303 ASSERT(mutex_owned(bgep->genlock));
3304
3305 rbp = shutdown_engine_regs;
3306 /*
3307 * When driver try to shutdown the BCM5705/5788/5721/5751/
3308 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
3309 * -ory arbiter should not be disabled.
3310 */
3311 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
3312 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3313 ok &= bge_chip_disable_engine(bgep, regno, 0);
3314 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
3315 (regno != DMA_COMPLETION_MODE_REG) &&
3316 (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
3317 (regno != BUFFER_MANAGER_MODE_REG) &&
3318 (regno != MEMORY_ARBITER_MODE_REG))
3319 ok &= bge_chip_disable_engine(bgep,
3320 regno, 0);
3321 }
3322
3323 if (!ok && !fault)
3324 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3325
3326 /*
3327 * Finally, disable (all) MAC events & clear the MAC status
3328 */
3329 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3330 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3331
3332 /*
3333 * if we're stopping the chip because of a detected fault then do
3334 * appropriate actions
3335 */
3336 if (fault) {
3337 if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3338 bgep->bge_chip_state = BGE_CHIP_FAULT;
3339 if (!bgep->manual_reset)
3340 ddi_fm_service_impact(bgep->devinfo,
3341 DDI_SERVICE_LOST);
3342 if (bgep->bge_dma_error) {
3343 /*
3344 * need to free buffers in case the fault was
3345 * due to a memory error in a buffer - got to
3346 * do a fair bit of tidying first
3347 */
3348 if (bgep->progress & PROGRESS_KSTATS) {
3349 bge_fini_kstats(bgep);
3350 bgep->progress &= ~PROGRESS_KSTATS;
3351 }
3352 if (bgep->progress & PROGRESS_INTR) {
3353 bge_intr_disable(bgep);
3354 rw_enter(bgep->errlock, RW_WRITER);
3355 bge_fini_rings(bgep);
3356 rw_exit(bgep->errlock);
3357 bgep->progress &= ~PROGRESS_INTR;
3358 }
3359 if (bgep->progress & PROGRESS_BUFS) {
3360 bge_free_bufs(bgep);
3361 bgep->progress &= ~PROGRESS_BUFS;
3362 }
3363 bgep->bge_dma_error = B_FALSE;
3364 }
3365 }
3366 } else
3367 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3368 }
3369
3370 /*
3371 * Poll for completion of chip's ROM firmware; also, at least on the
3372 * first time through, find and return the hardware MAC address, if any.
3373 */
3374 static uint64_t bge_poll_firmware(bge_t *bgep);
3375 #pragma no_inline(bge_poll_firmware)
3376
3377 static uint64_t
3378 bge_poll_firmware(bge_t *bgep)
3379 {
3380 uint64_t magic;
3381 uint64_t mac;
3382 uint32_t gen, val;
3383 uint32_t i;
3384
3385 /*
3386 * Step 19: poll for firmware completion (GENCOMM port set
3387 * to the ones complement of T3_MAGIC_NUMBER).
3388 *
3389 * While we're at it, we also read the MAC address register;
3390 * at some stage the firmware will load this with the
3391 * factory-set value.
3392 *
3393 * When both the magic number and the MAC address are set,
3394 * we're done; but we impose a time limit of one second
3395 * (1000*1000us) in case the firmware fails in some fashion
3396 * or the SEEPROM that provides that MAC address isn't fitted.
3397 *
3398 * After the first time through (chip state != INITIAL), we
3399 * don't need the MAC address to be set (we've already got it
3400 * or not, from the first time), so we don't wait for it, but
3401 * we still have to wait for the T3_MAGIC_NUMBER.
3402 *
3403 * Note: the magic number is only a 32-bit quantity, but the NIC
3404 * memory is 64-bit (and big-endian) internally. Addressing the
3405 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3406 * it work correctly on both big- and little-endian hosts.
3407 */
3408 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3409 MHCR_CHIP_ASIC_REV_5906) {
3410 for (i = 0; i < 1000; ++i) {
3411 drv_usecwait(1000);
3412 val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3413 if (val & VCPU_INIT_DONE)
3414 break;
3415 }
3416 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3417 (void *)bgep, i));
3418 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3419 } else {
3420 for (i = 0; i < 1000; ++i) {
3421 drv_usecwait(1000);
3422 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3423 #ifdef BGE_IPMI_ASF
3424 if (!bgep->asf_enabled) {
3425 #endif
3426 if (gen != ~T3_MAGIC_NUMBER)
3427 continue;
3428 #ifdef BGE_IPMI_ASF
3429 }
3430 #endif
3431 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3432 if (mac != 0ULL)
3433 break;
3434 if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3435 break;
3436 }
3437 }
3438
3439 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3440 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3441 (void *)bgep, gen, i));
3442 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3443 mac, magic));
3444
3445 return (mac);
3446 }
3447
3448 /*
3449 * Maximum times of trying to get the NVRAM access lock
3450 * by calling bge_nvmem_acquire()
3451 */
3452 #define MAX_TRY_NVMEM_ACQUIRE 10000
3453
3454 #ifdef BGE_IPMI_ASF
3455 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3456 #else
3457 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3458 #endif
3459 #pragma no_inline(bge_chip_reset)
3460
3461 int
3462 #ifdef BGE_IPMI_ASF
3463 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3464 #else
3465 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3466 #endif
3467 {
3468 chip_id_t chipid;
3469 uint64_t mac;
3470 uint64_t magic;
3471 uint32_t modeflags;
3472 uint32_t mhcr;
3473 uint32_t sx0;
3474 uint32_t i, tries;
3475 #ifdef BGE_IPMI_ASF
3476 uint32_t mailbox;
3477 #endif
3478 int retval = DDI_SUCCESS;
3479
3480 BGE_TRACE(("bge_chip_reset($%p, %d)",
3481 (void *)bgep, enable_dma));
3482
3483 ASSERT(mutex_owned(bgep->genlock));
3484
3485 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3486 (void *)bgep, enable_dma, bgep->bge_chip_state));
3487
3488 /*
3489 * Do we need to stop the chip cleanly before resetting?
3490 */
3491 switch (bgep->bge_chip_state) {
3492 default:
3493 _NOTE(NOTREACHED)
3494 return (DDI_FAILURE);
3495
3496 case BGE_CHIP_INITIAL:
3497 case BGE_CHIP_STOPPED:
3498 case BGE_CHIP_RESET:
3499 break;
3500
3501 case BGE_CHIP_RUNNING:
3502 case BGE_CHIP_ERROR:
3503 case BGE_CHIP_FAULT:
3504 bge_chip_stop(bgep, B_FALSE);
3505 break;
3506 }
3507
3508 #ifdef BGE_IPMI_ASF
3509 if (bgep->asf_enabled) {
3510 #ifdef __sparc
3511 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3512 MHCR_ENABLE_TAGGED_STATUS_MODE |
3513 MHCR_MASK_INTERRUPT_MODE |
3514 MHCR_CLEAR_INTERRUPT_INTA |
3515 MHCR_ENABLE_ENDIAN_WORD_SWAP |
3516 MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3517
3518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3520
3521 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3522 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3523 0);
3524 #else
3525 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3526 MHCR_ENABLE_TAGGED_STATUS_MODE |
3527 MHCR_MASK_INTERRUPT_MODE |
3528 MHCR_MASK_PCI_INT_OUTPUT |
3529 MHCR_CLEAR_INTERRUPT_INTA;
3530 #endif
3531 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3532 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3533 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3534 MEMORY_ARBITER_ENABLE);
3535 if (asf_mode == ASF_MODE_INIT) {
3536 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3537 } else if (asf_mode == ASF_MODE_SHUTDOWN) {
3538 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3539 }
3540 }
3541 #endif
3542 /*
3543 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3544 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3545 *
3546 * Before reset Core clock,it is
3547 * also required to initialize the Memory Arbiter as specified in step9
3548 * and Misc Host Control Register as specified in step-13
3549 * Step 4-5: reset Core clock & wait for completion
3550 * Steps 6-8: are done by bge_chip_cfg_init()
3551 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3552 */
3553 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3554 retval = DDI_FAILURE;
3555
3556 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3557 MHCR_ENABLE_TAGGED_STATUS_MODE |
3558 MHCR_ENABLE_PCI_STATE_WRITE |
3559 MHCR_MASK_INTERRUPT_MODE |
3560 MHCR_CLEAR_INTERRUPT_INTA;
3561
3562 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3563 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3564
3565 #ifdef _BIG_ENDIAN
3566 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3567 #endif /* _BIG_ENDIAN */
3568 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3569 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3570 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3571 #ifdef BGE_IPMI_ASF
3572 if (bgep->asf_enabled)
3573 bgep->asf_wordswapped = B_FALSE;
3574 #endif
3575
3576 if (DEVICE_IS_5755_PLUS(bgep) ||
3577 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3578 MHCR_CHIP_ASIC_REV_5752)
3579 bge_reg_put32(bgep, GRC_FASTBOOT_PC, 0);
3580
3581 /*
3582 * NVRAM Corruption Workaround
3583 */
3584 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3585 if (bge_nvmem_acquire(bgep) != EAGAIN)
3586 break;
3587 if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3588 BGE_DEBUG(("%s: fail to acquire nvram lock",
3589 bgep->ifname));
3590
3591 #ifdef BGE_IPMI_ASF
3592 if (!bgep->asf_enabled) {
3593 #endif
3594 magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3595 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3596 #ifdef BGE_IPMI_ASF
3597 }
3598 #endif
3599
3600 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3601 retval = DDI_FAILURE;
3602 bge_chip_cfg_init(bgep, &chipid, enable_dma);
3603
3604 /*
3605 * Step 8a: This may belong elsewhere, but BCM5721 needs
3606 * a bit set to avoid a fifo overflow/underflow bug.
3607 */
3608 if ((bgep->chipid.chip_label == 5721) ||
3609 (bgep->chipid.chip_label == 5751) ||
3610 (bgep->chipid.chip_label == 5752) ||
3611 (bgep->chipid.chip_label == 5755) ||
3612 (bgep->chipid.chip_label == 5756) ||
3613 (bgep->chipid.chip_label == 5789) ||
3614 (bgep->chipid.chip_label == 5906))
3615 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3616
3617
3618 /*
3619 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3620 * not be changed.
3621 */
3622 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3623 retval = DDI_FAILURE;
3624
3625 /*
3626 * Steps 10-11: configure PIO endianness options and
3627 * enable indirect register access -- already done
3628 * Steps 12-13: enable writing to the PCI state & clock
3629 * control registers -- not required; we aren't going to
3630 * use those features.
3631 * Steps 14-15: Configure DMA endianness options. See
3632 * the comments on the setting of the MHCR above.
3633 */
3634 #ifdef _BIG_ENDIAN
3635 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3636 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3637 #else
3638 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3639 #endif /* _BIG_ENDIAN */
3640 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3641 MHCR_CHIP_ASIC_REV_5720)
3642 modeflags |=
3643 MODE_BYTE_SWAP_B2HRX_DATA | MODE_WORD_SWAP_B2HRX_DATA |
3644 MODE_B2HRX_ENABLE | MODE_HTX2B_ENABLE;
3645 #ifdef BGE_IPMI_ASF
3646 if (bgep->asf_enabled)
3647 modeflags |= MODE_HOST_STACK_UP;
3648 #endif
3649 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3650
3651 #ifdef BGE_IPMI_ASF
3652 if (bgep->asf_enabled) {
3653 #ifdef __sparc
3654 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3655 MEMORY_ARBITER_ENABLE |
3656 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3657 #endif
3658
3659 #ifdef BGE_NETCONSOLE
3660 if (!bgep->asf_newhandshake) {
3661 if ((asf_mode == ASF_MODE_INIT) ||
3662 (asf_mode == ASF_MODE_POST_INIT)) {
3663 bge_asf_post_reset_old_mode(bgep,
3664 BGE_INIT_RESET);
3665 } else {
3666 bge_asf_post_reset_old_mode(bgep,
3667 BGE_SHUTDOWN_RESET);
3668 }
3669 }
3670 #endif
3671
3672 /* Wait for NVRAM init */
3673 i = 0;
3674 drv_usecwait(5000);
3675 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3676
3677 while ((mailbox != (uint32_t)
3678 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3679 (i < 10000)) {
3680 drv_usecwait(100);
3681 mailbox = bge_nic_get32(bgep,
3682 BGE_FIRMWARE_MAILBOX);
3683 i++;
3684 }
3685
3686 #ifndef BGE_NETCONSOLE
3687 if (!bgep->asf_newhandshake) {
3688 if ((asf_mode == ASF_MODE_INIT) ||
3689 (asf_mode == ASF_MODE_POST_INIT)) {
3690
3691 bge_asf_post_reset_old_mode(bgep,
3692 BGE_INIT_RESET);
3693 } else {
3694 bge_asf_post_reset_old_mode(bgep,
3695 BGE_SHUTDOWN_RESET);
3696 }
3697 }
3698 #endif
3699 }
3700 #endif
3701 /*
3702 * Steps 16-17: poll for firmware completion
3703 */
3704 mac = bge_poll_firmware(bgep);
3705
3706 /*
3707 * Step 18: enable external memory -- doesn't apply.
3708 *
3709 * However we take the opportunity to set the MLCR anyway, as
3710 * this register also controls the SEEPROM auto-access method
3711 * which we may want to use later ...
3712 *
3713 * The proper value here depends on the way the chip is wired
3714 * into the circuit board, as this register *also* controls which
3715 * of the "Miscellaneous I/O" pins are driven as outputs and the
3716 * values driven onto those pins!
3717 *
3718 * See also step 74 in the PRM ...
3719 */
3720 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3721 bgep->chipid.bge_mlcr_default);
3722 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3723
3724 /*
3725 * Step 20: clear the Ethernet MAC mode register
3726 */
3727 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3728
3729 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3730 MHCR_CHIP_ASIC_REV_5720) {
3731 uint32_t regval = bge_reg_get32(bgep, CPMU_CLCK_ORIDE_REG);
3732 bge_reg_put32(bgep, CPMU_CLCK_ORIDE_REG,
3733 regval & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
3734 }
3735
3736 /*
3737 * Step 21: restore cache-line-size, latency timer, and
3738 * subsystem ID registers to their original values (not
3739 * those read into the local structure <chipid>, 'cos
3740 * that was after they were cleared by the RESET).
3741 *
3742 * Note: the Subsystem Vendor/Device ID registers are not
3743 * directly writable in config space, so we use the shadow
3744 * copy in "Page Zero" of register space to restore them
3745 * both in one go ...
3746 */
3747 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3748 bgep->chipid.clsize);
3749 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3750 bgep->chipid.latency);
3751 bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3752 (bgep->chipid.subdev << 16) | bgep->chipid.subven);
3753
3754 /*
3755 * The SEND INDEX registers should be reset to zero by the
3756 * global chip reset; if they're not, there'll be trouble
3757 * later on.
3758 */
3759 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3760 if (sx0 != 0) {
3761 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3762 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3763 retval = DDI_FAILURE;
3764 }
3765
3766 /* Enable MSI code */
3767 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3768 bge_reg_set32(bgep, MSI_MODE_REG,
3769 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3770
3771 /*
3772 * On the first time through, save the factory-set MAC address
3773 * (if any). If bge_poll_firmware() above didn't return one
3774 * (from a chip register) consider looking in the attached NV
3775 * memory device, if any. Once we have it, we save it in both
3776 * register-image (64-bit) and byte-array forms. All-zero and
3777 * all-one addresses are not valid, and we refuse to stash those.
3778 */
3779 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3780 if (mac == 0ULL)
3781 mac = bge_get_nvmac(bgep);
3782 if (mac != 0ULL && mac != ~0ULL) {
3783 bgep->chipid.hw_mac_addr = mac;
3784 for (i = ETHERADDRL; i-- != 0; ) {
3785 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3786 mac >>= 8;
3787 }
3788 bgep->chipid.vendor_addr.set = B_TRUE;
3789 }
3790 }
3791
3792 #ifdef BGE_IPMI_ASF
3793 if (bgep->asf_enabled && bgep->asf_newhandshake) {
3794 if (asf_mode != ASF_MODE_NONE) {
3795 if ((asf_mode == ASF_MODE_INIT) ||
3796 (asf_mode == ASF_MODE_POST_INIT)) {
3797
3798 bge_asf_post_reset_new_mode(bgep,
3799 BGE_INIT_RESET);
3800 } else {
3801 bge_asf_post_reset_new_mode(bgep,
3802 BGE_SHUTDOWN_RESET);
3803 }
3804 }
3805 }
3806 #endif
3807
3808 /*
3809 * Record the new state
3810 */
3811 bgep->chip_resets += 1;
3812 bgep->bge_chip_state = BGE_CHIP_RESET;
3813 return (retval);
3814 }
3815
3816 /*
3817 * bge_chip_start() -- start the chip transmitting and/or receiving,
3818 * including enabling interrupts
3819 */
3820 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3821 #pragma no_inline(bge_chip_start)
3822
3823 void
3824 bge_chip_coalesce_update(bge_t *bgep)
3825 {
3826 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3827 bgep->chipid.tx_count_norm);
3828 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3829 bgep->chipid.tx_ticks_norm);
3830 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3831 bgep->chipid.rx_count_norm);
3832 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3833 bgep->chipid.rx_ticks_norm);
3834 }
3835
3836 int
3837 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3838 {
3839 uint32_t coalmode;
3840 uint32_t ledctl;
3841 uint32_t mtu;
3842 uint32_t maxring;
3843 uint32_t stats_mask;
3844 uint32_t dma_wrprio;
3845 uint64_t ring;
3846 uint32_t regval;
3847 int retval = DDI_SUCCESS;
3848
3849 BGE_TRACE(("bge_chip_start($%p)",
3850 (void *)bgep));
3851
3852 ASSERT(mutex_owned(bgep->genlock));
3853 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3854
3855 /*
3856 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3857 * The document specifies 95 separate steps to fully
3858 * initialise the chip!!!!
3859 *
3860 * The reset code above has already got us as far as step
3861 * 21, so we continue with ...
3862 *
3863 * Step 22: clear the MAC statistics block
3864 * (0x0300-0x0aff in NIC-local memory)
3865 */
3866 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3867 bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3868 NIC_MEM_STATISTICS_SIZE);
3869
3870 /*
3871 * Step 23: clear the status block (in host memory)
3872 */
3873 DMA_ZERO(bgep->status_block);
3874
3875 /*
3876 * Step 24: set DMA read/write control register
3877 */
3878 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3879 bgep->chipid.bge_dma_rwctrl);
3880
3881 /*
3882 * Step 25: Configure DMA endianness -- already done (16/17)
3883 * Step 26: Configure Host-Based Send Rings
3884 * Step 27: Indicate Host Stack Up
3885 */
3886 bge_reg_set32(bgep, MODE_CONTROL_REG,
3887 MODE_HOST_SEND_BDS |
3888 MODE_HOST_STACK_UP);
3889
3890 /*
3891 * Step 28: Configure checksum options:
3892 * Solaris supports the hardware default checksum options.
3893 *
3894 * Workaround for Incorrect pseudo-header checksum calculation.
3895 */
3896 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3897 bge_reg_set32(bgep, MODE_CONTROL_REG,
3898 MODE_SEND_NO_PSEUDO_HDR_CSUM);
3899
3900 /*
3901 * Step 29: configure Timer Prescaler. The value is always the
3902 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3903 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit
3904 * for the whole chip!
3905 */
3906 regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
3907 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT;
3908 bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
3909
3910 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3911 drv_usecwait(40);
3912 /* put PHY into ready state */
3913 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
3914 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
3915 drv_usecwait(40);
3916 }
3917
3918 /*
3919 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3920 *
3921 * If the mbuf_length is specified as 0, we just leave these at
3922 * their hardware defaults, rather than explicitly setting them.
3923 * As the Broadcom HRM,driver better not change the parameters
3924 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3925 */
3926 if ((bgep->chipid.mbuf_length != 0) &&
3927 (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3928 bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3929 bgep->chipid.mbuf_base);
3930 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3931 bgep->chipid.mbuf_length);
3932 bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3933 DMAD_POOL_BASE_DEFAULT);
3934 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3935 DMAD_POOL_LENGTH_DEFAULT);
3936 }
3937
3938 /*
3939 * Step 32: configure MAC memory pool watermarks
3940 */
3941 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3942 bgep->chipid.mbuf_lo_water_rdma);
3943 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3944 bgep->chipid.mbuf_lo_water_rmac);
3945 bge_reg_put32(bgep, MBUF_HIWAT_REG,
3946 bgep->chipid.mbuf_hi_water);
3947
3948 /*
3949 * Step 33: configure DMA resource watermarks
3950 */
3951 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3952 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3953 bge_dmad_lo_water);
3954 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3955 bge_dmad_hi_water);
3956 }
3957 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3958
3959 /*
3960 * Steps 34-36: enable buffer manager & internal h/w queues
3961 */
3962
3963 regval = STATE_MACHINE_ATTN_ENABLE_BIT;
3964 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3965 MHCR_CHIP_ASIC_REV_5719)
3966 regval |= BUFF_MGR_NO_TX_UNDERRUN;
3967 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3968 MHCR_CHIP_ASIC_REV_5717 ||
3969 bgep->chipid.asic_rev == MHCR_CHIP_REV_5719_A0 ||
3970 bgep->chipid.asic_rev == MHCR_CHIP_REV_5720_A0)
3971 regval |= BUFF_MGR_MBUF_LOW_ATTN_ENABLE;
3972 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, regval))
3973 retval = DDI_FAILURE;
3974 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3975 retval = DDI_FAILURE;
3976
3977 /*
3978 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3979 */
3980 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
3981 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
3982 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
3983 brp->desc.cookie.dmac_laddress);
3984 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
3985 (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
3986 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
3987 NIC_MEM_SHADOW_BUFF_STD_5717);
3988 } else
3989 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3990 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3991
3992 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3993 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3994 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3995 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3996 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3997 }
3998
3999 /*
4000 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
4001 */
4002 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
4003 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4004 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
4005 bge_replenish_jumbo);
4006 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
4007 bge_replenish_mini);
4008 }
4009
4010 /*
4011 * Steps 41-43: clear Send Ring Producer Indices and initialise
4012 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
4013 */
4014 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4015 maxring = BGE_SEND_RINGS_MAX;
4016 else
4017 maxring = BGE_SEND_RINGS_MAX_5705;
4018 for (ring = 0; ring < maxring; ++ring) {
4019 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
4020 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
4021 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
4022 &bgep->send[ring].hw_rcb);
4023 }
4024
4025 /*
4026 * Steps 44-45: initialise Receive Return Rings
4027 * (0x0200-0x02ff in NIC-local memory)
4028 */
4029 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4030 maxring = BGE_RECV_RINGS_MAX;
4031 else
4032 maxring = BGE_RECV_RINGS_MAX_5705;
4033 for (ring = 0; ring < maxring; ++ring)
4034 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
4035 &bgep->recv[ring].hw_rcb);
4036
4037 /*
4038 * Step 46: initialise Receive Buffer (Producer) Ring indexes
4039 */
4040 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
4041 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4042 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
4043 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
4044 }
4045 /*
4046 * Step 47: configure the MAC unicast address
4047 * Step 48: configure the random backoff seed
4048 * Step 96: set up multicast filters
4049 */
4050 #ifdef BGE_IPMI_ASF
4051 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
4052 #else
4053 if (bge_chip_sync(bgep) == DDI_FAILURE)
4054 #endif
4055 retval = DDI_FAILURE;
4056
4057 /*
4058 * Step 49: configure the MTU
4059 */
4060 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
4061 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
4062
4063 /*
4064 * Step 50: configure the IPG et al
4065 */
4066 regval = MAC_TX_LENGTHS_DEFAULT;
4067 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)
4068 == MHCR_CHIP_ASIC_REV_5720)
4069 regval |= bge_reg_get32(bgep, MAC_TX_LENGTHS_REG) &
4070 (MAC_TX_LENGTHS_JMB_FRM_LEN_MSK |
4071 MAC_TX_LENGTHS_CNT_DWN_VAL_MSK);
4072 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, regval);
4073
4074 /*
4075 * Step 51: configure the default Rx Return Ring
4076 */
4077 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
4078
4079 /*
4080 * Steps 52-54: configure Receive List Placement,
4081 * and enable Receive List Placement Statistics
4082 */
4083 bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
4084 RCV_LP_CONFIG(bgep->chipid.rx_rings));
4085 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
4086 case MHCR_CHIP_ASIC_REV_5700:
4087 case MHCR_CHIP_ASIC_REV_5701:
4088 case MHCR_CHIP_ASIC_REV_5703:
4089 case MHCR_CHIP_ASIC_REV_5704:
4090 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
4091 break;
4092 case MHCR_CHIP_ASIC_REV_5705:
4093 break;
4094 default:
4095 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
4096 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
4097 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
4098 break;
4099 }
4100 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
4101
4102 if (bgep->chipid.rx_rings > 1)
4103 bge_init_recv_rule(bgep);
4104
4105 /*
4106 * Steps 55-56: enable Send Data Initiator Statistics
4107 */
4108 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
4109 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4110 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4111 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
4112 } else {
4113 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
4114 SEND_INIT_STATS_ENABLE);
4115 }
4116 /*
4117 * Steps 57-58: stop (?) the Host Coalescing Engine
4118 */
4119 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
4120 retval = DDI_FAILURE;
4121
4122 /*
4123 * Steps 59-62: initialise Host Coalescing parameters
4124 */
4125 bge_chip_coalesce_update(bgep);
4126 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4127 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
4128 bge_tx_count_intr);
4129 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
4130 bge_tx_ticks_intr);
4131 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
4132 bge_rx_count_intr);
4133 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
4134 bge_rx_ticks_intr);
4135 }
4136
4137 /*
4138 * Steps 63-64: initialise status block & statistics
4139 * host memory addresses
4140 * The statistic block does not exist in some chipsets
4141 * Step 65: initialise Statistics Coalescing Tick Counter
4142 */
4143 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
4144 bgep->status_block.cookie.dmac_laddress);
4145
4146 /*
4147 * Steps 66-67: initialise status block & statistics
4148 * NIC-local memory addresses
4149 */
4150 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4151 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
4152 bgep->statistics.cookie.dmac_laddress);
4153 bge_reg_put32(bgep, STATISTICS_TICKS_REG,
4154 STATISTICS_TICKS_DEFAULT);
4155 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
4156 NIC_MEM_STATUS_BLOCK);
4157 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4158 NIC_MEM_STATISTICS);
4159 }
4160
4161 /*
4162 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4163 * Completion Engine, the Receive List Placement Engine, and the
4164 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4165 * and BCM5715.
4166 */
4167 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4168 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4169 coalmode = COALESCE_64_BYTE_STATUS;
4170 else
4171 coalmode = 0;
4172 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
4173 coalmode = COALESCE_CLR_TICKS_RX;
4174 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4175 retval = DDI_FAILURE;
4176 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4177 STATE_MACHINE_ATTN_ENABLE_BIT))
4178 retval = DDI_FAILURE;
4179 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4180 retval = DDI_FAILURE;
4181
4182 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4183 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4184 STATE_MACHINE_ATTN_ENABLE_BIT))
4185 retval = DDI_FAILURE;
4186
4187 /*
4188 * Step 72: Enable MAC DMA engines
4189 * Step 73: Clear & enable MAC statistics
4190 */
4191 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4192 ETHERNET_MODE_ENABLE_FHDE |
4193 ETHERNET_MODE_ENABLE_RDE |
4194 ETHERNET_MODE_ENABLE_TDE);
4195 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4196 ETHERNET_MODE_ENABLE_TX_STATS |
4197 ETHERNET_MODE_ENABLE_RX_STATS |
4198 ETHERNET_MODE_CLEAR_TX_STATS |
4199 ETHERNET_MODE_CLEAR_RX_STATS);
4200
4201 /*
4202 * Step 74: configure the MLCR (Miscellaneous Local Control
4203 * Register); not required, as we set up the MLCR in step 10
4204 * (part of the reset code) above.
4205 *
4206 * Step 75: clear Interrupt Mailbox 0
4207 */
4208 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4209
4210 /*
4211 * Steps 76-87: Gentlemen, start your engines ...
4212 *
4213 * Enable the DMA Completion Engine, the Write DMA Engine,
4214 * the Read DMA Engine, Receive Data Completion Engine,
4215 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4216 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4217 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4218 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4219 *
4220 * Beware exhaust fumes?
4221 */
4222 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4223 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4224 retval = DDI_FAILURE;
4225 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4226 ALL_DMA_ATTN_BITS;
4227 if (DEVICE_IS_5755_PLUS(bgep))
4228 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4229 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4230 dma_wrprio))
4231 retval = DDI_FAILURE;
4232 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4233 MHCR_CHIP_ASIC_REV_5761 ||
4234 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4235 MHCR_CHIP_ASIC_REV_5784 ||
4236 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4237 MHCR_CHIP_ASIC_REV_5785 ||
4238 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4239 MHCR_CHIP_ASIC_REV_57780 ||
4240 DEVICE_IS_57765_PLUS(bgep)) {
4241 regval = bge_reg_get32(bgep, READ_DMA_RESERVED_CONTROL_REG);
4242 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4243 MHCR_CHIP_ASIC_REV_5719 ||
4244 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4245 MHCR_CHIP_ASIC_REV_5720) {
4246 regval &= ~(RDMA_RSRVCTRL_TXMRGN_MASK |
4247 RDMA_RSRVCTRL_FIFO_LWM_MASK |
4248 RDMA_RSRVCTRL_FIFO_HWM_MASK);
4249 regval |= RDMA_RSRVCTRL_TXMRGN_320B |
4250 RDMA_RSRVCTRL_FIFO_LWM_1_5K |
4251 RDMA_RSRVCTRL_FIFO_HWM_1_5K;
4252 }
4253 bge_reg_put32(bgep, READ_DMA_RESERVED_CONTROL_REG,
4254 regval | RDMA_RSRVCTRL_FIFO_OFLW_FIX);
4255 }
4256 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4257 DEVICE_5717_SERIES_CHIPSETS(bgep))
4258 bge_dma_rdprio = 0;
4259 regval = bge_dma_rdprio << DMA_PRIORITY_SHIFT;
4260 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4261 MHCR_CHIP_ASIC_REV_5720)
4262 regval |= bge_reg_get32(bgep, READ_DMA_MODE_REG) &
4263 DMA_H2BNC_VLAN_DET;
4264 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4265 regval | ALL_DMA_ATTN_BITS))
4266 retval = DDI_FAILURE;
4267 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4268 STATE_MACHINE_ATTN_ENABLE_BIT))
4269 retval = DDI_FAILURE;
4270 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4271 if (!bge_chip_enable_engine(bgep,
4272 MBUF_CLUSTER_FREE_MODE_REG, 0))
4273 retval = DDI_FAILURE;
4274 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4275 retval = DDI_FAILURE;
4276 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4277 STATE_MACHINE_ATTN_ENABLE_BIT))
4278 retval = DDI_FAILURE;
4279 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4280 RCV_BD_DISABLED_RING_ATTN))
4281 retval = DDI_FAILURE;
4282 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4283 RCV_DATA_BD_ILL_RING_ATTN))
4284 retval = DDI_FAILURE;
4285 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4286 retval = DDI_FAILURE;
4287 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4288 STATE_MACHINE_ATTN_ENABLE_BIT))
4289 retval = DDI_FAILURE;
4290 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4291 STATE_MACHINE_ATTN_ENABLE_BIT))
4292 retval = DDI_FAILURE;
4293
4294 /*
4295 * Step 88: download firmware -- doesn't apply
4296 * Steps 89-90: enable Transmit & Receive MAC Engines
4297 */
4298 if (DEVICE_IS_5755_PLUS(bgep) ||
4299 MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4300 MHCR_CHIP_ASIC_REV_5906) {
4301 regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
4302 regval |= TRANSMIT_MODE_MBUF_LOCKUP_FIX;
4303 } else {
4304 regval = 0;
4305 }
4306 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4307 MHCR_CHIP_ASIC_REV_5720) {
4308 regval &= ~(TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
4309 TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
4310 regval |= bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG) &
4311 (TRANSMIT_MODE_HTX2B_JMB_FRM_LEN |
4312 TRANSMIT_MODE_HTX2B_CNT_DN_MODE);
4313 }
4314 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, regval))
4315 retval = DDI_FAILURE;
4316 #ifdef BGE_IPMI_ASF
4317 if (!bgep->asf_enabled) {
4318 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4319 RECEIVE_MODE_KEEP_VLAN_TAG))
4320 retval = DDI_FAILURE;
4321 } else {
4322 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4323 retval = DDI_FAILURE;
4324 }
4325 #else
4326 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4327 RECEIVE_MODE_KEEP_VLAN_TAG))
4328 retval = DDI_FAILURE;
4329 #endif
4330
4331 /*
4332 * Step 91: disable auto-polling of PHY status
4333 */
4334 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4335
4336 /*
4337 * Step 92: configure D0 power state (not required)
4338 * Step 93: initialise LED control register ()
4339 */
4340 ledctl = LED_CONTROL_DEFAULT;
4341 switch (bgep->chipid.device) {
4342 case DEVICE_ID_5700:
4343 case DEVICE_ID_5700x:
4344 case DEVICE_ID_5701:
4345 /*
4346 * Switch to 5700 (MAC) mode on these older chips
4347 */
4348 ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4349 ledctl |= LED_CONTROL_LED_MODE_5700;
4350 break;
4351
4352 default:
4353 break;
4354 }
4355 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4356
4357 /*
4358 * Step 94: activate link
4359 */
4360 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4361
4362 /*
4363 * Step 95: set up physical layer (PHY/SerDes)
4364 * restart autoneg (if required)
4365 */
4366 if (reset_phys)
4367 if (bge_phys_update(bgep) == DDI_FAILURE)
4368 retval = DDI_FAILURE;
4369
4370 /*
4371 * Extra step (DSG): hand over all the Receive Buffers to the chip
4372 */
4373 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4374 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4375 bgep->buff[ring].rf_next);
4376
4377 /*
4378 * MSI bits:The least significant MSI 16-bit word.
4379 * ISR will be triggered different.
4380 */
4381 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4382 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4383
4384 /*
4385 * Extra step (DSG): select which interrupts are enabled
4386 *
4387 * Program the Ethernet MAC engine to signal attention on
4388 * Link Change events, then enable interrupts on MAC, DMA,
4389 * and FLOW attention signals.
4390 */
4391 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4392 ETHERNET_EVENT_LINK_INT |
4393 ETHERNET_STATUS_PCS_ERROR_INT);
4394 #ifdef BGE_IPMI_ASF
4395 if (bgep->asf_enabled) {
4396 bge_reg_set32(bgep, MODE_CONTROL_REG,
4397 MODE_INT_ON_FLOW_ATTN |
4398 MODE_INT_ON_DMA_ATTN |
4399 MODE_HOST_STACK_UP|
4400 MODE_INT_ON_MAC_ATTN);
4401 } else {
4402 #endif
4403 bge_reg_set32(bgep, MODE_CONTROL_REG,
4404 MODE_INT_ON_FLOW_ATTN |
4405 MODE_INT_ON_DMA_ATTN |
4406 MODE_INT_ON_MAC_ATTN);
4407 #ifdef BGE_IPMI_ASF
4408 }
4409 #endif
4410
4411 /*
4412 * Step 97: enable PCI interrupts!!!
4413 */
4414 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4415 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4416 bgep->chipid.mask_pci_int);
4417 /*
4418 * All done!
4419 */
4420 bgep->bge_chip_state = BGE_CHIP_RUNNING;
4421 return (retval);
4422 }
4423
4424
4425 /*
4426 * ========== Hardware interrupt handler ==========
4427 */
4428
4429 #undef BGE_DBG
4430 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */
4431
4432 /*
4433 * Sync the status block, then atomically clear the specified bits in
4434 * the <flags-and-tag> field of the status block.
4435 * the <flags> word of the status block, returning the value of the
4436 * <tag> and the <flags> before the bits were cleared.
4437 */
4438 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4439 #pragma inline(bge_status_sync)
4440
4441 static int
4442 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4443 {
4444 bge_status_t *bsp;
4445 int retval;
4446
4447 BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4448 (void *)bgep, bits));
4449
4450 ASSERT(bgep->bge_guard == BGE_GUARD);
4451
4452 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4453 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4454 if (retval != DDI_FM_OK)
4455 return (retval);
4456
4457 bsp = DMA_VPTR(bgep->status_block);
4458 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4459
4460 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4461 (void *)bgep, bits, *flags));
4462
4463 return (retval);
4464 }
4465
4466 void bge_wake_factotum(bge_t *bgep);
4467 #pragma inline(bge_wake_factotum)
4468
4469 void
4470 bge_wake_factotum(bge_t *bgep)
4471 {
4472 mutex_enter(bgep->softintrlock);
4473 if (bgep->factotum_flag == 0) {
4474 bgep->factotum_flag = 1;
4475 ddi_trigger_softintr(bgep->factotum_id);
4476 }
4477 mutex_exit(bgep->softintrlock);
4478 }
4479
4480 /*
4481 * bge_intr() -- handle chip interrupts
4482 */
4483 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
4484 #pragma no_inline(bge_intr)
4485
4486 uint_t
4487 bge_intr(caddr_t arg1, caddr_t arg2)
4488 {
4489 bge_t *bgep = (void *)arg1; /* private device info */
4490 bge_status_t *bsp;
4491 uint64_t flags;
4492 uint32_t regval;
4493 uint_t result;
4494 int retval, loop_cnt = 0;
4495
4496 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
4497
4498 /*
4499 * GLD v2 checks that s/w setup is complete before passing
4500 * interrupts to this routine, thus eliminating the old
4501 * (and well-known) race condition around ddi_add_intr()
4502 */
4503 ASSERT(bgep->progress & PROGRESS_HWINT);
4504
4505 result = DDI_INTR_UNCLAIMED;
4506 mutex_enter(bgep->genlock);
4507
4508 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4509 /*
4510 * Check whether chip's says it's asserting #INTA;
4511 * if not, don't process or claim the interrupt.
4512 *
4513 * Note that the PCI signal is active low, so the
4514 * bit is *zero* when the interrupt is asserted.
4515 */
4516 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
4517 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) &&
4518 (regval & MLCR_INTA_STATE)) {
4519 if (bge_check_acc_handle(bgep, bgep->io_handle)
4520 != DDI_FM_OK)
4521 goto chip_stop;
4522 mutex_exit(bgep->genlock);
4523 return (result);
4524 }
4525
4526 /*
4527 * Block further PCI interrupts ...
4528 */
4529 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4530 bgep->chipid.mask_pci_int);
4531
4532 } else {
4533 /*
4534 * Check MSI status
4535 */
4536 regval = bge_reg_get32(bgep, MSI_STATUS_REG);
4537 if (regval & MSI_ERROR_ATTENTION) {
4538 BGE_REPORT((bgep, "msi error attention,"
4539 " status=0x%x", regval));
4540 bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4541 }
4542 }
4543
4544 result = DDI_INTR_CLAIMED;
4545
4546 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
4547
4548 /*
4549 * Sync the status block and grab the flags-n-tag from it.
4550 * We count the number of interrupts where there doesn't
4551 * seem to have been a DMA update of the status block; if
4552 * it *has* been updated, the counter will be cleared in
4553 * the while() loop below ...
4554 */
4555 bgep->missed_dmas += 1;
4556 bsp = DMA_VPTR(bgep->status_block);
4557 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
4558 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
4559 /*
4560 * bge_chip_stop() may have freed dma area etc
4561 * while we were in this interrupt handler -
4562 * better not call bge_status_sync()
4563 */
4564 (void) bge_check_acc_handle(bgep,
4565 bgep->io_handle);
4566 mutex_exit(bgep->genlock);
4567 return (DDI_INTR_CLAIMED);
4568 }
4569 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4570 &flags);
4571 if (retval != DDI_FM_OK) {
4572 bgep->bge_dma_error = B_TRUE;
4573 goto chip_stop;
4574 }
4575
4576 if (!(flags & STATUS_FLAG_UPDATED))
4577 break;
4578
4579 /*
4580 * Tell the chip that we're processing the interrupt
4581 */
4582 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4583 INTERRUPT_MBOX_DISABLE(flags));
4584 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4585 DDI_FM_OK)
4586 goto chip_stop;
4587
4588 /*
4589 * Drop the mutex while we:
4590 * Receive any newly-arrived packets
4591 * Recycle any newly-finished send buffers
4592 */
4593 bgep->bge_intr_running = B_TRUE;
4594 mutex_exit(bgep->genlock);
4595 bge_receive(bgep, bsp);
4596 (void) bge_recycle(bgep, bsp);
4597 mutex_enter(bgep->genlock);
4598 bgep->bge_intr_running = B_FALSE;
4599
4600 /*
4601 * Tell the chip we've finished processing, and
4602 * give it the tag that we got from the status
4603 * block earlier, so that it knows just how far
4604 * we've gone. If it's got more for us to do,
4605 * it will now update the status block and try
4606 * to assert an interrupt (but we've got the
4607 * #INTA blocked at present). If we see the
4608 * update, we'll loop around to do some more.
4609 * Eventually we'll get out of here ...
4610 */
4611 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4612 INTERRUPT_MBOX_ENABLE(flags));
4613 if (bgep->chipid.pci_type == BGE_PCI_E)
4614 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4615 bgep->missed_dmas = 0;
4616 }
4617
4618 /*
4619 * Check for exceptional conditions that we need to handle
4620 *
4621 * Link status changed
4622 * Status block not updated
4623 */
4624 if (flags & STATUS_FLAG_LINK_CHANGED)
4625 bge_wake_factotum(bgep);
4626
4627 if (bgep->missed_dmas) {
4628 /*
4629 * Probably due to the internal status tag not
4630 * being reset. Force a status block update now;
4631 * this should ensure that we get an update and
4632 * a new interrupt. After that, we should be in
4633 * sync again ...
4634 */
4635 BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4636 "not updated?", flags));
4637 bgep->missed_updates++;
4638 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4639 COALESCE_NOW);
4640
4641 if (bgep->missed_dmas >= bge_dma_miss_limit) {
4642 /*
4643 * If this happens multiple times in a row,
4644 * it means DMA is just not working. Maybe
4645 * the chip's failed, or maybe there's a
4646 * problem on the PCI bus or in the host-PCI
4647 * bridge (Tomatillo).
4648 *
4649 * At all events, we want to stop further
4650 * interrupts and let the recovery code take
4651 * over to see whether anything can be done
4652 * about it ...
4653 */
4654 bge_fm_ereport(bgep,
4655 DDI_FM_DEVICE_BADINT_LIMIT);
4656 goto chip_stop;
4657 }
4658 }
4659
4660 /*
4661 * Reenable assertion of #INTA, unless there's a DMA fault
4662 */
4663 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4664 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4665 bgep->chipid.mask_pci_int);
4666 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4667 DDI_FM_OK)
4668 goto chip_stop;
4669 }
4670
4671 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4672 goto chip_stop;
4673
4674 mutex_exit(bgep->genlock);
4675 return (result);
4676
4677 chip_stop:
4678 #ifdef BGE_IPMI_ASF
4679 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4680 /*
4681 * We must stop ASF heart beat before
4682 * bge_chip_stop(), otherwise some
4683 * computers (ex. IBM HS20 blade
4684 * server) may crash.
4685 */
4686 bge_asf_update_status(bgep);
4687 bge_asf_stop_timer(bgep);
4688 bgep->asf_status = ASF_STAT_STOP;
4689
4690 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4691 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4692 }
4693 #endif
4694 bge_chip_stop(bgep, B_TRUE);
4695 (void) bge_check_acc_handle(bgep, bgep->io_handle);
4696 mutex_exit(bgep->genlock);
4697 return (result);
4698 }
4699
4700 /*
4701 * ========== Factotum, implemented as a softint handler ==========
4702 */
4703
4704 #undef BGE_DBG
4705 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */
4706
4707 static void bge_factotum_error_handler(bge_t *bgep);
4708 #pragma no_inline(bge_factotum_error_handler)
4709
4710 static void
4711 bge_factotum_error_handler(bge_t *bgep)
4712 {
4713 uint32_t flow;
4714 uint32_t rdma;
4715 uint32_t wdma;
4716 uint32_t tmac;
4717 uint32_t rmac;
4718 uint32_t rxrs;
4719 uint32_t txrs = 0;
4720
4721 ASSERT(mutex_owned(bgep->genlock));
4722
4723 /*
4724 * Read all the registers that show the possible
4725 * reasons for the ERROR bit to be asserted
4726 */
4727 flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4728 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4729 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4730 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4731 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4732 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4733 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4734 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4735
4736 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4737 (void *)bgep, flow, rdma, wdma));
4738 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4739 (void *)bgep, tmac, rmac, rxrs, txrs));
4740
4741 /*
4742 * For now, just clear all the errors ...
4743 */
4744 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4745 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4746 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4747 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4748 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4749 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4750 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4751 }
4752
4753 /*
4754 * Handler for hardware link state change.
4755 *
4756 * When this routine is called, the hardware link state has changed
4757 * and the new state is reflected in the param_* variables. Here
4758 * we must update the softstate and reprogram the MAC to match.
4759 */
4760 static void bge_factotum_link_handler(bge_t *bgep);
4761 #pragma no_inline(bge_factotum_link_handler)
4762
4763 static void
4764 bge_factotum_link_handler(bge_t *bgep)
4765 {
4766 ASSERT(mutex_owned(bgep->genlock));
4767
4768 /*
4769 * Update the s/w link_state
4770 */
4771 if (bgep->param_link_up)
4772 bgep->link_state = LINK_STATE_UP;
4773 else
4774 bgep->link_state = LINK_STATE_DOWN;
4775
4776 /*
4777 * Reprogram the MAC modes to match
4778 */
4779 bge_sync_mac_modes(bgep);
4780 }
4781
4782 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4783 #pragma no_inline(bge_factotum_link_check)
4784
4785 static boolean_t
4786 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4787 {
4788 boolean_t check;
4789 uint64_t flags;
4790 uint32_t tmac_status;
4791
4792 ASSERT(mutex_owned(bgep->genlock));
4793
4794 /*
4795 * Get & clear the writable status bits in the Tx status register
4796 * (some bits are write-1-to-clear, others are just readonly).
4797 */
4798 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4799 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4800
4801 /*
4802 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4803 */
4804 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4805 STATUS_FLAG_LINK_CHANGED, &flags);
4806 if (*dma_state != DDI_FM_OK)
4807 return (B_FALSE);
4808
4809 /*
4810 * Clear any errors flagged in the status block ...
4811 */
4812 if (flags & STATUS_FLAG_ERROR)
4813 bge_factotum_error_handler(bgep);
4814
4815 /*
4816 * We need to check the link status if:
4817 * the status block says there's been a link change
4818 * or there's any discrepancy between the various
4819 * flags indicating the link state (link_state,
4820 * param_link_up, and the LINK STATE bit in the
4821 * Transmit MAC status register).
4822 */
4823 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4824 switch (bgep->link_state) {
4825 case LINK_STATE_UP:
4826 check |= (bgep->param_link_up == B_FALSE);
4827 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4828 break;
4829
4830 case LINK_STATE_DOWN:
4831 check |= (bgep->param_link_up != B_FALSE);
4832 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4833 break;
4834
4835 default:
4836 check = B_TRUE;
4837 break;
4838 }
4839
4840 /*
4841 * If <check> is false, we're sure the link hasn't changed.
4842 * If true, however, it's not yet definitive; we have to call
4843 * bge_phys_check() to determine whether the link has settled
4844 * into a new state yet ... and if it has, then call the link
4845 * state change handler.But when the chip is 5700 in Dell 6650
4846 * ,even if check is false, the link may have changed.So we
4847 * have to call bge_phys_check() to determine the link state.
4848 */
4849 if (check || bgep->chipid.device == DEVICE_ID_5700) {
4850 check = bge_phys_check(bgep);
4851 if (check)
4852 bge_factotum_link_handler(bgep);
4853 }
4854
4855 return (check);
4856 }
4857
4858 /*
4859 * Factotum routine to check for Tx stall, using the 'watchdog' counter
4860 */
4861 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4862 #pragma no_inline(bge_factotum_stall_check)
4863
4864 static boolean_t
4865 bge_factotum_stall_check(bge_t *bgep)
4866 {
4867 uint32_t dogval;
4868 bge_status_t *bsp;
4869 uint64_t now = gethrtime();
4870
4871 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
4872 return (B_FALSE);
4873
4874 bgep->timestamp = now;
4875
4876 ASSERT(mutex_owned(bgep->genlock));
4877
4878 /*
4879 * Specific check for Tx stall ...
4880 *
4881 * The 'watchdog' counter is incremented whenever a packet
4882 * is queued, reset to 1 when some (but not all) buffers
4883 * are reclaimed, reset to 0 (disabled) when all buffers
4884 * are reclaimed, and shifted left here. If it exceeds the
4885 * threshold value, the chip is assumed to have stalled and
4886 * is put into the ERROR state. The factotum will then reset
4887 * it on the next pass.
4888 *
4889 * All of which should ensure that we don't get into a state
4890 * where packets are left pending indefinitely!
4891 */
4892 dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4893 bsp = DMA_VPTR(bgep->status_block);
4894 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
4895 return (B_FALSE);
4896
4897 #if !defined(BGE_NETCONSOLE)
4898 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4899 #endif
4900 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4901 return (B_TRUE);
4902 }
4903
4904 /*
4905 * The factotum is woken up when there's something to do that we'd rather
4906 * not do from inside a hardware interrupt handler or high-level cyclic.
4907 * Its two main tasks are:
4908 * reset & restart the chip after an error
4909 * check the link status whenever necessary
4910 */
4911 uint_t bge_chip_factotum(caddr_t arg);
4912 #pragma no_inline(bge_chip_factotum)
4913
4914 uint_t
4915 bge_chip_factotum(caddr_t arg)
4916 {
4917 bge_t *bgep;
4918 uint_t result;
4919 boolean_t error;
4920 boolean_t linkchg;
4921 int dma_state;
4922
4923 bgep = (void *)arg;
4924
4925 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4926
4927 mutex_enter(bgep->softintrlock);
4928 if (bgep->factotum_flag == 0) {
4929 mutex_exit(bgep->softintrlock);
4930 return (DDI_INTR_UNCLAIMED);
4931 }
4932 bgep->factotum_flag = 0;
4933 mutex_exit(bgep->softintrlock);
4934
4935 result = DDI_INTR_CLAIMED;
4936 error = B_FALSE;
4937 linkchg = B_FALSE;
4938
4939 mutex_enter(bgep->genlock);
4940 switch (bgep->bge_chip_state) {
4941 default:
4942 break;
4943
4944 case BGE_CHIP_RUNNING:
4945 linkchg = bge_factotum_link_check(bgep, &dma_state);
4946 error = bge_factotum_stall_check(bgep);
4947 if (dma_state != DDI_FM_OK) {
4948 bgep->bge_dma_error = B_TRUE;
4949 error = B_TRUE;
4950 }
4951 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4952 error = B_TRUE;
4953 if (error)
4954 bgep->bge_chip_state = BGE_CHIP_ERROR;
4955 break;
4956
4957 case BGE_CHIP_ERROR:
4958 error = B_TRUE;
4959 break;
4960
4961 case BGE_CHIP_FAULT:
4962 /*
4963 * Fault detected, time to reset ...
4964 */
4965 if (bge_autorecover) {
4966 if (!(bgep->progress & PROGRESS_BUFS)) {
4967 /*
4968 * if we can't allocate the ring buffers,
4969 * try later
4970 */
4971 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4972 mutex_exit(bgep->genlock);
4973 return (result);
4974 }
4975 bgep->progress |= PROGRESS_BUFS;
4976 }
4977 if (!(bgep->progress & PROGRESS_INTR)) {
4978 bge_init_rings(bgep);
4979 bge_intr_enable(bgep);
4980 bgep->progress |= PROGRESS_INTR;
4981 }
4982 if (!(bgep->progress & PROGRESS_KSTATS)) {
4983 bge_init_kstats(bgep,
4984 ddi_get_instance(bgep->devinfo));
4985 bgep->progress |= PROGRESS_KSTATS;
4986 }
4987
4988 BGE_REPORT((bgep, "automatic recovery activated"));
4989
4990 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4991 bgep->bge_chip_state = BGE_CHIP_ERROR;
4992 error = B_TRUE;
4993 }
4994 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4995 DDI_FM_OK) {
4996 bgep->bge_chip_state = BGE_CHIP_ERROR;
4997 error = B_TRUE;
4998 }
4999 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
5000 DDI_FM_OK) {
5001 bgep->bge_chip_state = BGE_CHIP_ERROR;
5002 error = B_TRUE;
5003 }
5004 if (error == B_FALSE) {
5005 #ifdef BGE_IPMI_ASF
5006 if (bgep->asf_enabled &&
5007 bgep->asf_status != ASF_STAT_RUN) {
5008 bgep->asf_timeout_id = timeout(
5009 bge_asf_heartbeat, (void *)bgep,
5010 drv_usectohz(
5011 BGE_ASF_HEARTBEAT_INTERVAL));
5012 bgep->asf_status = ASF_STAT_RUN;
5013 }
5014 #endif
5015 if (!bgep->manual_reset) {
5016 ddi_fm_service_impact(bgep->devinfo,
5017 DDI_SERVICE_RESTORED);
5018 }
5019 }
5020 }
5021 break;
5022 }
5023
5024
5025 /*
5026 * If an error is detected, stop the chip now, marking it as
5027 * faulty, so that it will be reset next time through ...
5028 *
5029 * Note that if intr_running is set, then bge_intr() has dropped
5030 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
5031 * this point so have to wait until the next time the factotum runs.
5032 */
5033 if (error && !bgep->bge_intr_running) {
5034 #ifdef BGE_IPMI_ASF
5035 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
5036 /*
5037 * We must stop ASF heart beat before bge_chip_stop(),
5038 * otherwise some computers (ex. IBM HS20 blade server)
5039 * may crash.
5040 */
5041 bge_asf_update_status(bgep);
5042 bge_asf_stop_timer(bgep);
5043 bgep->asf_status = ASF_STAT_STOP;
5044
5045 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
5046 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
5047 }
5048 #endif
5049 bge_chip_stop(bgep, B_TRUE);
5050 (void) bge_check_acc_handle(bgep, bgep->io_handle);
5051 }
5052 mutex_exit(bgep->genlock);
5053
5054 /*
5055 * If the link state changed, tell the world about it.
5056 * Note: can't do this while still holding the mutex.
5057 */
5058 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
5059 bgep->link_state != LINK_STATE_UNKNOWN)
5060 linkchg = B_TRUE;
5061 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
5062 bgep->link_state == LINK_STATE_DOWN)
5063 linkchg = B_FALSE;
5064
5065 if (linkchg) {
5066 mac_link_update(bgep->mh, bgep->link_state);
5067 bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
5068 }
5069 if (bgep->manual_reset) {
5070 bgep->manual_reset = B_FALSE;
5071 }
5072
5073 return (result);
5074 }
5075
5076 /*
5077 * High-level cyclic handler
5078 *
5079 * This routine schedules a (low-level) softint callback to the
5080 * factotum, and prods the chip to update the status block (which
5081 * will cause a hardware interrupt when complete).
5082 */
5083 void bge_chip_cyclic(void *arg);
5084 #pragma no_inline(bge_chip_cyclic)
5085
5086 void
5087 bge_chip_cyclic(void *arg)
5088 {
5089 bge_t *bgep;
5090
5091 bgep = arg;
5092
5093 switch (bgep->bge_chip_state) {
5094 default:
5095 return;
5096
5097 case BGE_CHIP_RUNNING:
5098 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
5099 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5100 ddi_fm_service_impact(bgep->devinfo,
5101 DDI_SERVICE_UNAFFECTED);
5102
5103 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
5104 bgep->link_update_timer++;
5105
5106 break;
5107
5108 case BGE_CHIP_FAULT:
5109 case BGE_CHIP_ERROR:
5110 break;
5111 }
5112
5113 bge_wake_factotum(bgep);
5114 }
5115
5116
5117 /*
5118 * ========== Ioctl subfunctions ==========
5119 */
5120
5121 #undef BGE_DBG
5122 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */
5123
5124 #if BGE_DEBUGGING || BGE_DO_PPIO
5125
5126 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5127 #pragma no_inline(bge_chip_peek_cfg)
5128
5129 static void
5130 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5131 {
5132 uint64_t regval;
5133 uint64_t regno;
5134
5135 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
5136 (void *)bgep, (void *)ppd));
5137
5138 regno = ppd->pp_acc_offset;
5139
5140 switch (ppd->pp_acc_size) {
5141 case 1:
5142 regval = pci_config_get8(bgep->cfg_handle, regno);
5143 break;
5144
5145 case 2:
5146 regval = pci_config_get16(bgep->cfg_handle, regno);
5147 break;
5148
5149 case 4:
5150 regval = pci_config_get32(bgep->cfg_handle, regno);
5151 break;
5152
5153 case 8:
5154 regval = pci_config_get64(bgep->cfg_handle, regno);
5155 break;
5156 }
5157
5158 ppd->pp_acc_data = regval;
5159 }
5160
5161 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
5162 #pragma no_inline(bge_chip_poke_cfg)
5163
5164 static void
5165 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
5166 {
5167 uint64_t regval;
5168 uint64_t regno;
5169
5170 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
5171 (void *)bgep, (void *)ppd));
5172
5173 regno = ppd->pp_acc_offset;
5174 regval = ppd->pp_acc_data;
5175
5176 switch (ppd->pp_acc_size) {
5177 case 1:
5178 pci_config_put8(bgep->cfg_handle, regno, regval);
5179 break;
5180
5181 case 2:
5182 pci_config_put16(bgep->cfg_handle, regno, regval);
5183 break;
5184
5185 case 4:
5186 pci_config_put32(bgep->cfg_handle, regno, regval);
5187 break;
5188
5189 case 8:
5190 pci_config_put64(bgep->cfg_handle, regno, regval);
5191 break;
5192 }
5193 }
5194
5195 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5196 #pragma no_inline(bge_chip_peek_reg)
5197
5198 static void
5199 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5200 {
5201 uint64_t regval;
5202 void *regaddr;
5203
5204 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5205 (void *)bgep, (void *)ppd));
5206
5207 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5208
5209 switch (ppd->pp_acc_size) {
5210 case 1:
5211 regval = ddi_get8(bgep->io_handle, regaddr);
5212 break;
5213
5214 case 2:
5215 regval = ddi_get16(bgep->io_handle, regaddr);
5216 break;
5217
5218 case 4:
5219 regval = ddi_get32(bgep->io_handle, regaddr);
5220 break;
5221
5222 case 8:
5223 regval = ddi_get64(bgep->io_handle, regaddr);
5224 break;
5225 }
5226
5227 ppd->pp_acc_data = regval;
5228 }
5229
5230 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5231 #pragma no_inline(bge_chip_peek_reg)
5232
5233 static void
5234 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5235 {
5236 uint64_t regval;
5237 void *regaddr;
5238
5239 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5240 (void *)bgep, (void *)ppd));
5241
5242 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5243 regval = ppd->pp_acc_data;
5244
5245 switch (ppd->pp_acc_size) {
5246 case 1:
5247 ddi_put8(bgep->io_handle, regaddr, regval);
5248 break;
5249
5250 case 2:
5251 ddi_put16(bgep->io_handle, regaddr, regval);
5252 break;
5253
5254 case 4:
5255 ddi_put32(bgep->io_handle, regaddr, regval);
5256 break;
5257
5258 case 8:
5259 ddi_put64(bgep->io_handle, regaddr, regval);
5260 break;
5261 }
5262 BGE_PCICHK(bgep);
5263 }
5264
5265 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5266 #pragma no_inline(bge_chip_peek_nic)
5267
5268 static void
5269 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5270 {
5271 uint64_t regoff;
5272 uint64_t regval;
5273 void *regaddr;
5274
5275 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5276 (void *)bgep, (void *)ppd));
5277
5278 regoff = ppd->pp_acc_offset;
5279 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5280 regoff &= MWBAR_GRANULE_MASK;
5281 regoff += NIC_MEM_WINDOW_OFFSET;
5282 regaddr = PIO_ADDR(bgep, regoff);
5283
5284 switch (ppd->pp_acc_size) {
5285 case 1:
5286 regval = ddi_get8(bgep->io_handle, regaddr);
5287 break;
5288
5289 case 2:
5290 regval = ddi_get16(bgep->io_handle, regaddr);
5291 break;
5292
5293 case 4:
5294 regval = ddi_get32(bgep->io_handle, regaddr);
5295 break;
5296
5297 case 8:
5298 regval = ddi_get64(bgep->io_handle, regaddr);
5299 break;
5300 }
5301
5302 ppd->pp_acc_data = regval;
5303 }
5304
5305 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5306 #pragma no_inline(bge_chip_poke_nic)
5307
5308 static void
5309 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5310 {
5311 uint64_t regoff;
5312 uint64_t regval;
5313 void *regaddr;
5314
5315 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5316 (void *)bgep, (void *)ppd));
5317
5318 regoff = ppd->pp_acc_offset;
5319 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5320 regoff &= MWBAR_GRANULE_MASK;
5321 regoff += NIC_MEM_WINDOW_OFFSET;
5322 regaddr = PIO_ADDR(bgep, regoff);
5323 regval = ppd->pp_acc_data;
5324
5325 switch (ppd->pp_acc_size) {
5326 case 1:
5327 ddi_put8(bgep->io_handle, regaddr, regval);
5328 break;
5329
5330 case 2:
5331 ddi_put16(bgep->io_handle, regaddr, regval);
5332 break;
5333
5334 case 4:
5335 ddi_put32(bgep->io_handle, regaddr, regval);
5336 break;
5337
5338 case 8:
5339 ddi_put64(bgep->io_handle, regaddr, regval);
5340 break;
5341 }
5342 BGE_PCICHK(bgep);
5343 }
5344
5345 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5346 #pragma no_inline(bge_chip_peek_mii)
5347
5348 static void
5349 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5350 {
5351 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5352 (void *)bgep, (void *)ppd));
5353
5354 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5355 }
5356
5357 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5358 #pragma no_inline(bge_chip_poke_mii)
5359
5360 static void
5361 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5362 {
5363 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5364 (void *)bgep, (void *)ppd));
5365
5366 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5367 }
5368
5369 #if BGE_SEE_IO32
5370
5371 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5372 #pragma no_inline(bge_chip_peek_seeprom)
5373
5374 static void
5375 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5376 {
5377 uint32_t data;
5378 int err;
5379
5380 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5381 (void *)bgep, (void *)ppd));
5382
5383 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5384 ppd->pp_acc_data = err ? ~0ull : data;
5385 }
5386
5387 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5388 #pragma no_inline(bge_chip_poke_seeprom)
5389
5390 static void
5391 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5392 {
5393 uint32_t data;
5394
5395 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5396 (void *)bgep, (void *)ppd));
5397
5398 data = ppd->pp_acc_data;
5399 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5400 }
5401 #endif /* BGE_SEE_IO32 */
5402
5403 #if BGE_FLASH_IO32
5404
5405 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5406 #pragma no_inline(bge_chip_peek_flash)
5407
5408 static void
5409 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5410 {
5411 uint32_t data;
5412 int err;
5413
5414 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5415 (void *)bgep, (void *)ppd));
5416
5417 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5418 ppd->pp_acc_data = err ? ~0ull : data;
5419 }
5420
5421 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5422 #pragma no_inline(bge_chip_poke_flash)
5423
5424 static void
5425 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5426 {
5427 uint32_t data;
5428
5429 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5430 (void *)bgep, (void *)ppd));
5431
5432 data = ppd->pp_acc_data;
5433 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5434 ppd->pp_acc_offset, &data);
5435 }
5436 #endif /* BGE_FLASH_IO32 */
5437
5438 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5439 #pragma no_inline(bge_chip_peek_mem)
5440
5441 static void
5442 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5443 {
5444 uint64_t regval;
5445 void *vaddr;
5446
5447 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5448 (void *)bgep, (void *)ppd));
5449
5450 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5451
5452 switch (ppd->pp_acc_size) {
5453 case 1:
5454 regval = *(uint8_t *)vaddr;
5455 break;
5456
5457 case 2:
5458 regval = *(uint16_t *)vaddr;
5459 break;
5460
5461 case 4:
5462 regval = *(uint32_t *)vaddr;
5463 break;
5464
5465 case 8:
5466 regval = *(uint64_t *)vaddr;
5467 break;
5468 }
5469
5470 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5471 (void *)bgep, (void *)ppd, regval, vaddr));
5472
5473 ppd->pp_acc_data = regval;
5474 }
5475
5476 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5477 #pragma no_inline(bge_chip_poke_mem)
5478
5479 static void
5480 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5481 {
5482 uint64_t regval;
5483 void *vaddr;
5484
5485 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5486 (void *)bgep, (void *)ppd));
5487
5488 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5489 regval = ppd->pp_acc_data;
5490
5491 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5492 (void *)bgep, (void *)ppd, regval, vaddr));
5493
5494 switch (ppd->pp_acc_size) {
5495 case 1:
5496 *(uint8_t *)vaddr = (uint8_t)regval;
5497 break;
5498
5499 case 2:
5500 *(uint16_t *)vaddr = (uint16_t)regval;
5501 break;
5502
5503 case 4:
5504 *(uint32_t *)vaddr = (uint32_t)regval;
5505 break;
5506
5507 case 8:
5508 *(uint64_t *)vaddr = (uint64_t)regval;
5509 break;
5510 }
5511 }
5512
5513 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5514 struct iocblk *iocp);
5515 #pragma no_inline(bge_pp_ioctl)
5516
5517 static enum ioc_reply
5518 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5519 {
5520 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5521 bge_peekpoke_t *ppd;
5522 dma_area_t *areap;
5523 uint64_t sizemask;
5524 uint64_t mem_va;
5525 uint64_t maxoff;
5526 boolean_t peek;
5527
5528 switch (cmd) {
5529 default:
5530 /* NOTREACHED */
5531 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5532 return (IOC_INVAL);
5533
5534 case BGE_PEEK:
5535 peek = B_TRUE;
5536 break;
5537
5538 case BGE_POKE:
5539 peek = B_FALSE;
5540 break;
5541 }
5542
5543 /*
5544 * Validate format of ioctl
5545 */
5546 if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5547 return (IOC_INVAL);
5548 if (mp->b_cont == NULL)
5549 return (IOC_INVAL);
5550 ppd = (void *)mp->b_cont->b_rptr;
5551
5552 /*
5553 * Validate request parameters
5554 */
5555 switch (ppd->pp_acc_space) {
5556 default:
5557 return (IOC_INVAL);
5558
5559 case BGE_PP_SPACE_CFG:
5560 /*
5561 * Config space
5562 */
5563 sizemask = 8|4|2|1;
5564 mem_va = 0;
5565 maxoff = PCI_CONF_HDR_SIZE;
5566 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5567 break;
5568
5569 case BGE_PP_SPACE_REG:
5570 /*
5571 * Memory-mapped I/O space
5572 */
5573 sizemask = 8|4|2|1;
5574 mem_va = 0;
5575 maxoff = RIAAR_REGISTER_MAX;
5576 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5577 break;
5578
5579 case BGE_PP_SPACE_NIC:
5580 /*
5581 * NIC on-chip memory
5582 */
5583 sizemask = 8|4|2|1;
5584 mem_va = 0;
5585 maxoff = MWBAR_ONCHIP_MAX;
5586 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5587 break;
5588
5589 case BGE_PP_SPACE_MII:
5590 /*
5591 * PHY's MII registers
5592 * NB: all PHY registers are two bytes, but the
5593 * addresses increment in ones (word addressing).
5594 * So we scale the address here, then undo the
5595 * transformation inside the peek/poke functions.
5596 */
5597 ppd->pp_acc_offset *= 2;
5598 sizemask = 2;
5599 mem_va = 0;
5600 maxoff = (MII_MAXREG+1)*2;
5601 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5602 break;
5603
5604 #if BGE_SEE_IO32
5605 case BGE_PP_SPACE_SEEPROM:
5606 /*
5607 * Attached SEEPROM(s), if any.
5608 * NB: we use the high-order bits of the 'address' as
5609 * a device select to accommodate multiple SEEPROMS,
5610 * If each one is the maximum size (64kbytes), this
5611 * makes them appear contiguous. Otherwise, there may
5612 * be holes in the mapping. ENxS doesn't have any
5613 * SEEPROMs anyway ...
5614 */
5615 sizemask = 4;
5616 mem_va = 0;
5617 maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5618 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5619 break;
5620 #endif /* BGE_SEE_IO32 */
5621
5622 #if BGE_FLASH_IO32
5623 case BGE_PP_SPACE_FLASH:
5624 /*
5625 * Attached Flash device (if any); a maximum of one device
5626 * is currently supported. But it can be up to 1MB (unlike
5627 * the 64k limit on SEEPROMs) so why would you need more ;-)
5628 */
5629 sizemask = 4;
5630 mem_va = 0;
5631 maxoff = NVM_FLASH_ADDR_MASK;
5632 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5633 break;
5634 #endif /* BGE_FLASH_IO32 */
5635
5636 case BGE_PP_SPACE_BGE:
5637 /*
5638 * BGE data structure!
5639 */
5640 sizemask = 8|4|2|1;
5641 mem_va = (uintptr_t)bgep;
5642 maxoff = sizeof (*bgep);
5643 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5644 break;
5645
5646 case BGE_PP_SPACE_STATUS:
5647 case BGE_PP_SPACE_STATISTICS:
5648 case BGE_PP_SPACE_TXDESC:
5649 case BGE_PP_SPACE_TXBUFF:
5650 case BGE_PP_SPACE_RXDESC:
5651 case BGE_PP_SPACE_RXBUFF:
5652 /*
5653 * Various DMA_AREAs
5654 */
5655 switch (ppd->pp_acc_space) {
5656 case BGE_PP_SPACE_TXDESC:
5657 areap = &bgep->tx_desc;
5658 break;
5659 case BGE_PP_SPACE_TXBUFF:
5660 areap = &bgep->tx_buff[0];
5661 break;
5662 case BGE_PP_SPACE_RXDESC:
5663 areap = &bgep->rx_desc[0];
5664 break;
5665 case BGE_PP_SPACE_RXBUFF:
5666 areap = &bgep->rx_buff[0];
5667 break;
5668 case BGE_PP_SPACE_STATUS:
5669 areap = &bgep->status_block;
5670 break;
5671 case BGE_PP_SPACE_STATISTICS:
5672 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5673 areap = &bgep->statistics;
5674 break;
5675 }
5676
5677 sizemask = 8|4|2|1;
5678 mem_va = (uintptr_t)areap->mem_va;
5679 maxoff = areap->alength;
5680 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5681 break;
5682 }
5683
5684 switch (ppd->pp_acc_size) {
5685 default:
5686 return (IOC_INVAL);
5687
5688 case 8:
5689 case 4:
5690 case 2:
5691 case 1:
5692 if ((ppd->pp_acc_size & sizemask) == 0)
5693 return (IOC_INVAL);
5694 break;
5695 }
5696
5697 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5698 return (IOC_INVAL);
5699
5700 if (ppd->pp_acc_offset >= maxoff)
5701 return (IOC_INVAL);
5702
5703 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5704 return (IOC_INVAL);
5705
5706 /*
5707 * All OK - go do it!
5708 */
5709 ppd->pp_acc_offset += mem_va;
5710 (*ppfn)(bgep, ppd);
5711 return (peek ? IOC_REPLY : IOC_ACK);
5712 }
5713
5714 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5715 struct iocblk *iocp);
5716 #pragma no_inline(bge_diag_ioctl)
5717
5718 static enum ioc_reply
5719 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5720 {
5721 ASSERT(mutex_owned(bgep->genlock));
5722
5723 switch (cmd) {
5724 default:
5725 /* NOTREACHED */
5726 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5727 return (IOC_INVAL);
5728
5729 case BGE_DIAG:
5730 /*
5731 * Currently a no-op
5732 */
5733 return (IOC_ACK);
5734
5735 case BGE_PEEK:
5736 case BGE_POKE:
5737 return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5738
5739 case BGE_PHY_RESET:
5740 return (IOC_RESTART_ACK);
5741
5742 case BGE_SOFT_RESET:
5743 case BGE_HARD_RESET:
5744 /*
5745 * Reset and reinitialise the 570x hardware
5746 */
5747 bgep->bge_chip_state = BGE_CHIP_FAULT;
5748 ddi_trigger_softintr(bgep->factotum_id);
5749 (void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5750 return (IOC_ACK);
5751 }
5752
5753 /* NOTREACHED */
5754 }
5755
5756 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
5757
5758 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5759 struct iocblk *iocp);
5760 #pragma no_inline(bge_mii_ioctl)
5761
5762 static enum ioc_reply
5763 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5764 {
5765 struct bge_mii_rw *miirwp;
5766
5767 /*
5768 * Validate format of ioctl
5769 */
5770 if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5771 return (IOC_INVAL);
5772 if (mp->b_cont == NULL)
5773 return (IOC_INVAL);
5774 miirwp = (void *)mp->b_cont->b_rptr;
5775
5776 /*
5777 * Validate request parameters ...
5778 */
5779 if (miirwp->mii_reg > MII_MAXREG)
5780 return (IOC_INVAL);
5781
5782 switch (cmd) {
5783 default:
5784 /* NOTREACHED */
5785 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5786 return (IOC_INVAL);
5787
5788 case BGE_MII_READ:
5789 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5790 return (IOC_REPLY);
5791
5792 case BGE_MII_WRITE:
5793 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5794 return (IOC_ACK);
5795 }
5796
5797 /* NOTREACHED */
5798 }
5799
5800 #if BGE_SEE_IO32
5801
5802 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5803 struct iocblk *iocp);
5804 #pragma no_inline(bge_see_ioctl)
5805
5806 static enum ioc_reply
5807 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5808 {
5809 struct bge_see_rw *seerwp;
5810
5811 /*
5812 * Validate format of ioctl
5813 */
5814 if (iocp->ioc_count != sizeof (struct bge_see_rw))
5815 return (IOC_INVAL);
5816 if (mp->b_cont == NULL)
5817 return (IOC_INVAL);
5818 seerwp = (void *)mp->b_cont->b_rptr;
5819
5820 /*
5821 * Validate request parameters ...
5822 */
5823 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5824 return (IOC_INVAL);
5825
5826 switch (cmd) {
5827 default:
5828 /* NOTREACHED */
5829 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5830 return (IOC_INVAL);
5831
5832 case BGE_SEE_READ:
5833 case BGE_SEE_WRITE:
5834 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5835 seerwp->see_addr, &seerwp->see_data);
5836 return (IOC_REPLY);
5837 }
5838
5839 /* NOTREACHED */
5840 }
5841
5842 #endif /* BGE_SEE_IO32 */
5843
5844 #if BGE_FLASH_IO32
5845
5846 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5847 struct iocblk *iocp);
5848 #pragma no_inline(bge_flash_ioctl)
5849
5850 static enum ioc_reply
5851 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5852 {
5853 struct bge_flash_rw *flashrwp;
5854
5855 /*
5856 * Validate format of ioctl
5857 */
5858 if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5859 return (IOC_INVAL);
5860 if (mp->b_cont == NULL)
5861 return (IOC_INVAL);
5862 flashrwp = (void *)mp->b_cont->b_rptr;
5863
5864 /*
5865 * Validate request parameters ...
5866 */
5867 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5868 return (IOC_INVAL);
5869
5870 switch (cmd) {
5871 default:
5872 /* NOTREACHED */
5873 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5874 return (IOC_INVAL);
5875
5876 case BGE_FLASH_READ:
5877 case BGE_FLASH_WRITE:
5878 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5879 flashrwp->flash_addr, &flashrwp->flash_data);
5880 return (IOC_REPLY);
5881 }
5882
5883 /* NOTREACHED */
5884 }
5885
5886 #endif /* BGE_FLASH_IO32 */
5887
5888 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5889 struct iocblk *iocp);
5890 #pragma no_inline(bge_chip_ioctl)
5891
5892 enum ioc_reply
5893 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5894 {
5895 int cmd;
5896
5897 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5898 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5899
5900 ASSERT(mutex_owned(bgep->genlock));
5901
5902 cmd = iocp->ioc_cmd;
5903 switch (cmd) {
5904 default:
5905 /* NOTREACHED */
5906 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5907 return (IOC_INVAL);
5908
5909 case BGE_DIAG:
5910 case BGE_PEEK:
5911 case BGE_POKE:
5912 case BGE_PHY_RESET:
5913 case BGE_SOFT_RESET:
5914 case BGE_HARD_RESET:
5915 #if BGE_DEBUGGING || BGE_DO_PPIO
5916 return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5917 #else
5918 return (IOC_INVAL);
5919 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
5920
5921 case BGE_MII_READ:
5922 case BGE_MII_WRITE:
5923 return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5924
5925 #if BGE_SEE_IO32
5926 case BGE_SEE_READ:
5927 case BGE_SEE_WRITE:
5928 return (bge_see_ioctl(bgep, cmd, mp, iocp));
5929 #endif /* BGE_SEE_IO32 */
5930
5931 #if BGE_FLASH_IO32
5932 case BGE_FLASH_READ:
5933 case BGE_FLASH_WRITE:
5934 return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5935 #endif /* BGE_FLASH_IO32 */
5936 }
5937
5938 /* NOTREACHED */
5939 }
5940
5941 /* ARGSUSED */
5942 void
5943 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
5944 {
5945 recv_ring_t *rrp = arg;
5946 bge_t *bgep = rrp->bgep;
5947
5948 mutex_enter(bgep->genlock);
5949 rrp->poll_flag = flag;
5950 #ifdef NOT_YET
5951 /*
5952 * XXX-Sunay: Since most broadcom cards support only one
5953 * interrupt but multiple rx rings, we can't disable the
5954 * physical interrupt. This need to be done via capability
5955 * negotiation depending on the NIC.
5956 */
5957 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5958 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5959 #endif
5960 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5961 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5962 mutex_exit(bgep->genlock);
5963 }
5964
5965 #ifdef BGE_IPMI_ASF
5966
5967 uint32_t
5968 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5969 {
5970 uint32_t data;
5971
5972 #ifndef __sparc
5973 if (!bgep->asf_wordswapped) {
5974 /* a workaround word swap error */
5975 if (addr & 4)
5976 addr = addr - 4;
5977 else
5978 addr = addr + 4;
5979 }
5980 #else
5981 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
5982 addr = LE_32(addr);
5983 #endif
5984
5985 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5986 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5987 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5988
5989 data = LE_32(data);
5990
5991 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
5992 (void *)bgep, addr, data));
5993
5994 return (data);
5995 }
5996
5997 void
5998 bge_asf_update_status(bge_t *bgep)
5999 {
6000 uint32_t event;
6001
6002 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
6003 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
6004 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3);
6005
6006 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6007 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6008 }
6009
6010
6011 /*
6012 * The driver is supposed to notify ASF that the OS is still running
6013 * every three seconds, otherwise the management server may attempt
6014 * to reboot the machine. If it hasn't actually failed, this is
6015 * not a desirable result. However, this isn't running as a real-time
6016 * thread, and even if it were, it might not be able to generate the
6017 * heartbeat in a timely manner due to system load. As it isn't a
6018 * significant strain on the machine, we will set the interval to half
6019 * of the required value.
6020 */
6021 void
6022 bge_asf_heartbeat(void *arg)
6023 {
6024 bge_t *bgep = (bge_t *)arg;
6025
6026 mutex_enter(bgep->genlock);
6027 bge_asf_update_status((bge_t *)bgep);
6028 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
6029 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6030 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
6031 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
6032 mutex_exit(bgep->genlock);
6033 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
6034 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
6035 }
6036
6037
6038 void
6039 bge_asf_stop_timer(bge_t *bgep)
6040 {
6041 timeout_id_t tmp_id = 0;
6042
6043 while ((bgep->asf_timeout_id != 0) &&
6044 (tmp_id != bgep->asf_timeout_id)) {
6045 tmp_id = bgep->asf_timeout_id;
6046 (void) untimeout(tmp_id);
6047 }
6048 bgep->asf_timeout_id = 0;
6049 }
6050
6051
6052
6053 /*
6054 * This function should be placed at the earliest position of bge_attach().
6055 */
6056 void
6057 bge_asf_get_config(bge_t *bgep)
6058 {
6059 uint32_t nicsig;
6060 uint32_t niccfg;
6061
6062 bgep->asf_enabled = B_FALSE;
6063 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
6064 if (nicsig == BGE_NIC_DATA_SIG) {
6065 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
6066 if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
6067 /*
6068 * Here, we don't consider BAXTER, because BGE haven't
6069 * supported BAXTER (that is 5752). Also, as I know,
6070 * BAXTER doesn't support ASF feature.
6071 */
6072 bgep->asf_enabled = B_TRUE;
6073 else
6074 bgep->asf_enabled = B_FALSE;
6075 } else
6076 bgep->asf_enabled = B_FALSE;
6077 }
6078
6079
6080 void
6081 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
6082 {
6083 uint32_t tries;
6084 uint32_t event;
6085
6086 ASSERT(bgep->asf_enabled);
6087
6088 /* Issues "pause firmware" command and wait for ACK */
6089 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
6090 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6091 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
6092
6093 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6094 tries = 0;
6095 while ((event & RRER_ASF_EVENT) && (tries < 100)) {
6096 drv_usecwait(1);
6097 tries ++;
6098 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
6099 }
6100
6101 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
6102 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
6103
6104 if (bgep->asf_newhandshake) {
6105 switch (mode) {
6106 case BGE_INIT_RESET:
6107 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6108 BGE_DRV_STATE_START);
6109 break;
6110 case BGE_SHUTDOWN_RESET:
6111 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6112 BGE_DRV_STATE_UNLOAD);
6113 break;
6114 case BGE_SUSPEND_RESET:
6115 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6116 BGE_DRV_STATE_SUSPEND);
6117 break;
6118 default:
6119 break;
6120 }
6121 }
6122 }
6123
6124
6125 void
6126 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
6127 {
6128 switch (mode) {
6129 case BGE_INIT_RESET:
6130 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6131 BGE_DRV_STATE_START);
6132 break;
6133 case BGE_SHUTDOWN_RESET:
6134 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6135 BGE_DRV_STATE_UNLOAD);
6136 break;
6137 case BGE_SUSPEND_RESET:
6138 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6139 BGE_DRV_STATE_SUSPEND);
6140 break;
6141 default:
6142 break;
6143 }
6144 }
6145
6146
6147 void
6148 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
6149 {
6150 switch (mode) {
6151 case BGE_INIT_RESET:
6152 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6153 BGE_DRV_STATE_START_DONE);
6154 break;
6155 case BGE_SHUTDOWN_RESET:
6156 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
6157 BGE_DRV_STATE_UNLOAD_DONE);
6158 break;
6159 default:
6160 break;
6161 }
6162 }
6163
6164 #endif /* BGE_IPMI_ASF */