1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /*
27 * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
28 */
29
30 #include "bge_impl.h"
31
32 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset)))
33
34 /*
35 * Future features ... ?
36 */
37 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */
38 #define BGE_IND_IO32 1 /* indirect access code */
39 #define BGE_SEE_IO32 1 /* SEEPROM access code */
40 #define BGE_FLASH_IO32 1 /* FLASH access code */
41
42 /*
43 * BGE MSI tunable:
44 *
45 * By default MSI is enabled on all supported platforms but it is disabled
46 * for some Broadcom chips due to known MSI hardware issues. Currently MSI
47 * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
48 */
49 boolean_t bge_enable_msi = B_TRUE;
50
51 /*
52 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
53 */
54 boolean_t bge_relaxed_ordering = B_TRUE;
55
56 /*
57 * Property names
58 */
59 static char knownids_propname[] = "bge-known-subsystems";
60
61 /*
62 * Patchable globals:
63 *
64 * bge_autorecover
65 * Enables/disables automatic recovery after fault detection
66 *
67 * bge_mlcr_default
68 * Value to program into the MLCR; controls the chip's GPIO pins
69 *
70 * bge_dma_{rd,wr}prio
71 * Relative priorities of DMA reads & DMA writes respectively.
72 * These may each be patched to any value 0-3. Equal values
73 * will give "fair" (round-robin) arbitration for PCI access.
74 * Unequal values will give one or the other function priority.
75 *
76 * bge_dma_rwctrl
77 * Value to put in the Read/Write DMA control register. See
78 * the Broadcom PRM for things you can fiddle with in this
79 * register ...
80 *
81 * bge_{tx,rx}_{count,ticks}_{norm,intr}
82 * Send/receive interrupt coalescing parameters. Counts are
83 * #s of descriptors, ticks are in microseconds. *norm* values
84 * apply between status updates/interrupts; the *intr* values
85 * refer to the 'during-interrupt' versions - see the PRM.
86 *
87 * NOTE: these values have been determined by measurement. They
88 * differ significantly from the values recommended in the PRM.
89 */
90 static uint32_t bge_autorecover = 1;
91 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
92
93 static uint32_t bge_dma_rdprio = 1;
94 static uint32_t bge_dma_wrprio = 0;
95 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
96 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
97 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
98 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
99
100 uint32_t bge_rx_ticks_norm = 128;
101 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */
102 uint32_t bge_rx_count_norm = 8;
103 uint32_t bge_tx_count_norm = 128;
104
105 static uint32_t bge_rx_ticks_intr = 128;
106 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */
107 static uint32_t bge_rx_count_intr = 2;
108 static uint32_t bge_tx_count_intr = 0;
109
110 /*
111 * Memory pool configuration parameters.
112 *
113 * These are generally specific to each member of the chip family, since
114 * each one may have a different memory size/configuration.
115 *
116 * Setting the mbuf pool length for a specific type of chip to 0 inhibits
117 * the driver from programming the various registers; instead they are left
118 * at their hardware defaults. This is the preferred option for later chips
119 * (5705+), whereas the older chips *required* these registers to be set,
120 * since the h/w default was 0 ;-(
121 */
122 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT;
123 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704;
124 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705;
125 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
126 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT;
127 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704;
128 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */
129 static uint32_t bge_mbuf_pool_len_5721 = 0;
130
131 /*
132 * Various high and low water marks, thresholds, etc ...
133 *
134 * Note: these are taken from revision 7 of the PRM, and some are different
135 * from both the values in earlier PRMs *and* those determined experimentally
136 * and used in earlier versions of this driver ...
137 */
138 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT;
139 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT;
140 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT;
141
142 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT;
143 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT;
144 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT;
145
146 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT;
147 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT;
148 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT;
149
150 static uint32_t bge_watchdog_count = 1 << 16;
151 static uint16_t bge_dma_miss_limit = 20;
152
153 static uint32_t bge_stop_start_on_sync = 0;
154
155 /*
156 * bge_intr_max_loop controls the maximum loop number within bge_intr.
157 * When loading NIC with heavy network traffic, it is useful.
158 * Increasing this value could have positive effect to throughput,
159 * but it might also increase ticks of a bge ISR stick on CPU, which might
160 * lead to bad UI interactive experience. So tune this with caution.
161 */
162 static int bge_intr_max_loop = 1;
163
164 /*
165 * ========== Low-level chip & ring buffer manipulation ==========
166 */
167
168 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */
169
170
171 /*
172 * Config space read-modify-write routines
173 */
174
175 #if BGE_CFG_IO8
176
177 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
178 #pragma inline(bge_cfg_clr16)
179
180 static void
181 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
182 {
183 uint16_t regval;
184
185 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
186 (void *)bgep, regno, bits));
187
188 regval = pci_config_get16(bgep->cfg_handle, regno);
189
190 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
191 (void *)bgep, regno, bits, regval, regval & ~bits));
192
193 regval &= ~bits;
194 pci_config_put16(bgep->cfg_handle, regno, regval);
195 }
196
197 #endif /* BGE_CFG_IO8 */
198
199 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
200 #pragma inline(bge_cfg_clr32)
201
202 static void
203 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
204 {
205 uint32_t regval;
206
207 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
208 (void *)bgep, regno, bits));
209
210 regval = pci_config_get32(bgep->cfg_handle, regno);
211
212 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
213 (void *)bgep, regno, bits, regval, regval & ~bits));
214
215 regval &= ~bits;
216 pci_config_put32(bgep->cfg_handle, regno, regval);
217 }
218
219 #if BGE_IND_IO32
220
221 /*
222 * Indirect access to registers & RISC scratchpads, using config space
223 * accesses only.
224 *
225 * This isn't currently used, but someday we might want to use it for
226 * restoring the Subsystem Device/Vendor registers (which aren't directly
227 * writable in Config Space), or for downloading firmware into the RISCs
228 *
229 * In any case there are endian issues to be resolved before this code is
230 * enabled; the bizarre way that bytes get twisted by this chip AND by
231 * the PCI bridge in SPARC systems mean that we shouldn't enable it until
232 * it's been thoroughly tested for all access sizes on all supported
233 * architectures (SPARC *and* x86!).
234 */
235 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
236 #pragma inline(bge_ind_get32)
237
238 uint32_t
239 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
240 {
241 uint32_t val;
242
243 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
244
245 #ifdef __sparc
246 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
247 regno = LE_32(regno);
248 #endif
249 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
250 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
251
252 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
253 (void *)bgep, regno, val));
254
255 val = LE_32(val);
256
257 return (val);
258 }
259
260 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
261 #pragma inline(bge_ind_put32)
262
263 void
264 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
265 {
266 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
267 (void *)bgep, regno, val));
268
269 val = LE_32(val);
270 #ifdef __sparc
271 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
272 regno = LE_32(regno);
273 #endif
274 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
275 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
276 }
277
278 #endif /* BGE_IND_IO32 */
279
280 #if BGE_DEBUGGING
281
282 static void bge_pci_check(bge_t *bgep);
283 #pragma no_inline(bge_pci_check)
284
285 static void
286 bge_pci_check(bge_t *bgep)
287 {
288 uint16_t pcistatus;
289
290 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
291 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
292 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
293 (void *)bgep, pcistatus));
294 }
295
296 #endif /* BGE_DEBUGGING */
297
298 /*
299 * Perform first-stage chip (re-)initialisation, using only config-space
300 * accesses:
301 *
302 * + Read the vendor/device/revision/subsystem/cache-line-size registers,
303 * returning the data in the structure pointed to by <idp>.
304 * + Configure the target-mode endianness (swap) options.
305 * + Disable interrupts and enable Memory Space accesses.
306 * + Enable or disable Bus Mastering according to the <enable_dma> flag.
307 *
308 * This sequence is adapted from Broadcom document 570X-PG102-R,
309 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence
310 * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
311 *
312 * This function MUST be called before any non-config-space accesses
313 * are made; on this first call <enable_dma> is B_FALSE, and it
314 * effectively performs steps 3-1(!) of the initialisation sequence
315 * (the rest are not required but should be harmless).
316 *
317 * It MUST also be called after a chip reset, as this disables
318 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and
319 * it is effectively performing steps 6-8.
320 */
321 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
322 #pragma no_inline(bge_chip_cfg_init)
323
324 void
325 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
326 {
327 ddi_acc_handle_t handle;
328 uint16_t command;
329 uint32_t mhcr;
330 uint16_t value16;
331 int i;
332
333 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
334 (void *)bgep, (void *)cidp, enable_dma));
335
336 /*
337 * Step 3: save PCI cache line size and subsystem vendor ID
338 *
339 * Read all the config-space registers that characterise the
340 * chip, specifically vendor/device/revision/subsystem vendor
341 * and subsystem device id. We expect (but don't check) that
342 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
343 *
344 * Also save all bus-transaction related registers (cache-line
345 * size, bus-grant/latency parameters, etc). Some of these are
346 * cleared by reset, so we'll have to restore them later. This
347 * comes from the Broadcom document 570X-PG102-R ...
348 *
349 * Note: Broadcom document 570X-PG102-R seems to be in error
350 * here w.r.t. the offsets of the Subsystem Vendor ID and
351 * Subsystem (Device) ID registers, which are the opposite way
352 * round according to the PCI standard. For good measure, we
353 * save/restore both anyway.
354 */
355 handle = bgep->cfg_handle;
356
357 /*
358 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
359 * has been set in PCI_CONF_COMM already, we need to write the
360 * byte-swapped value to it. So we just write zero first for simplicity.
361 */
362 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
363 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
364 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
365 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
366 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
367 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
368 cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
369
370 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
371 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
372 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
373 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
374 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
375 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
376
377 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
378 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
379 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
380 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
381 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
382 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
383 cidp->vendor, cidp->device, cidp->revision));
384 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
385 cidp->subven, cidp->subdev, cidp->asic_rev));
386 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
387 cidp->clsize, cidp->latency, cidp->command));
388
389 /*
390 * Step 2 (also step 6): disable and clear interrupts.
391 * Steps 11-13: configure PIO endianness options, and enable
392 * indirect register access. We'll also select any other
393 * options controlled by the MHCR (e.g. tagged status, mask
394 * interrupt mode) at this stage ...
395 *
396 * Note: internally, the chip is 64-bit and BIG-endian, but
397 * since it talks to the host over a (LITTLE-endian) PCI bus,
398 * it normally swaps bytes around at the PCI interface.
399 * However, the PCI host bridge on SPARC systems normally
400 * swaps the byte lanes around too, since SPARCs are also
401 * BIG-endian. So it turns out that on SPARC, the right
402 * option is to tell the chip to swap (and the host bridge
403 * will swap back again), whereas on x86 we ask the chip
404 * NOT to swap, so the natural little-endianness of the
405 * PCI bus is assumed. Then the only thing that doesn't
406 * automatically work right is access to an 8-byte register
407 * by a little-endian host; but we don't want to set the
408 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
409 * accesses don't go where expected ;-( So we live with
410 * that, and perform word-swaps in software in the few cases
411 * where a chip register is defined as an 8-byte value --
412 * see the code below for details ...
413 *
414 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
415 * very clear in the register description in the PRM, but
416 * Broadcom document 570X-PG104-R page 248 explains a little
417 * more (under "Broadcom Mask Mode"). The bit changes the way
418 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
419 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
420 * way as the 5700 did, which isn't very convenient. Setting
421 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
422 * bit do just what its name says -- MASK the PCI #INTA output
423 * (i.e. deassert the signal at the pin) leaving all internal
424 * state unchanged. This is much more convenient for our
425 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
426 *
427 * Note: the inconvenient semantics of the interrupt mailbox
428 * (nonzero disables and acknowledges/clears the interrupt,
429 * zero enables AND CLEARS it) would make race conditions
430 * likely in the interrupt handler:
431 *
432 * (1) acknowledge & disable interrupts
433 * (2) while (more to do)
434 * process packets
435 * (3) enable interrupts -- also clears pending
436 *
437 * If the chip received more packets and internally generated
438 * an interrupt between the check at (2) and the mbox write
439 * at (3), this interrupt would be lost :-(
440 *
441 * The best way to avoid this is to use TAGGED STATUS mode,
442 * where the chip includes a unique tag in each status block
443 * update, and the host, when re-enabling interrupts, passes
444 * the last tag it saw back to the chip; then the chip can
445 * see whether the host is truly up to date, and regenerate
446 * its interrupt if not.
447 */
448 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
449 MHCR_ENABLE_TAGGED_STATUS_MODE |
450 MHCR_MASK_INTERRUPT_MODE |
451 MHCR_CLEAR_INTERRUPT_INTA;
452
453 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
454 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
455
456 #ifdef _BIG_ENDIAN
457 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
458 #endif /* _BIG_ENDIAN */
459
460 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
461 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
462 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
463
464 #ifdef BGE_IPMI_ASF
465 bgep->asf_wordswapped = B_FALSE;
466 #endif
467 /*
468 * Step 1 (also step 7): Enable PCI Memory Space accesses
469 * Disable Memory Write/Invalidate
470 * Enable or disable Bus Mastering
471 *
472 * Note that all other bits are taken from the original value saved
473 * the first time through here, rather than from the current register
474 * value, 'cos that will have been cleared by a soft RESET since.
475 * In this way we preserve the OBP/nexus-parent's preferred settings
476 * of the parity-error and system-error enable bits across multiple
477 * chip RESETs.
478 */
479 command = bgep->chipid.command | PCI_COMM_MAE;
480 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
481 if (enable_dma)
482 command |= PCI_COMM_ME;
483 /*
484 * on BCM5714 revision A0, false parity error gets generated
485 * due to a logic bug. Provide a workaround by disabling parity
486 * error.
487 */
488 if (((cidp->device == DEVICE_ID_5714C) ||
489 (cidp->device == DEVICE_ID_5714S)) &&
490 (cidp->revision == REVISION_ID_5714_A0)) {
491 command &= ~PCI_COMM_PARITY_DETECT;
492 }
493 pci_config_put16(handle, PCI_CONF_COMM, command);
494
495 /*
496 * On some PCI-E device, there were instances when
497 * the device was still link training.
498 */
499 if (bgep->chipid.pci_type == BGE_PCI_E) {
500 i = 0;
501 value16 = pci_config_get16(handle, PCI_CONF_COMM);
502 while ((value16 != command) && (i < 100)) {
503 drv_usecwait(200);
504 value16 = pci_config_get16(handle, PCI_CONF_COMM);
505 ++i;
506 }
507 }
508
509 /*
510 * Clear any remaining error status bits
511 */
512 pci_config_put16(handle, PCI_CONF_STAT, ~0);
513
514 /*
515 * Do following if and only if the device is NOT BCM5714C OR
516 * BCM5715C
517 */
518 if (!((cidp->device == DEVICE_ID_5714C) ||
519 (cidp->device == DEVICE_ID_5715C))) {
520 /*
521 * Make sure these indirect-access registers are sane
522 * rather than random after power-up or reset
523 */
524 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
525 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
526 }
527 /*
528 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
529 */
530 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
531
532 if (cidp->pci_type == BGE_PCI_E) {
533 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
534 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
535 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
536 } else
537 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
538 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
539 }
540 }
541
542 #ifdef __amd64
543 /*
544 * Distinguish CPU types
545 *
546 * These use to distinguish AMD64 or Intel EM64T of CPU running mode.
547 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
548 * for PCI-Express based network interface card. This is the work-around
549 * for those nics.
550 */
551 static boolean_t bge_get_em64t_type(void);
552 #pragma inline(bge_get_em64t_type)
553
554 static boolean_t
555 bge_get_em64t_type(void)
556 {
557
558 return (x86_vendor == X86_VENDOR_Intel);
559 }
560 #endif
561
562 /*
563 * Operating register get/set access routines
564 */
565
566 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
567 #pragma inline(bge_reg_get32)
568
569 uint32_t
570 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
571 {
572 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
573 (void *)bgep, regno));
574
575 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
576 }
577
578 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
579 #pragma inline(bge_reg_put32)
580
581 void
582 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
583 {
584 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
585 (void *)bgep, regno, data));
586
587 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
588 BGE_PCICHK(bgep);
589 }
590
591 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
592 #pragma inline(bge_reg_set32)
593
594 void
595 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
596 {
597 uint32_t regval;
598
599 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
600 (void *)bgep, regno, bits));
601
602 regval = bge_reg_get32(bgep, regno);
603 regval |= bits;
604 bge_reg_put32(bgep, regno, regval);
605 }
606
607 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
608 #pragma inline(bge_reg_clr32)
609
610 void
611 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
612 {
613 uint32_t regval;
614
615 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
616 (void *)bgep, regno, bits));
617
618 regval = bge_reg_get32(bgep, regno);
619 regval &= ~bits;
620 bge_reg_put32(bgep, regno, regval);
621 }
622
623 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
624 #pragma inline(bge_reg_get64)
625
626 static uint64_t
627 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
628 {
629 uint64_t regval;
630
631 #ifdef __amd64
632 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
633 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
634 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
635 regval <<= 32;
636 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
637 } else {
638 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
639 }
640 #elif defined(__sparc)
641 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
642 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
643 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
644 regval <<= 32;
645 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
646 } else {
647 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
648 }
649 #else
650 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
651 #endif
652
653 #ifdef _LITTLE_ENDIAN
654 regval = (regval >> 32) | (regval << 32);
655 #endif /* _LITTLE_ENDIAN */
656
657 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
658 (void *)bgep, regno, regval));
659
660 return (regval);
661 }
662
663 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
664 #pragma inline(bge_reg_put64)
665
666 static void
667 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
668 {
669 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
670 (void *)bgep, regno, data));
671
672 #ifdef _LITTLE_ENDIAN
673 data = ((data >> 32) | (data << 32));
674 #endif /* _LITTLE_ENDIAN */
675
676 #ifdef __amd64
677 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
678 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
679 ddi_put32(bgep->io_handle,
680 PIO_ADDR(bgep, regno), (uint32_t)data);
681 BGE_PCICHK(bgep);
682 ddi_put32(bgep->io_handle,
683 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
684
685 } else {
686 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
687 }
688 #elif defined(__sparc)
689 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
690 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
691 ddi_put32(bgep->io_handle,
692 PIO_ADDR(bgep, regno + 4), (uint32_t)data);
693 BGE_PCICHK(bgep);
694 ddi_put32(bgep->io_handle,
695 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
696 } else {
697 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
698 }
699 #else
700 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
701 #endif
702
703 BGE_PCICHK(bgep);
704 }
705
706 /*
707 * The DDI doesn't provide get/put functions for 128 bit data
708 * so we put RCBs out as two 64-bit chunks instead.
709 */
710 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
711 #pragma inline(bge_reg_putrcb)
712
713 static void
714 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
715 {
716 uint64_t *p;
717
718 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
719 (void *)bgep, addr, rcbp->host_ring_addr,
720 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
721
722 ASSERT((addr % sizeof (*rcbp)) == 0);
723
724 p = (void *)rcbp;
725 bge_reg_put64(bgep, addr, *p++);
726 bge_reg_put64(bgep, addr+8, *p);
727 }
728
729 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
730 #pragma inline(bge_mbx_put)
731
732 void
733 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
734 {
735 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
736 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
737
738 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
739 (void *)bgep, regno, data));
740
741 /*
742 * Mailbox registers are nominally 64 bits on the 5701, but
743 * the MSW isn't used. On the 5703, they're only 32 bits
744 * anyway. So here we just write the lower(!) 32 bits -
745 * remembering that the chip is big-endian, even though the
746 * PCI bus is little-endian ...
747 */
748 #ifdef _BIG_ENDIAN
749 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
750 #else
751 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
752 #endif /* _BIG_ENDIAN */
753 BGE_PCICHK(bgep);
754 }
755
756 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
757 #pragma inline(bge_mbx_get)
758
759 uint32_t
760 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
761 {
762 uint32_t val32;
763
764 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
765 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
766
767 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
768 (void *)bgep, regno));
769
770 #ifdef _BIG_ENDIAN
771 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
772 #else
773 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
774 #endif /* _BIG_ENDIAN */
775 BGE_PCICHK(bgep);
776
777 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
778 (void *)bgep, regno, val32));
779
780 return (val32);
781 }
782
783
784 #if BGE_DEBUGGING
785
786 void bge_led_mark(bge_t *bgep);
787 #pragma no_inline(bge_led_mark)
788
789 void
790 bge_led_mark(bge_t *bgep)
791 {
792 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
793 LED_CONTROL_1000MBPS_LED |
794 LED_CONTROL_100MBPS_LED |
795 LED_CONTROL_10MBPS_LED;
796
797 /*
798 * Blink all three LINK LEDs on simultaneously, then all off,
799 * then restore to automatic hardware control. This is used
800 * in laboratory testing to trigger a logic analyser or scope.
801 */
802 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
803 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
804 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
805 led_ctrl = LED_CONTROL_OVERRIDE_LINK;
806 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
807 }
808
809 #endif /* BGE_DEBUGGING */
810
811 /*
812 * NIC on-chip memory access routines
813 *
814 * Only 32K of NIC memory is visible at a time, controlled by the
815 * Memory Window Base Address Register (in PCI config space). Once
816 * this is set, the 32K region of NIC-local memory that it refers
817 * to can be directly addressed in the upper 32K of the 64K of PCI
818 * memory space used for the device.
819 */
820
821 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
822 #pragma inline(bge_nic_setwin)
823
824 static void
825 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
826 {
827 chip_id_t *cidp;
828
829 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
830 (void *)bgep, base));
831
832 ASSERT((base & MWBAR_GRANULE_MASK) == 0);
833
834 /*
835 * Don't do repeated zero data writes,
836 * if the device is BCM5714C/15C.
837 */
838 cidp = &bgep->chipid;
839 if ((cidp->device == DEVICE_ID_5714C) ||
840 (cidp->device == DEVICE_ID_5715C)) {
841 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
842 return;
843 /* Adjust lastWriteZeroData */
844 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
845 B_TRUE : B_FALSE);
846 }
847 #ifdef __sparc
848 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
849 base = LE_32(base);
850 #endif
851 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
852 }
853
854 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
855 #pragma inline(bge_nic_get32)
856
857 static uint32_t
858 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
859 {
860 uint32_t data;
861
862 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
863 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
864 /* workaround for word swap error */
865 if (addr & 4)
866 addr = addr - 4;
867 else
868 addr = addr + 4;
869 }
870 #endif
871
872 #ifdef __sparc
873 data = bge_nic_read32(bgep, addr);
874 #else
875 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
876 addr &= MWBAR_GRANULE_MASK;
877 addr += NIC_MEM_WINDOW_OFFSET;
878
879 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
880 #endif
881
882 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
883 (void *)bgep, addr, data));
884
885 return (data);
886 }
887
888 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
889 #pragma inline(bge_nic_put32)
890
891 void
892 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
893 {
894 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
895 (void *)bgep, addr, data));
896
897 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
898 if (bgep->asf_enabled && !bgep->asf_wordswapped) {
899 /* workaround for word swap error */
900 if (addr & 4)
901 addr = addr - 4;
902 else
903 addr = addr + 4;
904 }
905 #endif
906
907 #ifdef __sparc
908 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
909 addr = LE_32(addr);
910 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
911 data = LE_32(data);
912 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
913 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
914 #else
915 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
916 addr &= MWBAR_GRANULE_MASK;
917 addr += NIC_MEM_WINDOW_OFFSET;
918 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
919 BGE_PCICHK(bgep);
920 #endif
921 }
922
923 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
924 #pragma inline(bge_nic_get64)
925
926 static uint64_t
927 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
928 {
929 uint64_t data;
930
931 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
932 addr &= MWBAR_GRANULE_MASK;
933 addr += NIC_MEM_WINDOW_OFFSET;
934
935 #ifdef __amd64
936 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
937 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
938 data = ddi_get32(bgep->io_handle,
939 PIO_ADDR(bgep, addr + 4));
940 data <<= 32;
941 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
942 } else {
943 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
944 }
945 #elif defined(__sparc)
946 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
947 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
948 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
949 data <<= 32;
950 data |= ddi_get32(bgep->io_handle,
951 PIO_ADDR(bgep, addr + 4));
952 } else {
953 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
954 }
955 #else
956 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
957 #endif
958
959 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
960 (void *)bgep, addr, data));
961
962 return (data);
963 }
964
965 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
966 #pragma inline(bge_nic_put64)
967
968 static void
969 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
970 {
971 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
972 (void *)bgep, addr, data));
973
974 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
975 addr &= MWBAR_GRANULE_MASK;
976 addr += NIC_MEM_WINDOW_OFFSET;
977
978 #ifdef __amd64
979 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
980 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
981 ddi_put32(bgep->io_handle,
982 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
983 BGE_PCICHK(bgep);
984 ddi_put32(bgep->io_handle,
985 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
986 } else {
987 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
988 }
989 #elif defined(__sparc)
990 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
991 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
992 ddi_put32(bgep->io_handle,
993 PIO_ADDR(bgep, addr + 4), (uint32_t)data);
994 BGE_PCICHK(bgep);
995 ddi_put32(bgep->io_handle,
996 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
997 } else {
998 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
999 }
1000 #else
1001 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
1002 #endif
1003
1004 BGE_PCICHK(bgep);
1005 }
1006
1007 /*
1008 * The DDI doesn't provide get/put functions for 128 bit data
1009 * so we put RCBs out as two 64-bit chunks instead.
1010 */
1011 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1012 #pragma inline(bge_nic_putrcb)
1013
1014 static void
1015 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1016 {
1017 uint64_t *p;
1018
1019 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1020 (void *)bgep, addr, rcbp->host_ring_addr,
1021 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
1022
1023 ASSERT((addr % sizeof (*rcbp)) == 0);
1024
1025 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1026 addr &= MWBAR_GRANULE_MASK;
1027 addr += NIC_MEM_WINDOW_OFFSET;
1028
1029 p = (void *)rcbp;
1030 #ifdef __amd64
1031 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1032 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1033 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1034 (uint32_t)(*p));
1035 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1036 (uint32_t)(*p++ >> 32));
1037 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1038 (uint32_t)(*p));
1039 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1040 (uint32_t)(*p >> 32));
1041
1042 } else {
1043 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1044 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1045 }
1046 #elif defined(__sparc)
1047 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1048 DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1049 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1050 (uint32_t)(*p));
1051 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1052 (uint32_t)(*p++ >> 32));
1053 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1054 (uint32_t)(*p));
1055 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1056 (uint32_t)(*p >> 32));
1057 } else {
1058 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1059 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1060 }
1061 #else
1062 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1063 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1064 #endif
1065
1066 BGE_PCICHK(bgep);
1067 }
1068
1069 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1070 #pragma inline(bge_nic_zero)
1071
1072 static void
1073 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1074 {
1075 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1076 (void *)bgep, addr, nbytes));
1077
1078 ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1079 ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1080
1081 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1082 addr &= MWBAR_GRANULE_MASK;
1083 addr += NIC_MEM_WINDOW_OFFSET;
1084
1085 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1086 nbytes, 1, DDI_DATA_SZ08_ACC);
1087 BGE_PCICHK(bgep);
1088 }
1089
1090 /*
1091 * MII (PHY) register get/set access routines
1092 *
1093 * These use the chip's MII auto-access method, controlled by the
1094 * MII Communication register at 0x044c, so the CPU doesn't have
1095 * to fiddle with the individual bits.
1096 */
1097
1098 #undef BGE_DBG
1099 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */
1100
1101 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1102 uint16_t data, uint32_t cmd);
1103 #pragma no_inline(bge_mii_access)
1104
1105 static uint16_t
1106 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1107 {
1108 uint32_t timeout;
1109 uint32_t regval1;
1110 uint32_t regval2;
1111
1112 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1113 (void *)bgep, regno, data, cmd));
1114
1115 ASSERT(mutex_owned(bgep->genlock));
1116
1117 /*
1118 * Assemble the command ...
1119 */
1120 cmd |= data << MI_COMMS_DATA_SHIFT;
1121 cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1122 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1123 cmd |= MI_COMMS_START;
1124
1125 /*
1126 * Wait for any command already in progress ...
1127 *
1128 * Note: this *shouldn't* ever find that there is a command
1129 * in progress, because we already hold the <genlock> mutex.
1130 * Nonetheless, we have sometimes seen the MI_COMMS_START
1131 * bit set here -- it seems that the chip can initiate MII
1132 * accesses internally, even with polling OFF.
1133 */
1134 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1135 for (timeout = 100; ; ) {
1136 if ((regval2 & MI_COMMS_START) == 0) {
1137 bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1138 break;
1139 }
1140 if (--timeout == 0)
1141 break;
1142 drv_usecwait(10);
1143 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1144 }
1145
1146 if (timeout == 0)
1147 return ((uint16_t)~0u);
1148
1149 if (timeout != 100)
1150 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1151 "MI_COMMS_START set for %d us; 0x%x->0x%x",
1152 cmd, 10*(100-timeout), regval1, regval2));
1153
1154 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1155 for (timeout = 1000; ; ) {
1156 if ((regval1 & MI_COMMS_START) == 0)
1157 break;
1158 if (--timeout == 0)
1159 break;
1160 drv_usecwait(10);
1161 regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1162 }
1163
1164 /*
1165 * Drop out early if the READ FAILED bit is set -- this chip
1166 * could be a 5703/4S, with a SerDes instead of a PHY!
1167 */
1168 if (regval2 & MI_COMMS_READ_FAILED)
1169 return ((uint16_t)~0u);
1170
1171 if (timeout == 0)
1172 return ((uint16_t)~0u);
1173
1174 /*
1175 * The PRM says to wait 5us after seeing the START bit clear
1176 * and then re-read the register to get the final value of the
1177 * data field, in order to avoid a race condition where the
1178 * START bit is clear but the data field isn't yet valid.
1179 *
1180 * Note: we don't actually seem to be encounter this race;
1181 * except when the START bit is seen set again (see below),
1182 * the data field doesn't change during this 5us interval.
1183 */
1184 drv_usecwait(5);
1185 regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1186
1187 /*
1188 * Unfortunately, when following the PRMs instructions above,
1189 * we have occasionally seen the START bit set again(!) in the
1190 * value read after the 5us delay. This seems to be due to the
1191 * chip autonomously starting another MII access internally.
1192 * In such cases, the command/data/etc fields relate to the
1193 * internal command, rather than the one that we thought had
1194 * just finished. So in this case, we fall back to returning
1195 * the data from the original read that showed START clear.
1196 */
1197 if (regval2 & MI_COMMS_START) {
1198 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1199 "MI_COMMS_START set after transaction; 0x%x->0x%x",
1200 cmd, regval1, regval2));
1201 regval2 = regval1;
1202 }
1203
1204 if (regval2 & MI_COMMS_START)
1205 return ((uint16_t)~0u);
1206
1207 if (regval2 & MI_COMMS_READ_FAILED)
1208 return ((uint16_t)~0u);
1209
1210 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1211 }
1212
1213 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1214 #pragma no_inline(bge_mii_get16)
1215
1216 uint16_t
1217 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1218 {
1219 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1220 (void *)bgep, regno));
1221
1222 ASSERT(mutex_owned(bgep->genlock));
1223
1224 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1225 (regno == MII_MSCONTROL)))
1226 return (0);
1227
1228 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1229 }
1230
1231 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1232 #pragma no_inline(bge_mii_put16)
1233
1234 void
1235 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1236 {
1237 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1238 (void *)bgep, regno, data));
1239
1240 ASSERT(mutex_owned(bgep->genlock));
1241
1242 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1243 (regno == MII_MSCONTROL)))
1244 return;
1245
1246 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1247 }
1248
1249 #undef BGE_DBG
1250 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */
1251
1252 #if BGE_SEE_IO32 || BGE_FLASH_IO32
1253
1254 /*
1255 * Basic SEEPROM get/set access routine
1256 *
1257 * This uses the chip's SEEPROM auto-access method, controlled by the
1258 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1259 * doesn't have to fiddle with the individual bits.
1260 *
1261 * The caller should hold <genlock> and *also* have already acquired
1262 * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1263 *
1264 * Return value:
1265 * 0 on success,
1266 * ENODATA on access timeout (maybe retryable: device may just be busy)
1267 * EPROTO on other h/w or s/w errors.
1268 *
1269 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1270 * from a (successful) SEEPROM_ACCESS_READ.
1271 */
1272 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1273 uint32_t *dp);
1274 #pragma no_inline(bge_seeprom_access)
1275
1276 static int
1277 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1278 {
1279 uint32_t tries;
1280 uint32_t regval;
1281
1282 ASSERT(mutex_owned(bgep->genlock));
1283
1284 /*
1285 * On the newer chips that support both SEEPROM & Flash, we need
1286 * to specifically enable SEEPROM access (Flash is the default).
1287 * On older chips, we don't; SEEPROM is the only NVtype supported,
1288 * and the NVM control registers don't exist ...
1289 */
1290 switch (bgep->chipid.nvtype) {
1291 case BGE_NVTYPE_NONE:
1292 case BGE_NVTYPE_UNKNOWN:
1293 _NOTE(NOTREACHED)
1294 case BGE_NVTYPE_SEEPROM:
1295 break;
1296
1297 case BGE_NVTYPE_LEGACY_SEEPROM:
1298 case BGE_NVTYPE_UNBUFFERED_FLASH:
1299 case BGE_NVTYPE_BUFFERED_FLASH:
1300 default:
1301 bge_reg_set32(bgep, NVM_CONFIG1_REG,
1302 NVM_CFG1_LEGACY_SEEPROM_MODE);
1303 break;
1304 }
1305
1306 /*
1307 * Check there's no command in progress.
1308 *
1309 * Note: this *shouldn't* ever find that there is a command
1310 * in progress, because we already hold the <genlock> mutex.
1311 * Also, to ensure we don't have a conflict with the chip's
1312 * internal firmware or a process accessing the same (shared)
1313 * SEEPROM through the other port of a 5704, we've already
1314 * been through the "software arbitration" protocol.
1315 * So this is just a final consistency check: we shouldn't
1316 * see EITHER the START bit (command started but not complete)
1317 * OR the COMPLETE bit (command completed but not cleared).
1318 */
1319 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1320 if (regval & SEEPROM_ACCESS_START)
1321 return (EPROTO);
1322 if (regval & SEEPROM_ACCESS_COMPLETE)
1323 return (EPROTO);
1324
1325 /*
1326 * Assemble the command ...
1327 */
1328 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1329 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1330 addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1331 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1332 cmd |= SEEPROM_ACCESS_START;
1333 cmd |= SEEPROM_ACCESS_COMPLETE;
1334 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1335
1336 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1337 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1338
1339 /*
1340 * By observation, a successful access takes ~20us on a 5703/4,
1341 * but apparently much longer (up to 1000us) on the obsolescent
1342 * BCM5700/BCM5701. We want to be sure we don't get any false
1343 * timeouts here; but OTOH, we don't want a bogus access to lock
1344 * out interrupts for longer than necessary. So we'll allow up
1345 * to 1000us ...
1346 */
1347 for (tries = 0; tries < 1000; ++tries) {
1348 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1349 if (regval & SEEPROM_ACCESS_COMPLETE)
1350 break;
1351 drv_usecwait(1);
1352 }
1353
1354 if (regval & SEEPROM_ACCESS_COMPLETE) {
1355 /*
1356 * All OK; read the SEEPROM data register, then write back
1357 * the value read from the address register in order to
1358 * clear the <complete> bit and leave the SEEPROM access
1359 * state machine idle, ready for the next access ...
1360 */
1361 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1362 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1363 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1364 return (0);
1365 }
1366
1367 /*
1368 * Hmm ... what happened here?
1369 *
1370 * Most likely, the user addressed a non-existent SEEPROM. Or
1371 * maybe the SEEPROM was busy internally (e.g. processing a write)
1372 * and didn't respond to being addressed. Either way, it's left
1373 * the SEEPROM access state machine wedged. So we'll reset it
1374 * before we leave, so it's ready for next time ...
1375 */
1376 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1377 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1378 return (ENODATA);
1379 }
1380
1381 /*
1382 * Basic Flash get/set access routine
1383 *
1384 * These use the chip's Flash auto-access method, controlled by the
1385 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1386 * fiddle with the individual bits.
1387 *
1388 * The caller should hold <genlock> and *also* have already acquired
1389 * the right to access the Flash, via bge_nvmem_acquire() above.
1390 *
1391 * Return value:
1392 * 0 on success,
1393 * ENODATA on access timeout (maybe retryable: device may just be busy)
1394 * ENODEV if the NVmem device is missing or otherwise unusable
1395 *
1396 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1397 * from a (successful) NVM_FLASH_CMD_RD.
1398 */
1399 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1400 uint32_t *dp);
1401 #pragma no_inline(bge_flash_access)
1402
1403 static int
1404 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1405 {
1406 uint32_t tries;
1407 uint32_t regval;
1408
1409 ASSERT(mutex_owned(bgep->genlock));
1410
1411 /*
1412 * On the newer chips that support both SEEPROM & Flash, we need
1413 * to specifically disable SEEPROM access while accessing Flash.
1414 * The older chips don't support Flash, and the NVM registers don't
1415 * exist, so we shouldn't be here at all!
1416 */
1417 switch (bgep->chipid.nvtype) {
1418 case BGE_NVTYPE_NONE:
1419 case BGE_NVTYPE_UNKNOWN:
1420 _NOTE(NOTREACHED)
1421 case BGE_NVTYPE_SEEPROM:
1422 return (ENODEV);
1423
1424 case BGE_NVTYPE_LEGACY_SEEPROM:
1425 case BGE_NVTYPE_UNBUFFERED_FLASH:
1426 case BGE_NVTYPE_BUFFERED_FLASH:
1427 default:
1428 bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1429 NVM_CFG1_LEGACY_SEEPROM_MODE);
1430 break;
1431 }
1432
1433 /*
1434 * Assemble the command ...
1435 */
1436 addr &= NVM_FLASH_ADDR_MASK;
1437 cmd |= NVM_FLASH_CMD_DOIT;
1438 cmd |= NVM_FLASH_CMD_FIRST;
1439 cmd |= NVM_FLASH_CMD_LAST;
1440 cmd |= NVM_FLASH_CMD_DONE;
1441
1442 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1443 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1444 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1445
1446 /*
1447 * Allow up to 1000ms ...
1448 */
1449 for (tries = 0; tries < 1000; ++tries) {
1450 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1451 if (regval & NVM_FLASH_CMD_DONE)
1452 break;
1453 drv_usecwait(1);
1454 }
1455
1456 if (regval & NVM_FLASH_CMD_DONE) {
1457 /*
1458 * All OK; read the data from the Flash read register
1459 */
1460 BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1461 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1462 return (0);
1463 }
1464
1465 /*
1466 * Hmm ... what happened here?
1467 *
1468 * Most likely, the user addressed a non-existent Flash. Or
1469 * maybe the Flash was busy internally (e.g. processing a write)
1470 * and didn't respond to being addressed. Either way, there's
1471 * nothing we can here ...
1472 */
1473 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1474 return (ENODATA);
1475 }
1476
1477 /*
1478 * The next two functions regulate access to the NVram (if fitted).
1479 *
1480 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1481 * (SPI) interface, but they can be accessed through either port. These
1482 * are managed by different instance of this driver and have no software
1483 * state in common.
1484 *
1485 * In addition (and even on a single core chip) the chip's internal
1486 * firmware can access the SEEPROM/Flash, most notably after a RESET
1487 * when it may download code to run internally.
1488 *
1489 * So we need to arbitrate between these various software agents. For
1490 * this purpose, the chip provides the Software Arbitration Register,
1491 * which implements hardware(!) arbitration.
1492 *
1493 * This functionality didn't exist on older (5700/5701) chips, so there's
1494 * nothing we can do by way of arbitration on those; also, if there's no
1495 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1496 * nothing to do.
1497 *
1498 * The internal firmware appears to use Request 0, which is the highest
1499 * priority. So we'd like to use Request 2, leaving one higher and one
1500 * lower for any future developments ... but apparently this doesn't
1501 * always work. So for now, the code uses Request 1 ;-(
1502 */
1503
1504 #define NVM_READ_REQ NVM_READ_REQ1
1505 #define NVM_RESET_REQ NVM_RESET_REQ1
1506 #define NVM_SET_REQ NVM_SET_REQ1
1507
1508 static void bge_nvmem_relinquish(bge_t *bgep);
1509 #pragma no_inline(bge_nvmem_relinquish)
1510
1511 static void
1512 bge_nvmem_relinquish(bge_t *bgep)
1513 {
1514 ASSERT(mutex_owned(bgep->genlock));
1515
1516 switch (bgep->chipid.nvtype) {
1517 case BGE_NVTYPE_NONE:
1518 case BGE_NVTYPE_UNKNOWN:
1519 _NOTE(NOTREACHED)
1520 return;
1521
1522 case BGE_NVTYPE_SEEPROM:
1523 /*
1524 * No arbitration performed, no release needed
1525 */
1526 return;
1527
1528 case BGE_NVTYPE_LEGACY_SEEPROM:
1529 case BGE_NVTYPE_UNBUFFERED_FLASH:
1530 case BGE_NVTYPE_BUFFERED_FLASH:
1531 default:
1532 break;
1533 }
1534
1535 /*
1536 * Our own request should be present (whether or not granted) ...
1537 */
1538 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1539
1540 /*
1541 * ... this will make it go away.
1542 */
1543 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1544 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1545 }
1546
1547 /*
1548 * Arbitrate for access to the NVmem, if necessary
1549 *
1550 * Return value:
1551 * 0 on success
1552 * EAGAIN if the device is in use (retryable)
1553 * ENODEV if the NVmem device is missing or otherwise unusable
1554 */
1555 static int bge_nvmem_acquire(bge_t *bgep);
1556 #pragma no_inline(bge_nvmem_acquire)
1557
1558 static int
1559 bge_nvmem_acquire(bge_t *bgep)
1560 {
1561 uint32_t regval;
1562 uint32_t tries;
1563
1564 ASSERT(mutex_owned(bgep->genlock));
1565
1566 switch (bgep->chipid.nvtype) {
1567 case BGE_NVTYPE_NONE:
1568 case BGE_NVTYPE_UNKNOWN:
1569 /*
1570 * Access denied: no (recognisable) device fitted
1571 */
1572 return (ENODEV);
1573
1574 case BGE_NVTYPE_SEEPROM:
1575 /*
1576 * Access granted: no arbitration needed (or possible)
1577 */
1578 return (0);
1579
1580 case BGE_NVTYPE_LEGACY_SEEPROM:
1581 case BGE_NVTYPE_UNBUFFERED_FLASH:
1582 case BGE_NVTYPE_BUFFERED_FLASH:
1583 default:
1584 /*
1585 * Access conditional: conduct arbitration protocol
1586 */
1587 break;
1588 }
1589
1590 /*
1591 * We're holding the per-port mutex <genlock>, so no-one other
1592 * thread can be attempting to access the NVmem through *this*
1593 * port. But it could be in use by the *other* port (of a 5704),
1594 * or by the chip's internal firmware, so we have to go through
1595 * the full (hardware) arbitration protocol ...
1596 *
1597 * Note that *because* we're holding <genlock>, the interrupt handler
1598 * won't be able to progress. So we're only willing to spin for a
1599 * fairly short time. Specifically:
1600 *
1601 * We *must* wait long enough for the hardware to resolve all
1602 * requests and determine the winner. Fortunately, this is
1603 * "almost instantaneous", even as observed by GHz CPUs.
1604 *
1605 * A successful access by another Solaris thread (via either
1606 * port) typically takes ~20us. So waiting a bit longer than
1607 * that will give a good chance of success, if the other user
1608 * *is* another thread on the other port.
1609 *
1610 * However, the internal firmware can hold on to the NVmem
1611 * for *much* longer: at least 10 milliseconds just after a
1612 * RESET, and maybe even longer if the NVmem actually contains
1613 * code to download and run on the internal CPUs.
1614 *
1615 * So, we'll allow 50us; if that's not enough then it's up to the
1616 * caller to retry later (hence the choice of return code EAGAIN).
1617 */
1618 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1619 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1620
1621 for (tries = 0; tries < 50; ++tries) {
1622 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1623 if (regval & NVM_WON_REQ1)
1624 break;
1625 drv_usecwait(1);
1626 }
1627
1628 if (regval & NVM_WON_REQ1) {
1629 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1630 return (0);
1631 }
1632
1633 /*
1634 * Somebody else must be accessing the NVmem, so abandon our
1635 * attempt take control of it. The caller can try again later ...
1636 */
1637 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1638 bge_nvmem_relinquish(bgep);
1639 return (EAGAIN);
1640 }
1641
1642 /*
1643 * This code assumes that the GPIO1 bit has been wired up to the NVmem
1644 * write protect line in such a way that the NVmem is protected when
1645 * GPIO1 is an input, or is an output but driven high. Thus, to make the
1646 * NVmem writable we have to change GPIO1 to an output AND drive it low.
1647 *
1648 * Note: there's only one set of GPIO pins on a 5704, even though they
1649 * can be accessed through either port. So the chip has to resolve what
1650 * happens if the two ports program a single pin differently ... the rule
1651 * it uses is that if the ports disagree about the *direction* of a pin,
1652 * "output" wins over "input", but if they disagree about its *value* as
1653 * an output, then the pin is TRISTATED instead! In such a case, no-one
1654 * wins, and the external signal does whatever the external circuitry
1655 * defines as the default -- which we've assumed is the PROTECTED state.
1656 * So, we always change GPIO1 back to being an *input* whenever we're not
1657 * specifically using it to unprotect the NVmem. This allows either port
1658 * to update the NVmem, although obviously only one at a time!
1659 *
1660 * The caller should hold <genlock> and *also* have already acquired the
1661 * right to access the NVmem, via bge_nvmem_acquire() above.
1662 */
1663 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1664 #pragma inline(bge_nvmem_protect)
1665
1666 static void
1667 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1668 {
1669 uint32_t regval;
1670
1671 ASSERT(mutex_owned(bgep->genlock));
1672
1673 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1674 if (protect) {
1675 regval |= MLCR_MISC_PINS_OUTPUT_1;
1676 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1677 } else {
1678 regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1679 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1680 }
1681 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1682 }
1683
1684 /*
1685 * Now put it all together ...
1686 *
1687 * Try to acquire control of the NVmem; if successful, then:
1688 * unprotect it (if we want to write to it)
1689 * perform the requested access
1690 * reprotect it (after a write)
1691 * relinquish control
1692 *
1693 * Return value:
1694 * 0 on success,
1695 * EAGAIN if the device is in use (retryable)
1696 * ENODATA on access timeout (maybe retryable: device may just be busy)
1697 * ENODEV if the NVmem device is missing or otherwise unusable
1698 * EPROTO on other h/w or s/w errors.
1699 */
1700 static int
1701 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1702 {
1703 int err;
1704
1705 if ((err = bge_nvmem_acquire(bgep)) == 0) {
1706 switch (cmd) {
1707 case BGE_SEE_READ:
1708 err = bge_seeprom_access(bgep,
1709 SEEPROM_ACCESS_READ, addr, dp);
1710 break;
1711
1712 case BGE_SEE_WRITE:
1713 bge_nvmem_protect(bgep, B_FALSE);
1714 err = bge_seeprom_access(bgep,
1715 SEEPROM_ACCESS_WRITE, addr, dp);
1716 bge_nvmem_protect(bgep, B_TRUE);
1717 break;
1718
1719 case BGE_FLASH_READ:
1720 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1721 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1722 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1723 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1724 bge_reg_set32(bgep, NVM_ACCESS_REG,
1725 NVM_ACCESS_ENABLE);
1726 }
1727 err = bge_flash_access(bgep,
1728 NVM_FLASH_CMD_RD, addr, dp);
1729 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1730 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1731 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1732 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1733 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1734 NVM_ACCESS_ENABLE);
1735 }
1736 break;
1737
1738 case BGE_FLASH_WRITE:
1739 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1740 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1741 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1742 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1743 bge_reg_set32(bgep, NVM_ACCESS_REG,
1744 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1745 }
1746 bge_nvmem_protect(bgep, B_FALSE);
1747 err = bge_flash_access(bgep,
1748 NVM_FLASH_CMD_WR, addr, dp);
1749 bge_nvmem_protect(bgep, B_TRUE);
1750 if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1751 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1752 DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1753 DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1754 bge_reg_clr32(bgep, NVM_ACCESS_REG,
1755 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1756 }
1757
1758 break;
1759
1760 default:
1761 _NOTE(NOTREACHED)
1762 break;
1763 }
1764 bge_nvmem_relinquish(bgep);
1765 }
1766
1767 BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1768 return (err);
1769 }
1770
1771 /*
1772 * Attempt to get a MAC address from the SEEPROM or Flash, if any
1773 */
1774 static uint64_t bge_get_nvmac(bge_t *bgep);
1775 #pragma no_inline(bge_get_nvmac)
1776
1777 static uint64_t
1778 bge_get_nvmac(bge_t *bgep)
1779 {
1780 uint32_t mac_high;
1781 uint32_t mac_low;
1782 uint32_t addr;
1783 uint32_t cmd;
1784 uint64_t mac;
1785
1786 BGE_TRACE(("bge_get_nvmac($%p)",
1787 (void *)bgep));
1788
1789 switch (bgep->chipid.nvtype) {
1790 case BGE_NVTYPE_NONE:
1791 case BGE_NVTYPE_UNKNOWN:
1792 default:
1793 return (0ULL);
1794
1795 case BGE_NVTYPE_SEEPROM:
1796 case BGE_NVTYPE_LEGACY_SEEPROM:
1797 cmd = BGE_SEE_READ;
1798 break;
1799
1800 case BGE_NVTYPE_UNBUFFERED_FLASH:
1801 case BGE_NVTYPE_BUFFERED_FLASH:
1802 cmd = BGE_FLASH_READ;
1803 break;
1804 }
1805
1806 if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1807 addr = NVMEM_DATA_MAC_ADDRESS_5906;
1808 else
1809 addr = NVMEM_DATA_MAC_ADDRESS;
1810
1811 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1812 return (0ULL);
1813 addr += 4;
1814 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1815 return (0ULL);
1816
1817 /*
1818 * The Broadcom chip is natively BIG-endian, so that's how the
1819 * MAC address is represented in NVmem. We may need to swap it
1820 * around on a little-endian host ...
1821 */
1822 #ifdef _BIG_ENDIAN
1823 mac = mac_high;
1824 mac = mac << 32;
1825 mac |= mac_low;
1826 #else
1827 mac = BGE_BSWAP_32(mac_high);
1828 mac = mac << 32;
1829 mac |= BGE_BSWAP_32(mac_low);
1830 #endif /* _BIG_ENDIAN */
1831
1832 return (mac);
1833 }
1834
1835 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1836
1837 /*
1838 * Dummy version for when we're not supporting NVmem access
1839 */
1840 static uint64_t bge_get_nvmac(bge_t *bgep);
1841 #pragma inline(bge_get_nvmac)
1842
1843 static uint64_t
1844 bge_get_nvmac(bge_t *bgep)
1845 {
1846 _NOTE(ARGUNUSED(bgep))
1847 return (0ULL);
1848 }
1849
1850 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1851
1852 /*
1853 * Determine the type of NVmem that is (or may be) attached to this chip,
1854 */
1855 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1856 #pragma no_inline(bge_nvmem_id)
1857
1858 static enum bge_nvmem_type
1859 bge_nvmem_id(bge_t *bgep)
1860 {
1861 enum bge_nvmem_type nvtype;
1862 uint32_t config1;
1863
1864 BGE_TRACE(("bge_nvmem_id($%p)",
1865 (void *)bgep));
1866
1867 switch (bgep->chipid.device) {
1868 default:
1869 /*
1870 * We shouldn't get here; it means we don't recognise
1871 * the chip, which means we don't know how to determine
1872 * what sort of NVmem (if any) it has. So we'll say
1873 * NONE, to disable the NVmem access code ...
1874 */
1875 nvtype = BGE_NVTYPE_NONE;
1876 break;
1877
1878 case DEVICE_ID_5700:
1879 case DEVICE_ID_5700x:
1880 case DEVICE_ID_5701:
1881 /*
1882 * These devices support *only* SEEPROMs
1883 */
1884 nvtype = BGE_NVTYPE_SEEPROM;
1885 break;
1886
1887 case DEVICE_ID_5702:
1888 case DEVICE_ID_5702fe:
1889 case DEVICE_ID_5703C:
1890 case DEVICE_ID_5703S:
1891 case DEVICE_ID_5704C:
1892 case DEVICE_ID_5704S:
1893 case DEVICE_ID_5704:
1894 case DEVICE_ID_5705M:
1895 case DEVICE_ID_5705C:
1896 case DEVICE_ID_5705_2:
1897 case DEVICE_ID_5717:
1898 case DEVICE_ID_5718:
1899 case DEVICE_ID_5724:
1900 case DEVICE_ID_57760:
1901 case DEVICE_ID_57780:
1902 case DEVICE_ID_57788:
1903 case DEVICE_ID_57790:
1904 case DEVICE_ID_5780:
1905 case DEVICE_ID_5782:
1906 case DEVICE_ID_5784M:
1907 case DEVICE_ID_5785:
1908 case DEVICE_ID_5787:
1909 case DEVICE_ID_5787M:
1910 case DEVICE_ID_5788:
1911 case DEVICE_ID_5789:
1912 case DEVICE_ID_5751:
1913 case DEVICE_ID_5751M:
1914 case DEVICE_ID_5752:
1915 case DEVICE_ID_5752M:
1916 case DEVICE_ID_5754:
1917 case DEVICE_ID_5755:
1918 case DEVICE_ID_5755M:
1919 case DEVICE_ID_5756M:
1920 case DEVICE_ID_5721:
1921 case DEVICE_ID_5722:
1922 case DEVICE_ID_5723:
1923 case DEVICE_ID_5761:
1924 case DEVICE_ID_5761E:
1925 case DEVICE_ID_5761S:
1926 case DEVICE_ID_5761SE:
1927 case DEVICE_ID_5764:
1928 case DEVICE_ID_5714C:
1929 case DEVICE_ID_5714S:
1930 case DEVICE_ID_5715C:
1931 case DEVICE_ID_5715S:
1932 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1933 if (config1 & NVM_CFG1_FLASH_MODE)
1934 if (config1 & NVM_CFG1_BUFFERED_MODE)
1935 nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1936 else
1937 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1938 else
1939 nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1940 break;
1941 case DEVICE_ID_5906:
1942 case DEVICE_ID_5906M:
1943 nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1944 break;
1945 }
1946
1947 return (nvtype);
1948 }
1949
1950 #undef BGE_DBG
1951 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */
1952
1953 static void
1954 bge_init_recv_rule(bge_t *bgep)
1955 {
1956 bge_recv_rule_t *rulep = bgep->recv_rules;
1957 uint32_t i;
1958
1959 /*
1960 * Initialize receive rule registers.
1961 * Note that rules may persist across each bge_m_start/stop() call.
1962 */
1963 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1964 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1965 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1966 }
1967 }
1968
1969 /*
1970 * Using the values captured by bge_chip_cfg_init(), and additional probes
1971 * as required, characterise the chip fully: determine the label by which
1972 * to refer to this chip, the correct settings for various registers, and
1973 * of course whether the device and/or subsystem are supported!
1974 */
1975 int bge_chip_id_init(bge_t *bgep);
1976 #pragma no_inline(bge_chip_id_init)
1977
1978 int
1979 bge_chip_id_init(bge_t *bgep)
1980 {
1981 char buf[MAXPATHLEN]; /* any risk of stack overflow? */
1982 boolean_t sys_ok;
1983 boolean_t dev_ok;
1984 chip_id_t *cidp;
1985 uint32_t subid;
1986 char *devname;
1987 char *sysname;
1988 int *ids;
1989 int err;
1990 uint_t i;
1991
1992 sys_ok = dev_ok = B_FALSE;
1993 cidp = &bgep->chipid;
1994
1995 /*
1996 * Check the PCI device ID to determine the generic chip type and
1997 * select parameters that depend on this.
1998 *
1999 * Note: because the SPARC platforms in general don't fit the
2000 * SEEPROM 'behind' the chip, the PCI revision ID register reads
2001 * as zero - which is why we use <asic_rev> rather than <revision>
2002 * below ...
2003 *
2004 * Note: in general we can't distinguish between the Copper/SerDes
2005 * versions by ID alone, as some Copper devices (e.g. some but not
2006 * all 5703Cs) have the same ID as the SerDes equivalents. So we
2007 * treat them the same here, and the MII code works out the media
2008 * type later on ...
2009 */
2010 cidp->mbuf_base = bge_mbuf_pool_base;
2011 cidp->mbuf_length = bge_mbuf_pool_len;
2012 cidp->recv_slots = BGE_RECV_SLOTS_USED;
2013 cidp->bge_dma_rwctrl = bge_dma_rwctrl;
2014 cidp->pci_type = BGE_PCI_X;
2015 cidp->statistic_type = BGE_STAT_BLK;
2016 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
2017 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
2018 cidp->mbuf_hi_water = bge_mbuf_hi_water;
2019 cidp->rx_ticks_norm = bge_rx_ticks_norm;
2020 cidp->rx_count_norm = bge_rx_count_norm;
2021 cidp->tx_ticks_norm = bge_tx_ticks_norm;
2022 cidp->tx_count_norm = bge_tx_count_norm;
2023 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT;
2024
2025 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
2026 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
2027 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
2028 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
2029
2030 cidp->msi_enabled = B_FALSE;
2031
2032 switch (cidp->device) {
2033 case DEVICE_ID_5717:
2034 case DEVICE_ID_5718:
2035 case DEVICE_ID_5724:
2036 if (cidp->device == DEVICE_ID_5717)
2037 cidp->chip_label = 5717;
2038 else if (cidp->device == DEVICE_ID_5718)
2039 cidp->chip_label = 5718;
2040 else
2041 cidp->chip_label = 5724;
2042 cidp->msi_enabled = bge_enable_msi;
2043 #ifdef __sparc
2044 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
2045 #endif
2046 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717);
2047 cidp->pci_type = BGE_PCI_E;
2048 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2049 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717;
2050 cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2051 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2052 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2053 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2054 cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2055 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2056 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2057 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2058 cidp->statistic_type = BGE_STAT_REG;
2059 dev_ok = B_TRUE;
2060 break;
2061
2062 case DEVICE_ID_5700:
2063 case DEVICE_ID_5700x:
2064 cidp->chip_label = 5700;
2065 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2066 break;
2067
2068 case DEVICE_ID_5701:
2069 cidp->chip_label = 5701;
2070 dev_ok = B_TRUE;
2071 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2072 break;
2073
2074 case DEVICE_ID_5702:
2075 case DEVICE_ID_5702fe:
2076 cidp->chip_label = 5702;
2077 dev_ok = B_TRUE;
2078 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2079 cidp->pci_type = BGE_PCI;
2080 break;
2081
2082 case DEVICE_ID_5703C:
2083 case DEVICE_ID_5703S:
2084 case DEVICE_ID_5703:
2085 /*
2086 * Revision A0 of the 5703/5793 had various errata
2087 * that we can't or don't work around, so it's not
2088 * supported, but all later versions are
2089 */
2090 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2091 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2092 dev_ok = B_TRUE;
2093 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2094 break;
2095
2096 case DEVICE_ID_5704C:
2097 case DEVICE_ID_5704S:
2098 case DEVICE_ID_5704:
2099 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2100 cidp->mbuf_base = bge_mbuf_pool_base_5704;
2101 cidp->mbuf_length = bge_mbuf_pool_len_5704;
2102 dev_ok = B_TRUE;
2103 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2104 break;
2105
2106 case DEVICE_ID_5705C:
2107 case DEVICE_ID_5705M:
2108 case DEVICE_ID_5705MA3:
2109 case DEVICE_ID_5705F:
2110 case DEVICE_ID_5705_2:
2111 case DEVICE_ID_5754:
2112 if (cidp->device == DEVICE_ID_5754) {
2113 cidp->chip_label = 5754;
2114 cidp->pci_type = BGE_PCI_E;
2115 } else {
2116 cidp->chip_label = 5705;
2117 cidp->pci_type = BGE_PCI;
2118 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2119 }
2120 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2121 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2122 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2123 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2124 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2125 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2126 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2127 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2128 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2129 cidp->statistic_type = BGE_STAT_REG;
2130 dev_ok = B_TRUE;
2131 break;
2132
2133 case DEVICE_ID_5906:
2134 case DEVICE_ID_5906M:
2135 cidp->chip_label = 5906;
2136 cidp->pci_type = BGE_PCI_E;
2137 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2138 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2139 cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2140 cidp->mbuf_base = bge_mbuf_pool_base;
2141 cidp->mbuf_length = bge_mbuf_pool_len;
2142 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2143 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2144 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2145 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2146 cidp->statistic_type = BGE_STAT_REG;
2147 dev_ok = B_TRUE;
2148 break;
2149
2150 case DEVICE_ID_5753:
2151 cidp->chip_label = 5753;
2152 cidp->pci_type = BGE_PCI_E;
2153 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2154 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2155 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2156 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2157 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2158 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2159 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2160 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2161 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2162 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2163 cidp->statistic_type = BGE_STAT_REG;
2164 dev_ok = B_TRUE;
2165 break;
2166
2167 case DEVICE_ID_5755:
2168 case DEVICE_ID_5755M:
2169 cidp->chip_label = 5755;
2170 cidp->pci_type = BGE_PCI_E;
2171 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2172 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2173 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2174 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2175 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2176 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2177 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2178 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2179 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2180 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2181 if (cidp->device == DEVICE_ID_5755M)
2182 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2183 cidp->statistic_type = BGE_STAT_REG;
2184 dev_ok = B_TRUE;
2185 break;
2186
2187 case DEVICE_ID_5756M:
2188 /*
2189 * This is nearly identical to the 5755M.
2190 * (Actually reports the 5755 chip ID.)
2191 */
2192 cidp->chip_label = 5756;
2193 cidp->pci_type = BGE_PCI_E;
2194 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2195 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2196 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2197 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2198 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2199 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2200 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2201 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2202 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2203 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2204 cidp->statistic_type = BGE_STAT_REG;
2205 dev_ok = B_TRUE;
2206 break;
2207
2208 case DEVICE_ID_5787:
2209 case DEVICE_ID_5787M:
2210 cidp->chip_label = 5787;
2211 cidp->pci_type = BGE_PCI_E;
2212 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2213 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2214 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2215 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2216 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2217 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2218 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2219 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2220 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2221 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2222 cidp->statistic_type = BGE_STAT_REG;
2223 dev_ok = B_TRUE;
2224 break;
2225
2226 case DEVICE_ID_5723:
2227 case DEVICE_ID_5761:
2228 case DEVICE_ID_5761E:
2229 case DEVICE_ID_5761S:
2230 case DEVICE_ID_5761SE:
2231 case DEVICE_ID_5784M:
2232 case DEVICE_ID_57760:
2233 case DEVICE_ID_57780:
2234 case DEVICE_ID_57788:
2235 case DEVICE_ID_57790:
2236 cidp->msi_enabled = bge_enable_msi;
2237 /*
2238 * We don't use MSI for BCM5764 and BCM5785, as the
2239 * status block may fail to update when the network
2240 * traffic is heavy.
2241 */
2242 /* FALLTHRU */
2243 case DEVICE_ID_5785:
2244 case DEVICE_ID_5764:
2245 if (cidp->device == DEVICE_ID_5723)
2246 cidp->chip_label = 5723;
2247 else if (cidp->device == DEVICE_ID_5764)
2248 cidp->chip_label = 5764;
2249 else if (cidp->device == DEVICE_ID_5784M)
2250 cidp->chip_label = 5784;
2251 else if (cidp->device == DEVICE_ID_5785)
2252 cidp->chip_label = 5785;
2253 else if (cidp->device == DEVICE_ID_57760)
2254 cidp->chip_label = 57760;
2255 else if (cidp->device == DEVICE_ID_57780)
2256 cidp->chip_label = 57780;
2257 else if (cidp->device == DEVICE_ID_57788)
2258 cidp->chip_label = 57788;
2259 else if (cidp->device == DEVICE_ID_57790)
2260 cidp->chip_label = 57790;
2261 else
2262 cidp->chip_label = 5761;
2263 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2264 cidp->pci_type = BGE_PCI_E;
2265 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2266 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2267 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2268 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2269 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2270 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2271 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2272 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2273 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2274 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2275 cidp->statistic_type = BGE_STAT_REG;
2276 dev_ok = B_TRUE;
2277 break;
2278
2279 /* PCI-X device, identical to 5714 */
2280 case DEVICE_ID_5780:
2281 cidp->chip_label = 5780;
2282 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2283 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2284 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2285 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2286 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2287 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2288 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2289 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2290 cidp->statistic_type = BGE_STAT_REG;
2291 dev_ok = B_TRUE;
2292 break;
2293
2294 case DEVICE_ID_5782:
2295 /*
2296 * Apart from the label, we treat this as a 5705(?)
2297 */
2298 cidp->chip_label = 5782;
2299 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2300 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2301 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2302 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2303 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2304 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2305 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2306 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2307 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2308 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2309 cidp->statistic_type = BGE_STAT_REG;
2310 dev_ok = B_TRUE;
2311 break;
2312
2313 case DEVICE_ID_5788:
2314 /*
2315 * Apart from the label, we treat this as a 5705(?)
2316 */
2317 cidp->chip_label = 5788;
2318 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2319 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2320 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2321 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2322 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2323 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2324 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2325 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2326 cidp->statistic_type = BGE_STAT_REG;
2327 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2328 dev_ok = B_TRUE;
2329 break;
2330
2331 case DEVICE_ID_5714C:
2332 if (cidp->revision >= REVISION_ID_5714_A2)
2333 cidp->msi_enabled = bge_enable_msi;
2334 /* FALLTHRU */
2335 case DEVICE_ID_5714S:
2336 cidp->chip_label = 5714;
2337 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2338 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2339 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2340 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2341 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2342 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2343 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2344 cidp->bge_mlcr_default = bge_mlcr_default_5714;
2345 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2346 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2347 cidp->pci_type = BGE_PCI_E;
2348 cidp->statistic_type = BGE_STAT_REG;
2349 dev_ok = B_TRUE;
2350 break;
2351
2352 case DEVICE_ID_5715C:
2353 case DEVICE_ID_5715S:
2354 cidp->chip_label = 5715;
2355 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2356 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2357 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2358 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2359 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2360 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2361 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2362 cidp->bge_mlcr_default = bge_mlcr_default_5714;
2363 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2364 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2365 cidp->pci_type = BGE_PCI_E;
2366 cidp->statistic_type = BGE_STAT_REG;
2367 if (cidp->revision >= REVISION_ID_5715_A2)
2368 cidp->msi_enabled = bge_enable_msi;
2369 dev_ok = B_TRUE;
2370 break;
2371
2372 case DEVICE_ID_5721:
2373 cidp->chip_label = 5721;
2374 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2375 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2376 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2377 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2378 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2379 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2380 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2381 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2382 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2383 cidp->pci_type = BGE_PCI_E;
2384 cidp->statistic_type = BGE_STAT_REG;
2385 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2386 dev_ok = B_TRUE;
2387 break;
2388
2389 case DEVICE_ID_5722:
2390 cidp->chip_label = 5722;
2391 cidp->pci_type = BGE_PCI_E;
2392 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2393 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2394 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2395 cidp->mbuf_base = bge_mbuf_pool_base_5705;
2396 cidp->mbuf_length = bge_mbuf_pool_len_5705;
2397 cidp->recv_slots = BGE_RECV_SLOTS_5705;
2398 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2399 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2400 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2401 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2402 cidp->statistic_type = BGE_STAT_REG;
2403 dev_ok = B_TRUE;
2404 break;
2405
2406 case DEVICE_ID_5751:
2407 case DEVICE_ID_5751M:
2408 cidp->chip_label = 5751;
2409 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2410 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2411 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2412 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2413 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2414 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2415 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2416 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2417 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2418 cidp->pci_type = BGE_PCI_E;
2419 cidp->statistic_type = BGE_STAT_REG;
2420 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2421 dev_ok = B_TRUE;
2422 break;
2423
2424 case DEVICE_ID_5752:
2425 case DEVICE_ID_5752M:
2426 cidp->chip_label = 5752;
2427 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2428 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2429 cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2430 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2431 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2432 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2433 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2434 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2435 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2436 cidp->pci_type = BGE_PCI_E;
2437 cidp->statistic_type = BGE_STAT_REG;
2438 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2439 dev_ok = B_TRUE;
2440 break;
2441
2442 case DEVICE_ID_5789:
2443 cidp->chip_label = 5789;
2444 cidp->mbuf_base = bge_mbuf_pool_base_5721;
2445 cidp->mbuf_length = bge_mbuf_pool_len_5721;
2446 cidp->recv_slots = BGE_RECV_SLOTS_5721;
2447 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2448 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2449 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2450 cidp->pci_type = BGE_PCI_E;
2451 cidp->statistic_type = BGE_STAT_REG;
2452 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2453 cidp->flags |= CHIP_FLAG_NO_JUMBO;
2454 cidp->msi_enabled = B_TRUE;
2455 dev_ok = B_TRUE;
2456 break;
2457
2458 }
2459
2460 /*
2461 * Setup the default jumbo parameter.
2462 */
2463 cidp->ethmax_size = ETHERMAX;
2464 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2465 cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2466
2467 /*
2468 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2469 * setup below jumbo specific parameters.
2470 *
2471 * For BCM5714/5715, there is only one standard receive ring. So the
2472 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2473 * feature is enabled.
2474 */
2475 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2476 (cidp->default_mtu > BGE_DEFAULT_MTU)) {
2477 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2478 cidp->mbuf_lo_water_rdma =
2479 RDMA_MBUF_LOWAT_5714_JUMBO;
2480 cidp->mbuf_lo_water_rmac =
2481 MAC_RX_MBUF_LOWAT_5714_JUMBO;
2482 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2483 cidp->jumbo_slots = 0;
2484 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2485 } else {
2486 cidp->mbuf_lo_water_rdma =
2487 RDMA_MBUF_LOWAT_JUMBO;
2488 cidp->mbuf_lo_water_rmac =
2489 MAC_RX_MBUF_LOWAT_JUMBO;
2490 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2491 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2492 }
2493 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2494 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2495 cidp->ethmax_size = cidp->default_mtu +
2496 sizeof (struct ether_header);
2497 }
2498
2499 /*
2500 * Identify the NV memory type: SEEPROM or Flash?
2501 */
2502 cidp->nvtype = bge_nvmem_id(bgep);
2503
2504 /*
2505 * Now, we want to check whether this device is part of a
2506 * supported subsystem (e.g., on the motherboard of a Sun
2507 * branded platform).
2508 *
2509 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2510 */
2511 if (cidp->subven == VENDOR_ID_SUN)
2512 sys_ok = B_TRUE;
2513
2514 /*
2515 * Rule 2: If it's on the list on known subsystems, then it's OK.
2516 * Note: 0x14e41647 should *not* appear in the list, but the code
2517 * doesn't enforce that.
2518 */
2519 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2520 DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2521 if (err == DDI_PROP_SUCCESS) {
2522 /*
2523 * Got the list; scan for a matching subsystem vendor/device
2524 */
2525 subid = (cidp->subven << 16) | cidp->subdev;
2526 while (i--)
2527 if (ids[i] == subid)
2528 sys_ok = B_TRUE;
2529 ddi_prop_free(ids);
2530 }
2531
2532 /*
2533 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2534 *
2535 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2536 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore,
2537 * we have to check specially for the exact device paths to the
2538 * motherboard devices on those platforms ;-(
2539 *
2540 * Note: we can't just use the "supported-subsystems" mechanism
2541 * above, because the entry would have to be 0x14e41647 -- which
2542 * would then accept *any* plugin card that *didn't* contain a
2543 * (valid) SEEPROM ;-(
2544 */
2545 sysname = ddi_node_name(ddi_root_node());
2546 devname = ddi_pathname(bgep->devinfo, buf);
2547 ASSERT(strlen(devname) > 0);
2548 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */
2549 if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2550 sys_ok = B_TRUE;
2551 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */
2552 if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2553 sys_ok = B_TRUE;
2554
2555 /*
2556 * Now check what we've discovered: is this truly a supported
2557 * chip on (the motherboard of) a supported platform?
2558 *
2559 * Possible problems here:
2560 * 1) it's a completely unheard-of chip
2561 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2562 * 3) it's a chip we would support if it were on the motherboard
2563 * of a Sun platform, but this one isn't ;-(
2564 */
2565 if (cidp->chip_label == 0)
2566 bge_problem(bgep,
2567 "Device 'pci%04x,%04x' not recognized (%d?)",
2568 cidp->vendor, cidp->device, cidp->device);
2569 else if (!dev_ok)
2570 bge_problem(bgep,
2571 "Device 'pci%04x,%04x' (%d) revision %d not supported",
2572 cidp->vendor, cidp->device, cidp->chip_label,
2573 cidp->revision);
2574 #if BGE_DEBUGGING
2575 else if (!sys_ok)
2576 bge_problem(bgep,
2577 "%d-based subsystem 'pci%04x,%04x' not validated",
2578 cidp->chip_label, cidp->subven, cidp->subdev);
2579 #endif
2580 else
2581 cidp->flags |= CHIP_FLAG_SUPPORTED;
2582 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2583 return (EIO);
2584 return (0);
2585 }
2586
2587 void
2588 bge_chip_msi_trig(bge_t *bgep)
2589 {
2590 uint32_t regval;
2591
2592 regval = bgep->param_msi_cnt<<4;
2593 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2594 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2595 }
2596
2597 /*
2598 * Various registers that control the chip's internal engines (state
2599 * machines) have a <reset> and <enable> bits (fortunately, in the
2600 * same place in each such register :-).
2601 *
2602 * To reset the state machine, the <reset> bit must be written with 1;
2603 * it will then read back as 1 while the reset is in progress, but
2604 * self-clear to 0 when the reset completes.
2605 *
2606 * To enable a state machine, one must set the <enable> bit, which
2607 * will continue to read back as 0 until the state machine is running.
2608 *
2609 * To disable a state machine, the <enable> bit must be cleared, but
2610 * it will continue to read back as 1 until the state machine actually
2611 * stops.
2612 *
2613 * This routine implements polling for completion of a reset, enable
2614 * or disable operation, returning B_TRUE on success (bit reached the
2615 * required state) or B_FALSE on timeout (200*100us == 20ms).
2616 */
2617 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2618 uint32_t mask, uint32_t val);
2619 #pragma no_inline(bge_chip_poll_engine)
2620
2621 static boolean_t
2622 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2623 uint32_t mask, uint32_t val)
2624 {
2625 uint32_t regval;
2626 uint32_t n;
2627
2628 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2629 (void *)bgep, regno, mask, val));
2630
2631 for (n = 200; n; --n) {
2632 regval = bge_reg_get32(bgep, regno);
2633 if ((regval & mask) == val)
2634 return (B_TRUE);
2635 drv_usecwait(100);
2636 }
2637
2638 bge_problem(bgep, "bge_chip_poll_engine failed: regno = 0x%lx", regno);
2639 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2640 return (B_FALSE);
2641 }
2642
2643 /*
2644 * Various registers that control the chip's internal engines (state
2645 * machines) have a <reset> bit (fortunately, in the same place in
2646 * each such register :-). To reset the state machine, this bit must
2647 * be written with 1; it will then read back as 1 while the reset is
2648 * in progress, but self-clear to 0 when the reset completes.
2649 *
2650 * This code sets the bit, then polls for it to read back as zero.
2651 * The return value is B_TRUE on success (reset bit cleared itself),
2652 * or B_FALSE if the state machine didn't recover :(
2653 *
2654 * NOTE: the Core reset is similar to other resets, except that we
2655 * can't poll for completion, since the Core reset disables memory
2656 * access! So we just have to assume that it will all complete in
2657 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5.
2658 */
2659 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2660 #pragma no_inline(bge_chip_reset_engine)
2661
2662 static boolean_t
2663 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2664 {
2665 uint32_t regval;
2666 uint32_t val32;
2667
2668 regval = bge_reg_get32(bgep, regno);
2669
2670 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2671 (void *)bgep, regno));
2672 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2673 regno, regval));
2674
2675 regval |= STATE_MACHINE_RESET_BIT;
2676
2677 switch (regno) {
2678 case MISC_CONFIG_REG:
2679 /*
2680 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2681 * resetting PCIE block and bringing PCIE link down, bit 29
2682 * in the register needs to be set first, and then set it again
2683 * while the reset bit is written.
2684 * See:P500 of 57xx-PG102-RDS.pdf.
2685 */
2686 if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2687 DEVICE_5717_SERIES_CHIPSETS(bgep)||
2688 DEVICE_5721_SERIES_CHIPSETS(bgep)||
2689 DEVICE_5723_SERIES_CHIPSETS(bgep)||
2690 DEVICE_5714_SERIES_CHIPSETS(bgep)||
2691 DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2692 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2693 if (bgep->chipid.pci_type == BGE_PCI_E) {
2694 if (bgep->chipid.asic_rev ==
2695 MHCR_CHIP_REV_5751_A0 ||
2696 bgep->chipid.asic_rev ==
2697 MHCR_CHIP_REV_5721_A0 ||
2698 bgep->chipid.asic_rev ==
2699 MHCR_CHIP_REV_5755_A0) {
2700 val32 = bge_reg_get32(bgep,
2701 PHY_TEST_CTRL_REG);
2702 if (val32 == (PHY_PCIE_SCRAM_MODE |
2703 PHY_PCIE_LTASS_MODE))
2704 bge_reg_put32(bgep,
2705 PHY_TEST_CTRL_REG,
2706 PHY_PCIE_SCRAM_MODE);
2707 val32 = pci_config_get32
2708 (bgep->cfg_handle,
2709 PCI_CONF_BGE_CLKCTL);
2710 val32 |= CLKCTL_PCIE_A0_FIX;
2711 pci_config_put32(bgep->cfg_handle,
2712 PCI_CONF_BGE_CLKCTL, val32);
2713 }
2714 bge_reg_set32(bgep, regno,
2715 MISC_CONFIG_GRC_RESET_DISABLE);
2716 regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2717 }
2718 }
2719
2720 /*
2721 * Special case - causes Core reset
2722 *
2723 * On SPARC v9 we want to ensure that we don't start
2724 * timing until the I/O access has actually reached
2725 * the chip, otherwise we might make the next access
2726 * too early. And we can't just force the write out
2727 * by following it with a read (even to config space)
2728 * because that would cause the fault we're trying
2729 * to avoid. Hence the need for membar_sync() here.
2730 */
2731 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2732 #ifdef __sparcv9
2733 membar_sync();
2734 #endif /* __sparcv9 */
2735 /*
2736 * On some platforms,system need about 300us for
2737 * link setup.
2738 */
2739 drv_usecwait(300);
2740 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2741 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
2742 bge_reg_clr32(
2743 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
2744 }
2745
2746 if (bgep->chipid.pci_type == BGE_PCI_E) {
2747 /* PCI-E device need more reset time */
2748 drv_usecwait(120000);
2749
2750 /* Set PCIE max payload size and clear error status. */
2751 if ((bgep->chipid.chip_label == 5721) ||
2752 (bgep->chipid.chip_label == 5751) ||
2753 (bgep->chipid.chip_label == 5752) ||
2754 (bgep->chipid.chip_label == 5789) ||
2755 (bgep->chipid.chip_label == 5906)) {
2756 pci_config_put16(bgep->cfg_handle,
2757 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2758 pci_config_put16(bgep->cfg_handle,
2759 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2760 }
2761
2762 if ((bgep->chipid.chip_label == 5723) ||
2763 (bgep->chipid.chip_label == 5761)) {
2764 pci_config_put16(bgep->cfg_handle,
2765 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
2766 pci_config_put16(bgep->cfg_handle,
2767 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
2768 }
2769 }
2770
2771 BGE_PCICHK(bgep);
2772 return (B_TRUE);
2773
2774 default:
2775 bge_reg_put32(bgep, regno, regval);
2776 return (bge_chip_poll_engine(bgep, regno,
2777 STATE_MACHINE_RESET_BIT, 0));
2778 }
2779 }
2780
2781 /*
2782 * Various registers that control the chip's internal engines (state
2783 * machines) have an <enable> bit (fortunately, in the same place in
2784 * each such register :-). To stop the state machine, this bit must
2785 * be written with 0, then polled to see when the state machine has
2786 * actually stopped.
2787 *
2788 * The return value is B_TRUE on success (enable bit cleared), or
2789 * B_FALSE if the state machine didn't stop :(
2790 */
2791 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2792 uint32_t morebits);
2793 #pragma no_inline(bge_chip_disable_engine)
2794
2795 static boolean_t
2796 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2797 {
2798 uint32_t regval;
2799
2800 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2801 (void *)bgep, regno, morebits));
2802
2803 switch (regno) {
2804 case FTQ_RESET_REG:
2805 /*
2806 * For Schumacher's bugfix CR6490108
2807 */
2808 #ifdef BGE_IPMI_ASF
2809 #ifdef BGE_NETCONSOLE
2810 if (bgep->asf_enabled)
2811 return (B_TRUE);
2812 #endif
2813 #endif
2814 /*
2815 * Not quite like the others; it doesn't
2816 * have an <enable> bit, but instead we
2817 * have to set and then clear all the bits
2818 */
2819 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2820 drv_usecwait(100);
2821 bge_reg_put32(bgep, regno, 0);
2822 return (B_TRUE);
2823
2824 default:
2825 regval = bge_reg_get32(bgep, regno);
2826 regval &= ~STATE_MACHINE_ENABLE_BIT;
2827 regval &= ~morebits;
2828 bge_reg_put32(bgep, regno, regval);
2829 return (bge_chip_poll_engine(bgep, regno,
2830 STATE_MACHINE_ENABLE_BIT, 0));
2831 }
2832 }
2833
2834 /*
2835 * Various registers that control the chip's internal engines (state
2836 * machines) have an <enable> bit (fortunately, in the same place in
2837 * each such register :-). To start the state machine, this bit must
2838 * be written with 1, then polled to see when the state machine has
2839 * actually started.
2840 *
2841 * The return value is B_TRUE on success (enable bit set), or
2842 * B_FALSE if the state machine didn't start :(
2843 */
2844 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2845 uint32_t morebits);
2846 #pragma no_inline(bge_chip_enable_engine)
2847
2848 static boolean_t
2849 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2850 {
2851 uint32_t regval;
2852
2853 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2854 (void *)bgep, regno, morebits));
2855
2856 switch (regno) {
2857 case FTQ_RESET_REG:
2858 #ifdef BGE_IPMI_ASF
2859 #ifdef BGE_NETCONSOLE
2860 if (bgep->asf_enabled)
2861 return (B_TRUE);
2862 #endif
2863 #endif
2864 /*
2865 * Not quite like the others; it doesn't
2866 * have an <enable> bit, but instead we
2867 * have to set and then clear all the bits
2868 */
2869 bge_reg_put32(bgep, regno, ~(uint32_t)0);
2870 drv_usecwait(100);
2871 bge_reg_put32(bgep, regno, 0);
2872 return (B_TRUE);
2873
2874 default:
2875 regval = bge_reg_get32(bgep, regno);
2876 regval |= STATE_MACHINE_ENABLE_BIT;
2877 regval |= morebits;
2878 bge_reg_put32(bgep, regno, regval);
2879 return (bge_chip_poll_engine(bgep, regno,
2880 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2881 }
2882 }
2883
2884 /*
2885 * Reprogram the Ethernet, Transmit, and Receive MAC
2886 * modes to match the param_* variables
2887 */
2888 void bge_sync_mac_modes(bge_t *bgep);
2889 #pragma no_inline(bge_sync_mac_modes)
2890
2891 void
2892 bge_sync_mac_modes(bge_t *bgep)
2893 {
2894 uint32_t macmode;
2895 uint32_t regval;
2896
2897 ASSERT(mutex_owned(bgep->genlock));
2898
2899 /*
2900 * Reprogram the Ethernet MAC mode ...
2901 */
2902 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2903 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2904 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2905 if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2906 macmode |= ETHERNET_MODE_LINK_POLARITY;
2907 else
2908 macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2909 else
2910 macmode |= ETHERNET_MODE_LINK_POLARITY;
2911 macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2912 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2913 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
2914 if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2915 macmode |= ETHERNET_MODE_PORTMODE_GMII;
2916 else
2917 macmode |= ETHERNET_MODE_PORTMODE_TBI;
2918 } else if (bgep->param_link_speed == 10 ||
2919 bgep->param_link_speed == 100)
2920 macmode |= ETHERNET_MODE_PORTMODE_MII;
2921 else
2922 macmode |= ETHERNET_MODE_PORTMODE_GMII;
2923 if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2924 macmode |= ETHERNET_MODE_HALF_DUPLEX;
2925 else
2926 macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2927 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2928 macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2929 else
2930 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2931 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2932 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2933 (void *)bgep, regval, macmode));
2934
2935 /*
2936 * ... the Transmit MAC mode ...
2937 */
2938 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2939 if (bgep->param_link_tx_pause)
2940 macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2941 else
2942 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2943 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2944 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2945 (void *)bgep, regval, macmode));
2946
2947 /*
2948 * ... and the Receive MAC mode
2949 */
2950 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2951 if (bgep->param_link_rx_pause)
2952 macmode |= RECEIVE_MODE_FLOW_CONTROL;
2953 else
2954 macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2955 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2956 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2957 (void *)bgep, regval, macmode));
2958
2959 /*
2960 * For BCM5785, we need to configure the link status in the MI Status
2961 * register with a write command when auto-polling is disabled.
2962 */
2963 if (bgep->chipid.device == DEVICE_ID_5785)
2964 if (bgep->param_link_speed == 10)
2965 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
2966 | MI_STATUS_10MBPS);
2967 else
2968 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
2969 }
2970
2971 /*
2972 * bge_chip_sync() -- program the chip with the unicast MAC address,
2973 * the multicast hash table, the required level of promiscuity, and
2974 * the current loopback mode ...
2975 */
2976 #ifdef BGE_IPMI_ASF
2977 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2978 #else
2979 int bge_chip_sync(bge_t *bgep);
2980 #endif
2981 #pragma no_inline(bge_chip_sync)
2982
2983 int
2984 #ifdef BGE_IPMI_ASF
2985 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2986 #else
2987 bge_chip_sync(bge_t *bgep)
2988 #endif
2989 {
2990 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2991 boolean_t promisc;
2992 uint64_t macaddr;
2993 uint32_t fill = 0;
2994 int i, j;
2995 int retval = DDI_SUCCESS;
2996
2997 BGE_TRACE(("bge_chip_sync($%p)",
2998 (void *)bgep));
2999
3000 ASSERT(mutex_owned(bgep->genlock));
3001
3002 promisc = B_FALSE;
3003 fill = ~(uint32_t)0;
3004
3005 if (bgep->promisc)
3006 promisc = B_TRUE;
3007 else
3008 fill = (uint32_t)0;
3009
3010 /*
3011 * If the TX/RX MAC engines are already running, we should stop
3012 * them (and reset the RX engine) before changing the parameters.
3013 * If they're not running, this will have no effect ...
3014 *
3015 * NOTE: this is currently disabled by default because stopping
3016 * and restarting the Tx engine may cause an outgoing packet in
3017 * transit to be truncated. Also, stopping and restarting the
3018 * Rx engine seems to not work correctly on the 5705. Testing
3019 * has not (yet!) revealed any problems with NOT stopping and
3020 * restarting these engines (and Broadcom say their drivers don't
3021 * do this), but if it is found to cause problems, this variable
3022 * can be patched to re-enable the old behaviour ...
3023 */
3024 if (bge_stop_start_on_sync) {
3025 #ifdef BGE_IPMI_ASF
3026 if (!bgep->asf_enabled) {
3027 if (!bge_chip_disable_engine(bgep,
3028 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3029 retval = DDI_FAILURE;
3030 } else {
3031 if (!bge_chip_disable_engine(bgep,
3032 RECEIVE_MAC_MODE_REG, 0))
3033 retval = DDI_FAILURE;
3034 }
3035 #else
3036 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
3037 RECEIVE_MODE_KEEP_VLAN_TAG))
3038 retval = DDI_FAILURE;
3039 #endif
3040 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3041 retval = DDI_FAILURE;
3042 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3043 retval = DDI_FAILURE;
3044 }
3045
3046 /*
3047 * Reprogram the hashed multicast address table ...
3048 */
3049 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3050 bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3051
3052 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3053 bge_reg_put32(bgep, MAC_HASH_REG(i),
3054 bgep->mcast_hash[i] | fill);
3055
3056 #ifdef BGE_IPMI_ASF
3057 if (!bgep->asf_enabled || !asf_keeplive) {
3058 #endif
3059 /*
3060 * Transform the MAC address(es) from host to chip format, then
3061 * reprogram the transmit random backoff seed and the unicast
3062 * MAC address(es) ...
3063 */
3064 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
3065 for (i = 0, macaddr = 0ull;
3066 i < ETHERADDRL; ++i) {
3067 macaddr <<= 8;
3068 macaddr |= bgep->curr_addr[j].addr[i];
3069 }
3070 fill += (macaddr >> 16) + (macaddr & 0xffffffff);
3071 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3072
3073 BGE_DEBUG(("bge_chip_sync($%p) "
3074 "setting MAC address %012llx",
3075 (void *)bgep, macaddr));
3076 }
3077 #ifdef BGE_IPMI_ASF
3078 }
3079 #endif
3080 /*
3081 * Set random seed of backoff interval
3082 * - Writing zero means no backoff interval
3083 */
3084 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
3085 if (fill == 0)
3086 fill = 1;
3087 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3088
3089 /*
3090 * Set or clear the PROMISCUOUS mode bit
3091 */
3092 opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3093 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3094
3095 /*
3096 * Sync the rest of the MAC modes too ...
3097 */
3098 bge_sync_mac_modes(bgep);
3099
3100 /*
3101 * Restart RX/TX MAC engines if required ...
3102 */
3103 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3104 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3105 retval = DDI_FAILURE;
3106 #ifdef BGE_IPMI_ASF
3107 if (!bgep->asf_enabled) {
3108 if (!bge_chip_enable_engine(bgep,
3109 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3110 retval = DDI_FAILURE;
3111 } else {
3112 if (!bge_chip_enable_engine(bgep,
3113 RECEIVE_MAC_MODE_REG, 0))
3114 retval = DDI_FAILURE;
3115 }
3116 #else
3117 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3118 RECEIVE_MODE_KEEP_VLAN_TAG))
3119 retval = DDI_FAILURE;
3120 #endif
3121 }
3122 return (retval);
3123 }
3124
3125 /*
3126 * This array defines the sequence of state machine control registers
3127 * in which the <enable> bit must be cleared to bring the chip to a
3128 * clean stop. Taken from Broadcom document 570X-PG102-R, p116.
3129 */
3130 static bge_regno_t shutdown_engine_regs[] = {
3131 RECEIVE_MAC_MODE_REG,
3132 RCV_BD_INITIATOR_MODE_REG,
3133 RCV_LIST_PLACEMENT_MODE_REG,
3134 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */
3135 RCV_DATA_BD_INITIATOR_MODE_REG,
3136 RCV_DATA_COMPLETION_MODE_REG,
3137 RCV_BD_COMPLETION_MODE_REG,
3138
3139 SEND_BD_SELECTOR_MODE_REG,
3140 SEND_BD_INITIATOR_MODE_REG,
3141 SEND_DATA_INITIATOR_MODE_REG,
3142 READ_DMA_MODE_REG,
3143 SEND_DATA_COMPLETION_MODE_REG,
3144 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */
3145 SEND_BD_COMPLETION_MODE_REG,
3146 TRANSMIT_MAC_MODE_REG,
3147
3148 HOST_COALESCE_MODE_REG,
3149 WRITE_DMA_MODE_REG,
3150 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */
3151 FTQ_RESET_REG, /* special - see code */
3152 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */
3153 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */
3154 BGE_REGNO_NONE /* terminator */
3155 };
3156
3157 #ifndef __sparc
3158 static bge_regno_t quiesce_regs[] = {
3159 READ_DMA_MODE_REG,
3160 DMA_COMPLETION_MODE_REG,
3161 WRITE_DMA_MODE_REG,
3162 BGE_REGNO_NONE
3163 };
3164
3165 void bge_chip_stop_nonblocking(bge_t *bgep);
3166 #pragma no_inline(bge_chip_stop_nonblocking)
3167
3168 /*
3169 * This function is called by bge_quiesce(). We
3170 * turn off all the DMA engines here.
3171 */
3172 void
3173 bge_chip_stop_nonblocking(bge_t *bgep)
3174 {
3175 bge_regno_t *rbp;
3176
3177 /*
3178 * Flag that no more activity may be initiated
3179 */
3180 bgep->progress &= ~PROGRESS_READY;
3181
3182 rbp = quiesce_regs;
3183 while (*rbp != BGE_REGNO_NONE) {
3184 (void) bge_chip_disable_engine(bgep, *rbp, 0);
3185 ++rbp;
3186 }
3187
3188 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3189 }
3190
3191 #endif
3192
3193 /*
3194 * bge_chip_stop() -- stop all chip processing
3195 *
3196 * If the <fault> parameter is B_TRUE, we're stopping the chip because
3197 * we've detected a problem internally; otherwise, this is a normal
3198 * (clean) stop (at user request i.e. the last STREAM has been closed).
3199 */
3200 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3201 #pragma no_inline(bge_chip_stop)
3202
3203 void
3204 bge_chip_stop(bge_t *bgep, boolean_t fault)
3205 {
3206 bge_regno_t regno;
3207 bge_regno_t *rbp;
3208 boolean_t ok;
3209
3210 BGE_TRACE(("bge_chip_stop($%p)",
3211 (void *)bgep));
3212
3213 ASSERT(mutex_owned(bgep->genlock));
3214
3215 rbp = shutdown_engine_regs;
3216 /*
3217 * When driver try to shutdown the BCM5705/5788/5721/5751/
3218 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
3219 * -ory arbiter should not be disabled.
3220 */
3221 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
3222 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3223 ok &= bge_chip_disable_engine(bgep, regno, 0);
3224 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
3225 (regno != DMA_COMPLETION_MODE_REG) &&
3226 (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
3227 (regno != BUFFER_MANAGER_MODE_REG) &&
3228 (regno != MEMORY_ARBITER_MODE_REG))
3229 ok &= bge_chip_disable_engine(bgep,
3230 regno, 0);
3231 }
3232
3233 if (!ok && !fault)
3234 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3235
3236 /*
3237 * Finally, disable (all) MAC events & clear the MAC status
3238 */
3239 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3240 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3241
3242 /*
3243 * if we're stopping the chip because of a detected fault then do
3244 * appropriate actions
3245 */
3246 if (fault) {
3247 if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3248 bgep->bge_chip_state = BGE_CHIP_FAULT;
3249 if (!bgep->manual_reset)
3250 ddi_fm_service_impact(bgep->devinfo,
3251 DDI_SERVICE_LOST);
3252 if (bgep->bge_dma_error) {
3253 /*
3254 * need to free buffers in case the fault was
3255 * due to a memory error in a buffer - got to
3256 * do a fair bit of tidying first
3257 */
3258 if (bgep->progress & PROGRESS_KSTATS) {
3259 bge_fini_kstats(bgep);
3260 bgep->progress &= ~PROGRESS_KSTATS;
3261 }
3262 if (bgep->progress & PROGRESS_INTR) {
3263 bge_intr_disable(bgep);
3264 rw_enter(bgep->errlock, RW_WRITER);
3265 bge_fini_rings(bgep);
3266 rw_exit(bgep->errlock);
3267 bgep->progress &= ~PROGRESS_INTR;
3268 }
3269 if (bgep->progress & PROGRESS_BUFS) {
3270 bge_free_bufs(bgep);
3271 bgep->progress &= ~PROGRESS_BUFS;
3272 }
3273 bgep->bge_dma_error = B_FALSE;
3274 }
3275 }
3276 } else
3277 bgep->bge_chip_state = BGE_CHIP_STOPPED;
3278 }
3279
3280 /*
3281 * Poll for completion of chip's ROM firmware; also, at least on the
3282 * first time through, find and return the hardware MAC address, if any.
3283 */
3284 static uint64_t bge_poll_firmware(bge_t *bgep);
3285 #pragma no_inline(bge_poll_firmware)
3286
3287 static uint64_t
3288 bge_poll_firmware(bge_t *bgep)
3289 {
3290 uint64_t magic;
3291 uint64_t mac;
3292 uint32_t gen, val;
3293 uint32_t i;
3294
3295 /*
3296 * Step 19: poll for firmware completion (GENCOMM port set
3297 * to the ones complement of T3_MAGIC_NUMBER).
3298 *
3299 * While we're at it, we also read the MAC address register;
3300 * at some stage the firmware will load this with the
3301 * factory-set value.
3302 *
3303 * When both the magic number and the MAC address are set,
3304 * we're done; but we impose a time limit of one second
3305 * (1000*1000us) in case the firmware fails in some fashion
3306 * or the SEEPROM that provides that MAC address isn't fitted.
3307 *
3308 * After the first time through (chip state != INITIAL), we
3309 * don't need the MAC address to be set (we've already got it
3310 * or not, from the first time), so we don't wait for it, but
3311 * we still have to wait for the T3_MAGIC_NUMBER.
3312 *
3313 * Note: the magic number is only a 32-bit quantity, but the NIC
3314 * memory is 64-bit (and big-endian) internally. Addressing the
3315 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3316 * it work correctly on both big- and little-endian hosts.
3317 */
3318 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3319 MHCR_CHIP_ASIC_REV_5906) {
3320 for (i = 0; i < 1000; ++i) {
3321 drv_usecwait(1000);
3322 val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3323 if (val & VCPU_INIT_DONE)
3324 break;
3325 }
3326 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3327 (void *)bgep, i));
3328 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3329 } else {
3330 for (i = 0; i < 1000; ++i) {
3331 drv_usecwait(1000);
3332 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3333 #ifdef BGE_IPMI_ASF
3334 if (!bgep->asf_enabled) {
3335 #endif
3336 if (gen != ~T3_MAGIC_NUMBER)
3337 continue;
3338 #ifdef BGE_IPMI_ASF
3339 }
3340 #endif
3341 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3342 if (mac != 0ULL)
3343 break;
3344 if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3345 break;
3346 }
3347 }
3348
3349 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3350 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3351 (void *)bgep, gen, i));
3352 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3353 mac, magic));
3354
3355 return (mac);
3356 }
3357
3358 /*
3359 * Maximum times of trying to get the NVRAM access lock
3360 * by calling bge_nvmem_acquire()
3361 */
3362 #define MAX_TRY_NVMEM_ACQUIRE 10000
3363
3364 #ifdef BGE_IPMI_ASF
3365 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3366 #else
3367 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3368 #endif
3369 #pragma no_inline(bge_chip_reset)
3370
3371 int
3372 #ifdef BGE_IPMI_ASF
3373 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3374 #else
3375 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3376 #endif
3377 {
3378 chip_id_t chipid;
3379 uint64_t mac;
3380 uint64_t magic;
3381 uint32_t modeflags;
3382 uint32_t mhcr;
3383 uint32_t sx0;
3384 uint32_t i, tries;
3385 #ifdef BGE_IPMI_ASF
3386 uint32_t mailbox;
3387 #endif
3388 int retval = DDI_SUCCESS;
3389
3390 BGE_TRACE(("bge_chip_reset($%p, %d)",
3391 (void *)bgep, enable_dma));
3392
3393 ASSERT(mutex_owned(bgep->genlock));
3394
3395 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3396 (void *)bgep, enable_dma, bgep->bge_chip_state));
3397
3398 /*
3399 * Do we need to stop the chip cleanly before resetting?
3400 */
3401 switch (bgep->bge_chip_state) {
3402 default:
3403 _NOTE(NOTREACHED)
3404 return (DDI_FAILURE);
3405
3406 case BGE_CHIP_INITIAL:
3407 case BGE_CHIP_STOPPED:
3408 case BGE_CHIP_RESET:
3409 break;
3410
3411 case BGE_CHIP_RUNNING:
3412 case BGE_CHIP_ERROR:
3413 case BGE_CHIP_FAULT:
3414 bge_chip_stop(bgep, B_FALSE);
3415 break;
3416 }
3417
3418 #ifdef BGE_IPMI_ASF
3419 if (bgep->asf_enabled) {
3420 #ifdef __sparc
3421 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3422 MHCR_ENABLE_TAGGED_STATUS_MODE |
3423 MHCR_MASK_INTERRUPT_MODE |
3424 MHCR_CLEAR_INTERRUPT_INTA |
3425 MHCR_ENABLE_ENDIAN_WORD_SWAP |
3426 MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3427
3428 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3429 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3430
3431 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3432 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3433 0);
3434 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3435 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3436 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3437 MEMORY_ARBITER_ENABLE);
3438 #endif
3439 if (asf_mode == ASF_MODE_INIT) {
3440 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3441 } else if (asf_mode == ASF_MODE_SHUTDOWN) {
3442 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3443 }
3444 }
3445 #endif
3446 /*
3447 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3448 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3449 *
3450 * Before reset Core clock,it is
3451 * also required to initialize the Memory Arbiter as specified in step9
3452 * and Misc Host Control Register as specified in step-13
3453 * Step 4-5: reset Core clock & wait for completion
3454 * Steps 6-8: are done by bge_chip_cfg_init()
3455 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3456 */
3457 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3458 retval = DDI_FAILURE;
3459
3460 mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3461 MHCR_ENABLE_TAGGED_STATUS_MODE |
3462 MHCR_MASK_INTERRUPT_MODE |
3463 MHCR_CLEAR_INTERRUPT_INTA;
3464
3465 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
3466 mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
3467
3468 #ifdef _BIG_ENDIAN
3469 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3470 #endif /* _BIG_ENDIAN */
3471 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3472 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3473 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3474 #ifdef BGE_IPMI_ASF
3475 if (bgep->asf_enabled)
3476 bgep->asf_wordswapped = B_FALSE;
3477 #endif
3478 /*
3479 * NVRAM Corruption Workaround
3480 */
3481 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3482 if (bge_nvmem_acquire(bgep) != EAGAIN)
3483 break;
3484 if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3485 BGE_DEBUG(("%s: fail to acquire nvram lock",
3486 bgep->ifname));
3487
3488 #ifdef BGE_IPMI_ASF
3489 if (!bgep->asf_enabled) {
3490 #endif
3491 magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3492 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3493 #ifdef BGE_IPMI_ASF
3494 }
3495 #endif
3496
3497 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3498 retval = DDI_FAILURE;
3499 bge_chip_cfg_init(bgep, &chipid, enable_dma);
3500
3501 /*
3502 * Step 8a: This may belong elsewhere, but BCM5721 needs
3503 * a bit set to avoid a fifo overflow/underflow bug.
3504 */
3505 if ((bgep->chipid.chip_label == 5721) ||
3506 (bgep->chipid.chip_label == 5751) ||
3507 (bgep->chipid.chip_label == 5752) ||
3508 (bgep->chipid.chip_label == 5755) ||
3509 (bgep->chipid.chip_label == 5756) ||
3510 (bgep->chipid.chip_label == 5789) ||
3511 (bgep->chipid.chip_label == 5906))
3512 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3513
3514
3515 /*
3516 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3517 * not be changed.
3518 */
3519 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3520 retval = DDI_FAILURE;
3521
3522 /*
3523 * Steps 10-11: configure PIO endianness options and
3524 * enable indirect register access -- already done
3525 * Steps 12-13: enable writing to the PCI state & clock
3526 * control registers -- not required; we aren't going to
3527 * use those features.
3528 * Steps 14-15: Configure DMA endianness options. See
3529 * the comments on the setting of the MHCR above.
3530 */
3531 #ifdef _BIG_ENDIAN
3532 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3533 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3534 #else
3535 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3536 #endif /* _BIG_ENDIAN */
3537 #ifdef BGE_IPMI_ASF
3538 if (bgep->asf_enabled)
3539 modeflags |= MODE_HOST_STACK_UP;
3540 #endif
3541 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3542
3543 #ifdef BGE_IPMI_ASF
3544 if (bgep->asf_enabled) {
3545 #ifdef __sparc
3546 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3547 MEMORY_ARBITER_ENABLE |
3548 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3549 #endif
3550
3551 #ifdef BGE_NETCONSOLE
3552 if (!bgep->asf_newhandshake) {
3553 if ((asf_mode == ASF_MODE_INIT) ||
3554 (asf_mode == ASF_MODE_POST_INIT)) {
3555 bge_asf_post_reset_old_mode(bgep,
3556 BGE_INIT_RESET);
3557 } else {
3558 bge_asf_post_reset_old_mode(bgep,
3559 BGE_SHUTDOWN_RESET);
3560 }
3561 }
3562 #endif
3563
3564 /* Wait for NVRAM init */
3565 i = 0;
3566 drv_usecwait(5000);
3567 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3568
3569 while ((mailbox != (uint32_t)
3570 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3571 (i < 10000)) {
3572 drv_usecwait(100);
3573 mailbox = bge_nic_get32(bgep,
3574 BGE_FIRMWARE_MAILBOX);
3575 i++;
3576 }
3577
3578 #ifndef BGE_NETCONSOLE
3579 if (!bgep->asf_newhandshake) {
3580 if ((asf_mode == ASF_MODE_INIT) ||
3581 (asf_mode == ASF_MODE_POST_INIT)) {
3582
3583 bge_asf_post_reset_old_mode(bgep,
3584 BGE_INIT_RESET);
3585 } else {
3586 bge_asf_post_reset_old_mode(bgep,
3587 BGE_SHUTDOWN_RESET);
3588 }
3589 }
3590 #endif
3591 }
3592 #endif
3593 /*
3594 * Steps 16-17: poll for firmware completion
3595 */
3596 mac = bge_poll_firmware(bgep);
3597
3598 /*
3599 * Step 18: enable external memory -- doesn't apply.
3600 *
3601 * However we take the opportunity to set the MLCR anyway, as
3602 * this register also controls the SEEPROM auto-access method
3603 * which we may want to use later ...
3604 *
3605 * The proper value here depends on the way the chip is wired
3606 * into the circuit board, as this register *also* controls which
3607 * of the "Miscellaneous I/O" pins are driven as outputs and the
3608 * values driven onto those pins!
3609 *
3610 * See also step 74 in the PRM ...
3611 */
3612 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3613 bgep->chipid.bge_mlcr_default);
3614 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3615
3616 /*
3617 * Step 20: clear the Ethernet MAC mode register
3618 */
3619 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3620
3621 /*
3622 * Step 21: restore cache-line-size, latency timer, and
3623 * subsystem ID registers to their original values (not
3624 * those read into the local structure <chipid>, 'cos
3625 * that was after they were cleared by the RESET).
3626 *
3627 * Note: the Subsystem Vendor/Device ID registers are not
3628 * directly writable in config space, so we use the shadow
3629 * copy in "Page Zero" of register space to restore them
3630 * both in one go ...
3631 */
3632 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3633 bgep->chipid.clsize);
3634 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3635 bgep->chipid.latency);
3636 bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3637 (bgep->chipid.subdev << 16) | bgep->chipid.subven);
3638
3639 /*
3640 * The SEND INDEX registers should be reset to zero by the
3641 * global chip reset; if they're not, there'll be trouble
3642 * later on.
3643 */
3644 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3645 if (sx0 != 0) {
3646 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3647 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3648 retval = DDI_FAILURE;
3649 }
3650
3651 /* Enable MSI code */
3652 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3653 bge_reg_set32(bgep, MSI_MODE_REG,
3654 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3655
3656 /*
3657 * On the first time through, save the factory-set MAC address
3658 * (if any). If bge_poll_firmware() above didn't return one
3659 * (from a chip register) consider looking in the attached NV
3660 * memory device, if any. Once we have it, we save it in both
3661 * register-image (64-bit) and byte-array forms. All-zero and
3662 * all-one addresses are not valid, and we refuse to stash those.
3663 */
3664 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3665 if (mac == 0ULL)
3666 mac = bge_get_nvmac(bgep);
3667 if (mac != 0ULL && mac != ~0ULL) {
3668 bgep->chipid.hw_mac_addr = mac;
3669 for (i = ETHERADDRL; i-- != 0; ) {
3670 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3671 mac >>= 8;
3672 }
3673 bgep->chipid.vendor_addr.set = B_TRUE;
3674 }
3675 }
3676
3677 #ifdef BGE_IPMI_ASF
3678 if (bgep->asf_enabled && bgep->asf_newhandshake) {
3679 if (asf_mode != ASF_MODE_NONE) {
3680 if ((asf_mode == ASF_MODE_INIT) ||
3681 (asf_mode == ASF_MODE_POST_INIT)) {
3682
3683 bge_asf_post_reset_new_mode(bgep,
3684 BGE_INIT_RESET);
3685 } else {
3686 bge_asf_post_reset_new_mode(bgep,
3687 BGE_SHUTDOWN_RESET);
3688 }
3689 }
3690 }
3691 #endif
3692
3693 /*
3694 * Record the new state
3695 */
3696 bgep->chip_resets += 1;
3697 bgep->bge_chip_state = BGE_CHIP_RESET;
3698 return (retval);
3699 }
3700
3701 /*
3702 * bge_chip_start() -- start the chip transmitting and/or receiving,
3703 * including enabling interrupts
3704 */
3705 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3706 #pragma no_inline(bge_chip_start)
3707
3708 void
3709 bge_chip_coalesce_update(bge_t *bgep)
3710 {
3711 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3712 bgep->chipid.tx_count_norm);
3713 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3714 bgep->chipid.tx_ticks_norm);
3715 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3716 bgep->chipid.rx_count_norm);
3717 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3718 bgep->chipid.rx_ticks_norm);
3719 }
3720
3721 int
3722 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3723 {
3724 uint32_t coalmode;
3725 uint32_t ledctl;
3726 uint32_t mtu;
3727 uint32_t maxring;
3728 uint32_t stats_mask;
3729 uint32_t dma_wrprio;
3730 uint64_t ring;
3731 uint32_t regval;
3732 int retval = DDI_SUCCESS;
3733
3734 BGE_TRACE(("bge_chip_start($%p)",
3735 (void *)bgep));
3736
3737 ASSERT(mutex_owned(bgep->genlock));
3738 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3739
3740 /*
3741 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3742 * The document specifies 95 separate steps to fully
3743 * initialise the chip!!!!
3744 *
3745 * The reset code above has already got us as far as step
3746 * 21, so we continue with ...
3747 *
3748 * Step 22: clear the MAC statistics block
3749 * (0x0300-0x0aff in NIC-local memory)
3750 */
3751 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3752 bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3753 NIC_MEM_STATISTICS_SIZE);
3754
3755 /*
3756 * Step 23: clear the status block (in host memory)
3757 */
3758 DMA_ZERO(bgep->status_block);
3759
3760 /*
3761 * Step 24: set DMA read/write control register
3762 */
3763 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3764 bgep->chipid.bge_dma_rwctrl);
3765
3766 /*
3767 * Step 25: Configure DMA endianness -- already done (16/17)
3768 * Step 26: Configure Host-Based Send Rings
3769 * Step 27: Indicate Host Stack Up
3770 */
3771 bge_reg_set32(bgep, MODE_CONTROL_REG,
3772 MODE_HOST_SEND_BDS |
3773 MODE_HOST_STACK_UP);
3774
3775 /*
3776 * Step 28: Configure checksum options:
3777 * Solaris supports the hardware default checksum options.
3778 *
3779 * Workaround for Incorrect pseudo-header checksum calculation.
3780 */
3781 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3782 bge_reg_set32(bgep, MODE_CONTROL_REG,
3783 MODE_SEND_NO_PSEUDO_HDR_CSUM);
3784
3785 /*
3786 * Step 29: configure Timer Prescaler. The value is always the
3787 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3788 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit
3789 * for the whole chip!
3790 */
3791 regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
3792 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT;
3793 bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
3794
3795 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3796 drv_usecwait(40);
3797 /* put PHY into ready state */
3798 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
3799 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
3800 drv_usecwait(40);
3801 }
3802
3803 /*
3804 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3805 *
3806 * If the mbuf_length is specified as 0, we just leave these at
3807 * their hardware defaults, rather than explicitly setting them.
3808 * As the Broadcom HRM,driver better not change the parameters
3809 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3810 */
3811 if ((bgep->chipid.mbuf_length != 0) &&
3812 (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3813 bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3814 bgep->chipid.mbuf_base);
3815 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3816 bgep->chipid.mbuf_length);
3817 bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3818 DMAD_POOL_BASE_DEFAULT);
3819 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3820 DMAD_POOL_LENGTH_DEFAULT);
3821 }
3822
3823 /*
3824 * Step 32: configure MAC memory pool watermarks
3825 */
3826 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3827 bgep->chipid.mbuf_lo_water_rdma);
3828 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3829 bgep->chipid.mbuf_lo_water_rmac);
3830 bge_reg_put32(bgep, MBUF_HIWAT_REG,
3831 bgep->chipid.mbuf_hi_water);
3832
3833 /*
3834 * Step 33: configure DMA resource watermarks
3835 */
3836 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3837 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3838 bge_dmad_lo_water);
3839 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3840 bge_dmad_hi_water);
3841 }
3842 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3843
3844 /*
3845 * Steps 34-36: enable buffer manager & internal h/w queues
3846 */
3847 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3848 STATE_MACHINE_ATTN_ENABLE_BIT))
3849 retval = DDI_FAILURE;
3850 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3851 retval = DDI_FAILURE;
3852
3853 /*
3854 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3855 */
3856 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
3857 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
3858 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
3859 brp->desc.cookie.dmac_laddress);
3860 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
3861 (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
3862 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
3863 NIC_MEM_SHADOW_BUFF_STD_5717);
3864 } else
3865 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3866 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3867
3868 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3869 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3870 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3871 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3872 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3873 }
3874
3875 /*
3876 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3877 */
3878 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3879 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3880 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3881 bge_replenish_jumbo);
3882 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3883 bge_replenish_mini);
3884 }
3885
3886 /*
3887 * Steps 41-43: clear Send Ring Producer Indices and initialise
3888 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3889 */
3890 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3891 maxring = BGE_SEND_RINGS_MAX;
3892 else
3893 maxring = BGE_SEND_RINGS_MAX_5705;
3894 for (ring = 0; ring < maxring; ++ring) {
3895 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3896 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3897 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3898 &bgep->send[ring].hw_rcb);
3899 }
3900
3901 /*
3902 * Steps 44-45: initialise Receive Return Rings
3903 * (0x0200-0x02ff in NIC-local memory)
3904 */
3905 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3906 maxring = BGE_RECV_RINGS_MAX;
3907 else
3908 maxring = BGE_RECV_RINGS_MAX_5705;
3909 for (ring = 0; ring < maxring; ++ring)
3910 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3911 &bgep->recv[ring].hw_rcb);
3912
3913 /*
3914 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3915 */
3916 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3917 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3918 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3919 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3920 }
3921 /*
3922 * Step 47: configure the MAC unicast address
3923 * Step 48: configure the random backoff seed
3924 * Step 96: set up multicast filters
3925 */
3926 #ifdef BGE_IPMI_ASF
3927 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3928 #else
3929 if (bge_chip_sync(bgep) == DDI_FAILURE)
3930 #endif
3931 retval = DDI_FAILURE;
3932
3933 /*
3934 * Step 49: configure the MTU
3935 */
3936 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3937 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3938
3939 /*
3940 * Step 50: configure the IPG et al
3941 */
3942 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3943
3944 /*
3945 * Step 51: configure the default Rx Return Ring
3946 */
3947 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3948
3949 /*
3950 * Steps 52-54: configure Receive List Placement,
3951 * and enable Receive List Placement Statistics
3952 */
3953 bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3954 RCV_LP_CONFIG(bgep->chipid.rx_rings));
3955 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3956 case MHCR_CHIP_ASIC_REV_5700:
3957 case MHCR_CHIP_ASIC_REV_5701:
3958 case MHCR_CHIP_ASIC_REV_5703:
3959 case MHCR_CHIP_ASIC_REV_5704:
3960 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3961 break;
3962 case MHCR_CHIP_ASIC_REV_5705:
3963 break;
3964 default:
3965 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3966 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3967 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3968 break;
3969 }
3970 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3971
3972 if (bgep->chipid.rx_rings > 1)
3973 bge_init_recv_rule(bgep);
3974
3975 /*
3976 * Steps 55-56: enable Send Data Initiator Statistics
3977 */
3978 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3979 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3980 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3981 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3982 } else {
3983 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3984 SEND_INIT_STATS_ENABLE);
3985 }
3986 /*
3987 * Steps 57-58: stop (?) the Host Coalescing Engine
3988 */
3989 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3990 retval = DDI_FAILURE;
3991
3992 /*
3993 * Steps 59-62: initialise Host Coalescing parameters
3994 */
3995 bge_chip_coalesce_update(bgep);
3996 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3997 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3998 bge_tx_count_intr);
3999 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
4000 bge_tx_ticks_intr);
4001 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
4002 bge_rx_count_intr);
4003 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
4004 bge_rx_ticks_intr);
4005 }
4006
4007 /*
4008 * Steps 63-64: initialise status block & statistics
4009 * host memory addresses
4010 * The statistic block does not exist in some chipsets
4011 * Step 65: initialise Statistics Coalescing Tick Counter
4012 */
4013 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
4014 bgep->status_block.cookie.dmac_laddress);
4015
4016 /*
4017 * Steps 66-67: initialise status block & statistics
4018 * NIC-local memory addresses
4019 */
4020 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
4021 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
4022 bgep->statistics.cookie.dmac_laddress);
4023 bge_reg_put32(bgep, STATISTICS_TICKS_REG,
4024 STATISTICS_TICKS_DEFAULT);
4025 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
4026 NIC_MEM_STATUS_BLOCK);
4027 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4028 NIC_MEM_STATISTICS);
4029 }
4030
4031 /*
4032 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4033 * Completion Engine, the Receive List Placement Engine, and the
4034 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4035 * and BCM5715.
4036 */
4037 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4038 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4039 coalmode = COALESCE_64_BYTE_STATUS;
4040 else
4041 coalmode = 0;
4042 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
4043 coalmode = COALESCE_CLR_TICKS_RX;
4044 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4045 retval = DDI_FAILURE;
4046 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4047 STATE_MACHINE_ATTN_ENABLE_BIT))
4048 retval = DDI_FAILURE;
4049 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4050 retval = DDI_FAILURE;
4051
4052 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4053 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4054 STATE_MACHINE_ATTN_ENABLE_BIT))
4055 retval = DDI_FAILURE;
4056
4057 /*
4058 * Step 72: Enable MAC DMA engines
4059 * Step 73: Clear & enable MAC statistics
4060 */
4061 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4062 ETHERNET_MODE_ENABLE_FHDE |
4063 ETHERNET_MODE_ENABLE_RDE |
4064 ETHERNET_MODE_ENABLE_TDE);
4065 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4066 ETHERNET_MODE_ENABLE_TX_STATS |
4067 ETHERNET_MODE_ENABLE_RX_STATS |
4068 ETHERNET_MODE_CLEAR_TX_STATS |
4069 ETHERNET_MODE_CLEAR_RX_STATS);
4070
4071 /*
4072 * Step 74: configure the MLCR (Miscellaneous Local Control
4073 * Register); not required, as we set up the MLCR in step 10
4074 * (part of the reset code) above.
4075 *
4076 * Step 75: clear Interrupt Mailbox 0
4077 */
4078 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4079
4080 /*
4081 * Steps 76-87: Gentlemen, start your engines ...
4082 *
4083 * Enable the DMA Completion Engine, the Write DMA Engine,
4084 * the Read DMA Engine, Receive Data Completion Engine,
4085 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4086 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4087 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4088 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4089 *
4090 * Beware exhaust fumes?
4091 */
4092 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4093 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4094 retval = DDI_FAILURE;
4095 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4096 ALL_DMA_ATTN_BITS;
4097 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4098 MHCR_CHIP_ASIC_REV_5755) ||
4099 DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4100 DEVICE_5906_SERIES_CHIPSETS(bgep)) {
4101 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4102 }
4103 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4104 dma_wrprio))
4105 retval = DDI_FAILURE;
4106 if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4107 DEVICE_5717_SERIES_CHIPSETS(bgep))
4108 bge_dma_rdprio = 0;
4109 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4110 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
4111 retval = DDI_FAILURE;
4112 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4113 STATE_MACHINE_ATTN_ENABLE_BIT))
4114 retval = DDI_FAILURE;
4115 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4116 if (!bge_chip_enable_engine(bgep,
4117 MBUF_CLUSTER_FREE_MODE_REG, 0))
4118 retval = DDI_FAILURE;
4119 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4120 retval = DDI_FAILURE;
4121 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4122 STATE_MACHINE_ATTN_ENABLE_BIT))
4123 retval = DDI_FAILURE;
4124 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4125 RCV_BD_DISABLED_RING_ATTN))
4126 retval = DDI_FAILURE;
4127 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4128 RCV_DATA_BD_ILL_RING_ATTN))
4129 retval = DDI_FAILURE;
4130 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4131 retval = DDI_FAILURE;
4132 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4133 STATE_MACHINE_ATTN_ENABLE_BIT))
4134 retval = DDI_FAILURE;
4135 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4136 STATE_MACHINE_ATTN_ENABLE_BIT))
4137 retval = DDI_FAILURE;
4138
4139 /*
4140 * Step 88: download firmware -- doesn't apply
4141 * Steps 89-90: enable Transmit & Receive MAC Engines
4142 */
4143 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
4144 retval = DDI_FAILURE;
4145 #ifdef BGE_IPMI_ASF
4146 if (!bgep->asf_enabled) {
4147 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4148 RECEIVE_MODE_KEEP_VLAN_TAG))
4149 retval = DDI_FAILURE;
4150 } else {
4151 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4152 retval = DDI_FAILURE;
4153 }
4154 #else
4155 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4156 RECEIVE_MODE_KEEP_VLAN_TAG))
4157 retval = DDI_FAILURE;
4158 #endif
4159
4160 /*
4161 * Step 91: disable auto-polling of PHY status
4162 */
4163 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4164
4165 /*
4166 * Step 92: configure D0 power state (not required)
4167 * Step 93: initialise LED control register ()
4168 */
4169 ledctl = LED_CONTROL_DEFAULT;
4170 switch (bgep->chipid.device) {
4171 case DEVICE_ID_5700:
4172 case DEVICE_ID_5700x:
4173 case DEVICE_ID_5701:
4174 /*
4175 * Switch to 5700 (MAC) mode on these older chips
4176 */
4177 ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4178 ledctl |= LED_CONTROL_LED_MODE_5700;
4179 break;
4180
4181 default:
4182 break;
4183 }
4184 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4185
4186 /*
4187 * Step 94: activate link
4188 */
4189 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4190
4191 /*
4192 * Step 95: set up physical layer (PHY/SerDes)
4193 * restart autoneg (if required)
4194 */
4195 if (reset_phys)
4196 if (bge_phys_update(bgep) == DDI_FAILURE)
4197 retval = DDI_FAILURE;
4198
4199 /*
4200 * Extra step (DSG): hand over all the Receive Buffers to the chip
4201 */
4202 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4203 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4204 bgep->buff[ring].rf_next);
4205
4206 /*
4207 * MSI bits:The least significant MSI 16-bit word.
4208 * ISR will be triggered different.
4209 */
4210 if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4211 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4212
4213 /*
4214 * Extra step (DSG): select which interrupts are enabled
4215 *
4216 * Program the Ethernet MAC engine to signal attention on
4217 * Link Change events, then enable interrupts on MAC, DMA,
4218 * and FLOW attention signals.
4219 */
4220 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4221 ETHERNET_EVENT_LINK_INT |
4222 ETHERNET_STATUS_PCS_ERROR_INT);
4223 #ifdef BGE_IPMI_ASF
4224 if (bgep->asf_enabled) {
4225 bge_reg_set32(bgep, MODE_CONTROL_REG,
4226 MODE_INT_ON_FLOW_ATTN |
4227 MODE_INT_ON_DMA_ATTN |
4228 MODE_HOST_STACK_UP|
4229 MODE_INT_ON_MAC_ATTN);
4230 } else {
4231 #endif
4232 bge_reg_set32(bgep, MODE_CONTROL_REG,
4233 MODE_INT_ON_FLOW_ATTN |
4234 MODE_INT_ON_DMA_ATTN |
4235 MODE_INT_ON_MAC_ATTN);
4236 #ifdef BGE_IPMI_ASF
4237 }
4238 #endif
4239
4240 /*
4241 * Step 97: enable PCI interrupts!!!
4242 */
4243 if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4244 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4245 bgep->chipid.mask_pci_int);
4246
4247 /*
4248 * All done!
4249 */
4250 bgep->bge_chip_state = BGE_CHIP_RUNNING;
4251 return (retval);
4252 }
4253
4254
4255 /*
4256 * ========== Hardware interrupt handler ==========
4257 */
4258
4259 #undef BGE_DBG
4260 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */
4261
4262 /*
4263 * Sync the status block, then atomically clear the specified bits in
4264 * the <flags-and-tag> field of the status block.
4265 * the <flags> word of the status block, returning the value of the
4266 * <tag> and the <flags> before the bits were cleared.
4267 */
4268 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4269 #pragma inline(bge_status_sync)
4270
4271 static int
4272 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4273 {
4274 bge_status_t *bsp;
4275 int retval;
4276
4277 BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4278 (void *)bgep, bits));
4279
4280 ASSERT(bgep->bge_guard == BGE_GUARD);
4281
4282 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4283 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4284 if (retval != DDI_FM_OK)
4285 return (retval);
4286
4287 bsp = DMA_VPTR(bgep->status_block);
4288 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4289
4290 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4291 (void *)bgep, bits, *flags));
4292
4293 return (retval);
4294 }
4295
4296 void bge_wake_factotum(bge_t *bgep);
4297 #pragma inline(bge_wake_factotum)
4298
4299 void
4300 bge_wake_factotum(bge_t *bgep)
4301 {
4302 mutex_enter(bgep->softintrlock);
4303 if (bgep->factotum_flag == 0) {
4304 bgep->factotum_flag = 1;
4305 ddi_trigger_softintr(bgep->factotum_id);
4306 }
4307 mutex_exit(bgep->softintrlock);
4308 }
4309
4310 /*
4311 * bge_intr() -- handle chip interrupts
4312 */
4313 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
4314 #pragma no_inline(bge_intr)
4315
4316 uint_t
4317 bge_intr(caddr_t arg1, caddr_t arg2)
4318 {
4319 bge_t *bgep = (void *)arg1; /* private device info */
4320 bge_status_t *bsp;
4321 uint64_t flags;
4322 uint32_t regval;
4323 uint_t result;
4324 int retval, loop_cnt = 0;
4325
4326 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
4327
4328 /*
4329 * GLD v2 checks that s/w setup is complete before passing
4330 * interrupts to this routine, thus eliminating the old
4331 * (and well-known) race condition around ddi_add_intr()
4332 */
4333 ASSERT(bgep->progress & PROGRESS_HWINT);
4334
4335 result = DDI_INTR_UNCLAIMED;
4336 mutex_enter(bgep->genlock);
4337
4338 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4339 /*
4340 * Check whether chip's says it's asserting #INTA;
4341 * if not, don't process or claim the interrupt.
4342 *
4343 * Note that the PCI signal is active low, so the
4344 * bit is *zero* when the interrupt is asserted.
4345 */
4346 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
4347 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) &&
4348 (regval & MLCR_INTA_STATE)) {
4349 if (bge_check_acc_handle(bgep, bgep->io_handle)
4350 != DDI_FM_OK)
4351 goto chip_stop;
4352 mutex_exit(bgep->genlock);
4353 return (result);
4354 }
4355
4356 /*
4357 * Block further PCI interrupts ...
4358 */
4359 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4360 bgep->chipid.mask_pci_int);
4361
4362 } else {
4363 /*
4364 * Check MSI status
4365 */
4366 regval = bge_reg_get32(bgep, MSI_STATUS_REG);
4367 if (regval & MSI_ERROR_ATTENTION) {
4368 BGE_REPORT((bgep, "msi error attention,"
4369 " status=0x%x", regval));
4370 bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4371 }
4372 }
4373
4374 result = DDI_INTR_CLAIMED;
4375
4376 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
4377
4378 /*
4379 * Sync the status block and grab the flags-n-tag from it.
4380 * We count the number of interrupts where there doesn't
4381 * seem to have been a DMA update of the status block; if
4382 * it *has* been updated, the counter will be cleared in
4383 * the while() loop below ...
4384 */
4385 bgep->missed_dmas += 1;
4386 bsp = DMA_VPTR(bgep->status_block);
4387 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
4388 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
4389 /*
4390 * bge_chip_stop() may have freed dma area etc
4391 * while we were in this interrupt handler -
4392 * better not call bge_status_sync()
4393 */
4394 (void) bge_check_acc_handle(bgep,
4395 bgep->io_handle);
4396 mutex_exit(bgep->genlock);
4397 return (DDI_INTR_CLAIMED);
4398 }
4399 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4400 &flags);
4401 if (retval != DDI_FM_OK) {
4402 bgep->bge_dma_error = B_TRUE;
4403 goto chip_stop;
4404 }
4405
4406 if (!(flags & STATUS_FLAG_UPDATED))
4407 break;
4408
4409 /*
4410 * Tell the chip that we're processing the interrupt
4411 */
4412 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4413 INTERRUPT_MBOX_DISABLE(flags));
4414 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4415 DDI_FM_OK)
4416 goto chip_stop;
4417
4418 /*
4419 * Drop the mutex while we:
4420 * Receive any newly-arrived packets
4421 * Recycle any newly-finished send buffers
4422 */
4423 bgep->bge_intr_running = B_TRUE;
4424 mutex_exit(bgep->genlock);
4425 bge_receive(bgep, bsp);
4426 (void) bge_recycle(bgep, bsp);
4427 mutex_enter(bgep->genlock);
4428 bgep->bge_intr_running = B_FALSE;
4429
4430 /*
4431 * Tell the chip we've finished processing, and
4432 * give it the tag that we got from the status
4433 * block earlier, so that it knows just how far
4434 * we've gone. If it's got more for us to do,
4435 * it will now update the status block and try
4436 * to assert an interrupt (but we've got the
4437 * #INTA blocked at present). If we see the
4438 * update, we'll loop around to do some more.
4439 * Eventually we'll get out of here ...
4440 */
4441 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4442 INTERRUPT_MBOX_ENABLE(flags));
4443 if (bgep->chipid.pci_type == BGE_PCI_E)
4444 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4445 bgep->missed_dmas = 0;
4446 }
4447
4448 /*
4449 * Check for exceptional conditions that we need to handle
4450 *
4451 * Link status changed
4452 * Status block not updated
4453 */
4454 if (flags & STATUS_FLAG_LINK_CHANGED)
4455 bge_wake_factotum(bgep);
4456
4457 if (bgep->missed_dmas) {
4458 /*
4459 * Probably due to the internal status tag not
4460 * being reset. Force a status block update now;
4461 * this should ensure that we get an update and
4462 * a new interrupt. After that, we should be in
4463 * sync again ...
4464 */
4465 BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4466 "not updated?", flags));
4467 bgep->missed_updates++;
4468 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4469 COALESCE_NOW);
4470
4471 if (bgep->missed_dmas >= bge_dma_miss_limit) {
4472 /*
4473 * If this happens multiple times in a row,
4474 * it means DMA is just not working. Maybe
4475 * the chip's failed, or maybe there's a
4476 * problem on the PCI bus or in the host-PCI
4477 * bridge (Tomatillo).
4478 *
4479 * At all events, we want to stop further
4480 * interrupts and let the recovery code take
4481 * over to see whether anything can be done
4482 * about it ...
4483 */
4484 bge_fm_ereport(bgep,
4485 DDI_FM_DEVICE_BADINT_LIMIT);
4486 goto chip_stop;
4487 }
4488 }
4489
4490 /*
4491 * Reenable assertion of #INTA, unless there's a DMA fault
4492 */
4493 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4494 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4495 bgep->chipid.mask_pci_int);
4496 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4497 DDI_FM_OK)
4498 goto chip_stop;
4499 }
4500
4501 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4502 goto chip_stop;
4503
4504 mutex_exit(bgep->genlock);
4505 return (result);
4506
4507 chip_stop:
4508 #ifdef BGE_IPMI_ASF
4509 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4510 /*
4511 * We must stop ASF heart beat before
4512 * bge_chip_stop(), otherwise some
4513 * computers (ex. IBM HS20 blade
4514 * server) may crash.
4515 */
4516 bge_asf_update_status(bgep);
4517 bge_asf_stop_timer(bgep);
4518 bgep->asf_status = ASF_STAT_STOP;
4519
4520 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4521 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4522 }
4523 #endif
4524 bge_chip_stop(bgep, B_TRUE);
4525 (void) bge_check_acc_handle(bgep, bgep->io_handle);
4526 mutex_exit(bgep->genlock);
4527 return (result);
4528 }
4529
4530 /*
4531 * ========== Factotum, implemented as a softint handler ==========
4532 */
4533
4534 #undef BGE_DBG
4535 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */
4536
4537 static void bge_factotum_error_handler(bge_t *bgep);
4538 #pragma no_inline(bge_factotum_error_handler)
4539
4540 static void
4541 bge_factotum_error_handler(bge_t *bgep)
4542 {
4543 uint32_t flow;
4544 uint32_t rdma;
4545 uint32_t wdma;
4546 uint32_t tmac;
4547 uint32_t rmac;
4548 uint32_t rxrs;
4549 uint32_t txrs = 0;
4550
4551 ASSERT(mutex_owned(bgep->genlock));
4552
4553 /*
4554 * Read all the registers that show the possible
4555 * reasons for the ERROR bit to be asserted
4556 */
4557 flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4558 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4559 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4560 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4561 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4562 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4563 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4564 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4565
4566 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4567 (void *)bgep, flow, rdma, wdma));
4568 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4569 (void *)bgep, tmac, rmac, rxrs, txrs));
4570
4571 /*
4572 * For now, just clear all the errors ...
4573 */
4574 if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4575 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4576 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4577 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4578 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4579 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4580 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4581 }
4582
4583 /*
4584 * Handler for hardware link state change.
4585 *
4586 * When this routine is called, the hardware link state has changed
4587 * and the new state is reflected in the param_* variables. Here
4588 * we must update the softstate and reprogram the MAC to match.
4589 */
4590 static void bge_factotum_link_handler(bge_t *bgep);
4591 #pragma no_inline(bge_factotum_link_handler)
4592
4593 static void
4594 bge_factotum_link_handler(bge_t *bgep)
4595 {
4596 ASSERT(mutex_owned(bgep->genlock));
4597
4598 /*
4599 * Update the s/w link_state
4600 */
4601 if (bgep->param_link_up)
4602 bgep->link_state = LINK_STATE_UP;
4603 else
4604 bgep->link_state = LINK_STATE_DOWN;
4605
4606 /*
4607 * Reprogram the MAC modes to match
4608 */
4609 bge_sync_mac_modes(bgep);
4610 }
4611
4612 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4613 #pragma no_inline(bge_factotum_link_check)
4614
4615 static boolean_t
4616 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4617 {
4618 boolean_t check;
4619 uint64_t flags;
4620 uint32_t tmac_status;
4621
4622 ASSERT(mutex_owned(bgep->genlock));
4623
4624 /*
4625 * Get & clear the writable status bits in the Tx status register
4626 * (some bits are write-1-to-clear, others are just readonly).
4627 */
4628 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4629 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4630
4631 /*
4632 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4633 */
4634 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4635 STATUS_FLAG_LINK_CHANGED, &flags);
4636 if (*dma_state != DDI_FM_OK)
4637 return (B_FALSE);
4638
4639 /*
4640 * Clear any errors flagged in the status block ...
4641 */
4642 if (flags & STATUS_FLAG_ERROR)
4643 bge_factotum_error_handler(bgep);
4644
4645 /*
4646 * We need to check the link status if:
4647 * the status block says there's been a link change
4648 * or there's any discrepancy between the various
4649 * flags indicating the link state (link_state,
4650 * param_link_up, and the LINK STATE bit in the
4651 * Transmit MAC status register).
4652 */
4653 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4654 switch (bgep->link_state) {
4655 case LINK_STATE_UP:
4656 check |= (bgep->param_link_up == B_FALSE);
4657 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4658 break;
4659
4660 case LINK_STATE_DOWN:
4661 check |= (bgep->param_link_up != B_FALSE);
4662 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4663 break;
4664
4665 default:
4666 check = B_TRUE;
4667 break;
4668 }
4669
4670 /*
4671 * If <check> is false, we're sure the link hasn't changed.
4672 * If true, however, it's not yet definitive; we have to call
4673 * bge_phys_check() to determine whether the link has settled
4674 * into a new state yet ... and if it has, then call the link
4675 * state change handler.But when the chip is 5700 in Dell 6650
4676 * ,even if check is false, the link may have changed.So we
4677 * have to call bge_phys_check() to determine the link state.
4678 */
4679 if (check || bgep->chipid.device == DEVICE_ID_5700) {
4680 check = bge_phys_check(bgep);
4681 if (check)
4682 bge_factotum_link_handler(bgep);
4683 }
4684
4685 return (check);
4686 }
4687
4688 /*
4689 * Factotum routine to check for Tx stall, using the 'watchdog' counter
4690 */
4691 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4692 #pragma no_inline(bge_factotum_stall_check)
4693
4694 static boolean_t
4695 bge_factotum_stall_check(bge_t *bgep)
4696 {
4697 uint32_t dogval;
4698 bge_status_t *bsp;
4699 uint64_t now = gethrtime();
4700
4701 if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
4702 return (B_FALSE);
4703
4704 bgep->timestamp = now;
4705
4706 ASSERT(mutex_owned(bgep->genlock));
4707
4708 /*
4709 * Specific check for Tx stall ...
4710 *
4711 * The 'watchdog' counter is incremented whenever a packet
4712 * is queued, reset to 1 when some (but not all) buffers
4713 * are reclaimed, reset to 0 (disabled) when all buffers
4714 * are reclaimed, and shifted left here. If it exceeds the
4715 * threshold value, the chip is assumed to have stalled and
4716 * is put into the ERROR state. The factotum will then reset
4717 * it on the next pass.
4718 *
4719 * All of which should ensure that we don't get into a state
4720 * where packets are left pending indefinitely!
4721 */
4722 dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4723 bsp = DMA_VPTR(bgep->status_block);
4724 if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
4725 return (B_FALSE);
4726
4727 #if !defined(BGE_NETCONSOLE)
4728 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4729 #endif
4730 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4731 return (B_TRUE);
4732 }
4733
4734 /*
4735 * The factotum is woken up when there's something to do that we'd rather
4736 * not do from inside a hardware interrupt handler or high-level cyclic.
4737 * Its two main tasks are:
4738 * reset & restart the chip after an error
4739 * check the link status whenever necessary
4740 */
4741 uint_t bge_chip_factotum(caddr_t arg);
4742 #pragma no_inline(bge_chip_factotum)
4743
4744 uint_t
4745 bge_chip_factotum(caddr_t arg)
4746 {
4747 bge_t *bgep;
4748 uint_t result;
4749 boolean_t error;
4750 boolean_t linkchg;
4751 int dma_state;
4752
4753 bgep = (void *)arg;
4754
4755 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4756
4757 mutex_enter(bgep->softintrlock);
4758 if (bgep->factotum_flag == 0) {
4759 mutex_exit(bgep->softintrlock);
4760 return (DDI_INTR_UNCLAIMED);
4761 }
4762 bgep->factotum_flag = 0;
4763 mutex_exit(bgep->softintrlock);
4764
4765 result = DDI_INTR_CLAIMED;
4766 error = B_FALSE;
4767 linkchg = B_FALSE;
4768
4769 mutex_enter(bgep->genlock);
4770 switch (bgep->bge_chip_state) {
4771 default:
4772 break;
4773
4774 case BGE_CHIP_RUNNING:
4775 linkchg = bge_factotum_link_check(bgep, &dma_state);
4776 error = bge_factotum_stall_check(bgep);
4777 if (dma_state != DDI_FM_OK) {
4778 bgep->bge_dma_error = B_TRUE;
4779 error = B_TRUE;
4780 }
4781 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4782 error = B_TRUE;
4783 if (error)
4784 bgep->bge_chip_state = BGE_CHIP_ERROR;
4785 break;
4786
4787 case BGE_CHIP_ERROR:
4788 error = B_TRUE;
4789 break;
4790
4791 case BGE_CHIP_FAULT:
4792 /*
4793 * Fault detected, time to reset ...
4794 */
4795 if (bge_autorecover) {
4796 if (!(bgep->progress & PROGRESS_BUFS)) {
4797 /*
4798 * if we can't allocate the ring buffers,
4799 * try later
4800 */
4801 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4802 mutex_exit(bgep->genlock);
4803 return (result);
4804 }
4805 bgep->progress |= PROGRESS_BUFS;
4806 }
4807 if (!(bgep->progress & PROGRESS_INTR)) {
4808 bge_init_rings(bgep);
4809 bge_intr_enable(bgep);
4810 bgep->progress |= PROGRESS_INTR;
4811 }
4812 if (!(bgep->progress & PROGRESS_KSTATS)) {
4813 bge_init_kstats(bgep,
4814 ddi_get_instance(bgep->devinfo));
4815 bgep->progress |= PROGRESS_KSTATS;
4816 }
4817
4818 BGE_REPORT((bgep, "automatic recovery activated"));
4819
4820 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4821 bgep->bge_chip_state = BGE_CHIP_ERROR;
4822 error = B_TRUE;
4823 }
4824 if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4825 DDI_FM_OK) {
4826 bgep->bge_chip_state = BGE_CHIP_ERROR;
4827 error = B_TRUE;
4828 }
4829 if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4830 DDI_FM_OK) {
4831 bgep->bge_chip_state = BGE_CHIP_ERROR;
4832 error = B_TRUE;
4833 }
4834 if (error == B_FALSE) {
4835 #ifdef BGE_IPMI_ASF
4836 if (bgep->asf_enabled &&
4837 bgep->asf_status != ASF_STAT_RUN) {
4838 bgep->asf_timeout_id = timeout(
4839 bge_asf_heartbeat, (void *)bgep,
4840 drv_usectohz(
4841 BGE_ASF_HEARTBEAT_INTERVAL));
4842 bgep->asf_status = ASF_STAT_RUN;
4843 }
4844 #endif
4845 if (!bgep->manual_reset) {
4846 ddi_fm_service_impact(bgep->devinfo,
4847 DDI_SERVICE_RESTORED);
4848 }
4849 }
4850 }
4851 break;
4852 }
4853
4854
4855 /*
4856 * If an error is detected, stop the chip now, marking it as
4857 * faulty, so that it will be reset next time through ...
4858 *
4859 * Note that if intr_running is set, then bge_intr() has dropped
4860 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4861 * this point so have to wait until the next time the factotum runs.
4862 */
4863 if (error && !bgep->bge_intr_running) {
4864 #ifdef BGE_IPMI_ASF
4865 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4866 /*
4867 * We must stop ASF heart beat before bge_chip_stop(),
4868 * otherwise some computers (ex. IBM HS20 blade server)
4869 * may crash.
4870 */
4871 bge_asf_update_status(bgep);
4872 bge_asf_stop_timer(bgep);
4873 bgep->asf_status = ASF_STAT_STOP;
4874
4875 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4876 (void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4877 }
4878 #endif
4879 bge_chip_stop(bgep, B_TRUE);
4880 (void) bge_check_acc_handle(bgep, bgep->io_handle);
4881 }
4882 mutex_exit(bgep->genlock);
4883
4884 /*
4885 * If the link state changed, tell the world about it.
4886 * Note: can't do this while still holding the mutex.
4887 */
4888 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4889 bgep->link_state != LINK_STATE_UNKNOWN)
4890 linkchg = B_TRUE;
4891 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4892 bgep->link_state == LINK_STATE_DOWN)
4893 linkchg = B_FALSE;
4894
4895 if (linkchg) {
4896 mac_link_update(bgep->mh, bgep->link_state);
4897 bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4898 }
4899 if (bgep->manual_reset) {
4900 bgep->manual_reset = B_FALSE;
4901 }
4902
4903 return (result);
4904 }
4905
4906 /*
4907 * High-level cyclic handler
4908 *
4909 * This routine schedules a (low-level) softint callback to the
4910 * factotum, and prods the chip to update the status block (which
4911 * will cause a hardware interrupt when complete).
4912 */
4913 void bge_chip_cyclic(void *arg);
4914 #pragma no_inline(bge_chip_cyclic)
4915
4916 void
4917 bge_chip_cyclic(void *arg)
4918 {
4919 bge_t *bgep;
4920
4921 bgep = arg;
4922
4923 switch (bgep->bge_chip_state) {
4924 default:
4925 return;
4926
4927 case BGE_CHIP_RUNNING:
4928 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4929 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4930 ddi_fm_service_impact(bgep->devinfo,
4931 DDI_SERVICE_UNAFFECTED);
4932
4933 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4934 bgep->link_update_timer++;
4935
4936 break;
4937
4938 case BGE_CHIP_FAULT:
4939 case BGE_CHIP_ERROR:
4940 break;
4941 }
4942
4943 bge_wake_factotum(bgep);
4944 }
4945
4946
4947 /*
4948 * ========== Ioctl subfunctions ==========
4949 */
4950
4951 #undef BGE_DBG
4952 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */
4953
4954 #if BGE_DEBUGGING || BGE_DO_PPIO
4955
4956 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4957 #pragma no_inline(bge_chip_peek_cfg)
4958
4959 static void
4960 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4961 {
4962 uint64_t regval;
4963 uint64_t regno;
4964
4965 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4966 (void *)bgep, (void *)ppd));
4967
4968 regno = ppd->pp_acc_offset;
4969
4970 switch (ppd->pp_acc_size) {
4971 case 1:
4972 regval = pci_config_get8(bgep->cfg_handle, regno);
4973 break;
4974
4975 case 2:
4976 regval = pci_config_get16(bgep->cfg_handle, regno);
4977 break;
4978
4979 case 4:
4980 regval = pci_config_get32(bgep->cfg_handle, regno);
4981 break;
4982
4983 case 8:
4984 regval = pci_config_get64(bgep->cfg_handle, regno);
4985 break;
4986 }
4987
4988 ppd->pp_acc_data = regval;
4989 }
4990
4991 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4992 #pragma no_inline(bge_chip_poke_cfg)
4993
4994 static void
4995 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4996 {
4997 uint64_t regval;
4998 uint64_t regno;
4999
5000 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
5001 (void *)bgep, (void *)ppd));
5002
5003 regno = ppd->pp_acc_offset;
5004 regval = ppd->pp_acc_data;
5005
5006 switch (ppd->pp_acc_size) {
5007 case 1:
5008 pci_config_put8(bgep->cfg_handle, regno, regval);
5009 break;
5010
5011 case 2:
5012 pci_config_put16(bgep->cfg_handle, regno, regval);
5013 break;
5014
5015 case 4:
5016 pci_config_put32(bgep->cfg_handle, regno, regval);
5017 break;
5018
5019 case 8:
5020 pci_config_put64(bgep->cfg_handle, regno, regval);
5021 break;
5022 }
5023 }
5024
5025 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5026 #pragma no_inline(bge_chip_peek_reg)
5027
5028 static void
5029 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5030 {
5031 uint64_t regval;
5032 void *regaddr;
5033
5034 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5035 (void *)bgep, (void *)ppd));
5036
5037 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5038
5039 switch (ppd->pp_acc_size) {
5040 case 1:
5041 regval = ddi_get8(bgep->io_handle, regaddr);
5042 break;
5043
5044 case 2:
5045 regval = ddi_get16(bgep->io_handle, regaddr);
5046 break;
5047
5048 case 4:
5049 regval = ddi_get32(bgep->io_handle, regaddr);
5050 break;
5051
5052 case 8:
5053 regval = ddi_get64(bgep->io_handle, regaddr);
5054 break;
5055 }
5056
5057 ppd->pp_acc_data = regval;
5058 }
5059
5060 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5061 #pragma no_inline(bge_chip_peek_reg)
5062
5063 static void
5064 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5065 {
5066 uint64_t regval;
5067 void *regaddr;
5068
5069 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5070 (void *)bgep, (void *)ppd));
5071
5072 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5073 regval = ppd->pp_acc_data;
5074
5075 switch (ppd->pp_acc_size) {
5076 case 1:
5077 ddi_put8(bgep->io_handle, regaddr, regval);
5078 break;
5079
5080 case 2:
5081 ddi_put16(bgep->io_handle, regaddr, regval);
5082 break;
5083
5084 case 4:
5085 ddi_put32(bgep->io_handle, regaddr, regval);
5086 break;
5087
5088 case 8:
5089 ddi_put64(bgep->io_handle, regaddr, regval);
5090 break;
5091 }
5092 BGE_PCICHK(bgep);
5093 }
5094
5095 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5096 #pragma no_inline(bge_chip_peek_nic)
5097
5098 static void
5099 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5100 {
5101 uint64_t regoff;
5102 uint64_t regval;
5103 void *regaddr;
5104
5105 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5106 (void *)bgep, (void *)ppd));
5107
5108 regoff = ppd->pp_acc_offset;
5109 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5110 regoff &= MWBAR_GRANULE_MASK;
5111 regoff += NIC_MEM_WINDOW_OFFSET;
5112 regaddr = PIO_ADDR(bgep, regoff);
5113
5114 switch (ppd->pp_acc_size) {
5115 case 1:
5116 regval = ddi_get8(bgep->io_handle, regaddr);
5117 break;
5118
5119 case 2:
5120 regval = ddi_get16(bgep->io_handle, regaddr);
5121 break;
5122
5123 case 4:
5124 regval = ddi_get32(bgep->io_handle, regaddr);
5125 break;
5126
5127 case 8:
5128 regval = ddi_get64(bgep->io_handle, regaddr);
5129 break;
5130 }
5131
5132 ppd->pp_acc_data = regval;
5133 }
5134
5135 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5136 #pragma no_inline(bge_chip_poke_nic)
5137
5138 static void
5139 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5140 {
5141 uint64_t regoff;
5142 uint64_t regval;
5143 void *regaddr;
5144
5145 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5146 (void *)bgep, (void *)ppd));
5147
5148 regoff = ppd->pp_acc_offset;
5149 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5150 regoff &= MWBAR_GRANULE_MASK;
5151 regoff += NIC_MEM_WINDOW_OFFSET;
5152 regaddr = PIO_ADDR(bgep, regoff);
5153 regval = ppd->pp_acc_data;
5154
5155 switch (ppd->pp_acc_size) {
5156 case 1:
5157 ddi_put8(bgep->io_handle, regaddr, regval);
5158 break;
5159
5160 case 2:
5161 ddi_put16(bgep->io_handle, regaddr, regval);
5162 break;
5163
5164 case 4:
5165 ddi_put32(bgep->io_handle, regaddr, regval);
5166 break;
5167
5168 case 8:
5169 ddi_put64(bgep->io_handle, regaddr, regval);
5170 break;
5171 }
5172 BGE_PCICHK(bgep);
5173 }
5174
5175 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5176 #pragma no_inline(bge_chip_peek_mii)
5177
5178 static void
5179 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5180 {
5181 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5182 (void *)bgep, (void *)ppd));
5183
5184 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5185 }
5186
5187 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5188 #pragma no_inline(bge_chip_poke_mii)
5189
5190 static void
5191 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5192 {
5193 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5194 (void *)bgep, (void *)ppd));
5195
5196 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5197 }
5198
5199 #if BGE_SEE_IO32
5200
5201 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5202 #pragma no_inline(bge_chip_peek_seeprom)
5203
5204 static void
5205 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5206 {
5207 uint32_t data;
5208 int err;
5209
5210 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5211 (void *)bgep, (void *)ppd));
5212
5213 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5214 ppd->pp_acc_data = err ? ~0ull : data;
5215 }
5216
5217 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5218 #pragma no_inline(bge_chip_poke_seeprom)
5219
5220 static void
5221 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5222 {
5223 uint32_t data;
5224
5225 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5226 (void *)bgep, (void *)ppd));
5227
5228 data = ppd->pp_acc_data;
5229 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5230 }
5231 #endif /* BGE_SEE_IO32 */
5232
5233 #if BGE_FLASH_IO32
5234
5235 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5236 #pragma no_inline(bge_chip_peek_flash)
5237
5238 static void
5239 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5240 {
5241 uint32_t data;
5242 int err;
5243
5244 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5245 (void *)bgep, (void *)ppd));
5246
5247 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5248 ppd->pp_acc_data = err ? ~0ull : data;
5249 }
5250
5251 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5252 #pragma no_inline(bge_chip_poke_flash)
5253
5254 static void
5255 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5256 {
5257 uint32_t data;
5258
5259 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5260 (void *)bgep, (void *)ppd));
5261
5262 data = ppd->pp_acc_data;
5263 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5264 ppd->pp_acc_offset, &data);
5265 }
5266 #endif /* BGE_FLASH_IO32 */
5267
5268 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5269 #pragma no_inline(bge_chip_peek_mem)
5270
5271 static void
5272 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5273 {
5274 uint64_t regval;
5275 void *vaddr;
5276
5277 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5278 (void *)bgep, (void *)ppd));
5279
5280 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5281
5282 switch (ppd->pp_acc_size) {
5283 case 1:
5284 regval = *(uint8_t *)vaddr;
5285 break;
5286
5287 case 2:
5288 regval = *(uint16_t *)vaddr;
5289 break;
5290
5291 case 4:
5292 regval = *(uint32_t *)vaddr;
5293 break;
5294
5295 case 8:
5296 regval = *(uint64_t *)vaddr;
5297 break;
5298 }
5299
5300 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5301 (void *)bgep, (void *)ppd, regval, vaddr));
5302
5303 ppd->pp_acc_data = regval;
5304 }
5305
5306 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5307 #pragma no_inline(bge_chip_poke_mem)
5308
5309 static void
5310 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5311 {
5312 uint64_t regval;
5313 void *vaddr;
5314
5315 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5316 (void *)bgep, (void *)ppd));
5317
5318 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5319 regval = ppd->pp_acc_data;
5320
5321 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5322 (void *)bgep, (void *)ppd, regval, vaddr));
5323
5324 switch (ppd->pp_acc_size) {
5325 case 1:
5326 *(uint8_t *)vaddr = (uint8_t)regval;
5327 break;
5328
5329 case 2:
5330 *(uint16_t *)vaddr = (uint16_t)regval;
5331 break;
5332
5333 case 4:
5334 *(uint32_t *)vaddr = (uint32_t)regval;
5335 break;
5336
5337 case 8:
5338 *(uint64_t *)vaddr = (uint64_t)regval;
5339 break;
5340 }
5341 }
5342
5343 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5344 struct iocblk *iocp);
5345 #pragma no_inline(bge_pp_ioctl)
5346
5347 static enum ioc_reply
5348 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5349 {
5350 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5351 bge_peekpoke_t *ppd;
5352 dma_area_t *areap;
5353 uint64_t sizemask;
5354 uint64_t mem_va;
5355 uint64_t maxoff;
5356 boolean_t peek;
5357
5358 switch (cmd) {
5359 default:
5360 /* NOTREACHED */
5361 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5362 return (IOC_INVAL);
5363
5364 case BGE_PEEK:
5365 peek = B_TRUE;
5366 break;
5367
5368 case BGE_POKE:
5369 peek = B_FALSE;
5370 break;
5371 }
5372
5373 /*
5374 * Validate format of ioctl
5375 */
5376 if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5377 return (IOC_INVAL);
5378 if (mp->b_cont == NULL)
5379 return (IOC_INVAL);
5380 ppd = (void *)mp->b_cont->b_rptr;
5381
5382 /*
5383 * Validate request parameters
5384 */
5385 switch (ppd->pp_acc_space) {
5386 default:
5387 return (IOC_INVAL);
5388
5389 case BGE_PP_SPACE_CFG:
5390 /*
5391 * Config space
5392 */
5393 sizemask = 8|4|2|1;
5394 mem_va = 0;
5395 maxoff = PCI_CONF_HDR_SIZE;
5396 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5397 break;
5398
5399 case BGE_PP_SPACE_REG:
5400 /*
5401 * Memory-mapped I/O space
5402 */
5403 sizemask = 8|4|2|1;
5404 mem_va = 0;
5405 maxoff = RIAAR_REGISTER_MAX;
5406 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5407 break;
5408
5409 case BGE_PP_SPACE_NIC:
5410 /*
5411 * NIC on-chip memory
5412 */
5413 sizemask = 8|4|2|1;
5414 mem_va = 0;
5415 maxoff = MWBAR_ONCHIP_MAX;
5416 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5417 break;
5418
5419 case BGE_PP_SPACE_MII:
5420 /*
5421 * PHY's MII registers
5422 * NB: all PHY registers are two bytes, but the
5423 * addresses increment in ones (word addressing).
5424 * So we scale the address here, then undo the
5425 * transformation inside the peek/poke functions.
5426 */
5427 ppd->pp_acc_offset *= 2;
5428 sizemask = 2;
5429 mem_va = 0;
5430 maxoff = (MII_MAXREG+1)*2;
5431 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5432 break;
5433
5434 #if BGE_SEE_IO32
5435 case BGE_PP_SPACE_SEEPROM:
5436 /*
5437 * Attached SEEPROM(s), if any.
5438 * NB: we use the high-order bits of the 'address' as
5439 * a device select to accommodate multiple SEEPROMS,
5440 * If each one is the maximum size (64kbytes), this
5441 * makes them appear contiguous. Otherwise, there may
5442 * be holes in the mapping. ENxS doesn't have any
5443 * SEEPROMs anyway ...
5444 */
5445 sizemask = 4;
5446 mem_va = 0;
5447 maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5448 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5449 break;
5450 #endif /* BGE_SEE_IO32 */
5451
5452 #if BGE_FLASH_IO32
5453 case BGE_PP_SPACE_FLASH:
5454 /*
5455 * Attached Flash device (if any); a maximum of one device
5456 * is currently supported. But it can be up to 1MB (unlike
5457 * the 64k limit on SEEPROMs) so why would you need more ;-)
5458 */
5459 sizemask = 4;
5460 mem_va = 0;
5461 maxoff = NVM_FLASH_ADDR_MASK;
5462 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5463 break;
5464 #endif /* BGE_FLASH_IO32 */
5465
5466 case BGE_PP_SPACE_BGE:
5467 /*
5468 * BGE data structure!
5469 */
5470 sizemask = 8|4|2|1;
5471 mem_va = (uintptr_t)bgep;
5472 maxoff = sizeof (*bgep);
5473 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5474 break;
5475
5476 case BGE_PP_SPACE_STATUS:
5477 case BGE_PP_SPACE_STATISTICS:
5478 case BGE_PP_SPACE_TXDESC:
5479 case BGE_PP_SPACE_TXBUFF:
5480 case BGE_PP_SPACE_RXDESC:
5481 case BGE_PP_SPACE_RXBUFF:
5482 /*
5483 * Various DMA_AREAs
5484 */
5485 switch (ppd->pp_acc_space) {
5486 case BGE_PP_SPACE_TXDESC:
5487 areap = &bgep->tx_desc;
5488 break;
5489 case BGE_PP_SPACE_TXBUFF:
5490 areap = &bgep->tx_buff[0];
5491 break;
5492 case BGE_PP_SPACE_RXDESC:
5493 areap = &bgep->rx_desc[0];
5494 break;
5495 case BGE_PP_SPACE_RXBUFF:
5496 areap = &bgep->rx_buff[0];
5497 break;
5498 case BGE_PP_SPACE_STATUS:
5499 areap = &bgep->status_block;
5500 break;
5501 case BGE_PP_SPACE_STATISTICS:
5502 if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5503 areap = &bgep->statistics;
5504 break;
5505 }
5506
5507 sizemask = 8|4|2|1;
5508 mem_va = (uintptr_t)areap->mem_va;
5509 maxoff = areap->alength;
5510 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5511 break;
5512 }
5513
5514 switch (ppd->pp_acc_size) {
5515 default:
5516 return (IOC_INVAL);
5517
5518 case 8:
5519 case 4:
5520 case 2:
5521 case 1:
5522 if ((ppd->pp_acc_size & sizemask) == 0)
5523 return (IOC_INVAL);
5524 break;
5525 }
5526
5527 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5528 return (IOC_INVAL);
5529
5530 if (ppd->pp_acc_offset >= maxoff)
5531 return (IOC_INVAL);
5532
5533 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5534 return (IOC_INVAL);
5535
5536 /*
5537 * All OK - go do it!
5538 */
5539 ppd->pp_acc_offset += mem_va;
5540 (*ppfn)(bgep, ppd);
5541 return (peek ? IOC_REPLY : IOC_ACK);
5542 }
5543
5544 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5545 struct iocblk *iocp);
5546 #pragma no_inline(bge_diag_ioctl)
5547
5548 static enum ioc_reply
5549 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5550 {
5551 ASSERT(mutex_owned(bgep->genlock));
5552
5553 switch (cmd) {
5554 default:
5555 /* NOTREACHED */
5556 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5557 return (IOC_INVAL);
5558
5559 case BGE_DIAG:
5560 /*
5561 * Currently a no-op
5562 */
5563 return (IOC_ACK);
5564
5565 case BGE_PEEK:
5566 case BGE_POKE:
5567 return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5568
5569 case BGE_PHY_RESET:
5570 return (IOC_RESTART_ACK);
5571
5572 case BGE_SOFT_RESET:
5573 case BGE_HARD_RESET:
5574 /*
5575 * Reset and reinitialise the 570x hardware
5576 */
5577 bgep->bge_chip_state = BGE_CHIP_FAULT;
5578 ddi_trigger_softintr(bgep->factotum_id);
5579 (void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5580 return (IOC_ACK);
5581 }
5582
5583 /* NOTREACHED */
5584 }
5585
5586 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
5587
5588 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5589 struct iocblk *iocp);
5590 #pragma no_inline(bge_mii_ioctl)
5591
5592 static enum ioc_reply
5593 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5594 {
5595 struct bge_mii_rw *miirwp;
5596
5597 /*
5598 * Validate format of ioctl
5599 */
5600 if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5601 return (IOC_INVAL);
5602 if (mp->b_cont == NULL)
5603 return (IOC_INVAL);
5604 miirwp = (void *)mp->b_cont->b_rptr;
5605
5606 /*
5607 * Validate request parameters ...
5608 */
5609 if (miirwp->mii_reg > MII_MAXREG)
5610 return (IOC_INVAL);
5611
5612 switch (cmd) {
5613 default:
5614 /* NOTREACHED */
5615 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5616 return (IOC_INVAL);
5617
5618 case BGE_MII_READ:
5619 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5620 return (IOC_REPLY);
5621
5622 case BGE_MII_WRITE:
5623 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5624 return (IOC_ACK);
5625 }
5626
5627 /* NOTREACHED */
5628 }
5629
5630 #if BGE_SEE_IO32
5631
5632 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5633 struct iocblk *iocp);
5634 #pragma no_inline(bge_see_ioctl)
5635
5636 static enum ioc_reply
5637 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5638 {
5639 struct bge_see_rw *seerwp;
5640
5641 /*
5642 * Validate format of ioctl
5643 */
5644 if (iocp->ioc_count != sizeof (struct bge_see_rw))
5645 return (IOC_INVAL);
5646 if (mp->b_cont == NULL)
5647 return (IOC_INVAL);
5648 seerwp = (void *)mp->b_cont->b_rptr;
5649
5650 /*
5651 * Validate request parameters ...
5652 */
5653 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5654 return (IOC_INVAL);
5655
5656 switch (cmd) {
5657 default:
5658 /* NOTREACHED */
5659 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5660 return (IOC_INVAL);
5661
5662 case BGE_SEE_READ:
5663 case BGE_SEE_WRITE:
5664 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5665 seerwp->see_addr, &seerwp->see_data);
5666 return (IOC_REPLY);
5667 }
5668
5669 /* NOTREACHED */
5670 }
5671
5672 #endif /* BGE_SEE_IO32 */
5673
5674 #if BGE_FLASH_IO32
5675
5676 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5677 struct iocblk *iocp);
5678 #pragma no_inline(bge_flash_ioctl)
5679
5680 static enum ioc_reply
5681 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5682 {
5683 struct bge_flash_rw *flashrwp;
5684
5685 /*
5686 * Validate format of ioctl
5687 */
5688 if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5689 return (IOC_INVAL);
5690 if (mp->b_cont == NULL)
5691 return (IOC_INVAL);
5692 flashrwp = (void *)mp->b_cont->b_rptr;
5693
5694 /*
5695 * Validate request parameters ...
5696 */
5697 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5698 return (IOC_INVAL);
5699
5700 switch (cmd) {
5701 default:
5702 /* NOTREACHED */
5703 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5704 return (IOC_INVAL);
5705
5706 case BGE_FLASH_READ:
5707 case BGE_FLASH_WRITE:
5708 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5709 flashrwp->flash_addr, &flashrwp->flash_data);
5710 return (IOC_REPLY);
5711 }
5712
5713 /* NOTREACHED */
5714 }
5715
5716 #endif /* BGE_FLASH_IO32 */
5717
5718 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5719 struct iocblk *iocp);
5720 #pragma no_inline(bge_chip_ioctl)
5721
5722 enum ioc_reply
5723 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5724 {
5725 int cmd;
5726
5727 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5728 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5729
5730 ASSERT(mutex_owned(bgep->genlock));
5731
5732 cmd = iocp->ioc_cmd;
5733 switch (cmd) {
5734 default:
5735 /* NOTREACHED */
5736 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5737 return (IOC_INVAL);
5738
5739 case BGE_DIAG:
5740 case BGE_PEEK:
5741 case BGE_POKE:
5742 case BGE_PHY_RESET:
5743 case BGE_SOFT_RESET:
5744 case BGE_HARD_RESET:
5745 #if BGE_DEBUGGING || BGE_DO_PPIO
5746 return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5747 #else
5748 return (IOC_INVAL);
5749 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */
5750
5751 case BGE_MII_READ:
5752 case BGE_MII_WRITE:
5753 return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5754
5755 #if BGE_SEE_IO32
5756 case BGE_SEE_READ:
5757 case BGE_SEE_WRITE:
5758 return (bge_see_ioctl(bgep, cmd, mp, iocp));
5759 #endif /* BGE_SEE_IO32 */
5760
5761 #if BGE_FLASH_IO32
5762 case BGE_FLASH_READ:
5763 case BGE_FLASH_WRITE:
5764 return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5765 #endif /* BGE_FLASH_IO32 */
5766 }
5767
5768 /* NOTREACHED */
5769 }
5770
5771 /* ARGSUSED */
5772 void
5773 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
5774 {
5775 recv_ring_t *rrp = arg;
5776 bge_t *bgep = rrp->bgep;
5777
5778 mutex_enter(bgep->genlock);
5779 rrp->poll_flag = flag;
5780 #ifdef NOT_YET
5781 /*
5782 * XXX-Sunay: Since most broadcom cards support only one
5783 * interrupt but multiple rx rings, we can't disable the
5784 * physical interrupt. This need to be done via capability
5785 * negotiation depending on the NIC.
5786 */
5787 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5788 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5789 #endif
5790 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5791 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5792 mutex_exit(bgep->genlock);
5793 }
5794
5795 #ifdef BGE_IPMI_ASF
5796
5797 uint32_t
5798 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5799 {
5800 uint32_t data;
5801
5802 #ifndef __sparc
5803 if (!bgep->asf_wordswapped) {
5804 /* a workaround word swap error */
5805 if (addr & 4)
5806 addr = addr - 4;
5807 else
5808 addr = addr + 4;
5809 }
5810 #else
5811 if (DEVICE_5717_SERIES_CHIPSETS(bgep))
5812 addr = LE_32(addr);
5813 #endif
5814
5815 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5816 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5817 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5818
5819 data = LE_32(data);
5820
5821 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
5822 (void *)bgep, addr, data));
5823
5824 return (data);
5825 }
5826
5827 void
5828 bge_asf_update_status(bge_t *bgep)
5829 {
5830 uint32_t event;
5831
5832 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5833 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5834 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3);
5835
5836 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5837 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5838 }
5839
5840
5841 /*
5842 * The driver is supposed to notify ASF that the OS is still running
5843 * every three seconds, otherwise the management server may attempt
5844 * to reboot the machine. If it hasn't actually failed, this is
5845 * not a desirable result. However, this isn't running as a real-time
5846 * thread, and even if it were, it might not be able to generate the
5847 * heartbeat in a timely manner due to system load. As it isn't a
5848 * significant strain on the machine, we will set the interval to half
5849 * of the required value.
5850 */
5851 void
5852 bge_asf_heartbeat(void *arg)
5853 {
5854 bge_t *bgep = (bge_t *)arg;
5855
5856 mutex_enter(bgep->genlock);
5857 bge_asf_update_status((bge_t *)bgep);
5858 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5859 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5860 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5861 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5862 mutex_exit(bgep->genlock);
5863 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5864 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5865 }
5866
5867
5868 void
5869 bge_asf_stop_timer(bge_t *bgep)
5870 {
5871 timeout_id_t tmp_id = 0;
5872
5873 while ((bgep->asf_timeout_id != 0) &&
5874 (tmp_id != bgep->asf_timeout_id)) {
5875 tmp_id = bgep->asf_timeout_id;
5876 (void) untimeout(tmp_id);
5877 }
5878 bgep->asf_timeout_id = 0;
5879 }
5880
5881
5882
5883 /*
5884 * This function should be placed at the earliest position of bge_attach().
5885 */
5886 void
5887 bge_asf_get_config(bge_t *bgep)
5888 {
5889 uint32_t nicsig;
5890 uint32_t niccfg;
5891
5892 bgep->asf_enabled = B_FALSE;
5893 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5894 if (nicsig == BGE_NIC_DATA_SIG) {
5895 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5896 if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5897 /*
5898 * Here, we don't consider BAXTER, because BGE haven't
5899 * supported BAXTER (that is 5752). Also, as I know,
5900 * BAXTER doesn't support ASF feature.
5901 */
5902 bgep->asf_enabled = B_TRUE;
5903 else
5904 bgep->asf_enabled = B_FALSE;
5905 } else
5906 bgep->asf_enabled = B_FALSE;
5907 }
5908
5909
5910 void
5911 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5912 {
5913 uint32_t tries;
5914 uint32_t event;
5915
5916 ASSERT(bgep->asf_enabled);
5917
5918 /* Issues "pause firmware" command and wait for ACK */
5919 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5920 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5921 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5922
5923 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5924 tries = 0;
5925 while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5926 drv_usecwait(1);
5927 tries ++;
5928 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5929 }
5930
5931 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5932 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5933
5934 if (bgep->asf_newhandshake) {
5935 switch (mode) {
5936 case BGE_INIT_RESET:
5937 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5938 BGE_DRV_STATE_START);
5939 break;
5940 case BGE_SHUTDOWN_RESET:
5941 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5942 BGE_DRV_STATE_UNLOAD);
5943 break;
5944 case BGE_SUSPEND_RESET:
5945 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5946 BGE_DRV_STATE_SUSPEND);
5947 break;
5948 default:
5949 break;
5950 }
5951 }
5952 }
5953
5954
5955 void
5956 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5957 {
5958 switch (mode) {
5959 case BGE_INIT_RESET:
5960 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5961 BGE_DRV_STATE_START);
5962 break;
5963 case BGE_SHUTDOWN_RESET:
5964 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5965 BGE_DRV_STATE_UNLOAD);
5966 break;
5967 case BGE_SUSPEND_RESET:
5968 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5969 BGE_DRV_STATE_SUSPEND);
5970 break;
5971 default:
5972 break;
5973 }
5974 }
5975
5976
5977 void
5978 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5979 {
5980 switch (mode) {
5981 case BGE_INIT_RESET:
5982 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5983 BGE_DRV_STATE_START_DONE);
5984 break;
5985 case BGE_SHUTDOWN_RESET:
5986 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5987 BGE_DRV_STATE_UNLOAD_DONE);
5988 break;
5989 default:
5990 break;
5991 }
5992 }
5993
5994 #endif /* BGE_IPMI_ASF */