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--- old/usr/src/uts/common/sys/smbios.h
+++ new/usr/src/uts/common/sys/smbios.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
24 24 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
25 25 * Use is subject to license terms.
26 26 */
27 27
28 28 /*
29 29 * This header file defines the interfaces available from the SMBIOS access
30 30 * library, libsmbios, and an equivalent kernel module. This API can be used
31 31 * to access DMTF SMBIOS data from a device, file, or raw memory buffer.
32 32 *
33 33 * This is NOT a Public interface, and should be considered Unstable, as it is
34 34 * subject to change without notice as the DMTF SMBIOS specification evolves.
35 35 * Therefore, be aware that any program linked with this API in this
36 36 * instance of illumos is almost guaranteed to break in the next release.
37 37 */
38 38
39 39 #ifndef _SYS_SMBIOS_H
40 40 #define _SYS_SMBIOS_H
41 41
42 42 #include <sys/types.h>
43 43
44 44 #ifdef __cplusplus
45 45 extern "C" {
46 46 #endif
47 47
48 48 /*
49 49 * SMBIOS Structure Table Entry Point. See DSP0134 5.2.1 for more information.
50 50 * The structure table entry point is located by searching for the anchor.
51 51 */
52 52 #pragma pack(1)
53 53
54 54 typedef struct smbios_entry {
55 55 char smbe_eanchor[4]; /* anchor tag (SMB_ENTRY_EANCHOR) */
56 56 uint8_t smbe_ecksum; /* checksum of entry point structure */
57 57 uint8_t smbe_elen; /* length in bytes of entry point */
58 58 uint8_t smbe_major; /* major version of the SMBIOS spec */
59 59 uint8_t smbe_minor; /* minor version of the SMBIOS spec */
60 60 uint16_t smbe_maxssize; /* maximum size in bytes of a struct */
61 61 uint8_t smbe_revision; /* entry point structure revision */
62 62 uint8_t smbe_format[5]; /* entry point revision-specific data */
63 63 char smbe_ianchor[5]; /* intermed. tag (SMB_ENTRY_IANCHOR) */
64 64 uint8_t smbe_icksum; /* intermed. checksum */
65 65 uint16_t smbe_stlen; /* length in bytes of structure table */
66 66 uint32_t smbe_staddr; /* physical addr of structure table */
67 67 uint16_t smbe_stnum; /* number of structure table entries */
68 68 uint8_t smbe_bcdrev; /* BCD value representing DMI version */
69 69 } smbios_entry_t;
70 70
71 71 #pragma pack()
72 72
73 73 #define SMB_ENTRY_EANCHOR "_SM_" /* structure table entry point anchor */
74 74 #define SMB_ENTRY_EANCHORLEN 4 /* length of entry point anchor */
75 75 #define SMB_ENTRY_IANCHOR "_DMI_" /* intermediate anchor string */
76 76 #define SMB_ENTRY_IANCHORLEN 5 /* length of intermediate anchor */
77 77 #define SMB_ENTRY_MAXLEN 255 /* maximum length of entry point */
78 78
79 79 /*
80 80 * Structure type codes. The comments next to each type include an (R) note to
81 81 * indicate a structure that is required as of SMBIOS v2.8 and an (O) note to
82 82 * indicate a structure that is obsolete as of SMBIOS v2.8.
83 83 */
84 84 #define SMB_TYPE_BIOS 0 /* BIOS information (R) */
85 85 #define SMB_TYPE_SYSTEM 1 /* system information (R) */
86 86 #define SMB_TYPE_BASEBOARD 2 /* base board */
87 87 #define SMB_TYPE_CHASSIS 3 /* system enclosure or chassis (R) */
88 88 #define SMB_TYPE_PROCESSOR 4 /* processor (R) */
89 89 #define SMB_TYPE_MEMCTL 5 /* memory controller (O) */
90 90 #define SMB_TYPE_MEMMOD 6 /* memory module (O) */
91 91 #define SMB_TYPE_CACHE 7 /* processor cache (R) */
92 92 #define SMB_TYPE_PORT 8 /* port connector */
93 93 #define SMB_TYPE_SLOT 9 /* upgradeable system slot (R) */
94 94 #define SMB_TYPE_OBDEVS 10 /* on-board devices (O) */
95 95 #define SMB_TYPE_OEMSTR 11 /* OEM string table */
96 96 #define SMB_TYPE_SYSCONFSTR 12 /* system configuration string table */
97 97 #define SMB_TYPE_LANG 13 /* BIOS language information */
98 98 #define SMB_TYPE_GROUP 14 /* group associations */
99 99 #define SMB_TYPE_EVENTLOG 15 /* system event log */
100 100 #define SMB_TYPE_MEMARRAY 16 /* physical memory array (R) */
101 101 #define SMB_TYPE_MEMDEVICE 17 /* memory device (R) */
102 102 #define SMB_TYPE_MEMERR32 18 /* 32-bit memory error information */
103 103 #define SMB_TYPE_MEMARRAYMAP 19 /* memory array mapped address (R) */
104 104 #define SMB_TYPE_MEMDEVICEMAP 20 /* memory device mapped address */
105 105 #define SMB_TYPE_POINTDEV 21 /* built-in pointing device */
106 106 #define SMB_TYPE_BATTERY 22 /* portable battery */
107 107 #define SMB_TYPE_RESET 23 /* system reset settings */
108 108 #define SMB_TYPE_SECURITY 24 /* hardware security settings */
109 109 #define SMB_TYPE_POWERCTL 25 /* system power controls */
110 110 #define SMB_TYPE_VPROBE 26 /* voltage probe */
111 111 #define SMB_TYPE_COOLDEV 27 /* cooling device */
112 112 #define SMB_TYPE_TPROBE 28 /* temperature probe */
113 113 #define SMB_TYPE_IPROBE 29 /* current probe */
114 114 #define SMB_TYPE_OOBRA 30 /* out-of-band remote access facility */
115 115 #define SMB_TYPE_BIS 31 /* boot integrity services */
116 116 #define SMB_TYPE_BOOT 32 /* system boot status (R) */
117 117 #define SMB_TYPE_MEMERR64 33 /* 64-bit memory error information */
118 118 #define SMB_TYPE_MGMTDEV 34 /* management device */
119 119 #define SMB_TYPE_MGMTDEVCP 35 /* management device component */
120 120 #define SMB_TYPE_MGMTDEVDATA 36 /* management device threshold data */
121 121 #define SMB_TYPE_MEMCHAN 37 /* memory channel */
122 122 #define SMB_TYPE_IPMIDEV 38 /* IPMI device information */
123 123 #define SMB_TYPE_POWERSUP 39 /* system power supply */
124 124 #define SMB_TYPE_ADDINFO 40 /* additional information */
125 125 #define SMB_TYPE_OBDEVEXT 41 /* on-board device extended info */
126 126 #define SMB_TYPE_MCHI 42 /* mgmt controller host interface */
127 127 #define SMB_TYPE_INACTIVE 126 /* inactive table entry */
128 128 #define SMB_TYPE_EOT 127 /* end of table */
129 129
130 130 #define SMB_TYPE_OEM_LO 128 /* start of OEM-specific type range */
131 131 #define SUN_OEM_EXT_PROCESSOR 132 /* processor extended info */
132 132 #define SUN_OEM_EXT_PORT 136 /* port exteded info */
133 133 #define SUN_OEM_PCIEXRC 138 /* PCIE RootComplex/RootPort info */
134 134 #define SUN_OEM_EXT_MEMARRAY 144 /* phys memory array extended info */
135 135 #define SUN_OEM_EXT_MEMDEVICE 145 /* memory device extended info */
136 136 #define SMB_TYPE_OEM_HI 256 /* end of OEM-specific type range */
137 137
138 138 /*
139 139 * OEM string indicating "Platform Resource Management Specification"
140 140 * compliance.
141 141 */
142 142 #define SMB_PRMS1 "SUNW-PRMS-1"
143 143
144 144 /*
145 145 * Some default values set by BIOS vendor
146 146 */
147 147 #define SMB_DEFAULT1 "To Be Filled By O.E.M."
148 148 #define SMB_DEFAULT2 "Not Available"
149 149
150 150 /*
151 151 * SMBIOS Common Information. These structures do not correspond to anything
152 152 * in the SMBIOS specification, but allow library clients to more easily read
153 153 * information that is frequently encoded into the various SMBIOS structures.
154 154 */
155 155 typedef struct smbios_info {
156 156 const char *smbi_manufacturer; /* manufacturer */
157 157 const char *smbi_product; /* product name */
158 158 const char *smbi_version; /* version */
159 159 const char *smbi_serial; /* serial number */
160 160 const char *smbi_asset; /* asset tag */
161 161 const char *smbi_location; /* location tag */
162 162 const char *smbi_part; /* part number */
163 163 } smbios_info_t;
164 164
165 165 typedef struct smbios_version {
166 166 uint8_t smbv_major; /* version major number */
167 167 uint8_t smbv_minor; /* version minor number */
168 168 } smbios_version_t;
169 169
170 170 #define SMB_CONT_BYTE 1 /* contained elements are byte size */
171 171 #define SMB_CONT_WORD 2 /* contained elements are word size */
172 172 #define SMB_CONT_MAX 255 /* maximum contained objects */
173 173
174 174 /*
175 175 * SMBIOS Bios Information. See DSP0134 Section 7.1 for more information.
176 176 * smbb_romsize is converted from the implementation format into bytes.
177 177 */
178 178 typedef struct smbios_bios {
179 179 const char *smbb_vendor; /* bios vendor string */
180 180 const char *smbb_version; /* bios version string */
181 181 const char *smbb_reldate; /* bios release date */
182 182 uint32_t smbb_segment; /* bios address segment location */
183 183 uint32_t smbb_romsize; /* bios rom size in bytes */
184 184 uint32_t smbb_runsize; /* bios image size in bytes */
185 185 uint64_t smbb_cflags; /* bios characteristics */
186 186 const uint8_t *smbb_xcflags; /* bios characteristics extensions */
187 187 size_t smbb_nxcflags; /* number of smbb_xcflags[] bytes */
188 188 smbios_version_t smbb_biosv; /* bios version */
189 189 smbios_version_t smbb_ecfwv; /* bios embedded ctrl f/w version */
190 190 } smbios_bios_t;
191 191
192 192 #define SMB_BIOSFL_RSV0 0x00000001 /* reserved bit zero */
193 193 #define SMB_BIOSFL_RSV1 0x00000002 /* reserved bit one */
194 194 #define SMB_BIOSFL_UNKNOWN 0x00000004 /* unknown */
195 195 #define SMB_BIOSFL_BCNOTSUP 0x00000008 /* BIOS chars not supported */
196 196 #define SMB_BIOSFL_ISA 0x00000010 /* ISA is supported */
197 197 #define SMB_BIOSFL_MCA 0x00000020 /* MCA is supported */
198 198 #define SMB_BIOSFL_EISA 0x00000040 /* EISA is supported */
199 199 #define SMB_BIOSFL_PCI 0x00000080 /* PCI is supported */
200 200 #define SMB_BIOSFL_PCMCIA 0x00000100 /* PCMCIA is supported */
201 201 #define SMB_BIOSFL_PLUGNPLAY 0x00000200 /* Plug and Play is supported */
202 202 #define SMB_BIOSFL_APM 0x00000400 /* APM is supported */
203 203 #define SMB_BIOSFL_FLASH 0x00000800 /* BIOS is Flash Upgradeable */
204 204 #define SMB_BIOSFL_SHADOW 0x00001000 /* BIOS shadowing is allowed */
205 205 #define SMB_BIOSFL_VLVESA 0x00002000 /* VL-VESA is supported */
206 206 #define SMB_BIOSFL_ESCD 0x00004000 /* ESCD support is available */
207 207 #define SMB_BIOSFL_CDBOOT 0x00008000 /* Boot from CD is supported */
208 208 #define SMB_BIOSFL_SELBOOT 0x00010000 /* Selectable Boot supported */
209 209 #define SMB_BIOSFL_ROMSOCK 0x00020000 /* BIOS ROM is socketed */
210 210 #define SMB_BIOSFL_PCMBOOT 0x00040000 /* Boot from PCMCIA supported */
211 211 #define SMB_BIOSFL_EDD 0x00080000 /* EDD Spec is supported */
212 212 #define SMB_BIOSFL_NEC9800 0x00100000 /* int 0x13 NEC 9800 floppy */
213 213 #define SMB_BIOSFL_TOSHIBA 0x00200000 /* int 0x13 Toshiba floppy */
214 214 #define SMB_BIOSFL_525_360K 0x00400000 /* int 0x13 5.25" 360K floppy */
215 215 #define SMB_BIOSFL_525_12M 0x00800000 /* int 0x13 5.25" 1.2M floppy */
216 216 #define SMB_BIOSFL_35_720K 0x01000000 /* int 0x13 3.5" 720K floppy */
217 217 #define SMB_BIOSFL_35_288M 0x02000000 /* int 0x13 3.5" 2.88M floppy */
218 218 #define SMB_BIOSFL_I5_PRINT 0x04000000 /* int 0x5 print screen svcs */
219 219 #define SMB_BIOSFL_I9_KBD 0x08000000 /* int 0x9 8042 keyboard svcs */
220 220 #define SMB_BIOSFL_I14_SER 0x10000000 /* int 0x14 serial svcs */
221 221 #define SMB_BIOSFL_I17_PRINTER 0x20000000 /* int 0x17 printer svcs */
222 222 #define SMB_BIOSFL_I10_CGA 0x40000000 /* int 0x10 CGA svcs */
223 223 #define SMB_BIOSFL_NEC_PC98 0x80000000 /* NEC PC-98 */
224 224
225 225 #define SMB_BIOSXB_1 0 /* bios extension byte 1 (7.1.2.1) */
226 226 #define SMB_BIOSXB_2 1 /* bios extension byte 2 (7.1.2.2) */
227 227 #define SMB_BIOSXB_BIOS_MAJ 2 /* bios major version */
228 228 #define SMB_BIOSXB_BIOS_MIN 3 /* bios minor version */
229 229 #define SMB_BIOSXB_ECFW_MAJ 4 /* extended ctlr f/w major version */
230 230 #define SMB_BIOSXB_ECFW_MIN 5 /* extended ctlr f/w minor version */
231 231
232 232 #define SMB_BIOSXB1_ACPI 0x01 /* ACPI is supported */
233 233 #define SMB_BIOSXB1_USBL 0x02 /* USB legacy is supported */
234 234 #define SMB_BIOSXB1_AGP 0x04 /* AGP is supported */
235 235 #define SMB_BIOSXB1_I20 0x08 /* I2O boot is supported */
236 236 #define SMB_BIOSXB1_LS120 0x10 /* LS-120 boot is supported */
237 237 #define SMB_BIOSXB1_ATZIP 0x20 /* ATAPI ZIP drive boot is supported */
238 238 #define SMB_BIOSXB1_1394 0x40 /* 1394 boot is supported */
239 239 #define SMB_BIOSXB1_SMBAT 0x80 /* Smart Battery is supported */
240 240
241 241 #define SMB_BIOSXB2_BBOOT 0x01 /* BIOS Boot Specification supported */
242 242 #define SMB_BIOSXB2_FKNETSVC 0x02 /* F-key Network Svc boot supported */
243 243 #define SMB_BIOSXB2_ETCDIST 0x04 /* Enable Targeted Content Distrib. */
244 244 #define SMB_BIOSXB2_UEFI 0x08 /* UEFI Specification supported */
245 245 #define SMB_BIOSXB2_VM 0x10 /* SMBIOS table describes a VM */
246 246
247 247 /*
248 248 * SMBIOS System Information. See DSP0134 Section 7.2 for more information.
249 249 * The current set of smbs_wakeup values is defined after the structure.
250 250 */
251 251 typedef struct smbios_system {
252 252 const uint8_t *smbs_uuid; /* UUID byte array */
253 253 uint8_t smbs_uuidlen; /* UUID byte array length */
254 254 uint8_t smbs_wakeup; /* wake-up event */
255 255 const char *smbs_sku; /* SKU number */
256 256 const char *smbs_family; /* family */
257 257 } smbios_system_t;
258 258
259 259 #define SMB_WAKEUP_RSV0 0x00 /* reserved */
260 260 #define SMB_WAKEUP_OTHER 0x01 /* other */
261 261 #define SMB_WAKEUP_UNKNOWN 0x02 /* unknown */
262 262 #define SMB_WAKEUP_APM 0x03 /* APM timer */
263 263 #define SMB_WAKEUP_MODEM 0x04 /* modem ring */
264 264 #define SMB_WAKEUP_LAN 0x05 /* LAN remote */
265 265 #define SMB_WAKEUP_SWITCH 0x06 /* power switch */
266 266 #define SMB_WAKEUP_PCIPME 0x07 /* PCI PME# */
267 267 #define SMB_WAKEUP_AC 0x08 /* AC power restored */
268 268
269 269 /*
270 270 * SMBIOS Base Board description. See DSP0134 Section 7.3 for more
271 271 * information. smbb_flags and smbb_type definitions are below.
272 272 */
273 273 typedef struct smbios_bboard {
274 274 id_t smbb_chassis; /* chassis containing this board */
275 275 uint8_t smbb_flags; /* flags (see below) */
276 276 uint8_t smbb_type; /* board type (see below) */
277 277 uint8_t smbb_contn; /* number of contained object hdls */
278 278 } smbios_bboard_t;
279 279
280 280 #define SMB_BBFL_MOTHERBOARD 0x01 /* board is a motherboard */
281 281 #define SMB_BBFL_NEEDAUX 0x02 /* auxiliary card or daughter req'd */
282 282 #define SMB_BBFL_REMOVABLE 0x04 /* board is removable */
283 283 #define SMB_BBFL_REPLACABLE 0x08 /* board is field-replacable */
284 284 #define SMB_BBFL_HOTSWAP 0x10 /* board is hot-swappable */
285 285
286 286 #define SMB_BBT_UNKNOWN 0x1 /* unknown */
287 287 #define SMB_BBT_OTHER 0x2 /* other */
288 288 #define SMB_BBT_SBLADE 0x3 /* server blade */
289 289 #define SMB_BBT_CSWITCH 0x4 /* connectivity switch */
290 290 #define SMB_BBT_SMM 0x5 /* system management module */
291 291 #define SMB_BBT_PROC 0x6 /* processor module */
292 292 #define SMB_BBT_IO 0x7 /* i/o module */
293 293 #define SMB_BBT_MEM 0x8 /* memory module */
294 294 #define SMB_BBT_DAUGHTER 0x9 /* daughterboard */
295 295 #define SMB_BBT_MOTHER 0xA /* motherboard */
296 296 #define SMB_BBT_PROCMEM 0xB /* processor/memory module */
297 297 #define SMB_BBT_PROCIO 0xC /* processor/i/o module */
298 298 #define SMB_BBT_INTER 0xD /* interconnect board */
299 299
300 300 /*
301 301 * SMBIOS Chassis description. See DSP0134 Section 7.4 for more information.
302 302 * We move the lock bit of the type field into smbc_lock for easier processing.
303 303 */
304 304 typedef struct smbios_chassis {
305 305 uint32_t smbc_oemdata; /* OEM-specific data */
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306 306 uint8_t smbc_lock; /* lock present? */
307 307 uint8_t smbc_type; /* type */
308 308 uint8_t smbc_bustate; /* boot-up state */
309 309 uint8_t smbc_psstate; /* power supply state */
310 310 uint8_t smbc_thstate; /* thermal state */
311 311 uint8_t smbc_security; /* security status */
312 312 uint8_t smbc_uheight; /* enclosure height in U's */
313 313 uint8_t smbc_cords; /* number of power cords */
314 314 uint8_t smbc_elems; /* number of element records (n) */
315 315 uint8_t smbc_elemlen; /* length of contained element (m) */
316 - const char *smbc_sku; /* SKU number */
316 + char smbc_sku[256]; /* SKU number (as a string) */
317 317 } smbios_chassis_t;
318 318
319 319 #define SMB_CHT_OTHER 0x01 /* other */
320 320 #define SMB_CHT_UNKNOWN 0x02 /* unknown */
321 321 #define SMB_CHT_DESKTOP 0x03 /* desktop */
322 322 #define SMB_CHT_LPDESKTOP 0x04 /* low-profile desktop */
323 323 #define SMB_CHT_PIZZA 0x05 /* pizza box */
324 324 #define SMB_CHT_MINITOWER 0x06 /* mini-tower */
325 325 #define SMB_CHT_TOWER 0x07 /* tower */
326 326 #define SMB_CHT_PORTABLE 0x08 /* portable */
327 327 #define SMB_CHT_LAPTOP 0x09 /* laptop */
328 328 #define SMB_CHT_NOTEBOOK 0x0A /* notebook */
329 329 #define SMB_CHT_HANDHELD 0x0B /* hand-held */
330 330 #define SMB_CHT_DOCK 0x0C /* docking station */
331 331 #define SMB_CHT_ALLIN1 0x0D /* all-in-one */
332 332 #define SMB_CHT_SUBNOTE 0x0E /* sub-notebook */
333 333 #define SMB_CHT_SPACESAVE 0x0F /* space-saving */
334 334 #define SMB_CHT_LUNCHBOX 0x10 /* lunchbox */
335 335 #define SMB_CHT_MAIN 0x11 /* main server chassis */
336 336 #define SMB_CHT_EXPANSION 0x12 /* expansion chassis */
337 337 #define SMB_CHT_SUB 0x13 /* sub-chassis */
338 338 #define SMB_CHT_BUS 0x14 /* bus expansion chassis */
339 339 #define SMB_CHT_PERIPHERAL 0x15 /* peripheral chassis */
340 340 #define SMB_CHT_RAID 0x16 /* raid chassis */
341 341 #define SMB_CHT_RACK 0x17 /* rack mount chassis */
342 342 #define SMB_CHT_SEALED 0x18 /* sealed case pc */
343 343 #define SMB_CHT_MULTI 0x19 /* multi-system chassis */
344 344 #define SMB_CHT_CPCI 0x1A /* compact PCI */
345 345 #define SMB_CHT_ATCA 0x1B /* advanced TCA */
346 346 #define SMB_CHT_BLADE 0x1C /* blade */
347 347 #define SMB_CHT_BLADEENC 0x1D /* blade enclosure */
348 348
349 349 #define SMB_CHST_OTHER 0x01 /* other */
350 350 #define SMB_CHST_UNKNOWN 0x02 /* unknown */
351 351 #define SMB_CHST_SAFE 0x03 /* safe */
352 352 #define SMB_CHST_WARNING 0x04 /* warning */
353 353 #define SMB_CHST_CRITICAL 0x05 /* critical */
354 354 #define SMB_CHST_NONREC 0x06 /* non-recoverable */
355 355
356 356 #define SMB_CHSC_OTHER 0x01 /* other */
357 357 #define SMB_CHSC_UNKNOWN 0x02 /* unknown */
358 358 #define SMB_CHSC_NONE 0x03 /* none */
359 359 #define SMB_CHSC_EILOCK 0x04 /* external interface locked out */
360 360 #define SMB_CHSC_EIENAB 0x05 /* external interface enabled */
361 361
362 362 /*
363 363 * SMBIOS Processor description. See DSP0134 Section 7.5 for more details.
364 364 * If the L1, L2, or L3 cache handle is -1, the cache information is unknown.
365 365 * If the handle refers to something of size 0, that type of cache is absent.
366 366 *
367 367 * NOTE: Although SMBIOS exports a 64-bit CPUID result, this value should not
368 368 * be used for any purpose other than BIOS debugging. illumos itself computes
369 369 * its own CPUID value and applies knowledge of additional errata and processor
370 370 * specific CPUID variations, so this value should not be used for anything.
371 371 */
372 372 typedef struct smbios_processor {
373 373 uint64_t smbp_cpuid; /* processor cpuid information */
374 374 uint32_t smbp_family; /* processor family */
375 375 uint8_t smbp_type; /* processor type (SMB_PRT_*) */
376 376 uint8_t smbp_voltage; /* voltage (SMB_PRV_*) */
377 377 uint8_t smbp_status; /* status (SMB_PRS_*) */
378 378 uint8_t smbp_upgrade; /* upgrade (SMB_PRU_*) */
379 379 uint32_t smbp_clkspeed; /* external clock speed in MHz */
380 380 uint32_t smbp_maxspeed; /* maximum speed in MHz */
381 381 uint32_t smbp_curspeed; /* current speed in MHz */
382 382 id_t smbp_l1cache; /* L1 cache handle */
383 383 id_t smbp_l2cache; /* L2 cache handle */
384 384 id_t smbp_l3cache; /* L3 cache handle */
385 385 uint8_t smbp_corecount; /* number of cores per processor socket */
386 386 uint8_t smbp_coresenabled;
387 387 /* number of enabled cores per processor socket */
388 388 uint8_t smbp_threadcount;
389 389 /* number of threads per processor socket */
390 390 uint16_t smbp_cflags;
391 391 /* processor characteristics (SMB_PRC_*) */
392 392 uint16_t smbp_family2; /* processor family 2 */
393 393 } smbios_processor_t;
394 394
395 395 #define SMB_PRT_OTHER 0x01 /* other */
396 396 #define SMB_PRT_UNKNOWN 0x02 /* unknown */
397 397 #define SMB_PRT_CENTRAL 0x03 /* central processor */
398 398 #define SMB_PRT_MATH 0x04 /* math processor */
399 399 #define SMB_PRT_DSP 0x05 /* DSP processor */
400 400 #define SMB_PRT_VIDEO 0x06 /* video processor */
401 401
402 402 #define SMB_PRV_LEGACY(v) (!((v) & 0x80)) /* legacy voltage mode */
403 403 #define SMB_PRV_FIXED(v) ((v) & 0x80) /* fixed voltage mode */
404 404
405 405 #define SMB_PRV_5V 0x01 /* 5V is supported */
406 406 #define SMB_PRV_33V 0x02 /* 3.3V is supported */
407 407 #define SMB_PRV_29V 0x04 /* 2.9V is supported */
408 408
409 409 #define SMB_PRV_VOLTAGE(v) ((v) & 0x7f)
410 410
411 411 #define SMB_PRSTATUS_PRESENT(s) ((s) & 0x40) /* socket is populated */
412 412 #define SMB_PRSTATUS_STATUS(s) ((s) & 0x07) /* status (see below) */
413 413
414 414 #define SMB_PRS_UNKNOWN 0x0 /* unknown */
415 415 #define SMB_PRS_ENABLED 0x1 /* enabled */
416 416 #define SMB_PRS_BDISABLED 0x2 /* disabled in bios user setup */
417 417 #define SMB_PRS_PDISABLED 0x3 /* disabled in bios from post error */
418 418 #define SMB_PRS_IDLE 0x4 /* waiting to be enabled */
419 419 #define SMB_PRS_OTHER 0x7 /* other */
420 420
421 421 #define SMB_PRU_OTHER 0x01 /* other */
422 422 #define SMB_PRU_UNKNOWN 0x02 /* unknown */
423 423 #define SMB_PRU_DAUGHTER 0x03 /* daughter board */
424 424 #define SMB_PRU_ZIF 0x04 /* ZIF socket */
425 425 #define SMB_PRU_PIGGY 0x05 /* replaceable piggy back */
426 426 #define SMB_PRU_NONE 0x06 /* none */
427 427 #define SMB_PRU_LIF 0x07 /* LIF socket */
428 428 #define SMB_PRU_SLOT1 0x08 /* slot 1 */
429 429 #define SMB_PRU_SLOT2 0x09 /* slot 2 */
430 430 #define SMB_PRU_370PIN 0x0A /* 370-pin socket */
431 431 #define SMB_PRU_SLOTA 0x0B /* slot A */
432 432 #define SMB_PRU_SLOTM 0x0C /* slot M */
433 433 #define SMB_PRU_423 0x0D /* socket 423 */
434 434 #define SMB_PRU_A 0x0E /* socket A (socket 462) */
435 435 #define SMB_PRU_478 0x0F /* socket 478 */
436 436 #define SMB_PRU_754 0x10 /* socket 754 */
437 437 #define SMB_PRU_940 0x11 /* socket 940 */
438 438 #define SMB_PRU_939 0x12 /* socket 939 */
439 439 #define SMB_PRU_MPGA604 0x13 /* mPGA604 */
440 440 #define SMB_PRU_LGA771 0x14 /* LGA771 */
441 441 #define SMB_PRU_LGA775 0x15 /* LGA775 */
442 442 #define SMB_PRU_S1 0x16 /* socket S1 */
443 443 #define SMB_PRU_AM2 0x17 /* socket AM2 */
444 444 #define SMB_PRU_F 0x18 /* socket F */
445 445 #define SMB_PRU_LGA1366 0x19 /* LGA1366 */
446 446 #define SMB_PRU_G34 0x1A /* socket G34 */
447 447 #define SMB_PRU_AM3 0x1B /* socket AM3 */
448 448 #define SMB_PRU_C32 0x1C /* socket C32 */
449 449 #define SMB_PRU_LGA1156 0x1D /* LGA1156 */
450 450 #define SMB_PRU_LGA1567 0x1E /* LGA1567 */
451 451 #define SMB_PRU_PGA988A 0x1F /* PGA988A */
452 452 #define SMB_PRU_BGA1288 0x20 /* BGA1288 */
453 453 #define SMB_PRU_RPGA988B 0x21 /* rPGA988B */
454 454 #define SMB_PRU_BGA1023 0x22 /* BGA1023 */
455 455 #define SMB_PRU_BGA1224 0x23 /* BGA1224 */
456 456 #define SMB_PRU_LGA1155 0x24 /* LGA1155 */
457 457 #define SMB_PRU_LGA1356 0x25 /* LGA1356 */
458 458 #define SMB_PRU_LGA2011 0x26 /* LGA2011 */
459 459 #define SMB_PRU_FS1 0x27 /* socket FS1 */
460 460 #define SMB_PRU_FS2 0x28 /* socket FS2 */
461 461 #define SMB_PRU_FM1 0x29 /* socket FM1 */
462 462 #define SMB_PRU_FM2 0x2A /* socket FM2 */
463 463 #define SMB_PRU_LGA20113 0x2B /* LGA2011-3 */
464 464 #define SMB_PRU_LGA13563 0x2C /* LGA1356-3 */
465 465
466 466 #define SMB_PRC_RESERVED 0x0001 /* reserved */
467 467 #define SMB_PRC_UNKNOWN 0x0002 /* unknown */
468 468 #define SMB_PRC_64BIT 0x0004 /* 64-bit capable */
469 469 #define SMB_PRC_MC 0x0008 /* multi-core */
470 470 #define SMB_PRC_HT 0x0010 /* hardware thread */
471 471 #define SMB_PRC_NX 0x0020 /* execution protection */
472 472 #define SMB_PRC_VT 0x0040 /* enhanced virtualization */
473 473 #define SMB_PRC_PM 0x0080 /* power/performance control */
474 474
475 475 #define SMB_PRF_OTHER 0x01 /* other */
476 476 #define SMB_PRF_UNKNOWN 0x02 /* unknown */
477 477 #define SMB_PRF_8086 0x03 /* 8086 */
478 478 #define SMB_PRF_80286 0x04 /* 80286 */
479 479 #define SMB_PRF_I386 0x05 /* Intel 386 */
480 480 #define SMB_PRF_I486 0x06 /* Intel 486 */
481 481 #define SMB_PRF_8087 0x07 /* 8087 */
482 482 #define SMB_PRF_80287 0x08 /* 80287 */
483 483 #define SMB_PRF_80387 0x09 /* 80387 */
484 484 #define SMB_PRF_80487 0x0A /* 80487 */
485 485 #define SMB_PRF_PENTIUM 0x0B /* Pentium Family */
486 486 #define SMB_PRF_PENTIUMPRO 0x0C /* Pentium Pro */
487 487 #define SMB_PRF_PENTIUMII 0x0D /* Pentium II */
488 488 #define SMB_PRF_PENTIUM_MMX 0x0E /* Pentium w/ MMX */
489 489 #define SMB_PRF_CELERON 0x0F /* Celeron */
490 490 #define SMB_PRF_PENTIUMII_XEON 0x10 /* Pentium II Xeon */
491 491 #define SMB_PRF_PENTIUMIII 0x11 /* Pentium III */
492 492 #define SMB_PRF_M1 0x12 /* M1 */
493 493 #define SMB_PRF_M2 0x13 /* M2 */
494 494 #define SMB_PRF_CELERON_M 0x14 /* Celeron M */
495 495 #define SMB_PRF_PENTIUMIV_HT 0x15 /* Pentium 4 HT */
496 496 #define SMB_PRF_DURON 0x18 /* AMD Duron */
497 497 #define SMB_PRF_K5 0x19 /* K5 */
498 498 #define SMB_PRF_K6 0x1A /* K6 */
499 499 #define SMB_PRF_K6_2 0x1B /* K6-2 */
500 500 #define SMB_PRF_K6_3 0x1C /* K6-3 */
501 501 #define SMB_PRF_ATHLON 0x1D /* Athlon */
502 502 #define SMB_PRF_2900 0x1E /* AMD 2900 */
503 503 #define SMB_PRF_K6_2PLUS 0x1F /* K6-2+ */
504 504 #define SMB_PRF_PPC 0x20 /* PowerPC */
505 505 #define SMB_PRF_PPC_601 0x21 /* PowerPC 601 */
506 506 #define SMB_PRF_PPC_603 0x22 /* PowerPC 603 */
507 507 #define SMB_PRF_PPC_603PLUS 0x23 /* PowerPC 603+ */
508 508 #define SMB_PRF_PPC_604 0x24 /* PowerPC 604 */
509 509 #define SMB_PRF_PPC_620 0x25 /* PowerPC 620 */
510 510 #define SMB_PRF_PPC_704 0x26 /* PowerPC x704 */
511 511 #define SMB_PRF_PPC_750 0x27 /* PowerPC 750 */
512 512 #define SMB_PRF_CORE_DUO 0x28 /* Core Duo */
513 513 #define SMB_PRF_CORE_DUO_M 0x29 /* Core Duo mobile */
514 514 #define SMB_PRF_CORE_SOLO_M 0x2A /* Core Solo mobile */
515 515 #define SMB_PRF_ATOM 0x2B /* Intel Atom */
516 516 #define SMB_PRF_ALPHA 0x30 /* Alpha */
517 517 #define SMB_PRF_ALPHA_21064 0x31 /* Alpha 21064 */
518 518 #define SMB_PRF_ALPHA_21066 0x32 /* Alpha 21066 */
519 519 #define SMB_PRF_ALPHA_21164 0x33 /* Alpha 21164 */
520 520 #define SMB_PRF_ALPHA_21164PC 0x34 /* Alpha 21164PC */
521 521 #define SMB_PRF_ALPHA_21164A 0x35 /* Alpha 21164a */
522 522 #define SMB_PRF_ALPHA_21264 0x36 /* Alpha 21264 */
523 523 #define SMB_PRF_ALPHA_21364 0x37 /* Alpha 21364 */
524 524 #define SMB_PRF_TURION2U_2C_MM 0x38
525 525 /* AMD Turion II Ultra Dual-Core Mobile M */
526 526 #define SMB_PRF_TURION2_2C_MM 0x39 /* AMD Turion II Dual-Core Mobile M */
527 527 #define SMB_PRF_ATHLON2_2C_M 0x3A /* AMD Athlon II Dual-Core M */
528 528 #define SMB_PRF_OPTERON_6100 0x3B /* AMD Opteron 6100 series */
529 529 #define SMB_PRF_OPTERON_4100 0x3C /* AMD Opteron 4100 series */
530 530 #define SMB_PRF_OPTERON_6200 0x3D /* AMD Opteron 6200 series */
531 531 #define SMB_PRF_OPTERON_4200 0x3E /* AMD Opteron 4200 series */
532 532 #define SMB_PRF_AMD_FX 0x3F /* AMD FX series */
533 533 #define SMB_PRF_MIPS 0x40 /* MIPS */
534 534 #define SMB_PRF_MIPS_R4000 0x41 /* MIPS R4000 */
535 535 #define SMB_PRF_MIPS_R4200 0x42 /* MIPS R4200 */
536 536 #define SMB_PRF_MIPS_R4400 0x43 /* MIPS R4400 */
537 537 #define SMB_PRF_MIPS_R4600 0x44 /* MIPS R4600 */
538 538 #define SMB_PRF_MIPS_R10000 0x45 /* MIPS R10000 */
539 539 #define SMB_PRF_AMD_C 0x46 /* AMD C-series */
540 540 #define SMB_PRF_AMD_E 0x47 /* AMD E-series */
541 541 #define SMB_PRF_AMD_A 0x48 /* AMD A-series */
542 542 #define SMB_PRF_AMD_G 0x49 /* AMD G-series */
543 543 #define SMB_PRF_AMD_Z 0x4A /* AMD Z-series */
544 544 #define SMB_PRF_AMD_R 0x4B /* AMD R-series */
545 545 #define SMB_PRF_OPTERON_4300 0x4C /* AMD Opteron 4300 series */
546 546 #define SMB_PRF_OPTERON_6300 0x4D /* AMD Opteron 6300 series */
547 547 #define SMB_PRF_OPTERON_3300 0x4E /* AMD Opteron 3300 series */
548 548 #define SMB_PRF_AMD_FIREPRO 0x4F /* AMD FirePro series */
549 549 #define SMB_PRF_SPARC 0x50 /* SPARC */
550 550 #define SMB_PRF_SUPERSPARC 0x51 /* SuperSPARC */
551 551 #define SMB_PRF_MICROSPARCII 0x52 /* microSPARC II */
552 552 #define SMB_PRF_MICROSPARCIIep 0x53 /* microSPARC IIep */
553 553 #define SMB_PRF_ULTRASPARC 0x54 /* UltraSPARC */
554 554 #define SMB_PRF_USII 0x55 /* UltraSPARC II */
555 555 #define SMB_PRF_USIIi 0x56 /* UltraSPARC IIi */
556 556 #define SMB_PRF_USIII 0x57 /* UltraSPARC III */
557 557 #define SMB_PRF_USIIIi 0x58 /* UltraSPARC IIIi */
558 558 #define SMB_PRF_68040 0x60 /* 68040 */
559 559 #define SMB_PRF_68XXX 0x61 /* 68XXX */
560 560 #define SMB_PRF_68000 0x62 /* 68000 */
561 561 #define SMB_PRF_68010 0x63 /* 68010 */
562 562 #define SMB_PRF_68020 0x64 /* 68020 */
563 563 #define SMB_PRF_68030 0x65 /* 68030 */
564 564 #define SMB_PRF_HOBBIT 0x70 /* Hobbit */
565 565 #define SMB_PRF_TM5000 0x78 /* Crusoe TM5000 */
566 566 #define SMB_PRF_TM3000 0x79 /* Crusoe TM3000 */
567 567 #define SMB_PRF_TM8000 0x7A /* Efficeon TM8000 */
568 568 #define SMB_PRF_WEITEK 0x80 /* Weitek */
569 569 #define SMB_PRF_ITANIC 0x82 /* Itanium */
570 570 #define SMB_PRF_ATHLON64 0x83 /* Athlon64 */
571 571 #define SMB_PRF_OPTERON 0x84 /* Opteron */
572 572 #define SMB_PRF_SEMPRON 0x85 /* Sempron */
573 573 #define SMB_PRF_TURION64_M 0x86 /* Turion 64 Mobile */
574 574 #define SMB_PRF_OPTERON_2C 0x87 /* AMD Opteron Dual-Core */
575 575 #define SMB_PRF_ATHLON64_X2_2C 0x88 /* AMD Athlon 64 X2 Dual-Core */
576 576 #define SMB_PRF_TURION64_X2_M 0x89 /* AMD Turion 64 X2 Mobile */
577 577 #define SMB_PRF_OPTERON_4C 0x8A /* AMD Opteron Quad-Core */
578 578 #define SMB_PRF_OPTERON_3G 0x8B /* AMD Opteron 3rd Generation */
579 579 #define SMB_PRF_PHENOM_FX_4C 0x8C /* AMD Phenom FX Quad-Core */
580 580 #define SMB_PRF_PHENOM_X4_4C 0x8D /* AMD Phenom X4 Quad-Core */
581 581 #define SMB_PRF_PHENOM_X2_2C 0x8E /* AMD Phenom X2 Dual-Core */
582 582 #define SMB_PRF_ATHLON_X2_2C 0x8F /* AMD Athlon X2 Dual-Core */
583 583 #define SMB_PRF_PA 0x90 /* PA-RISC */
584 584 #define SMB_PRF_PA8500 0x91 /* PA-RISC 8500 */
585 585 #define SMB_PRF_PA8000 0x92 /* PA-RISC 8000 */
586 586 #define SMB_PRF_PA7300LC 0x93 /* PA-RISC 7300LC */
587 587 #define SMB_PRF_PA7200 0x94 /* PA-RISC 7200 */
588 588 #define SMB_PRF_PA7100LC 0x95 /* PA-RISC 7100LC */
589 589 #define SMB_PRF_PA7100 0x96 /* PA-RISC 7100 */
590 590 #define SMB_PRF_V30 0xA0 /* V30 */
591 591 #define SMB_PRF_XEON_4C_3200 0xA1 /* Xeon Quad Core 3200 */
592 592 #define SMB_PRF_XEON_2C_3000 0xA2 /* Xeon Dual Core 3000 */
593 593 #define SMB_PRF_XEON_4C_5300 0xA3 /* Xeon Quad Core 5300 */
594 594 #define SMB_PRF_XEON_2C_5100 0xA4 /* Xeon Dual Core 5100 */
595 595 #define SMB_PRF_XEON_2C_5000 0xA5 /* Xeon Dual Core 5000 */
596 596 #define SMB_PRF_XEON_2C_LV 0xA6 /* Xeon Dual Core LV */
597 597 #define SMB_PRF_XEON_2C_ULV 0xA7 /* Xeon Dual Core ULV */
598 598 #define SMB_PRF_XEON_2C_7100 0xA8 /* Xeon Dual Core 7100 */
599 599 #define SMB_PRF_XEON_4C_5400 0xA9 /* Xeon Quad Core 5400 */
600 600 #define SMB_PRF_XEON_4C 0xAA /* Xeon Quad Core */
601 601 #define SMB_PRF_XEON_2C_5200 0xAB /* Xeon Dual Core 5200 */
602 602 #define SMB_PRF_XEON_2C_7200 0xAC /* Xeon Dual Core 7200 */
603 603 #define SMB_PRF_XEON_4C_7300 0xAD /* Xeon Quad Core 7300 */
604 604 #define SMB_PRF_XEON_4C_7400 0xAE /* Xeon Quad Core 7400 */
605 605 #define SMB_PRF_XEON_XC_7400 0xAF /* Xeon Multi Core 7400 */
606 606 #define SMB_PRF_PENTIUMIII_XEON 0xB0 /* Pentium III Xeon */
607 607 #define SMB_PRF_PENTIUMIII_SS 0xB1 /* Pentium III with SpeedStep */
608 608 #define SMB_PRF_P4 0xB2 /* Pentium 4 */
609 609 #define SMB_PRF_XEON 0xB3 /* Intel Xeon */
610 610 #define SMB_PRF_AS400 0xB4 /* AS400 */
611 611 #define SMB_PRF_XEON_MP 0xB5 /* Intel Xeon MP */
612 612 #define SMB_PRF_ATHLON_XP 0xB6 /* AMD Athlon XP */
613 613 #define SMB_PRF_ATHLON_MP 0xB7 /* AMD Athlon MP */
614 614 #define SMB_PRF_ITANIC2 0xB8 /* Itanium 2 */
615 615 #define SMB_PRF_PENTIUM_M 0xB9 /* Pentium M */
616 616 #define SMB_PRF_CELERON_D 0xBA /* Celeron D */
617 617 #define SMB_PRF_PENTIUM_D 0xBB /* Pentium D */
618 618 #define SMB_PRF_PENTIUM_EE 0xBC /* Pentium Extreme Edition */
619 619 #define SMB_PRF_CORE_SOLO 0xBD /* Intel Core Solo */
620 620 #define SMB_PRF_CORE2_DUO 0xBF /* Intel Core 2 Duo */
621 621 #define SMB_PRF_CORE2_SOLO 0xC0 /* Intel Core 2 Solo */
622 622 #define SMB_PRF_CORE2_EX 0xC1 /* Intel Core 2 Extreme */
623 623 #define SMB_PRF_CORE2_QUAD 0xC2 /* Intel Core 2 Quad */
624 624 #define SMB_PRF_CORE2_EX_M 0xC3 /* Intel Core 2 Extreme mobile */
625 625 #define SMB_PRF_CORE2_DUO_M 0xC4 /* Intel Core 2 Duo mobile */
626 626 #define SMB_PRF_CORE2_SOLO_M 0xC5 /* Intel Core 2 Solo mobile */
627 627 #define SMB_PRF_CORE_I7 0xC6 /* Intel Core i7 */
628 628 #define SMB_PRF_CELERON_2C 0xC7 /* Celeron Dual-Core */
629 629 #define SMB_PRF_IBM390 0xC8 /* IBM 390 */
630 630 #define SMB_PRF_G4 0xC9 /* G4 */
631 631 #define SMB_PRF_G5 0xCA /* G5 */
632 632 #define SMB_PRF_ESA390 0xCB /* ESA390 */
633 633 #define SMB_PRF_ZARCH 0xCC /* z/Architecture */
634 634 #define SMB_PRF_CORE_I5 0xCD /* Intel Core i5 */
635 635 #define SMB_PRF_CORE_I3 0xCE /* Intel Core i3 */
636 636 #define SMB_PRF_C7M 0xD2 /* VIA C7-M */
637 637 #define SMB_PRF_C7D 0xD3 /* VIA C7-D */
638 638 #define SMB_PRF_C7 0xD4 /* VIA C7 */
639 639 #define SMB_PRF_EDEN 0xD5 /* VIA Eden */
640 640 #define SMB_PRF_XEON_XC 0xD6 /* Intel Xeon Multi-Core */
641 641 #define SMB_PRF_XEON_2C_3XXX 0xD7 /* Intel Xeon Dual-Core 3xxx */
642 642 #define SMB_PRF_XEON_4C_3XXX 0xD8 /* Intel Xeon Quad-Core 3xxx */
643 643 #define SMB_PRF_VIA_NANO 0xD9 /* VIA Nano */
644 644 #define SMB_PRF_XEON_2C_5XXX 0xDA /* Intel Xeon Dual-Core 5xxx */
645 645 #define SMB_PRF_XEON_4C_5XXX 0xDB /* Intel Xeon Quad-Core 5xxx */
646 646 #define SMB_PRF_XEON_2C_7XXX 0xDD /* Intel Xeon Dual-Core 7xxx */
647 647 #define SMB_PRF_XEON_4C_7XXX 0xDE /* Intel Xeon Quad-Core 7xxx */
648 648 #define SMB_PRF_XEON_XC_7XXX 0xDF /* Intel Xeon Multi-Core 7xxx */
649 649 #define SMB_PRF_XEON_XC_3400 0xE0 /* Intel Xeon Multi-Core 3400 */
650 650 #define SMB_PRF_OPTERON_3000 0xE4 /* AMD Opteron 3000 */
651 651 #define SMB_PRF_SEMPRON_II 0xE5 /* AMD Sempron II */
652 652 #define SMB_PRF_OPTERON_4C_EM 0xE6 /* AMD Opteron Quad-Core embedded */
653 653 #define SMB_PRF_PHENOM_3C 0xE7 /* AMD Phenom Triple-Core */
654 654 #define SMB_PRF_TURIONU_2C_M 0xE8 /* AMD Turion Ultra Dual-Core mobile */
655 655 #define SMB_PRF_TURION_2C_M 0xE9 /* AMD Turion Dual-Core mobile */
656 656 #define SMB_PRF_ATHLON_2C 0xEA /* AMD Athlon Dual-Core */
657 657 #define SMB_PRF_SEMPRON_SI 0xEB /* AMD Sempron SI */
658 658 #define SMB_PRF_PHENOM_II 0xEC /* AMD Phenom II */
659 659 #define SMB_PRF_ATHLON_II 0xED /* AMD Athlon II */
660 660 #define SMB_PRF_OPTERON_6C 0xEE /* AMD Opteron Six-Core */
661 661 #define SMB_PRF_SEMPRON_M 0xEF /* AMD Sempron M */
662 662 #define SMB_PRF_I860 0xFA /* i860 */
663 663 #define SMB_PRF_I960 0xFB /* i960 */
664 664 #define SMB_PRF_SH3 0x104 /* SH-3 */
665 665 #define SMB_PRF_SH4 0x105 /* SH-4 */
666 666 #define SMB_PRF_ARM 0x118 /* ARM */
667 667 #define SMB_PRF_SARM 0x119 /* StrongARM */
668 668 #define SMB_PRF_6X86 0x12C /* 6x86 */
669 669 #define SMB_PRF_MEDIAGX 0x12D /* MediaGX */
670 670 #define SMB_PRF_MII 0x12E /* MII */
671 671 #define SMB_PRF_WINCHIP 0x140 /* WinChip */
672 672 #define SMB_PRF_DSP 0x15E /* DSP */
673 673 #define SMB_PRF_VIDEO 0x1F4 /* Video Processor */
674 674
675 675 /*
676 676 * SMBIOS Cache Information. See DSP0134 Section 7.8 for more information.
677 677 * If smba_size is zero, this indicates the specified cache is not present.
678 678 */
679 679 typedef struct smbios_cache {
680 680 uint32_t smba_maxsize; /* maximum installed size in bytes */
681 681 uint32_t smba_size; /* installed size in bytes */
682 682 uint16_t smba_stype; /* supported SRAM types (SMB_CAT_*) */
683 683 uint16_t smba_ctype; /* current SRAM type (SMB_CAT_*) */
684 684 uint8_t smba_speed; /* speed in nanoseconds */
685 685 uint8_t smba_etype; /* error correction type (SMB_CAE_*) */
686 686 uint8_t smba_ltype; /* logical cache type (SMB_CAG_*) */
687 687 uint8_t smba_assoc; /* associativity (SMB_CAA_*) */
688 688 uint8_t smba_level; /* cache level */
689 689 uint8_t smba_mode; /* cache mode (SMB_CAM_*) */
690 690 uint8_t smba_location; /* cache location (SMB_CAL_*) */
691 691 uint8_t smba_flags; /* cache flags (SMB_CAF_*) */
692 692 } smbios_cache_t;
693 693
694 694 #define SMB_CAT_OTHER 0x0001 /* other */
695 695 #define SMB_CAT_UNKNOWN 0x0002 /* unknown */
696 696 #define SMB_CAT_NONBURST 0x0004 /* non-burst */
697 697 #define SMB_CAT_BURST 0x0008 /* burst */
698 698 #define SMB_CAT_PBURST 0x0010 /* pipeline burst */
699 699 #define SMB_CAT_SYNC 0x0020 /* synchronous */
700 700 #define SMB_CAT_ASYNC 0x0040 /* asynchronous */
701 701
702 702 #define SMB_CAE_OTHER 0x01 /* other */
703 703 #define SMB_CAE_UNKNOWN 0x02 /* unknown */
704 704 #define SMB_CAE_NONE 0x03 /* none */
705 705 #define SMB_CAE_PARITY 0x04 /* parity */
706 706 #define SMB_CAE_SBECC 0x05 /* single-bit ECC */
707 707 #define SMB_CAE_MBECC 0x06 /* multi-bit ECC */
708 708
709 709 #define SMB_CAG_OTHER 0x01 /* other */
710 710 #define SMB_CAG_UNKNOWN 0x02 /* unknown */
711 711 #define SMB_CAG_INSTR 0x03 /* instruction */
712 712 #define SMB_CAG_DATA 0x04 /* data */
713 713 #define SMB_CAG_UNIFIED 0x05 /* unified */
714 714
715 715 #define SMB_CAA_OTHER 0x01 /* other */
716 716 #define SMB_CAA_UNKNOWN 0x02 /* unknown */
717 717 #define SMB_CAA_DIRECT 0x03 /* direct mapped */
718 718 #define SMB_CAA_2WAY 0x04 /* 2-way set associative */
719 719 #define SMB_CAA_4WAY 0x05 /* 4-way set associative */
720 720 #define SMB_CAA_FULL 0x06 /* fully associative */
721 721 #define SMB_CAA_8WAY 0x07 /* 8-way set associative */
722 722 #define SMB_CAA_16WAY 0x08 /* 16-way set associative */
723 723 #define SMB_CAA_12WAY 0x09 /* 12-way set associative */
724 724 #define SMB_CAA_24WAY 0x0A /* 24-way set associative */
725 725 #define SMB_CAA_32WAY 0x0B /* 32-way set associative */
726 726 #define SMB_CAA_48WAY 0x0C /* 48-way set associative */
727 727 #define SMB_CAA_64WAY 0x0D /* 64-way set associative */
728 728 #define SMB_CAA_20WAY 0x0E /* 20-way set associative */
729 729
730 730 #define SMB_CAM_WT 0x00 /* write-through */
731 731 #define SMB_CAM_WB 0x01 /* write-back */
732 732 #define SMB_CAM_VARY 0x02 /* varies by address */
733 733 #define SMB_CAM_UNKNOWN 0x03 /* unknown */
734 734
735 735 #define SMB_CAL_INTERNAL 0x00 /* internal */
736 736 #define SMB_CAL_EXTERNAL 0x01 /* external */
737 737 #define SMB_CAL_RESERVED 0x02 /* reserved */
738 738 #define SMB_CAL_UNKNOWN 0x03 /* unknown */
739 739
740 740 #define SMB_CAF_ENABLED 0x01 /* enabled at boot time */
741 741 #define SMB_CAF_SOCKETED 0x02 /* cache is socketed */
742 742
743 743 /*
744 744 * SMBIOS Port Information. See DSP0134 Section 7.9 for more information.
745 745 * The internal reference designator string is also mapped to the location.
746 746 */
747 747 typedef struct smbios_port {
748 748 const char *smbo_iref; /* internal reference designator */
749 749 const char *smbo_eref; /* external reference designator */
750 750 uint8_t smbo_itype; /* internal connector type (SMB_POC_*) */
751 751 uint8_t smbo_etype; /* external connector type (SMB_POC_*) */
752 752 uint8_t smbo_ptype; /* port type (SMB_POT_*) */
753 753 uint8_t smbo_pad; /* padding */
754 754 } smbios_port_t;
755 755
756 756 #define SMB_POC_NONE 0x00 /* none */
757 757 #define SMB_POC_CENT 0x01 /* Centronics */
758 758 #define SMB_POC_MINICENT 0x02 /* Mini-Centronics */
759 759 #define SMB_POC_PROPRIETARY 0x03 /* proprietary */
760 760 #define SMB_POC_DB25M 0x04 /* DB-25 pin male */
761 761 #define SMB_POC_DB25F 0x05 /* DB-25 pin female */
762 762 #define SMB_POC_DB15M 0x06 /* DB-15 pin male */
763 763 #define SMB_POC_DB15F 0x07 /* DB-15 pin female */
764 764 #define SMB_POC_DB9M 0x08 /* DB-9 pin male */
765 765 #define SMB_POC_DB9F 0x09 /* DB-9 pin female */
766 766 #define SMB_POC_RJ11 0x0A /* RJ-11 */
767 767 #define SMB_POC_RJ45 0x0B /* RJ-45 */
768 768 #define SMB_POC_MINISCSI 0x0C /* 50-pin MiniSCSI */
769 769 #define SMB_POC_MINIDIN 0x0D /* Mini-DIN */
770 770 #define SMB_POC_MICRODIN 0x0E /* Micro-DIN */
771 771 #define SMB_POC_PS2 0x0F /* PS/2 */
772 772 #define SMB_POC_IR 0x10 /* Infrared */
773 773 #define SMB_POC_HPHIL 0x11 /* HP-HIL */
774 774 #define SMB_POC_USB 0x12 /* USB */
775 775 #define SMB_POC_SSA 0x13 /* SSA SCSI */
776 776 #define SMB_POC_DIN8M 0x14 /* Circular DIN-8 male */
777 777 #define SMB_POC_DIN8F 0x15 /* Circular DIN-8 female */
778 778 #define SMB_POC_OBIDE 0x16 /* on-board IDE */
779 779 #define SMB_POC_OBFLOPPY 0x17 /* on-board floppy */
780 780 #define SMB_POC_DI9 0x18 /* 9p dual inline (p10 cut) */
781 781 #define SMB_POC_DI25 0x19 /* 25p dual inline (p26 cut) */
782 782 #define SMB_POC_DI50 0x1A /* 50p dual inline */
783 783 #define SMB_POC_DI68 0x1B /* 68p dual inline */
784 784 #define SMB_POC_CDROM 0x1C /* on-board sound from CDROM */
785 785 #define SMB_POC_MINI14 0x1D /* Mini-Centronics Type 14 */
786 786 #define SMB_POC_MINI26 0x1E /* Mini-Centronics Type 26 */
787 787 #define SMB_POC_MINIJACK 0x1F /* Mini-jack (headphones) */
788 788 #define SMB_POC_BNC 0x20 /* BNC */
789 789 #define SMB_POC_1394 0x21 /* 1394 */
790 790 #define SMB_POC_SATA 0x22 /* SAS/SATA plug receptacle */
791 791 #define SMB_POC_PC98 0xA0 /* PC-98 */
792 792 #define SMB_POC_PC98HR 0xA1 /* PC-98Hireso */
793 793 #define SMB_POC_PCH98 0xA2 /* PC-H98 */
794 794 #define SMB_POC_PC98NOTE 0xA3 /* PC-98Note */
795 795 #define SMB_POC_PC98FULL 0xA4 /* PC-98Full */
796 796 #define SMB_POC_OTHER 0xFF /* other */
797 797
798 798 #define SMB_POT_NONE 0x00 /* none */
799 799 #define SMB_POT_PP_XTAT 0x01 /* Parallel Port XT/AT compat */
800 800 #define SMB_POT_PP_PS2 0x02 /* Parallel Port PS/2 */
801 801 #define SMB_POT_PP_ECP 0x03 /* Parallel Port ECP */
802 802 #define SMB_POT_PP_EPP 0x04 /* Parallel Port EPP */
803 803 #define SMB_POT_PP_ECPEPP 0x05 /* Parallel Port ECP/EPP */
804 804 #define SMB_POT_SP_XTAT 0x06 /* Serial Port XT/AT compat */
805 805 #define SMB_POT_SP_16450 0x07 /* Serial Port 16450 compat */
806 806 #define SMB_POT_SP_16550 0x08 /* Serial Port 16550 compat */
807 807 #define SMB_POT_SP_16550A 0x09 /* Serial Port 16550A compat */
808 808 #define SMB_POT_SCSI 0x0A /* SCSI port */
809 809 #define SMB_POT_MIDI 0x0B /* MIDI port */
810 810 #define SMB_POT_JOYSTICK 0x0C /* Joystick port */
811 811 #define SMB_POT_KEYBOARD 0x0D /* Keyboard port */
812 812 #define SMB_POT_MOUSE 0x0E /* Mouse port */
813 813 #define SMB_POT_SSA 0x0F /* SSA SCSI */
814 814 #define SMB_POT_USB 0x10 /* USB */
815 815 #define SMB_POT_FIREWIRE 0x11 /* FireWrite (IEEE P1394) */
816 816 #define SMB_POT_PCMII 0x12 /* PCMCIA Type II */
817 817 #define SMB_POT_PCMIIa 0x13 /* PCMCIA Type II (alternate) */
818 818 #define SMB_POT_PCMIII 0x14 /* PCMCIA Type III */
819 819 #define SMB_POT_CARDBUS 0x15 /* Cardbus */
820 820 #define SMB_POT_ACCESS 0x16 /* Access Bus Port */
821 821 #define SMB_POT_SCSI2 0x17 /* SCSI II */
822 822 #define SMB_POT_SCSIW 0x18 /* SCSI Wide */
823 823 #define SMB_POT_PC98 0x19 /* PC-98 */
824 824 #define SMB_POT_PC98HR 0x1A /* PC-98Hireso */
825 825 #define SMB_POT_PCH98 0x1B /* PC-H98 */
826 826 #define SMB_POT_VIDEO 0x1C /* Video port */
827 827 #define SMB_POT_AUDIO 0x1D /* Audio port */
828 828 #define SMB_POT_MODEM 0x1E /* Modem port */
829 829 #define SMB_POT_NETWORK 0x1F /* Network port */
830 830 #define SMB_POT_SATA 0x20 /* SATA */
831 831 #define SMB_POT_SAS 0x21 /* SAS */
832 832 #define SMB_POT_8251 0xA0 /* 8251 compatible */
833 833 #define SMB_POT_8251F 0xA1 /* 8251 FIFO compatible */
834 834 #define SMB_POT_OTHER 0xFF /* other */
835 835
836 836 /*
837 837 * SMBIOS Slot Information. See DSP0134 Section 7.10 for more information.
838 838 * See DSP0134 7.10.5 for how to interpret the value of smbl_id.
839 839 */
840 840 typedef struct smbios_slot {
841 841 const char *smbl_name; /* reference designation */
842 842 uint8_t smbl_type; /* slot type */
843 843 uint8_t smbl_width; /* slot data bus width */
844 844 uint8_t smbl_usage; /* current usage */
845 845 uint8_t smbl_length; /* slot length */
846 846 uint16_t smbl_id; /* slot ID */
847 847 uint8_t smbl_ch1; /* slot characteristics 1 */
848 848 uint8_t smbl_ch2; /* slot characteristics 2 */
849 849 uint16_t smbl_sg; /* segment group number */
850 850 uint8_t smbl_bus; /* bus number */
851 851 uint8_t smbl_df; /* device/function number */
852 852 } smbios_slot_t;
853 853
854 854 #define SMB_SLT_OTHER 0x01 /* other */
855 855 #define SMB_SLT_UNKNOWN 0x02 /* unknown */
856 856 #define SMB_SLT_ISA 0x03 /* ISA */
857 857 #define SMB_SLT_MCA 0x04 /* MCA */
858 858 #define SMB_SLT_EISA 0x05 /* EISA */
859 859 #define SMB_SLT_PCI 0x06 /* PCI */
860 860 #define SMB_SLT_PCMCIA 0x07 /* PCMCIA */
861 861 #define SMB_SLT_VLVESA 0x08 /* VL-VESA */
862 862 #define SMB_SLT_PROPRIETARY 0x09 /* proprietary */
863 863 #define SMB_SLT_PROC 0x0A /* processor card slot */
864 864 #define SMB_SLT_MEM 0x0B /* proprietary memory card slot */
865 865 #define SMB_SLT_IOR 0x0C /* I/O riser card slot */
866 866 #define SMB_SLT_NUBUS 0x0D /* NuBus */
867 867 #define SMB_SLT_PCI66 0x0E /* PCI (66MHz capable) */
868 868 #define SMB_SLT_AGP 0x0F /* AGP */
869 869 #define SMB_SLT_AGP2X 0x10 /* AGP 2X */
870 870 #define SMB_SLT_AGP4X 0x11 /* AGP 4X */
871 871 #define SMB_SLT_PCIX 0x12 /* PCI-X */
872 872 #define SMB_SLT_AGP8X 0x13 /* AGP 8X */
873 873 #define SMB_SLT_PC98_C20 0xA0 /* PC-98/C20 */
874 874 #define SMB_SLT_PC98_C24 0xA1 /* PC-98/C24 */
875 875 #define SMB_SLT_PC98_E 0xA2 /* PC-98/E */
876 876 #define SMB_SLT_PC98_LB 0xA3 /* PC-98/Local Bus */
877 877 #define SMB_SLT_PC98_C 0xA4 /* PC-98/Card */
878 878 #define SMB_SLT_PCIE 0xA5 /* PCI Express */
879 879 #define SMB_SLT_PCIE1 0xA6 /* PCI Express x1 */
880 880 #define SMB_SLT_PCIE2 0xA7 /* PCI Express x2 */
881 881 #define SMB_SLT_PCIE4 0xA8 /* PCI Express x4 */
882 882 #define SMB_SLT_PCIE8 0xA9 /* PCI Express x8 */
883 883 #define SMB_SLT_PCIE16 0xAA /* PCI Express x16 */
884 884 #define SMB_SLT_PCIE2G 0xAB /* PCI Exp. Gen 2 */
885 885 #define SMB_SLT_PCIE2G1 0xAC /* PCI Exp. Gen 2 x1 */
886 886 #define SMB_SLT_PCIE2G2 0xAD /* PCI Exp. Gen 2 x2 */
887 887 #define SMB_SLT_PCIE2G4 0xAE /* PCI Exp. Gen 2 x4 */
888 888 #define SMB_SLT_PCIE2G8 0xAF /* PCI Exp. Gen 2 x8 */
889 889 #define SMB_SLT_PCIE2G16 0xB0 /* PCI Exp. Gen 2 x16 */
890 890 #define SMB_SLT_PCIE3G 0xB1 /* PCI Exp. Gen 3 */
891 891 #define SMB_SLT_PCIE3G1 0xB2 /* PCI Exp. Gen 3 x1 */
892 892 #define SMB_SLT_PCIE3G2 0xB3 /* PCI Exp. Gen 3 x2 */
893 893 #define SMB_SLT_PCIE3G4 0xB4 /* PCI Exp. Gen 3 x4 */
894 894 #define SMB_SLT_PCIE3G8 0xB5 /* PCI Exp. Gen 3 x8 */
895 895 #define SMB_SLT_PCIE3G16 0xB6 /* PCI Exp. Gen 3 x16 */
896 896
897 897 #define SMB_SLW_OTHER 0x01 /* other */
898 898 #define SMB_SLW_UNKNOWN 0x02 /* unknown */
899 899 #define SMB_SLW_8 0x03 /* 8 bit */
900 900 #define SMB_SLW_16 0x04 /* 16 bit */
901 901 #define SMB_SLW_32 0x05 /* 32 bit */
902 902 #define SMB_SLW_64 0x06 /* 64 bit */
903 903 #define SMB_SLW_128 0x07 /* 128 bit */
904 904 #define SMB_SLW_1X 0x08 /* 1x or x1 */
905 905 #define SMB_SLW_2X 0x09 /* 2x or x2 */
906 906 #define SMB_SLW_4X 0x0A /* 4x or x4 */
907 907 #define SMB_SLW_8X 0x0B /* 8x or x8 */
908 908 #define SMB_SLW_12X 0x0C /* 12x or x12 */
909 909 #define SMB_SLW_16X 0x0D /* 16x or x16 */
910 910 #define SMB_SLW_32X 0x0E /* 32x or x32 */
911 911
912 912 #define SMB_SLU_OTHER 0x01 /* other */
913 913 #define SMB_SLU_UNKNOWN 0x02 /* unknown */
914 914 #define SMB_SLU_AVAIL 0x03 /* available */
915 915 #define SMB_SLU_INUSE 0x04 /* in use */
916 916
917 917 #define SMB_SLL_OTHER 0x01 /* other */
918 918 #define SMB_SLL_UNKNOWN 0x02 /* unknown */
919 919 #define SMB_SLL_SHORT 0x03 /* short length */
920 920 #define SMB_SLL_LONG 0x04 /* long length */
921 921
922 922 #define SMB_SLCH1_UNKNOWN 0x01 /* characteristics unknown */
923 923 #define SMB_SLCH1_5V 0x02 /* provides 5.0V */
924 924 #define SMB_SLCH1_33V 0x04 /* provides 3.3V */
925 925 #define SMB_SLCH1_SHARED 0x08 /* opening shared with other slot */
926 926 #define SMB_SLCH1_PC16 0x10 /* slot supports PC Card-16 */
927 927 #define SMB_SLCH1_PCCB 0x20 /* slot supports CardBus */
928 928 #define SMB_SLCH1_PCZV 0x40 /* slot supports Zoom Video */
929 929 #define SMB_SLCH1_PCMRR 0x80 /* slot supports Modem Ring Resume */
930 930
931 931 #define SMB_SLCH2_PME 0x01 /* slot supports PME# signal */
932 932 #define SMB_SLCH2_HOTPLUG 0x02 /* slot supports hot-plug devices */
933 933 #define SMB_SLCH2_SMBUS 0x04 /* slot supports SMBus signal */
934 934
935 935 /*
936 936 * SMBIOS On-Board Device Information. See DSP0134 Section 7.11 for more
937 937 * information. Any number of on-board device sections may be present, each
938 938 * containing one or more records. The smbios_info_obdevs() function permits
939 939 * the caller to retrieve one or more of the records from a given section.
940 940 */
941 941 typedef struct smbios_obdev {
942 942 const char *smbd_name; /* description string for this device */
943 943 uint8_t smbd_type; /* type code (SMB_OBT_*) */
944 944 uint8_t smbd_enabled; /* boolean (device is enabled) */
945 945 } smbios_obdev_t;
946 946
947 947 #define SMB_OBT_OTHER 0x01 /* other */
948 948 #define SMB_OBT_UNKNOWN 0x02 /* unknown */
949 949 #define SMB_OBT_VIDEO 0x03 /* video */
950 950 #define SMB_OBT_SCSI 0x04 /* scsi */
951 951 #define SMB_OBT_ETHERNET 0x05 /* ethernet */
952 952 #define SMB_OBT_TOKEN 0x06 /* token ring */
953 953 #define SMB_OBT_SOUND 0x07 /* sound */
954 954 #define SMB_OBT_PATA 0x08 /* pata */
955 955 #define SMB_OBT_SATA 0x09 /* sata */
956 956 #define SMB_OBT_SAS 0x0A /* sas */
957 957
958 958 /*
959 959 * SMBIOS BIOS Language Information. See DSP0134 Section 7.14 for more
960 960 * information. The smbios_info_strtab() function can be applied using a
961 961 * count of smbla_num to retrieve the other possible language settings.
962 962 */
963 963 typedef struct smbios_lang {
964 964 const char *smbla_cur; /* current language setting */
965 965 uint_t smbla_fmt; /* language name format (see below) */
966 966 uint_t smbla_num; /* number of installed languages */
967 967 } smbios_lang_t;
968 968
969 969 #define SMB_LFMT_LONG 0 /* <ISO639>|<ISO3166>|Encoding Method */
970 970 #define SMB_LFMT_SHORT 1 /* <ISO930><ISO3166> */
971 971
972 972 /*
973 973 * SMBIOS System Event Log Information. See DSP0134 Section 7.16 for more
974 974 * information. Accessing the event log itself requires additional interfaces.
975 975 */
976 976 typedef struct smbios_evtype {
977 977 uint8_t smbevt_ltype; /* log type */
978 978 uint8_t smbevt_dtype; /* variable data format type */
979 979 } smbios_evtype_t;
980 980
981 981 typedef struct smbios_evlog {
982 982 size_t smbev_size; /* size in bytes of log area */
983 983 size_t smbev_hdr; /* offset or index of header */
984 984 size_t smbev_data; /* offset or index of data */
985 985 uint8_t smbev_method; /* data access method (see below) */
986 986 uint8_t smbev_flags; /* flags (see below) */
987 987 uint8_t smbev_format; /* log header format (see below) */
988 988 uint8_t smbev_pad; /* padding */
989 989 uint32_t smbev_token; /* data update change token */
990 990 union {
991 991 struct {
992 992 uint16_t evi_iaddr; /* index address */
993 993 uint16_t evi_daddr; /* data address */
994 994 } eva_io; /* i/o address for SMB_EVM_XxY */
995 995 uint32_t eva_addr; /* address for SMB_EVM_MEM32 */
996 996 uint16_t eva_gpnv; /* handle for SMB_EVM_GPNV */
997 997 } smbev_addr;
998 998 uint32_t smbev_typec; /* number of type descriptors */
999 999 const smbios_evtype_t *smbev_typev; /* type descriptor array */
1000 1000 } smbios_evlog_t;
1001 1001
1002 1002 #define SMB_EVM_1x1i_1x1d 0 /* I/O: 1 1b idx port, 1 1b data port */
1003 1003 #define SMB_EVM_2x1i_1x1d 1 /* I/O: 2 1b idx port, 1 1b data port */
1004 1004 #define SMB_EVM_1x2i_1x1d 2 /* I/O: 1 2b idx port, 1 1b data port */
1005 1005 #define SMB_EVM_MEM32 3 /* Memory-Mapped 32-bit Physical Addr */
1006 1006 #define SMB_EVM_GPNV 4 /* GP Non-Volatile API Access */
1007 1007
1008 1008 #define SMB_EVFL_VALID 0x1 /* log area valid */
1009 1009 #define SMB_EVFL_FULL 0x2 /* log area full */
1010 1010
1011 1011 #define SMB_EVHF_NONE 0 /* no log headers used */
1012 1012 #define SMB_EVHF_F1 1 /* DMTF log header type 1 */
1013 1013
1014 1014 /*
1015 1015 * SMBIOS Physical Memory Array Information. See DSP0134 Section 7.17 for
1016 1016 * more information. This describes a collection of physical memory devices.
1017 1017 */
1018 1018 typedef struct smbios_memarray {
1019 1019 uint8_t smbma_location; /* physical device location */
1020 1020 uint8_t smbma_use; /* physical device functional purpose */
1021 1021 uint8_t smbma_ecc; /* error detect/correct mechanism */
1022 1022 uint8_t smbma_pad0; /* padding */
1023 1023 uint32_t smbma_pad1; /* padding */
1024 1024 uint32_t smbma_ndevs; /* number of slots or sockets */
1025 1025 id_t smbma_err; /* handle of error (if any) */
1026 1026 uint64_t smbma_size; /* maximum capacity in bytes */
1027 1027 } smbios_memarray_t;
1028 1028
1029 1029 #define SMB_MAL_OTHER 0x01 /* other */
1030 1030 #define SMB_MAL_UNKNOWN 0x02 /* unknown */
1031 1031 #define SMB_MAL_SYSMB 0x03 /* system board or motherboard */
1032 1032 #define SMB_MAL_ISA 0x04 /* ISA add-on card */
1033 1033 #define SMB_MAL_EISA 0x05 /* EISA add-on card */
1034 1034 #define SMB_MAL_PCI 0x06 /* PCI add-on card */
1035 1035 #define SMB_MAL_MCA 0x07 /* MCA add-on card */
1036 1036 #define SMB_MAL_PCMCIA 0x08 /* PCMCIA add-on card */
1037 1037 #define SMB_MAL_PROP 0x09 /* proprietary add-on card */
1038 1038 #define SMB_MAL_NUBUS 0x0A /* NuBus */
1039 1039 #define SMB_MAL_PC98C20 0xA0 /* PC-98/C20 add-on card */
1040 1040 #define SMB_MAL_PC98C24 0xA1 /* PC-98/C24 add-on card */
1041 1041 #define SMB_MAL_PC98E 0xA2 /* PC-98/E add-on card */
1042 1042 #define SMB_MAL_PC98LB 0xA3 /* PC-98/Local bus add-on card */
1043 1043
1044 1044 #define SMB_MAU_OTHER 0x01 /* other */
1045 1045 #define SMB_MAU_UNKNOWN 0x02 /* unknown */
1046 1046 #define SMB_MAU_SYSTEM 0x03 /* system memory */
1047 1047 #define SMB_MAU_VIDEO 0x04 /* video memory */
1048 1048 #define SMB_MAU_FLASH 0x05 /* flash memory */
1049 1049 #define SMB_MAU_NVRAM 0x06 /* non-volatile RAM */
1050 1050 #define SMB_MAU_CACHE 0x07 /* cache memory */
1051 1051
1052 1052 #define SMB_MAE_OTHER 0x01 /* other */
1053 1053 #define SMB_MAE_UNKNOWN 0x02 /* unknown */
1054 1054 #define SMB_MAE_NONE 0x03 /* none */
1055 1055 #define SMB_MAE_PARITY 0x04 /* parity */
1056 1056 #define SMB_MAE_SECC 0x05 /* single-bit ECC */
1057 1057 #define SMB_MAE_MECC 0x06 /* multi-bit ECC */
1058 1058 #define SMB_MAE_CRC 0x07 /* CRC */
1059 1059
1060 1060 /*
1061 1061 * SMBIOS Memory Device Information. See DSP0134 Section 7.19 for more
1062 1062 * information. One or more of these structures are associated with each
1063 1063 * smbios_memarray_t. A structure is present even for unpopulated sockets.
1064 1064 * Unknown values are set to -1. A smbmd_size of 0 indicates unpopulated.
1065 1065 * WARNING: Some BIOSes appear to export the *maximum* size of the device
1066 1066 * that can appear in the corresponding socket as opposed to the current one.
1067 1067 */
1068 1068 typedef struct smbios_memdevice {
1069 1069 id_t smbmd_array; /* handle of physical memory array */
1070 1070 id_t smbmd_error; /* handle of memory error data */
1071 1071 uint32_t smbmd_twidth; /* total width in bits including ecc */
1072 1072 uint32_t smbmd_dwidth; /* data width in bits */
1073 1073 uint64_t smbmd_size; /* size in bytes (see note above) */
1074 1074 uint8_t smbmd_form; /* form factor */
1075 1075 uint8_t smbmd_set; /* set (0x00=none, 0xFF=unknown) */
1076 1076 uint8_t smbmd_type; /* memory type */
1077 1077 uint8_t smbmd_pad; /* padding */
1078 1078 uint32_t smbmd_flags; /* flags (see below) */
1079 1079 uint32_t smbmd_speed; /* speed in MHz */
1080 1080 const char *smbmd_dloc; /* physical device locator string */
1081 1081 const char *smbmd_bloc; /* physical bank locator string */
1082 1082 uint8_t smbmd_rank; /* rank */
1083 1083 uint16_t smbmd_clkspeed; /* configured clock speed */
1084 1084 uint16_t smbmd_minvolt; /* minimum voltage */
1085 1085 uint16_t smbmd_maxvolt; /* maximum voltage */
1086 1086 uint16_t smbmd_confvolt; /* configured voltage */
1087 1087 } smbios_memdevice_t;
1088 1088
1089 1089 #define SMB_MDFF_OTHER 0x01 /* other */
1090 1090 #define SMB_MDFF_UNKNOWN 0x02 /* unknown */
1091 1091 #define SMB_MDFF_SIMM 0x03 /* SIMM */
1092 1092 #define SMB_MDFF_SIP 0x04 /* SIP */
1093 1093 #define SMB_MDFF_CHIP 0x05 /* chip */
1094 1094 #define SMB_MDFF_DIP 0x06 /* DIP */
1095 1095 #define SMB_MDFF_ZIP 0x07 /* ZIP */
1096 1096 #define SMB_MDFF_PROP 0x08 /* proprietary card */
1097 1097 #define SMB_MDFF_DIMM 0x09 /* DIMM */
1098 1098 #define SMB_MDFF_TSOP 0x0A /* TSOP */
1099 1099 #define SMB_MDFF_CHIPROW 0x0B /* row of chips */
1100 1100 #define SMB_MDFF_RIMM 0x0C /* RIMM */
1101 1101 #define SMB_MDFF_SODIMM 0x0D /* SODIMM */
1102 1102 #define SMB_MDFF_SRIMM 0x0E /* SRIMM */
1103 1103 #define SMB_MDFF_FBDIMM 0x0F /* FBDIMM */
1104 1104
1105 1105 #define SMB_MDT_OTHER 0x01 /* other */
1106 1106 #define SMB_MDT_UNKNOWN 0x02 /* unknown */
1107 1107 #define SMB_MDT_DRAM 0x03 /* DRAM */
1108 1108 #define SMB_MDT_EDRAM 0x04 /* EDRAM */
1109 1109 #define SMB_MDT_VRAM 0x05 /* VRAM */
1110 1110 #define SMB_MDT_SRAM 0x06 /* SRAM */
1111 1111 #define SMB_MDT_RAM 0x07 /* RAM */
1112 1112 #define SMB_MDT_ROM 0x08 /* ROM */
1113 1113 #define SMB_MDT_FLASH 0x09 /* FLASH */
1114 1114 #define SMB_MDT_EEPROM 0x0A /* EEPROM */
1115 1115 #define SMB_MDT_FEPROM 0x0B /* FEPROM */
1116 1116 #define SMB_MDT_EPROM 0x0C /* EPROM */
1117 1117 #define SMB_MDT_CDRAM 0x0D /* CDRAM */
1118 1118 #define SMB_MDT_3DRAM 0x0E /* 3DRAM */
1119 1119 #define SMB_MDT_SDRAM 0x0F /* SDRAM */
1120 1120 #define SMB_MDT_SGRAM 0x10 /* SGRAM */
1121 1121 #define SMB_MDT_RDRAM 0x11 /* RDRAM */
1122 1122 #define SMB_MDT_DDR 0x12 /* DDR */
1123 1123 #define SMB_MDT_DDR2 0x13 /* DDR2 */
1124 1124 #define SMB_MDT_DDR2FBDIMM 0x14 /* DDR2 FBDIMM */
1125 1125 #define SMB_MDT_DDR3 0x18 /* DDR3 */
1126 1126 #define SMB_MDT_FBD2 0x19 /* FBD2 */
1127 1127
1128 1128 #define SMB_MDF_OTHER 0x0002 /* other */
1129 1129 #define SMB_MDF_UNKNOWN 0x0004 /* unknown */
1130 1130 #define SMB_MDF_FASTPG 0x0008 /* fast-paged */
1131 1131 #define SMB_MDF_STATIC 0x0010 /* static column */
1132 1132 #define SMB_MDF_PSTATIC 0x0020 /* pseudo-static */
1133 1133 #define SMB_MDF_RAMBUS 0x0040 /* RAMBUS */
1134 1134 #define SMB_MDF_SYNC 0x0080 /* synchronous */
1135 1135 #define SMB_MDF_CMOS 0x0100 /* CMOS */
1136 1136 #define SMB_MDF_EDO 0x0200 /* EDO */
1137 1137 #define SMB_MDF_WDRAM 0x0400 /* Window DRAM */
1138 1138 #define SMB_MDF_CDRAM 0x0800 /* Cache DRAM */
1139 1139 #define SMB_MDF_NV 0x1000 /* non-volatile */
1140 1140 #define SMB_MDF_REG 0x2000 /* Registered (Buffered) */
1141 1141 #define SMB_MDF_UNREG 0x4000 /* Unregistered (Unbuffered) */
1142 1142 #define SMB_MDF_LRDIMM 0x8000 /* LRDIMM */
1143 1143
1144 1144 #define SMB_MDR_SINGLE 0x01 /* single */
1145 1145 #define SMB_MDR_DUAL 0x02 /* dual */
1146 1146 #define SMB_MDR_QUAD 0x04 /* quad */
1147 1147 #define SMB_MDR_OCTAL 0x08 /* octal */
1148 1148
1149 1149 /*
1150 1150 * SMBIOS Memory Array Mapped Address. See DSP0134 Section 7.20 for more
1151 1151 * information. We convert start/end addresses into addr/size for convenience.
1152 1152 */
1153 1153 typedef struct smbios_memarrmap {
1154 1154 id_t smbmam_array; /* physical memory array handle */
1155 1155 uint32_t smbmam_width; /* number of devices that form a row */
1156 1156 uint64_t smbmam_addr; /* physical address of mapping */
1157 1157 uint64_t smbmam_size; /* size in bytes of address range */
1158 1158 } smbios_memarrmap_t;
1159 1159
1160 1160 /*
1161 1161 * SMBIOS Memory Device Mapped Address. See DSP0134 Section 7.21 for more
1162 1162 * information. We convert start/end addresses into addr/size for convenience.
1163 1163 */
1164 1164 typedef struct smbios_memdevmap {
1165 1165 id_t smbmdm_device; /* memory device handle */
1166 1166 id_t smbmdm_arrmap; /* memory array mapped address handle */
1167 1167 uint64_t smbmdm_addr; /* physical address of mapping */
1168 1168 uint64_t smbmdm_size; /* size in bytes of address range */
1169 1169 uint8_t smbmdm_rpos; /* partition row position */
1170 1170 uint8_t smbmdm_ipos; /* interleave position */
1171 1171 uint8_t smbmdm_idepth; /* interleave data depth */
1172 1172 } smbios_memdevmap_t;
1173 1173
1174 1174 /*
1175 1175 * SMBIOS Hardware Security Settings. See DSP0134 Section 7.25 for more
1176 1176 * information. Only one such record will be present in the SMBIOS.
1177 1177 */
1178 1178 typedef struct smbios_hwsec {
1179 1179 uint8_t smbh_pwr_ps; /* power-on password status */
1180 1180 uint8_t smbh_kbd_ps; /* keyboard password status */
1181 1181 uint8_t smbh_adm_ps; /* administrator password status */
1182 1182 uint8_t smbh_pan_ps; /* front panel reset status */
1183 1183 } smbios_hwsec_t;
1184 1184
1185 1185 #define SMB_HWSEC_PS_DISABLED 0x00 /* password disabled */
1186 1186 #define SMB_HWSEC_PS_ENABLED 0x01 /* password enabled */
1187 1187 #define SMB_HWSEC_PS_NOTIMPL 0x02 /* password not implemented */
1188 1188 #define SMB_HWSEC_PS_UNKNOWN 0x03 /* password status unknown */
1189 1189
1190 1190 /*
1191 1191 * SMBIOS System Boot Information. See DSP0134 Section 7.33 for more
1192 1192 * information. The contents of the data varies by type and is undocumented
1193 1193 * from the perspective of DSP0134 -- it seems to be left as vendor-specific.
1194 1194 * The (D) annotation next to SMB_BOOT_* below indicates possible data payload.
1195 1195 */
1196 1196 typedef struct smbios_boot {
1197 1197 uint8_t smbt_status; /* boot status code (see below) */
1198 1198 const void *smbt_data; /* data buffer specific to status */
1199 1199 size_t smbt_size; /* size of smbt_data buffer in bytes */
1200 1200 } smbios_boot_t;
1201 1201
1202 1202 #define SMB_BOOT_NORMAL 0 /* no errors detected */
1203 1203 #define SMB_BOOT_NOMEDIA 1 /* no bootable media */
1204 1204 #define SMB_BOOT_OSFAIL 2 /* normal o/s failed to load */
1205 1205 #define SMB_BOOT_FWHWFAIL 3 /* firmware-detected hardware failure */
1206 1206 #define SMB_BOOT_OSHWFAIL 4 /* o/s-detected hardware failure */
1207 1207 #define SMB_BOOT_USERREQ 5 /* user-requested boot (keystroke) */
1208 1208 #define SMB_BOOT_SECURITY 6 /* system security violation */
1209 1209 #define SMB_BOOT_PREVREQ 7 /* previously requested image (D) */
1210 1210 #define SMB_BOOT_WATCHDOG 8 /* watchdog initiated reboot */
1211 1211 #define SMB_BOOT_RESV_LO 9 /* low end of reserved range */
1212 1212 #define SMB_BOOT_RESV_HI 127 /* high end of reserved range */
1213 1213 #define SMB_BOOT_OEM_LO 128 /* low end of OEM-specific range */
1214 1214 #define SMB_BOOT_OEM_HI 191 /* high end of OEM-specific range */
1215 1215 #define SMB_BOOT_PROD_LO 192 /* low end of product-specific range */
1216 1216 #define SMB_BOOT_PROD_HI 255 /* high end of product-specific range */
1217 1217
1218 1218 /*
1219 1219 * SMBIOS IPMI Device Information. See DSP0134 Section 7.39 and also
1220 1220 * Appendix C1 of the IPMI specification for more information on this record.
1221 1221 */
1222 1222 typedef struct smbios_ipmi {
1223 1223 uint_t smbip_type; /* BMC interface type */
1224 1224 smbios_version_t smbip_vers; /* BMC's IPMI specification version */
1225 1225 uint32_t smbip_i2c; /* BMC I2C bus slave address */
1226 1226 uint32_t smbip_bus; /* bus ID of NV storage device, or -1 */
1227 1227 uint64_t smbip_addr; /* BMC base address */
1228 1228 uint32_t smbip_flags; /* flags (see below) */
1229 1229 uint16_t smbip_intr; /* interrupt number (or zero if none) */
1230 1230 uint16_t smbip_regspacing; /* i/o space register spacing (bytes) */
1231 1231 } smbios_ipmi_t;
1232 1232
1233 1233 #define SMB_IPMI_T_UNKNOWN 0x00 /* unknown */
1234 1234 #define SMB_IPMI_T_KCS 0x01 /* KCS: Keyboard Controller Style */
1235 1235 #define SMB_IPMI_T_SMIC 0x02 /* SMIC: Server Mgmt Interface Chip */
1236 1236 #define SMB_IPMI_T_BT 0x03 /* BT: Block Transfer */
1237 1237 #define SMB_IPMI_T_SSIF 0x04 /* SSIF: SMBus System Interface */
1238 1238
1239 1239 #define SMB_IPMI_F_IOADDR 0x01 /* base address is in i/o space */
1240 1240 #define SMB_IPMI_F_INTRSPEC 0x02 /* intr information is specified */
1241 1241 #define SMB_IPMI_F_INTRHIGH 0x04 /* intr active high (else low) */
1242 1242 #define SMB_IPMI_F_INTREDGE 0x08 /* intr is edge triggered (else lvl) */
1243 1243
1244 1244 /*
1245 1245 * SMBIOS Onboard Devices Extended Information. See DSP0134 Section 7.42
1246 1246 * for more information.
1247 1247 */
1248 1248 typedef struct smbios_obdev_ext {
1249 1249 const char *smboe_name; /* reference designation */
1250 1250 uint8_t smboe_dtype; /* device type */
1251 1251 uint8_t smboe_dti; /* device type instance */
1252 1252 uint16_t smboe_sg; /* segment group number */
1253 1253 uint8_t smboe_bus; /* bus number */
1254 1254 uint8_t smboe_df; /* device/function number */
1255 1255 } smbios_obdev_ext_t;
1256 1256
1257 1257
1258 1258 /*
1259 1259 * SMBIOS OEM-specific (Type 132) Processor Extended Information.
1260 1260 */
1261 1261 typedef struct smbios_processor_ext {
1262 1262 uint16_t smbpe_processor; /* extending processor handle */
1263 1263 uint8_t smbpe_fru; /* FRU indicaor */
1264 1264 uint8_t smbpe_n; /* number of APIC IDs */
1265 1265 uint16_t *smbpe_apicid; /* strand Inital APIC IDs */
1266 1266 } smbios_processor_ext_t;
1267 1267
1268 1268 /*
1269 1269 * SMBIOS OEM-specific (Type 136) Port Extended Information.
1270 1270 */
1271 1271 typedef struct smbios_port_ext {
1272 1272 uint16_t smbporte_chassis; /* chassis handle */
1273 1273 uint16_t smbporte_port; /* port connector handle */
1274 1274 uint8_t smbporte_dtype; /* device type */
1275 1275 uint16_t smbporte_devhdl; /* device handle */
1276 1276 uint8_t smbporte_phy; /* PHY number */
1277 1277 } smbios_port_ext_t;
1278 1278
1279 1279 /*
1280 1280 * SMBIOS OEM-specific (Type 138) PCI-Express RC/RP Information.
1281 1281 */
1282 1282 typedef struct smbios_pciexrc {
1283 1283 uint16_t smbpcie_bb; /* base board handle */
1284 1284 uint16_t smbpcie_bdf; /* Bus/Dev/Funct (PCI) */
1285 1285 } smbios_pciexrc_t;
1286 1286
1287 1287 /*
1288 1288 * SMBIOS OEM-specific (Type 144) Memory Array Extended Information.
1289 1289 */
1290 1290 typedef struct smbios_memarray_ext {
1291 1291 uint16_t smbmae_ma; /* memory array handle */
1292 1292 uint16_t smbmae_comp; /* component parent handle */
1293 1293 uint16_t smbmae_bdf; /* Bus/Dev/Funct (PCI) */
1294 1294 } smbios_memarray_ext_t;
1295 1295
1296 1296 /*
1297 1297 * SMBIOS OEM-specific (Type 145) Memory Device Extended Information.
1298 1298 */
1299 1299 typedef struct smbios_memdevice_ext {
1300 1300 uint16_t smbmdeve_md; /* memory device handle */
1301 1301 uint8_t smbmdeve_drch; /* DRAM channel */
1302 1302 uint8_t smbmdeve_ncs; /* number of chip selects */
1303 1303 uint8_t *smbmdeve_cs; /* array of chip select numbers */
1304 1304 } smbios_memdevice_ext_t;
1305 1305
1306 1306 /*
1307 1307 * SMBIOS Interfaces. An SMBIOS image can be opened by either providing a file
1308 1308 * pathname, device pathname, file descriptor, or raw memory buffer. Once an
1309 1309 * image is opened the functions below can be used to iterate over the various
1310 1310 * structures and convert the underlying data representation into the simpler
1311 1311 * data structures described earlier in this header file. The SMB_VERSION
1312 1312 * constant specified when opening an image indicates the version of the ABI
1313 1313 * the caller expects and the DMTF SMBIOS version the client can understand.
1314 1314 * The library will then map older or newer data structures to that as needed.
1315 1315 */
1316 1316
1317 1317 #define SMB_VERSION_23 0x0203 /* SMBIOS encoding for DMTF spec 2.3 */
1318 1318 #define SMB_VERSION_24 0x0204 /* SMBIOS encoding for DMTF spec 2.4 */
1319 1319 #define SMB_VERSION_25 0x0205 /* SMBIOS encoding for DMTF spec 2.5 */
1320 1320 #define SMB_VERSION_26 0x0206 /* SMBIOS encoding for DMTF spec 2.6 */
1321 1321 #define SMB_VERSION_27 0x0207 /* SMBIOS encoding for DMTF spec 2.7 */
1322 1322 #define SMB_VERSION_28 0x0208 /* SMBIOS encoding for DMTF spec 2.8 */
1323 1323 #define SMB_VERSION SMB_VERSION_28 /* SMBIOS latest version definitions */
1324 1324
1325 1325 #define SMB_O_NOCKSUM 0x1 /* do not verify header checksums */
1326 1326 #define SMB_O_NOVERS 0x2 /* do not verify header versions */
1327 1327 #define SMB_O_ZIDS 0x4 /* strip out identification numbers */
1328 1328 #define SMB_O_MASK 0x7 /* mask of valid smbios_*open flags */
1329 1329
1330 1330 #define SMB_ID_NOTSUP 0xFFFE /* structure is not supported by BIOS */
1331 1331 #define SMB_ID_NONE 0xFFFF /* structure is a null reference */
1332 1332
1333 1333 #define SMB_ERR (-1) /* id_t value indicating error */
1334 1334
1335 1335 typedef struct smbios_hdl smbios_hdl_t;
1336 1336
1337 1337 typedef struct smbios_struct {
1338 1338 id_t smbstr_id; /* structure ID handle */
1339 1339 uint_t smbstr_type; /* structure type */
1340 1340 const void *smbstr_data; /* structure data */
1341 1341 size_t smbstr_size; /* structure size */
1342 1342 } smbios_struct_t;
1343 1343
1344 1344 typedef int smbios_struct_f(smbios_hdl_t *,
1345 1345 const smbios_struct_t *, void *);
1346 1346
1347 1347 extern smbios_hdl_t *smbios_open(const char *, int, int, int *);
1348 1348 extern smbios_hdl_t *smbios_fdopen(int, int, int, int *);
1349 1349 extern smbios_hdl_t *smbios_bufopen(const smbios_entry_t *,
1350 1350 const void *, size_t, int, int, int *);
1351 1351
1352 1352 extern const void *smbios_buf(smbios_hdl_t *);
1353 1353 extern size_t smbios_buflen(smbios_hdl_t *);
1354 1354
1355 1355 extern void smbios_checksum(smbios_hdl_t *, smbios_entry_t *);
1356 1356 extern int smbios_write(smbios_hdl_t *, int);
1357 1357 extern void smbios_close(smbios_hdl_t *);
1358 1358
1359 1359 extern int smbios_errno(smbios_hdl_t *);
1360 1360 extern const char *smbios_errmsg(int);
1361 1361
1362 1362 extern int smbios_lookup_id(smbios_hdl_t *, id_t, smbios_struct_t *);
1363 1363 extern int smbios_lookup_type(smbios_hdl_t *, uint_t, smbios_struct_t *);
1364 1364 extern int smbios_iter(smbios_hdl_t *, smbios_struct_f *, void *);
1365 1365
1366 1366 extern void smbios_info_smbios(smbios_hdl_t *, smbios_entry_t *);
1367 1367 extern int smbios_info_common(smbios_hdl_t *, id_t, smbios_info_t *);
1368 1368 extern int smbios_info_contains(smbios_hdl_t *, id_t, uint_t, id_t *);
1369 1369 extern id_t smbios_info_bios(smbios_hdl_t *, smbios_bios_t *);
1370 1370 extern id_t smbios_info_system(smbios_hdl_t *, smbios_system_t *);
1371 1371 extern int smbios_info_bboard(smbios_hdl_t *, id_t, smbios_bboard_t *);
1372 1372 extern int smbios_info_chassis(smbios_hdl_t *, id_t, smbios_chassis_t *);
1373 1373 extern int smbios_info_processor(smbios_hdl_t *, id_t, smbios_processor_t *);
1374 1374 extern int smbios_info_extprocessor(smbios_hdl_t *, id_t,
1375 1375 smbios_processor_ext_t *);
1376 1376 extern int smbios_info_cache(smbios_hdl_t *, id_t, smbios_cache_t *);
1377 1377 extern int smbios_info_port(smbios_hdl_t *, id_t, smbios_port_t *);
1378 1378 extern int smbios_info_extport(smbios_hdl_t *, id_t, smbios_port_ext_t *);
1379 1379 extern int smbios_info_slot(smbios_hdl_t *, id_t, smbios_slot_t *);
1380 1380 extern int smbios_info_obdevs(smbios_hdl_t *, id_t, int, smbios_obdev_t *);
1381 1381 extern int smbios_info_obdevs_ext(smbios_hdl_t *, id_t, smbios_obdev_ext_t *);
1382 1382 extern int smbios_info_strtab(smbios_hdl_t *, id_t, int, const char *[]);
1383 1383 extern id_t smbios_info_lang(smbios_hdl_t *, smbios_lang_t *);
1384 1384 extern id_t smbios_info_eventlog(smbios_hdl_t *, smbios_evlog_t *);
1385 1385 extern int smbios_info_memarray(smbios_hdl_t *, id_t, smbios_memarray_t *);
1386 1386 extern int smbios_info_extmemarray(smbios_hdl_t *, id_t,
1387 1387 smbios_memarray_ext_t *);
1388 1388 extern int smbios_info_memarrmap(smbios_hdl_t *, id_t, smbios_memarrmap_t *);
1389 1389 extern int smbios_info_memdevice(smbios_hdl_t *, id_t, smbios_memdevice_t *);
1390 1390 extern int smbios_info_extmemdevice(smbios_hdl_t *, id_t,
1391 1391 smbios_memdevice_ext_t *);
1392 1392 extern int smbios_info_memdevmap(smbios_hdl_t *, id_t, smbios_memdevmap_t *);
1393 1393 extern id_t smbios_info_hwsec(smbios_hdl_t *, smbios_hwsec_t *);
1394 1394 extern id_t smbios_info_boot(smbios_hdl_t *, smbios_boot_t *);
1395 1395 extern id_t smbios_info_ipmi(smbios_hdl_t *, smbios_ipmi_t *);
1396 1396 extern int smbios_info_pciexrc(smbios_hdl_t *, id_t, smbios_pciexrc_t *);
1397 1397
1398 1398 extern const char *smbios_psn(smbios_hdl_t *);
1399 1399 extern const char *smbios_csn(smbios_hdl_t *);
1400 1400
1401 1401 #ifndef _KERNEL
1402 1402 /*
1403 1403 * The smbios_*_desc() and smbios_*_name() interfaces can be used for utilities
1404 1404 * such as smbios(1M) that wish to decode SMBIOS fields for humans. The _desc
1405 1405 * functions return the comment string next to the #defines listed above, and
1406 1406 * the _name functions return the appropriate #define identifier itself.
1407 1407 */
1408 1408 extern const char *smbios_bboard_flag_desc(uint_t);
1409 1409 extern const char *smbios_bboard_flag_name(uint_t);
1410 1410 extern const char *smbios_bboard_type_desc(uint_t);
1411 1411
1412 1412 extern const char *smbios_bios_flag_desc(uint64_t);
1413 1413 extern const char *smbios_bios_flag_name(uint64_t);
1414 1414
1415 1415 extern const char *smbios_bios_xb1_desc(uint_t);
1416 1416 extern const char *smbios_bios_xb1_name(uint_t);
1417 1417 extern const char *smbios_bios_xb2_desc(uint_t);
1418 1418 extern const char *smbios_bios_xb2_name(uint_t);
1419 1419
1420 1420 extern const char *smbios_boot_desc(uint_t);
1421 1421
1422 1422 extern const char *smbios_cache_assoc_desc(uint_t);
1423 1423 extern const char *smbios_cache_ctype_desc(uint_t);
1424 1424 extern const char *smbios_cache_ctype_name(uint_t);
1425 1425 extern const char *smbios_cache_ecc_desc(uint_t);
1426 1426 extern const char *smbios_cache_flag_desc(uint_t);
1427 1427 extern const char *smbios_cache_flag_name(uint_t);
1428 1428 extern const char *smbios_cache_loc_desc(uint_t);
1429 1429 extern const char *smbios_cache_logical_desc(uint_t);
1430 1430 extern const char *smbios_cache_mode_desc(uint_t);
1431 1431
1432 1432 extern const char *smbios_chassis_state_desc(uint_t);
1433 1433 extern const char *smbios_chassis_type_desc(uint_t);
1434 1434
1435 1435 extern const char *smbios_evlog_flag_desc(uint_t);
1436 1436 extern const char *smbios_evlog_flag_name(uint_t);
1437 1437 extern const char *smbios_evlog_format_desc(uint_t);
1438 1438 extern const char *smbios_evlog_method_desc(uint_t);
1439 1439
1440 1440 extern const char *smbios_ipmi_flag_name(uint_t);
1441 1441 extern const char *smbios_ipmi_flag_desc(uint_t);
1442 1442 extern const char *smbios_ipmi_type_desc(uint_t);
1443 1443
1444 1444 extern const char *smbios_hwsec_desc(uint_t);
1445 1445
1446 1446 extern const char *smbios_memarray_loc_desc(uint_t);
1447 1447 extern const char *smbios_memarray_use_desc(uint_t);
1448 1448 extern const char *smbios_memarray_ecc_desc(uint_t);
1449 1449
1450 1450 extern const char *smbios_memdevice_form_desc(uint_t);
1451 1451 extern const char *smbios_memdevice_type_desc(uint_t);
1452 1452 extern const char *smbios_memdevice_flag_name(uint_t);
1453 1453 extern const char *smbios_memdevice_flag_desc(uint_t);
1454 1454 extern const char *smbios_memdevice_rank_desc(uint_t);
1455 1455
1456 1456 extern const char *smbios_port_conn_desc(uint_t);
1457 1457 extern const char *smbios_port_type_desc(uint_t);
1458 1458
1459 1459 extern const char *smbios_processor_family_desc(uint_t);
1460 1460 extern const char *smbios_processor_status_desc(uint_t);
1461 1461 extern const char *smbios_processor_type_desc(uint_t);
1462 1462 extern const char *smbios_processor_upgrade_desc(uint_t);
1463 1463 extern const char *smbios_processor_core_flag_name(uint_t);
1464 1464 extern const char *smbios_processor_core_flag_desc(uint_t);
1465 1465
1466 1466 extern const char *smbios_slot_type_desc(uint_t);
1467 1467 extern const char *smbios_slot_width_desc(uint_t);
1468 1468 extern const char *smbios_slot_usage_desc(uint_t);
1469 1469 extern const char *smbios_slot_length_desc(uint_t);
1470 1470 extern const char *smbios_slot_ch1_desc(uint_t);
1471 1471 extern const char *smbios_slot_ch1_name(uint_t);
1472 1472 extern const char *smbios_slot_ch2_desc(uint_t);
1473 1473 extern const char *smbios_slot_ch2_name(uint_t);
1474 1474
1475 1475 extern const char *smbios_type_desc(uint_t);
1476 1476 extern const char *smbios_type_name(uint_t);
1477 1477
1478 1478 extern const char *smbios_system_wakeup_desc(uint_t);
1479 1479 #endif /* !_KERNEL */
1480 1480
1481 1481 #ifdef _KERNEL
1482 1482 /*
1483 1483 * For SMBIOS clients within the kernel itself, ksmbios is used to refer to
1484 1484 * the kernel's current snapshot of the SMBIOS, if one exists, and the
1485 1485 * ksmbios_flags tunable is the set of flags for use with smbios_open().
1486 1486 */
1487 1487 extern smbios_hdl_t *ksmbios;
1488 1488 extern int ksmbios_flags;
1489 1489 #endif /* _KERNEL */
1490 1490
1491 1491 #ifdef __cplusplus
1492 1492 }
1493 1493 #endif
1494 1494
1495 1495 #endif /* _SYS_SMBIOS_H */
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