2004 m->m_next = mpt->m_next;
2005 break;
2006 }
2007 }
2008 if (m == NULL) {
2009 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2010 }
2011 }
2012
2013 if (mptsas_tail == mpt) {
2014 mptsas_tail = m;
2015 }
2016 rw_exit(&mptsas_global_rwlock);
2017 }
2018
2019 static int
2020 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2021 {
2022 ddi_dma_attr_t task_dma_attrs;
2023
2024 task_dma_attrs = mpt->m_msg_dma_attr;
2025 task_dma_attrs.dma_attr_sgllen = 1;
2026 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2027
2028 /* allocate Task Management ddi_dma resources */
2029 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2030 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2031 alloc_size, NULL) == FALSE) {
2032 return (DDI_FAILURE);
2033 }
2034 mpt->m_hshk_dma_size = alloc_size;
2035
2036 return (DDI_SUCCESS);
2037 }
2038
2039 static void
2040 mptsas_free_handshake_msg(mptsas_t *mpt)
2041 {
2042 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2043 mpt->m_hshk_dma_size = 0;
2044 }
2045
2046 static int
2047 mptsas_hba_setup(mptsas_t *mpt)
2048 {
2049 scsi_hba_tran_t *hba_tran;
2050 int tran_flags;
2051
2052 /* Allocate a transport structure */
2053 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2054 SCSI_HBA_CANSLEEP);
2055 ASSERT(mpt->m_tran != NULL);
2056
2057 hba_tran->tran_hba_private = mpt;
2058 hba_tran->tran_tgt_private = NULL;
2059
2060 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2061 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
15427 *status = LE_32(rep.SlotStatus);
15428 }
15429
15430 return (0);
15431 }
15432
15433 int
15434 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15435 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15436 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
15437 {
15438 ddi_dma_cookie_t new_cookie;
15439 size_t alloc_len;
15440 uint_t ncookie;
15441
15442 if (cookiep == NULL)
15443 cookiep = &new_cookie;
15444
15445 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15446 NULL, dma_hdp) != DDI_SUCCESS) {
15447 dma_hdp = NULL;
15448 return (FALSE);
15449 }
15450
15451 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15452 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15453 acc_hdp) != DDI_SUCCESS) {
15454 ddi_dma_free_handle(dma_hdp);
15455 dma_hdp = NULL;
15456 return (FALSE);
15457 }
15458
15459 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15460 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15461 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15462 (void) ddi_dma_mem_free(acc_hdp);
15463 ddi_dma_free_handle(dma_hdp);
15464 dma_hdp = NULL;
15465 return (FALSE);
15466 }
15467
15468 return (TRUE);
15469 }
15470
15471 void
15472 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15473 {
15474 if (*dma_hdp == NULL)
15475 return;
15476
15477 (void) ddi_dma_unbind_handle(*dma_hdp);
15478 (void) ddi_dma_mem_free(acc_hdp);
15479 ddi_dma_free_handle(dma_hdp);
15480 dma_hdp = NULL;
15481 }
|
2004 m->m_next = mpt->m_next;
2005 break;
2006 }
2007 }
2008 if (m == NULL) {
2009 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2010 }
2011 }
2012
2013 if (mptsas_tail == mpt) {
2014 mptsas_tail = m;
2015 }
2016 rw_exit(&mptsas_global_rwlock);
2017 }
2018
2019 static int
2020 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2021 {
2022 ddi_dma_attr_t task_dma_attrs;
2023
2024 mpt->m_hshk_dma_size = 0;
2025 task_dma_attrs = mpt->m_msg_dma_attr;
2026 task_dma_attrs.dma_attr_sgllen = 1;
2027 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2028
2029 /* allocate Task Management ddi_dma resources */
2030 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2031 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2032 alloc_size, NULL) == FALSE) {
2033 return (DDI_FAILURE);
2034 }
2035 mpt->m_hshk_dma_size = alloc_size;
2036
2037 return (DDI_SUCCESS);
2038 }
2039
2040 static void
2041 mptsas_free_handshake_msg(mptsas_t *mpt)
2042 {
2043 if (mpt->m_hshk_dma_size == 0)
2044 return;
2045 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2046 mpt->m_hshk_dma_size = 0;
2047 }
2048
2049 static int
2050 mptsas_hba_setup(mptsas_t *mpt)
2051 {
2052 scsi_hba_tran_t *hba_tran;
2053 int tran_flags;
2054
2055 /* Allocate a transport structure */
2056 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2057 SCSI_HBA_CANSLEEP);
2058 ASSERT(mpt->m_tran != NULL);
2059
2060 hba_tran->tran_hba_private = mpt;
2061 hba_tran->tran_tgt_private = NULL;
2062
2063 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2064 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
15430 *status = LE_32(rep.SlotStatus);
15431 }
15432
15433 return (0);
15434 }
15435
15436 int
15437 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15438 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15439 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
15440 {
15441 ddi_dma_cookie_t new_cookie;
15442 size_t alloc_len;
15443 uint_t ncookie;
15444
15445 if (cookiep == NULL)
15446 cookiep = &new_cookie;
15447
15448 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15449 NULL, dma_hdp) != DDI_SUCCESS) {
15450 return (FALSE);
15451 }
15452
15453 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15454 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15455 acc_hdp) != DDI_SUCCESS) {
15456 ddi_dma_free_handle(dma_hdp);
15457 return (FALSE);
15458 }
15459
15460 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15461 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15462 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15463 (void) ddi_dma_mem_free(acc_hdp);
15464 ddi_dma_free_handle(dma_hdp);
15465 return (FALSE);
15466 }
15467
15468 return (TRUE);
15469 }
15470
15471 void
15472 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15473 {
15474 if (*dma_hdp == NULL)
15475 return;
15476
15477 (void) ddi_dma_unbind_handle(*dma_hdp);
15478 (void) ddi_dma_mem_free(acc_hdp);
15479 ddi_dma_free_handle(dma_hdp);
15480 }
|