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13275 bhyve needs richer INIT/SIPI support
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>
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--- old/usr/src/uts/i86pc/sys/vmm_dev.h
+++ new/usr/src/uts/i86pc/sys/vmm_dev.h
1 1 /*-
2 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 3 *
4 4 * Copyright (c) 2011 NetApp, Inc.
5 5 * All rights reserved.
6 6 *
7 7 * Redistribution and use in source and binary forms, with or without
8 8 * modification, are permitted provided that the following conditions
9 9 * are met:
10 10 * 1. Redistributions of source code must retain the above copyright
11 11 * notice, this list of conditions and the following disclaimer.
12 12 * 2. Redistributions in binary form must reproduce the above copyright
13 13 * notice, this list of conditions and the following disclaimer in the
14 14 * documentation and/or other materials provided with the distribution.
15 15 *
16 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 26 * SUCH DAMAGE.
27 27 *
28 28 * $FreeBSD$
29 29 */
30 30 /*
31 31 * This file and its contents are supplied under the terms of the
32 32 * Common Development and Distribution License ("CDDL"), version 1.0.
33 33 * You may only use this file in accordance with the terms of version
34 34 * 1.0 of the CDDL.
35 35 *
36 36 * A full copy of the text of the CDDL should have accompanied this
37 37 * source. A copy of the CDDL is also available via the Internet at
38 38 * http://www.illumos.org/license/CDDL.
39 39 *
40 40 * Copyright 2015 Pluribus Networks Inc.
41 41 * Copyright 2019 Joyent, Inc.
42 42 */
43 43
44 44 #ifndef _VMM_DEV_H_
45 45 #define _VMM_DEV_H_
46 46
47 47 #include <machine/vmm.h>
48 48
49 49 struct vm_memmap {
50 50 vm_paddr_t gpa;
51 51 int segid; /* memory segment */
52 52 vm_ooffset_t segoff; /* offset into memory segment */
53 53 size_t len; /* mmap length */
54 54 int prot; /* RWX */
55 55 int flags;
56 56 };
57 57 #define VM_MEMMAP_F_WIRED 0x01
58 58 #define VM_MEMMAP_F_IOMMU 0x02
59 59
60 60 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
61 61 struct vm_memseg {
62 62 int segid;
63 63 size_t len;
64 64 char name[SPECNAMELEN + 1];
65 65 };
66 66
67 67 struct vm_register {
68 68 int cpuid;
69 69 int regnum; /* enum vm_reg_name */
70 70 uint64_t regval;
71 71 };
72 72
73 73 struct vm_seg_desc { /* data or code segment */
74 74 int cpuid;
75 75 int regnum; /* enum vm_reg_name */
76 76 struct seg_desc desc;
77 77 };
78 78
79 79 struct vm_register_set {
80 80 int cpuid;
81 81 unsigned int count;
82 82 const int *regnums; /* enum vm_reg_name */
83 83 uint64_t *regvals;
84 84 };
85 85
86 86 struct vm_exception {
87 87 int cpuid;
88 88 int vector;
89 89 uint32_t error_code;
90 90 int error_code_valid;
91 91 int restart_instruction;
92 92 };
93 93
94 94 struct vm_lapic_msi {
95 95 uint64_t msg;
96 96 uint64_t addr;
97 97 };
98 98
99 99 struct vm_lapic_irq {
100 100 int cpuid;
101 101 int vector;
102 102 };
103 103
104 104 struct vm_ioapic_irq {
105 105 int irq;
106 106 };
107 107
108 108 struct vm_isa_irq {
109 109 int atpic_irq;
110 110 int ioapic_irq;
111 111 };
112 112
113 113 struct vm_isa_irq_trigger {
114 114 int atpic_irq;
115 115 enum vm_intr_trigger trigger;
116 116 };
117 117
118 118 struct vm_capability {
119 119 int cpuid;
120 120 enum vm_cap_type captype;
121 121 int capval;
122 122 int allcpus;
123 123 };
124 124
125 125 struct vm_pptdev {
126 126 int pptfd;
127 127 };
128 128
129 129 struct vm_pptdev_mmio {
130 130 int pptfd;
131 131 vm_paddr_t gpa;
132 132 vm_paddr_t hpa;
133 133 size_t len;
134 134 };
135 135
136 136 struct vm_pptdev_msi {
137 137 int vcpu;
138 138 int pptfd;
139 139 int numvec; /* 0 means disabled */
140 140 uint64_t msg;
141 141 uint64_t addr;
142 142 };
143 143
144 144 struct vm_pptdev_msix {
145 145 int vcpu;
146 146 int pptfd;
147 147 int idx;
148 148 uint64_t msg;
149 149 uint32_t vector_control;
150 150 uint64_t addr;
151 151 };
152 152
153 153 struct vm_pptdev_limits {
154 154 int pptfd;
155 155 int msi_limit;
156 156 int msix_limit;
157 157 };
158 158
159 159 struct vm_nmi {
160 160 int cpuid;
161 161 };
162 162
163 163 #ifdef __FreeBSD__
164 164 #define MAX_VM_STATS 64
165 165 #else
166 166 #define MAX_VM_STATS (64 + VM_MAXCPU)
167 167 #endif
168 168
169 169 struct vm_stats {
170 170 int cpuid; /* in */
171 171 int num_entries; /* out */
172 172 struct timeval tv;
173 173 uint64_t statbuf[MAX_VM_STATS];
174 174 };
175 175
176 176 struct vm_stat_desc {
177 177 int index; /* in */
178 178 char desc[128]; /* out */
179 179 };
180 180
181 181 struct vm_x2apic {
182 182 int cpuid;
183 183 enum x2apic_state state;
184 184 };
185 185
186 186 struct vm_gpa_pte {
187 187 uint64_t gpa; /* in */
188 188 uint64_t pte[4]; /* out */
189 189 int ptenum;
190 190 };
191 191
192 192 struct vm_hpet_cap {
193 193 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
194 194 };
195 195
196 196 struct vm_suspend {
197 197 enum vm_suspend_how how;
198 198 };
199 199
200 200 struct vm_gla2gpa {
201 201 int vcpuid; /* inputs */
202 202 int prot; /* PROT_READ or PROT_WRITE */
203 203 uint64_t gla;
204 204 struct vm_guest_paging paging;
205 205 int fault; /* outputs */
206 206 uint64_t gpa;
207 207 };
208 208
209 209 struct vm_activate_cpu {
210 210 int vcpuid;
211 211 };
212 212
213 213 struct vm_cpuset {
214 214 int which;
215 215 int cpusetsize;
216 216 #ifndef _KERNEL
217 217 cpuset_t *cpus;
218 218 #else
219 219 void *cpus;
220 220 #endif
221 221 };
222 222 #define VM_ACTIVE_CPUS 0
223 223 #define VM_SUSPENDED_CPUS 1
224 224 #define VM_DEBUG_CPUS 2
225 225
226 226 struct vm_intinfo {
227 227 int vcpuid;
228 228 uint64_t info1;
229 229 uint64_t info2;
230 230 };
231 231
232 232 struct vm_rtc_time {
233 233 time_t secs;
234 234 };
235 235
236 236 struct vm_rtc_data {
237 237 int offset;
238 238 uint8_t value;
239 239 };
240 240
241 241 struct vm_devmem_offset {
242 242 int segid;
243 243 off_t offset;
244 244 };
245 245
246 246 struct vm_cpu_topology {
247 247 uint16_t sockets;
248 248 uint16_t cores;
249 249 uint16_t threads;
250 250 uint16_t maxcpus;
251 251 };
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252 252
253 253 struct vm_readwrite_kernemu_device {
254 254 int vcpuid;
255 255 unsigned access_width : 3;
256 256 unsigned _unused : 29;
257 257 uint64_t gpa;
258 258 uint64_t value;
259 259 };
260 260 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
261 261
262 +enum vcpu_reset_kind {
263 + VRK_RESET = 0,
264 + /*
265 + * The reset performed by an INIT IPI clears much of the CPU state, but
266 + * some portions are left untouched, unlike VRK_RESET, which represents
267 + * a "full" reset as if the system was freshly powered on.
268 + */
269 + VRK_INIT = 1,
270 +};
271 +
272 +struct vm_vcpu_reset {
273 + int vcpuid;
274 + uint32_t kind; /* contains: enum vcpu_reset_kind */
275 +};
276 +
277 +struct vm_run_state {
278 + int vcpuid;
279 + uint32_t state; /* of enum cpu_init_status type */
280 + uint8_t sipi_vector; /* vector of SIPI, if any */
281 + uint8_t _pad[3];
282 +};
283 +
262 284 #define VMMCTL_IOC_BASE (('V' << 16) | ('M' << 8))
263 285 #define VMM_IOC_BASE (('v' << 16) | ('m' << 8))
264 286 #define VMM_LOCK_IOC_BASE (('v' << 16) | ('l' << 8))
265 287 #define VMM_CPU_IOC_BASE (('v' << 16) | ('p' << 8))
266 288
267 289 /* Operations performed on the vmmctl device */
268 290 #define VMM_CREATE_VM (VMMCTL_IOC_BASE | 0x01)
269 291 #define VMM_DESTROY_VM (VMMCTL_IOC_BASE | 0x02)
270 292 #define VMM_VM_SUPPORTED (VMMCTL_IOC_BASE | 0x03)
271 293
272 294 /* Operations performed in the context of a given vCPU */
273 295 #define VM_RUN (VMM_CPU_IOC_BASE | 0x01)
274 296 #define VM_SET_REGISTER (VMM_CPU_IOC_BASE | 0x02)
275 297 #define VM_GET_REGISTER (VMM_CPU_IOC_BASE | 0x03)
276 298 #define VM_SET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x04)
277 299 #define VM_GET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x05)
278 300 #define VM_SET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x06)
279 301 #define VM_GET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x07)
280 302 #define VM_INJECT_EXCEPTION (VMM_CPU_IOC_BASE | 0x08)
281 303 #define VM_SET_CAPABILITY (VMM_CPU_IOC_BASE | 0x09)
282 304 #define VM_GET_CAPABILITY (VMM_CPU_IOC_BASE | 0x0a)
283 305 #define VM_PPTDEV_MSI (VMM_CPU_IOC_BASE | 0x0b)
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284 306 #define VM_PPTDEV_MSIX (VMM_CPU_IOC_BASE | 0x0c)
285 307 #define VM_SET_X2APIC_STATE (VMM_CPU_IOC_BASE | 0x0d)
286 308 #define VM_GLA2GPA (VMM_CPU_IOC_BASE | 0x0e)
287 309 #define VM_GLA2GPA_NOFAULT (VMM_CPU_IOC_BASE | 0x0f)
288 310 #define VM_ACTIVATE_CPU (VMM_CPU_IOC_BASE | 0x10)
289 311 #define VM_SET_INTINFO (VMM_CPU_IOC_BASE | 0x11)
290 312 #define VM_GET_INTINFO (VMM_CPU_IOC_BASE | 0x12)
291 313 #define VM_RESTART_INSTRUCTION (VMM_CPU_IOC_BASE | 0x13)
292 314 #define VM_SET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x14)
293 315 #define VM_GET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x15)
316 +#define VM_RESET_CPU (VMM_CPU_IOC_BASE | 0x16)
317 +#define VM_GET_RUN_STATE (VMM_CPU_IOC_BASE | 0x17)
318 +#define VM_SET_RUN_STATE (VMM_CPU_IOC_BASE | 0x18)
294 319
295 320 /* Operations requiring write-locking the VM */
296 321 #define VM_REINIT (VMM_LOCK_IOC_BASE | 0x01)
297 322 #define VM_BIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x02)
298 323 #define VM_UNBIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x03)
299 324 #define VM_MAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x04)
300 325 #define VM_ALLOC_MEMSEG (VMM_LOCK_IOC_BASE | 0x05)
301 326 #define VM_MMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x06)
302 327 #define VM_PMTMR_LOCATE (VMM_LOCK_IOC_BASE | 0x07)
303 328
304 329 #define VM_WRLOCK_CYCLE (VMM_LOCK_IOC_BASE | 0xff)
305 330
306 331 /* All other ioctls */
307 332 #define VM_GET_GPA_PMAP (VMM_IOC_BASE | 0x01)
308 333 #define VM_GET_MEMSEG (VMM_IOC_BASE | 0x02)
309 334 #define VM_MMAP_GETNEXT (VMM_IOC_BASE | 0x03)
310 335
311 336 #define VM_LAPIC_IRQ (VMM_IOC_BASE | 0x04)
312 337 #define VM_LAPIC_LOCAL_IRQ (VMM_IOC_BASE | 0x05)
313 338 #define VM_LAPIC_MSI (VMM_IOC_BASE | 0x06)
314 339
315 340 #define VM_IOAPIC_ASSERT_IRQ (VMM_IOC_BASE | 0x07)
316 341 #define VM_IOAPIC_DEASSERT_IRQ (VMM_IOC_BASE | 0x08)
317 342 #define VM_IOAPIC_PULSE_IRQ (VMM_IOC_BASE | 0x09)
318 343
319 344 #define VM_ISA_ASSERT_IRQ (VMM_IOC_BASE | 0x0a)
320 345 #define VM_ISA_DEASSERT_IRQ (VMM_IOC_BASE | 0x0b)
321 346 #define VM_ISA_PULSE_IRQ (VMM_IOC_BASE | 0x0c)
322 347 #define VM_ISA_SET_IRQ_TRIGGER (VMM_IOC_BASE | 0x0d)
323 348
324 349 #define VM_RTC_WRITE (VMM_IOC_BASE | 0x0e)
325 350 #define VM_RTC_READ (VMM_IOC_BASE | 0x0f)
326 351 #define VM_RTC_SETTIME (VMM_IOC_BASE | 0x10)
327 352 #define VM_RTC_GETTIME (VMM_IOC_BASE | 0x11)
328 353
329 354 #define VM_SUSPEND (VMM_IOC_BASE | 0x12)
330 355
331 356 #define VM_IOAPIC_PINCOUNT (VMM_IOC_BASE | 0x13)
332 357 #define VM_GET_PPTDEV_LIMITS (VMM_IOC_BASE | 0x14)
333 358 #define VM_GET_HPET_CAPABILITIES (VMM_IOC_BASE | 0x15)
334 359
335 360 #define VM_STATS_IOC (VMM_IOC_BASE | 0x16)
336 361 #define VM_STAT_DESC (VMM_IOC_BASE | 0x17)
337 362
338 363 #define VM_INJECT_NMI (VMM_IOC_BASE | 0x18)
339 364 #define VM_GET_X2APIC_STATE (VMM_IOC_BASE | 0x19)
340 365 #define VM_SET_TOPOLOGY (VMM_IOC_BASE | 0x1a)
341 366 #define VM_GET_TOPOLOGY (VMM_IOC_BASE | 0x1b)
342 367 #define VM_GET_CPUS (VMM_IOC_BASE | 0x1c)
343 368 #define VM_SUSPEND_CPU (VMM_IOC_BASE | 0x1d)
344 369 #define VM_RESUME_CPU (VMM_IOC_BASE | 0x1e)
345 370
346 371
347 372 #define VM_DEVMEM_GETOFFSET (VMM_IOC_BASE | 0xff)
348 373
349 374 #define VMM_CTL_DEV "/dev/vmmctl"
350 375
351 376 #endif
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