242 int segid;
243 off_t offset;
244 };
245
246 struct vm_cpu_topology {
247 uint16_t sockets;
248 uint16_t cores;
249 uint16_t threads;
250 uint16_t maxcpus;
251 };
252
253 struct vm_readwrite_kernemu_device {
254 int vcpuid;
255 unsigned access_width : 3;
256 unsigned _unused : 29;
257 uint64_t gpa;
258 uint64_t value;
259 };
260 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
261
262 #define VMMCTL_IOC_BASE (('V' << 16) | ('M' << 8))
263 #define VMM_IOC_BASE (('v' << 16) | ('m' << 8))
264 #define VMM_LOCK_IOC_BASE (('v' << 16) | ('l' << 8))
265 #define VMM_CPU_IOC_BASE (('v' << 16) | ('p' << 8))
266
267 /* Operations performed on the vmmctl device */
268 #define VMM_CREATE_VM (VMMCTL_IOC_BASE | 0x01)
269 #define VMM_DESTROY_VM (VMMCTL_IOC_BASE | 0x02)
270 #define VMM_VM_SUPPORTED (VMMCTL_IOC_BASE | 0x03)
271
272 /* Operations performed in the context of a given vCPU */
273 #define VM_RUN (VMM_CPU_IOC_BASE | 0x01)
274 #define VM_SET_REGISTER (VMM_CPU_IOC_BASE | 0x02)
275 #define VM_GET_REGISTER (VMM_CPU_IOC_BASE | 0x03)
276 #define VM_SET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x04)
277 #define VM_GET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x05)
278 #define VM_SET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x06)
279 #define VM_GET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x07)
280 #define VM_INJECT_EXCEPTION (VMM_CPU_IOC_BASE | 0x08)
281 #define VM_SET_CAPABILITY (VMM_CPU_IOC_BASE | 0x09)
282 #define VM_GET_CAPABILITY (VMM_CPU_IOC_BASE | 0x0a)
283 #define VM_PPTDEV_MSI (VMM_CPU_IOC_BASE | 0x0b)
284 #define VM_PPTDEV_MSIX (VMM_CPU_IOC_BASE | 0x0c)
285 #define VM_SET_X2APIC_STATE (VMM_CPU_IOC_BASE | 0x0d)
286 #define VM_GLA2GPA (VMM_CPU_IOC_BASE | 0x0e)
287 #define VM_GLA2GPA_NOFAULT (VMM_CPU_IOC_BASE | 0x0f)
288 #define VM_ACTIVATE_CPU (VMM_CPU_IOC_BASE | 0x10)
289 #define VM_SET_INTINFO (VMM_CPU_IOC_BASE | 0x11)
290 #define VM_GET_INTINFO (VMM_CPU_IOC_BASE | 0x12)
291 #define VM_RESTART_INSTRUCTION (VMM_CPU_IOC_BASE | 0x13)
292 #define VM_SET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x14)
293 #define VM_GET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x15)
294
295 /* Operations requiring write-locking the VM */
296 #define VM_REINIT (VMM_LOCK_IOC_BASE | 0x01)
297 #define VM_BIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x02)
298 #define VM_UNBIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x03)
299 #define VM_MAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x04)
300 #define VM_ALLOC_MEMSEG (VMM_LOCK_IOC_BASE | 0x05)
301 #define VM_MMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x06)
302 #define VM_PMTMR_LOCATE (VMM_LOCK_IOC_BASE | 0x07)
303
304 #define VM_WRLOCK_CYCLE (VMM_LOCK_IOC_BASE | 0xff)
305
306 /* All other ioctls */
307 #define VM_GET_GPA_PMAP (VMM_IOC_BASE | 0x01)
308 #define VM_GET_MEMSEG (VMM_IOC_BASE | 0x02)
309 #define VM_MMAP_GETNEXT (VMM_IOC_BASE | 0x03)
310
311 #define VM_LAPIC_IRQ (VMM_IOC_BASE | 0x04)
312 #define VM_LAPIC_LOCAL_IRQ (VMM_IOC_BASE | 0x05)
313 #define VM_LAPIC_MSI (VMM_IOC_BASE | 0x06)
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242 int segid;
243 off_t offset;
244 };
245
246 struct vm_cpu_topology {
247 uint16_t sockets;
248 uint16_t cores;
249 uint16_t threads;
250 uint16_t maxcpus;
251 };
252
253 struct vm_readwrite_kernemu_device {
254 int vcpuid;
255 unsigned access_width : 3;
256 unsigned _unused : 29;
257 uint64_t gpa;
258 uint64_t value;
259 };
260 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
261
262 enum vcpu_reset_kind {
263 VRK_RESET = 0,
264 /*
265 * The reset performed by an INIT IPI clears much of the CPU state, but
266 * some portions are left untouched, unlike VRK_RESET, which represents
267 * a "full" reset as if the system was freshly powered on.
268 */
269 VRK_INIT = 1,
270 };
271
272 struct vm_vcpu_reset {
273 int vcpuid;
274 uint32_t kind; /* contains: enum vcpu_reset_kind */
275 };
276
277 struct vm_run_state {
278 int vcpuid;
279 uint32_t state; /* of enum cpu_init_status type */
280 uint8_t sipi_vector; /* vector of SIPI, if any */
281 uint8_t _pad[3];
282 };
283
284 #define VMMCTL_IOC_BASE (('V' << 16) | ('M' << 8))
285 #define VMM_IOC_BASE (('v' << 16) | ('m' << 8))
286 #define VMM_LOCK_IOC_BASE (('v' << 16) | ('l' << 8))
287 #define VMM_CPU_IOC_BASE (('v' << 16) | ('p' << 8))
288
289 /* Operations performed on the vmmctl device */
290 #define VMM_CREATE_VM (VMMCTL_IOC_BASE | 0x01)
291 #define VMM_DESTROY_VM (VMMCTL_IOC_BASE | 0x02)
292 #define VMM_VM_SUPPORTED (VMMCTL_IOC_BASE | 0x03)
293
294 /* Operations performed in the context of a given vCPU */
295 #define VM_RUN (VMM_CPU_IOC_BASE | 0x01)
296 #define VM_SET_REGISTER (VMM_CPU_IOC_BASE | 0x02)
297 #define VM_GET_REGISTER (VMM_CPU_IOC_BASE | 0x03)
298 #define VM_SET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x04)
299 #define VM_GET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x05)
300 #define VM_SET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x06)
301 #define VM_GET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x07)
302 #define VM_INJECT_EXCEPTION (VMM_CPU_IOC_BASE | 0x08)
303 #define VM_SET_CAPABILITY (VMM_CPU_IOC_BASE | 0x09)
304 #define VM_GET_CAPABILITY (VMM_CPU_IOC_BASE | 0x0a)
305 #define VM_PPTDEV_MSI (VMM_CPU_IOC_BASE | 0x0b)
306 #define VM_PPTDEV_MSIX (VMM_CPU_IOC_BASE | 0x0c)
307 #define VM_SET_X2APIC_STATE (VMM_CPU_IOC_BASE | 0x0d)
308 #define VM_GLA2GPA (VMM_CPU_IOC_BASE | 0x0e)
309 #define VM_GLA2GPA_NOFAULT (VMM_CPU_IOC_BASE | 0x0f)
310 #define VM_ACTIVATE_CPU (VMM_CPU_IOC_BASE | 0x10)
311 #define VM_SET_INTINFO (VMM_CPU_IOC_BASE | 0x11)
312 #define VM_GET_INTINFO (VMM_CPU_IOC_BASE | 0x12)
313 #define VM_RESTART_INSTRUCTION (VMM_CPU_IOC_BASE | 0x13)
314 #define VM_SET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x14)
315 #define VM_GET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x15)
316 #define VM_RESET_CPU (VMM_CPU_IOC_BASE | 0x16)
317 #define VM_GET_RUN_STATE (VMM_CPU_IOC_BASE | 0x17)
318 #define VM_SET_RUN_STATE (VMM_CPU_IOC_BASE | 0x18)
319
320 /* Operations requiring write-locking the VM */
321 #define VM_REINIT (VMM_LOCK_IOC_BASE | 0x01)
322 #define VM_BIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x02)
323 #define VM_UNBIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x03)
324 #define VM_MAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x04)
325 #define VM_ALLOC_MEMSEG (VMM_LOCK_IOC_BASE | 0x05)
326 #define VM_MMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x06)
327 #define VM_PMTMR_LOCATE (VMM_LOCK_IOC_BASE | 0x07)
328
329 #define VM_WRLOCK_CYCLE (VMM_LOCK_IOC_BASE | 0xff)
330
331 /* All other ioctls */
332 #define VM_GET_GPA_PMAP (VMM_IOC_BASE | 0x01)
333 #define VM_GET_MEMSEG (VMM_IOC_BASE | 0x02)
334 #define VM_MMAP_GETNEXT (VMM_IOC_BASE | 0x03)
335
336 #define VM_LAPIC_IRQ (VMM_IOC_BASE | 0x04)
337 #define VM_LAPIC_LOCAL_IRQ (VMM_IOC_BASE | 0x05)
338 #define VM_LAPIC_MSI (VMM_IOC_BASE | 0x06)
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