1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30 /*
31 * This file and its contents are supplied under the terms of the
32 * Common Development and Distribution License ("CDDL"), version 1.0.
33 * You may only use this file in accordance with the terms of version
34 * 1.0 of the CDDL.
35 *
36 * A full copy of the text of the CDDL should have accompanied this
37 * source. A copy of the CDDL is also available via the Internet at
38 * http://www.illumos.org/license/CDDL.
39 *
40 * Copyright 2015 Pluribus Networks Inc.
41 * Copyright 2019 Joyent, Inc.
42 */
43
44 #ifndef _VMM_DEV_H_
45 #define _VMM_DEV_H_
46
47 #include <machine/vmm.h>
48
49 struct vm_memmap {
50 vm_paddr_t gpa;
51 int segid; /* memory segment */
52 vm_ooffset_t segoff; /* offset into memory segment */
53 size_t len; /* mmap length */
54 int prot; /* RWX */
55 int flags;
56 };
57 #define VM_MEMMAP_F_WIRED 0x01
58 #define VM_MEMMAP_F_IOMMU 0x02
59
60 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
61 struct vm_memseg {
62 int segid;
63 size_t len;
64 char name[SPECNAMELEN + 1];
65 };
66
67 struct vm_register {
68 int cpuid;
69 int regnum; /* enum vm_reg_name */
70 uint64_t regval;
71 };
72
73 struct vm_seg_desc { /* data or code segment */
74 int cpuid;
75 int regnum; /* enum vm_reg_name */
76 struct seg_desc desc;
77 };
78
79 struct vm_register_set {
80 int cpuid;
81 unsigned int count;
82 const int *regnums; /* enum vm_reg_name */
83 uint64_t *regvals;
84 };
85
86 struct vm_exception {
87 int cpuid;
88 int vector;
89 uint32_t error_code;
90 int error_code_valid;
91 int restart_instruction;
92 };
93
94 struct vm_lapic_msi {
95 uint64_t msg;
96 uint64_t addr;
97 };
98
99 struct vm_lapic_irq {
100 int cpuid;
101 int vector;
102 };
103
104 struct vm_ioapic_irq {
105 int irq;
106 };
107
108 struct vm_isa_irq {
109 int atpic_irq;
110 int ioapic_irq;
111 };
112
113 struct vm_isa_irq_trigger {
114 int atpic_irq;
115 enum vm_intr_trigger trigger;
116 };
117
118 struct vm_capability {
119 int cpuid;
120 enum vm_cap_type captype;
121 int capval;
122 int allcpus;
123 };
124
125 struct vm_pptdev {
126 int pptfd;
127 };
128
129 struct vm_pptdev_mmio {
130 int pptfd;
131 vm_paddr_t gpa;
132 vm_paddr_t hpa;
133 size_t len;
134 };
135
136 struct vm_pptdev_msi {
137 int vcpu;
138 int pptfd;
139 int numvec; /* 0 means disabled */
140 uint64_t msg;
141 uint64_t addr;
142 };
143
144 struct vm_pptdev_msix {
145 int vcpu;
146 int pptfd;
147 int idx;
148 uint64_t msg;
149 uint32_t vector_control;
150 uint64_t addr;
151 };
152
153 struct vm_pptdev_limits {
154 int pptfd;
155 int msi_limit;
156 int msix_limit;
157 };
158
159 struct vm_nmi {
160 int cpuid;
161 };
162
163 #ifdef __FreeBSD__
164 #define MAX_VM_STATS 64
165 #else
166 #define MAX_VM_STATS (64 + VM_MAXCPU)
167 #endif
168
169 struct vm_stats {
170 int cpuid; /* in */
171 int num_entries; /* out */
172 struct timeval tv;
173 uint64_t statbuf[MAX_VM_STATS];
174 };
175
176 struct vm_stat_desc {
177 int index; /* in */
178 char desc[128]; /* out */
179 };
180
181 struct vm_x2apic {
182 int cpuid;
183 enum x2apic_state state;
184 };
185
186 struct vm_gpa_pte {
187 uint64_t gpa; /* in */
188 uint64_t pte[4]; /* out */
189 int ptenum;
190 };
191
192 struct vm_hpet_cap {
193 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
194 };
195
196 struct vm_suspend {
197 enum vm_suspend_how how;
198 };
199
200 struct vm_gla2gpa {
201 int vcpuid; /* inputs */
202 int prot; /* PROT_READ or PROT_WRITE */
203 uint64_t gla;
204 struct vm_guest_paging paging;
205 int fault; /* outputs */
206 uint64_t gpa;
207 };
208
209 struct vm_activate_cpu {
210 int vcpuid;
211 };
212
213 struct vm_cpuset {
214 int which;
215 int cpusetsize;
216 #ifndef _KERNEL
217 cpuset_t *cpus;
218 #else
219 void *cpus;
220 #endif
221 };
222 #define VM_ACTIVE_CPUS 0
223 #define VM_SUSPENDED_CPUS 1
224 #define VM_DEBUG_CPUS 2
225
226 struct vm_intinfo {
227 int vcpuid;
228 uint64_t info1;
229 uint64_t info2;
230 };
231
232 struct vm_rtc_time {
233 time_t secs;
234 };
235
236 struct vm_rtc_data {
237 int offset;
238 uint8_t value;
239 };
240
241 struct vm_devmem_offset {
242 int segid;
243 off_t offset;
244 };
245
246 struct vm_cpu_topology {
247 uint16_t sockets;
248 uint16_t cores;
249 uint16_t threads;
250 uint16_t maxcpus;
251 };
252
253 struct vm_readwrite_kernemu_device {
254 int vcpuid;
255 unsigned access_width : 3;
256 unsigned _unused : 29;
257 uint64_t gpa;
258 uint64_t value;
259 };
260 _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
261
262 #define VMMCTL_IOC_BASE (('V' << 16) | ('M' << 8))
263 #define VMM_IOC_BASE (('v' << 16) | ('m' << 8))
264 #define VMM_LOCK_IOC_BASE (('v' << 16) | ('l' << 8))
265 #define VMM_CPU_IOC_BASE (('v' << 16) | ('p' << 8))
266
267 /* Operations performed on the vmmctl device */
268 #define VMM_CREATE_VM (VMMCTL_IOC_BASE | 0x01)
269 #define VMM_DESTROY_VM (VMMCTL_IOC_BASE | 0x02)
270 #define VMM_VM_SUPPORTED (VMMCTL_IOC_BASE | 0x03)
271
272 /* Operations performed in the context of a given vCPU */
273 #define VM_RUN (VMM_CPU_IOC_BASE | 0x01)
274 #define VM_SET_REGISTER (VMM_CPU_IOC_BASE | 0x02)
275 #define VM_GET_REGISTER (VMM_CPU_IOC_BASE | 0x03)
276 #define VM_SET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x04)
277 #define VM_GET_SEGMENT_DESCRIPTOR (VMM_CPU_IOC_BASE | 0x05)
278 #define VM_SET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x06)
279 #define VM_GET_REGISTER_SET (VMM_CPU_IOC_BASE | 0x07)
280 #define VM_INJECT_EXCEPTION (VMM_CPU_IOC_BASE | 0x08)
281 #define VM_SET_CAPABILITY (VMM_CPU_IOC_BASE | 0x09)
282 #define VM_GET_CAPABILITY (VMM_CPU_IOC_BASE | 0x0a)
283 #define VM_PPTDEV_MSI (VMM_CPU_IOC_BASE | 0x0b)
284 #define VM_PPTDEV_MSIX (VMM_CPU_IOC_BASE | 0x0c)
285 #define VM_SET_X2APIC_STATE (VMM_CPU_IOC_BASE | 0x0d)
286 #define VM_GLA2GPA (VMM_CPU_IOC_BASE | 0x0e)
287 #define VM_GLA2GPA_NOFAULT (VMM_CPU_IOC_BASE | 0x0f)
288 #define VM_ACTIVATE_CPU (VMM_CPU_IOC_BASE | 0x10)
289 #define VM_SET_INTINFO (VMM_CPU_IOC_BASE | 0x11)
290 #define VM_GET_INTINFO (VMM_CPU_IOC_BASE | 0x12)
291 #define VM_RESTART_INSTRUCTION (VMM_CPU_IOC_BASE | 0x13)
292 #define VM_SET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x14)
293 #define VM_GET_KERNEMU_DEV (VMM_CPU_IOC_BASE | 0x15)
294
295 /* Operations requiring write-locking the VM */
296 #define VM_REINIT (VMM_LOCK_IOC_BASE | 0x01)
297 #define VM_BIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x02)
298 #define VM_UNBIND_PPTDEV (VMM_LOCK_IOC_BASE | 0x03)
299 #define VM_MAP_PPTDEV_MMIO (VMM_LOCK_IOC_BASE | 0x04)
300 #define VM_ALLOC_MEMSEG (VMM_LOCK_IOC_BASE | 0x05)
301 #define VM_MMAP_MEMSEG (VMM_LOCK_IOC_BASE | 0x06)
302 #define VM_PMTMR_LOCATE (VMM_LOCK_IOC_BASE | 0x07)
303
304 #define VM_WRLOCK_CYCLE (VMM_LOCK_IOC_BASE | 0xff)
305
306 /* All other ioctls */
307 #define VM_GET_GPA_PMAP (VMM_IOC_BASE | 0x01)
308 #define VM_GET_MEMSEG (VMM_IOC_BASE | 0x02)
309 #define VM_MMAP_GETNEXT (VMM_IOC_BASE | 0x03)
310
311 #define VM_LAPIC_IRQ (VMM_IOC_BASE | 0x04)
312 #define VM_LAPIC_LOCAL_IRQ (VMM_IOC_BASE | 0x05)
313 #define VM_LAPIC_MSI (VMM_IOC_BASE | 0x06)
314
315 #define VM_IOAPIC_ASSERT_IRQ (VMM_IOC_BASE | 0x07)
316 #define VM_IOAPIC_DEASSERT_IRQ (VMM_IOC_BASE | 0x08)
317 #define VM_IOAPIC_PULSE_IRQ (VMM_IOC_BASE | 0x09)
318
319 #define VM_ISA_ASSERT_IRQ (VMM_IOC_BASE | 0x0a)
320 #define VM_ISA_DEASSERT_IRQ (VMM_IOC_BASE | 0x0b)
321 #define VM_ISA_PULSE_IRQ (VMM_IOC_BASE | 0x0c)
322 #define VM_ISA_SET_IRQ_TRIGGER (VMM_IOC_BASE | 0x0d)
323
324 #define VM_RTC_WRITE (VMM_IOC_BASE | 0x0e)
325 #define VM_RTC_READ (VMM_IOC_BASE | 0x0f)
326 #define VM_RTC_SETTIME (VMM_IOC_BASE | 0x10)
327 #define VM_RTC_GETTIME (VMM_IOC_BASE | 0x11)
328
329 #define VM_SUSPEND (VMM_IOC_BASE | 0x12)
330
331 #define VM_IOAPIC_PINCOUNT (VMM_IOC_BASE | 0x13)
332 #define VM_GET_PPTDEV_LIMITS (VMM_IOC_BASE | 0x14)
333 #define VM_GET_HPET_CAPABILITIES (VMM_IOC_BASE | 0x15)
334
335 #define VM_STATS_IOC (VMM_IOC_BASE | 0x16)
336 #define VM_STAT_DESC (VMM_IOC_BASE | 0x17)
337
338 #define VM_INJECT_NMI (VMM_IOC_BASE | 0x18)
339 #define VM_GET_X2APIC_STATE (VMM_IOC_BASE | 0x19)
340 #define VM_SET_TOPOLOGY (VMM_IOC_BASE | 0x1a)
341 #define VM_GET_TOPOLOGY (VMM_IOC_BASE | 0x1b)
342 #define VM_GET_CPUS (VMM_IOC_BASE | 0x1c)
343 #define VM_SUSPEND_CPU (VMM_IOC_BASE | 0x1d)
344 #define VM_RESUME_CPU (VMM_IOC_BASE | 0x1e)
345
346
347 #define VM_DEVMEM_GETOFFSET (VMM_IOC_BASE | 0xff)
348
349 #define VMM_CTL_DEV "/dev/vmmctl"
350
351 #endif