1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
27 */
28
29 /*
30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms of all code within
34 * this file that is exclusively owned by LSI, with or without
35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 * License requirements, the following conditions are met:
37 *
38 * Neither the name of the author nor the names of its contributors may be
39 * used to endorse or promote products derived from this software without
40 * specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 * DAMAGE.
54 */
55
56 /*
57 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface.
58 *
59 */
60
61 #if defined(lint) || defined(DEBUG)
62 #define MPTSAS_DEBUG
63 #endif
64
65 /*
66 * standard header files.
67 */
68 #include <sys/note.h>
69 #include <sys/scsi/scsi.h>
70 #include <sys/pci.h>
71 #include <sys/file.h>
72 #include <sys/policy.h>
73 #include <sys/model.h>
74 #include <sys/sysevent.h>
75 #include <sys/sysevent/eventdefs.h>
76 #include <sys/sysevent/dr.h>
77 #include <sys/sata/sata_defs.h>
78 #include <sys/scsi/generic/sas.h>
79 #include <sys/scsi/impl/scsi_sas.h>
80
81 #pragma pack(1)
82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
90 #pragma pack()
91
92 /*
93 * private header files.
94 *
95 */
96 #include <sys/scsi/impl/scsi_reset_notify.h>
97 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
98 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
99 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
100 #include <sys/raidioctl.h>
101
102 #include <sys/fs/dv_node.h> /* devfs_clean */
103
104 /*
105 * FMA header files
106 */
107 #include <sys/ddifm.h>
108 #include <sys/fm/protocol.h>
109 #include <sys/fm/util.h>
110 #include <sys/fm/io/ddi.h>
111
112 /*
113 * autoconfiguration data and routines.
114 */
115 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
116 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
117 static int mptsas_power(dev_info_t *dip, int component, int level);
118
119 /*
120 * cb_ops function
121 */
122 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
123 cred_t *credp, int *rval);
124 #ifdef __sparc
125 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
126 #else /* __sparc */
127 static int mptsas_quiesce(dev_info_t *devi);
128 #endif /* __sparc */
129
130 /*
131 * Resource initilaization for hardware
132 */
133 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
134 static void mptsas_disable_bus_master(mptsas_t *mpt);
135 static void mptsas_hba_fini(mptsas_t *mpt);
136 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
137 static int mptsas_hba_setup(mptsas_t *mpt);
138 static void mptsas_hba_teardown(mptsas_t *mpt);
139 static int mptsas_config_space_init(mptsas_t *mpt);
140 static void mptsas_config_space_fini(mptsas_t *mpt);
141 static void mptsas_iport_register(mptsas_t *mpt);
142 static int mptsas_smp_setup(mptsas_t *mpt);
143 static void mptsas_smp_teardown(mptsas_t *mpt);
144 static int mptsas_cache_create(mptsas_t *mpt);
145 static void mptsas_cache_destroy(mptsas_t *mpt);
146 static int mptsas_alloc_request_frames(mptsas_t *mpt);
147 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
148 static int mptsas_alloc_free_queue(mptsas_t *mpt);
149 static int mptsas_alloc_post_queue(mptsas_t *mpt);
150 static void mptsas_alloc_reply_args(mptsas_t *mpt);
151 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
152 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
153 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
154
155 /*
156 * SCSA function prototypes
157 */
158 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
159 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
160 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
161 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
162 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
163 int tgtonly);
164 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
165 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
166 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
167 int tgtlen, int flags, int (*callback)(), caddr_t arg);
168 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
169 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
170 struct scsi_pkt *pkt);
171 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
172 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
173 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
174 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
175 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
176 void (*callback)(caddr_t), caddr_t arg);
177 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
178 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
179 static int mptsas_scsi_quiesce(dev_info_t *dip);
180 static int mptsas_scsi_unquiesce(dev_info_t *dip);
181 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
182 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
183
184 /*
185 * SMP functions
186 */
187 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
188
189 /*
190 * internal function prototypes.
191 */
192 static void mptsas_list_add(mptsas_t *mpt);
193 static void mptsas_list_del(mptsas_t *mpt);
194
195 static int mptsas_quiesce_bus(mptsas_t *mpt);
196 static int mptsas_unquiesce_bus(mptsas_t *mpt);
197
198 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
199 static void mptsas_free_handshake_msg(mptsas_t *mpt);
200
201 static void mptsas_ncmds_checkdrain(void *arg);
202
203 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
204 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
205 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
206 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
207
208 static int mptsas_do_detach(dev_info_t *dev);
209 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
210 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
211 struct scsi_pkt *pkt);
212 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
213
214 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
215 static void mptsas_handle_event(void *args);
216 static int mptsas_handle_event_sync(void *args);
217 static void mptsas_handle_dr(void *args);
218 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
219 dev_info_t *pdip);
220
221 static void mptsas_restart_cmd(void *);
222
223 static void mptsas_flush_hba(mptsas_t *mpt);
224 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
225 uint8_t tasktype);
226 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
227 uchar_t reason, uint_t stat);
228
229 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
230 static void mptsas_process_intr(mptsas_t *mpt,
231 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
232 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
233 pMpi2ReplyDescriptorsUnion_t reply_desc);
234 static void mptsas_handle_address_reply(mptsas_t *mpt,
235 pMpi2ReplyDescriptorsUnion_t reply_desc);
236 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
237 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
238 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
239
240 static void mptsas_watch(void *arg);
241 static void mptsas_watchsubr(mptsas_t *mpt);
242 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl);
243
244 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
245 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
246 uint8_t *data, uint32_t request_size, uint32_t reply_size,
247 uint32_t data_size, uint32_t direction, uint8_t *dataout,
248 uint32_t dataout_size, short timeout, int mode);
249 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
250
251 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
252 uint32_t unique_id);
253 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
254 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
255 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
256 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
257 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
258 uint32_t diag_type);
259 static int mptsas_diag_register(mptsas_t *mpt,
260 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
261 static int mptsas_diag_unregister(mptsas_t *mpt,
262 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
263 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
264 uint32_t *return_code);
265 static int mptsas_diag_read_buffer(mptsas_t *mpt,
266 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
267 uint32_t *return_code, int ioctl_mode);
268 static int mptsas_diag_release(mptsas_t *mpt,
269 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
270 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
271 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
272 int ioctl_mode);
273 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
274 int mode);
275
276 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
277 int cmdlen, int tgtlen, int statuslen, int kf);
278 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
279
280 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
281 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
282
283 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
284 int kmflags);
285 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
286
287 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
288 mptsas_cmd_t *cmd);
289 static void mptsas_check_task_mgt(mptsas_t *mpt,
290 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
291 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
292 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
293 int *resid);
294
295 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
296 static void mptsas_free_active_slots(mptsas_t *mpt);
297 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
298
299 static void mptsas_restart_hba(mptsas_t *mpt);
300 static void mptsas_restart_waitq(mptsas_t *mpt);
301
302 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
303 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
304 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
305
306 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
307 static void mptsas_doneq_empty(mptsas_t *mpt);
308 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
309
310 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
311 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
312 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
313 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
314
315
316 static void mptsas_start_watch_reset_delay();
317 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
318 static void mptsas_watch_reset_delay(void *arg);
319 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
320
321 /*
322 * helper functions
323 */
324 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
325
326 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
327 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
328 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
329 int lun);
330 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
331 int lun);
332 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
333 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
334
335 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
336 int *lun);
337 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
338
339 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask,
340 uint8_t phy);
341 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask,
342 uint64_t wwid);
343 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask,
344 uint64_t wwid);
345
346 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
347 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
348
349 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
350 uint16_t *handle, mptsas_target_t **pptgt);
351 static void mptsas_update_phymask(mptsas_t *mpt);
352
353 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
354 uint32_t *status, uint8_t cmd);
355 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
356 mptsas_phymask_t *phymask);
357 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
358 mptsas_phymask_t phymask);
359 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
360
361
362 /*
363 * Enumeration / DR functions
364 */
365 static void mptsas_config_all(dev_info_t *pdip);
366 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
367 dev_info_t **lundip);
368 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
369 dev_info_t **lundip);
370
371 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
372 static int mptsas_offline_target(dev_info_t *pdip, char *name);
373
374 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
375 dev_info_t **dip);
376
377 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
378 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
379 dev_info_t **dip, mptsas_target_t *ptgt);
380
381 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
382 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
383
384 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
385 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
386 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
387 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
388 int lun);
389
390 static void mptsas_offline_missed_luns(dev_info_t *pdip,
391 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
392 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
393 mdi_pathinfo_t *rpip, uint_t flags);
394
395 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
396 dev_info_t **smp_dip);
397 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
398 uint_t flags);
399
400 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
401 int mode, int *rval);
402 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
403 int mode, int *rval);
404 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
405 int mode, int *rval);
406 static void mptsas_record_event(void *args);
407 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
408 int mode);
409
410 static void mptsas_hash_init(mptsas_hash_table_t *hashtab);
411 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen);
412 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data);
413 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
414 mptsas_phymask_t key2);
415 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
416 mptsas_phymask_t key2);
417 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos);
418
419 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t,
420 uint32_t, mptsas_phymask_t, uint8_t);
421 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab,
422 mptsas_smp_t *data);
423 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
424 mptsas_phymask_t phymask);
425 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t);
426 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t);
427 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
428 dev_info_t **smp_dip);
429
430 /*
431 * Power management functions
432 */
433 static int mptsas_get_pci_cap(mptsas_t *mpt);
434 static int mptsas_init_pm(mptsas_t *mpt);
435
436 /*
437 * MPT MSI tunable:
438 *
439 * By default MSI is enabled on all supported platforms.
440 */
441 boolean_t mptsas_enable_msi = B_TRUE;
442 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
443
444 static int mptsas_register_intrs(mptsas_t *);
445 static void mptsas_unregister_intrs(mptsas_t *);
446 static int mptsas_add_intrs(mptsas_t *, int);
447 static void mptsas_rem_intrs(mptsas_t *);
448
449 /*
450 * FMA Prototypes
451 */
452 static void mptsas_fm_init(mptsas_t *mpt);
453 static void mptsas_fm_fini(mptsas_t *mpt);
454 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
455
456 extern pri_t minclsyspri, maxclsyspri;
457
458 /*
459 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
460 * under this device that the paths to a physical device are created when
461 * MPxIO is used.
462 */
463 extern dev_info_t *scsi_vhci_dip;
464
465 /*
466 * Tunable timeout value for Inquiry VPD page 0x83
467 * By default the value is 30 seconds.
468 */
469 int mptsas_inq83_retry_timeout = 30;
470
471 /*
472 * This is used to allocate memory for message frame storage, not for
473 * data I/O DMA. All message frames must be stored in the first 4G of
474 * physical memory.
475 */
476 ddi_dma_attr_t mptsas_dma_attrs = {
477 DMA_ATTR_V0, /* attribute layout version */
478 0x0ull, /* address low - should be 0 (longlong) */
479 0xffffffffull, /* address high - 32-bit max range */
480 0x00ffffffull, /* count max - max DMA object size */
481 4, /* allocation alignment requirements */
482 0x78, /* burstsizes - binary encoded values */
483 1, /* minxfer - gran. of DMA engine */
484 0x00ffffffull, /* maxxfer - gran. of DMA engine */
485 0xffffffffull, /* max segment size (DMA boundary) */
486 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
487 512, /* granularity - device transfer size */
488 0 /* flags, set to 0 */
489 };
490
491 /*
492 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
493 * physical addresses are supported.)
494 */
495 ddi_dma_attr_t mptsas_dma_attrs64 = {
496 DMA_ATTR_V0, /* attribute layout version */
497 0x0ull, /* address low - should be 0 (longlong) */
498 0xffffffffffffffffull, /* address high - 64-bit max */
499 0x00ffffffull, /* count max - max DMA object size */
500 4, /* allocation alignment requirements */
501 0x78, /* burstsizes - binary encoded values */
502 1, /* minxfer - gran. of DMA engine */
503 0x00ffffffull, /* maxxfer - gran. of DMA engine */
504 0xffffffffull, /* max segment size (DMA boundary) */
505 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
506 512, /* granularity - device transfer size */
507 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */
508 };
509
510 ddi_device_acc_attr_t mptsas_dev_attr = {
511 DDI_DEVICE_ATTR_V1,
512 DDI_STRUCTURE_LE_ACC,
513 DDI_STRICTORDER_ACC,
514 DDI_DEFAULT_ACC
515 };
516
517 static struct cb_ops mptsas_cb_ops = {
518 scsi_hba_open, /* open */
519 scsi_hba_close, /* close */
520 nodev, /* strategy */
521 nodev, /* print */
522 nodev, /* dump */
523 nodev, /* read */
524 nodev, /* write */
525 mptsas_ioctl, /* ioctl */
526 nodev, /* devmap */
527 nodev, /* mmap */
528 nodev, /* segmap */
529 nochpoll, /* chpoll */
530 ddi_prop_op, /* cb_prop_op */
531 NULL, /* streamtab */
532 D_MP, /* cb_flag */
533 CB_REV, /* rev */
534 nodev, /* aread */
535 nodev /* awrite */
536 };
537
538 static struct dev_ops mptsas_ops = {
539 DEVO_REV, /* devo_rev, */
540 0, /* refcnt */
541 ddi_no_info, /* info */
542 nulldev, /* identify */
543 nulldev, /* probe */
544 mptsas_attach, /* attach */
545 mptsas_detach, /* detach */
546 #ifdef __sparc
547 mptsas_reset,
548 #else
549 nodev, /* reset */
550 #endif /* __sparc */
551 &mptsas_cb_ops, /* driver operations */
552 NULL, /* bus operations */
553 mptsas_power, /* power management */
554 #ifdef __sparc
555 ddi_quiesce_not_needed
556 #else
557 mptsas_quiesce /* quiesce */
558 #endif /* __sparc */
559 };
560
561
562 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
563
564 static struct modldrv modldrv = {
565 &mod_driverops, /* Type of module. This one is a driver */
566 MPTSAS_MOD_STRING, /* Name of the module. */
567 &mptsas_ops, /* driver ops */
568 };
569
570 static struct modlinkage modlinkage = {
571 MODREV_1, &modldrv, NULL
572 };
573 #define TARGET_PROP "target"
574 #define LUN_PROP "lun"
575 #define LUN64_PROP "lun64"
576 #define SAS_PROP "sas-mpt"
577 #define MDI_GUID "wwn"
578 #define NDI_GUID "guid"
579 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
580
581 /*
582 * Local static data
583 */
584 #if defined(MPTSAS_DEBUG)
585 uint32_t mptsas_debug_flags = 0;
586 #endif /* defined(MPTSAS_DEBUG) */
587 uint32_t mptsas_debug_resets = 0;
588
589 static kmutex_t mptsas_global_mutex;
590 static void *mptsas_state; /* soft state ptr */
591 static krwlock_t mptsas_global_rwlock;
592
593 static kmutex_t mptsas_log_mutex;
594 static char mptsas_log_buf[256];
595 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
596
597 static mptsas_t *mptsas_head, *mptsas_tail;
598 static clock_t mptsas_scsi_watchdog_tick;
599 static clock_t mptsas_tick;
600 static timeout_id_t mptsas_reset_watch;
601 static timeout_id_t mptsas_timeout_id;
602 static int mptsas_timeouts_enabled = 0;
603 /*
604 * warlock directives
605 */
606 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
607 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
608 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
609 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
610 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
611 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
612
613 /*
614 * SM - HBA statics
615 */
616 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
617
618 #ifdef MPTSAS_DEBUG
619 void debug_enter(char *);
620 #endif
621
622 /*
623 * Notes:
624 * - scsi_hba_init(9F) initializes SCSI HBA modules
625 * - must call scsi_hba_fini(9F) if modload() fails
626 */
627 int
628 _init(void)
629 {
630 int status;
631 /* CONSTCOND */
632 ASSERT(NO_COMPETING_THREADS);
633
634 NDBG0(("_init"));
635
636 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
637 MPTSAS_INITIAL_SOFT_SPACE);
638 if (status != 0) {
639 return (status);
640 }
641
642 if ((status = scsi_hba_init(&modlinkage)) != 0) {
643 ddi_soft_state_fini(&mptsas_state);
644 return (status);
645 }
646
647 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
648 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
649 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
650
651 if ((status = mod_install(&modlinkage)) != 0) {
652 mutex_destroy(&mptsas_log_mutex);
653 rw_destroy(&mptsas_global_rwlock);
654 mutex_destroy(&mptsas_global_mutex);
655 ddi_soft_state_fini(&mptsas_state);
656 scsi_hba_fini(&modlinkage);
657 }
658
659 return (status);
660 }
661
662 /*
663 * Notes:
664 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
665 */
666 int
667 _fini(void)
668 {
669 int status;
670 /* CONSTCOND */
671 ASSERT(NO_COMPETING_THREADS);
672
673 NDBG0(("_fini"));
674
675 if ((status = mod_remove(&modlinkage)) == 0) {
676 ddi_soft_state_fini(&mptsas_state);
677 scsi_hba_fini(&modlinkage);
678 mutex_destroy(&mptsas_global_mutex);
679 rw_destroy(&mptsas_global_rwlock);
680 mutex_destroy(&mptsas_log_mutex);
681 }
682 return (status);
683 }
684
685 /*
686 * The loadable-module _info(9E) entry point
687 */
688 int
689 _info(struct modinfo *modinfop)
690 {
691 /* CONSTCOND */
692 ASSERT(NO_COMPETING_THREADS);
693 NDBG0(("mptsas _info"));
694
695 return (mod_info(&modlinkage, modinfop));
696 }
697
698
699 static int
700 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
701 {
702 dev_info_t *pdip;
703 mptsas_t *mpt;
704 scsi_hba_tran_t *hba_tran;
705 char *iport = NULL;
706 char phymask[MPTSAS_MAX_PHYS];
707 mptsas_phymask_t phy_mask = 0;
708 int dynamic_port = 0;
709 uint32_t page_address;
710 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
711 int rval = DDI_FAILURE;
712 int i = 0;
713 uint8_t numphys = 0;
714 uint8_t phy_id;
715 uint8_t phy_port = 0;
716 uint16_t attached_devhdl = 0;
717 uint32_t dev_info;
718 uint64_t attached_sas_wwn;
719 uint16_t dev_hdl;
720 uint16_t pdev_hdl;
721 uint16_t bay_num, enclosure;
722 char attached_wwnstr[MPTSAS_WWN_STRLEN];
723
724 /* CONSTCOND */
725 ASSERT(NO_COMPETING_THREADS);
726
727 switch (cmd) {
728 case DDI_ATTACH:
729 break;
730
731 case DDI_RESUME:
732 /*
733 * If this a scsi-iport node, nothing to do here.
734 */
735 return (DDI_SUCCESS);
736
737 default:
738 return (DDI_FAILURE);
739 }
740
741 pdip = ddi_get_parent(dip);
742
743 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
744 NULL) {
745 cmn_err(CE_WARN, "Failed attach iport because fail to "
746 "get tran vector for the HBA node");
747 return (DDI_FAILURE);
748 }
749
750 mpt = TRAN2MPT(hba_tran);
751 ASSERT(mpt != NULL);
752 if (mpt == NULL)
753 return (DDI_FAILURE);
754
755 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
756 NULL) {
757 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
758 "get tran vector for the iport node");
759 return (DDI_FAILURE);
760 }
761
762 /*
763 * Overwrite parent's tran_hba_private to iport's tran vector
764 */
765 hba_tran->tran_hba_private = mpt;
766
767 ddi_report_dev(dip);
768
769 /*
770 * Get SAS address for initiator port according dev_handle
771 */
772 iport = ddi_get_name_addr(dip);
773 if (iport && strncmp(iport, "v0", 2) == 0) {
774 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
775 MPTSAS_VIRTUAL_PORT, 1) !=
776 DDI_PROP_SUCCESS) {
777 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
778 MPTSAS_VIRTUAL_PORT);
779 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
780 "prop update failed");
781 return (DDI_FAILURE);
782 }
783 return (DDI_SUCCESS);
784 }
785
786 mutex_enter(&mpt->m_mutex);
787 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
788 bzero(phymask, sizeof (phymask));
789 (void) sprintf(phymask,
790 "%x", mpt->m_phy_info[i].phy_mask);
791 if (strcmp(phymask, iport) == 0) {
792 break;
793 }
794 }
795
796 if (i == MPTSAS_MAX_PHYS) {
797 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
798 "seems not exist", iport);
799 mutex_exit(&mpt->m_mutex);
800 return (DDI_FAILURE);
801 }
802
803 phy_mask = mpt->m_phy_info[i].phy_mask;
804
805 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
806 dynamic_port = 1;
807 else
808 dynamic_port = 0;
809
810 /*
811 * Update PHY info for smhba
812 */
813 if (mptsas_smhba_phy_init(mpt)) {
814 mutex_exit(&mpt->m_mutex);
815 mptsas_log(mpt, CE_WARN, "mptsas phy update "
816 "failed");
817 return (DDI_FAILURE);
818 }
819
820 mutex_exit(&mpt->m_mutex);
821
822 numphys = 0;
823 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
824 if ((phy_mask >> i) & 0x01) {
825 numphys++;
826 }
827 }
828
829 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
830 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
831 mpt->un.m_base_wwid);
832
833 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
834 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
835 DDI_PROP_SUCCESS) {
836 (void) ddi_prop_remove(DDI_DEV_T_NONE,
837 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
838 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
839 "prop update failed");
840 return (DDI_FAILURE);
841 }
842 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
843 MPTSAS_NUM_PHYS, numphys) !=
844 DDI_PROP_SUCCESS) {
845 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
846 return (DDI_FAILURE);
847 }
848
849 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
850 "phymask", phy_mask) !=
851 DDI_PROP_SUCCESS) {
852 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
853 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
854 "prop update failed");
855 return (DDI_FAILURE);
856 }
857
858 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
859 "dynamic-port", dynamic_port) !=
860 DDI_PROP_SUCCESS) {
861 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
862 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
863 "prop update failed");
864 return (DDI_FAILURE);
865 }
866 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
867 MPTSAS_VIRTUAL_PORT, 0) !=
868 DDI_PROP_SUCCESS) {
869 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
870 MPTSAS_VIRTUAL_PORT);
871 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
872 "prop update failed");
873 return (DDI_FAILURE);
874 }
875 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
876 &attached_devhdl);
877
878 mutex_enter(&mpt->m_mutex);
879 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
880 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
881 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
882 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
883 &pdev_hdl, &bay_num, &enclosure);
884 if (rval != DDI_SUCCESS) {
885 mptsas_log(mpt, CE_WARN,
886 "Failed to get device page0 for handle:%d",
887 attached_devhdl);
888 mutex_exit(&mpt->m_mutex);
889 return (DDI_FAILURE);
890 }
891
892 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
893 bzero(phymask, sizeof (phymask));
894 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
895 if (strcmp(phymask, iport) == 0) {
896 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
897 "%x",
898 mpt->m_phy_info[i].phy_mask);
899 }
900 }
901 mutex_exit(&mpt->m_mutex);
902
903 bzero(attached_wwnstr, sizeof (attached_wwnstr));
904 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
905 attached_sas_wwn);
906 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
907 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
908 DDI_PROP_SUCCESS) {
909 (void) ddi_prop_remove(DDI_DEV_T_NONE,
910 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
911 return (DDI_FAILURE);
912 }
913
914 /* Create kstats for each phy on this iport */
915
916 mptsas_create_phy_stats(mpt, iport, dip);
917
918 /*
919 * register sas hba iport with mdi (MPxIO/vhci)
920 */
921 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
922 dip, 0) == MDI_SUCCESS) {
923 mpt->m_mpxio_enable = TRUE;
924 }
925 return (DDI_SUCCESS);
926 }
927
928 /*
929 * Notes:
930 * Set up all device state and allocate data structures,
931 * mutexes, condition variables, etc. for device operation.
932 * Add interrupts needed.
933 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
934 */
935 static int
936 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
937 {
938 mptsas_t *mpt = NULL;
939 int instance, i, j;
940 int doneq_thread_num;
941 char intr_added = 0;
942 char map_setup = 0;
943 char config_setup = 0;
944 char hba_attach_setup = 0;
945 char smp_attach_setup = 0;
946 char mutex_init_done = 0;
947 char event_taskq_create = 0;
948 char dr_taskq_create = 0;
949 char doneq_thread_create = 0;
950 scsi_hba_tran_t *hba_tran;
951 uint_t mem_bar = MEM_SPACE;
952 int rval = DDI_FAILURE;
953
954 /* CONSTCOND */
955 ASSERT(NO_COMPETING_THREADS);
956
957 if (scsi_hba_iport_unit_address(dip)) {
958 return (mptsas_iport_attach(dip, cmd));
959 }
960
961 switch (cmd) {
962 case DDI_ATTACH:
963 break;
964
965 case DDI_RESUME:
966 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
967 return (DDI_FAILURE);
968
969 mpt = TRAN2MPT(hba_tran);
970
971 if (!mpt) {
972 return (DDI_FAILURE);
973 }
974
975 /*
976 * Reset hardware and softc to "no outstanding commands"
977 * Note that a check condition can result on first command
978 * to a target.
979 */
980 mutex_enter(&mpt->m_mutex);
981
982 /*
983 * raise power.
984 */
985 if (mpt->m_options & MPTSAS_OPT_PM) {
986 mutex_exit(&mpt->m_mutex);
987 (void) pm_busy_component(dip, 0);
988 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
989 if (rval == DDI_SUCCESS) {
990 mutex_enter(&mpt->m_mutex);
991 } else {
992 /*
993 * The pm_raise_power() call above failed,
994 * and that can only occur if we were unable
995 * to reset the hardware. This is probably
996 * due to unhealty hardware, and because
997 * important filesystems(such as the root
998 * filesystem) could be on the attached disks,
999 * it would not be a good idea to continue,
1000 * as we won't be entirely certain we are
1001 * writing correct data. So we panic() here
1002 * to not only prevent possible data corruption,
1003 * but to give developers or end users a hope
1004 * of identifying and correcting any problems.
1005 */
1006 fm_panic("mptsas could not reset hardware "
1007 "during resume");
1008 }
1009 }
1010
1011 mpt->m_suspended = 0;
1012
1013 /*
1014 * Reinitialize ioc
1015 */
1016 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1017 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1018 mutex_exit(&mpt->m_mutex);
1019 if (mpt->m_options & MPTSAS_OPT_PM) {
1020 (void) pm_idle_component(dip, 0);
1021 }
1022 fm_panic("mptsas init chip fail during resume");
1023 }
1024 /*
1025 * mptsas_update_driver_data needs interrupts so enable them
1026 * first.
1027 */
1028 MPTSAS_ENABLE_INTR(mpt);
1029 mptsas_update_driver_data(mpt);
1030
1031 /* start requests, if possible */
1032 mptsas_restart_hba(mpt);
1033
1034 mutex_exit(&mpt->m_mutex);
1035
1036 /*
1037 * Restart watch thread
1038 */
1039 mutex_enter(&mptsas_global_mutex);
1040 if (mptsas_timeout_id == 0) {
1041 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1042 mptsas_tick);
1043 mptsas_timeouts_enabled = 1;
1044 }
1045 mutex_exit(&mptsas_global_mutex);
1046
1047 /* report idle status to pm framework */
1048 if (mpt->m_options & MPTSAS_OPT_PM) {
1049 (void) pm_idle_component(dip, 0);
1050 }
1051
1052 return (DDI_SUCCESS);
1053
1054 default:
1055 return (DDI_FAILURE);
1056
1057 }
1058
1059 instance = ddi_get_instance(dip);
1060
1061 /*
1062 * Allocate softc information.
1063 */
1064 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1065 mptsas_log(NULL, CE_WARN,
1066 "mptsas%d: cannot allocate soft state", instance);
1067 goto fail;
1068 }
1069
1070 mpt = ddi_get_soft_state(mptsas_state, instance);
1071
1072 if (mpt == NULL) {
1073 mptsas_log(NULL, CE_WARN,
1074 "mptsas%d: cannot get soft state", instance);
1075 goto fail;
1076 }
1077
1078 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1079 scsi_size_clean(dip);
1080
1081 mpt->m_dip = dip;
1082 mpt->m_instance = instance;
1083
1084 /* Make a per-instance copy of the structures */
1085 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1086 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1087 mpt->m_reg_acc_attr = mptsas_dev_attr;
1088 mpt->m_dev_acc_attr = mptsas_dev_attr;
1089
1090 /*
1091 * Initialize FMA
1092 */
1093 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1094 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1095 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1096 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1097
1098 mptsas_fm_init(mpt);
1099
1100 if (mptsas_alloc_handshake_msg(mpt,
1101 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1102 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1103 goto fail;
1104 }
1105
1106 /*
1107 * Setup configuration space
1108 */
1109 if (mptsas_config_space_init(mpt) == FALSE) {
1110 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1111 goto fail;
1112 }
1113 config_setup++;
1114
1115 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1116 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1117 mptsas_log(mpt, CE_WARN, "map setup failed");
1118 goto fail;
1119 }
1120 map_setup++;
1121
1122 /*
1123 * A taskq is created for dealing with the event handler
1124 */
1125 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1126 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1127 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1128 goto fail;
1129 }
1130 event_taskq_create++;
1131
1132 /*
1133 * A taskq is created for dealing with dr events
1134 */
1135 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1136 "mptsas_dr_taskq",
1137 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1138 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1139 "failed");
1140 goto fail;
1141 }
1142 dr_taskq_create++;
1143
1144 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1145 0, "mptsas_doneq_thread_threshold_prop", 10);
1146 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1147 0, "mptsas_doneq_length_threshold_prop", 8);
1148 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1149 0, "mptsas_doneq_thread_n_prop", 8);
1150
1151 if (mpt->m_doneq_thread_n) {
1152 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1153 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1154
1155 mutex_enter(&mpt->m_doneq_mutex);
1156 mpt->m_doneq_thread_id =
1157 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1158 * mpt->m_doneq_thread_n, KM_SLEEP);
1159
1160 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1161 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1162 CV_DRIVER, NULL);
1163 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1164 MUTEX_DRIVER, NULL);
1165 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1166 mpt->m_doneq_thread_id[j].flag |=
1167 MPTSAS_DONEQ_THREAD_ACTIVE;
1168 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1169 mpt->m_doneq_thread_id[j].arg.t = j;
1170 mpt->m_doneq_thread_id[j].threadp =
1171 thread_create(NULL, 0, mptsas_doneq_thread,
1172 &mpt->m_doneq_thread_id[j].arg,
1173 0, &p0, TS_RUN, minclsyspri);
1174 mpt->m_doneq_thread_id[j].donetail =
1175 &mpt->m_doneq_thread_id[j].doneq;
1176 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1177 }
1178 mutex_exit(&mpt->m_doneq_mutex);
1179 doneq_thread_create++;
1180 }
1181
1182 /* Initialize mutex used in interrupt handler */
1183 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1184 DDI_INTR_PRI(mpt->m_intr_pri));
1185 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1186 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1187 DDI_INTR_PRI(mpt->m_intr_pri));
1188 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1189 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1190 NULL, MUTEX_DRIVER,
1191 DDI_INTR_PRI(mpt->m_intr_pri));
1192 }
1193
1194 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1195 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1196 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1197 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1198 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1199 mutex_init_done++;
1200
1201 /*
1202 * Disable hardware interrupt since we're not ready to
1203 * handle it yet.
1204 */
1205 MPTSAS_DISABLE_INTR(mpt);
1206 if (mptsas_register_intrs(mpt) == FALSE)
1207 goto fail;
1208 intr_added++;
1209
1210 mutex_enter(&mpt->m_mutex);
1211 /*
1212 * Initialize power management component
1213 */
1214 if (mpt->m_options & MPTSAS_OPT_PM) {
1215 if (mptsas_init_pm(mpt)) {
1216 mutex_exit(&mpt->m_mutex);
1217 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1218 "failed");
1219 goto fail;
1220 }
1221 }
1222
1223 /*
1224 * Initialize chip using Message Unit Reset, if allowed
1225 */
1226 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1227 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1228 mutex_exit(&mpt->m_mutex);
1229 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1230 goto fail;
1231 }
1232
1233 /*
1234 * Fill in the phy_info structure and get the base WWID
1235 */
1236 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1237 mptsas_log(mpt, CE_WARN,
1238 "mptsas_get_manufacture_page5 failed!");
1239 goto fail;
1240 }
1241
1242 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1243 mptsas_log(mpt, CE_WARN,
1244 "mptsas_get_sas_io_unit_page_hndshk failed!");
1245 goto fail;
1246 }
1247
1248 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1249 mptsas_log(mpt, CE_WARN,
1250 "mptsas_get_manufacture_page0 failed!");
1251 goto fail;
1252 }
1253
1254 mutex_exit(&mpt->m_mutex);
1255
1256 /*
1257 * Register the iport for multiple port HBA
1258 */
1259 mptsas_iport_register(mpt);
1260
1261 /*
1262 * initialize SCSI HBA transport structure
1263 */
1264 if (mptsas_hba_setup(mpt) == FALSE)
1265 goto fail;
1266 hba_attach_setup++;
1267
1268 if (mptsas_smp_setup(mpt) == FALSE)
1269 goto fail;
1270 smp_attach_setup++;
1271
1272 if (mptsas_cache_create(mpt) == FALSE)
1273 goto fail;
1274
1275 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1276 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1277 if (mpt->m_scsi_reset_delay == 0) {
1278 mptsas_log(mpt, CE_NOTE,
1279 "scsi_reset_delay of 0 is not recommended,"
1280 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1281 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1282 }
1283
1284 /*
1285 * Initialize the wait and done FIFO queue
1286 */
1287 mpt->m_donetail = &mpt->m_doneq;
1288 mpt->m_waitqtail = &mpt->m_waitq;
1289 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1290 mpt->m_tx_draining = 0;
1291
1292 /*
1293 * ioc cmd queue initialize
1294 */
1295 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1296 mpt->m_dev_handle = 0xFFFF;
1297
1298 MPTSAS_ENABLE_INTR(mpt);
1299
1300 /*
1301 * enable event notification
1302 */
1303 mutex_enter(&mpt->m_mutex);
1304 if (mptsas_ioc_enable_event_notification(mpt)) {
1305 mutex_exit(&mpt->m_mutex);
1306 goto fail;
1307 }
1308 mutex_exit(&mpt->m_mutex);
1309
1310 /*
1311 * Initialize PHY info for smhba
1312 */
1313 if (mptsas_smhba_setup(mpt)) {
1314 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1315 "failed");
1316 goto fail;
1317 }
1318
1319 /* Check all dma handles allocated in attach */
1320 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1321 != DDI_SUCCESS) ||
1322 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1323 != DDI_SUCCESS) ||
1324 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1325 != DDI_SUCCESS) ||
1326 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1327 != DDI_SUCCESS) ||
1328 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1329 != DDI_SUCCESS)) {
1330 goto fail;
1331 }
1332
1333 /* Check all acc handles allocated in attach */
1334 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1335 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1336 != DDI_SUCCESS) ||
1337 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1338 != DDI_SUCCESS) ||
1339 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1340 != DDI_SUCCESS) ||
1341 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1342 != DDI_SUCCESS) ||
1343 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1344 != DDI_SUCCESS) ||
1345 (mptsas_check_acc_handle(mpt->m_config_handle)
1346 != DDI_SUCCESS)) {
1347 goto fail;
1348 }
1349
1350 /*
1351 * After this point, we are not going to fail the attach.
1352 */
1353 /*
1354 * used for mptsas_watch
1355 */
1356 mptsas_list_add(mpt);
1357
1358 mutex_enter(&mptsas_global_mutex);
1359 if (mptsas_timeouts_enabled == 0) {
1360 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1361 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1362
1363 mptsas_tick = mptsas_scsi_watchdog_tick *
1364 drv_usectohz((clock_t)1000000);
1365
1366 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1367 mptsas_timeouts_enabled = 1;
1368 }
1369 mutex_exit(&mptsas_global_mutex);
1370
1371 /* Print message of HBA present */
1372 ddi_report_dev(dip);
1373
1374 /* report idle status to pm framework */
1375 if (mpt->m_options & MPTSAS_OPT_PM) {
1376 (void) pm_idle_component(dip, 0);
1377 }
1378
1379 return (DDI_SUCCESS);
1380
1381 fail:
1382 mptsas_log(mpt, CE_WARN, "attach failed");
1383 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1384 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1385 if (mpt) {
1386 mutex_enter(&mptsas_global_mutex);
1387
1388 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1389 timeout_id_t tid = mptsas_timeout_id;
1390 mptsas_timeouts_enabled = 0;
1391 mptsas_timeout_id = 0;
1392 mutex_exit(&mptsas_global_mutex);
1393 (void) untimeout(tid);
1394 mutex_enter(&mptsas_global_mutex);
1395 }
1396 mutex_exit(&mptsas_global_mutex);
1397 /* deallocate in reverse order */
1398 mptsas_cache_destroy(mpt);
1399
1400 if (smp_attach_setup) {
1401 mptsas_smp_teardown(mpt);
1402 }
1403 if (hba_attach_setup) {
1404 mptsas_hba_teardown(mpt);
1405 }
1406
1407 if (mpt->m_active) {
1408 mptsas_hash_uninit(&mpt->m_active->m_smptbl,
1409 sizeof (mptsas_smp_t));
1410 mptsas_hash_uninit(&mpt->m_active->m_tgttbl,
1411 sizeof (mptsas_target_t));
1412 mptsas_free_active_slots(mpt);
1413 }
1414 if (intr_added) {
1415 mptsas_unregister_intrs(mpt);
1416 }
1417
1418 if (doneq_thread_create) {
1419 mutex_enter(&mpt->m_doneq_mutex);
1420 doneq_thread_num = mpt->m_doneq_thread_n;
1421 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1422 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1423 mpt->m_doneq_thread_id[j].flag &=
1424 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1425 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1426 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1427 }
1428 while (mpt->m_doneq_thread_n) {
1429 cv_wait(&mpt->m_doneq_thread_cv,
1430 &mpt->m_doneq_mutex);
1431 }
1432 for (j = 0; j < doneq_thread_num; j++) {
1433 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1434 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1435 }
1436 kmem_free(mpt->m_doneq_thread_id,
1437 sizeof (mptsas_doneq_thread_list_t)
1438 * doneq_thread_num);
1439 mutex_exit(&mpt->m_doneq_mutex);
1440 cv_destroy(&mpt->m_doneq_thread_cv);
1441 mutex_destroy(&mpt->m_doneq_mutex);
1442 }
1443 if (event_taskq_create) {
1444 ddi_taskq_destroy(mpt->m_event_taskq);
1445 }
1446 if (dr_taskq_create) {
1447 ddi_taskq_destroy(mpt->m_dr_taskq);
1448 }
1449 if (mutex_init_done) {
1450 mutex_destroy(&mpt->m_tx_waitq_mutex);
1451 mutex_destroy(&mpt->m_passthru_mutex);
1452 mutex_destroy(&mpt->m_mutex);
1453 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1454 mutex_destroy(
1455 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1456 }
1457 cv_destroy(&mpt->m_cv);
1458 cv_destroy(&mpt->m_passthru_cv);
1459 cv_destroy(&mpt->m_fw_cv);
1460 cv_destroy(&mpt->m_config_cv);
1461 cv_destroy(&mpt->m_fw_diag_cv);
1462 }
1463
1464 if (map_setup) {
1465 mptsas_cfg_fini(mpt);
1466 }
1467 if (config_setup) {
1468 mptsas_config_space_fini(mpt);
1469 }
1470 mptsas_free_handshake_msg(mpt);
1471 mptsas_hba_fini(mpt);
1472
1473 mptsas_fm_fini(mpt);
1474 ddi_soft_state_free(mptsas_state, instance);
1475 ddi_prop_remove_all(dip);
1476 }
1477 return (DDI_FAILURE);
1478 }
1479
1480 static int
1481 mptsas_suspend(dev_info_t *devi)
1482 {
1483 mptsas_t *mpt, *g;
1484 scsi_hba_tran_t *tran;
1485
1486 if (scsi_hba_iport_unit_address(devi)) {
1487 return (DDI_SUCCESS);
1488 }
1489
1490 if ((tran = ddi_get_driver_private(devi)) == NULL)
1491 return (DDI_SUCCESS);
1492
1493 mpt = TRAN2MPT(tran);
1494 if (!mpt) {
1495 return (DDI_SUCCESS);
1496 }
1497
1498 mutex_enter(&mpt->m_mutex);
1499
1500 if (mpt->m_suspended++) {
1501 mutex_exit(&mpt->m_mutex);
1502 return (DDI_SUCCESS);
1503 }
1504
1505 /*
1506 * Cancel timeout threads for this mpt
1507 */
1508 if (mpt->m_quiesce_timeid) {
1509 timeout_id_t tid = mpt->m_quiesce_timeid;
1510 mpt->m_quiesce_timeid = 0;
1511 mutex_exit(&mpt->m_mutex);
1512 (void) untimeout(tid);
1513 mutex_enter(&mpt->m_mutex);
1514 }
1515
1516 if (mpt->m_restart_cmd_timeid) {
1517 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1518 mpt->m_restart_cmd_timeid = 0;
1519 mutex_exit(&mpt->m_mutex);
1520 (void) untimeout(tid);
1521 mutex_enter(&mpt->m_mutex);
1522 }
1523
1524 mutex_exit(&mpt->m_mutex);
1525
1526 (void) pm_idle_component(mpt->m_dip, 0);
1527
1528 /*
1529 * Cancel watch threads if all mpts suspended
1530 */
1531 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1532 for (g = mptsas_head; g != NULL; g = g->m_next) {
1533 if (!g->m_suspended)
1534 break;
1535 }
1536 rw_exit(&mptsas_global_rwlock);
1537
1538 mutex_enter(&mptsas_global_mutex);
1539 if (g == NULL) {
1540 timeout_id_t tid;
1541
1542 mptsas_timeouts_enabled = 0;
1543 if (mptsas_timeout_id) {
1544 tid = mptsas_timeout_id;
1545 mptsas_timeout_id = 0;
1546 mutex_exit(&mptsas_global_mutex);
1547 (void) untimeout(tid);
1548 mutex_enter(&mptsas_global_mutex);
1549 }
1550 if (mptsas_reset_watch) {
1551 tid = mptsas_reset_watch;
1552 mptsas_reset_watch = 0;
1553 mutex_exit(&mptsas_global_mutex);
1554 (void) untimeout(tid);
1555 mutex_enter(&mptsas_global_mutex);
1556 }
1557 }
1558 mutex_exit(&mptsas_global_mutex);
1559
1560 mutex_enter(&mpt->m_mutex);
1561
1562 /*
1563 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1564 */
1565 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1566 (mpt->m_power_level != PM_LEVEL_D0)) {
1567 mutex_exit(&mpt->m_mutex);
1568 return (DDI_SUCCESS);
1569 }
1570
1571 /* Disable HBA interrupts in hardware */
1572 MPTSAS_DISABLE_INTR(mpt);
1573 /*
1574 * Send RAID action system shutdown to sync IR
1575 */
1576 mptsas_raid_action_system_shutdown(mpt);
1577
1578 mutex_exit(&mpt->m_mutex);
1579
1580 /* drain the taskq */
1581 ddi_taskq_wait(mpt->m_event_taskq);
1582 ddi_taskq_wait(mpt->m_dr_taskq);
1583
1584 return (DDI_SUCCESS);
1585 }
1586
1587 #ifdef __sparc
1588 /*ARGSUSED*/
1589 static int
1590 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1591 {
1592 mptsas_t *mpt;
1593 scsi_hba_tran_t *tran;
1594
1595 /*
1596 * If this call is for iport, just return.
1597 */
1598 if (scsi_hba_iport_unit_address(devi))
1599 return (DDI_SUCCESS);
1600
1601 if ((tran = ddi_get_driver_private(devi)) == NULL)
1602 return (DDI_SUCCESS);
1603
1604 if ((mpt = TRAN2MPT(tran)) == NULL)
1605 return (DDI_SUCCESS);
1606
1607 /*
1608 * Send RAID action system shutdown to sync IR. Disable HBA
1609 * interrupts in hardware first.
1610 */
1611 MPTSAS_DISABLE_INTR(mpt);
1612 mptsas_raid_action_system_shutdown(mpt);
1613
1614 return (DDI_SUCCESS);
1615 }
1616 #else /* __sparc */
1617 /*
1618 * quiesce(9E) entry point.
1619 *
1620 * This function is called when the system is single-threaded at high
1621 * PIL with preemption disabled. Therefore, this function must not be
1622 * blocked.
1623 *
1624 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1625 * DDI_FAILURE indicates an error condition and should almost never happen.
1626 */
1627 static int
1628 mptsas_quiesce(dev_info_t *devi)
1629 {
1630 mptsas_t *mpt;
1631 scsi_hba_tran_t *tran;
1632
1633 /*
1634 * If this call is for iport, just return.
1635 */
1636 if (scsi_hba_iport_unit_address(devi))
1637 return (DDI_SUCCESS);
1638
1639 if ((tran = ddi_get_driver_private(devi)) == NULL)
1640 return (DDI_SUCCESS);
1641
1642 if ((mpt = TRAN2MPT(tran)) == NULL)
1643 return (DDI_SUCCESS);
1644
1645 /* Disable HBA interrupts in hardware */
1646 MPTSAS_DISABLE_INTR(mpt);
1647 /* Send RAID action system shutdonw to sync IR */
1648 mptsas_raid_action_system_shutdown(mpt);
1649
1650 return (DDI_SUCCESS);
1651 }
1652 #endif /* __sparc */
1653
1654 /*
1655 * detach(9E). Remove all device allocations and system resources;
1656 * disable device interrupts.
1657 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1658 */
1659 static int
1660 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1661 {
1662 /* CONSTCOND */
1663 ASSERT(NO_COMPETING_THREADS);
1664 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1665
1666 switch (cmd) {
1667 case DDI_DETACH:
1668 return (mptsas_do_detach(devi));
1669
1670 case DDI_SUSPEND:
1671 return (mptsas_suspend(devi));
1672
1673 default:
1674 return (DDI_FAILURE);
1675 }
1676 /* NOTREACHED */
1677 }
1678
1679 static int
1680 mptsas_do_detach(dev_info_t *dip)
1681 {
1682 mptsas_t *mpt;
1683 scsi_hba_tran_t *tran;
1684 int circ = 0;
1685 int circ1 = 0;
1686 mdi_pathinfo_t *pip = NULL;
1687 int i;
1688 int doneq_thread_num = 0;
1689
1690 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1691
1692 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1693 return (DDI_FAILURE);
1694
1695 mpt = TRAN2MPT(tran);
1696 if (!mpt) {
1697 return (DDI_FAILURE);
1698 }
1699 /*
1700 * Still have pathinfo child, should not detach mpt driver
1701 */
1702 if (scsi_hba_iport_unit_address(dip)) {
1703 if (mpt->m_mpxio_enable) {
1704 /*
1705 * MPxIO enabled for the iport
1706 */
1707 ndi_devi_enter(scsi_vhci_dip, &circ1);
1708 ndi_devi_enter(dip, &circ);
1709 while (pip = mdi_get_next_client_path(dip, NULL)) {
1710 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1711 continue;
1712 }
1713 ndi_devi_exit(dip, circ);
1714 ndi_devi_exit(scsi_vhci_dip, circ1);
1715 NDBG12(("detach failed because of "
1716 "outstanding path info"));
1717 return (DDI_FAILURE);
1718 }
1719 ndi_devi_exit(dip, circ);
1720 ndi_devi_exit(scsi_vhci_dip, circ1);
1721 (void) mdi_phci_unregister(dip, 0);
1722 }
1723
1724 ddi_prop_remove_all(dip);
1725
1726 return (DDI_SUCCESS);
1727 }
1728
1729 /* Make sure power level is D0 before accessing registers */
1730 if (mpt->m_options & MPTSAS_OPT_PM) {
1731 (void) pm_busy_component(dip, 0);
1732 if (mpt->m_power_level != PM_LEVEL_D0) {
1733 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1734 DDI_SUCCESS) {
1735 mptsas_log(mpt, CE_WARN,
1736 "mptsas%d: Raise power request failed.",
1737 mpt->m_instance);
1738 (void) pm_idle_component(dip, 0);
1739 return (DDI_FAILURE);
1740 }
1741 }
1742 }
1743
1744 /*
1745 * Send RAID action system shutdown to sync IR. After action, send a
1746 * Message Unit Reset. Since after that DMA resource will be freed,
1747 * set ioc to READY state will avoid HBA initiated DMA operation.
1748 */
1749 mutex_enter(&mpt->m_mutex);
1750 MPTSAS_DISABLE_INTR(mpt);
1751 mptsas_raid_action_system_shutdown(mpt);
1752 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1753 (void) mptsas_ioc_reset(mpt, FALSE);
1754 mutex_exit(&mpt->m_mutex);
1755 mptsas_rem_intrs(mpt);
1756 ddi_taskq_destroy(mpt->m_event_taskq);
1757 ddi_taskq_destroy(mpt->m_dr_taskq);
1758
1759 if (mpt->m_doneq_thread_n) {
1760 mutex_enter(&mpt->m_doneq_mutex);
1761 doneq_thread_num = mpt->m_doneq_thread_n;
1762 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1763 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1764 mpt->m_doneq_thread_id[i].flag &=
1765 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1766 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1767 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1768 }
1769 while (mpt->m_doneq_thread_n) {
1770 cv_wait(&mpt->m_doneq_thread_cv,
1771 &mpt->m_doneq_mutex);
1772 }
1773 for (i = 0; i < doneq_thread_num; i++) {
1774 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1775 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1776 }
1777 kmem_free(mpt->m_doneq_thread_id,
1778 sizeof (mptsas_doneq_thread_list_t)
1779 * doneq_thread_num);
1780 mutex_exit(&mpt->m_doneq_mutex);
1781 cv_destroy(&mpt->m_doneq_thread_cv);
1782 mutex_destroy(&mpt->m_doneq_mutex);
1783 }
1784
1785 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1786
1787 mptsas_list_del(mpt);
1788
1789 /*
1790 * Cancel timeout threads for this mpt
1791 */
1792 mutex_enter(&mpt->m_mutex);
1793 if (mpt->m_quiesce_timeid) {
1794 timeout_id_t tid = mpt->m_quiesce_timeid;
1795 mpt->m_quiesce_timeid = 0;
1796 mutex_exit(&mpt->m_mutex);
1797 (void) untimeout(tid);
1798 mutex_enter(&mpt->m_mutex);
1799 }
1800
1801 if (mpt->m_restart_cmd_timeid) {
1802 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1803 mpt->m_restart_cmd_timeid = 0;
1804 mutex_exit(&mpt->m_mutex);
1805 (void) untimeout(tid);
1806 mutex_enter(&mpt->m_mutex);
1807 }
1808
1809 mutex_exit(&mpt->m_mutex);
1810
1811 /*
1812 * last mpt? ... if active, CANCEL watch threads.
1813 */
1814 mutex_enter(&mptsas_global_mutex);
1815 if (mptsas_head == NULL) {
1816 timeout_id_t tid;
1817 /*
1818 * Clear mptsas_timeouts_enable so that the watch thread
1819 * gets restarted on DDI_ATTACH
1820 */
1821 mptsas_timeouts_enabled = 0;
1822 if (mptsas_timeout_id) {
1823 tid = mptsas_timeout_id;
1824 mptsas_timeout_id = 0;
1825 mutex_exit(&mptsas_global_mutex);
1826 (void) untimeout(tid);
1827 mutex_enter(&mptsas_global_mutex);
1828 }
1829 if (mptsas_reset_watch) {
1830 tid = mptsas_reset_watch;
1831 mptsas_reset_watch = 0;
1832 mutex_exit(&mptsas_global_mutex);
1833 (void) untimeout(tid);
1834 mutex_enter(&mptsas_global_mutex);
1835 }
1836 }
1837 mutex_exit(&mptsas_global_mutex);
1838
1839 /*
1840 * Delete Phy stats
1841 */
1842 mptsas_destroy_phy_stats(mpt);
1843
1844 /*
1845 * Delete nt_active.
1846 */
1847 mutex_enter(&mpt->m_mutex);
1848 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t));
1849 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t));
1850 mptsas_free_active_slots(mpt);
1851 mutex_exit(&mpt->m_mutex);
1852
1853 /* deallocate everything that was allocated in mptsas_attach */
1854 mptsas_cache_destroy(mpt);
1855
1856 mptsas_hba_fini(mpt);
1857 mptsas_cfg_fini(mpt);
1858
1859 /* Lower the power informing PM Framework */
1860 if (mpt->m_options & MPTSAS_OPT_PM) {
1861 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
1862 mptsas_log(mpt, CE_WARN,
1863 "!mptsas%d: Lower power request failed "
1864 "during detach, ignoring.",
1865 mpt->m_instance);
1866 }
1867
1868 mutex_destroy(&mpt->m_tx_waitq_mutex);
1869 mutex_destroy(&mpt->m_passthru_mutex);
1870 mutex_destroy(&mpt->m_mutex);
1871 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1872 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
1873 }
1874 cv_destroy(&mpt->m_cv);
1875 cv_destroy(&mpt->m_passthru_cv);
1876 cv_destroy(&mpt->m_fw_cv);
1877 cv_destroy(&mpt->m_config_cv);
1878 cv_destroy(&mpt->m_fw_diag_cv);
1879
1880
1881 mptsas_smp_teardown(mpt);
1882 mptsas_hba_teardown(mpt);
1883
1884 mptsas_config_space_fini(mpt);
1885
1886 mptsas_free_handshake_msg(mpt);
1887
1888 mptsas_fm_fini(mpt);
1889 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
1890 ddi_prop_remove_all(dip);
1891
1892 return (DDI_SUCCESS);
1893 }
1894
1895 static void
1896 mptsas_list_add(mptsas_t *mpt)
1897 {
1898 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1899
1900 if (mptsas_head == NULL) {
1901 mptsas_head = mpt;
1902 } else {
1903 mptsas_tail->m_next = mpt;
1904 }
1905 mptsas_tail = mpt;
1906 rw_exit(&mptsas_global_rwlock);
1907 }
1908
1909 static void
1910 mptsas_list_del(mptsas_t *mpt)
1911 {
1912 mptsas_t *m;
1913 /*
1914 * Remove device instance from the global linked list
1915 */
1916 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1917 if (mptsas_head == mpt) {
1918 m = mptsas_head = mpt->m_next;
1919 } else {
1920 for (m = mptsas_head; m != NULL; m = m->m_next) {
1921 if (m->m_next == mpt) {
1922 m->m_next = mpt->m_next;
1923 break;
1924 }
1925 }
1926 if (m == NULL) {
1927 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
1928 }
1929 }
1930
1931 if (mptsas_tail == mpt) {
1932 mptsas_tail = m;
1933 }
1934 rw_exit(&mptsas_global_rwlock);
1935 }
1936
1937 static int
1938 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
1939 {
1940 ddi_dma_attr_t task_dma_attrs;
1941
1942 mpt->m_hshk_dma_size = 0;
1943 task_dma_attrs = mpt->m_msg_dma_attr;
1944 task_dma_attrs.dma_attr_sgllen = 1;
1945 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
1946
1947 /* allocate Task Management ddi_dma resources */
1948 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
1949 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
1950 alloc_size, NULL) == FALSE) {
1951 return (DDI_FAILURE);
1952 }
1953 mpt->m_hshk_dma_size = alloc_size;
1954
1955 return (DDI_SUCCESS);
1956 }
1957
1958 static void
1959 mptsas_free_handshake_msg(mptsas_t *mpt)
1960 {
1961 if (mpt->m_hshk_dma_size == 0)
1962 return;
1963 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
1964 mpt->m_hshk_dma_size = 0;
1965 }
1966
1967 static int
1968 mptsas_hba_setup(mptsas_t *mpt)
1969 {
1970 scsi_hba_tran_t *hba_tran;
1971 int tran_flags;
1972
1973 /* Allocate a transport structure */
1974 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
1975 SCSI_HBA_CANSLEEP);
1976 ASSERT(mpt->m_tran != NULL);
1977
1978 hba_tran->tran_hba_private = mpt;
1979 hba_tran->tran_tgt_private = NULL;
1980
1981 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
1982 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
1983
1984 hba_tran->tran_start = mptsas_scsi_start;
1985 hba_tran->tran_reset = mptsas_scsi_reset;
1986 hba_tran->tran_abort = mptsas_scsi_abort;
1987 hba_tran->tran_getcap = mptsas_scsi_getcap;
1988 hba_tran->tran_setcap = mptsas_scsi_setcap;
1989 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
1990 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
1991
1992 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
1993 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
1994 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
1995
1996 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
1997 hba_tran->tran_get_name = mptsas_get_name;
1998
1999 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2000 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2001 hba_tran->tran_bus_reset = NULL;
2002
2003 hba_tran->tran_add_eventcall = NULL;
2004 hba_tran->tran_get_eventcookie = NULL;
2005 hba_tran->tran_post_event = NULL;
2006 hba_tran->tran_remove_eventcall = NULL;
2007
2008 hba_tran->tran_bus_config = mptsas_bus_config;
2009
2010 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2011
2012 /*
2013 * All children of the HBA are iports. We need tran was cloned.
2014 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2015 * inherited to iport's tran vector.
2016 */
2017 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2018
2019 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2020 hba_tran, tran_flags) != DDI_SUCCESS) {
2021 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2022 scsi_hba_tran_free(hba_tran);
2023 mpt->m_tran = NULL;
2024 return (FALSE);
2025 }
2026 return (TRUE);
2027 }
2028
2029 static void
2030 mptsas_hba_teardown(mptsas_t *mpt)
2031 {
2032 (void) scsi_hba_detach(mpt->m_dip);
2033 if (mpt->m_tran != NULL) {
2034 scsi_hba_tran_free(mpt->m_tran);
2035 mpt->m_tran = NULL;
2036 }
2037 }
2038
2039 static void
2040 mptsas_iport_register(mptsas_t *mpt)
2041 {
2042 int i, j;
2043 mptsas_phymask_t mask = 0x0;
2044 /*
2045 * initial value of mask is 0
2046 */
2047 mutex_enter(&mpt->m_mutex);
2048 for (i = 0; i < mpt->m_num_phys; i++) {
2049 mptsas_phymask_t phy_mask = 0x0;
2050 char phy_mask_name[MPTSAS_MAX_PHYS];
2051 uint8_t current_port;
2052
2053 if (mpt->m_phy_info[i].attached_devhdl == 0)
2054 continue;
2055
2056 bzero(phy_mask_name, sizeof (phy_mask_name));
2057
2058 current_port = mpt->m_phy_info[i].port_num;
2059
2060 if ((mask & (1 << i)) != 0)
2061 continue;
2062
2063 for (j = 0; j < mpt->m_num_phys; j++) {
2064 if (mpt->m_phy_info[j].attached_devhdl &&
2065 (mpt->m_phy_info[j].port_num == current_port)) {
2066 phy_mask |= (1 << j);
2067 }
2068 }
2069 mask = mask | phy_mask;
2070
2071 for (j = 0; j < mpt->m_num_phys; j++) {
2072 if ((phy_mask >> j) & 0x01) {
2073 mpt->m_phy_info[j].phy_mask = phy_mask;
2074 }
2075 }
2076
2077 (void) sprintf(phy_mask_name, "%x", phy_mask);
2078
2079 mutex_exit(&mpt->m_mutex);
2080 /*
2081 * register a iport
2082 */
2083 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2084 mutex_enter(&mpt->m_mutex);
2085 }
2086 mutex_exit(&mpt->m_mutex);
2087 /*
2088 * register a virtual port for RAID volume always
2089 */
2090 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2091
2092 }
2093
2094 static int
2095 mptsas_smp_setup(mptsas_t *mpt)
2096 {
2097 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2098 ASSERT(mpt->m_smptran != NULL);
2099 mpt->m_smptran->smp_tran_hba_private = mpt;
2100 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2101 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2102 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2103 smp_hba_tran_free(mpt->m_smptran);
2104 mpt->m_smptran = NULL;
2105 return (FALSE);
2106 }
2107 /*
2108 * Initialize smp hash table
2109 */
2110 mptsas_hash_init(&mpt->m_active->m_smptbl);
2111 mpt->m_smp_devhdl = 0xFFFF;
2112
2113 return (TRUE);
2114 }
2115
2116 static void
2117 mptsas_smp_teardown(mptsas_t *mpt)
2118 {
2119 (void) smp_hba_detach(mpt->m_dip);
2120 if (mpt->m_smptran != NULL) {
2121 smp_hba_tran_free(mpt->m_smptran);
2122 mpt->m_smptran = NULL;
2123 }
2124 mpt->m_smp_devhdl = 0;
2125 }
2126
2127 static int
2128 mptsas_cache_create(mptsas_t *mpt)
2129 {
2130 int instance = mpt->m_instance;
2131 char buf[64];
2132
2133 /*
2134 * create kmem cache for packets
2135 */
2136 (void) sprintf(buf, "mptsas%d_cache", instance);
2137 mpt->m_kmem_cache = kmem_cache_create(buf,
2138 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2139 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2140 NULL, (void *)mpt, NULL, 0);
2141
2142 if (mpt->m_kmem_cache == NULL) {
2143 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2144 return (FALSE);
2145 }
2146
2147 /*
2148 * create kmem cache for extra SGL frames if SGL cannot
2149 * be accomodated into main request frame.
2150 */
2151 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2152 mpt->m_cache_frames = kmem_cache_create(buf,
2153 sizeof (mptsas_cache_frames_t), 8,
2154 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2155 NULL, (void *)mpt, NULL, 0);
2156
2157 if (mpt->m_cache_frames == NULL) {
2158 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2159 return (FALSE);
2160 }
2161
2162 return (TRUE);
2163 }
2164
2165 static void
2166 mptsas_cache_destroy(mptsas_t *mpt)
2167 {
2168 /* deallocate in reverse order */
2169 if (mpt->m_cache_frames) {
2170 kmem_cache_destroy(mpt->m_cache_frames);
2171 mpt->m_cache_frames = NULL;
2172 }
2173 if (mpt->m_kmem_cache) {
2174 kmem_cache_destroy(mpt->m_kmem_cache);
2175 mpt->m_kmem_cache = NULL;
2176 }
2177 }
2178
2179 static int
2180 mptsas_power(dev_info_t *dip, int component, int level)
2181 {
2182 #ifndef __lock_lint
2183 _NOTE(ARGUNUSED(component))
2184 #endif
2185 mptsas_t *mpt;
2186 int rval = DDI_SUCCESS;
2187 int polls = 0;
2188 uint32_t ioc_status;
2189
2190 if (scsi_hba_iport_unit_address(dip) != 0)
2191 return (DDI_SUCCESS);
2192
2193 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2194 if (mpt == NULL) {
2195 return (DDI_FAILURE);
2196 }
2197
2198 mutex_enter(&mpt->m_mutex);
2199
2200 /*
2201 * If the device is busy, don't lower its power level
2202 */
2203 if (mpt->m_busy && (mpt->m_power_level > level)) {
2204 mutex_exit(&mpt->m_mutex);
2205 return (DDI_FAILURE);
2206 }
2207 switch (level) {
2208 case PM_LEVEL_D0:
2209 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2210 MPTSAS_POWER_ON(mpt);
2211 /*
2212 * Wait up to 30 seconds for IOC to come out of reset.
2213 */
2214 while (((ioc_status = ddi_get32(mpt->m_datap,
2215 &mpt->m_reg->Doorbell)) &
2216 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2217 if (polls++ > 3000) {
2218 break;
2219 }
2220 delay(drv_usectohz(10000));
2221 }
2222 /*
2223 * If IOC is not in operational state, try to hard reset it.
2224 */
2225 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2226 MPI2_IOC_STATE_OPERATIONAL) {
2227 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2228 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2229 mptsas_log(mpt, CE_WARN,
2230 "mptsas_power: hard reset failed");
2231 mutex_exit(&mpt->m_mutex);
2232 return (DDI_FAILURE);
2233 }
2234 }
2235 mpt->m_power_level = PM_LEVEL_D0;
2236 break;
2237 case PM_LEVEL_D3:
2238 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2239 MPTSAS_POWER_OFF(mpt);
2240 break;
2241 default:
2242 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2243 mpt->m_instance, level);
2244 rval = DDI_FAILURE;
2245 break;
2246 }
2247 mutex_exit(&mpt->m_mutex);
2248 return (rval);
2249 }
2250
2251 /*
2252 * Initialize configuration space and figure out which
2253 * chip and revison of the chip the mpt driver is using.
2254 */
2255 static int
2256 mptsas_config_space_init(mptsas_t *mpt)
2257 {
2258 NDBG0(("mptsas_config_space_init"));
2259
2260 if (mpt->m_config_handle != NULL)
2261 return (TRUE);
2262
2263 if (pci_config_setup(mpt->m_dip,
2264 &mpt->m_config_handle) != DDI_SUCCESS) {
2265 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2266 return (FALSE);
2267 }
2268
2269 /*
2270 * This is a workaround for a XMITS ASIC bug which does not
2271 * drive the CBE upper bits.
2272 */
2273 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2274 PCI_STAT_PERROR) {
2275 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2276 PCI_STAT_PERROR);
2277 }
2278
2279 mptsas_setup_cmd_reg(mpt);
2280
2281 /*
2282 * Get the chip device id:
2283 */
2284 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2285
2286 /*
2287 * Save the revision.
2288 */
2289 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2290
2291 /*
2292 * Save the SubSystem Vendor and Device IDs
2293 */
2294 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2295 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2296
2297 /*
2298 * Set the latency timer to 0x40 as specified by the upa -> pci
2299 * bridge chip design team. This may be done by the sparc pci
2300 * bus nexus driver, but the driver should make sure the latency
2301 * timer is correct for performance reasons.
2302 */
2303 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2304 MPTSAS_LATENCY_TIMER);
2305
2306 (void) mptsas_get_pci_cap(mpt);
2307 return (TRUE);
2308 }
2309
2310 static void
2311 mptsas_config_space_fini(mptsas_t *mpt)
2312 {
2313 if (mpt->m_config_handle != NULL) {
2314 mptsas_disable_bus_master(mpt);
2315 pci_config_teardown(&mpt->m_config_handle);
2316 mpt->m_config_handle = NULL;
2317 }
2318 }
2319
2320 static void
2321 mptsas_setup_cmd_reg(mptsas_t *mpt)
2322 {
2323 ushort_t cmdreg;
2324
2325 /*
2326 * Set the command register to the needed values.
2327 */
2328 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2329 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2330 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2331 cmdreg &= ~PCI_COMM_IO;
2332 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2333 }
2334
2335 static void
2336 mptsas_disable_bus_master(mptsas_t *mpt)
2337 {
2338 ushort_t cmdreg;
2339
2340 /*
2341 * Clear the master enable bit in the PCI command register.
2342 * This prevents any bus mastering activity like DMA.
2343 */
2344 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2345 cmdreg &= ~PCI_COMM_ME;
2346 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2347 }
2348
2349 int
2350 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2351 {
2352 ddi_dma_attr_t attrs;
2353
2354 attrs = mpt->m_io_dma_attr;
2355 attrs.dma_attr_sgllen = 1;
2356
2357 ASSERT(dma_statep != NULL);
2358
2359 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2360 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2361 &dma_statep->cookie) == FALSE) {
2362 return (DDI_FAILURE);
2363 }
2364
2365 return (DDI_SUCCESS);
2366 }
2367
2368 void
2369 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2370 {
2371 ASSERT(dma_statep != NULL);
2372 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2373 dma_statep->size = 0;
2374 }
2375
2376 int
2377 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2378 {
2379 ddi_dma_attr_t attrs;
2380 ddi_dma_handle_t dma_handle;
2381 caddr_t memp;
2382 ddi_acc_handle_t accessp;
2383 int rval;
2384
2385 ASSERT(mutex_owned(&mpt->m_mutex));
2386
2387 attrs = mpt->m_msg_dma_attr;
2388 attrs.dma_attr_sgllen = 1;
2389 attrs.dma_attr_granular = size;
2390
2391 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2392 &accessp, &memp, size, NULL) == FALSE) {
2393 return (DDI_FAILURE);
2394 }
2395
2396 rval = (*callback) (mpt, memp, var, accessp);
2397
2398 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2399 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2400 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2401 rval = DDI_FAILURE;
2402 }
2403
2404 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2405 return (rval);
2406
2407 }
2408
2409 static int
2410 mptsas_alloc_request_frames(mptsas_t *mpt)
2411 {
2412 ddi_dma_attr_t frame_dma_attrs;
2413 caddr_t memp;
2414 ddi_dma_cookie_t cookie;
2415 size_t mem_size;
2416
2417 /*
2418 * re-alloc when it has already alloced
2419 */
2420 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2421 &mpt->m_acc_req_frame_hdl);
2422
2423 /*
2424 * The size of the request frame pool is:
2425 * Number of Request Frames * Request Frame Size
2426 */
2427 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2428
2429 /*
2430 * set the DMA attributes. System Request Message Frames must be
2431 * aligned on a 16-byte boundry.
2432 */
2433 frame_dma_attrs = mpt->m_msg_dma_attr;
2434 frame_dma_attrs.dma_attr_align = 16;
2435 frame_dma_attrs.dma_attr_sgllen = 1;
2436
2437 /*
2438 * allocate the request frame pool.
2439 */
2440 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2441 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2442 mem_size, &cookie) == FALSE) {
2443 return (DDI_FAILURE);
2444 }
2445
2446 /*
2447 * Store the request frame memory address. This chip uses this
2448 * address to dma to and from the driver's frame. The second
2449 * address is the address mpt uses to fill in the frame.
2450 */
2451 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2452 mpt->m_req_frame = memp;
2453
2454 /*
2455 * Clear the request frame pool.
2456 */
2457 bzero(mpt->m_req_frame, mem_size);
2458
2459 return (DDI_SUCCESS);
2460 }
2461
2462 static int
2463 mptsas_alloc_reply_frames(mptsas_t *mpt)
2464 {
2465 ddi_dma_attr_t frame_dma_attrs;
2466 caddr_t memp;
2467 ddi_dma_cookie_t cookie;
2468 size_t mem_size;
2469
2470 /*
2471 * re-alloc when it has already alloced
2472 */
2473 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2474 &mpt->m_acc_reply_frame_hdl);
2475
2476 /*
2477 * The size of the reply frame pool is:
2478 * Number of Reply Frames * Reply Frame Size
2479 */
2480 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2481
2482 /*
2483 * set the DMA attributes. System Reply Message Frames must be
2484 * aligned on a 4-byte boundry. This is the default.
2485 */
2486 frame_dma_attrs = mpt->m_msg_dma_attr;
2487 frame_dma_attrs.dma_attr_sgllen = 1;
2488
2489 /*
2490 * allocate the reply frame pool
2491 */
2492 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2493 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2494 mem_size, &cookie) == FALSE) {
2495 return (DDI_FAILURE);
2496 }
2497
2498 /*
2499 * Store the reply frame memory address. This chip uses this
2500 * address to dma to and from the driver's frame. The second
2501 * address is the address mpt uses to process the frame.
2502 */
2503 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2504 mpt->m_reply_frame = memp;
2505
2506 /*
2507 * Clear the reply frame pool.
2508 */
2509 bzero(mpt->m_reply_frame, mem_size);
2510
2511 return (DDI_SUCCESS);
2512 }
2513
2514 static int
2515 mptsas_alloc_free_queue(mptsas_t *mpt)
2516 {
2517 ddi_dma_attr_t frame_dma_attrs;
2518 caddr_t memp;
2519 ddi_dma_cookie_t cookie;
2520 size_t mem_size;
2521
2522 /*
2523 * re-alloc when it has already alloced
2524 */
2525 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2526 &mpt->m_acc_free_queue_hdl);
2527
2528 /*
2529 * The reply free queue size is:
2530 * Reply Free Queue Depth * 4
2531 * The "4" is the size of one 32 bit address (low part of 64-bit
2532 * address)
2533 */
2534 mem_size = mpt->m_free_queue_depth * 4;
2535
2536 /*
2537 * set the DMA attributes The Reply Free Queue must be aligned on a
2538 * 16-byte boundry.
2539 */
2540 frame_dma_attrs = mpt->m_msg_dma_attr;
2541 frame_dma_attrs.dma_attr_align = 16;
2542 frame_dma_attrs.dma_attr_sgllen = 1;
2543
2544 /*
2545 * allocate the reply free queue
2546 */
2547 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2548 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2549 mem_size, &cookie) == FALSE) {
2550 return (DDI_FAILURE);
2551 }
2552
2553 /*
2554 * Store the reply free queue memory address. This chip uses this
2555 * address to read from the reply free queue. The second address
2556 * is the address mpt uses to manage the queue.
2557 */
2558 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2559 mpt->m_free_queue = memp;
2560
2561 /*
2562 * Clear the reply free queue memory.
2563 */
2564 bzero(mpt->m_free_queue, mem_size);
2565
2566 return (DDI_SUCCESS);
2567 }
2568
2569 static int
2570 mptsas_alloc_post_queue(mptsas_t *mpt)
2571 {
2572 ddi_dma_attr_t frame_dma_attrs;
2573 caddr_t memp;
2574 ddi_dma_cookie_t cookie;
2575 size_t mem_size;
2576
2577 /*
2578 * re-alloc when it has already alloced
2579 */
2580 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2581 &mpt->m_acc_post_queue_hdl);
2582
2583 /*
2584 * The reply descriptor post queue size is:
2585 * Reply Descriptor Post Queue Depth * 8
2586 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2587 */
2588 mem_size = mpt->m_post_queue_depth * 8;
2589
2590 /*
2591 * set the DMA attributes. The Reply Descriptor Post Queue must be
2592 * aligned on a 16-byte boundry.
2593 */
2594 frame_dma_attrs = mpt->m_msg_dma_attr;
2595 frame_dma_attrs.dma_attr_align = 16;
2596 frame_dma_attrs.dma_attr_sgllen = 1;
2597
2598 /*
2599 * allocate the reply post queue
2600 */
2601 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2602 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2603 mem_size, &cookie) == FALSE) {
2604 return (DDI_FAILURE);
2605 }
2606
2607 /*
2608 * Store the reply descriptor post queue memory address. This chip
2609 * uses this address to write to the reply descriptor post queue. The
2610 * second address is the address mpt uses to manage the queue.
2611 */
2612 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2613 mpt->m_post_queue = memp;
2614
2615 /*
2616 * Clear the reply post queue memory.
2617 */
2618 bzero(mpt->m_post_queue, mem_size);
2619
2620 return (DDI_SUCCESS);
2621 }
2622
2623 static void
2624 mptsas_alloc_reply_args(mptsas_t *mpt)
2625 {
2626 if (mpt->m_replyh_args == NULL) {
2627 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2628 mpt->m_max_replies, KM_SLEEP);
2629 }
2630 }
2631
2632 static int
2633 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2634 {
2635 mptsas_cache_frames_t *frames = NULL;
2636 if (cmd->cmd_extra_frames == NULL) {
2637 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2638 if (frames == NULL) {
2639 return (DDI_FAILURE);
2640 }
2641 cmd->cmd_extra_frames = frames;
2642 }
2643 return (DDI_SUCCESS);
2644 }
2645
2646 static void
2647 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2648 {
2649 if (cmd->cmd_extra_frames) {
2650 kmem_cache_free(mpt->m_cache_frames,
2651 (void *)cmd->cmd_extra_frames);
2652 cmd->cmd_extra_frames = NULL;
2653 }
2654 }
2655
2656 static void
2657 mptsas_cfg_fini(mptsas_t *mpt)
2658 {
2659 NDBG0(("mptsas_cfg_fini"));
2660 ddi_regs_map_free(&mpt->m_datap);
2661 }
2662
2663 static void
2664 mptsas_hba_fini(mptsas_t *mpt)
2665 {
2666 NDBG0(("mptsas_hba_fini"));
2667
2668 /*
2669 * Free up any allocated memory
2670 */
2671 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2672 &mpt->m_acc_req_frame_hdl);
2673
2674 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2675 &mpt->m_acc_reply_frame_hdl);
2676
2677 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2678 &mpt->m_acc_free_queue_hdl);
2679
2680 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2681 &mpt->m_acc_post_queue_hdl);
2682
2683 if (mpt->m_replyh_args != NULL) {
2684 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2685 * mpt->m_max_replies);
2686 }
2687 }
2688
2689 static int
2690 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2691 {
2692 int lun = 0;
2693 char *sas_wwn = NULL;
2694 int phynum = -1;
2695 int reallen = 0;
2696
2697 /* Get the target num */
2698 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2699 LUN_PROP, 0);
2700
2701 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2702 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2703 /*
2704 * Stick in the address of form "pPHY,LUN"
2705 */
2706 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2707 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2708 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2709 == DDI_PROP_SUCCESS) {
2710 /*
2711 * Stick in the address of the form "wWWN,LUN"
2712 */
2713 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2714 ddi_prop_free(sas_wwn);
2715 } else {
2716 return (DDI_FAILURE);
2717 }
2718
2719 ASSERT(reallen < len);
2720 if (reallen >= len) {
2721 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
2722 "length too small, it needs to be %d bytes", reallen + 1);
2723 }
2724 return (DDI_SUCCESS);
2725 }
2726
2727 /*
2728 * tran_tgt_init(9E) - target device instance initialization
2729 */
2730 static int
2731 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2732 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2733 {
2734 #ifndef __lock_lint
2735 _NOTE(ARGUNUSED(hba_tran))
2736 #endif
2737
2738 /*
2739 * At this point, the scsi_device structure already exists
2740 * and has been initialized.
2741 *
2742 * Use this function to allocate target-private data structures,
2743 * if needed by this HBA. Add revised flow-control and queue
2744 * properties for child here, if desired and if you can tell they
2745 * support tagged queueing by now.
2746 */
2747 mptsas_t *mpt;
2748 int lun = sd->sd_address.a_lun;
2749 mdi_pathinfo_t *pip = NULL;
2750 mptsas_tgt_private_t *tgt_private = NULL;
2751 mptsas_target_t *ptgt = NULL;
2752 char *psas_wwn = NULL;
2753 int phymask = 0;
2754 uint64_t sas_wwn = 0;
2755 mpt = SDEV2MPT(sd);
2756
2757 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
2758
2759 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
2760 (void *)hba_dip, (void *)tgt_dip, lun));
2761
2762 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
2763 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
2764 ddi_set_name_addr(tgt_dip, NULL);
2765 return (DDI_FAILURE);
2766 }
2767 /*
2768 * phymask is 0 means the virtual port for RAID
2769 */
2770 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
2771 "phymask", 0);
2772 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2773 if ((pip = (void *)(sd->sd_private)) == NULL) {
2774 /*
2775 * Very bad news if this occurs. Somehow scsi_vhci has
2776 * lost the pathinfo node for this target.
2777 */
2778 return (DDI_NOT_WELL_FORMED);
2779 }
2780
2781 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
2782 DDI_PROP_SUCCESS) {
2783 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
2784 return (DDI_FAILURE);
2785 }
2786
2787 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
2788 &psas_wwn) == MDI_SUCCESS) {
2789 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2790 sas_wwn = 0;
2791 }
2792 (void) mdi_prop_free(psas_wwn);
2793 }
2794 } else {
2795 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
2796 DDI_PROP_DONTPASS, LUN_PROP, 0);
2797 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
2798 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
2799 DDI_PROP_SUCCESS) {
2800 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
2801 sas_wwn = 0;
2802 }
2803 ddi_prop_free(psas_wwn);
2804 } else {
2805 sas_wwn = 0;
2806 }
2807 }
2808 ASSERT((sas_wwn != 0) || (phymask != 0));
2809 mutex_enter(&mpt->m_mutex);
2810 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask);
2811 mutex_exit(&mpt->m_mutex);
2812 if (ptgt == NULL) {
2813 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
2814 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
2815 sas_wwn);
2816 return (DDI_FAILURE);
2817 }
2818 if (hba_tran->tran_tgt_private == NULL) {
2819 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
2820 KM_SLEEP);
2821 tgt_private->t_lun = lun;
2822 tgt_private->t_private = ptgt;
2823 hba_tran->tran_tgt_private = tgt_private;
2824 }
2825
2826 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
2827 return (DDI_SUCCESS);
2828 }
2829 mutex_enter(&mpt->m_mutex);
2830
2831 if (ptgt->m_deviceinfo &
2832 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
2833 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
2834 uchar_t *inq89 = NULL;
2835 int inq89_len = 0x238;
2836 int reallen = 0;
2837 int rval = 0;
2838 struct sata_id *sid = NULL;
2839 char model[SATA_ID_MODEL_LEN + 1];
2840 char fw[SATA_ID_FW_LEN + 1];
2841 char *vid, *pid;
2842 int i;
2843
2844 mutex_exit(&mpt->m_mutex);
2845 /*
2846 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
2847 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
2848 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
2849 */
2850 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
2851 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
2852 inq89, inq89_len, &reallen, 1);
2853
2854 if (rval != 0) {
2855 if (inq89 != NULL) {
2856 kmem_free(inq89, inq89_len);
2857 }
2858
2859 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
2860 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
2861 return (DDI_SUCCESS);
2862 }
2863 sid = (void *)(&inq89[60]);
2864
2865 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
2866 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
2867
2868 model[SATA_ID_MODEL_LEN] = 0;
2869 fw[SATA_ID_FW_LEN] = 0;
2870
2871 /*
2872 * split model into into vid/pid
2873 */
2874 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++)
2875 if ((*pid == ' ') || (*pid == '\t'))
2876 break;
2877 if (i < SATA_ID_MODEL_LEN) {
2878 vid = model;
2879 /*
2880 * terminate vid, establish pid
2881 */
2882 *pid++ = 0;
2883 } else {
2884 /*
2885 * vid will stay "ATA ", the rule is same
2886 * as sata framework implementation.
2887 */
2888 vid = NULL;
2889 /*
2890 * model is all pid
2891 */
2892 pid = model;
2893 }
2894
2895 /*
2896 * override SCSA "inquiry-*" properties
2897 */
2898 if (vid)
2899 (void) scsi_device_prop_update_inqstring(sd,
2900 INQUIRY_VENDOR_ID, vid, strlen(vid));
2901 if (pid)
2902 (void) scsi_device_prop_update_inqstring(sd,
2903 INQUIRY_PRODUCT_ID, pid, strlen(pid));
2904 (void) scsi_device_prop_update_inqstring(sd,
2905 INQUIRY_REVISION_ID, fw, strlen(fw));
2906
2907 if (inq89 != NULL) {
2908 kmem_free(inq89, inq89_len);
2909 }
2910 } else {
2911 mutex_exit(&mpt->m_mutex);
2912 }
2913
2914 return (DDI_SUCCESS);
2915 }
2916 /*
2917 * tran_tgt_free(9E) - target device instance deallocation
2918 */
2919 static void
2920 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
2921 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
2922 {
2923 #ifndef __lock_lint
2924 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
2925 #endif
2926
2927 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
2928
2929 if (tgt_private != NULL) {
2930 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
2931 hba_tran->tran_tgt_private = NULL;
2932 }
2933 }
2934
2935 /*
2936 * scsi_pkt handling
2937 *
2938 * Visible to the external world via the transport structure.
2939 */
2940
2941 /*
2942 * Notes:
2943 * - transport the command to the addressed SCSI target/lun device
2944 * - normal operation is to schedule the command to be transported,
2945 * and return TRAN_ACCEPT if this is successful.
2946 * - if NO_INTR, tran_start must poll device for command completion
2947 */
2948 static int
2949 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
2950 {
2951 #ifndef __lock_lint
2952 _NOTE(ARGUNUSED(ap))
2953 #endif
2954 mptsas_t *mpt = PKT2MPT(pkt);
2955 mptsas_cmd_t *cmd = PKT2CMD(pkt);
2956 int rval;
2957 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
2958
2959 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
2960 ASSERT(ptgt);
2961 if (ptgt == NULL)
2962 return (TRAN_FATAL_ERROR);
2963
2964 /*
2965 * prepare the pkt before taking mutex.
2966 */
2967 rval = mptsas_prepare_pkt(cmd);
2968 if (rval != TRAN_ACCEPT) {
2969 return (rval);
2970 }
2971
2972 /*
2973 * Send the command to target/lun, however your HBA requires it.
2974 * If busy, return TRAN_BUSY; if there's some other formatting error
2975 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
2976 * return of TRAN_ACCEPT.
2977 *
2978 * Remember that access to shared resources, including the mptsas_t
2979 * data structure and the HBA hardware registers, must be protected
2980 * with mutexes, here and everywhere.
2981 *
2982 * Also remember that at interrupt time, you'll get an argument
2983 * to the interrupt handler which is a pointer to your mptsas_t
2984 * structure; you'll have to remember which commands are outstanding
2985 * and which scsi_pkt is the currently-running command so the
2986 * interrupt handler can refer to the pkt to set completion
2987 * status, call the target driver back through pkt_comp, etc.
2988 *
2989 * If the instance lock is held by other thread, don't spin to wait
2990 * for it. Instead, queue the cmd and next time when the instance lock
2991 * is not held, accept all the queued cmd. A extra tx_waitq is
2992 * introduced to protect the queue.
2993 *
2994 * The polled cmd will not be queud and accepted as usual.
2995 *
2996 * Under the tx_waitq mutex, record whether a thread is draining
2997 * the tx_waitq. An IO requesting thread that finds the instance
2998 * mutex contended appends to the tx_waitq and while holding the
2999 * tx_wait mutex, if the draining flag is not set, sets it and then
3000 * proceeds to spin for the instance mutex. This scheme ensures that
3001 * the last cmd in a burst be processed.
3002 *
3003 * we enable this feature only when the helper threads are enabled,
3004 * at which we think the loads are heavy.
3005 *
3006 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3007 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3008 */
3009
3010 if (mpt->m_doneq_thread_n) {
3011 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3012 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3013 mutex_exit(&mpt->m_mutex);
3014 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3015 mutex_enter(&mpt->m_mutex);
3016 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3017 mutex_exit(&mpt->m_mutex);
3018 } else {
3019 mutex_enter(&mpt->m_tx_waitq_mutex);
3020 /*
3021 * ptgt->m_dr_flag is protected by m_mutex or
3022 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3023 * is acquired.
3024 */
3025 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3026 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3027 /*
3028 * The command should be allowed to
3029 * retry by returning TRAN_BUSY to
3030 * to stall the I/O's which come from
3031 * scsi_vhci since the device/path is
3032 * in unstable state now.
3033 */
3034 mutex_exit(&mpt->m_tx_waitq_mutex);
3035 return (TRAN_BUSY);
3036 } else {
3037 /*
3038 * The device is offline, just fail the
3039 * command by returning
3040 * TRAN_FATAL_ERROR.
3041 */
3042 mutex_exit(&mpt->m_tx_waitq_mutex);
3043 return (TRAN_FATAL_ERROR);
3044 }
3045 }
3046 if (mpt->m_tx_draining) {
3047 cmd->cmd_flags |= CFLAG_TXQ;
3048 *mpt->m_tx_waitqtail = cmd;
3049 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3050 mutex_exit(&mpt->m_tx_waitq_mutex);
3051 } else { /* drain the queue */
3052 mpt->m_tx_draining = 1;
3053 mutex_exit(&mpt->m_tx_waitq_mutex);
3054 mutex_enter(&mpt->m_mutex);
3055 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3056 mutex_exit(&mpt->m_mutex);
3057 }
3058 }
3059 } else {
3060 mutex_enter(&mpt->m_mutex);
3061 /*
3062 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3063 * in this case, m_mutex is acquired.
3064 */
3065 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3066 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3067 /*
3068 * commands should be allowed to retry by
3069 * returning TRAN_BUSY to stall the I/O's
3070 * which come from scsi_vhci since the device/
3071 * path is in unstable state now.
3072 */
3073 mutex_exit(&mpt->m_mutex);
3074 return (TRAN_BUSY);
3075 } else {
3076 /*
3077 * The device is offline, just fail the
3078 * command by returning TRAN_FATAL_ERROR.
3079 */
3080 mutex_exit(&mpt->m_mutex);
3081 return (TRAN_FATAL_ERROR);
3082 }
3083 }
3084 rval = mptsas_accept_pkt(mpt, cmd);
3085 mutex_exit(&mpt->m_mutex);
3086 }
3087
3088 return (rval);
3089 }
3090
3091 /*
3092 * Accept all the queued cmds(if any) before accept the current one.
3093 */
3094 static int
3095 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3096 {
3097 int rval;
3098 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3099
3100 ASSERT(mutex_owned(&mpt->m_mutex));
3101 /*
3102 * The call to mptsas_accept_tx_waitq() must always be performed
3103 * because that is where mpt->m_tx_draining is cleared.
3104 */
3105 mutex_enter(&mpt->m_tx_waitq_mutex);
3106 mptsas_accept_tx_waitq(mpt);
3107 mutex_exit(&mpt->m_tx_waitq_mutex);
3108 /*
3109 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3110 * in this case, m_mutex is acquired.
3111 */
3112 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3113 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3114 /*
3115 * The command should be allowed to retry by returning
3116 * TRAN_BUSY to stall the I/O's which come from
3117 * scsi_vhci since the device/path is in unstable state
3118 * now.
3119 */
3120 return (TRAN_BUSY);
3121 } else {
3122 /*
3123 * The device is offline, just fail the command by
3124 * return TRAN_FATAL_ERROR.
3125 */
3126 return (TRAN_FATAL_ERROR);
3127 }
3128 }
3129 rval = mptsas_accept_pkt(mpt, cmd);
3130
3131 return (rval);
3132 }
3133
3134 static int
3135 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3136 {
3137 int rval = TRAN_ACCEPT;
3138 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3139
3140 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3141
3142 ASSERT(mutex_owned(&mpt->m_mutex));
3143
3144 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3145 rval = mptsas_prepare_pkt(cmd);
3146 if (rval != TRAN_ACCEPT) {
3147 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3148 return (rval);
3149 }
3150 }
3151
3152 /*
3153 * reset the throttle if we were draining
3154 */
3155 if ((ptgt->m_t_ncmds == 0) &&
3156 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3157 NDBG23(("reset throttle"));
3158 ASSERT(ptgt->m_reset_delay == 0);
3159 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3160 }
3161
3162 /*
3163 * If HBA is being reset, the DevHandles are being re-initialized,
3164 * which means that they could be invalid even if the target is still
3165 * attached. Check if being reset and if DevHandle is being
3166 * re-initialized. If this is the case, return BUSY so the I/O can be
3167 * retried later.
3168 */
3169 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3170 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3171 if (cmd->cmd_flags & CFLAG_TXQ) {
3172 mptsas_doneq_add(mpt, cmd);
3173 mptsas_doneq_empty(mpt);
3174 return (rval);
3175 } else {
3176 return (TRAN_BUSY);
3177 }
3178 }
3179
3180 /*
3181 * If device handle has already been invalidated, just
3182 * fail the command. In theory, command from scsi_vhci
3183 * client is impossible send down command with invalid
3184 * devhdl since devhdl is set after path offline, target
3185 * driver is not suppose to select a offlined path.
3186 */
3187 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3188 NDBG20(("rejecting command, it might because invalid devhdl "
3189 "request."));
3190 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3191 if (cmd->cmd_flags & CFLAG_TXQ) {
3192 mptsas_doneq_add(mpt, cmd);
3193 mptsas_doneq_empty(mpt);
3194 return (rval);
3195 } else {
3196 return (TRAN_FATAL_ERROR);
3197 }
3198 }
3199 /*
3200 * The first case is the normal case. mpt gets a command from the
3201 * target driver and starts it.
3202 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3203 * commands is m_max_requests - 2.
3204 */
3205 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3206 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3207 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3208 (ptgt->m_reset_delay == 0) &&
3209 (ptgt->m_t_nwait == 0) &&
3210 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3211 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3212 (void) mptsas_start_cmd(mpt, cmd);
3213 } else {
3214 mptsas_waitq_add(mpt, cmd);
3215 }
3216 } else {
3217 /*
3218 * Add this pkt to the work queue
3219 */
3220 mptsas_waitq_add(mpt, cmd);
3221
3222 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3223 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3224
3225 /*
3226 * Only flush the doneq if this is not a TM
3227 * cmd. For TM cmds the flushing of the
3228 * doneq will be done in those routines.
3229 */
3230 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3231 mptsas_doneq_empty(mpt);
3232 }
3233 }
3234 }
3235 return (rval);
3236 }
3237
3238 int
3239 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3240 {
3241 mptsas_slots_t *slots;
3242 int slot;
3243 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3244
3245 ASSERT(mutex_owned(&mpt->m_mutex));
3246 slots = mpt->m_active;
3247
3248 /*
3249 * Account for reserved TM request slot and reserved SMID of 0.
3250 */
3251 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2));
3252
3253 /*
3254 * m_tags is equivalent to the SMID when sending requests. Since the
3255 * SMID cannot be 0, start out at one if rolling over past the size
3256 * of the request queue depth. Also, don't use the last SMID, which is
3257 * reserved for TM requests.
3258 */
3259 slot = (slots->m_tags)++;
3260 if (slots->m_tags > slots->m_n_slots) {
3261 slots->m_tags = 1;
3262 }
3263
3264 alloc_tag:
3265 /* Validate tag, should never fail. */
3266 if (slots->m_slot[slot] == NULL) {
3267 /*
3268 * Make sure SMID is not using reserved value of 0
3269 * and the TM request slot.
3270 */
3271 ASSERT((slot > 0) && (slot <= slots->m_n_slots));
3272 cmd->cmd_slot = slot;
3273 slots->m_slot[slot] = cmd;
3274 mpt->m_ncmds++;
3275
3276 /*
3277 * only increment per target ncmds if this is not a
3278 * command that has no target associated with it (i.e. a
3279 * event acknoledgment)
3280 */
3281 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3282 ptgt->m_t_ncmds++;
3283 }
3284 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time;
3285
3286 /*
3287 * If initial timout is less than or equal to one tick, bump
3288 * the timeout by a tick so that command doesn't timeout before
3289 * its allotted time.
3290 */
3291 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) {
3292 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick;
3293 }
3294 return (TRUE);
3295 } else {
3296 int i;
3297
3298 /*
3299 * If slot in use, scan until a free one is found. Don't use 0
3300 * or final slot, which is reserved for TM requests.
3301 */
3302 for (i = 0; i < slots->m_n_slots; i++) {
3303 slot = slots->m_tags;
3304 if (++(slots->m_tags) > slots->m_n_slots) {
3305 slots->m_tags = 1;
3306 }
3307 if (slots->m_slot[slot] == NULL) {
3308 NDBG22(("found free slot %d", slot));
3309 goto alloc_tag;
3310 }
3311 }
3312 }
3313 return (FALSE);
3314 }
3315
3316 /*
3317 * prepare the pkt:
3318 * the pkt may have been resubmitted or just reused so
3319 * initialize some fields and do some checks.
3320 */
3321 static int
3322 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3323 {
3324 struct scsi_pkt *pkt = CMD2PKT(cmd);
3325
3326 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3327
3328 /*
3329 * Reinitialize some fields that need it; the packet may
3330 * have been resubmitted
3331 */
3332 pkt->pkt_reason = CMD_CMPLT;
3333 pkt->pkt_state = 0;
3334 pkt->pkt_statistics = 0;
3335 pkt->pkt_resid = 0;
3336 cmd->cmd_age = 0;
3337 cmd->cmd_pkt_flags = pkt->pkt_flags;
3338
3339 /*
3340 * zero status byte.
3341 */
3342 *(pkt->pkt_scbp) = 0;
3343
3344 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3345 pkt->pkt_resid = cmd->cmd_dmacount;
3346
3347 /*
3348 * consistent packets need to be sync'ed first
3349 * (only for data going out)
3350 */
3351 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3352 (cmd->cmd_flags & CFLAG_DMASEND)) {
3353 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3354 DDI_DMA_SYNC_FORDEV);
3355 }
3356 }
3357
3358 cmd->cmd_flags =
3359 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3360 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3361
3362 return (TRAN_ACCEPT);
3363 }
3364
3365 /*
3366 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3367 *
3368 * One of three possibilities:
3369 * - allocate scsi_pkt
3370 * - allocate scsi_pkt and DMA resources
3371 * - allocate DMA resources to an already-allocated pkt
3372 */
3373 static struct scsi_pkt *
3374 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3375 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3376 int (*callback)(), caddr_t arg)
3377 {
3378 mptsas_cmd_t *cmd, *new_cmd;
3379 mptsas_t *mpt = ADDR2MPT(ap);
3380 int failure = 1;
3381 uint_t oldcookiec;
3382 mptsas_target_t *ptgt = NULL;
3383 int rval;
3384 mptsas_tgt_private_t *tgt_private;
3385 int kf;
3386
3387 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3388
3389 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3390 tran_tgt_private;
3391 ASSERT(tgt_private != NULL);
3392 if (tgt_private == NULL) {
3393 return (NULL);
3394 }
3395 ptgt = tgt_private->t_private;
3396 ASSERT(ptgt != NULL);
3397 if (ptgt == NULL)
3398 return (NULL);
3399 ap->a_target = ptgt->m_devhdl;
3400 ap->a_lun = tgt_private->t_lun;
3401
3402 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3403 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3404 statuslen *= 100; tgtlen *= 4;
3405 #endif
3406 NDBG3(("mptsas_scsi_init_pkt:\n"
3407 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3408 ap->a_target, (void *)pkt, (void *)bp,
3409 cmdlen, statuslen, tgtlen, flags));
3410
3411 /*
3412 * Allocate the new packet.
3413 */
3414 if (pkt == NULL) {
3415 ddi_dma_handle_t save_dma_handle;
3416 ddi_dma_handle_t save_arq_dma_handle;
3417 struct buf *save_arq_bp;
3418 ddi_dma_cookie_t save_arqcookie;
3419
3420 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3421
3422 if (cmd) {
3423 save_dma_handle = cmd->cmd_dmahandle;
3424 save_arq_dma_handle = cmd->cmd_arqhandle;
3425 save_arq_bp = cmd->cmd_arq_buf;
3426 save_arqcookie = cmd->cmd_arqcookie;
3427 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3428 cmd->cmd_dmahandle = save_dma_handle;
3429 cmd->cmd_arqhandle = save_arq_dma_handle;
3430 cmd->cmd_arq_buf = save_arq_bp;
3431 cmd->cmd_arqcookie = save_arqcookie;
3432
3433 pkt = (void *)((uchar_t *)cmd +
3434 sizeof (struct mptsas_cmd));
3435 pkt->pkt_ha_private = (opaque_t)cmd;
3436 pkt->pkt_address = *ap;
3437 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3438 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3439 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3440 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3441 cmd->cmd_cdblen = (uchar_t)cmdlen;
3442 cmd->cmd_scblen = statuslen;
3443 cmd->cmd_rqslen = SENSE_LENGTH;
3444 cmd->cmd_tgt_addr = ptgt;
3445 failure = 0;
3446 }
3447
3448 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) ||
3449 (tgtlen > PKT_PRIV_LEN) ||
3450 (statuslen > EXTCMDS_STATUS_SIZE)) {
3451 if (failure == 0) {
3452 /*
3453 * if extern alloc fails, all will be
3454 * deallocated, including cmd
3455 */
3456 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3457 cmdlen, tgtlen, statuslen, kf);
3458 }
3459 if (failure) {
3460 /*
3461 * if extern allocation fails, it will
3462 * deallocate the new pkt as well
3463 */
3464 return (NULL);
3465 }
3466 }
3467 new_cmd = cmd;
3468
3469 } else {
3470 cmd = PKT2CMD(pkt);
3471 new_cmd = NULL;
3472 }
3473
3474
3475 /* grab cmd->cmd_cookiec here as oldcookiec */
3476
3477 oldcookiec = cmd->cmd_cookiec;
3478
3479 /*
3480 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3481 * greater than 0 and we'll need to grab the next dma window
3482 */
3483 /*
3484 * SLM-not doing extra command frame right now; may add later
3485 */
3486
3487 if (cmd->cmd_nwin > 0) {
3488
3489 /*
3490 * Make sure we havn't gone past the the total number
3491 * of windows
3492 */
3493 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3494 return (NULL);
3495 }
3496 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3497 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3498 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3499 return (NULL);
3500 }
3501 goto get_dma_cookies;
3502 }
3503
3504
3505 if (flags & PKT_XARQ) {
3506 cmd->cmd_flags |= CFLAG_XARQ;
3507 }
3508
3509 /*
3510 * DMA resource allocation. This version assumes your
3511 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3512 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3513 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3514 */
3515 if (bp && (bp->b_bcount != 0) &&
3516 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3517
3518 int cnt, dma_flags;
3519 mptti_t *dmap; /* ptr to the S/G list */
3520
3521 /*
3522 * Set up DMA memory and position to the next DMA segment.
3523 */
3524 ASSERT(cmd->cmd_dmahandle != NULL);
3525
3526 if (bp->b_flags & B_READ) {
3527 dma_flags = DDI_DMA_READ;
3528 cmd->cmd_flags &= ~CFLAG_DMASEND;
3529 } else {
3530 dma_flags = DDI_DMA_WRITE;
3531 cmd->cmd_flags |= CFLAG_DMASEND;
3532 }
3533 if (flags & PKT_CONSISTENT) {
3534 cmd->cmd_flags |= CFLAG_CMDIOPB;
3535 dma_flags |= DDI_DMA_CONSISTENT;
3536 }
3537
3538 if (flags & PKT_DMA_PARTIAL) {
3539 dma_flags |= DDI_DMA_PARTIAL;
3540 }
3541
3542 /*
3543 * workaround for byte hole issue on psycho and
3544 * schizo pre 2.1
3545 */
3546 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3547 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3548 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3549 dma_flags |= DDI_DMA_CONSISTENT;
3550 }
3551
3552 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3553 dma_flags, callback, arg,
3554 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3555 if (rval == DDI_DMA_PARTIAL_MAP) {
3556 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3557 &cmd->cmd_nwin);
3558 cmd->cmd_winindex = 0;
3559 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3560 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3561 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3562 &cmd->cmd_cookiec);
3563 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3564 switch (rval) {
3565 case DDI_DMA_NORESOURCES:
3566 bioerror(bp, 0);
3567 break;
3568 case DDI_DMA_BADATTR:
3569 case DDI_DMA_NOMAPPING:
3570 bioerror(bp, EFAULT);
3571 break;
3572 case DDI_DMA_TOOBIG:
3573 default:
3574 bioerror(bp, EINVAL);
3575 break;
3576 }
3577 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3578 if (new_cmd) {
3579 mptsas_scsi_destroy_pkt(ap, pkt);
3580 }
3581 return ((struct scsi_pkt *)NULL);
3582 }
3583
3584 get_dma_cookies:
3585 cmd->cmd_flags |= CFLAG_DMAVALID;
3586 ASSERT(cmd->cmd_cookiec > 0);
3587
3588 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3589 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3590 cmd->cmd_cookiec);
3591 bioerror(bp, EINVAL);
3592 if (new_cmd) {
3593 mptsas_scsi_destroy_pkt(ap, pkt);
3594 }
3595 return ((struct scsi_pkt *)NULL);
3596 }
3597
3598 /*
3599 * Allocate extra SGL buffer if needed.
3600 */
3601 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3602 (cmd->cmd_extra_frames == NULL)) {
3603 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3604 DDI_FAILURE) {
3605 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3606 "failed");
3607 bioerror(bp, ENOMEM);
3608 if (new_cmd) {
3609 mptsas_scsi_destroy_pkt(ap, pkt);
3610 }
3611 return ((struct scsi_pkt *)NULL);
3612 }
3613 }
3614
3615 /*
3616 * Always use scatter-gather transfer
3617 * Use the loop below to store physical addresses of
3618 * DMA segments, from the DMA cookies, into your HBA's
3619 * scatter-gather list.
3620 * We need to ensure we have enough kmem alloc'd
3621 * for the sg entries since we are no longer using an
3622 * array inside mptsas_cmd_t.
3623 *
3624 * We check cmd->cmd_cookiec against oldcookiec so
3625 * the scatter-gather list is correctly allocated
3626 */
3627
3628 if (oldcookiec != cmd->cmd_cookiec) {
3629 if (cmd->cmd_sg != (mptti_t *)NULL) {
3630 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3631 oldcookiec);
3632 cmd->cmd_sg = NULL;
3633 }
3634 }
3635
3636 if (cmd->cmd_sg == (mptti_t *)NULL) {
3637 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3638 cmd->cmd_cookiec), kf);
3639
3640 if (cmd->cmd_sg == (mptti_t *)NULL) {
3641 mptsas_log(mpt, CE_WARN,
3642 "unable to kmem_alloc enough memory "
3643 "for scatter/gather list");
3644 /*
3645 * if we have an ENOMEM condition we need to behave
3646 * the same way as the rest of this routine
3647 */
3648
3649 bioerror(bp, ENOMEM);
3650 if (new_cmd) {
3651 mptsas_scsi_destroy_pkt(ap, pkt);
3652 }
3653 return ((struct scsi_pkt *)NULL);
3654 }
3655 }
3656
3657 dmap = cmd->cmd_sg;
3658
3659 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3660
3661 /*
3662 * store the first segment into the S/G list
3663 */
3664 dmap->count = cmd->cmd_cookie.dmac_size;
3665 dmap->addr.address64.Low = (uint32_t)
3666 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3667 dmap->addr.address64.High = (uint32_t)
3668 (cmd->cmd_cookie.dmac_laddress >> 32);
3669
3670 /*
3671 * dmacount counts the size of the dma for this window
3672 * (if partial dma is being used). totaldmacount
3673 * keeps track of the total amount of dma we have
3674 * transferred for all the windows (needed to calculate
3675 * the resid value below).
3676 */
3677 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3678 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3679
3680 /*
3681 * We already stored the first DMA scatter gather segment,
3682 * start at 1 if we need to store more.
3683 */
3684 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3685 /*
3686 * Get next DMA cookie
3687 */
3688 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3689 &cmd->cmd_cookie);
3690 dmap++;
3691
3692 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3693 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3694
3695 /*
3696 * store the segment parms into the S/G list
3697 */
3698 dmap->count = cmd->cmd_cookie.dmac_size;
3699 dmap->addr.address64.Low = (uint32_t)
3700 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3701 dmap->addr.address64.High = (uint32_t)
3702 (cmd->cmd_cookie.dmac_laddress >> 32);
3703 }
3704
3705 /*
3706 * If this was partially allocated we set the resid
3707 * the amount of data NOT transferred in this window
3708 * If there is only one window, the resid will be 0
3709 */
3710 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3711 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount));
3712 }
3713 return (pkt);
3714 }
3715
3716 /*
3717 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3718 *
3719 * Notes:
3720 * - also frees DMA resources if allocated
3721 * - implicit DMA synchonization
3722 */
3723 static void
3724 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3725 {
3726 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3727 mptsas_t *mpt = ADDR2MPT(ap);
3728
3729 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
3730 ap->a_target, (void *)pkt));
3731
3732 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3733 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
3734 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3735 }
3736
3737 if (cmd->cmd_sg) {
3738 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
3739 cmd->cmd_sg = NULL;
3740 }
3741
3742 mptsas_free_extra_sgl_frame(mpt, cmd);
3743
3744 if ((cmd->cmd_flags &
3745 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
3746 CFLAG_SCBEXTERN)) == 0) {
3747 cmd->cmd_flags = CFLAG_FREE;
3748 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
3749 } else {
3750 mptsas_pkt_destroy_extern(mpt, cmd);
3751 }
3752 }
3753
3754 /*
3755 * kmem cache constructor and destructor:
3756 * When constructing, we bzero the cmd and allocate the dma handle
3757 * When destructing, just free the dma handle
3758 */
3759 static int
3760 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
3761 {
3762 mptsas_cmd_t *cmd = buf;
3763 mptsas_t *mpt = cdrarg;
3764 struct scsi_address ap;
3765 uint_t cookiec;
3766 ddi_dma_attr_t arq_dma_attr;
3767 int (*callback)(caddr_t);
3768
3769 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3770
3771 NDBG4(("mptsas_kmem_cache_constructor"));
3772
3773 ap.a_hba_tran = mpt->m_tran;
3774 ap.a_target = 0;
3775 ap.a_lun = 0;
3776
3777 /*
3778 * allocate a dma handle
3779 */
3780 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
3781 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
3782 cmd->cmd_dmahandle = NULL;
3783 return (-1);
3784 }
3785
3786 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL,
3787 SENSE_LENGTH, B_READ, callback, NULL);
3788 if (cmd->cmd_arq_buf == NULL) {
3789 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3790 cmd->cmd_dmahandle = NULL;
3791 return (-1);
3792 }
3793
3794 /*
3795 * allocate a arq handle
3796 */
3797 arq_dma_attr = mpt->m_msg_dma_attr;
3798 arq_dma_attr.dma_attr_sgllen = 1;
3799 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback,
3800 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) {
3801 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3802 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3803 cmd->cmd_dmahandle = NULL;
3804 cmd->cmd_arqhandle = NULL;
3805 return (-1);
3806 }
3807
3808 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle,
3809 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
3810 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) {
3811 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3812 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3813 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3814 cmd->cmd_dmahandle = NULL;
3815 cmd->cmd_arqhandle = NULL;
3816 cmd->cmd_arq_buf = NULL;
3817 return (-1);
3818 }
3819
3820 return (0);
3821 }
3822
3823 static void
3824 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
3825 {
3826 #ifndef __lock_lint
3827 _NOTE(ARGUNUSED(cdrarg))
3828 #endif
3829 mptsas_cmd_t *cmd = buf;
3830
3831 NDBG4(("mptsas_kmem_cache_destructor"));
3832
3833 if (cmd->cmd_arqhandle) {
3834 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle);
3835 ddi_dma_free_handle(&cmd->cmd_arqhandle);
3836 cmd->cmd_arqhandle = NULL;
3837 }
3838 if (cmd->cmd_arq_buf) {
3839 scsi_free_consistent_buf(cmd->cmd_arq_buf);
3840 cmd->cmd_arq_buf = NULL;
3841 }
3842 if (cmd->cmd_dmahandle) {
3843 ddi_dma_free_handle(&cmd->cmd_dmahandle);
3844 cmd->cmd_dmahandle = NULL;
3845 }
3846 }
3847
3848 static int
3849 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
3850 {
3851 mptsas_cache_frames_t *p = buf;
3852 mptsas_t *mpt = cdrarg;
3853 ddi_dma_attr_t frame_dma_attr;
3854 size_t mem_size, alloc_len;
3855 ddi_dma_cookie_t cookie;
3856 uint_t ncookie;
3857 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
3858 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
3859
3860 frame_dma_attr = mpt->m_msg_dma_attr;
3861 frame_dma_attr.dma_attr_align = 0x10;
3862 frame_dma_attr.dma_attr_sgllen = 1;
3863
3864 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
3865 &p->m_dma_hdl) != DDI_SUCCESS) {
3866 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
3867 " extra SGL.");
3868 return (DDI_FAILURE);
3869 }
3870
3871 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
3872
3873 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
3874 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
3875 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
3876 ddi_dma_free_handle(&p->m_dma_hdl);
3877 p->m_dma_hdl = NULL;
3878 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
3879 " extra SGL.");
3880 return (DDI_FAILURE);
3881 }
3882
3883 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
3884 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
3885 &cookie, &ncookie) != DDI_DMA_MAPPED) {
3886 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3887 ddi_dma_free_handle(&p->m_dma_hdl);
3888 p->m_dma_hdl = NULL;
3889 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
3890 " extra SGL");
3891 return (DDI_FAILURE);
3892 }
3893
3894 /*
3895 * Store the SGL memory address. This chip uses this
3896 * address to dma to and from the driver. The second
3897 * address is the address mpt uses to fill in the SGL.
3898 */
3899 p->m_phys_addr = cookie.dmac_address;
3900
3901 return (DDI_SUCCESS);
3902 }
3903
3904 static void
3905 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
3906 {
3907 #ifndef __lock_lint
3908 _NOTE(ARGUNUSED(cdrarg))
3909 #endif
3910 mptsas_cache_frames_t *p = buf;
3911 if (p->m_dma_hdl != NULL) {
3912 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
3913 (void) ddi_dma_mem_free(&p->m_acc_hdl);
3914 ddi_dma_free_handle(&p->m_dma_hdl);
3915 p->m_phys_addr = NULL;
3916 p->m_frames_addr = NULL;
3917 p->m_dma_hdl = NULL;
3918 p->m_acc_hdl = NULL;
3919 }
3920
3921 }
3922
3923 /*
3924 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
3925 * for non-standard length cdb, pkt_private, status areas
3926 * if allocation fails, then deallocate all external space and the pkt
3927 */
3928 /* ARGSUSED */
3929 static int
3930 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
3931 int cmdlen, int tgtlen, int statuslen, int kf)
3932 {
3933 caddr_t cdbp, scbp, tgt;
3934 int (*callback)(caddr_t) = (kf == KM_SLEEP) ?
3935 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT;
3936 struct scsi_address ap;
3937 size_t senselength;
3938 ddi_dma_attr_t ext_arq_dma_attr;
3939 uint_t cookiec;
3940
3941 NDBG3(("mptsas_pkt_alloc_extern: "
3942 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
3943 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
3944
3945 tgt = cdbp = scbp = NULL;
3946 cmd->cmd_scblen = statuslen;
3947 cmd->cmd_privlen = (uchar_t)tgtlen;
3948
3949 if (cmdlen > sizeof (cmd->cmd_cdb)) {
3950 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
3951 goto fail;
3952 }
3953 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
3954 cmd->cmd_flags |= CFLAG_CDBEXTERN;
3955 }
3956 if (tgtlen > PKT_PRIV_LEN) {
3957 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
3958 goto fail;
3959 }
3960 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
3961 cmd->cmd_pkt->pkt_private = tgt;
3962 }
3963 if (statuslen > EXTCMDS_STATUS_SIZE) {
3964 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
3965 goto fail;
3966 }
3967 cmd->cmd_flags |= CFLAG_SCBEXTERN;
3968 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
3969
3970 /* allocate sense data buf for DMA */
3971
3972 senselength = statuslen - MPTSAS_GET_ITEM_OFF(
3973 struct scsi_arq_status, sts_sensedata);
3974 cmd->cmd_rqslen = (uchar_t)senselength;
3975
3976 ap.a_hba_tran = mpt->m_tran;
3977 ap.a_target = 0;
3978 ap.a_lun = 0;
3979
3980 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap,
3981 (struct buf *)NULL, senselength, B_READ,
3982 callback, NULL);
3983
3984 if (cmd->cmd_ext_arq_buf == NULL) {
3985 goto fail;
3986 }
3987 /*
3988 * allocate a extern arq handle and bind the buf
3989 */
3990 ext_arq_dma_attr = mpt->m_msg_dma_attr;
3991 ext_arq_dma_attr.dma_attr_sgllen = 1;
3992 if ((ddi_dma_alloc_handle(mpt->m_dip,
3993 &ext_arq_dma_attr, callback,
3994 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) {
3995 goto fail;
3996 }
3997
3998 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle,
3999 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT),
4000 callback, NULL, &cmd->cmd_ext_arqcookie,
4001 &cookiec)
4002 != DDI_SUCCESS) {
4003 goto fail;
4004 }
4005 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID;
4006 }
4007 return (0);
4008 fail:
4009 mptsas_pkt_destroy_extern(mpt, cmd);
4010 return (1);
4011 }
4012
4013 /*
4014 * deallocate external pkt space and deallocate the pkt
4015 */
4016 static void
4017 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4018 {
4019 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4020
4021 if (cmd->cmd_flags & CFLAG_FREE) {
4022 mptsas_log(mpt, CE_PANIC,
4023 "mptsas_pkt_destroy_extern: freeing free packet");
4024 _NOTE(NOT_REACHED)
4025 /* NOTREACHED */
4026 }
4027 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4028 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4029 }
4030 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4031 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4032 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4033 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4034 }
4035 if (cmd->cmd_ext_arqhandle) {
4036 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle);
4037 cmd->cmd_ext_arqhandle = NULL;
4038 }
4039 if (cmd->cmd_ext_arq_buf)
4040 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf);
4041 }
4042 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4043 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4044 }
4045 cmd->cmd_flags = CFLAG_FREE;
4046 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4047 }
4048
4049 /*
4050 * tran_sync_pkt(9E) - explicit DMA synchronization
4051 */
4052 /*ARGSUSED*/
4053 static void
4054 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4055 {
4056 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4057
4058 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4059 ap->a_target, (void *)pkt));
4060
4061 if (cmd->cmd_dmahandle) {
4062 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4063 (cmd->cmd_flags & CFLAG_DMASEND) ?
4064 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4065 }
4066 }
4067
4068 /*
4069 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4070 */
4071 /*ARGSUSED*/
4072 static void
4073 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4074 {
4075 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4076 mptsas_t *mpt = ADDR2MPT(ap);
4077
4078 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4079 ap->a_target, (void *)pkt));
4080
4081 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4082 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4083 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4084 }
4085
4086 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) {
4087 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle);
4088 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID;
4089 }
4090
4091 mptsas_free_extra_sgl_frame(mpt, cmd);
4092 }
4093
4094 static void
4095 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4096 {
4097 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4098 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4099 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4100 DDI_DMA_SYNC_FORCPU);
4101 }
4102 (*pkt->pkt_comp)(pkt);
4103 }
4104
4105 static void
4106 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4107 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4108 {
4109 uint_t cookiec;
4110 mptti_t *dmap;
4111 uint32_t flags;
4112 pMpi2SGESimple64_t sge;
4113 pMpi2SGEChain64_t sgechain;
4114 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4115
4116 /*
4117 * Save the number of entries in the DMA
4118 * Scatter/Gather list
4119 */
4120 cookiec = cmd->cmd_cookiec;
4121
4122 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec));
4123
4124 /*
4125 * Set read/write bit in control.
4126 */
4127 if (cmd->cmd_flags & CFLAG_DMASEND) {
4128 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4129 } else {
4130 *control |= MPI2_SCSIIO_CONTROL_READ;
4131 }
4132
4133 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
4134
4135 /*
4136 * We have 2 cases here. First where we can fit all the
4137 * SG elements into the main frame, and the case
4138 * where we can't.
4139 * If we have more cookies than we can attach to a frame
4140 * we will need to use a chain element to point
4141 * a location of memory where the rest of the S/G
4142 * elements reside.
4143 */
4144 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
4145 dmap = cmd->cmd_sg;
4146 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4147 while (cookiec--) {
4148 ddi_put32(acc_hdl,
4149 &sge->Address.Low, dmap->addr.address64.Low);
4150 ddi_put32(acc_hdl,
4151 &sge->Address.High, dmap->addr.address64.High);
4152 ddi_put32(acc_hdl, &sge->FlagsLength,
4153 dmap->count);
4154 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4155 flags |= ((uint32_t)
4156 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4157 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4158 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4159 MPI2_SGE_FLAGS_SHIFT);
4160
4161 /*
4162 * If this is the last cookie, we set the flags
4163 * to indicate so
4164 */
4165 if (cookiec == 0) {
4166 flags |=
4167 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
4168 | MPI2_SGE_FLAGS_END_OF_BUFFER
4169 | MPI2_SGE_FLAGS_END_OF_LIST) <<
4170 MPI2_SGE_FLAGS_SHIFT);
4171 }
4172 if (cmd->cmd_flags & CFLAG_DMASEND) {
4173 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4174 MPI2_SGE_FLAGS_SHIFT);
4175 } else {
4176 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4177 MPI2_SGE_FLAGS_SHIFT);
4178 }
4179 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4180 dmap++;
4181 sge++;
4182 }
4183 } else {
4184 /*
4185 * Hereby we start to deal with multiple frames.
4186 * The process is as follows:
4187 * 1. Determine how many frames are needed for SGL element
4188 * storage; Note that all frames are stored in contiguous
4189 * memory space and in 64-bit DMA mode each element is
4190 * 3 double-words (12 bytes) long.
4191 * 2. Fill up the main frame. We need to do this separately
4192 * since it contains the SCSI IO request header and needs
4193 * dedicated processing. Note that the last 4 double-words
4194 * of the SCSI IO header is for SGL element storage
4195 * (MPI2_SGE_IO_UNION).
4196 * 3. Fill the chain element in the main frame, so the DMA
4197 * engine can use the following frames.
4198 * 4. Enter a loop to fill the remaining frames. Note that the
4199 * last frame contains no chain element. The remaining
4200 * frames go into the mpt SGL buffer allocated on the fly,
4201 * not immediately following the main message frame, as in
4202 * Gen1.
4203 * Some restrictions:
4204 * 1. For 64-bit DMA, the simple element and chain element
4205 * are both of 3 double-words (12 bytes) in size, even
4206 * though all frames are stored in the first 4G of mem
4207 * range and the higher 32-bits of the address are always 0.
4208 * 2. On some controllers (like the 1064/1068), a frame can
4209 * hold SGL elements with the last 1 or 2 double-words
4210 * (4 or 8 bytes) un-used. On these controllers, we should
4211 * recognize that there's not enough room for another SGL
4212 * element and move the sge pointer to the next frame.
4213 */
4214 int i, j, k, l, frames, sgemax;
4215 int temp;
4216 uint8_t chainflags;
4217 uint16_t chainlength;
4218 mptsas_cache_frames_t *p;
4219
4220 /*
4221 * Sgemax is the number of SGE's that will fit
4222 * each extra frame and frames is total
4223 * number of frames we'll need. 1 sge entry per
4224 * frame is reseverd for the chain element thus the -1 below.
4225 */
4226 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4227 - 1);
4228 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4229
4230 /*
4231 * A little check to see if we need to round up the number
4232 * of frames we need
4233 */
4234 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4235 sgemax) > 1) {
4236 frames = (temp + 1);
4237 } else {
4238 frames = temp;
4239 }
4240 dmap = cmd->cmd_sg;
4241 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4242
4243 /*
4244 * First fill in the main frame
4245 */
4246 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) {
4247 ddi_put32(acc_hdl, &sge->Address.Low,
4248 dmap->addr.address64.Low);
4249 ddi_put32(acc_hdl, &sge->Address.High,
4250 dmap->addr.address64.High);
4251 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count);
4252 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4253 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4254 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4255 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4256 MPI2_SGE_FLAGS_SHIFT);
4257
4258 /*
4259 * If this is the last SGE of this frame
4260 * we set the end of list flag
4261 */
4262 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) {
4263 flags |= ((uint32_t)
4264 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4265 MPI2_SGE_FLAGS_SHIFT);
4266 }
4267 if (cmd->cmd_flags & CFLAG_DMASEND) {
4268 flags |=
4269 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4270 MPI2_SGE_FLAGS_SHIFT);
4271 } else {
4272 flags |=
4273 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4274 MPI2_SGE_FLAGS_SHIFT);
4275 }
4276 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4277 dmap++;
4278 sge++;
4279 }
4280
4281 /*
4282 * Fill in the chain element in the main frame.
4283 * About calculation on ChainOffset:
4284 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4285 * in the end reserved for SGL element storage
4286 * (MPI2_SGE_IO_UNION); we should count it in our
4287 * calculation. See its definition in the header file.
4288 * 2. Constant j is the counter of the current SGL element
4289 * that will be processed, and (j - 1) is the number of
4290 * SGL elements that have been processed (stored in the
4291 * main frame).
4292 * 3. ChainOffset value should be in units of double-words (4
4293 * bytes) so the last value should be divided by 4.
4294 */
4295 ddi_put8(acc_hdl, &frame->ChainOffset,
4296 (sizeof (MPI2_SCSI_IO_REQUEST) -
4297 sizeof (MPI2_SGE_IO_UNION) +
4298 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4299 sgechain = (pMpi2SGEChain64_t)sge;
4300 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4301 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4302 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4303 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4304
4305 /*
4306 * The size of the next frame is the accurate size of space
4307 * (in bytes) used to store the SGL elements. j is the counter
4308 * of SGL elements. (j - 1) is the number of SGL elements that
4309 * have been processed (stored in frames).
4310 */
4311 if (frames >= 2) {
4312 chainlength = mpt->m_req_frame_size /
4313 sizeof (MPI2_SGE_SIMPLE64) *
4314 sizeof (MPI2_SGE_SIMPLE64);
4315 } else {
4316 chainlength = ((cookiec - (j - 1)) *
4317 sizeof (MPI2_SGE_SIMPLE64));
4318 }
4319
4320 p = cmd->cmd_extra_frames;
4321
4322 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4323 ddi_put32(acc_hdl, &sgechain->Address.Low,
4324 p->m_phys_addr);
4325 /* SGL is allocated in the first 4G mem range */
4326 ddi_put32(acc_hdl, &sgechain->Address.High, 0);
4327
4328 /*
4329 * If there are more than 2 frames left we have to
4330 * fill in the next chain offset to the location of
4331 * the chain element in the next frame.
4332 * sgemax is the number of simple elements in an extra
4333 * frame. Note that the value NextChainOffset should be
4334 * in double-words (4 bytes).
4335 */
4336 if (frames >= 2) {
4337 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4338 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4339 } else {
4340 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4341 }
4342
4343 /*
4344 * Jump to next frame;
4345 * Starting here, chain buffers go into the per command SGL.
4346 * This buffer is allocated when chain buffers are needed.
4347 */
4348 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4349 i = cookiec;
4350
4351 /*
4352 * Start filling in frames with SGE's. If we
4353 * reach the end of frame and still have SGE's
4354 * to fill we need to add a chain element and
4355 * use another frame. j will be our counter
4356 * for what cookie we are at and i will be
4357 * the total cookiec. k is the current frame
4358 */
4359 for (k = 1; k <= frames; k++) {
4360 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4361
4362 /*
4363 * If we have reached the end of frame
4364 * and we have more SGE's to fill in
4365 * we have to fill the final entry
4366 * with a chain element and then
4367 * continue to the next frame
4368 */
4369 if ((l == (sgemax + 1)) && (k != frames)) {
4370 sgechain = (pMpi2SGEChain64_t)sge;
4371 j--;
4372 chainflags = (
4373 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4374 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4375 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4376 ddi_put8(p->m_acc_hdl,
4377 &sgechain->Flags, chainflags);
4378 /*
4379 * k is the frame counter and (k + 1)
4380 * is the number of the next frame.
4381 * Note that frames are in contiguous
4382 * memory space.
4383 */
4384 ddi_put32(p->m_acc_hdl,
4385 &sgechain->Address.Low,
4386 (p->m_phys_addr +
4387 (mpt->m_req_frame_size * k)));
4388 ddi_put32(p->m_acc_hdl,
4389 &sgechain->Address.High, 0);
4390
4391 /*
4392 * If there are more than 2 frames left
4393 * we have to next chain offset to
4394 * the location of the chain element
4395 * in the next frame and fill in the
4396 * length of the next chain
4397 */
4398 if ((frames - k) >= 2) {
4399 ddi_put8(p->m_acc_hdl,
4400 &sgechain->NextChainOffset,
4401 (sgemax *
4402 sizeof (MPI2_SGE_SIMPLE64))
4403 >> 2);
4404 ddi_put16(p->m_acc_hdl,
4405 &sgechain->Length,
4406 mpt->m_req_frame_size /
4407 sizeof (MPI2_SGE_SIMPLE64) *
4408 sizeof (MPI2_SGE_SIMPLE64));
4409 } else {
4410 /*
4411 * This is the last frame. Set
4412 * the NextChainOffset to 0 and
4413 * Length is the total size of
4414 * all remaining simple elements
4415 */
4416 ddi_put8(p->m_acc_hdl,
4417 &sgechain->NextChainOffset,
4418 0);
4419 ddi_put16(p->m_acc_hdl,
4420 &sgechain->Length,
4421 (cookiec - j) *
4422 sizeof (MPI2_SGE_SIMPLE64));
4423 }
4424
4425 /* Jump to the next frame */
4426 sge = (pMpi2SGESimple64_t)
4427 ((char *)p->m_frames_addr +
4428 (int)mpt->m_req_frame_size * k);
4429
4430 continue;
4431 }
4432
4433 ddi_put32(p->m_acc_hdl,
4434 &sge->Address.Low,
4435 dmap->addr.address64.Low);
4436 ddi_put32(p->m_acc_hdl,
4437 &sge->Address.High,
4438 dmap->addr.address64.High);
4439 ddi_put32(p->m_acc_hdl,
4440 &sge->FlagsLength, dmap->count);
4441 flags = ddi_get32(p->m_acc_hdl,
4442 &sge->FlagsLength);
4443 flags |= ((uint32_t)(
4444 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4445 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4446 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4447 MPI2_SGE_FLAGS_SHIFT);
4448
4449 /*
4450 * If we are at the end of the frame and
4451 * there is another frame to fill in
4452 * we set the last simple element as last
4453 * element
4454 */
4455 if ((l == sgemax) && (k != frames)) {
4456 flags |= ((uint32_t)
4457 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4458 MPI2_SGE_FLAGS_SHIFT);
4459 }
4460
4461 /*
4462 * If this is the final cookie we
4463 * indicate it by setting the flags
4464 */
4465 if (j == i) {
4466 flags |= ((uint32_t)
4467 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4468 MPI2_SGE_FLAGS_END_OF_BUFFER |
4469 MPI2_SGE_FLAGS_END_OF_LIST) <<
4470 MPI2_SGE_FLAGS_SHIFT);
4471 }
4472 if (cmd->cmd_flags & CFLAG_DMASEND) {
4473 flags |=
4474 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4475 MPI2_SGE_FLAGS_SHIFT);
4476 } else {
4477 flags |=
4478 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4479 MPI2_SGE_FLAGS_SHIFT);
4480 }
4481 ddi_put32(p->m_acc_hdl,
4482 &sge->FlagsLength, flags);
4483 dmap++;
4484 sge++;
4485 }
4486 }
4487
4488 /*
4489 * Sync DMA with the chain buffers that were just created
4490 */
4491 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4492 }
4493 }
4494
4495 /*
4496 * Interrupt handling
4497 * Utility routine. Poll for status of a command sent to HBA
4498 * without interrupts (a FLAG_NOINTR command).
4499 */
4500 int
4501 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
4502 {
4503 int rval = TRUE;
4504
4505 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
4506
4507 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
4508 mptsas_restart_hba(mpt);
4509 }
4510
4511 /*
4512 * Wait, using drv_usecwait(), long enough for the command to
4513 * reasonably return from the target if the target isn't
4514 * "dead". A polled command may well be sent from scsi_poll, and
4515 * there are retries built in to scsi_poll if the transport
4516 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
4517 * and retries the transport up to scsi_poll_busycnt times
4518 * (currently 60) if
4519 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
4520 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
4521 *
4522 * limit the waiting to avoid a hang in the event that the
4523 * cmd never gets started but we are still receiving interrupts
4524 */
4525 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
4526 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
4527 NDBG5(("mptsas_poll: command incomplete"));
4528 rval = FALSE;
4529 break;
4530 }
4531 }
4532
4533 if (rval == FALSE) {
4534
4535 /*
4536 * this isn't supposed to happen, the hba must be wedged
4537 * Mark this cmd as a timeout.
4538 */
4539 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
4540 (STAT_TIMEOUT|STAT_ABORTED));
4541
4542 if (poll_cmd->cmd_queued == FALSE) {
4543
4544 NDBG5(("mptsas_poll: not on waitq"));
4545
4546 poll_cmd->cmd_pkt->pkt_state |=
4547 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
4548 } else {
4549
4550 /* find and remove it from the waitq */
4551 NDBG5(("mptsas_poll: delete from waitq"));
4552 mptsas_waitq_delete(mpt, poll_cmd);
4553 }
4554
4555 }
4556 mptsas_fma_check(mpt, poll_cmd);
4557 NDBG5(("mptsas_poll: done"));
4558 return (rval);
4559 }
4560
4561 /*
4562 * Used for polling cmds and TM function
4563 */
4564 static int
4565 mptsas_wait_intr(mptsas_t *mpt, int polltime)
4566 {
4567 int cnt;
4568 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
4569 uint32_t int_mask;
4570
4571 NDBG5(("mptsas_wait_intr"));
4572
4573 mpt->m_polled_intr = 1;
4574
4575 /*
4576 * Get the current interrupt mask and disable interrupts. When
4577 * re-enabling ints, set mask to saved value.
4578 */
4579 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
4580 MPTSAS_DISABLE_INTR(mpt);
4581
4582 /*
4583 * Keep polling for at least (polltime * 1000) seconds
4584 */
4585 for (cnt = 0; cnt < polltime; cnt++) {
4586 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
4587 DDI_DMA_SYNC_FORCPU);
4588
4589 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
4590 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
4591
4592 if (ddi_get32(mpt->m_acc_post_queue_hdl,
4593 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
4594 ddi_get32(mpt->m_acc_post_queue_hdl,
4595 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
4596 drv_usecwait(1000);
4597 continue;
4598 }
4599
4600 /*
4601 * The reply is valid, process it according to its
4602 * type.
4603 */
4604 mptsas_process_intr(mpt, reply_desc_union);
4605
4606 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
4607 mpt->m_post_index = 0;
4608 }
4609
4610 /*
4611 * Update the global reply index
4612 */
4613 ddi_put32(mpt->m_datap,
4614 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
4615 mpt->m_polled_intr = 0;
4616
4617 /*
4618 * Re-enable interrupts and quit.
4619 */
4620 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
4621 int_mask);
4622 return (TRUE);
4623
4624 }
4625
4626 /*
4627 * Clear polling flag, re-enable interrupts and quit.
4628 */
4629 mpt->m_polled_intr = 0;
4630 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
4631 return (FALSE);
4632 }
4633
4634 static void
4635 mptsas_handle_scsi_io_success(mptsas_t *mpt,
4636 pMpi2ReplyDescriptorsUnion_t reply_desc)
4637 {
4638 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
4639 uint16_t SMID;
4640 mptsas_slots_t *slots = mpt->m_active;
4641 mptsas_cmd_t *cmd = NULL;
4642 struct scsi_pkt *pkt;
4643
4644 ASSERT(mutex_owned(&mpt->m_mutex));
4645
4646 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
4647 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
4648
4649 /*
4650 * This is a success reply so just complete the IO. First, do a sanity
4651 * check on the SMID. The final slot is used for TM requests, which
4652 * would not come into this reply handler.
4653 */
4654 if ((SMID == 0) || (SMID > slots->m_n_slots)) {
4655 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
4656 SMID);
4657 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4658 return;
4659 }
4660
4661 cmd = slots->m_slot[SMID];
4662
4663 /*
4664 * print warning and return if the slot is empty
4665 */
4666 if (cmd == NULL) {
4667 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
4668 "in slot %d", SMID);
4669 return;
4670 }
4671
4672 pkt = CMD2PKT(cmd);
4673 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
4674 STATE_GOT_STATUS);
4675 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4676 pkt->pkt_state |= STATE_XFERRED_DATA;
4677 }
4678 pkt->pkt_resid = 0;
4679
4680 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
4681 cmd->cmd_flags |= CFLAG_FINISHED;
4682 cv_broadcast(&mpt->m_passthru_cv);
4683 return;
4684 } else {
4685 mptsas_remove_cmd(mpt, cmd);
4686 }
4687
4688 if (cmd->cmd_flags & CFLAG_RETRY) {
4689 /*
4690 * The target returned QFULL or busy, do not add tihs
4691 * pkt to the doneq since the hba will retry
4692 * this cmd.
4693 *
4694 * The pkt has already been resubmitted in
4695 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4696 * Remove this cmd_flag here.
4697 */
4698 cmd->cmd_flags &= ~CFLAG_RETRY;
4699 } else {
4700 mptsas_doneq_add(mpt, cmd);
4701 }
4702 }
4703
4704 static void
4705 mptsas_handle_address_reply(mptsas_t *mpt,
4706 pMpi2ReplyDescriptorsUnion_t reply_desc)
4707 {
4708 pMpi2AddressReplyDescriptor_t address_reply;
4709 pMPI2DefaultReply_t reply;
4710 mptsas_fw_diagnostic_buffer_t *pBuffer;
4711 uint32_t reply_addr;
4712 uint16_t SMID, iocstatus;
4713 mptsas_slots_t *slots = mpt->m_active;
4714 mptsas_cmd_t *cmd = NULL;
4715 uint8_t function, buffer_type;
4716 m_replyh_arg_t *args;
4717 int reply_frame_no;
4718
4719 ASSERT(mutex_owned(&mpt->m_mutex));
4720
4721 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
4722 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
4723 &address_reply->ReplyFrameAddress);
4724 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
4725
4726 /*
4727 * If reply frame is not in the proper range we should ignore this
4728 * message and exit the interrupt handler.
4729 */
4730 if ((reply_addr < mpt->m_reply_frame_dma_addr) ||
4731 (reply_addr >= (mpt->m_reply_frame_dma_addr +
4732 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
4733 ((reply_addr - mpt->m_reply_frame_dma_addr) %
4734 mpt->m_reply_frame_size != 0)) {
4735 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
4736 "address 0x%x\n", reply_addr);
4737 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
4738 return;
4739 }
4740
4741 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
4742 DDI_DMA_SYNC_FORCPU);
4743 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
4744 mpt->m_reply_frame_dma_addr));
4745 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
4746
4747 /*
4748 * don't get slot information and command for events since these values
4749 * don't exist
4750 */
4751 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
4752 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
4753 /*
4754 * This could be a TM reply, which use the last allocated SMID,
4755 * so allow for that.
4756 */
4757 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) {
4758 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
4759 "%d\n", SMID);
4760 ddi_fm_service_impact(mpt->m_dip,
4761 DDI_SERVICE_UNAFFECTED);
4762 return;
4763 }
4764
4765 cmd = slots->m_slot[SMID];
4766
4767 /*
4768 * print warning and return if the slot is empty
4769 */
4770 if (cmd == NULL) {
4771 mptsas_log(mpt, CE_WARN, "?NULL command for address "
4772 "reply in slot %d", SMID);
4773 return;
4774 }
4775 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
4776 (cmd->cmd_flags & CFLAG_CONFIG) ||
4777 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
4778 cmd->cmd_rfm = reply_addr;
4779 cmd->cmd_flags |= CFLAG_FINISHED;
4780 cv_broadcast(&mpt->m_passthru_cv);
4781 cv_broadcast(&mpt->m_config_cv);
4782 cv_broadcast(&mpt->m_fw_diag_cv);
4783 return;
4784 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
4785 mptsas_remove_cmd(mpt, cmd);
4786 }
4787 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
4788 }
4789 /*
4790 * Depending on the function, we need to handle
4791 * the reply frame (and cmd) differently.
4792 */
4793 switch (function) {
4794 case MPI2_FUNCTION_SCSI_IO_REQUEST:
4795 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
4796 break;
4797 case MPI2_FUNCTION_SCSI_TASK_MGMT:
4798 cmd->cmd_rfm = reply_addr;
4799 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
4800 cmd);
4801 break;
4802 case MPI2_FUNCTION_FW_DOWNLOAD:
4803 cmd->cmd_flags |= CFLAG_FINISHED;
4804 cv_signal(&mpt->m_fw_cv);
4805 break;
4806 case MPI2_FUNCTION_EVENT_NOTIFICATION:
4807 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) /
4808 mpt->m_reply_frame_size;
4809 args = &mpt->m_replyh_args[reply_frame_no];
4810 args->mpt = (void *)mpt;
4811 args->rfm = reply_addr;
4812
4813 /*
4814 * Record the event if its type is enabled in
4815 * this mpt instance by ioctl.
4816 */
4817 mptsas_record_event(args);
4818
4819 /*
4820 * Handle time critical events
4821 * NOT_RESPONDING/ADDED only now
4822 */
4823 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
4824 /*
4825 * Would not return main process,
4826 * just let taskq resolve ack action
4827 * and ack would be sent in taskq thread
4828 */
4829 NDBG20(("send mptsas_handle_event_sync success"));
4830 }
4831
4832 if (mpt->m_in_reset) {
4833 NDBG20(("dropping event received during reset"));
4834 return;
4835 }
4836
4837 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
4838 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
4839 mptsas_log(mpt, CE_WARN, "No memory available"
4840 "for dispatch taskq");
4841 /*
4842 * Return the reply frame to the free queue.
4843 */
4844 ddi_put32(mpt->m_acc_free_queue_hdl,
4845 &((uint32_t *)(void *)
4846 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
4847 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4848 DDI_DMA_SYNC_FORDEV);
4849 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4850 mpt->m_free_index = 0;
4851 }
4852
4853 ddi_put32(mpt->m_datap,
4854 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
4855 }
4856 return;
4857 case MPI2_FUNCTION_DIAG_BUFFER_POST:
4858 /*
4859 * If SMID is 0, this implies that the reply is due to a
4860 * release function with a status that the buffer has been
4861 * released. Set the buffer flags accordingly.
4862 */
4863 if (SMID == 0) {
4864 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
4865 &reply->IOCStatus);
4866 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
4867 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
4868 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
4869 pBuffer =
4870 &mpt->m_fw_diag_buffer_list[buffer_type];
4871 pBuffer->valid_data = TRUE;
4872 pBuffer->owned_by_firmware = FALSE;
4873 pBuffer->immediate = FALSE;
4874 }
4875 } else {
4876 /*
4877 * Normal handling of diag post reply with SMID.
4878 */
4879 cmd = slots->m_slot[SMID];
4880
4881 /*
4882 * print warning and return if the slot is empty
4883 */
4884 if (cmd == NULL) {
4885 mptsas_log(mpt, CE_WARN, "?NULL command for "
4886 "address reply in slot %d", SMID);
4887 return;
4888 }
4889 cmd->cmd_rfm = reply_addr;
4890 cmd->cmd_flags |= CFLAG_FINISHED;
4891 cv_broadcast(&mpt->m_fw_diag_cv);
4892 }
4893 return;
4894 default:
4895 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
4896 break;
4897 }
4898
4899 /*
4900 * Return the reply frame to the free queue.
4901 */
4902 ddi_put32(mpt->m_acc_free_queue_hdl,
4903 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
4904 reply_addr);
4905 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
4906 DDI_DMA_SYNC_FORDEV);
4907 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
4908 mpt->m_free_index = 0;
4909 }
4910 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
4911 mpt->m_free_index);
4912
4913 if (cmd->cmd_flags & CFLAG_FW_CMD)
4914 return;
4915
4916 if (cmd->cmd_flags & CFLAG_RETRY) {
4917 /*
4918 * The target returned QFULL or busy, do not add tihs
4919 * pkt to the doneq since the hba will retry
4920 * this cmd.
4921 *
4922 * The pkt has already been resubmitted in
4923 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
4924 * Remove this cmd_flag here.
4925 */
4926 cmd->cmd_flags &= ~CFLAG_RETRY;
4927 } else {
4928 mptsas_doneq_add(mpt, cmd);
4929 }
4930 }
4931
4932 static void
4933 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
4934 mptsas_cmd_t *cmd)
4935 {
4936 uint8_t scsi_status, scsi_state;
4937 uint16_t ioc_status;
4938 uint32_t xferred, sensecount, responsedata, loginfo = 0;
4939 struct scsi_pkt *pkt;
4940 struct scsi_arq_status *arqstat;
4941 struct buf *bp;
4942 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
4943 uint8_t *sensedata = NULL;
4944
4945 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
4946 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
4947 bp = cmd->cmd_ext_arq_buf;
4948 } else {
4949 bp = cmd->cmd_arq_buf;
4950 }
4951
4952 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
4953 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
4954 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
4955 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
4956 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
4957 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
4958 &reply->ResponseInfo);
4959
4960 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
4961 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
4962 &reply->IOCLogInfo);
4963 mptsas_log(mpt, CE_NOTE,
4964 "?Log info 0x%x received for target %d.\n"
4965 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4966 loginfo, Tgt(cmd), scsi_status, ioc_status,
4967 scsi_state);
4968 }
4969
4970 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
4971 scsi_status, ioc_status, scsi_state));
4972
4973 pkt = CMD2PKT(cmd);
4974 *(pkt->pkt_scbp) = scsi_status;
4975
4976 if (loginfo == 0x31170000) {
4977 /*
4978 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
4979 * 0x31170000 comes, that means the device missing delay
4980 * is in progressing, the command need retry later.
4981 */
4982 *(pkt->pkt_scbp) = STATUS_BUSY;
4983 return;
4984 }
4985
4986 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
4987 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
4988 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
4989 pkt->pkt_reason = CMD_INCOMPLETE;
4990 pkt->pkt_state |= STATE_GOT_BUS;
4991 if (ptgt->m_reset_delay == 0) {
4992 mptsas_set_throttle(mpt, ptgt,
4993 DRAIN_THROTTLE);
4994 }
4995 return;
4996 }
4997
4998 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
4999 responsedata &= 0x000000FF;
5000 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5001 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5002 pkt->pkt_reason = CMD_TLR_OFF;
5003 return;
5004 }
5005 }
5006
5007
5008 switch (scsi_status) {
5009 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5010 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5011 arqstat = (void*)(pkt->pkt_scbp);
5012 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5013 (pkt->pkt_scbp));
5014 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5015 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5016 if (cmd->cmd_flags & CFLAG_XARQ) {
5017 pkt->pkt_state |= STATE_XARQ_DONE;
5018 }
5019 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5020 pkt->pkt_state |= STATE_XFERRED_DATA;
5021 }
5022 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5023 arqstat->sts_rqpkt_state = pkt->pkt_state;
5024 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5025 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5026 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5027
5028 bcopy((uchar_t *)bp->b_un.b_addr, sensedata,
5029 ((cmd->cmd_rqslen >= sensecount) ? sensecount :
5030 cmd->cmd_rqslen));
5031 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount);
5032 cmd->cmd_flags |= CFLAG_CMDARQ;
5033 /*
5034 * Set proper status for pkt if autosense was valid
5035 */
5036 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5037 struct scsi_status zero_status = { 0 };
5038 arqstat->sts_rqpkt_status = zero_status;
5039 }
5040
5041 /*
5042 * ASC=0x47 is parity error
5043 * ASC=0x48 is initiator detected error received
5044 */
5045 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5046 ((scsi_sense_asc(sensedata) == 0x47) ||
5047 (scsi_sense_asc(sensedata) == 0x48))) {
5048 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5049 }
5050
5051 /*
5052 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5053 * ASC/ASCQ=0x25/0x00 means invalid lun
5054 */
5055 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5056 (scsi_sense_asc(sensedata) == 0x3F) &&
5057 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5058 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5059 (scsi_sense_asc(sensedata) == 0x25) &&
5060 (scsi_sense_ascq(sensedata) == 0x00))) {
5061 mptsas_topo_change_list_t *topo_node = NULL;
5062
5063 topo_node = kmem_zalloc(
5064 sizeof (mptsas_topo_change_list_t),
5065 KM_NOSLEEP);
5066 if (topo_node == NULL) {
5067 mptsas_log(mpt, CE_NOTE, "No memory"
5068 "resource for handle SAS dynamic"
5069 "reconfigure.\n");
5070 break;
5071 }
5072 topo_node->mpt = mpt;
5073 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5074 topo_node->un.phymask = ptgt->m_phymask;
5075 topo_node->devhdl = ptgt->m_devhdl;
5076 topo_node->object = (void *)ptgt;
5077 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5078
5079 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5080 mptsas_handle_dr,
5081 (void *)topo_node,
5082 DDI_NOSLEEP)) != DDI_SUCCESS) {
5083 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5084 "for handle SAS dynamic reconfigure"
5085 "failed. \n");
5086 }
5087 }
5088 break;
5089 case MPI2_SCSI_STATUS_GOOD:
5090 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5091 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5092 pkt->pkt_reason = CMD_DEV_GONE;
5093 pkt->pkt_state |= STATE_GOT_BUS;
5094 if (ptgt->m_reset_delay == 0) {
5095 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5096 }
5097 NDBG31(("lost disk for target%d, command:%x",
5098 Tgt(cmd), pkt->pkt_cdbp[0]));
5099 break;
5100 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5101 NDBG31(("data overrun: xferred=%d", xferred));
5102 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5103 pkt->pkt_reason = CMD_DATA_OVR;
5104 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5105 | STATE_SENT_CMD | STATE_GOT_STATUS
5106 | STATE_XFERRED_DATA);
5107 pkt->pkt_resid = 0;
5108 break;
5109 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5110 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5111 NDBG31(("data underrun: xferred=%d", xferred));
5112 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5113 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5114 | STATE_SENT_CMD | STATE_GOT_STATUS);
5115 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5116 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5117 pkt->pkt_state |= STATE_XFERRED_DATA;
5118 }
5119 break;
5120 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5121 mptsas_set_pkt_reason(mpt,
5122 cmd, CMD_RESET, STAT_BUS_RESET);
5123 break;
5124 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5125 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5126 mptsas_set_pkt_reason(mpt,
5127 cmd, CMD_RESET, STAT_DEV_RESET);
5128 break;
5129 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5130 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5131 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5132 mptsas_set_pkt_reason(mpt,
5133 cmd, CMD_TERMINATED, STAT_TERMINATED);
5134 break;
5135 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5136 case MPI2_IOCSTATUS_BUSY:
5137 /*
5138 * set throttles to drain
5139 */
5140 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5141 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
5142 while (ptgt != NULL) {
5143 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5144
5145 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
5146 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
5147 }
5148
5149 /*
5150 * retry command
5151 */
5152 cmd->cmd_flags |= CFLAG_RETRY;
5153 cmd->cmd_pkt_flags |= FLAG_HEAD;
5154
5155 (void) mptsas_accept_pkt(mpt, cmd);
5156 break;
5157 default:
5158 mptsas_log(mpt, CE_WARN,
5159 "unknown ioc_status = %x\n", ioc_status);
5160 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5161 "count = %x, scsi_status = %x", scsi_state,
5162 xferred, scsi_status);
5163 break;
5164 }
5165 break;
5166 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5167 mptsas_handle_qfull(mpt, cmd);
5168 break;
5169 case MPI2_SCSI_STATUS_BUSY:
5170 NDBG31(("scsi_status busy received"));
5171 break;
5172 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5173 NDBG31(("scsi_status reservation conflict received"));
5174 break;
5175 default:
5176 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5177 scsi_status, ioc_status);
5178 mptsas_log(mpt, CE_WARN,
5179 "mptsas_process_intr: invalid scsi status\n");
5180 break;
5181 }
5182 }
5183
5184 static void
5185 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5186 mptsas_cmd_t *cmd)
5187 {
5188 uint8_t task_type;
5189 uint16_t ioc_status;
5190 uint32_t log_info;
5191 uint16_t dev_handle;
5192 struct scsi_pkt *pkt = CMD2PKT(cmd);
5193
5194 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5195 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5196 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5197 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5198
5199 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5200 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5201 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5202 task_type, ioc_status, log_info, dev_handle);
5203 pkt->pkt_reason = CMD_INCOMPLETE;
5204 return;
5205 }
5206
5207 switch (task_type) {
5208 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5209 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5210 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5211 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5212 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5213 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5214 break;
5215 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5216 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5217 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5218 /*
5219 * Check for invalid DevHandle of 0 in case application
5220 * sends bad command. DevHandle of 0 could cause problems.
5221 */
5222 if (dev_handle == 0) {
5223 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5224 " DevHandle of 0.");
5225 } else {
5226 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5227 task_type);
5228 }
5229 break;
5230 default:
5231 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5232 task_type);
5233 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5234 break;
5235 }
5236 }
5237
5238 static void
5239 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5240 {
5241 mptsas_t *mpt = arg->mpt;
5242 uint64_t t = arg->t;
5243 mptsas_cmd_t *cmd;
5244 struct scsi_pkt *pkt;
5245 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5246
5247 mutex_enter(&item->mutex);
5248 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5249 if (!item->doneq) {
5250 cv_wait(&item->cv, &item->mutex);
5251 }
5252 pkt = NULL;
5253 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5254 cmd->cmd_flags |= CFLAG_COMPLETED;
5255 pkt = CMD2PKT(cmd);
5256 }
5257 mutex_exit(&item->mutex);
5258 if (pkt) {
5259 mptsas_pkt_comp(pkt, cmd);
5260 }
5261 mutex_enter(&item->mutex);
5262 }
5263 mutex_exit(&item->mutex);
5264 mutex_enter(&mpt->m_doneq_mutex);
5265 mpt->m_doneq_thread_n--;
5266 cv_broadcast(&mpt->m_doneq_thread_cv);
5267 mutex_exit(&mpt->m_doneq_mutex);
5268 }
5269
5270
5271 /*
5272 * mpt interrupt handler.
5273 */
5274 static uint_t
5275 mptsas_intr(caddr_t arg1, caddr_t arg2)
5276 {
5277 mptsas_t *mpt = (void *)arg1;
5278 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5279 uchar_t did_reply = FALSE;
5280
5281 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5282
5283 mutex_enter(&mpt->m_mutex);
5284
5285 /*
5286 * If interrupts are shared by two channels then check whether this
5287 * interrupt is genuinely for this channel by making sure first the
5288 * chip is in high power state.
5289 */
5290 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5291 (mpt->m_power_level != PM_LEVEL_D0)) {
5292 mutex_exit(&mpt->m_mutex);
5293 return (DDI_INTR_UNCLAIMED);
5294 }
5295
5296 /*
5297 * If polling, interrupt was triggered by some shared interrupt because
5298 * IOC interrupts are disabled during polling, so polling routine will
5299 * handle any replies. Considering this, if polling is happening,
5300 * return with interrupt unclaimed.
5301 */
5302 if (mpt->m_polled_intr) {
5303 mutex_exit(&mpt->m_mutex);
5304 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5305 return (DDI_INTR_UNCLAIMED);
5306 }
5307
5308 /*
5309 * Read the istat register.
5310 */
5311 if ((INTPENDING(mpt)) != 0) {
5312 /*
5313 * read fifo until empty.
5314 */
5315 #ifndef __lock_lint
5316 _NOTE(CONSTCOND)
5317 #endif
5318 while (TRUE) {
5319 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5320 DDI_DMA_SYNC_FORCPU);
5321 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5322 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5323
5324 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5325 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5326 ddi_get32(mpt->m_acc_post_queue_hdl,
5327 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5328 break;
5329 }
5330
5331 /*
5332 * The reply is valid, process it according to its
5333 * type. Also, set a flag for updating the reply index
5334 * after they've all been processed.
5335 */
5336 did_reply = TRUE;
5337
5338 mptsas_process_intr(mpt, reply_desc_union);
5339
5340 /*
5341 * Increment post index and roll over if needed.
5342 */
5343 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5344 mpt->m_post_index = 0;
5345 }
5346 }
5347
5348 /*
5349 * Update the global reply index if at least one reply was
5350 * processed.
5351 */
5352 if (did_reply) {
5353 ddi_put32(mpt->m_datap,
5354 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5355 }
5356 } else {
5357 mutex_exit(&mpt->m_mutex);
5358 return (DDI_INTR_UNCLAIMED);
5359 }
5360 NDBG1(("mptsas_intr complete"));
5361
5362 /*
5363 * If no helper threads are created, process the doneq in ISR. If
5364 * helpers are created, use the doneq length as a metric to measure the
5365 * load on the interrupt CPU. If it is long enough, which indicates the
5366 * load is heavy, then we deliver the IO completions to the helpers.
5367 * This measurement has some limitations, although it is simple and
5368 * straightforward and works well for most of the cases at present.
5369 */
5370 if (!mpt->m_doneq_thread_n ||
5371 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5372 mptsas_doneq_empty(mpt);
5373 } else {
5374 mptsas_deliver_doneq_thread(mpt);
5375 }
5376
5377 /*
5378 * If there are queued cmd, start them now.
5379 */
5380 if (mpt->m_waitq != NULL) {
5381 mptsas_restart_waitq(mpt);
5382 }
5383
5384 mutex_exit(&mpt->m_mutex);
5385 return (DDI_INTR_CLAIMED);
5386 }
5387
5388 static void
5389 mptsas_process_intr(mptsas_t *mpt,
5390 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5391 {
5392 uint8_t reply_type;
5393
5394 ASSERT(mutex_owned(&mpt->m_mutex));
5395
5396 /*
5397 * The reply is valid, process it according to its
5398 * type. Also, set a flag for updated the reply index
5399 * after they've all been processed.
5400 */
5401 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5402 &reply_desc_union->Default.ReplyFlags);
5403 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5404 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
5405 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5406 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5407 mptsas_handle_address_reply(mpt, reply_desc_union);
5408 } else {
5409 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5410 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5411 }
5412
5413 /*
5414 * Clear the reply descriptor for re-use and increment
5415 * index.
5416 */
5417 ddi_put64(mpt->m_acc_post_queue_hdl,
5418 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
5419 0xFFFFFFFFFFFFFFFF);
5420 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5421 DDI_DMA_SYNC_FORDEV);
5422 }
5423
5424 /*
5425 * handle qfull condition
5426 */
5427 static void
5428 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5429 {
5430 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5431
5432 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5433 (ptgt->m_qfull_retries == 0)) {
5434 /*
5435 * We have exhausted the retries on QFULL, or,
5436 * the target driver has indicated that it
5437 * wants to handle QFULL itself by setting
5438 * qfull-retries capability to 0. In either case
5439 * we want the target driver's QFULL handling
5440 * to kick in. We do this by having pkt_reason
5441 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
5442 */
5443 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5444 } else {
5445 if (ptgt->m_reset_delay == 0) {
5446 ptgt->m_t_throttle =
5447 max((ptgt->m_t_ncmds - 2), 0);
5448 }
5449
5450 cmd->cmd_pkt_flags |= FLAG_HEAD;
5451 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
5452 cmd->cmd_flags |= CFLAG_RETRY;
5453
5454 (void) mptsas_accept_pkt(mpt, cmd);
5455
5456 /*
5457 * when target gives queue full status with no commands
5458 * outstanding (m_t_ncmds == 0), throttle is set to 0
5459 * (HOLD_THROTTLE), and the queue full handling start
5460 * (see psarc/1994/313); if there are commands outstanding,
5461 * throttle is set to (m_t_ncmds - 2)
5462 */
5463 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
5464 /*
5465 * By setting throttle to QFULL_THROTTLE, we
5466 * avoid submitting new commands and in
5467 * mptsas_restart_cmd find out slots which need
5468 * their throttles to be cleared.
5469 */
5470 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
5471 if (mpt->m_restart_cmd_timeid == 0) {
5472 mpt->m_restart_cmd_timeid =
5473 timeout(mptsas_restart_cmd, mpt,
5474 ptgt->m_qfull_retry_interval);
5475 }
5476 }
5477 }
5478 }
5479
5480 mptsas_phymask_t
5481 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
5482 {
5483 mptsas_phymask_t phy_mask = 0;
5484 uint8_t i = 0;
5485
5486 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
5487
5488 ASSERT(mutex_owned(&mpt->m_mutex));
5489
5490 /*
5491 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
5492 */
5493 if (physport == 0xFF) {
5494 return (0);
5495 }
5496
5497 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
5498 if (mpt->m_phy_info[i].attached_devhdl &&
5499 (mpt->m_phy_info[i].phy_mask != 0) &&
5500 (mpt->m_phy_info[i].port_num == physport)) {
5501 phy_mask = mpt->m_phy_info[i].phy_mask;
5502 break;
5503 }
5504 }
5505 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
5506 mpt->m_instance, physport, phy_mask));
5507 return (phy_mask);
5508 }
5509
5510 /*
5511 * mpt free device handle after device gone, by use of passthrough
5512 */
5513 static int
5514 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
5515 {
5516 Mpi2SasIoUnitControlRequest_t req;
5517 Mpi2SasIoUnitControlReply_t rep;
5518 int ret;
5519
5520 ASSERT(mutex_owned(&mpt->m_mutex));
5521
5522 /*
5523 * Need to compose a SAS IO Unit Control request message
5524 * and call mptsas_do_passthru() function
5525 */
5526 bzero(&req, sizeof (req));
5527 bzero(&rep, sizeof (rep));
5528
5529 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
5530 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
5531 req.DevHandle = LE_16(devhdl);
5532
5533 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
5534 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
5535 if (ret != 0) {
5536 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5537 "Control error %d", ret);
5538 return (DDI_FAILURE);
5539 }
5540
5541 /* do passthrough success, check the ioc status */
5542 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
5543 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
5544 "Control IOCStatus %d", LE_16(rep.IOCStatus));
5545 return (DDI_FAILURE);
5546 }
5547
5548 return (DDI_SUCCESS);
5549 }
5550
5551 static void
5552 mptsas_update_phymask(mptsas_t *mpt)
5553 {
5554 mptsas_phymask_t mask = 0, phy_mask;
5555 char *phy_mask_name;
5556 uint8_t current_port;
5557 int i, j;
5558
5559 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
5560
5561 ASSERT(mutex_owned(&mpt->m_mutex));
5562
5563 (void) mptsas_get_sas_io_unit_page(mpt);
5564
5565 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5566
5567 for (i = 0; i < mpt->m_num_phys; i++) {
5568 phy_mask = 0x00;
5569
5570 if (mpt->m_phy_info[i].attached_devhdl == 0)
5571 continue;
5572
5573 bzero(phy_mask_name, sizeof (phy_mask_name));
5574
5575 current_port = mpt->m_phy_info[i].port_num;
5576
5577 if ((mask & (1 << i)) != 0)
5578 continue;
5579
5580 for (j = 0; j < mpt->m_num_phys; j++) {
5581 if (mpt->m_phy_info[j].attached_devhdl &&
5582 (mpt->m_phy_info[j].port_num == current_port)) {
5583 phy_mask |= (1 << j);
5584 }
5585 }
5586 mask = mask | phy_mask;
5587
5588 for (j = 0; j < mpt->m_num_phys; j++) {
5589 if ((phy_mask >> j) & 0x01) {
5590 mpt->m_phy_info[j].phy_mask = phy_mask;
5591 }
5592 }
5593
5594 (void) sprintf(phy_mask_name, "%x", phy_mask);
5595
5596 mutex_exit(&mpt->m_mutex);
5597 /*
5598 * register a iport, if the port has already been existed
5599 * SCSA will do nothing and just return.
5600 */
5601 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
5602 mutex_enter(&mpt->m_mutex);
5603 }
5604 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5605 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
5606 }
5607
5608 /*
5609 * mptsas_handle_dr is a task handler for DR, the DR action includes:
5610 * 1. Directly attched Device Added/Removed.
5611 * 2. Expander Device Added/Removed.
5612 * 3. Indirectly Attached Device Added/Expander.
5613 * 4. LUNs of a existing device status change.
5614 * 5. RAID volume created/deleted.
5615 * 6. Member of RAID volume is released because of RAID deletion.
5616 * 7. Physical disks are removed because of RAID creation.
5617 */
5618 static void
5619 mptsas_handle_dr(void *args) {
5620 mptsas_topo_change_list_t *topo_node = NULL;
5621 mptsas_topo_change_list_t *save_node = NULL;
5622 mptsas_t *mpt;
5623 dev_info_t *parent = NULL;
5624 mptsas_phymask_t phymask = 0;
5625 char *phy_mask_name;
5626 uint8_t flags = 0, physport = 0xff;
5627 uint8_t port_update = 0;
5628 uint_t event;
5629
5630 topo_node = (mptsas_topo_change_list_t *)args;
5631
5632 mpt = topo_node->mpt;
5633 event = topo_node->event;
5634 flags = topo_node->flags;
5635
5636 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5637
5638 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
5639
5640 switch (event) {
5641 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5642 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5643 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
5644 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
5645 /*
5646 * Direct attached or expander attached device added
5647 * into system or a Phys Disk that is being unhidden.
5648 */
5649 port_update = 1;
5650 }
5651 break;
5652 case MPTSAS_DR_EVENT_RECONFIG_SMP:
5653 /*
5654 * New expander added into system, it must be the head
5655 * of topo_change_list_t
5656 */
5657 port_update = 1;
5658 break;
5659 default:
5660 port_update = 0;
5661 break;
5662 }
5663 /*
5664 * All cases port_update == 1 may cause initiator port form change
5665 */
5666 mutex_enter(&mpt->m_mutex);
5667 if (mpt->m_port_chng && port_update) {
5668 /*
5669 * mpt->m_port_chng flag indicates some PHYs of initiator
5670 * port have changed to online. So when expander added or
5671 * directly attached device online event come, we force to
5672 * update port information by issueing SAS IO Unit Page and
5673 * update PHYMASKs.
5674 */
5675 (void) mptsas_update_phymask(mpt);
5676 mpt->m_port_chng = 0;
5677
5678 }
5679 mutex_exit(&mpt->m_mutex);
5680 while (topo_node) {
5681 phymask = 0;
5682 if (parent == NULL) {
5683 physport = topo_node->un.physport;
5684 event = topo_node->event;
5685 flags = topo_node->flags;
5686 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
5687 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
5688 /*
5689 * For all offline events, phymask is known
5690 */
5691 phymask = topo_node->un.phymask;
5692 goto find_parent;
5693 }
5694 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
5695 goto handle_topo_change;
5696 }
5697 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
5698 phymask = topo_node->un.phymask;
5699 goto find_parent;
5700 }
5701
5702 if ((flags ==
5703 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
5704 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
5705 /*
5706 * There is no any field in IR_CONFIG_CHANGE
5707 * event indicate physport/phynum, let's get
5708 * parent after SAS Device Page0 request.
5709 */
5710 goto handle_topo_change;
5711 }
5712
5713 mutex_enter(&mpt->m_mutex);
5714 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5715 /*
5716 * If the direct attached device added or a
5717 * phys disk is being unhidden, argument
5718 * physport actually is PHY#, so we have to get
5719 * phymask according PHY#.
5720 */
5721 physport = mpt->m_phy_info[physport].port_num;
5722 }
5723
5724 /*
5725 * Translate physport to phymask so that we can search
5726 * parent dip.
5727 */
5728 phymask = mptsas_physport_to_phymask(mpt,
5729 physport);
5730 mutex_exit(&mpt->m_mutex);
5731
5732 find_parent:
5733 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
5734 /*
5735 * For RAID topology change node, write the iport name
5736 * as v0.
5737 */
5738 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5739 (void) sprintf(phy_mask_name, "v0");
5740 } else {
5741 /*
5742 * phymask can bo 0 if the drive has been
5743 * pulled by the time an add event is
5744 * processed. If phymask is 0, just skip this
5745 * event and continue.
5746 */
5747 if (phymask == 0) {
5748 mutex_enter(&mpt->m_mutex);
5749 save_node = topo_node;
5750 topo_node = topo_node->next;
5751 ASSERT(save_node);
5752 kmem_free(save_node,
5753 sizeof (mptsas_topo_change_list_t));
5754 mutex_exit(&mpt->m_mutex);
5755
5756 parent = NULL;
5757 continue;
5758 }
5759 (void) sprintf(phy_mask_name, "%x", phymask);
5760 }
5761 parent = scsi_hba_iport_find(mpt->m_dip,
5762 phy_mask_name);
5763 if (parent == NULL) {
5764 mptsas_log(mpt, CE_WARN, "Failed to find an "
5765 "iport, should not happen!");
5766 goto out;
5767 }
5768
5769 }
5770 ASSERT(parent);
5771 handle_topo_change:
5772
5773 mutex_enter(&mpt->m_mutex);
5774 /*
5775 * If HBA is being reset, don't perform operations depending
5776 * on the IOC. We must free the topo list, however.
5777 */
5778 if (!mpt->m_in_reset)
5779 mptsas_handle_topo_change(topo_node, parent);
5780 else
5781 NDBG20(("skipping topo change received during reset"));
5782 save_node = topo_node;
5783 topo_node = topo_node->next;
5784 ASSERT(save_node);
5785 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
5786 mutex_exit(&mpt->m_mutex);
5787
5788 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
5789 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
5790 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
5791 /*
5792 * If direct attached device associated, make sure
5793 * reset the parent before start the next one. But
5794 * all devices associated with expander shares the
5795 * parent. Also, reset parent if this is for RAID.
5796 */
5797 parent = NULL;
5798 }
5799 }
5800 out:
5801 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5802 }
5803
5804 static void
5805 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
5806 dev_info_t *parent)
5807 {
5808 mptsas_target_t *ptgt = NULL;
5809 mptsas_smp_t *psmp = NULL;
5810 mptsas_t *mpt = (void *)topo_node->mpt;
5811 uint16_t devhdl;
5812 uint16_t attached_devhdl;
5813 uint64_t sas_wwn = 0;
5814 int rval = 0;
5815 uint32_t page_address;
5816 uint8_t phy, flags;
5817 char *addr = NULL;
5818 dev_info_t *lundip;
5819 int circ = 0, circ1 = 0;
5820 char attached_wwnstr[MPTSAS_WWN_STRLEN];
5821
5822 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance));
5823
5824 ASSERT(mutex_owned(&mpt->m_mutex));
5825
5826 switch (topo_node->event) {
5827 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
5828 {
5829 char *phy_mask_name;
5830 mptsas_phymask_t phymask = 0;
5831
5832 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5833 /*
5834 * Get latest RAID info.
5835 */
5836 (void) mptsas_get_raid_info(mpt);
5837 ptgt = mptsas_search_by_devhdl(
5838 &mpt->m_active->m_tgttbl, topo_node->devhdl);
5839 if (ptgt == NULL)
5840 break;
5841 } else {
5842 ptgt = (void *)topo_node->object;
5843 }
5844
5845 if (ptgt == NULL) {
5846 /*
5847 * If a Phys Disk was deleted, RAID info needs to be
5848 * updated to reflect the new topology.
5849 */
5850 (void) mptsas_get_raid_info(mpt);
5851
5852 /*
5853 * Get sas device page 0 by DevHandle to make sure if
5854 * SSP/SATA end device exist.
5855 */
5856 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
5857 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
5858 topo_node->devhdl;
5859
5860 rval = mptsas_get_target_device_info(mpt, page_address,
5861 &devhdl, &ptgt);
5862 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
5863 mptsas_log(mpt, CE_NOTE,
5864 "mptsas_handle_topo_change: target %d is "
5865 "not a SAS/SATA device. \n",
5866 topo_node->devhdl);
5867 } else if (rval == DEV_INFO_FAIL_ALLOC) {
5868 mptsas_log(mpt, CE_NOTE,
5869 "mptsas_handle_topo_change: could not "
5870 "allocate memory. \n");
5871 }
5872 /*
5873 * If rval is DEV_INFO_PHYS_DISK than there is nothing
5874 * else to do, just leave.
5875 */
5876 if (rval != DEV_INFO_SUCCESS) {
5877 return;
5878 }
5879 }
5880
5881 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
5882
5883 mutex_exit(&mpt->m_mutex);
5884 flags = topo_node->flags;
5885
5886 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
5887 phymask = ptgt->m_phymask;
5888 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
5889 (void) sprintf(phy_mask_name, "%x", phymask);
5890 parent = scsi_hba_iport_find(mpt->m_dip,
5891 phy_mask_name);
5892 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
5893 if (parent == NULL) {
5894 mptsas_log(mpt, CE_WARN, "Failed to find a "
5895 "iport for PD, should not happen!");
5896 mutex_enter(&mpt->m_mutex);
5897 break;
5898 }
5899 }
5900
5901 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
5902 ndi_devi_enter(parent, &circ1);
5903 (void) mptsas_config_raid(parent, topo_node->devhdl,
5904 &lundip);
5905 ndi_devi_exit(parent, circ1);
5906 } else {
5907 /*
5908 * hold nexus for bus configure
5909 */
5910 ndi_devi_enter(scsi_vhci_dip, &circ);
5911 ndi_devi_enter(parent, &circ1);
5912 rval = mptsas_config_target(parent, ptgt);
5913 /*
5914 * release nexus for bus configure
5915 */
5916 ndi_devi_exit(parent, circ1);
5917 ndi_devi_exit(scsi_vhci_dip, circ);
5918
5919 /*
5920 * Add parent's props for SMHBA support
5921 */
5922 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
5923 bzero(attached_wwnstr,
5924 sizeof (attached_wwnstr));
5925 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
5926 ptgt->m_sas_wwn);
5927 if (ddi_prop_update_string(DDI_DEV_T_NONE,
5928 parent,
5929 SCSI_ADDR_PROP_ATTACHED_PORT,
5930 attached_wwnstr)
5931 != DDI_PROP_SUCCESS) {
5932 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5933 parent,
5934 SCSI_ADDR_PROP_ATTACHED_PORT);
5935 mptsas_log(mpt, CE_WARN, "Failed to"
5936 "attached-port props");
5937 return;
5938 }
5939 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5940 MPTSAS_NUM_PHYS, 1) !=
5941 DDI_PROP_SUCCESS) {
5942 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5943 parent, MPTSAS_NUM_PHYS);
5944 mptsas_log(mpt, CE_WARN, "Failed to"
5945 " create num-phys props");
5946 return;
5947 }
5948
5949 /*
5950 * Update PHY info for smhba
5951 */
5952 mutex_enter(&mpt->m_mutex);
5953 if (mptsas_smhba_phy_init(mpt)) {
5954 mutex_exit(&mpt->m_mutex);
5955 mptsas_log(mpt, CE_WARN, "mptsas phy"
5956 " update failed");
5957 return;
5958 }
5959 mutex_exit(&mpt->m_mutex);
5960
5961 /*
5962 * topo_node->un.physport is really the PHY#
5963 * for direct attached devices
5964 */
5965 mptsas_smhba_set_one_phy_props(mpt, parent,
5966 topo_node->un.physport, &attached_devhdl);
5967
5968 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
5969 MPTSAS_VIRTUAL_PORT, 0) !=
5970 DDI_PROP_SUCCESS) {
5971 (void) ddi_prop_remove(DDI_DEV_T_NONE,
5972 parent, MPTSAS_VIRTUAL_PORT);
5973 mptsas_log(mpt, CE_WARN,
5974 "mptsas virtual-port"
5975 "port prop update failed");
5976 return;
5977 }
5978 }
5979 }
5980 mutex_enter(&mpt->m_mutex);
5981
5982 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
5983 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
5984 ptgt->m_phymask));
5985 break;
5986 }
5987 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
5988 {
5989 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl;
5990 devhdl = topo_node->devhdl;
5991 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl);
5992 if (ptgt == NULL)
5993 break;
5994
5995 sas_wwn = ptgt->m_sas_wwn;
5996 phy = ptgt->m_phynum;
5997
5998 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
5999
6000 if (sas_wwn) {
6001 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6002 } else {
6003 (void) sprintf(addr, "p%x", phy);
6004 }
6005 ASSERT(ptgt->m_devhdl == devhdl);
6006
6007 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6008 (topo_node->flags ==
6009 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6010 /*
6011 * Get latest RAID info if RAID volume status changes
6012 * or Phys Disk status changes
6013 */
6014 (void) mptsas_get_raid_info(mpt);
6015 }
6016 /*
6017 * Abort all outstanding command on the device
6018 */
6019 rval = mptsas_do_scsi_reset(mpt, devhdl);
6020 if (rval) {
6021 NDBG20(("mptsas%d handle_topo_change to reset target "
6022 "before offline devhdl:%x, phymask:%x, rval:%x",
6023 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask,
6024 rval));
6025 }
6026
6027 mutex_exit(&mpt->m_mutex);
6028
6029 ndi_devi_enter(scsi_vhci_dip, &circ);
6030 ndi_devi_enter(parent, &circ1);
6031 rval = mptsas_offline_target(parent, addr);
6032 ndi_devi_exit(parent, circ1);
6033 ndi_devi_exit(scsi_vhci_dip, circ);
6034 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6035 "phymask:%x, rval:%x", mpt->m_instance,
6036 ptgt->m_devhdl, ptgt->m_phymask, rval));
6037
6038 kmem_free(addr, SCSI_MAXNAMELEN);
6039
6040 /*
6041 * Clear parent's props for SMHBA support
6042 */
6043 flags = topo_node->flags;
6044 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6045 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6046 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6047 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6048 DDI_PROP_SUCCESS) {
6049 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6050 SCSI_ADDR_PROP_ATTACHED_PORT);
6051 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6052 "prop update failed");
6053 break;
6054 }
6055 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6056 MPTSAS_NUM_PHYS, 0) !=
6057 DDI_PROP_SUCCESS) {
6058 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6059 MPTSAS_NUM_PHYS);
6060 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6061 "prop update failed");
6062 break;
6063 }
6064 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6065 MPTSAS_VIRTUAL_PORT, 1) !=
6066 DDI_PROP_SUCCESS) {
6067 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6068 MPTSAS_VIRTUAL_PORT);
6069 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6070 "prop update failed");
6071 break;
6072 }
6073 }
6074
6075 mutex_enter(&mpt->m_mutex);
6076 ptgt->m_led_status = 0;
6077 (void) mptsas_flush_led_status(mpt, ptgt);
6078 if (rval == DDI_SUCCESS) {
6079 mptsas_tgt_free(&mpt->m_active->m_tgttbl,
6080 ptgt->m_sas_wwn, ptgt->m_phymask);
6081 ptgt = NULL;
6082 } else {
6083 /*
6084 * clean DR_INTRANSITION flag to allow I/O down to
6085 * PHCI driver since failover finished.
6086 * Invalidate the devhdl
6087 */
6088 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6089 ptgt->m_tgt_unconfigured = 0;
6090 mutex_enter(&mpt->m_tx_waitq_mutex);
6091 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6092 mutex_exit(&mpt->m_tx_waitq_mutex);
6093 }
6094
6095 /*
6096 * Send SAS IO Unit Control to free the dev handle
6097 */
6098 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6099 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6100 rval = mptsas_free_devhdl(mpt, devhdl);
6101
6102 NDBG20(("mptsas%d handle_topo_change to remove "
6103 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6104 rval));
6105 }
6106
6107 break;
6108 }
6109 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6110 {
6111 devhdl = topo_node->devhdl;
6112 /*
6113 * If this is the remove handle event, do a reset first.
6114 */
6115 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6116 rval = mptsas_do_scsi_reset(mpt, devhdl);
6117 if (rval) {
6118 NDBG20(("mpt%d reset target before remove "
6119 "devhdl:%x, rval:%x", mpt->m_instance,
6120 devhdl, rval));
6121 }
6122 }
6123
6124 /*
6125 * Send SAS IO Unit Control to free the dev handle
6126 */
6127 rval = mptsas_free_devhdl(mpt, devhdl);
6128 NDBG20(("mptsas%d handle_topo_change to remove "
6129 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6130 rval));
6131 break;
6132 }
6133 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6134 {
6135 mptsas_smp_t smp;
6136 dev_info_t *smpdip;
6137 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6138
6139 devhdl = topo_node->devhdl;
6140
6141 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6142 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6143 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6144 if (rval != DDI_SUCCESS) {
6145 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6146 "handle %x", devhdl);
6147 return;
6148 }
6149
6150 psmp = mptsas_smp_alloc(smptbl, &smp);
6151 if (psmp == NULL) {
6152 return;
6153 }
6154
6155 mutex_exit(&mpt->m_mutex);
6156 ndi_devi_enter(parent, &circ1);
6157 (void) mptsas_online_smp(parent, psmp, &smpdip);
6158 ndi_devi_exit(parent, circ1);
6159
6160 mutex_enter(&mpt->m_mutex);
6161 break;
6162 }
6163 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6164 {
6165 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl;
6166 devhdl = topo_node->devhdl;
6167 uint32_t dev_info;
6168
6169 psmp = mptsas_search_by_devhdl(smptbl, devhdl);
6170 if (psmp == NULL)
6171 break;
6172 /*
6173 * The mptsas_smp_t data is released only if the dip is offlined
6174 * successfully.
6175 */
6176 mutex_exit(&mpt->m_mutex);
6177
6178 ndi_devi_enter(parent, &circ1);
6179 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6180 ndi_devi_exit(parent, circ1);
6181
6182 dev_info = psmp->m_deviceinfo;
6183 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6184 DEVINFO_DIRECT_ATTACHED) {
6185 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6186 MPTSAS_VIRTUAL_PORT, 1) !=
6187 DDI_PROP_SUCCESS) {
6188 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6189 MPTSAS_VIRTUAL_PORT);
6190 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6191 "prop update failed");
6192 return;
6193 }
6194 /*
6195 * Check whether the smp connected to the iport,
6196 */
6197 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6198 MPTSAS_NUM_PHYS, 0) !=
6199 DDI_PROP_SUCCESS) {
6200 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6201 MPTSAS_NUM_PHYS);
6202 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6203 "prop update failed");
6204 return;
6205 }
6206 /*
6207 * Clear parent's attached-port props
6208 */
6209 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6210 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6211 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6212 DDI_PROP_SUCCESS) {
6213 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6214 SCSI_ADDR_PROP_ATTACHED_PORT);
6215 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6216 "prop update failed");
6217 return;
6218 }
6219 }
6220
6221 mutex_enter(&mpt->m_mutex);
6222 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6223 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6224 if (rval == DDI_SUCCESS) {
6225 mptsas_smp_free(smptbl, psmp->m_sasaddr,
6226 psmp->m_phymask);
6227 } else {
6228 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6229 }
6230
6231 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6232
6233 break;
6234 }
6235 default:
6236 return;
6237 }
6238 }
6239
6240 /*
6241 * Record the event if its type is enabled in mpt instance by ioctl.
6242 */
6243 static void
6244 mptsas_record_event(void *args)
6245 {
6246 m_replyh_arg_t *replyh_arg;
6247 pMpi2EventNotificationReply_t eventreply;
6248 uint32_t event, rfm;
6249 mptsas_t *mpt;
6250 int i, j;
6251 uint16_t event_data_len;
6252 boolean_t sendAEN = FALSE;
6253
6254 replyh_arg = (m_replyh_arg_t *)args;
6255 rfm = replyh_arg->rfm;
6256 mpt = replyh_arg->mpt;
6257
6258 eventreply = (pMpi2EventNotificationReply_t)
6259 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6260 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6261
6262
6263 /*
6264 * Generate a system event to let anyone who cares know that a
6265 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6266 * event mask is set to.
6267 */
6268 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6269 sendAEN = TRUE;
6270 }
6271
6272 /*
6273 * Record the event only if it is not masked. Determine which dword
6274 * and bit of event mask to test.
6275 */
6276 i = (uint8_t)(event / 32);
6277 j = (uint8_t)(event % 32);
6278 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6279 i = mpt->m_event_index;
6280 mpt->m_events[i].Type = event;
6281 mpt->m_events[i].Number = ++mpt->m_event_number;
6282 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6283 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6284 &eventreply->EventDataLength);
6285
6286 if (event_data_len > 0) {
6287 /*
6288 * Limit data to size in m_event entry
6289 */
6290 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6291 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6292 }
6293 for (j = 0; j < event_data_len; j++) {
6294 mpt->m_events[i].Data[j] =
6295 ddi_get32(mpt->m_acc_reply_frame_hdl,
6296 &(eventreply->EventData[j]));
6297 }
6298
6299 /*
6300 * check for index wrap-around
6301 */
6302 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6303 i = 0;
6304 }
6305 mpt->m_event_index = (uint8_t)i;
6306
6307 /*
6308 * Set flag to send the event.
6309 */
6310 sendAEN = TRUE;
6311 }
6312 }
6313
6314 /*
6315 * Generate a system event if flag is set to let anyone who cares know
6316 * that an event has occurred.
6317 */
6318 if (sendAEN) {
6319 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6320 "SAS", NULL, NULL, DDI_NOSLEEP);
6321 }
6322 }
6323
6324 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6325 /*
6326 * handle sync events from ioc in interrupt
6327 * return value:
6328 * DDI_SUCCESS: The event is handled by this func
6329 * DDI_FAILURE: Event is not handled
6330 */
6331 static int
6332 mptsas_handle_event_sync(void *args)
6333 {
6334 m_replyh_arg_t *replyh_arg;
6335 pMpi2EventNotificationReply_t eventreply;
6336 uint32_t event, rfm;
6337 mptsas_t *mpt;
6338 uint_t iocstatus;
6339
6340 replyh_arg = (m_replyh_arg_t *)args;
6341 rfm = replyh_arg->rfm;
6342 mpt = replyh_arg->mpt;
6343
6344 ASSERT(mutex_owned(&mpt->m_mutex));
6345
6346 eventreply = (pMpi2EventNotificationReply_t)
6347 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
6348 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6349
6350 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6351 &eventreply->IOCStatus)) {
6352 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6353 mptsas_log(mpt, CE_WARN,
6354 "!mptsas_handle_event_sync: IOCStatus=0x%x, "
6355 "IOCLogInfo=0x%x", iocstatus,
6356 ddi_get32(mpt->m_acc_reply_frame_hdl,
6357 &eventreply->IOCLogInfo));
6358 } else {
6359 mptsas_log(mpt, CE_WARN,
6360 "mptsas_handle_event_sync: IOCStatus=0x%x, "
6361 "IOCLogInfo=0x%x", iocstatus,
6362 ddi_get32(mpt->m_acc_reply_frame_hdl,
6363 &eventreply->IOCLogInfo));
6364 }
6365 }
6366
6367 /*
6368 * figure out what kind of event we got and handle accordingly
6369 */
6370 switch (event) {
6371 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6372 {
6373 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6374 uint8_t num_entries, expstatus, phy;
6375 uint8_t phystatus, physport, state, i;
6376 uint8_t start_phy_num, link_rate;
6377 uint16_t dev_handle, reason_code;
6378 uint16_t enc_handle, expd_handle;
6379 char string[80], curr[80], prev[80];
6380 mptsas_topo_change_list_t *topo_head = NULL;
6381 mptsas_topo_change_list_t *topo_tail = NULL;
6382 mptsas_topo_change_list_t *topo_node = NULL;
6383 mptsas_target_t *ptgt;
6384 mptsas_smp_t *psmp;
6385 mptsas_hash_table_t *tgttbl, *smptbl;
6386 uint8_t flags = 0, exp_flag;
6387 smhba_info_t *pSmhba = NULL;
6388
6389 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6390
6391 tgttbl = &mpt->m_active->m_tgttbl;
6392 smptbl = &mpt->m_active->m_smptbl;
6393
6394 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6395 eventreply->EventData;
6396
6397 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6398 &sas_topo_change_list->EnclosureHandle);
6399 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6400 &sas_topo_change_list->ExpanderDevHandle);
6401 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6402 &sas_topo_change_list->NumEntries);
6403 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6404 &sas_topo_change_list->StartPhyNum);
6405 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6406 &sas_topo_change_list->ExpStatus);
6407 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6408 &sas_topo_change_list->PhysicalPort);
6409
6410 string[0] = 0;
6411 if (expd_handle) {
6412 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6413 switch (expstatus) {
6414 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6415 (void) sprintf(string, " added");
6416 /*
6417 * New expander device added
6418 */
6419 mpt->m_port_chng = 1;
6420 topo_node = kmem_zalloc(
6421 sizeof (mptsas_topo_change_list_t),
6422 KM_SLEEP);
6423 topo_node->mpt = mpt;
6424 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6425 topo_node->un.physport = physport;
6426 topo_node->devhdl = expd_handle;
6427 topo_node->flags = flags;
6428 topo_node->object = NULL;
6429 if (topo_head == NULL) {
6430 topo_head = topo_tail = topo_node;
6431 } else {
6432 topo_tail->next = topo_node;
6433 topo_tail = topo_node;
6434 }
6435 break;
6436 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
6437 (void) sprintf(string, " not responding, "
6438 "removed");
6439 psmp = mptsas_search_by_devhdl(smptbl,
6440 expd_handle);
6441 if (psmp == NULL)
6442 break;
6443
6444 topo_node = kmem_zalloc(
6445 sizeof (mptsas_topo_change_list_t),
6446 KM_SLEEP);
6447 topo_node->mpt = mpt;
6448 topo_node->un.phymask = psmp->m_phymask;
6449 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
6450 topo_node->devhdl = expd_handle;
6451 topo_node->flags = flags;
6452 topo_node->object = NULL;
6453 if (topo_head == NULL) {
6454 topo_head = topo_tail = topo_node;
6455 } else {
6456 topo_tail->next = topo_node;
6457 topo_tail = topo_node;
6458 }
6459 break;
6460 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
6461 break;
6462 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
6463 (void) sprintf(string, " not responding, "
6464 "delaying removal");
6465 break;
6466 default:
6467 break;
6468 }
6469 } else {
6470 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
6471 }
6472
6473 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
6474 enc_handle, expd_handle, string));
6475 for (i = 0; i < num_entries; i++) {
6476 phy = i + start_phy_num;
6477 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6478 &sas_topo_change_list->PHY[i].PhyStatus);
6479 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6480 &sas_topo_change_list->PHY[i].AttachedDevHandle);
6481 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
6482 /*
6483 * Filter out processing of Phy Vacant Status unless
6484 * the reason code is "Not Responding". Process all
6485 * other combinations of Phy Status and Reason Codes.
6486 */
6487 if ((phystatus &
6488 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
6489 (reason_code !=
6490 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
6491 continue;
6492 }
6493 curr[0] = 0;
6494 prev[0] = 0;
6495 string[0] = 0;
6496 switch (reason_code) {
6497 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
6498 {
6499 NDBG20(("mptsas%d phy %d physical_port %d "
6500 "dev_handle %d added", mpt->m_instance, phy,
6501 physport, dev_handle));
6502 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6503 &sas_topo_change_list->PHY[i].LinkRate);
6504 state = (link_rate &
6505 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6506 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6507 switch (state) {
6508 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6509 (void) sprintf(curr, "is disabled");
6510 break;
6511 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6512 (void) sprintf(curr, "is offline, "
6513 "failed speed negotiation");
6514 break;
6515 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6516 (void) sprintf(curr, "SATA OOB "
6517 "complete");
6518 break;
6519 case SMP_RESET_IN_PROGRESS:
6520 (void) sprintf(curr, "SMP reset in "
6521 "progress");
6522 break;
6523 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6524 (void) sprintf(curr, "is online at "
6525 "1.5 Gbps");
6526 break;
6527 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6528 (void) sprintf(curr, "is online at 3.0 "
6529 "Gbps");
6530 break;
6531 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6532 (void) sprintf(curr, "is online at 6.0 "
6533 "Gbps");
6534 break;
6535 default:
6536 (void) sprintf(curr, "state is "
6537 "unknown");
6538 break;
6539 }
6540 /*
6541 * New target device added into the system.
6542 * Set association flag according to if an
6543 * expander is used or not.
6544 */
6545 exp_flag =
6546 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6547 if (flags ==
6548 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6549 flags = exp_flag;
6550 }
6551 topo_node = kmem_zalloc(
6552 sizeof (mptsas_topo_change_list_t),
6553 KM_SLEEP);
6554 topo_node->mpt = mpt;
6555 topo_node->event =
6556 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6557 if (expd_handle == 0) {
6558 /*
6559 * Per MPI 2, if expander dev handle
6560 * is 0, it's a directly attached
6561 * device. So driver use PHY to decide
6562 * which iport is associated
6563 */
6564 physport = phy;
6565 mpt->m_port_chng = 1;
6566 }
6567 topo_node->un.physport = physport;
6568 topo_node->devhdl = dev_handle;
6569 topo_node->flags = flags;
6570 topo_node->object = NULL;
6571 if (topo_head == NULL) {
6572 topo_head = topo_tail = topo_node;
6573 } else {
6574 topo_tail->next = topo_node;
6575 topo_tail = topo_node;
6576 }
6577 break;
6578 }
6579 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
6580 {
6581 NDBG20(("mptsas%d phy %d physical_port %d "
6582 "dev_handle %d removed", mpt->m_instance,
6583 phy, physport, dev_handle));
6584 /*
6585 * Set association flag according to if an
6586 * expander is used or not.
6587 */
6588 exp_flag =
6589 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
6590 if (flags ==
6591 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
6592 flags = exp_flag;
6593 }
6594 /*
6595 * Target device is removed from the system
6596 * Before the device is really offline from
6597 * from system.
6598 */
6599 ptgt = mptsas_search_by_devhdl(tgttbl,
6600 dev_handle);
6601 /*
6602 * If ptgt is NULL here, it means that the
6603 * DevHandle is not in the hash table. This is
6604 * reasonable sometimes. For example, if a
6605 * disk was pulled, then added, then pulled
6606 * again, the disk will not have been put into
6607 * the hash table because the add event will
6608 * have an invalid phymask. BUT, this does not
6609 * mean that the DevHandle is invalid. The
6610 * controller will still have a valid DevHandle
6611 * that must be removed. To do this, use the
6612 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
6613 */
6614 if (ptgt == NULL) {
6615 topo_node = kmem_zalloc(
6616 sizeof (mptsas_topo_change_list_t),
6617 KM_SLEEP);
6618 topo_node->mpt = mpt;
6619 topo_node->un.phymask = 0;
6620 topo_node->event =
6621 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
6622 topo_node->devhdl = dev_handle;
6623 topo_node->flags = flags;
6624 topo_node->object = NULL;
6625 if (topo_head == NULL) {
6626 topo_head = topo_tail =
6627 topo_node;
6628 } else {
6629 topo_tail->next = topo_node;
6630 topo_tail = topo_node;
6631 }
6632 break;
6633 }
6634
6635 /*
6636 * Update DR flag immediately avoid I/O failure
6637 * before failover finish. Pay attention to the
6638 * mutex protect, we need grab m_tx_waitq_mutex
6639 * during set m_dr_flag because we won't add
6640 * the following command into waitq, instead,
6641 * we need return TRAN_BUSY in the tran_start
6642 * context.
6643 */
6644 mutex_enter(&mpt->m_tx_waitq_mutex);
6645 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6646 mutex_exit(&mpt->m_tx_waitq_mutex);
6647
6648 topo_node = kmem_zalloc(
6649 sizeof (mptsas_topo_change_list_t),
6650 KM_SLEEP);
6651 topo_node->mpt = mpt;
6652 topo_node->un.phymask = ptgt->m_phymask;
6653 topo_node->event =
6654 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6655 topo_node->devhdl = dev_handle;
6656 topo_node->flags = flags;
6657 topo_node->object = NULL;
6658 if (topo_head == NULL) {
6659 topo_head = topo_tail = topo_node;
6660 } else {
6661 topo_tail->next = topo_node;
6662 topo_tail = topo_node;
6663 }
6664 break;
6665 }
6666 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
6667 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
6668 &sas_topo_change_list->PHY[i].LinkRate);
6669 state = (link_rate &
6670 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
6671 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
6672 pSmhba = &mpt->m_phy_info[i].smhba_info;
6673 pSmhba->negotiated_link_rate = state;
6674 switch (state) {
6675 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6676 (void) sprintf(curr, "is disabled");
6677 mptsas_smhba_log_sysevent(mpt,
6678 ESC_SAS_PHY_EVENT,
6679 SAS_PHY_REMOVE,
6680 &mpt->m_phy_info[i].smhba_info);
6681 mpt->m_phy_info[i].smhba_info.
6682 negotiated_link_rate
6683 = 0x1;
6684 break;
6685 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6686 (void) sprintf(curr, "is offline, "
6687 "failed speed negotiation");
6688 mptsas_smhba_log_sysevent(mpt,
6689 ESC_SAS_PHY_EVENT,
6690 SAS_PHY_OFFLINE,
6691 &mpt->m_phy_info[i].smhba_info);
6692 break;
6693 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6694 (void) sprintf(curr, "SATA OOB "
6695 "complete");
6696 break;
6697 case SMP_RESET_IN_PROGRESS:
6698 (void) sprintf(curr, "SMP reset in "
6699 "progress");
6700 break;
6701 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6702 (void) sprintf(curr, "is online at "
6703 "1.5 Gbps");
6704 if ((expd_handle == 0) &&
6705 (enc_handle == 1)) {
6706 mpt->m_port_chng = 1;
6707 }
6708 mptsas_smhba_log_sysevent(mpt,
6709 ESC_SAS_PHY_EVENT,
6710 SAS_PHY_ONLINE,
6711 &mpt->m_phy_info[i].smhba_info);
6712 break;
6713 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6714 (void) sprintf(curr, "is online at 3.0 "
6715 "Gbps");
6716 if ((expd_handle == 0) &&
6717 (enc_handle == 1)) {
6718 mpt->m_port_chng = 1;
6719 }
6720 mptsas_smhba_log_sysevent(mpt,
6721 ESC_SAS_PHY_EVENT,
6722 SAS_PHY_ONLINE,
6723 &mpt->m_phy_info[i].smhba_info);
6724 break;
6725 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6726 (void) sprintf(curr, "is online at "
6727 "6.0 Gbps");
6728 if ((expd_handle == 0) &&
6729 (enc_handle == 1)) {
6730 mpt->m_port_chng = 1;
6731 }
6732 mptsas_smhba_log_sysevent(mpt,
6733 ESC_SAS_PHY_EVENT,
6734 SAS_PHY_ONLINE,
6735 &mpt->m_phy_info[i].smhba_info);
6736 break;
6737 default:
6738 (void) sprintf(curr, "state is "
6739 "unknown");
6740 break;
6741 }
6742
6743 state = (link_rate &
6744 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
6745 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
6746 switch (state) {
6747 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
6748 (void) sprintf(prev, ", was disabled");
6749 break;
6750 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
6751 (void) sprintf(prev, ", was offline, "
6752 "failed speed negotiation");
6753 break;
6754 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
6755 (void) sprintf(prev, ", was SATA OOB "
6756 "complete");
6757 break;
6758 case SMP_RESET_IN_PROGRESS:
6759 (void) sprintf(prev, ", was SMP reset "
6760 "in progress");
6761 break;
6762 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
6763 (void) sprintf(prev, ", was online at "
6764 "1.5 Gbps");
6765 break;
6766 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
6767 (void) sprintf(prev, ", was online at "
6768 "3.0 Gbps");
6769 break;
6770 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
6771 (void) sprintf(prev, ", was online at "
6772 "6.0 Gbps");
6773 break;
6774 default:
6775 break;
6776 }
6777 (void) sprintf(&string[strlen(string)], "link "
6778 "changed, ");
6779 break;
6780 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
6781 continue;
6782 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
6783 (void) sprintf(&string[strlen(string)],
6784 "target not responding, delaying "
6785 "removal");
6786 break;
6787 }
6788 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
6789 mpt->m_instance, phy, dev_handle, string, curr,
6790 prev));
6791 }
6792 if (topo_head != NULL) {
6793 /*
6794 * Launch DR taskq to handle topology change
6795 */
6796 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6797 mptsas_handle_dr, (void *)topo_head,
6798 DDI_NOSLEEP)) != DDI_SUCCESS) {
6799 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6800 "for handle SAS DR event failed. \n");
6801 }
6802 }
6803 break;
6804 }
6805 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
6806 {
6807 Mpi2EventDataIrConfigChangeList_t *irChangeList;
6808 mptsas_topo_change_list_t *topo_head = NULL;
6809 mptsas_topo_change_list_t *topo_tail = NULL;
6810 mptsas_topo_change_list_t *topo_node = NULL;
6811 mptsas_target_t *ptgt;
6812 mptsas_hash_table_t *tgttbl;
6813 uint8_t num_entries, i, reason;
6814 uint16_t volhandle, diskhandle;
6815
6816 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
6817 eventreply->EventData;
6818 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6819 &irChangeList->NumElements);
6820
6821 tgttbl = &mpt->m_active->m_tgttbl;
6822
6823 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
6824 mpt->m_instance));
6825
6826 for (i = 0; i < num_entries; i++) {
6827 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
6828 &irChangeList->ConfigElement[i].ReasonCode);
6829 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6830 &irChangeList->ConfigElement[i].VolDevHandle);
6831 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6832 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
6833
6834 switch (reason) {
6835 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
6836 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
6837 {
6838 NDBG20(("mptsas %d volume added\n",
6839 mpt->m_instance));
6840
6841 topo_node = kmem_zalloc(
6842 sizeof (mptsas_topo_change_list_t),
6843 KM_SLEEP);
6844
6845 topo_node->mpt = mpt;
6846 topo_node->event =
6847 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6848 topo_node->un.physport = 0xff;
6849 topo_node->devhdl = volhandle;
6850 topo_node->flags =
6851 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6852 topo_node->object = NULL;
6853 if (topo_head == NULL) {
6854 topo_head = topo_tail = topo_node;
6855 } else {
6856 topo_tail->next = topo_node;
6857 topo_tail = topo_node;
6858 }
6859 break;
6860 }
6861 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
6862 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
6863 {
6864 NDBG20(("mptsas %d volume deleted\n",
6865 mpt->m_instance));
6866 ptgt = mptsas_search_by_devhdl(tgttbl,
6867 volhandle);
6868 if (ptgt == NULL)
6869 break;
6870
6871 /*
6872 * Clear any flags related to volume
6873 */
6874 (void) mptsas_delete_volume(mpt, volhandle);
6875
6876 /*
6877 * Update DR flag immediately avoid I/O failure
6878 */
6879 mutex_enter(&mpt->m_tx_waitq_mutex);
6880 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6881 mutex_exit(&mpt->m_tx_waitq_mutex);
6882
6883 topo_node = kmem_zalloc(
6884 sizeof (mptsas_topo_change_list_t),
6885 KM_SLEEP);
6886 topo_node->mpt = mpt;
6887 topo_node->un.phymask = ptgt->m_phymask;
6888 topo_node->event =
6889 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6890 topo_node->devhdl = volhandle;
6891 topo_node->flags =
6892 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
6893 topo_node->object = (void *)ptgt;
6894 if (topo_head == NULL) {
6895 topo_head = topo_tail = topo_node;
6896 } else {
6897 topo_tail->next = topo_node;
6898 topo_tail = topo_node;
6899 }
6900 break;
6901 }
6902 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
6903 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
6904 {
6905 ptgt = mptsas_search_by_devhdl(tgttbl,
6906 diskhandle);
6907 if (ptgt == NULL)
6908 break;
6909
6910 /*
6911 * Update DR flag immediately avoid I/O failure
6912 */
6913 mutex_enter(&mpt->m_tx_waitq_mutex);
6914 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
6915 mutex_exit(&mpt->m_tx_waitq_mutex);
6916
6917 topo_node = kmem_zalloc(
6918 sizeof (mptsas_topo_change_list_t),
6919 KM_SLEEP);
6920 topo_node->mpt = mpt;
6921 topo_node->un.phymask = ptgt->m_phymask;
6922 topo_node->event =
6923 MPTSAS_DR_EVENT_OFFLINE_TARGET;
6924 topo_node->devhdl = diskhandle;
6925 topo_node->flags =
6926 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6927 topo_node->object = (void *)ptgt;
6928 if (topo_head == NULL) {
6929 topo_head = topo_tail = topo_node;
6930 } else {
6931 topo_tail->next = topo_node;
6932 topo_tail = topo_node;
6933 }
6934 break;
6935 }
6936 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
6937 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
6938 {
6939 /*
6940 * The physical drive is released by a IR
6941 * volume. But we cannot get the the physport
6942 * or phynum from the event data, so we only
6943 * can get the physport/phynum after SAS
6944 * Device Page0 request for the devhdl.
6945 */
6946 topo_node = kmem_zalloc(
6947 sizeof (mptsas_topo_change_list_t),
6948 KM_SLEEP);
6949 topo_node->mpt = mpt;
6950 topo_node->un.phymask = 0;
6951 topo_node->event =
6952 MPTSAS_DR_EVENT_RECONFIG_TARGET;
6953 topo_node->devhdl = diskhandle;
6954 topo_node->flags =
6955 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
6956 topo_node->object = NULL;
6957 mpt->m_port_chng = 1;
6958 if (topo_head == NULL) {
6959 topo_head = topo_tail = topo_node;
6960 } else {
6961 topo_tail->next = topo_node;
6962 topo_tail = topo_node;
6963 }
6964 break;
6965 }
6966 default:
6967 break;
6968 }
6969 }
6970
6971 if (topo_head != NULL) {
6972 /*
6973 * Launch DR taskq to handle topology change
6974 */
6975 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
6976 mptsas_handle_dr, (void *)topo_head,
6977 DDI_NOSLEEP)) != DDI_SUCCESS) {
6978 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
6979 "for handle SAS DR event failed. \n");
6980 }
6981 }
6982 break;
6983 }
6984 default:
6985 return (DDI_FAILURE);
6986 }
6987
6988 return (DDI_SUCCESS);
6989 }
6990
6991 /*
6992 * handle events from ioc
6993 */
6994 static void
6995 mptsas_handle_event(void *args)
6996 {
6997 m_replyh_arg_t *replyh_arg;
6998 pMpi2EventNotificationReply_t eventreply;
6999 uint32_t event, iocloginfo, rfm;
7000 uint32_t status;
7001 uint8_t port;
7002 mptsas_t *mpt;
7003 uint_t iocstatus;
7004
7005 replyh_arg = (m_replyh_arg_t *)args;
7006 rfm = replyh_arg->rfm;
7007 mpt = replyh_arg->mpt;
7008
7009 mutex_enter(&mpt->m_mutex);
7010 /*
7011 * If HBA is being reset, drop incoming event.
7012 */
7013 if (mpt->m_in_reset) {
7014 NDBG20(("dropping event received prior to reset"));
7015 mutex_exit(&mpt->m_mutex);
7016 return;
7017 }
7018
7019 eventreply = (pMpi2EventNotificationReply_t)
7020 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr));
7021 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7022
7023 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7024 &eventreply->IOCStatus)) {
7025 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7026 mptsas_log(mpt, CE_WARN,
7027 "!mptsas_handle_event: IOCStatus=0x%x, "
7028 "IOCLogInfo=0x%x", iocstatus,
7029 ddi_get32(mpt->m_acc_reply_frame_hdl,
7030 &eventreply->IOCLogInfo));
7031 } else {
7032 mptsas_log(mpt, CE_WARN,
7033 "mptsas_handle_event: IOCStatus=0x%x, "
7034 "IOCLogInfo=0x%x", iocstatus,
7035 ddi_get32(mpt->m_acc_reply_frame_hdl,
7036 &eventreply->IOCLogInfo));
7037 }
7038 }
7039
7040 /*
7041 * figure out what kind of event we got and handle accordingly
7042 */
7043 switch (event) {
7044 case MPI2_EVENT_LOG_ENTRY_ADDED:
7045 break;
7046 case MPI2_EVENT_LOG_DATA:
7047 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7048 &eventreply->IOCLogInfo);
7049 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7050 iocloginfo));
7051 break;
7052 case MPI2_EVENT_STATE_CHANGE:
7053 NDBG20(("mptsas%d state change.", mpt->m_instance));
7054 break;
7055 case MPI2_EVENT_HARD_RESET_RECEIVED:
7056 NDBG20(("mptsas%d event change.", mpt->m_instance));
7057 break;
7058 case MPI2_EVENT_SAS_DISCOVERY:
7059 {
7060 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7061 char string[80];
7062 uint8_t rc;
7063
7064 sasdiscovery =
7065 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7066
7067 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7068 &sasdiscovery->ReasonCode);
7069 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7070 &sasdiscovery->PhysicalPort);
7071 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7072 &sasdiscovery->DiscoveryStatus);
7073
7074 string[0] = 0;
7075 switch (rc) {
7076 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7077 (void) sprintf(string, "STARTING");
7078 break;
7079 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7080 (void) sprintf(string, "COMPLETED");
7081 break;
7082 default:
7083 (void) sprintf(string, "UNKNOWN");
7084 break;
7085 }
7086
7087 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7088 port, status));
7089
7090 break;
7091 }
7092 case MPI2_EVENT_EVENT_CHANGE:
7093 NDBG20(("mptsas%d event change.", mpt->m_instance));
7094 break;
7095 case MPI2_EVENT_TASK_SET_FULL:
7096 {
7097 pMpi2EventDataTaskSetFull_t taskfull;
7098
7099 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7100
7101 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7102 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7103 &taskfull->CurrentDepth)));
7104 break;
7105 }
7106 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7107 {
7108 /*
7109 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7110 * in mptsas_handle_event_sync() of interrupt context
7111 */
7112 break;
7113 }
7114 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7115 {
7116 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7117 uint8_t rc;
7118 char string[80];
7119
7120 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7121 eventreply->EventData;
7122
7123 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7124 &encstatus->ReasonCode);
7125 switch (rc) {
7126 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7127 (void) sprintf(string, "added");
7128 break;
7129 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7130 (void) sprintf(string, ", not responding");
7131 break;
7132 default:
7133 break;
7134 }
7135 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n",
7136 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7137 &encstatus->EnclosureHandle), string));
7138 break;
7139 }
7140
7141 /*
7142 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7143 * mptsas_handle_event_sync,in here just send ack message.
7144 */
7145 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7146 {
7147 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7148 uint8_t rc;
7149 uint16_t devhdl;
7150 uint64_t wwn = 0;
7151 uint32_t wwn_lo, wwn_hi;
7152
7153 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7154 eventreply->EventData;
7155 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7156 &statuschange->ReasonCode);
7157 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7158 (uint32_t *)(void *)&statuschange->SASAddress);
7159 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7160 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7161 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7162 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7163 &statuschange->DevHandle);
7164
7165 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7166 wwn));
7167
7168 switch (rc) {
7169 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7170 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7171 ddi_get8(mpt->m_acc_reply_frame_hdl,
7172 &statuschange->ASC),
7173 ddi_get8(mpt->m_acc_reply_frame_hdl,
7174 &statuschange->ASCQ)));
7175 break;
7176
7177 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7178 NDBG20(("Device not supported"));
7179 break;
7180
7181 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7182 NDBG20(("IOC internally generated the Target Reset "
7183 "for devhdl:%x", devhdl));
7184 break;
7185
7186 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7187 NDBG20(("IOC's internally generated Target Reset "
7188 "completed for devhdl:%x", devhdl));
7189 break;
7190
7191 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7192 NDBG20(("IOC internally generated Abort Task"));
7193 break;
7194
7195 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7196 NDBG20(("IOC's internally generated Abort Task "
7197 "completed"));
7198 break;
7199
7200 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7201 NDBG20(("IOC internally generated Abort Task Set"));
7202 break;
7203
7204 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7205 NDBG20(("IOC internally generated Clear Task Set"));
7206 break;
7207
7208 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7209 NDBG20(("IOC internally generated Query Task"));
7210 break;
7211
7212 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7213 NDBG20(("Device sent an Asynchronous Notification"));
7214 break;
7215
7216 default:
7217 break;
7218 }
7219 break;
7220 }
7221 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7222 {
7223 /*
7224 * IR TOPOLOGY CHANGE LIST Event has already been handled
7225 * in mpt_handle_event_sync() of interrupt context
7226 */
7227 break;
7228 }
7229 case MPI2_EVENT_IR_OPERATION_STATUS:
7230 {
7231 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7232 char reason_str[80];
7233 uint8_t rc, percent;
7234 uint16_t handle;
7235
7236 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7237 eventreply->EventData;
7238 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7239 &irOpStatus->RAIDOperation);
7240 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7241 &irOpStatus->PercentComplete);
7242 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7243 &irOpStatus->VolDevHandle);
7244
7245 switch (rc) {
7246 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7247 (void) sprintf(reason_str, "resync");
7248 break;
7249 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7250 (void) sprintf(reason_str, "online capacity "
7251 "expansion");
7252 break;
7253 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7254 (void) sprintf(reason_str, "consistency check");
7255 break;
7256 default:
7257 (void) sprintf(reason_str, "unknown reason %x",
7258 rc);
7259 }
7260
7261 NDBG20(("mptsas%d raid operational status: (%s)"
7262 "\thandle(0x%04x), percent complete(%d)\n",
7263 mpt->m_instance, reason_str, handle, percent));
7264 break;
7265 }
7266 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7267 {
7268 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7269 uint8_t phy_num;
7270 uint8_t primitive;
7271
7272 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7273 eventreply->EventData;
7274
7275 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7276 &sas_broadcast->PhyNum);
7277 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7278 &sas_broadcast->Primitive);
7279
7280 switch (primitive) {
7281 case MPI2_EVENT_PRIMITIVE_CHANGE:
7282 mptsas_smhba_log_sysevent(mpt,
7283 ESC_SAS_HBA_PORT_BROADCAST,
7284 SAS_PORT_BROADCAST_CHANGE,
7285 &mpt->m_phy_info[phy_num].smhba_info);
7286 break;
7287 case MPI2_EVENT_PRIMITIVE_SES:
7288 mptsas_smhba_log_sysevent(mpt,
7289 ESC_SAS_HBA_PORT_BROADCAST,
7290 SAS_PORT_BROADCAST_SES,
7291 &mpt->m_phy_info[phy_num].smhba_info);
7292 break;
7293 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7294 mptsas_smhba_log_sysevent(mpt,
7295 ESC_SAS_HBA_PORT_BROADCAST,
7296 SAS_PORT_BROADCAST_D01_4,
7297 &mpt->m_phy_info[phy_num].smhba_info);
7298 break;
7299 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7300 mptsas_smhba_log_sysevent(mpt,
7301 ESC_SAS_HBA_PORT_BROADCAST,
7302 SAS_PORT_BROADCAST_D04_7,
7303 &mpt->m_phy_info[phy_num].smhba_info);
7304 break;
7305 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7306 mptsas_smhba_log_sysevent(mpt,
7307 ESC_SAS_HBA_PORT_BROADCAST,
7308 SAS_PORT_BROADCAST_D16_7,
7309 &mpt->m_phy_info[phy_num].smhba_info);
7310 break;
7311 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7312 mptsas_smhba_log_sysevent(mpt,
7313 ESC_SAS_HBA_PORT_BROADCAST,
7314 SAS_PORT_BROADCAST_D29_7,
7315 &mpt->m_phy_info[phy_num].smhba_info);
7316 break;
7317 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7318 mptsas_smhba_log_sysevent(mpt,
7319 ESC_SAS_HBA_PORT_BROADCAST,
7320 SAS_PORT_BROADCAST_D24_0,
7321 &mpt->m_phy_info[phy_num].smhba_info);
7322 break;
7323 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7324 mptsas_smhba_log_sysevent(mpt,
7325 ESC_SAS_HBA_PORT_BROADCAST,
7326 SAS_PORT_BROADCAST_D27_4,
7327 &mpt->m_phy_info[phy_num].smhba_info);
7328 break;
7329 default:
7330 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE"
7331 " %x received",
7332 mpt->m_instance, primitive));
7333 break;
7334 }
7335 NDBG20(("mptsas%d sas broadcast primitive: "
7336 "\tprimitive(0x%04x), phy(%d) complete\n",
7337 mpt->m_instance, primitive, phy_num));
7338 break;
7339 }
7340 case MPI2_EVENT_IR_VOLUME:
7341 {
7342 Mpi2EventDataIrVolume_t *irVolume;
7343 uint16_t devhandle;
7344 uint32_t state;
7345 int config, vol;
7346 mptsas_slots_t *slots = mpt->m_active;
7347 uint8_t found = FALSE;
7348
7349 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7350 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7351 &irVolume->NewValue);
7352 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7353 &irVolume->VolDevHandle);
7354
7355 NDBG20(("EVENT_IR_VOLUME event is received"));
7356
7357 /*
7358 * Get latest RAID info and then find the DevHandle for this
7359 * event in the configuration. If the DevHandle is not found
7360 * just exit the event.
7361 */
7362 (void) mptsas_get_raid_info(mpt);
7363 for (config = 0; (config < slots->m_num_raid_configs) &&
7364 (!found); config++) {
7365 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7366 if (slots->m_raidconfig[config].m_raidvol[vol].
7367 m_raidhandle == devhandle) {
7368 found = TRUE;
7369 break;
7370 }
7371 }
7372 }
7373 if (!found) {
7374 break;
7375 }
7376
7377 switch (irVolume->ReasonCode) {
7378 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7379 {
7380 uint32_t i;
7381 slots->m_raidconfig[config].m_raidvol[vol].m_settings =
7382 state;
7383
7384 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7385 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7386 ", auto-config of hot-swap drives is %s"
7387 ", write caching is %s"
7388 ", hot-spare pool mask is %02x\n",
7389 vol, state &
7390 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7391 ? "disabled" : "enabled",
7392 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7393 ? "controlled by member disks" :
7394 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
7395 ? "disabled" :
7396 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
7397 ? "enabled" :
7398 "incorrectly set",
7399 (state >> 16) & 0xff);
7400 break;
7401 }
7402 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
7403 {
7404 slots->m_raidconfig[config].m_raidvol[vol].m_state =
7405 (uint8_t)state;
7406
7407 mptsas_log(mpt, CE_NOTE,
7408 "Volume %d is now %s\n", vol,
7409 state == MPI2_RAID_VOL_STATE_OPTIMAL
7410 ? "optimal" :
7411 state == MPI2_RAID_VOL_STATE_DEGRADED
7412 ? "degraded" :
7413 state == MPI2_RAID_VOL_STATE_ONLINE
7414 ? "online" :
7415 state == MPI2_RAID_VOL_STATE_INITIALIZING
7416 ? "initializing" :
7417 state == MPI2_RAID_VOL_STATE_FAILED
7418 ? "failed" :
7419 state == MPI2_RAID_VOL_STATE_MISSING
7420 ? "missing" :
7421 "state unknown");
7422 break;
7423 }
7424 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
7425 {
7426 slots->m_raidconfig[config].m_raidvol[vol].
7427 m_statusflags = state;
7428
7429 mptsas_log(mpt, CE_NOTE,
7430 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
7431 vol,
7432 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
7433 ? ", enabled" : ", disabled",
7434 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
7435 ? ", quiesced" : "",
7436 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
7437 ? ", inactive" : ", active",
7438 state &
7439 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
7440 ? ", bad block table is full" : "",
7441 state &
7442 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
7443 ? ", resync in progress" : "",
7444 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
7445 ? ", background initialization in progress" : "",
7446 state &
7447 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
7448 ? ", capacity expansion in progress" : "",
7449 state &
7450 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
7451 ? ", consistency check in progress" : "",
7452 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
7453 ? ", data scrub in progress" : "");
7454 break;
7455 }
7456 default:
7457 break;
7458 }
7459 break;
7460 }
7461 case MPI2_EVENT_IR_PHYSICAL_DISK:
7462 {
7463 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
7464 uint16_t devhandle, enchandle, slot;
7465 uint32_t status, state;
7466 uint8_t physdisknum, reason;
7467
7468 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
7469 eventreply->EventData;
7470 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
7471 &irPhysDisk->PhysDiskNum);
7472 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7473 &irPhysDisk->PhysDiskDevHandle);
7474 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7475 &irPhysDisk->EnclosureHandle);
7476 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
7477 &irPhysDisk->Slot);
7478 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7479 &irPhysDisk->NewValue);
7480 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7481 &irPhysDisk->ReasonCode);
7482
7483 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
7484
7485 switch (reason) {
7486 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
7487 mptsas_log(mpt, CE_NOTE,
7488 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7489 "for enclosure with handle 0x%x is now in hot "
7490 "spare pool %d",
7491 physdisknum, devhandle, slot, enchandle,
7492 (state >> 16) & 0xff);
7493 break;
7494
7495 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
7496 status = state;
7497 mptsas_log(mpt, CE_NOTE,
7498 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7499 "for enclosure with handle 0x%x is now "
7500 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
7501 enchandle,
7502 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
7503 ? ", inactive" : ", active",
7504 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
7505 ? ", out of sync" : "",
7506 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
7507 ? ", quiesced" : "",
7508 status &
7509 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
7510 ? ", write cache enabled" : "",
7511 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
7512 ? ", capacity expansion target" : "");
7513 break;
7514
7515 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
7516 mptsas_log(mpt, CE_NOTE,
7517 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
7518 "for enclosure with handle 0x%x is now %s\n",
7519 physdisknum, devhandle, slot, enchandle,
7520 state == MPI2_RAID_PD_STATE_OPTIMAL
7521 ? "optimal" :
7522 state == MPI2_RAID_PD_STATE_REBUILDING
7523 ? "rebuilding" :
7524 state == MPI2_RAID_PD_STATE_DEGRADED
7525 ? "degraded" :
7526 state == MPI2_RAID_PD_STATE_HOT_SPARE
7527 ? "a hot spare" :
7528 state == MPI2_RAID_PD_STATE_ONLINE
7529 ? "online" :
7530 state == MPI2_RAID_PD_STATE_OFFLINE
7531 ? "offline" :
7532 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
7533 ? "not compatible" :
7534 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
7535 ? "not configured" :
7536 "state unknown");
7537 break;
7538 }
7539 break;
7540 }
7541 default:
7542 NDBG20(("mptsas%d: unknown event %x received",
7543 mpt->m_instance, event));
7544 break;
7545 }
7546
7547 /*
7548 * Return the reply frame to the free queue.
7549 */
7550 ddi_put32(mpt->m_acc_free_queue_hdl,
7551 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
7552 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
7553 DDI_DMA_SYNC_FORDEV);
7554 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
7555 mpt->m_free_index = 0;
7556 }
7557 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
7558 mpt->m_free_index);
7559 mutex_exit(&mpt->m_mutex);
7560 }
7561
7562 /*
7563 * invoked from timeout() to restart qfull cmds with throttle == 0
7564 */
7565 static void
7566 mptsas_restart_cmd(void *arg)
7567 {
7568 mptsas_t *mpt = arg;
7569 mptsas_target_t *ptgt = NULL;
7570
7571 mutex_enter(&mpt->m_mutex);
7572
7573 mpt->m_restart_cmd_timeid = 0;
7574
7575 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
7576 MPTSAS_HASH_FIRST);
7577 while (ptgt != NULL) {
7578 if (ptgt->m_reset_delay == 0) {
7579 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
7580 mptsas_set_throttle(mpt, ptgt,
7581 MAX_THROTTLE);
7582 }
7583 }
7584
7585 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
7586 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
7587 }
7588 mptsas_restart_hba(mpt);
7589 mutex_exit(&mpt->m_mutex);
7590 }
7591
7592 void
7593 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7594 {
7595 int slot;
7596 mptsas_slots_t *slots = mpt->m_active;
7597 int t;
7598 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7599
7600 ASSERT(cmd != NULL);
7601 ASSERT(cmd->cmd_queued == FALSE);
7602
7603 /*
7604 * Task Management cmds are removed in their own routines. Also,
7605 * we don't want to modify timeout based on TM cmds.
7606 */
7607 if (cmd->cmd_flags & CFLAG_TM_CMD) {
7608 return;
7609 }
7610
7611 t = Tgt(cmd);
7612 slot = cmd->cmd_slot;
7613
7614 /*
7615 * remove the cmd.
7616 */
7617 if (cmd == slots->m_slot[slot]) {
7618 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd));
7619 slots->m_slot[slot] = NULL;
7620 mpt->m_ncmds--;
7621
7622 /*
7623 * only decrement per target ncmds if command
7624 * has a target associated with it.
7625 */
7626 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
7627 ptgt->m_t_ncmds--;
7628 /*
7629 * reset throttle if we just ran an untagged command
7630 * to a tagged target
7631 */
7632 if ((ptgt->m_t_ncmds == 0) &&
7633 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
7634 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7635 }
7636 }
7637
7638 }
7639
7640 /*
7641 * This is all we need to do for ioc commands.
7642 */
7643 if (cmd->cmd_flags & CFLAG_CMDIOC) {
7644 mptsas_return_to_pool(mpt, cmd);
7645 return;
7646 }
7647
7648 /*
7649 * Figure out what to set tag Q timeout for...
7650 *
7651 * Optimize: If we have duplicate's of same timeout
7652 * we're using, then we'll use it again until we run
7653 * out of duplicates. This should be the normal case
7654 * for block and raw I/O.
7655 * If no duplicates, we have to scan through tag que and
7656 * find the longest timeout value and use it. This is
7657 * going to take a while...
7658 * Add 1 to m_n_slots to account for TM request.
7659 */
7660 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) {
7661 if (--(ptgt->m_dups) == 0) {
7662 if (ptgt->m_t_ncmds) {
7663 mptsas_cmd_t *ssp;
7664 uint_t n = 0;
7665 ushort_t nslots = (slots->m_n_slots + 1);
7666 ushort_t i;
7667 /*
7668 * This crude check assumes we don't do
7669 * this too often which seems reasonable
7670 * for block and raw I/O.
7671 */
7672 for (i = 0; i < nslots; i++) {
7673 ssp = slots->m_slot[i];
7674 if (ssp && (Tgt(ssp) == t) &&
7675 (ssp->cmd_pkt->pkt_time > n)) {
7676 n = ssp->cmd_pkt->pkt_time;
7677 ptgt->m_dups = 1;
7678 } else if (ssp && (Tgt(ssp) == t) &&
7679 (ssp->cmd_pkt->pkt_time == n)) {
7680 ptgt->m_dups++;
7681 }
7682 }
7683 ptgt->m_timebase = n;
7684 } else {
7685 ptgt->m_dups = 0;
7686 ptgt->m_timebase = 0;
7687 }
7688 }
7689 }
7690 ptgt->m_timeout = ptgt->m_timebase;
7691
7692 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
7693 }
7694
7695 /*
7696 * accept all cmds on the tx_waitq if any and then
7697 * start a fresh request from the top of the device queue.
7698 *
7699 * since there are always cmds queued on the tx_waitq, and rare cmds on
7700 * the instance waitq, so this function should not be invoked in the ISR,
7701 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
7702 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
7703 */
7704 static void
7705 mptsas_restart_hba(mptsas_t *mpt)
7706 {
7707 ASSERT(mutex_owned(&mpt->m_mutex));
7708
7709 mutex_enter(&mpt->m_tx_waitq_mutex);
7710 if (mpt->m_tx_waitq) {
7711 mptsas_accept_tx_waitq(mpt);
7712 }
7713 mutex_exit(&mpt->m_tx_waitq_mutex);
7714 mptsas_restart_waitq(mpt);
7715 }
7716
7717 /*
7718 * start a fresh request from the top of the device queue
7719 */
7720 static void
7721 mptsas_restart_waitq(mptsas_t *mpt)
7722 {
7723 mptsas_cmd_t *cmd, *next_cmd;
7724 mptsas_target_t *ptgt = NULL;
7725
7726 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
7727
7728 ASSERT(mutex_owned(&mpt->m_mutex));
7729
7730 /*
7731 * If there is a reset delay, don't start any cmds. Otherwise, start
7732 * as many cmds as possible.
7733 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
7734 * commands is m_max_requests - 2.
7735 */
7736 cmd = mpt->m_waitq;
7737
7738 while (cmd != NULL) {
7739 next_cmd = cmd->cmd_linkp;
7740 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
7741 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7742 /*
7743 * passthru command get slot need
7744 * set CFLAG_PREPARED.
7745 */
7746 cmd->cmd_flags |= CFLAG_PREPARED;
7747 mptsas_waitq_delete(mpt, cmd);
7748 mptsas_start_passthru(mpt, cmd);
7749 }
7750 cmd = next_cmd;
7751 continue;
7752 }
7753 if (cmd->cmd_flags & CFLAG_CONFIG) {
7754 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7755 /*
7756 * Send the config page request and delete it
7757 * from the waitq.
7758 */
7759 cmd->cmd_flags |= CFLAG_PREPARED;
7760 mptsas_waitq_delete(mpt, cmd);
7761 mptsas_start_config_page_access(mpt, cmd);
7762 }
7763 cmd = next_cmd;
7764 continue;
7765 }
7766 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
7767 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7768 /*
7769 * Send the FW Diag request and delete if from
7770 * the waitq.
7771 */
7772 cmd->cmd_flags |= CFLAG_PREPARED;
7773 mptsas_waitq_delete(mpt, cmd);
7774 mptsas_start_diag(mpt, cmd);
7775 }
7776 cmd = next_cmd;
7777 continue;
7778 }
7779
7780 ptgt = cmd->cmd_tgt_addr;
7781 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
7782 (ptgt->m_t_ncmds == 0)) {
7783 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
7784 }
7785 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
7786 (ptgt && (ptgt->m_reset_delay == 0)) &&
7787 (ptgt && (ptgt->m_t_ncmds <
7788 ptgt->m_t_throttle))) {
7789 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
7790 mptsas_waitq_delete(mpt, cmd);
7791 (void) mptsas_start_cmd(mpt, cmd);
7792 }
7793 }
7794 cmd = next_cmd;
7795 }
7796 }
7797 /*
7798 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
7799 * Accept all those queued cmds before new cmd is accept so that the
7800 * cmds are sent in order.
7801 */
7802 static void
7803 mptsas_accept_tx_waitq(mptsas_t *mpt)
7804 {
7805 mptsas_cmd_t *cmd;
7806
7807 ASSERT(mutex_owned(&mpt->m_mutex));
7808 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
7809
7810 /*
7811 * A Bus Reset could occur at any time and flush the tx_waitq,
7812 * so we cannot count on the tx_waitq to contain even one cmd.
7813 * And when the m_tx_waitq_mutex is released and run
7814 * mptsas_accept_pkt(), the tx_waitq may be flushed.
7815 */
7816 cmd = mpt->m_tx_waitq;
7817 for (;;) {
7818 if ((cmd = mpt->m_tx_waitq) == NULL) {
7819 mpt->m_tx_draining = 0;
7820 break;
7821 }
7822 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
7823 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
7824 }
7825 cmd->cmd_linkp = NULL;
7826 mutex_exit(&mpt->m_tx_waitq_mutex);
7827 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
7828 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
7829 "to accept cmd on queue\n");
7830 mutex_enter(&mpt->m_tx_waitq_mutex);
7831 }
7832 }
7833
7834
7835 /*
7836 * mpt tag type lookup
7837 */
7838 static char mptsas_tag_lookup[] =
7839 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
7840
7841 static int
7842 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
7843 {
7844 struct scsi_pkt *pkt = CMD2PKT(cmd);
7845 uint32_t control = 0;
7846 int n;
7847 caddr_t mem;
7848 pMpi2SCSIIORequest_t io_request;
7849 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
7850 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
7851 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
7852 uint16_t SMID, io_flags = 0;
7853 uint32_t request_desc_low, request_desc_high;
7854
7855 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd));
7856
7857 /*
7858 * Set SMID and increment index. Rollover to 1 instead of 0 if index
7859 * is at the max. 0 is an invalid SMID, so we call the first index 1.
7860 */
7861 SMID = cmd->cmd_slot;
7862
7863 /*
7864 * It is possible for back to back device reset to
7865 * happen before the reset delay has expired. That's
7866 * ok, just let the device reset go out on the bus.
7867 */
7868 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7869 ASSERT(ptgt->m_reset_delay == 0);
7870 }
7871
7872 /*
7873 * if a non-tagged cmd is submitted to an active tagged target
7874 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
7875 * to be untagged
7876 */
7877 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
7878 (ptgt->m_t_ncmds > 1) &&
7879 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
7880 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
7881 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
7882 NDBG23(("target=%d, untagged cmd, start draining\n",
7883 ptgt->m_devhdl));
7884
7885 if (ptgt->m_reset_delay == 0) {
7886 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
7887 }
7888
7889 mptsas_remove_cmd(mpt, cmd);
7890 cmd->cmd_pkt_flags |= FLAG_HEAD;
7891 mptsas_waitq_add(mpt, cmd);
7892 }
7893 return (DDI_FAILURE);
7894 }
7895
7896 /*
7897 * Set correct tag bits.
7898 */
7899 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
7900 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
7901 FLAG_TAGMASK) >> 12)]) {
7902 case MSG_SIMPLE_QTAG:
7903 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7904 break;
7905 case MSG_HEAD_QTAG:
7906 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
7907 break;
7908 case MSG_ORDERED_QTAG:
7909 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
7910 break;
7911 default:
7912 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
7913 break;
7914 }
7915 } else {
7916 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
7917 ptgt->m_t_throttle = 1;
7918 }
7919 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
7920 }
7921
7922 if (cmd->cmd_pkt_flags & FLAG_TLR) {
7923 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
7924 }
7925
7926 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
7927 io_request = (pMpi2SCSIIORequest_t)mem;
7928
7929 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
7930 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
7931 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
7932 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
7933 MPI2_FUNCTION_SCSI_IO_REQUEST);
7934
7935 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
7936 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
7937
7938 io_flags = cmd->cmd_cdblen;
7939 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
7940 /*
7941 * setup the Scatter/Gather DMA list for this request
7942 */
7943 if (cmd->cmd_cookiec > 0) {
7944 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
7945 } else {
7946 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
7947 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
7948 MPI2_SGE_FLAGS_END_OF_BUFFER |
7949 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
7950 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
7951 }
7952
7953 /*
7954 * save ARQ information
7955 */
7956 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen);
7957 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) ==
7958 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) {
7959 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7960 cmd->cmd_ext_arqcookie.dmac_address);
7961 } else {
7962 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress,
7963 cmd->cmd_arqcookie.dmac_address);
7964 }
7965
7966 ddi_put32(acc_hdl, &io_request->Control, control);
7967
7968 NDBG31(("starting message=0x%p, with cmd=0x%p",
7969 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd));
7970
7971 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
7972
7973 /*
7974 * Build request descriptor and write it to the request desc post reg.
7975 */
7976 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
7977 request_desc_high = ptgt->m_devhdl << 16;
7978 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
7979
7980 /*
7981 * Start timeout.
7982 */
7983 #ifdef MPTSAS_TEST
7984 /*
7985 * Temporarily set timebase = 0; needed for
7986 * timeout torture test.
7987 */
7988 if (mptsas_test_timeouts) {
7989 ptgt->m_timebase = 0;
7990 }
7991 #endif
7992 n = pkt->pkt_time - ptgt->m_timebase;
7993
7994 if (n == 0) {
7995 (ptgt->m_dups)++;
7996 ptgt->m_timeout = ptgt->m_timebase;
7997 } else if (n > 0) {
7998 ptgt->m_timeout =
7999 ptgt->m_timebase = pkt->pkt_time;
8000 ptgt->m_dups = 1;
8001 } else if (n < 0) {
8002 ptgt->m_timeout = ptgt->m_timebase;
8003 }
8004 #ifdef MPTSAS_TEST
8005 /*
8006 * Set back to a number higher than
8007 * mptsas_scsi_watchdog_tick
8008 * so timeouts will happen in mptsas_watchsubr
8009 */
8010 if (mptsas_test_timeouts) {
8011 ptgt->m_timebase = 60;
8012 }
8013 #endif
8014
8015 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8016 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8017 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8018 return (DDI_FAILURE);
8019 }
8020 return (DDI_SUCCESS);
8021 }
8022
8023 /*
8024 * Select a helper thread to handle current doneq
8025 */
8026 static void
8027 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8028 {
8029 uint64_t t, i;
8030 uint32_t min = 0xffffffff;
8031 mptsas_doneq_thread_list_t *item;
8032
8033 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8034 item = &mpt->m_doneq_thread_id[i];
8035 /*
8036 * If the completed command on help thread[i] less than
8037 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8038 * pick a thread which has least completed command.
8039 */
8040
8041 mutex_enter(&item->mutex);
8042 if (item->len < mpt->m_doneq_thread_threshold) {
8043 t = i;
8044 mutex_exit(&item->mutex);
8045 break;
8046 }
8047 if (item->len < min) {
8048 min = item->len;
8049 t = i;
8050 }
8051 mutex_exit(&item->mutex);
8052 }
8053 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8054 mptsas_doneq_mv(mpt, t);
8055 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8056 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8057 }
8058
8059 /*
8060 * move the current global doneq to the doneq of thead[t]
8061 */
8062 static void
8063 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8064 {
8065 mptsas_cmd_t *cmd;
8066 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8067
8068 ASSERT(mutex_owned(&item->mutex));
8069 while ((cmd = mpt->m_doneq) != NULL) {
8070 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8071 mpt->m_donetail = &mpt->m_doneq;
8072 }
8073 cmd->cmd_linkp = NULL;
8074 *item->donetail = cmd;
8075 item->donetail = &cmd->cmd_linkp;
8076 mpt->m_doneq_len--;
8077 item->len++;
8078 }
8079 }
8080
8081 void
8082 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8083 {
8084 struct scsi_pkt *pkt = CMD2PKT(cmd);
8085
8086 /* Check all acc and dma handles */
8087 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8088 DDI_SUCCESS) ||
8089 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8090 DDI_SUCCESS) ||
8091 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8092 DDI_SUCCESS) ||
8093 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8094 DDI_SUCCESS) ||
8095 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8096 DDI_SUCCESS) ||
8097 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8098 DDI_SUCCESS) ||
8099 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8100 DDI_SUCCESS)) {
8101 ddi_fm_service_impact(mpt->m_dip,
8102 DDI_SERVICE_UNAFFECTED);
8103 ddi_fm_acc_err_clear(mpt->m_config_handle,
8104 DDI_FME_VER0);
8105 pkt->pkt_reason = CMD_TRAN_ERR;
8106 pkt->pkt_statistics = 0;
8107 }
8108 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8109 DDI_SUCCESS) ||
8110 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8111 DDI_SUCCESS) ||
8112 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8113 DDI_SUCCESS) ||
8114 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8115 DDI_SUCCESS) ||
8116 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8117 DDI_SUCCESS)) {
8118 ddi_fm_service_impact(mpt->m_dip,
8119 DDI_SERVICE_UNAFFECTED);
8120 pkt->pkt_reason = CMD_TRAN_ERR;
8121 pkt->pkt_statistics = 0;
8122 }
8123 if (cmd->cmd_dmahandle &&
8124 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8125 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8126 pkt->pkt_reason = CMD_TRAN_ERR;
8127 pkt->pkt_statistics = 0;
8128 }
8129 if ((cmd->cmd_extra_frames &&
8130 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8131 DDI_SUCCESS) ||
8132 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8133 DDI_SUCCESS)))) {
8134 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8135 pkt->pkt_reason = CMD_TRAN_ERR;
8136 pkt->pkt_statistics = 0;
8137 }
8138 if (cmd->cmd_arqhandle &&
8139 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) {
8140 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8141 pkt->pkt_reason = CMD_TRAN_ERR;
8142 pkt->pkt_statistics = 0;
8143 }
8144 if (cmd->cmd_ext_arqhandle &&
8145 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) {
8146 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8147 pkt->pkt_reason = CMD_TRAN_ERR;
8148 pkt->pkt_statistics = 0;
8149 }
8150 }
8151
8152 /*
8153 * These routines manipulate the queue of commands that
8154 * are waiting for their completion routines to be called.
8155 * The queue is usually in FIFO order but on an MP system
8156 * it's possible for the completion routines to get out
8157 * of order. If that's a problem you need to add a global
8158 * mutex around the code that calls the completion routine
8159 * in the interrupt handler.
8160 */
8161 static void
8162 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8163 {
8164 struct scsi_pkt *pkt = CMD2PKT(cmd);
8165
8166 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8167
8168 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8169 cmd->cmd_linkp = NULL;
8170 cmd->cmd_flags |= CFLAG_FINISHED;
8171 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8172
8173 mptsas_fma_check(mpt, cmd);
8174
8175 /*
8176 * only add scsi pkts that have completion routines to
8177 * the doneq. no intr cmds do not have callbacks.
8178 */
8179 if (pkt && (pkt->pkt_comp)) {
8180 *mpt->m_donetail = cmd;
8181 mpt->m_donetail = &cmd->cmd_linkp;
8182 mpt->m_doneq_len++;
8183 }
8184 }
8185
8186 static mptsas_cmd_t *
8187 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8188 {
8189 mptsas_cmd_t *cmd;
8190 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8191
8192 /* pop one off the done queue */
8193 if ((cmd = item->doneq) != NULL) {
8194 /* if the queue is now empty fix the tail pointer */
8195 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8196 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8197 item->donetail = &item->doneq;
8198 }
8199 cmd->cmd_linkp = NULL;
8200 item->len--;
8201 }
8202 return (cmd);
8203 }
8204
8205 static void
8206 mptsas_doneq_empty(mptsas_t *mpt)
8207 {
8208 if (mpt->m_doneq && !mpt->m_in_callback) {
8209 mptsas_cmd_t *cmd, *next;
8210 struct scsi_pkt *pkt;
8211
8212 mpt->m_in_callback = 1;
8213 cmd = mpt->m_doneq;
8214 mpt->m_doneq = NULL;
8215 mpt->m_donetail = &mpt->m_doneq;
8216 mpt->m_doneq_len = 0;
8217
8218 mutex_exit(&mpt->m_mutex);
8219 /*
8220 * run the completion routines of all the
8221 * completed commands
8222 */
8223 while (cmd != NULL) {
8224 next = cmd->cmd_linkp;
8225 cmd->cmd_linkp = NULL;
8226 /* run this command's completion routine */
8227 cmd->cmd_flags |= CFLAG_COMPLETED;
8228 pkt = CMD2PKT(cmd);
8229 mptsas_pkt_comp(pkt, cmd);
8230 cmd = next;
8231 }
8232 mutex_enter(&mpt->m_mutex);
8233 mpt->m_in_callback = 0;
8234 }
8235 }
8236
8237 /*
8238 * These routines manipulate the target's queue of pending requests
8239 */
8240 void
8241 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8242 {
8243 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8244 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8245 cmd->cmd_queued = TRUE;
8246 if (ptgt)
8247 ptgt->m_t_nwait++;
8248 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8249 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8250 mpt->m_waitqtail = &cmd->cmd_linkp;
8251 }
8252 mpt->m_waitq = cmd;
8253 } else {
8254 cmd->cmd_linkp = NULL;
8255 *(mpt->m_waitqtail) = cmd;
8256 mpt->m_waitqtail = &cmd->cmd_linkp;
8257 }
8258 }
8259
8260 static mptsas_cmd_t *
8261 mptsas_waitq_rm(mptsas_t *mpt)
8262 {
8263 mptsas_cmd_t *cmd;
8264 mptsas_target_t *ptgt;
8265 NDBG7(("mptsas_waitq_rm"));
8266
8267 MPTSAS_WAITQ_RM(mpt, cmd);
8268
8269 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8270 if (cmd) {
8271 ptgt = cmd->cmd_tgt_addr;
8272 if (ptgt) {
8273 ptgt->m_t_nwait--;
8274 ASSERT(ptgt->m_t_nwait >= 0);
8275 }
8276 }
8277 return (cmd);
8278 }
8279
8280 /*
8281 * remove specified cmd from the middle of the wait queue.
8282 */
8283 static void
8284 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8285 {
8286 mptsas_cmd_t *prevp = mpt->m_waitq;
8287 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8288
8289 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8290 (void *)mpt, (void *)cmd));
8291 if (ptgt) {
8292 ptgt->m_t_nwait--;
8293 ASSERT(ptgt->m_t_nwait >= 0);
8294 }
8295
8296 if (prevp == cmd) {
8297 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8298 mpt->m_waitqtail = &mpt->m_waitq;
8299
8300 cmd->cmd_linkp = NULL;
8301 cmd->cmd_queued = FALSE;
8302 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8303 (void *)mpt, (void *)cmd));
8304 return;
8305 }
8306
8307 while (prevp != NULL) {
8308 if (prevp->cmd_linkp == cmd) {
8309 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8310 mpt->m_waitqtail = &prevp->cmd_linkp;
8311
8312 cmd->cmd_linkp = NULL;
8313 cmd->cmd_queued = FALSE;
8314 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8315 (void *)mpt, (void *)cmd));
8316 return;
8317 }
8318 prevp = prevp->cmd_linkp;
8319 }
8320 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8321 }
8322
8323 static mptsas_cmd_t *
8324 mptsas_tx_waitq_rm(mptsas_t *mpt)
8325 {
8326 mptsas_cmd_t *cmd;
8327 NDBG7(("mptsas_tx_waitq_rm"));
8328
8329 MPTSAS_TX_WAITQ_RM(mpt, cmd);
8330
8331 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8332
8333 return (cmd);
8334 }
8335
8336 /*
8337 * remove specified cmd from the middle of the tx_waitq.
8338 */
8339 static void
8340 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8341 {
8342 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8343
8344 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8345 (void *)mpt, (void *)cmd));
8346
8347 if (prevp == cmd) {
8348 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8349 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8350
8351 cmd->cmd_linkp = NULL;
8352 cmd->cmd_queued = FALSE;
8353 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8354 (void *)mpt, (void *)cmd));
8355 return;
8356 }
8357
8358 while (prevp != NULL) {
8359 if (prevp->cmd_linkp == cmd) {
8360 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8361 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8362
8363 cmd->cmd_linkp = NULL;
8364 cmd->cmd_queued = FALSE;
8365 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8366 (void *)mpt, (void *)cmd));
8367 return;
8368 }
8369 prevp = prevp->cmd_linkp;
8370 }
8371 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8372 }
8373
8374 /*
8375 * device and bus reset handling
8376 *
8377 * Notes:
8378 * - RESET_ALL: reset the controller
8379 * - RESET_TARGET: reset the target specified in scsi_address
8380 */
8381 static int
8382 mptsas_scsi_reset(struct scsi_address *ap, int level)
8383 {
8384 mptsas_t *mpt = ADDR2MPT(ap);
8385 int rval;
8386 mptsas_tgt_private_t *tgt_private;
8387 mptsas_target_t *ptgt = NULL;
8388
8389 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8390 ptgt = tgt_private->t_private;
8391 if (ptgt == NULL) {
8392 return (FALSE);
8393 }
8394 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8395 level));
8396
8397 mutex_enter(&mpt->m_mutex);
8398 /*
8399 * if we are not in panic set up a reset delay for this target
8400 */
8401 if (!ddi_in_panic()) {
8402 mptsas_setup_bus_reset_delay(mpt);
8403 } else {
8404 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8405 }
8406 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8407 mutex_exit(&mpt->m_mutex);
8408
8409 /*
8410 * The transport layer expect to only see TRUE and
8411 * FALSE. Therefore, we will adjust the return value
8412 * if mptsas_do_scsi_reset returns FAILED.
8413 */
8414 if (rval == FAILED)
8415 rval = FALSE;
8416 return (rval);
8417 }
8418
8419 static int
8420 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
8421 {
8422 int rval = FALSE;
8423 uint8_t config, disk;
8424 mptsas_slots_t *slots = mpt->m_active;
8425
8426 ASSERT(mutex_owned(&mpt->m_mutex));
8427
8428 if (mptsas_debug_resets) {
8429 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
8430 devhdl);
8431 }
8432
8433 /*
8434 * Issue a Target Reset message to the target specified but not to a
8435 * disk making up a raid volume. Just look through the RAID config
8436 * Phys Disk list of DevHandles. If the target's DevHandle is in this
8437 * list, then don't reset this target.
8438 */
8439 for (config = 0; config < slots->m_num_raid_configs; config++) {
8440 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
8441 if (devhdl == slots->m_raidconfig[config].
8442 m_physdisk_devhdl[disk]) {
8443 return (TRUE);
8444 }
8445 }
8446 }
8447
8448 rval = mptsas_ioc_task_management(mpt,
8449 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
8450
8451 mptsas_doneq_empty(mpt);
8452 return (rval);
8453 }
8454
8455 static int
8456 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
8457 void (*callback)(caddr_t), caddr_t arg)
8458 {
8459 mptsas_t *mpt = ADDR2MPT(ap);
8460
8461 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
8462
8463 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
8464 &mpt->m_mutex, &mpt->m_reset_notify_listf));
8465 }
8466
8467 static int
8468 mptsas_get_name(struct scsi_device *sd, char *name, int len)
8469 {
8470 dev_info_t *lun_dip = NULL;
8471
8472 ASSERT(sd != NULL);
8473 ASSERT(name != NULL);
8474 lun_dip = sd->sd_dev;
8475 ASSERT(lun_dip != NULL);
8476
8477 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
8478 return (1);
8479 } else {
8480 return (0);
8481 }
8482 }
8483
8484 static int
8485 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
8486 {
8487 return (mptsas_get_name(sd, name, len));
8488 }
8489
8490 void
8491 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
8492 {
8493
8494 NDBG25(("mptsas_set_throttle: throttle=%x", what));
8495
8496 /*
8497 * if the bus is draining/quiesced, no changes to the throttles
8498 * are allowed. Not allowing change of throttles during draining
8499 * limits error recovery but will reduce draining time
8500 *
8501 * all throttles should have been set to HOLD_THROTTLE
8502 */
8503 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
8504 return;
8505 }
8506
8507 if (what == HOLD_THROTTLE) {
8508 ptgt->m_t_throttle = HOLD_THROTTLE;
8509 } else if (ptgt->m_reset_delay == 0) {
8510 ptgt->m_t_throttle = what;
8511 }
8512 }
8513
8514 /*
8515 * Clean up from a device reset.
8516 * For the case of target reset, this function clears the waitq of all
8517 * commands for a particular target. For the case of abort task set, this
8518 * function clears the waitq of all commonds for a particular target/lun.
8519 */
8520 static void
8521 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
8522 {
8523 mptsas_slots_t *slots = mpt->m_active;
8524 mptsas_cmd_t *cmd, *next_cmd;
8525 int slot;
8526 uchar_t reason;
8527 uint_t stat;
8528
8529 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
8530
8531 /*
8532 * Make sure the I/O Controller has flushed all cmds
8533 * that are associated with this target for a target reset
8534 * and target/lun for abort task set.
8535 * Account for TM requests, which use the last SMID.
8536 */
8537 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8538 if ((cmd = slots->m_slot[slot]) == NULL)
8539 continue;
8540 reason = CMD_RESET;
8541 stat = STAT_DEV_RESET;
8542 switch (tasktype) {
8543 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8544 if (Tgt(cmd) == target) {
8545 NDBG25(("mptsas_flush_target discovered non-"
8546 "NULL cmd in slot %d, tasktype 0x%x", slot,
8547 tasktype));
8548 mptsas_dump_cmd(mpt, cmd);
8549 mptsas_remove_cmd(mpt, cmd);
8550 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
8551 mptsas_doneq_add(mpt, cmd);
8552 }
8553 break;
8554 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8555 reason = CMD_ABORTED;
8556 stat = STAT_ABORTED;
8557 /*FALLTHROUGH*/
8558 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8559 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8560
8561 NDBG25(("mptsas_flush_target discovered non-"
8562 "NULL cmd in slot %d, tasktype 0x%x", slot,
8563 tasktype));
8564 mptsas_dump_cmd(mpt, cmd);
8565 mptsas_remove_cmd(mpt, cmd);
8566 mptsas_set_pkt_reason(mpt, cmd, reason,
8567 stat);
8568 mptsas_doneq_add(mpt, cmd);
8569 }
8570 break;
8571 default:
8572 break;
8573 }
8574 }
8575
8576 /*
8577 * Flush the waitq and tx_waitq of this target's cmds
8578 */
8579 cmd = mpt->m_waitq;
8580
8581 reason = CMD_RESET;
8582 stat = STAT_DEV_RESET;
8583
8584 switch (tasktype) {
8585 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
8586 while (cmd != NULL) {
8587 next_cmd = cmd->cmd_linkp;
8588 if (Tgt(cmd) == target) {
8589 mptsas_waitq_delete(mpt, cmd);
8590 mptsas_set_pkt_reason(mpt, cmd,
8591 reason, stat);
8592 mptsas_doneq_add(mpt, cmd);
8593 }
8594 cmd = next_cmd;
8595 }
8596 mutex_enter(&mpt->m_tx_waitq_mutex);
8597 cmd = mpt->m_tx_waitq;
8598 while (cmd != NULL) {
8599 next_cmd = cmd->cmd_linkp;
8600 if (Tgt(cmd) == target) {
8601 mptsas_tx_waitq_delete(mpt, cmd);
8602 mutex_exit(&mpt->m_tx_waitq_mutex);
8603 mptsas_set_pkt_reason(mpt, cmd,
8604 reason, stat);
8605 mptsas_doneq_add(mpt, cmd);
8606 mutex_enter(&mpt->m_tx_waitq_mutex);
8607 }
8608 cmd = next_cmd;
8609 }
8610 mutex_exit(&mpt->m_tx_waitq_mutex);
8611 break;
8612 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
8613 reason = CMD_ABORTED;
8614 stat = STAT_ABORTED;
8615 /*FALLTHROUGH*/
8616 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
8617 while (cmd != NULL) {
8618 next_cmd = cmd->cmd_linkp;
8619 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8620 mptsas_waitq_delete(mpt, cmd);
8621 mptsas_set_pkt_reason(mpt, cmd,
8622 reason, stat);
8623 mptsas_doneq_add(mpt, cmd);
8624 }
8625 cmd = next_cmd;
8626 }
8627 mutex_enter(&mpt->m_tx_waitq_mutex);
8628 cmd = mpt->m_tx_waitq;
8629 while (cmd != NULL) {
8630 next_cmd = cmd->cmd_linkp;
8631 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
8632 mptsas_tx_waitq_delete(mpt, cmd);
8633 mutex_exit(&mpt->m_tx_waitq_mutex);
8634 mptsas_set_pkt_reason(mpt, cmd,
8635 reason, stat);
8636 mptsas_doneq_add(mpt, cmd);
8637 mutex_enter(&mpt->m_tx_waitq_mutex);
8638 }
8639 cmd = next_cmd;
8640 }
8641 mutex_exit(&mpt->m_tx_waitq_mutex);
8642 break;
8643 default:
8644 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
8645 tasktype);
8646 break;
8647 }
8648 }
8649
8650 /*
8651 * Clean up hba state, abort all outstanding command and commands in waitq
8652 * reset timeout of all targets.
8653 */
8654 static void
8655 mptsas_flush_hba(mptsas_t *mpt)
8656 {
8657 mptsas_slots_t *slots = mpt->m_active;
8658 mptsas_cmd_t *cmd;
8659 int slot;
8660
8661 NDBG25(("mptsas_flush_hba"));
8662
8663 /*
8664 * The I/O Controller should have already sent back
8665 * all commands via the scsi I/O reply frame. Make
8666 * sure all commands have been flushed.
8667 * Account for TM request, which use the last SMID.
8668 */
8669 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) {
8670 if ((cmd = slots->m_slot[slot]) == NULL)
8671 continue;
8672
8673 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8674 /*
8675 * Need to make sure to tell everyone that might be
8676 * waiting on this command that it's going to fail. If
8677 * we get here, this command will never timeout because
8678 * the active command table is going to be re-allocated,
8679 * so there will be nothing to check against a time out.
8680 * Instead, mark the command as failed due to reset.
8681 */
8682 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
8683 STAT_BUS_RESET);
8684 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8685 (cmd->cmd_flags & CFLAG_CONFIG) ||
8686 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8687 cmd->cmd_flags |= CFLAG_FINISHED;
8688 cv_broadcast(&mpt->m_passthru_cv);
8689 cv_broadcast(&mpt->m_config_cv);
8690 cv_broadcast(&mpt->m_fw_diag_cv);
8691 }
8692 continue;
8693 }
8694
8695 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
8696 slot));
8697 mptsas_dump_cmd(mpt, cmd);
8698
8699 mptsas_remove_cmd(mpt, cmd);
8700 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8701 mptsas_doneq_add(mpt, cmd);
8702 }
8703
8704 /*
8705 * Flush the waitq.
8706 */
8707 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
8708 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8709 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
8710 (cmd->cmd_flags & CFLAG_CONFIG) ||
8711 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
8712 cmd->cmd_flags |= CFLAG_FINISHED;
8713 cv_broadcast(&mpt->m_passthru_cv);
8714 cv_broadcast(&mpt->m_config_cv);
8715 cv_broadcast(&mpt->m_fw_diag_cv);
8716 } else {
8717 mptsas_doneq_add(mpt, cmd);
8718 }
8719 }
8720
8721 /*
8722 * Flush the tx_waitq
8723 */
8724 mutex_enter(&mpt->m_tx_waitq_mutex);
8725 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
8726 mutex_exit(&mpt->m_tx_waitq_mutex);
8727 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
8728 mptsas_doneq_add(mpt, cmd);
8729 mutex_enter(&mpt->m_tx_waitq_mutex);
8730 }
8731 mutex_exit(&mpt->m_tx_waitq_mutex);
8732
8733 /*
8734 * Drain the taskqs prior to reallocating resources.
8735 */
8736 mutex_exit(&mpt->m_mutex);
8737 ddi_taskq_wait(mpt->m_event_taskq);
8738 ddi_taskq_wait(mpt->m_dr_taskq);
8739 mutex_enter(&mpt->m_mutex);
8740 }
8741
8742 /*
8743 * set pkt_reason and OR in pkt_statistics flag
8744 */
8745 static void
8746 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
8747 uint_t stat)
8748 {
8749 #ifndef __lock_lint
8750 _NOTE(ARGUNUSED(mpt))
8751 #endif
8752
8753 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
8754 (void *)cmd, reason, stat));
8755
8756 if (cmd) {
8757 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
8758 cmd->cmd_pkt->pkt_reason = reason;
8759 }
8760 cmd->cmd_pkt->pkt_statistics |= stat;
8761 }
8762 }
8763
8764 static void
8765 mptsas_start_watch_reset_delay()
8766 {
8767 NDBG22(("mptsas_start_watch_reset_delay"));
8768
8769 mutex_enter(&mptsas_global_mutex);
8770 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
8771 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
8772 drv_usectohz((clock_t)
8773 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
8774 ASSERT(mptsas_reset_watch != NULL);
8775 }
8776 mutex_exit(&mptsas_global_mutex);
8777 }
8778
8779 static void
8780 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
8781 {
8782 mptsas_target_t *ptgt = NULL;
8783
8784 NDBG22(("mptsas_setup_bus_reset_delay"));
8785 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8786 MPTSAS_HASH_FIRST);
8787 while (ptgt != NULL) {
8788 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
8789 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
8790
8791 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8792 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8793 }
8794
8795 mptsas_start_watch_reset_delay();
8796 }
8797
8798 /*
8799 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
8800 * mpt instance for active reset delays
8801 */
8802 static void
8803 mptsas_watch_reset_delay(void *arg)
8804 {
8805 #ifndef __lock_lint
8806 _NOTE(ARGUNUSED(arg))
8807 #endif
8808
8809 mptsas_t *mpt;
8810 int not_done = 0;
8811
8812 NDBG22(("mptsas_watch_reset_delay"));
8813
8814 mutex_enter(&mptsas_global_mutex);
8815 mptsas_reset_watch = 0;
8816 mutex_exit(&mptsas_global_mutex);
8817 rw_enter(&mptsas_global_rwlock, RW_READER);
8818 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
8819 if (mpt->m_tran == 0) {
8820 continue;
8821 }
8822 mutex_enter(&mpt->m_mutex);
8823 not_done += mptsas_watch_reset_delay_subr(mpt);
8824 mutex_exit(&mpt->m_mutex);
8825 }
8826 rw_exit(&mptsas_global_rwlock);
8827
8828 if (not_done) {
8829 mptsas_start_watch_reset_delay();
8830 }
8831 }
8832
8833 static int
8834 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
8835 {
8836 int done = 0;
8837 int restart = 0;
8838 mptsas_target_t *ptgt = NULL;
8839
8840 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
8841
8842 ASSERT(mutex_owned(&mpt->m_mutex));
8843
8844 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
8845 MPTSAS_HASH_FIRST);
8846 while (ptgt != NULL) {
8847 if (ptgt->m_reset_delay != 0) {
8848 ptgt->m_reset_delay -=
8849 MPTSAS_WATCH_RESET_DELAY_TICK;
8850 if (ptgt->m_reset_delay <= 0) {
8851 ptgt->m_reset_delay = 0;
8852 mptsas_set_throttle(mpt, ptgt,
8853 MAX_THROTTLE);
8854 restart++;
8855 } else {
8856 done = -1;
8857 }
8858 }
8859
8860 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
8861 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
8862 }
8863
8864 if (restart > 0) {
8865 mptsas_restart_hba(mpt);
8866 }
8867 return (done);
8868 }
8869
8870 #ifdef MPTSAS_TEST
8871 static void
8872 mptsas_test_reset(mptsas_t *mpt, int target)
8873 {
8874 mptsas_target_t *ptgt = NULL;
8875
8876 if (mptsas_rtest == target) {
8877 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
8878 mptsas_rtest = -1;
8879 }
8880 if (mptsas_rtest == -1) {
8881 NDBG22(("mptsas_test_reset success"));
8882 }
8883 }
8884 }
8885 #endif
8886
8887 /*
8888 * abort handling:
8889 *
8890 * Notes:
8891 * - if pkt is not NULL, abort just that command
8892 * - if pkt is NULL, abort all outstanding commands for target
8893 */
8894 static int
8895 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
8896 {
8897 mptsas_t *mpt = ADDR2MPT(ap);
8898 int rval;
8899 mptsas_tgt_private_t *tgt_private;
8900 int target, lun;
8901
8902 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
8903 tran_tgt_private;
8904 ASSERT(tgt_private != NULL);
8905 target = tgt_private->t_private->m_devhdl;
8906 lun = tgt_private->t_lun;
8907
8908 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
8909
8910 mutex_enter(&mpt->m_mutex);
8911 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
8912 mutex_exit(&mpt->m_mutex);
8913 return (rval);
8914 }
8915
8916 static int
8917 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
8918 {
8919 mptsas_cmd_t *sp = NULL;
8920 mptsas_slots_t *slots = mpt->m_active;
8921 int rval = FALSE;
8922
8923 ASSERT(mutex_owned(&mpt->m_mutex));
8924
8925 /*
8926 * Abort the command pkt on the target/lun in ap. If pkt is
8927 * NULL, abort all outstanding commands on that target/lun.
8928 * If you can abort them, return 1, else return 0.
8929 * Each packet that's aborted should be sent back to the target
8930 * driver through the callback routine, with pkt_reason set to
8931 * CMD_ABORTED.
8932 *
8933 * abort cmd pkt on HBA hardware; clean out of outstanding
8934 * command lists, etc.
8935 */
8936 if (pkt != NULL) {
8937 /* abort the specified packet */
8938 sp = PKT2CMD(pkt);
8939
8940 if (sp->cmd_queued) {
8941 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
8942 (void *)sp));
8943 mptsas_waitq_delete(mpt, sp);
8944 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
8945 STAT_ABORTED);
8946 mptsas_doneq_add(mpt, sp);
8947 rval = TRUE;
8948 goto done;
8949 }
8950
8951 /*
8952 * Have mpt firmware abort this command
8953 */
8954
8955 if (slots->m_slot[sp->cmd_slot] != NULL) {
8956 rval = mptsas_ioc_task_management(mpt,
8957 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
8958 lun, NULL, 0, 0);
8959
8960 /*
8961 * The transport layer expects only TRUE and FALSE.
8962 * Therefore, if mptsas_ioc_task_management returns
8963 * FAILED we will return FALSE.
8964 */
8965 if (rval == FAILED)
8966 rval = FALSE;
8967 goto done;
8968 }
8969 }
8970
8971 /*
8972 * If pkt is NULL then abort task set
8973 */
8974 rval = mptsas_ioc_task_management(mpt,
8975 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
8976
8977 /*
8978 * The transport layer expects only TRUE and FALSE.
8979 * Therefore, if mptsas_ioc_task_management returns
8980 * FAILED we will return FALSE.
8981 */
8982 if (rval == FAILED)
8983 rval = FALSE;
8984
8985 #ifdef MPTSAS_TEST
8986 if (rval && mptsas_test_stop) {
8987 debug_enter("mptsas_do_scsi_abort");
8988 }
8989 #endif
8990
8991 done:
8992 mptsas_doneq_empty(mpt);
8993 return (rval);
8994 }
8995
8996 /*
8997 * capability handling:
8998 * (*tran_getcap). Get the capability named, and return its value.
8999 */
9000 static int
9001 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9002 {
9003 mptsas_t *mpt = ADDR2MPT(ap);
9004 int ckey;
9005 int rval = FALSE;
9006
9007 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9008 ap->a_target, cap, tgtonly));
9009
9010 mutex_enter(&mpt->m_mutex);
9011
9012 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9013 mutex_exit(&mpt->m_mutex);
9014 return (UNDEFINED);
9015 }
9016
9017 switch (ckey) {
9018 case SCSI_CAP_DMA_MAX:
9019 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9020 break;
9021 case SCSI_CAP_ARQ:
9022 rval = TRUE;
9023 break;
9024 case SCSI_CAP_MSG_OUT:
9025 case SCSI_CAP_PARITY:
9026 case SCSI_CAP_UNTAGGED_QING:
9027 rval = TRUE;
9028 break;
9029 case SCSI_CAP_TAGGED_QING:
9030 rval = TRUE;
9031 break;
9032 case SCSI_CAP_RESET_NOTIFICATION:
9033 rval = TRUE;
9034 break;
9035 case SCSI_CAP_LINKED_CMDS:
9036 rval = FALSE;
9037 break;
9038 case SCSI_CAP_QFULL_RETRIES:
9039 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9040 tran_tgt_private))->t_private->m_qfull_retries;
9041 break;
9042 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9043 rval = drv_hztousec(((mptsas_tgt_private_t *)
9044 (ap->a_hba_tran->tran_tgt_private))->
9045 t_private->m_qfull_retry_interval) / 1000;
9046 break;
9047 case SCSI_CAP_CDB_LEN:
9048 rval = CDB_GROUP4;
9049 break;
9050 case SCSI_CAP_INTERCONNECT_TYPE:
9051 rval = INTERCONNECT_SAS;
9052 break;
9053 case SCSI_CAP_TRAN_LAYER_RETRIES:
9054 if (mpt->m_ioc_capabilities &
9055 MPI2_IOCFACTS_CAPABILITY_TLR)
9056 rval = TRUE;
9057 else
9058 rval = FALSE;
9059 break;
9060 default:
9061 rval = UNDEFINED;
9062 break;
9063 }
9064
9065 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9066
9067 mutex_exit(&mpt->m_mutex);
9068 return (rval);
9069 }
9070
9071 /*
9072 * (*tran_setcap). Set the capability named to the value given.
9073 */
9074 static int
9075 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9076 {
9077 mptsas_t *mpt = ADDR2MPT(ap);
9078 int ckey;
9079 int rval = FALSE;
9080
9081 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9082 ap->a_target, cap, value, tgtonly));
9083
9084 if (!tgtonly) {
9085 return (rval);
9086 }
9087
9088 mutex_enter(&mpt->m_mutex);
9089
9090 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9091 mutex_exit(&mpt->m_mutex);
9092 return (UNDEFINED);
9093 }
9094
9095 switch (ckey) {
9096 case SCSI_CAP_DMA_MAX:
9097 case SCSI_CAP_MSG_OUT:
9098 case SCSI_CAP_PARITY:
9099 case SCSI_CAP_INITIATOR_ID:
9100 case SCSI_CAP_LINKED_CMDS:
9101 case SCSI_CAP_UNTAGGED_QING:
9102 case SCSI_CAP_RESET_NOTIFICATION:
9103 /*
9104 * None of these are settable via
9105 * the capability interface.
9106 */
9107 break;
9108 case SCSI_CAP_ARQ:
9109 /*
9110 * We cannot turn off arq so return false if asked to
9111 */
9112 if (value) {
9113 rval = TRUE;
9114 } else {
9115 rval = FALSE;
9116 }
9117 break;
9118 case SCSI_CAP_TAGGED_QING:
9119 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9120 (ap->a_hba_tran->tran_tgt_private))->t_private,
9121 MAX_THROTTLE);
9122 rval = TRUE;
9123 break;
9124 case SCSI_CAP_QFULL_RETRIES:
9125 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9126 t_private->m_qfull_retries = (uchar_t)value;
9127 rval = TRUE;
9128 break;
9129 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9130 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9131 t_private->m_qfull_retry_interval =
9132 drv_usectohz(value * 1000);
9133 rval = TRUE;
9134 break;
9135 default:
9136 rval = UNDEFINED;
9137 break;
9138 }
9139 mutex_exit(&mpt->m_mutex);
9140 return (rval);
9141 }
9142
9143 /*
9144 * Utility routine for mptsas_ifsetcap/ifgetcap
9145 */
9146 /*ARGSUSED*/
9147 static int
9148 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9149 {
9150 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9151
9152 if (!cap)
9153 return (FALSE);
9154
9155 *cidxp = scsi_hba_lookup_capstr(cap);
9156 return (TRUE);
9157 }
9158
9159 static int
9160 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9161 {
9162 mptsas_slots_t *old_active = mpt->m_active;
9163 mptsas_slots_t *new_active;
9164 size_t size;
9165 int rval = -1, i;
9166
9167 /*
9168 * if there are active commands, then we cannot
9169 * change size of active slots array.
9170 */
9171 ASSERT(mpt->m_ncmds == 0);
9172
9173 size = MPTSAS_SLOTS_SIZE(mpt);
9174 new_active = kmem_zalloc(size, flag);
9175 if (new_active == NULL) {
9176 NDBG1(("new active alloc failed"));
9177 return (rval);
9178 }
9179 /*
9180 * Since SMID 0 is reserved and the TM slot is reserved, the
9181 * number of slots that can be used at any one time is
9182 * m_max_requests - 2.
9183 */
9184 new_active->m_n_slots = (mpt->m_max_requests - 2);
9185 new_active->m_size = size;
9186 new_active->m_tags = 1;
9187 if (old_active) {
9188 new_active->m_tgttbl = old_active->m_tgttbl;
9189 new_active->m_smptbl = old_active->m_smptbl;
9190 new_active->m_num_raid_configs =
9191 old_active->m_num_raid_configs;
9192 for (i = 0; i < new_active->m_num_raid_configs; i++) {
9193 new_active->m_raidconfig[i] =
9194 old_active->m_raidconfig[i];
9195 }
9196 mptsas_free_active_slots(mpt);
9197 }
9198 mpt->m_active = new_active;
9199 rval = 0;
9200
9201 return (rval);
9202 }
9203
9204 static void
9205 mptsas_free_active_slots(mptsas_t *mpt)
9206 {
9207 mptsas_slots_t *active = mpt->m_active;
9208 size_t size;
9209
9210 if (active == NULL)
9211 return;
9212 size = active->m_size;
9213 kmem_free(active, size);
9214 mpt->m_active = NULL;
9215 }
9216
9217 /*
9218 * Error logging, printing, and debug print routines.
9219 */
9220 static char *mptsas_label = "mpt_sas";
9221
9222 /*PRINTFLIKE3*/
9223 void
9224 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9225 {
9226 dev_info_t *dev;
9227 va_list ap;
9228
9229 if (mpt) {
9230 dev = mpt->m_dip;
9231 } else {
9232 dev = 0;
9233 }
9234
9235 mutex_enter(&mptsas_log_mutex);
9236
9237 va_start(ap, fmt);
9238 (void) vsprintf(mptsas_log_buf, fmt, ap);
9239 va_end(ap);
9240
9241 if (level == CE_CONT) {
9242 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9243 } else {
9244 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9245 }
9246
9247 mutex_exit(&mptsas_log_mutex);
9248 }
9249
9250 #ifdef MPTSAS_DEBUG
9251 /*PRINTFLIKE1*/
9252 void
9253 mptsas_printf(char *fmt, ...)
9254 {
9255 dev_info_t *dev = 0;
9256 va_list ap;
9257
9258 mutex_enter(&mptsas_log_mutex);
9259
9260 va_start(ap, fmt);
9261 (void) vsprintf(mptsas_log_buf, fmt, ap);
9262 va_end(ap);
9263
9264 #ifdef PROM_PRINTF
9265 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9266 #else
9267 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf);
9268 #endif
9269 mutex_exit(&mptsas_log_mutex);
9270 }
9271 #endif
9272
9273 /*
9274 * timeout handling
9275 */
9276 static void
9277 mptsas_watch(void *arg)
9278 {
9279 #ifndef __lock_lint
9280 _NOTE(ARGUNUSED(arg))
9281 #endif
9282
9283 mptsas_t *mpt;
9284 uint32_t doorbell;
9285
9286 NDBG30(("mptsas_watch"));
9287
9288 rw_enter(&mptsas_global_rwlock, RW_READER);
9289 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9290
9291 mutex_enter(&mpt->m_mutex);
9292
9293 /* Skip device if not powered on */
9294 if (mpt->m_options & MPTSAS_OPT_PM) {
9295 if (mpt->m_power_level == PM_LEVEL_D0) {
9296 (void) pm_busy_component(mpt->m_dip, 0);
9297 mpt->m_busy = 1;
9298 } else {
9299 mutex_exit(&mpt->m_mutex);
9300 continue;
9301 }
9302 }
9303
9304 /*
9305 * Check if controller is in a FAULT state. If so, reset it.
9306 */
9307 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9308 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9309 doorbell &= MPI2_DOORBELL_DATA_MASK;
9310 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9311 "code: %04x", doorbell);
9312 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9313 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9314 mptsas_log(mpt, CE_WARN, "Reset failed"
9315 "after fault was detected");
9316 }
9317 }
9318
9319 /*
9320 * For now, always call mptsas_watchsubr.
9321 */
9322 mptsas_watchsubr(mpt);
9323
9324 if (mpt->m_options & MPTSAS_OPT_PM) {
9325 mpt->m_busy = 0;
9326 (void) pm_idle_component(mpt->m_dip, 0);
9327 }
9328
9329 mutex_exit(&mpt->m_mutex);
9330 }
9331 rw_exit(&mptsas_global_rwlock);
9332
9333 mutex_enter(&mptsas_global_mutex);
9334 if (mptsas_timeouts_enabled)
9335 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9336 mutex_exit(&mptsas_global_mutex);
9337 }
9338
9339 static void
9340 mptsas_watchsubr(mptsas_t *mpt)
9341 {
9342 int i;
9343 mptsas_cmd_t *cmd;
9344 mptsas_target_t *ptgt = NULL;
9345
9346 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
9347
9348 #ifdef MPTSAS_TEST
9349 if (mptsas_enable_untagged) {
9350 mptsas_test_untagged++;
9351 }
9352 #endif
9353
9354 /*
9355 * Check for commands stuck in active slot
9356 * Account for TM requests, which use the last SMID.
9357 */
9358 for (i = 0; i <= mpt->m_active->m_n_slots; i++) {
9359 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
9360 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
9361 cmd->cmd_active_timeout -=
9362 mptsas_scsi_watchdog_tick;
9363 if (cmd->cmd_active_timeout <= 0) {
9364 /*
9365 * There seems to be a command stuck
9366 * in the active slot. Drain throttle.
9367 */
9368 mptsas_set_throttle(mpt,
9369 cmd->cmd_tgt_addr,
9370 DRAIN_THROTTLE);
9371 }
9372 }
9373 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9374 (cmd->cmd_flags & CFLAG_CONFIG) ||
9375 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9376 cmd->cmd_active_timeout -=
9377 mptsas_scsi_watchdog_tick;
9378 if (cmd->cmd_active_timeout <= 0) {
9379 /*
9380 * passthrough command timeout
9381 */
9382 cmd->cmd_flags |= (CFLAG_FINISHED |
9383 CFLAG_TIMEOUT);
9384 cv_broadcast(&mpt->m_passthru_cv);
9385 cv_broadcast(&mpt->m_config_cv);
9386 cv_broadcast(&mpt->m_fw_diag_cv);
9387 }
9388 }
9389 }
9390 }
9391
9392 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9393 MPTSAS_HASH_FIRST);
9394 while (ptgt != NULL) {
9395 /*
9396 * If we were draining due to a qfull condition,
9397 * go back to full throttle.
9398 */
9399 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9400 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9401 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9402 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9403 mptsas_restart_hba(mpt);
9404 }
9405
9406 if ((ptgt->m_t_ncmds > 0) &&
9407 (ptgt->m_timebase)) {
9408
9409 if (ptgt->m_timebase <=
9410 mptsas_scsi_watchdog_tick) {
9411 ptgt->m_timebase +=
9412 mptsas_scsi_watchdog_tick;
9413 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9414 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9415 continue;
9416 }
9417
9418 ptgt->m_timeout -= mptsas_scsi_watchdog_tick;
9419
9420 if (ptgt->m_timeout < 0) {
9421 mptsas_cmd_timeout(mpt, ptgt->m_devhdl);
9422 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9423 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9424 continue;
9425 }
9426
9427 if ((ptgt->m_timeout) <=
9428 mptsas_scsi_watchdog_tick) {
9429 NDBG23(("pending timeout"));
9430 mptsas_set_throttle(mpt, ptgt,
9431 DRAIN_THROTTLE);
9432 }
9433 }
9434
9435 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9436 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9437 }
9438 }
9439
9440 /*
9441 * timeout recovery
9442 */
9443 static void
9444 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl)
9445 {
9446
9447 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
9448 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
9449 "Target %d", devhdl);
9450
9451 /*
9452 * If the current target is not the target passed in,
9453 * try to reset that target.
9454 */
9455 NDBG29(("mptsas_cmd_timeout: device reset"));
9456 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
9457 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
9458 "recovery failed!", devhdl);
9459 }
9460 }
9461
9462 /*
9463 * Device / Hotplug control
9464 */
9465 static int
9466 mptsas_scsi_quiesce(dev_info_t *dip)
9467 {
9468 mptsas_t *mpt;
9469 scsi_hba_tran_t *tran;
9470
9471 tran = ddi_get_driver_private(dip);
9472 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9473 return (-1);
9474
9475 return (mptsas_quiesce_bus(mpt));
9476 }
9477
9478 static int
9479 mptsas_scsi_unquiesce(dev_info_t *dip)
9480 {
9481 mptsas_t *mpt;
9482 scsi_hba_tran_t *tran;
9483
9484 tran = ddi_get_driver_private(dip);
9485 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
9486 return (-1);
9487
9488 return (mptsas_unquiesce_bus(mpt));
9489 }
9490
9491 static int
9492 mptsas_quiesce_bus(mptsas_t *mpt)
9493 {
9494 mptsas_target_t *ptgt = NULL;
9495
9496 NDBG28(("mptsas_quiesce_bus"));
9497 mutex_enter(&mpt->m_mutex);
9498
9499 /* Set all the throttles to zero */
9500 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9501 MPTSAS_HASH_FIRST);
9502 while (ptgt != NULL) {
9503 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9504
9505 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9506 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9507 }
9508
9509 /* If there are any outstanding commands in the queue */
9510 if (mpt->m_ncmds) {
9511 mpt->m_softstate |= MPTSAS_SS_DRAINING;
9512 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9513 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
9514 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
9515 /*
9516 * Quiesce has been interrupted
9517 */
9518 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9519 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9520 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9521 while (ptgt != NULL) {
9522 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9523
9524 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9525 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9526 }
9527 mptsas_restart_hba(mpt);
9528 if (mpt->m_quiesce_timeid != 0) {
9529 timeout_id_t tid = mpt->m_quiesce_timeid;
9530 mpt->m_quiesce_timeid = 0;
9531 mutex_exit(&mpt->m_mutex);
9532 (void) untimeout(tid);
9533 return (-1);
9534 }
9535 mutex_exit(&mpt->m_mutex);
9536 return (-1);
9537 } else {
9538 /* Bus has been quiesced */
9539 ASSERT(mpt->m_quiesce_timeid == 0);
9540 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
9541 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
9542 mutex_exit(&mpt->m_mutex);
9543 return (0);
9544 }
9545 }
9546 /* Bus was not busy - QUIESCED */
9547 mutex_exit(&mpt->m_mutex);
9548
9549 return (0);
9550 }
9551
9552 static int
9553 mptsas_unquiesce_bus(mptsas_t *mpt)
9554 {
9555 mptsas_target_t *ptgt = NULL;
9556
9557 NDBG28(("mptsas_unquiesce_bus"));
9558 mutex_enter(&mpt->m_mutex);
9559 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
9560 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
9561 MPTSAS_HASH_FIRST);
9562 while (ptgt != NULL) {
9563 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9564
9565 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9566 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9567 }
9568 mptsas_restart_hba(mpt);
9569 mutex_exit(&mpt->m_mutex);
9570 return (0);
9571 }
9572
9573 static void
9574 mptsas_ncmds_checkdrain(void *arg)
9575 {
9576 mptsas_t *mpt = arg;
9577 mptsas_target_t *ptgt = NULL;
9578
9579 mutex_enter(&mpt->m_mutex);
9580 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
9581 mpt->m_quiesce_timeid = 0;
9582 if (mpt->m_ncmds == 0) {
9583 /* Command queue has been drained */
9584 cv_signal(&mpt->m_cv);
9585 } else {
9586 /*
9587 * The throttle may have been reset because
9588 * of a SCSI bus reset
9589 */
9590 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9591 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST);
9592 while (ptgt != NULL) {
9593 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9594
9595 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
9596 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
9597 }
9598
9599 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
9600 mpt, (MPTSAS_QUIESCE_TIMEOUT *
9601 drv_usectohz(1000000)));
9602 }
9603 }
9604 mutex_exit(&mpt->m_mutex);
9605 }
9606
9607 /*ARGSUSED*/
9608 static void
9609 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
9610 {
9611 int i;
9612 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
9613 char buf[128];
9614
9615 buf[0] = '\0';
9616 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
9617 Tgt(cmd), Lun(cmd)));
9618 (void) sprintf(&buf[0], "\tcdb=[");
9619 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
9620 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
9621 }
9622 (void) sprintf(&buf[strlen(buf)], " ]");
9623 NDBG25(("?%s\n", buf));
9624 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
9625 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
9626 cmd->cmd_pkt->pkt_state));
9627 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
9628 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
9629 }
9630
9631 static void
9632 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
9633 {
9634 caddr_t memp;
9635 pMPI2RequestHeader_t request_hdrp;
9636 struct scsi_pkt *pkt = cmd->cmd_pkt;
9637 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
9638 uint32_t request_size, data_size, dataout_size;
9639 uint32_t direction;
9640 ddi_dma_cookie_t data_cookie;
9641 ddi_dma_cookie_t dataout_cookie;
9642 uint32_t request_desc_low, request_desc_high = 0;
9643 uint32_t i, sense_bufp;
9644 uint8_t desc_type;
9645 uint8_t *request, function;
9646 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
9647 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
9648
9649 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
9650
9651 request = pt->request;
9652 direction = pt->direction;
9653 request_size = pt->request_size;
9654 data_size = pt->data_size;
9655 dataout_size = pt->dataout_size;
9656 data_cookie = pt->data_cookie;
9657 dataout_cookie = pt->dataout_cookie;
9658
9659 /*
9660 * Store the passthrough message in memory location
9661 * corresponding to our slot number
9662 */
9663 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot);
9664 request_hdrp = (pMPI2RequestHeader_t)memp;
9665 bzero(memp, mpt->m_req_frame_size);
9666
9667 for (i = 0; i < request_size; i++) {
9668 bcopy(request + i, memp + i, 1);
9669 }
9670
9671 if (data_size || dataout_size) {
9672 pMpi2SGESimple64_t sgep;
9673 uint32_t sge_flags;
9674
9675 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp +
9676 request_size);
9677 if (dataout_size) {
9678
9679 sge_flags = dataout_size |
9680 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9681 MPI2_SGE_FLAGS_END_OF_BUFFER |
9682 MPI2_SGE_FLAGS_HOST_TO_IOC |
9683 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9684 MPI2_SGE_FLAGS_SHIFT);
9685 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
9686 ddi_put32(acc_hdl, &sgep->Address.Low,
9687 (uint32_t)(dataout_cookie.dmac_laddress &
9688 0xffffffffull));
9689 ddi_put32(acc_hdl, &sgep->Address.High,
9690 (uint32_t)(dataout_cookie.dmac_laddress
9691 >> 32));
9692 sgep++;
9693 }
9694 sge_flags = data_size;
9695 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
9696 MPI2_SGE_FLAGS_LAST_ELEMENT |
9697 MPI2_SGE_FLAGS_END_OF_BUFFER |
9698 MPI2_SGE_FLAGS_END_OF_LIST |
9699 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
9700 MPI2_SGE_FLAGS_SHIFT);
9701 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9702 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
9703 MPI2_SGE_FLAGS_SHIFT);
9704 } else {
9705 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
9706 MPI2_SGE_FLAGS_SHIFT);
9707 }
9708 ddi_put32(acc_hdl, &sgep->FlagsLength,
9709 sge_flags);
9710 ddi_put32(acc_hdl, &sgep->Address.Low,
9711 (uint32_t)(data_cookie.dmac_laddress &
9712 0xffffffffull));
9713 ddi_put32(acc_hdl, &sgep->Address.High,
9714 (uint32_t)(data_cookie.dmac_laddress >> 32));
9715 }
9716
9717 function = request_hdrp->Function;
9718 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9719 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9720 pMpi2SCSIIORequest_t scsi_io_req;
9721
9722 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
9723 /*
9724 * Put SGE for data and data_out buffer at the end of
9725 * scsi_io_request message header.(64 bytes in total)
9726 * Following above SGEs, the residual space will be
9727 * used by sense data.
9728 */
9729 ddi_put8(acc_hdl,
9730 &scsi_io_req->SenseBufferLength,
9731 (uint8_t)(request_size - 64));
9732
9733 sense_bufp = mpt->m_req_frame_dma_addr +
9734 (mpt->m_req_frame_size * cmd->cmd_slot);
9735 sense_bufp += 64;
9736 ddi_put32(acc_hdl,
9737 &scsi_io_req->SenseBufferLowAddress, sense_bufp);
9738
9739 /*
9740 * Set SGLOffset0 value
9741 */
9742 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
9743 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
9744
9745 /*
9746 * Setup descriptor info. RAID passthrough must use the
9747 * default request descriptor which is already set, so if this
9748 * is a SCSI IO request, change the descriptor to SCSI IO.
9749 */
9750 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
9751 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
9752 request_desc_high = (ddi_get16(acc_hdl,
9753 &scsi_io_req->DevHandle) << 16);
9754 }
9755 }
9756
9757 /*
9758 * We must wait till the message has been completed before
9759 * beginning the next message so we wait for this one to
9760 * finish.
9761 */
9762 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
9763 request_desc_low = (cmd->cmd_slot << 16) + desc_type;
9764 cmd->cmd_rfm = NULL;
9765 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high);
9766 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
9767 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
9768 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
9769 }
9770 }
9771
9772
9773
9774 static int
9775 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
9776 uint8_t *data, uint32_t request_size, uint32_t reply_size,
9777 uint32_t data_size, uint32_t direction, uint8_t *dataout,
9778 uint32_t dataout_size, short timeout, int mode)
9779 {
9780 mptsas_pt_request_t pt;
9781 mptsas_dma_alloc_state_t data_dma_state;
9782 mptsas_dma_alloc_state_t dataout_dma_state;
9783 caddr_t memp;
9784 mptsas_cmd_t *cmd = NULL;
9785 struct scsi_pkt *pkt;
9786 uint32_t reply_len = 0, sense_len = 0;
9787 pMPI2RequestHeader_t request_hdrp;
9788 pMPI2RequestHeader_t request_msg;
9789 pMPI2DefaultReply_t reply_msg;
9790 Mpi2SCSIIOReply_t rep_msg;
9791 int i, status = 0, pt_flags = 0, rv = 0;
9792 int rvalue;
9793 uint8_t function;
9794
9795 ASSERT(mutex_owned(&mpt->m_mutex));
9796
9797 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
9798 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
9799 request_msg = kmem_zalloc(request_size, KM_SLEEP);
9800
9801 mutex_exit(&mpt->m_mutex);
9802 /*
9803 * copy in the request buffer since it could be used by
9804 * another thread when the pt request into waitq
9805 */
9806 if (ddi_copyin(request, request_msg, request_size, mode)) {
9807 mutex_enter(&mpt->m_mutex);
9808 status = EFAULT;
9809 mptsas_log(mpt, CE_WARN, "failed to copy request data");
9810 goto out;
9811 }
9812 mutex_enter(&mpt->m_mutex);
9813
9814 function = request_msg->Function;
9815 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
9816 pMpi2SCSITaskManagementRequest_t task;
9817 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
9818 mptsas_setup_bus_reset_delay(mpt);
9819 rv = mptsas_ioc_task_management(mpt, task->TaskType,
9820 task->DevHandle, (int)task->LUN[1], reply, reply_size,
9821 mode);
9822
9823 if (rv != TRUE) {
9824 status = EIO;
9825 mptsas_log(mpt, CE_WARN, "task management failed");
9826 }
9827 goto out;
9828 }
9829
9830 if (data_size != 0) {
9831 data_dma_state.size = data_size;
9832 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
9833 status = ENOMEM;
9834 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9835 "resource");
9836 goto out;
9837 }
9838 pt_flags |= MPTSAS_DATA_ALLOCATED;
9839 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
9840 mutex_exit(&mpt->m_mutex);
9841 for (i = 0; i < data_size; i++) {
9842 if (ddi_copyin(data + i, (uint8_t *)
9843 data_dma_state.memp + i, 1, mode)) {
9844 mutex_enter(&mpt->m_mutex);
9845 status = EFAULT;
9846 mptsas_log(mpt, CE_WARN, "failed to "
9847 "copy read data");
9848 goto out;
9849 }
9850 }
9851 mutex_enter(&mpt->m_mutex);
9852 }
9853 }
9854
9855 if (dataout_size != 0) {
9856 dataout_dma_state.size = dataout_size;
9857 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
9858 status = ENOMEM;
9859 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
9860 "resource");
9861 goto out;
9862 }
9863 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
9864 mutex_exit(&mpt->m_mutex);
9865 for (i = 0; i < dataout_size; i++) {
9866 if (ddi_copyin(dataout + i, (uint8_t *)
9867 dataout_dma_state.memp + i, 1, mode)) {
9868 mutex_enter(&mpt->m_mutex);
9869 mptsas_log(mpt, CE_WARN, "failed to copy out"
9870 " data");
9871 status = EFAULT;
9872 goto out;
9873 }
9874 }
9875 mutex_enter(&mpt->m_mutex);
9876 }
9877
9878 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
9879 status = EAGAIN;
9880 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
9881 goto out;
9882 }
9883 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
9884
9885 bzero((caddr_t)cmd, sizeof (*cmd));
9886 bzero((caddr_t)pkt, scsi_pkt_size());
9887 bzero((caddr_t)&pt, sizeof (pt));
9888
9889 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
9890
9891 pt.request = (uint8_t *)request_msg;
9892 pt.direction = direction;
9893 pt.request_size = request_size;
9894 pt.data_size = data_size;
9895 pt.dataout_size = dataout_size;
9896 pt.data_cookie = data_dma_state.cookie;
9897 pt.dataout_cookie = dataout_dma_state.cookie;
9898
9899 /*
9900 * Form a blank cmd/pkt to store the acknowledgement message
9901 */
9902 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
9903 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
9904 pkt->pkt_ha_private = (opaque_t)&pt;
9905 pkt->pkt_flags = FLAG_HEAD;
9906 pkt->pkt_time = timeout;
9907 cmd->cmd_pkt = pkt;
9908 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
9909
9910 /*
9911 * Save the command in a slot
9912 */
9913 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
9914 /*
9915 * Once passthru command get slot, set cmd_flags
9916 * CFLAG_PREPARED.
9917 */
9918 cmd->cmd_flags |= CFLAG_PREPARED;
9919 mptsas_start_passthru(mpt, cmd);
9920 } else {
9921 mptsas_waitq_add(mpt, cmd);
9922 }
9923
9924 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
9925 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
9926 }
9927
9928 if (cmd->cmd_flags & CFLAG_PREPARED) {
9929 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
9930 cmd->cmd_slot);
9931 request_hdrp = (pMPI2RequestHeader_t)memp;
9932 }
9933
9934 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
9935 status = ETIMEDOUT;
9936 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
9937 pt_flags |= MPTSAS_CMD_TIMEOUT;
9938 goto out;
9939 }
9940
9941 if (cmd->cmd_rfm) {
9942 /*
9943 * cmd_rfm is zero means the command reply is a CONTEXT
9944 * reply and no PCI Write to post the free reply SMFA
9945 * because no reply message frame is used.
9946 * cmd_rfm is non-zero means the reply is a ADDRESS
9947 * reply and reply message frame is used.
9948 */
9949 pt_flags |= MPTSAS_ADDRESS_REPLY;
9950 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
9951 DDI_DMA_SYNC_FORCPU);
9952 reply_msg = (pMPI2DefaultReply_t)
9953 (mpt->m_reply_frame + (cmd->cmd_rfm -
9954 mpt->m_reply_frame_dma_addr));
9955 }
9956
9957 mptsas_fma_check(mpt, cmd);
9958 if (pkt->pkt_reason == CMD_TRAN_ERR) {
9959 status = EAGAIN;
9960 mptsas_log(mpt, CE_WARN, "passthru fma error");
9961 goto out;
9962 }
9963 if (pkt->pkt_reason == CMD_RESET) {
9964 status = EAGAIN;
9965 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
9966 goto out;
9967 }
9968
9969 if (pkt->pkt_reason == CMD_INCOMPLETE) {
9970 status = EIO;
9971 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
9972 goto out;
9973 }
9974
9975 mutex_exit(&mpt->m_mutex);
9976 if (cmd->cmd_flags & CFLAG_PREPARED) {
9977 function = request_hdrp->Function;
9978 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
9979 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
9980 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
9981 sense_len = reply_size - reply_len;
9982 } else {
9983 reply_len = reply_size;
9984 sense_len = 0;
9985 }
9986
9987 for (i = 0; i < reply_len; i++) {
9988 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
9989 mode)) {
9990 mutex_enter(&mpt->m_mutex);
9991 status = EFAULT;
9992 mptsas_log(mpt, CE_WARN, "failed to copy out "
9993 "reply data");
9994 goto out;
9995 }
9996 }
9997 for (i = 0; i < sense_len; i++) {
9998 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
9999 reply + reply_len + i, 1, mode)) {
10000 mutex_enter(&mpt->m_mutex);
10001 status = EFAULT;
10002 mptsas_log(mpt, CE_WARN, "failed to copy out "
10003 "sense data");
10004 goto out;
10005 }
10006 }
10007 }
10008
10009 if (data_size) {
10010 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10011 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
10012 DDI_DMA_SYNC_FORCPU);
10013 for (i = 0; i < data_size; i++) {
10014 if (ddi_copyout((uint8_t *)(
10015 data_dma_state.memp + i), data + i, 1,
10016 mode)) {
10017 mutex_enter(&mpt->m_mutex);
10018 status = EFAULT;
10019 mptsas_log(mpt, CE_WARN, "failed to "
10020 "copy out the reply data");
10021 goto out;
10022 }
10023 }
10024 }
10025 }
10026 mutex_enter(&mpt->m_mutex);
10027 out:
10028 /*
10029 * Put the reply frame back on the free queue, increment the free
10030 * index, and write the new index to the free index register. But only
10031 * if this reply is an ADDRESS reply.
10032 */
10033 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
10034 ddi_put32(mpt->m_acc_free_queue_hdl,
10035 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10036 cmd->cmd_rfm);
10037 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10038 DDI_DMA_SYNC_FORDEV);
10039 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10040 mpt->m_free_index = 0;
10041 }
10042 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10043 mpt->m_free_index);
10044 }
10045 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10046 mptsas_remove_cmd(mpt, cmd);
10047 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10048 }
10049 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
10050 mptsas_return_to_pool(mpt, cmd);
10051 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
10052 if (mptsas_check_dma_handle(data_dma_state.handle) !=
10053 DDI_SUCCESS) {
10054 ddi_fm_service_impact(mpt->m_dip,
10055 DDI_SERVICE_UNAFFECTED);
10056 status = EFAULT;
10057 }
10058 mptsas_dma_free(&data_dma_state);
10059 }
10060 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
10061 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
10062 DDI_SUCCESS) {
10063 ddi_fm_service_impact(mpt->m_dip,
10064 DDI_SERVICE_UNAFFECTED);
10065 status = EFAULT;
10066 }
10067 mptsas_dma_free(&dataout_dma_state);
10068 }
10069 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
10070 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
10071 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
10072 }
10073 }
10074 if (request_msg)
10075 kmem_free(request_msg, request_size);
10076
10077 return (status);
10078 }
10079
10080 static int
10081 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
10082 {
10083 /*
10084 * If timeout is 0, set timeout to default of 60 seconds.
10085 */
10086 if (data->Timeout == 0) {
10087 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
10088 }
10089
10090 if (((data->DataSize == 0) &&
10091 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
10092 ((data->DataSize != 0) &&
10093 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
10094 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
10095 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
10096 (data->DataOutSize != 0))))) {
10097 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
10098 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
10099 } else {
10100 data->DataOutSize = 0;
10101 }
10102 /*
10103 * Send passthru request messages
10104 */
10105 return (mptsas_do_passthru(mpt,
10106 (uint8_t *)((uintptr_t)data->PtrRequest),
10107 (uint8_t *)((uintptr_t)data->PtrReply),
10108 (uint8_t *)((uintptr_t)data->PtrData),
10109 data->RequestSize, data->ReplySize,
10110 data->DataSize, data->DataDirection,
10111 (uint8_t *)((uintptr_t)data->PtrDataOut),
10112 data->DataOutSize, data->Timeout, mode));
10113 } else {
10114 return (EINVAL);
10115 }
10116 }
10117
10118 static uint8_t
10119 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
10120 {
10121 uint8_t index;
10122
10123 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
10124 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
10125 return (index);
10126 }
10127 }
10128
10129 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
10130 }
10131
10132 static void
10133 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
10134 {
10135 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
10136 pMpi2DiagReleaseRequest_t pDiag_release_msg;
10137 struct scsi_pkt *pkt = cmd->cmd_pkt;
10138 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
10139 uint32_t request_desc_low, i;
10140
10141 ASSERT(mutex_owned(&mpt->m_mutex));
10142
10143 /*
10144 * Form the diag message depending on the post or release function.
10145 */
10146 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
10147 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
10148 (mpt->m_req_frame + (mpt->m_req_frame_size *
10149 cmd->cmd_slot));
10150 bzero(pDiag_post_msg, mpt->m_req_frame_size);
10151 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
10152 diag->function);
10153 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
10154 diag->pBuffer->buffer_type);
10155 ddi_put8(mpt->m_acc_req_frame_hdl,
10156 &pDiag_post_msg->ExtendedType,
10157 diag->pBuffer->extended_type);
10158 ddi_put32(mpt->m_acc_req_frame_hdl,
10159 &pDiag_post_msg->BufferLength,
10160 diag->pBuffer->buffer_data.size);
10161 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
10162 i++) {
10163 ddi_put32(mpt->m_acc_req_frame_hdl,
10164 &pDiag_post_msg->ProductSpecific[i],
10165 diag->pBuffer->product_specific[i]);
10166 }
10167 ddi_put32(mpt->m_acc_req_frame_hdl,
10168 &pDiag_post_msg->BufferAddress.Low,
10169 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10170 & 0xffffffffull));
10171 ddi_put32(mpt->m_acc_req_frame_hdl,
10172 &pDiag_post_msg->BufferAddress.High,
10173 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
10174 >> 32));
10175 } else {
10176 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
10177 (mpt->m_req_frame + (mpt->m_req_frame_size *
10178 cmd->cmd_slot));
10179 bzero(pDiag_release_msg, mpt->m_req_frame_size);
10180 ddi_put8(mpt->m_acc_req_frame_hdl,
10181 &pDiag_release_msg->Function, diag->function);
10182 ddi_put8(mpt->m_acc_req_frame_hdl,
10183 &pDiag_release_msg->BufferType,
10184 diag->pBuffer->buffer_type);
10185 }
10186
10187 /*
10188 * Send the message
10189 */
10190 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
10191 DDI_DMA_SYNC_FORDEV);
10192 request_desc_low = (cmd->cmd_slot << 16) +
10193 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10194 cmd->cmd_rfm = NULL;
10195 MPTSAS_START_CMD(mpt, request_desc_low, 0);
10196 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
10197 DDI_SUCCESS) ||
10198 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
10199 DDI_SUCCESS)) {
10200 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10201 }
10202 }
10203
10204 static int
10205 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
10206 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
10207 {
10208 mptsas_diag_request_t diag;
10209 int status, slot_num, post_flags = 0;
10210 mptsas_cmd_t *cmd = NULL;
10211 struct scsi_pkt *pkt;
10212 pMpi2DiagBufferPostReply_t reply;
10213 uint16_t iocstatus;
10214 uint32_t iocloginfo, transfer_length;
10215
10216 /*
10217 * If buffer is not enabled, just leave.
10218 */
10219 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
10220 if (!pBuffer->enabled) {
10221 status = DDI_FAILURE;
10222 goto out;
10223 }
10224
10225 /*
10226 * Clear some flags initially.
10227 */
10228 pBuffer->force_release = FALSE;
10229 pBuffer->valid_data = FALSE;
10230 pBuffer->owned_by_firmware = FALSE;
10231
10232 /*
10233 * Get a cmd buffer from the cmd buffer pool
10234 */
10235 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10236 status = DDI_FAILURE;
10237 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
10238 goto out;
10239 }
10240 post_flags |= MPTSAS_REQUEST_POOL_CMD;
10241
10242 bzero((caddr_t)cmd, sizeof (*cmd));
10243 bzero((caddr_t)pkt, scsi_pkt_size());
10244
10245 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10246
10247 diag.pBuffer = pBuffer;
10248 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
10249
10250 /*
10251 * Form a blank cmd/pkt to store the acknowledgement message
10252 */
10253 pkt->pkt_ha_private = (opaque_t)&diag;
10254 pkt->pkt_flags = FLAG_HEAD;
10255 pkt->pkt_time = 60;
10256 cmd->cmd_pkt = pkt;
10257 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10258
10259 /*
10260 * Save the command in a slot
10261 */
10262 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10263 /*
10264 * Once passthru command get slot, set cmd_flags
10265 * CFLAG_PREPARED.
10266 */
10267 cmd->cmd_flags |= CFLAG_PREPARED;
10268 mptsas_start_diag(mpt, cmd);
10269 } else {
10270 mptsas_waitq_add(mpt, cmd);
10271 }
10272
10273 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10274 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10275 }
10276
10277 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10278 status = DDI_FAILURE;
10279 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
10280 goto out;
10281 }
10282
10283 /*
10284 * cmd_rfm points to the reply message if a reply was given. Check the
10285 * IOCStatus to make sure everything went OK with the FW diag request
10286 * and set buffer flags.
10287 */
10288 if (cmd->cmd_rfm) {
10289 post_flags |= MPTSAS_ADDRESS_REPLY;
10290 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10291 DDI_DMA_SYNC_FORCPU);
10292 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
10293 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10294
10295 /*
10296 * Get the reply message data
10297 */
10298 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10299 &reply->IOCStatus);
10300 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10301 &reply->IOCLogInfo);
10302 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
10303 &reply->TransferLength);
10304
10305 /*
10306 * If post failed quit.
10307 */
10308 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
10309 status = DDI_FAILURE;
10310 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
10311 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
10312 iocloginfo, transfer_length));
10313 goto out;
10314 }
10315
10316 /*
10317 * Post was successful.
10318 */
10319 pBuffer->valid_data = TRUE;
10320 pBuffer->owned_by_firmware = TRUE;
10321 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10322 status = DDI_SUCCESS;
10323 }
10324
10325 out:
10326 /*
10327 * Put the reply frame back on the free queue, increment the free
10328 * index, and write the new index to the free index register. But only
10329 * if this reply is an ADDRESS reply.
10330 */
10331 if (post_flags & MPTSAS_ADDRESS_REPLY) {
10332 ddi_put32(mpt->m_acc_free_queue_hdl,
10333 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10334 cmd->cmd_rfm);
10335 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10336 DDI_DMA_SYNC_FORDEV);
10337 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10338 mpt->m_free_index = 0;
10339 }
10340 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10341 mpt->m_free_index);
10342 }
10343 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10344 mptsas_remove_cmd(mpt, cmd);
10345 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10346 }
10347 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
10348 mptsas_return_to_pool(mpt, cmd);
10349 }
10350
10351 return (status);
10352 }
10353
10354 static int
10355 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
10356 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
10357 uint32_t diag_type)
10358 {
10359 mptsas_diag_request_t diag;
10360 int status, slot_num, rel_flags = 0;
10361 mptsas_cmd_t *cmd = NULL;
10362 struct scsi_pkt *pkt;
10363 pMpi2DiagReleaseReply_t reply;
10364 uint16_t iocstatus;
10365 uint32_t iocloginfo;
10366
10367 /*
10368 * If buffer is not enabled, just leave.
10369 */
10370 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
10371 if (!pBuffer->enabled) {
10372 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
10373 "by the IOC");
10374 status = DDI_FAILURE;
10375 goto out;
10376 }
10377
10378 /*
10379 * Clear some flags initially.
10380 */
10381 pBuffer->force_release = FALSE;
10382 pBuffer->valid_data = FALSE;
10383 pBuffer->owned_by_firmware = FALSE;
10384
10385 /*
10386 * Get a cmd buffer from the cmd buffer pool
10387 */
10388 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10389 status = DDI_FAILURE;
10390 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
10391 "Diag");
10392 goto out;
10393 }
10394 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
10395
10396 bzero((caddr_t)cmd, sizeof (*cmd));
10397 bzero((caddr_t)pkt, scsi_pkt_size());
10398
10399 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
10400
10401 diag.pBuffer = pBuffer;
10402 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
10403
10404 /*
10405 * Form a blank cmd/pkt to store the acknowledgement message
10406 */
10407 pkt->pkt_ha_private = (opaque_t)&diag;
10408 pkt->pkt_flags = FLAG_HEAD;
10409 pkt->pkt_time = 60;
10410 cmd->cmd_pkt = pkt;
10411 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
10412
10413 /*
10414 * Save the command in a slot
10415 */
10416 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
10417 /*
10418 * Once passthru command get slot, set cmd_flags
10419 * CFLAG_PREPARED.
10420 */
10421 cmd->cmd_flags |= CFLAG_PREPARED;
10422 mptsas_start_diag(mpt, cmd);
10423 } else {
10424 mptsas_waitq_add(mpt, cmd);
10425 }
10426
10427 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
10428 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
10429 }
10430
10431 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
10432 status = DDI_FAILURE;
10433 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
10434 goto out;
10435 }
10436
10437 /*
10438 * cmd_rfm points to the reply message if a reply was given. Check the
10439 * IOCStatus to make sure everything went OK with the FW diag request
10440 * and set buffer flags.
10441 */
10442 if (cmd->cmd_rfm) {
10443 rel_flags |= MPTSAS_ADDRESS_REPLY;
10444 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
10445 DDI_DMA_SYNC_FORCPU);
10446 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
10447 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr));
10448
10449 /*
10450 * Get the reply message data
10451 */
10452 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
10453 &reply->IOCStatus);
10454 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
10455 &reply->IOCLogInfo);
10456
10457 /*
10458 * If release failed quit.
10459 */
10460 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
10461 pBuffer->owned_by_firmware) {
10462 status = DDI_FAILURE;
10463 NDBG13(("release FW Diag Buffer failed: "
10464 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
10465 iocloginfo));
10466 goto out;
10467 }
10468
10469 /*
10470 * Release was successful.
10471 */
10472 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10473 status = DDI_SUCCESS;
10474
10475 /*
10476 * If this was for an UNREGISTER diag type command, clear the
10477 * unique ID.
10478 */
10479 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
10480 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10481 }
10482 }
10483
10484 out:
10485 /*
10486 * Put the reply frame back on the free queue, increment the free
10487 * index, and write the new index to the free index register. But only
10488 * if this reply is an ADDRESS reply.
10489 */
10490 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
10491 ddi_put32(mpt->m_acc_free_queue_hdl,
10492 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
10493 cmd->cmd_rfm);
10494 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
10495 DDI_DMA_SYNC_FORDEV);
10496 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
10497 mpt->m_free_index = 0;
10498 }
10499 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
10500 mpt->m_free_index);
10501 }
10502 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
10503 mptsas_remove_cmd(mpt, cmd);
10504 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
10505 }
10506 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
10507 mptsas_return_to_pool(mpt, cmd);
10508 }
10509
10510 return (status);
10511 }
10512
10513 static int
10514 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
10515 uint32_t *return_code)
10516 {
10517 mptsas_fw_diagnostic_buffer_t *pBuffer;
10518 uint8_t extended_type, buffer_type, i;
10519 uint32_t buffer_size;
10520 uint32_t unique_id;
10521 int status;
10522
10523 ASSERT(mutex_owned(&mpt->m_mutex));
10524
10525 extended_type = diag_register->ExtendedType;
10526 buffer_type = diag_register->BufferType;
10527 buffer_size = diag_register->RequestedBufferSize;
10528 unique_id = diag_register->UniqueId;
10529
10530 /*
10531 * Check for valid buffer type
10532 */
10533 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
10534 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10535 return (DDI_FAILURE);
10536 }
10537
10538 /*
10539 * Get the current buffer and look up the unique ID. The unique ID
10540 * should not be found. If it is, the ID is already in use.
10541 */
10542 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10543 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
10544 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10545 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10546 return (DDI_FAILURE);
10547 }
10548
10549 /*
10550 * The buffer's unique ID should not be registered yet, and the given
10551 * unique ID cannot be 0.
10552 */
10553 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
10554 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10555 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10556 return (DDI_FAILURE);
10557 }
10558
10559 /*
10560 * If this buffer is already posted as immediate, just change owner.
10561 */
10562 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
10563 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
10564 pBuffer->immediate = FALSE;
10565 pBuffer->unique_id = unique_id;
10566 return (DDI_SUCCESS);
10567 }
10568
10569 /*
10570 * Post a new buffer after checking if it's enabled. The DMA buffer
10571 * that is allocated will be contiguous (sgl_len = 1).
10572 */
10573 if (!pBuffer->enabled) {
10574 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10575 return (DDI_FAILURE);
10576 }
10577 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
10578 pBuffer->buffer_data.size = buffer_size;
10579 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
10580 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
10581 "diag buffer: size = %d bytes", buffer_size);
10582 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
10583 return (DDI_FAILURE);
10584 }
10585
10586 /*
10587 * Copy the given info to the diag buffer and post the buffer.
10588 */
10589 pBuffer->buffer_type = buffer_type;
10590 pBuffer->immediate = FALSE;
10591 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
10592 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
10593 i++) {
10594 pBuffer->product_specific[i] =
10595 diag_register->ProductSpecific[i];
10596 }
10597 }
10598 pBuffer->extended_type = extended_type;
10599 pBuffer->unique_id = unique_id;
10600 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
10601
10602 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10603 DDI_SUCCESS) {
10604 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
10605 "mptsas_diag_register.");
10606 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10607 status = DDI_FAILURE;
10608 }
10609
10610 /*
10611 * In case there was a failure, free the DMA buffer.
10612 */
10613 if (status == DDI_FAILURE) {
10614 mptsas_dma_free(&pBuffer->buffer_data);
10615 }
10616
10617 return (status);
10618 }
10619
10620 static int
10621 mptsas_diag_unregister(mptsas_t *mpt,
10622 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
10623 {
10624 mptsas_fw_diagnostic_buffer_t *pBuffer;
10625 uint8_t i;
10626 uint32_t unique_id;
10627 int status;
10628
10629 ASSERT(mutex_owned(&mpt->m_mutex));
10630
10631 unique_id = diag_unregister->UniqueId;
10632
10633 /*
10634 * Get the current buffer and look up the unique ID. The unique ID
10635 * should be there.
10636 */
10637 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10638 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10639 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10640 return (DDI_FAILURE);
10641 }
10642
10643 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10644
10645 /*
10646 * Try to release the buffer from FW before freeing it. If release
10647 * fails, don't free the DMA buffer in case FW tries to access it
10648 * later. If buffer is not owned by firmware, can't release it.
10649 */
10650 if (!pBuffer->owned_by_firmware) {
10651 status = DDI_SUCCESS;
10652 } else {
10653 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
10654 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
10655 }
10656
10657 /*
10658 * At this point, return the current status no matter what happens with
10659 * the DMA buffer.
10660 */
10661 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
10662 if (status == DDI_SUCCESS) {
10663 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
10664 DDI_SUCCESS) {
10665 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
10666 "in mptsas_diag_unregister.");
10667 ddi_fm_service_impact(mpt->m_dip,
10668 DDI_SERVICE_UNAFFECTED);
10669 }
10670 mptsas_dma_free(&pBuffer->buffer_data);
10671 }
10672
10673 return (status);
10674 }
10675
10676 static int
10677 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
10678 uint32_t *return_code)
10679 {
10680 mptsas_fw_diagnostic_buffer_t *pBuffer;
10681 uint8_t i;
10682 uint32_t unique_id;
10683
10684 ASSERT(mutex_owned(&mpt->m_mutex));
10685
10686 unique_id = diag_query->UniqueId;
10687
10688 /*
10689 * If ID is valid, query on ID.
10690 * If ID is invalid, query on buffer type.
10691 */
10692 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
10693 i = diag_query->BufferType;
10694 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
10695 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10696 return (DDI_FAILURE);
10697 }
10698 } else {
10699 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10700 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10701 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10702 return (DDI_FAILURE);
10703 }
10704 }
10705
10706 /*
10707 * Fill query structure with the diag buffer info.
10708 */
10709 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10710 diag_query->BufferType = pBuffer->buffer_type;
10711 diag_query->ExtendedType = pBuffer->extended_type;
10712 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
10713 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
10714 i++) {
10715 diag_query->ProductSpecific[i] =
10716 pBuffer->product_specific[i];
10717 }
10718 }
10719 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
10720 diag_query->DriverAddedBufferSize = 0;
10721 diag_query->UniqueId = pBuffer->unique_id;
10722 diag_query->ApplicationFlags = 0;
10723 diag_query->DiagnosticFlags = 0;
10724
10725 /*
10726 * Set/Clear application flags
10727 */
10728 if (pBuffer->immediate) {
10729 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10730 } else {
10731 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
10732 }
10733 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
10734 diag_query->ApplicationFlags |=
10735 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10736 } else {
10737 diag_query->ApplicationFlags &=
10738 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
10739 }
10740 if (pBuffer->owned_by_firmware) {
10741 diag_query->ApplicationFlags |=
10742 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10743 } else {
10744 diag_query->ApplicationFlags &=
10745 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
10746 }
10747
10748 return (DDI_SUCCESS);
10749 }
10750
10751 static int
10752 mptsas_diag_read_buffer(mptsas_t *mpt,
10753 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
10754 uint32_t *return_code, int ioctl_mode)
10755 {
10756 mptsas_fw_diagnostic_buffer_t *pBuffer;
10757 uint8_t i, *pData;
10758 uint32_t unique_id, byte;
10759 int status;
10760
10761 ASSERT(mutex_owned(&mpt->m_mutex));
10762
10763 unique_id = diag_read_buffer->UniqueId;
10764
10765 /*
10766 * Get the current buffer and look up the unique ID. The unique ID
10767 * should be there.
10768 */
10769 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10770 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10771 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10772 return (DDI_FAILURE);
10773 }
10774
10775 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10776
10777 /*
10778 * Make sure requested read is within limits
10779 */
10780 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
10781 pBuffer->buffer_data.size) {
10782 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10783 return (DDI_FAILURE);
10784 }
10785
10786 /*
10787 * Copy the requested data from DMA to the diag_read_buffer. The DMA
10788 * buffer that was allocated is one contiguous buffer.
10789 */
10790 pData = (uint8_t *)(pBuffer->buffer_data.memp +
10791 diag_read_buffer->StartingOffset);
10792 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
10793 DDI_DMA_SYNC_FORCPU);
10794 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
10795 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
10796 != 0) {
10797 return (DDI_FAILURE);
10798 }
10799 }
10800 diag_read_buffer->Status = 0;
10801
10802 /*
10803 * Set or clear the Force Release flag.
10804 */
10805 if (pBuffer->force_release) {
10806 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10807 } else {
10808 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
10809 }
10810
10811 /*
10812 * If buffer is to be reregistered, make sure it's not already owned by
10813 * firmware first.
10814 */
10815 status = DDI_SUCCESS;
10816 if (!pBuffer->owned_by_firmware) {
10817 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
10818 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
10819 return_code);
10820 }
10821 }
10822
10823 return (status);
10824 }
10825
10826 static int
10827 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
10828 uint32_t *return_code)
10829 {
10830 mptsas_fw_diagnostic_buffer_t *pBuffer;
10831 uint8_t i;
10832 uint32_t unique_id;
10833 int status;
10834
10835 ASSERT(mutex_owned(&mpt->m_mutex));
10836
10837 unique_id = diag_release->UniqueId;
10838
10839 /*
10840 * Get the current buffer and look up the unique ID. The unique ID
10841 * should be there.
10842 */
10843 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
10844 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
10845 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
10846 return (DDI_FAILURE);
10847 }
10848
10849 pBuffer = &mpt->m_fw_diag_buffer_list[i];
10850
10851 /*
10852 * If buffer is not owned by firmware, it's already been released.
10853 */
10854 if (!pBuffer->owned_by_firmware) {
10855 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
10856 return (DDI_FAILURE);
10857 }
10858
10859 /*
10860 * Release the buffer.
10861 */
10862 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
10863 MPTSAS_FW_DIAG_TYPE_RELEASE);
10864 return (status);
10865 }
10866
10867 static int
10868 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
10869 uint32_t length, uint32_t *return_code, int ioctl_mode)
10870 {
10871 mptsas_fw_diag_register_t diag_register;
10872 mptsas_fw_diag_unregister_t diag_unregister;
10873 mptsas_fw_diag_query_t diag_query;
10874 mptsas_diag_read_buffer_t diag_read_buffer;
10875 mptsas_fw_diag_release_t diag_release;
10876 int status = DDI_SUCCESS;
10877 uint32_t original_return_code, read_buf_len;
10878
10879 ASSERT(mutex_owned(&mpt->m_mutex));
10880
10881 original_return_code = *return_code;
10882 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
10883
10884 switch (action) {
10885 case MPTSAS_FW_DIAG_TYPE_REGISTER:
10886 if (!length) {
10887 *return_code =
10888 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10889 status = DDI_FAILURE;
10890 break;
10891 }
10892 if (ddi_copyin(diag_action, &diag_register,
10893 sizeof (diag_register), ioctl_mode) != 0) {
10894 return (DDI_FAILURE);
10895 }
10896 status = mptsas_diag_register(mpt, &diag_register,
10897 return_code);
10898 break;
10899
10900 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
10901 if (length < sizeof (diag_unregister)) {
10902 *return_code =
10903 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10904 status = DDI_FAILURE;
10905 break;
10906 }
10907 if (ddi_copyin(diag_action, &diag_unregister,
10908 sizeof (diag_unregister), ioctl_mode) != 0) {
10909 return (DDI_FAILURE);
10910 }
10911 status = mptsas_diag_unregister(mpt, &diag_unregister,
10912 return_code);
10913 break;
10914
10915 case MPTSAS_FW_DIAG_TYPE_QUERY:
10916 if (length < sizeof (diag_query)) {
10917 *return_code =
10918 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10919 status = DDI_FAILURE;
10920 break;
10921 }
10922 if (ddi_copyin(diag_action, &diag_query,
10923 sizeof (diag_query), ioctl_mode) != 0) {
10924 return (DDI_FAILURE);
10925 }
10926 status = mptsas_diag_query(mpt, &diag_query,
10927 return_code);
10928 if (status == DDI_SUCCESS) {
10929 if (ddi_copyout(&diag_query, diag_action,
10930 sizeof (diag_query), ioctl_mode) != 0) {
10931 return (DDI_FAILURE);
10932 }
10933 }
10934 break;
10935
10936 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
10937 if (ddi_copyin(diag_action, &diag_read_buffer,
10938 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
10939 return (DDI_FAILURE);
10940 }
10941 read_buf_len = sizeof (diag_read_buffer) -
10942 sizeof (diag_read_buffer.DataBuffer) +
10943 diag_read_buffer.BytesToRead;
10944 if (length < read_buf_len) {
10945 *return_code =
10946 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10947 status = DDI_FAILURE;
10948 break;
10949 }
10950 status = mptsas_diag_read_buffer(mpt,
10951 &diag_read_buffer, diag_action +
10952 sizeof (diag_read_buffer) - 4, return_code,
10953 ioctl_mode);
10954 if (status == DDI_SUCCESS) {
10955 if (ddi_copyout(&diag_read_buffer, diag_action,
10956 sizeof (diag_read_buffer) - 4, ioctl_mode)
10957 != 0) {
10958 return (DDI_FAILURE);
10959 }
10960 }
10961 break;
10962
10963 case MPTSAS_FW_DIAG_TYPE_RELEASE:
10964 if (length < sizeof (diag_release)) {
10965 *return_code =
10966 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10967 status = DDI_FAILURE;
10968 break;
10969 }
10970 if (ddi_copyin(diag_action, &diag_release,
10971 sizeof (diag_release), ioctl_mode) != 0) {
10972 return (DDI_FAILURE);
10973 }
10974 status = mptsas_diag_release(mpt, &diag_release,
10975 return_code);
10976 break;
10977
10978 default:
10979 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
10980 status = DDI_FAILURE;
10981 break;
10982 }
10983
10984 if ((status == DDI_FAILURE) &&
10985 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
10986 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
10987 status = DDI_SUCCESS;
10988 }
10989
10990 return (status);
10991 }
10992
10993 static int
10994 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
10995 {
10996 int status;
10997 mptsas_diag_action_t driver_data;
10998
10999 ASSERT(mutex_owned(&mpt->m_mutex));
11000
11001 /*
11002 * Copy the user data to a driver data buffer.
11003 */
11004 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
11005 mode) == 0) {
11006 /*
11007 * Send diag action request if Action is valid
11008 */
11009 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
11010 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
11011 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
11012 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
11013 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
11014 status = mptsas_do_diag_action(mpt, driver_data.Action,
11015 (void *)(uintptr_t)driver_data.PtrDiagAction,
11016 driver_data.Length, &driver_data.ReturnCode,
11017 mode);
11018 if (status == DDI_SUCCESS) {
11019 if (ddi_copyout(&driver_data.ReturnCode,
11020 &user_data->ReturnCode,
11021 sizeof (user_data->ReturnCode), mode)
11022 != 0) {
11023 status = EFAULT;
11024 } else {
11025 status = 0;
11026 }
11027 } else {
11028 status = EIO;
11029 }
11030 } else {
11031 status = EINVAL;
11032 }
11033 } else {
11034 status = EFAULT;
11035 }
11036
11037 return (status);
11038 }
11039
11040 /*
11041 * This routine handles the "event query" ioctl.
11042 */
11043 static int
11044 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
11045 int *rval)
11046 {
11047 int status;
11048 mptsas_event_query_t driverdata;
11049 uint8_t i;
11050
11051 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
11052
11053 mutex_enter(&mpt->m_mutex);
11054 for (i = 0; i < 4; i++) {
11055 driverdata.Types[i] = mpt->m_event_mask[i];
11056 }
11057 mutex_exit(&mpt->m_mutex);
11058
11059 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
11060 status = EFAULT;
11061 } else {
11062 *rval = MPTIOCTL_STATUS_GOOD;
11063 status = 0;
11064 }
11065
11066 return (status);
11067 }
11068
11069 /*
11070 * This routine handles the "event enable" ioctl.
11071 */
11072 static int
11073 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
11074 int *rval)
11075 {
11076 int status;
11077 mptsas_event_enable_t driverdata;
11078 uint8_t i;
11079
11080 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11081 mutex_enter(&mpt->m_mutex);
11082 for (i = 0; i < 4; i++) {
11083 mpt->m_event_mask[i] = driverdata.Types[i];
11084 }
11085 mutex_exit(&mpt->m_mutex);
11086
11087 *rval = MPTIOCTL_STATUS_GOOD;
11088 status = 0;
11089 } else {
11090 status = EFAULT;
11091 }
11092 return (status);
11093 }
11094
11095 /*
11096 * This routine handles the "event report" ioctl.
11097 */
11098 static int
11099 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
11100 int *rval)
11101 {
11102 int status;
11103 mptsas_event_report_t driverdata;
11104
11105 mutex_enter(&mpt->m_mutex);
11106
11107 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
11108 mode) == 0) {
11109 if (driverdata.Size >= sizeof (mpt->m_events)) {
11110 if (ddi_copyout(mpt->m_events, data->Events,
11111 sizeof (mpt->m_events), mode) != 0) {
11112 status = EFAULT;
11113 } else {
11114 if (driverdata.Size > sizeof (mpt->m_events)) {
11115 driverdata.Size =
11116 sizeof (mpt->m_events);
11117 if (ddi_copyout(&driverdata.Size,
11118 &data->Size,
11119 sizeof (driverdata.Size),
11120 mode) != 0) {
11121 status = EFAULT;
11122 } else {
11123 *rval = MPTIOCTL_STATUS_GOOD;
11124 status = 0;
11125 }
11126 } else {
11127 *rval = MPTIOCTL_STATUS_GOOD;
11128 status = 0;
11129 }
11130 }
11131 } else {
11132 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11133 status = 0;
11134 }
11135 } else {
11136 status = EFAULT;
11137 }
11138
11139 mutex_exit(&mpt->m_mutex);
11140 return (status);
11141 }
11142
11143 static void
11144 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11145 {
11146 int *reg_data;
11147 uint_t reglen;
11148
11149 /*
11150 * Lookup the 'reg' property and extract the other data
11151 */
11152 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11153 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11154 DDI_PROP_SUCCESS) {
11155 /*
11156 * Extract the PCI data from the 'reg' property first DWORD.
11157 * The entry looks like the following:
11158 * First DWORD:
11159 * Bits 0 - 7 8-bit Register number
11160 * Bits 8 - 10 3-bit Function number
11161 * Bits 11 - 15 5-bit Device number
11162 * Bits 16 - 23 8-bit Bus number
11163 * Bits 24 - 25 2-bit Address Space type identifier
11164 *
11165 */
11166 adapter_data->PciInformation.u.bits.BusNumber =
11167 (reg_data[0] & 0x00FF0000) >> 16;
11168 adapter_data->PciInformation.u.bits.DeviceNumber =
11169 (reg_data[0] & 0x0000F800) >> 11;
11170 adapter_data->PciInformation.u.bits.FunctionNumber =
11171 (reg_data[0] & 0x00000700) >> 8;
11172 ddi_prop_free((void *)reg_data);
11173 } else {
11174 /*
11175 * If we can't determine the PCI data then we fill in FF's for
11176 * the data to indicate this.
11177 */
11178 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
11179 adapter_data->MpiPortNumber = 0xFFFFFFFF;
11180 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
11181 }
11182
11183 /*
11184 * Saved in the mpt->m_fwversion
11185 */
11186 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
11187 }
11188
11189 static void
11190 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
11191 {
11192 char *driver_verstr = MPTSAS_MOD_STRING;
11193
11194 mptsas_lookup_pci_data(mpt, adapter_data);
11195 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2;
11196 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
11197 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
11198 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
11199 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
11200 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
11201 adapter_data->BiosVersion = 0;
11202 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
11203 }
11204
11205 static void
11206 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
11207 {
11208 int *reg_data, i;
11209 uint_t reglen;
11210
11211 /*
11212 * Lookup the 'reg' property and extract the other data
11213 */
11214 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
11215 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
11216 DDI_PROP_SUCCESS) {
11217 /*
11218 * Extract the PCI data from the 'reg' property first DWORD.
11219 * The entry looks like the following:
11220 * First DWORD:
11221 * Bits 8 - 10 3-bit Function number
11222 * Bits 11 - 15 5-bit Device number
11223 * Bits 16 - 23 8-bit Bus number
11224 */
11225 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
11226 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
11227 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
11228 ddi_prop_free((void *)reg_data);
11229 } else {
11230 /*
11231 * If we can't determine the PCI info then we fill in FF's for
11232 * the data to indicate this.
11233 */
11234 pci_info->BusNumber = 0xFFFFFFFF;
11235 pci_info->DeviceNumber = 0xFF;
11236 pci_info->FunctionNumber = 0xFF;
11237 }
11238
11239 /*
11240 * Now get the interrupt vector and the pci header. The vector can
11241 * only be 0 right now. The header is the first 256 bytes of config
11242 * space.
11243 */
11244 pci_info->InterruptVector = 0;
11245 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
11246 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
11247 i);
11248 }
11249 }
11250
11251 static int
11252 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
11253 {
11254 int status = 0;
11255 mptsas_reg_access_t driverdata;
11256
11257 mutex_enter(&mpt->m_mutex);
11258 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
11259 switch (driverdata.Command) {
11260 /*
11261 * IO access is not supported.
11262 */
11263 case REG_IO_READ:
11264 case REG_IO_WRITE:
11265 mptsas_log(mpt, CE_WARN, "IO access is not "
11266 "supported. Use memory access.");
11267 status = EINVAL;
11268 break;
11269
11270 case REG_MEM_READ:
11271 driverdata.RegData = ddi_get32(mpt->m_datap,
11272 (uint32_t *)(void *)mpt->m_reg +
11273 driverdata.RegOffset);
11274 if (ddi_copyout(&driverdata.RegData,
11275 &data->RegData,
11276 sizeof (driverdata.RegData), mode) != 0) {
11277 mptsas_log(mpt, CE_WARN, "Register "
11278 "Read Failed");
11279 status = EFAULT;
11280 }
11281 break;
11282
11283 case REG_MEM_WRITE:
11284 ddi_put32(mpt->m_datap,
11285 (uint32_t *)(void *)mpt->m_reg +
11286 driverdata.RegOffset,
11287 driverdata.RegData);
11288 break;
11289
11290 default:
11291 status = EINVAL;
11292 break;
11293 }
11294 } else {
11295 status = EFAULT;
11296 }
11297
11298 mutex_exit(&mpt->m_mutex);
11299 return (status);
11300 }
11301
11302 static int
11303 led_control(mptsas_t *mpt, intptr_t data, int mode)
11304 {
11305 int ret = 0;
11306 mptsas_led_control_t lc;
11307 mptsas_target_t *ptgt;
11308
11309 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
11310 return (EFAULT);
11311 }
11312
11313 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
11314 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
11315 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
11316 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
11317 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
11318 lc.LedStatus != 1)) {
11319 return (EINVAL);
11320 }
11321
11322 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
11323 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
11324 return (EACCES);
11325
11326 /* Locate the target we're interrogating... */
11327 mutex_enter(&mpt->m_mutex);
11328 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11329 MPTSAS_HASH_FIRST);
11330 while (ptgt != NULL) {
11331 if (ptgt->m_enclosure == lc.Enclosure &&
11332 ptgt->m_slot_num == lc.Slot) {
11333 break;
11334 }
11335 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11336 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11337 }
11338 if (ptgt == NULL) {
11339 /* We could not find a target for that enclosure/slot. */
11340 mutex_exit(&mpt->m_mutex);
11341 return (ENOENT);
11342 }
11343
11344 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
11345 /* Update our internal LED state. */
11346 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
11347 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
11348
11349 /* Flush it to the controller. */
11350 ret = mptsas_flush_led_status(mpt, ptgt);
11351 mutex_exit(&mpt->m_mutex);
11352 return (ret);
11353 }
11354
11355 /* Return our internal LED state. */
11356 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
11357 mutex_exit(&mpt->m_mutex);
11358
11359 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
11360 return (EFAULT);
11361 }
11362
11363 return (0);
11364 }
11365
11366 static int
11367 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
11368 {
11369 uint16_t i = 0;
11370 uint16_t count = 0;
11371 int ret = 0;
11372 mptsas_target_t *ptgt;
11373 mptsas_disk_info_t *di;
11374 STRUCT_DECL(mptsas_get_disk_info, gdi);
11375
11376 if ((mode & FREAD) == 0)
11377 return (EACCES);
11378
11379 STRUCT_INIT(gdi, get_udatamodel());
11380
11381 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
11382 mode) != 0) {
11383 return (EFAULT);
11384 }
11385
11386 /* Find out how many targets there are. */
11387 mutex_enter(&mpt->m_mutex);
11388 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11389 MPTSAS_HASH_FIRST);
11390 while (ptgt != NULL) {
11391 count++;
11392 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11393 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11394 }
11395 mutex_exit(&mpt->m_mutex);
11396
11397 /*
11398 * If we haven't been asked to copy out information on each target,
11399 * then just return the count.
11400 */
11401 STRUCT_FSET(gdi, DiskCount, count);
11402 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
11403 goto copy_out;
11404
11405 /*
11406 * If we haven't been given a large enough buffer to copy out into,
11407 * let the caller know.
11408 */
11409 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
11410 count * sizeof (mptsas_disk_info_t)) {
11411 ret = ENOSPC;
11412 goto copy_out;
11413 }
11414
11415 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
11416
11417 mutex_enter(&mpt->m_mutex);
11418 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11419 MPTSAS_HASH_FIRST);
11420 while (ptgt != NULL) {
11421 if (i >= count) {
11422 /*
11423 * The number of targets changed while we weren't
11424 * looking, so give up.
11425 */
11426 mutex_exit(&mpt->m_mutex);
11427 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11428 return (EAGAIN);
11429 }
11430 di[i].Instance = mpt->m_instance;
11431 di[i].Enclosure = ptgt->m_enclosure;
11432 di[i].Slot = ptgt->m_slot_num;
11433 di[i].SasAddress = ptgt->m_sas_wwn;
11434
11435 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11436 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11437 i++;
11438 }
11439 mutex_exit(&mpt->m_mutex);
11440 STRUCT_FSET(gdi, DiskCount, i);
11441
11442 /* Copy out the disk information to the caller. */
11443 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
11444 i * sizeof (mptsas_disk_info_t), mode) != 0) {
11445 ret = EFAULT;
11446 }
11447
11448 kmem_free(di, count * sizeof (mptsas_disk_info_t));
11449
11450 copy_out:
11451 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
11452 mode) != 0) {
11453 ret = EFAULT;
11454 }
11455
11456 return (ret);
11457 }
11458
11459 static int
11460 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
11461 int *rval)
11462 {
11463 int status = 0;
11464 mptsas_t *mpt;
11465 mptsas_update_flash_t flashdata;
11466 mptsas_pass_thru_t passthru_data;
11467 mptsas_adapter_data_t adapter_data;
11468 mptsas_pci_info_t pci_info;
11469 int copylen;
11470
11471 int iport_flag = 0;
11472 dev_info_t *dip = NULL;
11473 mptsas_phymask_t phymask = 0;
11474 struct devctl_iocdata *dcp = NULL;
11475 char *addr = NULL;
11476 mptsas_target_t *ptgt = NULL;
11477
11478 *rval = MPTIOCTL_STATUS_GOOD;
11479 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
11480 return (EPERM);
11481 }
11482
11483 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
11484 if (mpt == NULL) {
11485 /*
11486 * Called from iport node, get the states
11487 */
11488 iport_flag = 1;
11489 dip = mptsas_get_dip_from_dev(dev, &phymask);
11490 if (dip == NULL) {
11491 return (ENXIO);
11492 }
11493 mpt = DIP2MPT(dip);
11494 }
11495 /* Make sure power level is D0 before accessing registers */
11496 mutex_enter(&mpt->m_mutex);
11497 if (mpt->m_options & MPTSAS_OPT_PM) {
11498 (void) pm_busy_component(mpt->m_dip, 0);
11499 if (mpt->m_power_level != PM_LEVEL_D0) {
11500 mutex_exit(&mpt->m_mutex);
11501 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
11502 DDI_SUCCESS) {
11503 mptsas_log(mpt, CE_WARN,
11504 "mptsas%d: mptsas_ioctl: Raise power "
11505 "request failed.", mpt->m_instance);
11506 (void) pm_idle_component(mpt->m_dip, 0);
11507 return (ENXIO);
11508 }
11509 } else {
11510 mutex_exit(&mpt->m_mutex);
11511 }
11512 } else {
11513 mutex_exit(&mpt->m_mutex);
11514 }
11515
11516 if (iport_flag) {
11517 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
11518 if (status != 0) {
11519 goto out;
11520 }
11521 /*
11522 * The following code control the OK2RM LED, it doesn't affect
11523 * the ioctl return status.
11524 */
11525 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
11526 (cmd == DEVCTL_DEVICE_OFFLINE)) {
11527 if (ndi_dc_allochdl((void *)data, &dcp) !=
11528 NDI_SUCCESS) {
11529 goto out;
11530 }
11531 addr = ndi_dc_getaddr(dcp);
11532 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
11533 if (ptgt == NULL) {
11534 NDBG14(("mptsas_ioctl led control: tgt %s not "
11535 "found", addr));
11536 ndi_dc_freehdl(dcp);
11537 goto out;
11538 }
11539 mutex_enter(&mpt->m_mutex);
11540 if (cmd == DEVCTL_DEVICE_ONLINE) {
11541 ptgt->m_tgt_unconfigured = 0;
11542 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
11543 ptgt->m_tgt_unconfigured = 1;
11544 }
11545 if (cmd == DEVCTL_DEVICE_OFFLINE) {
11546 ptgt->m_led_status |=
11547 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11548 } else {
11549 ptgt->m_led_status &=
11550 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
11551 }
11552 (void) mptsas_flush_led_status(mpt, ptgt);
11553 mutex_exit(&mpt->m_mutex);
11554 ndi_dc_freehdl(dcp);
11555 }
11556 goto out;
11557 }
11558 switch (cmd) {
11559 case MPTIOCTL_GET_DISK_INFO:
11560 status = get_disk_info(mpt, data, mode);
11561 break;
11562 case MPTIOCTL_LED_CONTROL:
11563 status = led_control(mpt, data, mode);
11564 break;
11565 case MPTIOCTL_UPDATE_FLASH:
11566 if (ddi_copyin((void *)data, &flashdata,
11567 sizeof (struct mptsas_update_flash), mode)) {
11568 status = EFAULT;
11569 break;
11570 }
11571
11572 mutex_enter(&mpt->m_mutex);
11573 if (mptsas_update_flash(mpt,
11574 (caddr_t)(long)flashdata.PtrBuffer,
11575 flashdata.ImageSize, flashdata.ImageType, mode)) {
11576 status = EFAULT;
11577 }
11578
11579 /*
11580 * Reset the chip to start using the new
11581 * firmware. Reset if failed also.
11582 */
11583 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11584 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
11585 status = EFAULT;
11586 }
11587 mutex_exit(&mpt->m_mutex);
11588 break;
11589 case MPTIOCTL_PASS_THRU:
11590 /*
11591 * The user has requested to pass through a command to
11592 * be executed by the MPT firmware. Call our routine
11593 * which does this. Only allow one passthru IOCTL at
11594 * one time. Other threads will block on
11595 * m_passthru_mutex, which is of adaptive variant.
11596 */
11597 if (ddi_copyin((void *)data, &passthru_data,
11598 sizeof (mptsas_pass_thru_t), mode)) {
11599 status = EFAULT;
11600 break;
11601 }
11602 mutex_enter(&mpt->m_passthru_mutex);
11603 mutex_enter(&mpt->m_mutex);
11604 status = mptsas_pass_thru(mpt, &passthru_data, mode);
11605 mutex_exit(&mpt->m_mutex);
11606 mutex_exit(&mpt->m_passthru_mutex);
11607
11608 break;
11609 case MPTIOCTL_GET_ADAPTER_DATA:
11610 /*
11611 * The user has requested to read adapter data. Call
11612 * our routine which does this.
11613 */
11614 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
11615 if (ddi_copyin((void *)data, (void *)&adapter_data,
11616 sizeof (mptsas_adapter_data_t), mode)) {
11617 status = EFAULT;
11618 break;
11619 }
11620 if (adapter_data.StructureLength >=
11621 sizeof (mptsas_adapter_data_t)) {
11622 adapter_data.StructureLength = (uint32_t)
11623 sizeof (mptsas_adapter_data_t);
11624 copylen = sizeof (mptsas_adapter_data_t);
11625 mutex_enter(&mpt->m_mutex);
11626 mptsas_read_adapter_data(mpt, &adapter_data);
11627 mutex_exit(&mpt->m_mutex);
11628 } else {
11629 adapter_data.StructureLength = (uint32_t)
11630 sizeof (mptsas_adapter_data_t);
11631 copylen = sizeof (adapter_data.StructureLength);
11632 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
11633 }
11634 if (ddi_copyout((void *)(&adapter_data), (void *)data,
11635 copylen, mode) != 0) {
11636 status = EFAULT;
11637 }
11638 break;
11639 case MPTIOCTL_GET_PCI_INFO:
11640 /*
11641 * The user has requested to read pci info. Call
11642 * our routine which does this.
11643 */
11644 bzero(&pci_info, sizeof (mptsas_pci_info_t));
11645 mutex_enter(&mpt->m_mutex);
11646 mptsas_read_pci_info(mpt, &pci_info);
11647 mutex_exit(&mpt->m_mutex);
11648 if (ddi_copyout((void *)(&pci_info), (void *)data,
11649 sizeof (mptsas_pci_info_t), mode) != 0) {
11650 status = EFAULT;
11651 }
11652 break;
11653 case MPTIOCTL_RESET_ADAPTER:
11654 mutex_enter(&mpt->m_mutex);
11655 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
11656 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11657 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
11658 "failed");
11659 status = EFAULT;
11660 }
11661 mutex_exit(&mpt->m_mutex);
11662 break;
11663 case MPTIOCTL_DIAG_ACTION:
11664 /*
11665 * The user has done a diag buffer action. Call our
11666 * routine which does this. Only allow one diag action
11667 * at one time.
11668 */
11669 mutex_enter(&mpt->m_mutex);
11670 if (mpt->m_diag_action_in_progress) {
11671 mutex_exit(&mpt->m_mutex);
11672 return (EBUSY);
11673 }
11674 mpt->m_diag_action_in_progress = 1;
11675 status = mptsas_diag_action(mpt,
11676 (mptsas_diag_action_t *)data, mode);
11677 mpt->m_diag_action_in_progress = 0;
11678 mutex_exit(&mpt->m_mutex);
11679 break;
11680 case MPTIOCTL_EVENT_QUERY:
11681 /*
11682 * The user has done an event query. Call our routine
11683 * which does this.
11684 */
11685 status = mptsas_event_query(mpt,
11686 (mptsas_event_query_t *)data, mode, rval);
11687 break;
11688 case MPTIOCTL_EVENT_ENABLE:
11689 /*
11690 * The user has done an event enable. Call our routine
11691 * which does this.
11692 */
11693 status = mptsas_event_enable(mpt,
11694 (mptsas_event_enable_t *)data, mode, rval);
11695 break;
11696 case MPTIOCTL_EVENT_REPORT:
11697 /*
11698 * The user has done an event report. Call our routine
11699 * which does this.
11700 */
11701 status = mptsas_event_report(mpt,
11702 (mptsas_event_report_t *)data, mode, rval);
11703 break;
11704 case MPTIOCTL_REG_ACCESS:
11705 /*
11706 * The user has requested register access. Call our
11707 * routine which does this.
11708 */
11709 status = mptsas_reg_access(mpt,
11710 (mptsas_reg_access_t *)data, mode);
11711 break;
11712 default:
11713 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
11714 rval);
11715 break;
11716 }
11717
11718 out:
11719 return (status);
11720 }
11721
11722 int
11723 mptsas_restart_ioc(mptsas_t *mpt)
11724 {
11725 int rval = DDI_SUCCESS;
11726 mptsas_target_t *ptgt = NULL;
11727
11728 ASSERT(mutex_owned(&mpt->m_mutex));
11729
11730 /*
11731 * Set a flag telling I/O path that we're processing a reset. This is
11732 * needed because after the reset is complete, the hash table still
11733 * needs to be rebuilt. If I/Os are started before the hash table is
11734 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
11735 * so that they can be retried.
11736 */
11737 mpt->m_in_reset = TRUE;
11738
11739 /*
11740 * Set all throttles to HOLD
11741 */
11742 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11743 MPTSAS_HASH_FIRST);
11744 while (ptgt != NULL) {
11745 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
11746
11747 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11748 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11749 }
11750
11751 /*
11752 * Disable interrupts
11753 */
11754 MPTSAS_DISABLE_INTR(mpt);
11755
11756 /*
11757 * Abort all commands: outstanding commands, commands in waitq and
11758 * tx_waitq.
11759 */
11760 mptsas_flush_hba(mpt);
11761
11762 /*
11763 * Reinitialize the chip.
11764 */
11765 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
11766 rval = DDI_FAILURE;
11767 }
11768
11769 /*
11770 * Enable interrupts again
11771 */
11772 MPTSAS_ENABLE_INTR(mpt);
11773
11774 /*
11775 * If mptsas_init_chip was successful, update the driver data.
11776 */
11777 if (rval == DDI_SUCCESS) {
11778 mptsas_update_driver_data(mpt);
11779 }
11780
11781 /*
11782 * Reset the throttles
11783 */
11784 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
11785 MPTSAS_HASH_FIRST);
11786 while (ptgt != NULL) {
11787 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
11788
11789 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
11790 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
11791 }
11792
11793 mptsas_doneq_empty(mpt);
11794 mptsas_restart_hba(mpt);
11795
11796 if (rval != DDI_SUCCESS) {
11797 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
11798 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
11799 }
11800
11801 /*
11802 * Clear the reset flag so that I/Os can continue.
11803 */
11804 mpt->m_in_reset = FALSE;
11805
11806 return (rval);
11807 }
11808
11809 static int
11810 mptsas_init_chip(mptsas_t *mpt, int first_time)
11811 {
11812 ddi_dma_cookie_t cookie;
11813 uint32_t i;
11814 int rval;
11815
11816 /*
11817 * Check to see if the firmware image is valid
11818 */
11819 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
11820 MPI2_DIAG_FLASH_BAD_SIG) {
11821 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
11822 goto fail;
11823 }
11824
11825 /*
11826 * Reset the chip
11827 */
11828 rval = mptsas_ioc_reset(mpt, first_time);
11829 if (rval == MPTSAS_RESET_FAIL) {
11830 mptsas_log(mpt, CE_WARN, "hard reset failed!");
11831 goto fail;
11832 }
11833
11834 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
11835 goto mur;
11836 }
11837 /*
11838 * Setup configuration space
11839 */
11840 if (mptsas_config_space_init(mpt) == FALSE) {
11841 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
11842 "failed!");
11843 goto fail;
11844 }
11845
11846 /*
11847 * IOC facts can change after a diag reset so all buffers that are
11848 * based on these numbers must be de-allocated and re-allocated. Get
11849 * new IOC facts each time chip is initialized.
11850 */
11851 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
11852 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
11853 goto fail;
11854 }
11855
11856 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
11857 goto fail;
11858 }
11859 /*
11860 * Allocate request message frames, reply free queue, reply descriptor
11861 * post queue, and reply message frames using latest IOC facts.
11862 */
11863 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
11864 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
11865 goto fail;
11866 }
11867 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
11868 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
11869 goto fail;
11870 }
11871 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
11872 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
11873 goto fail;
11874 }
11875 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
11876 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
11877 goto fail;
11878 }
11879
11880 mur:
11881 /*
11882 * Re-Initialize ioc to operational state
11883 */
11884 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
11885 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
11886 goto fail;
11887 }
11888
11889 mptsas_alloc_reply_args(mpt);
11890
11891 /*
11892 * Initialize reply post index. Reply free index is initialized after
11893 * the next loop.
11894 */
11895 mpt->m_post_index = 0;
11896
11897 /*
11898 * Initialize the Reply Free Queue with the physical addresses of our
11899 * reply frames.
11900 */
11901 cookie.dmac_address = mpt->m_reply_frame_dma_addr;
11902 for (i = 0; i < mpt->m_max_replies; i++) {
11903 ddi_put32(mpt->m_acc_free_queue_hdl,
11904 &((uint32_t *)(void *)mpt->m_free_queue)[i],
11905 cookie.dmac_address);
11906 cookie.dmac_address += mpt->m_reply_frame_size;
11907 }
11908 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11909 DDI_DMA_SYNC_FORDEV);
11910
11911 /*
11912 * Initialize the reply free index to one past the last frame on the
11913 * queue. This will signify that the queue is empty to start with.
11914 */
11915 mpt->m_free_index = i;
11916 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
11917
11918 /*
11919 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
11920 */
11921 for (i = 0; i < mpt->m_post_queue_depth; i++) {
11922 ddi_put64(mpt->m_acc_post_queue_hdl,
11923 &((uint64_t *)(void *)mpt->m_post_queue)[i],
11924 0xFFFFFFFFFFFFFFFF);
11925 }
11926 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
11927 DDI_DMA_SYNC_FORDEV);
11928
11929 /*
11930 * Enable ports
11931 */
11932 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
11933 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
11934 goto fail;
11935 }
11936
11937 /*
11938 * enable events
11939 */
11940 if (mptsas_ioc_enable_event_notification(mpt)) {
11941 goto fail;
11942 }
11943
11944 /*
11945 * We need checks in attach and these.
11946 * chip_init is called in mult. places
11947 */
11948
11949 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11950 DDI_SUCCESS) ||
11951 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
11952 DDI_SUCCESS) ||
11953 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
11954 DDI_SUCCESS) ||
11955 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
11956 DDI_SUCCESS) ||
11957 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
11958 DDI_SUCCESS)) {
11959 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11960 goto fail;
11961 }
11962
11963 /* Check all acc handles */
11964 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
11965 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11966 DDI_SUCCESS) ||
11967 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
11968 DDI_SUCCESS) ||
11969 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
11970 DDI_SUCCESS) ||
11971 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
11972 DDI_SUCCESS) ||
11973 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
11974 DDI_SUCCESS) ||
11975 (mptsas_check_acc_handle(mpt->m_config_handle) !=
11976 DDI_SUCCESS)) {
11977 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11978 goto fail;
11979 }
11980
11981 return (DDI_SUCCESS);
11982
11983 fail:
11984 return (DDI_FAILURE);
11985 }
11986
11987 static int
11988 mptsas_get_pci_cap(mptsas_t *mpt)
11989 {
11990 ushort_t caps_ptr, cap, cap_count;
11991
11992 if (mpt->m_config_handle == NULL)
11993 return (FALSE);
11994 /*
11995 * Check if capabilities list is supported and if so,
11996 * get initial capabilities pointer and clear bits 0,1.
11997 */
11998 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
11999 & PCI_STAT_CAP) {
12000 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12001 PCI_CONF_CAP_PTR), 4);
12002 } else {
12003 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
12004 }
12005
12006 /*
12007 * Walk capabilities if supported.
12008 */
12009 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
12010
12011 /*
12012 * Check that we haven't exceeded the maximum number of
12013 * capabilities and that the pointer is in a valid range.
12014 */
12015 if (++cap_count > 48) {
12016 mptsas_log(mpt, CE_WARN,
12017 "too many device capabilities.\n");
12018 break;
12019 }
12020 if (caps_ptr < 64) {
12021 mptsas_log(mpt, CE_WARN,
12022 "capabilities pointer 0x%x out of range.\n",
12023 caps_ptr);
12024 break;
12025 }
12026
12027 /*
12028 * Get next capability and check that it is valid.
12029 * For now, we only support power management.
12030 */
12031 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
12032 switch (cap) {
12033 case PCI_CAP_ID_PM:
12034 mptsas_log(mpt, CE_NOTE,
12035 "?mptsas%d supports power management.\n",
12036 mpt->m_instance);
12037 mpt->m_options |= MPTSAS_OPT_PM;
12038
12039 /* Save PMCSR offset */
12040 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
12041 break;
12042 /*
12043 * The following capabilities are valid. Any others
12044 * will cause a message to be logged.
12045 */
12046 case PCI_CAP_ID_VPD:
12047 case PCI_CAP_ID_MSI:
12048 case PCI_CAP_ID_PCIX:
12049 case PCI_CAP_ID_PCI_E:
12050 case PCI_CAP_ID_MSI_X:
12051 break;
12052 default:
12053 mptsas_log(mpt, CE_NOTE,
12054 "?mptsas%d unrecognized capability "
12055 "0x%x.\n", mpt->m_instance, cap);
12056 break;
12057 }
12058
12059 /*
12060 * Get next capabilities pointer and clear bits 0,1.
12061 */
12062 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
12063 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
12064 }
12065 return (TRUE);
12066 }
12067
12068 static int
12069 mptsas_init_pm(mptsas_t *mpt)
12070 {
12071 char pmc_name[16];
12072 char *pmc[] = {
12073 NULL,
12074 "0=Off (PCI D3 State)",
12075 "3=On (PCI D0 State)",
12076 NULL
12077 };
12078 uint16_t pmcsr_stat;
12079
12080 if (mptsas_get_pci_cap(mpt) == FALSE) {
12081 return (DDI_FAILURE);
12082 }
12083 /*
12084 * If PCI's capability does not support PM, then don't need
12085 * to registe the pm-components
12086 */
12087 if (!(mpt->m_options & MPTSAS_OPT_PM))
12088 return (DDI_SUCCESS);
12089 /*
12090 * If power management is supported by this chip, create
12091 * pm-components property for the power management framework
12092 */
12093 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
12094 pmc[0] = pmc_name;
12095 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
12096 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
12097 mpt->m_options &= ~MPTSAS_OPT_PM;
12098 mptsas_log(mpt, CE_WARN,
12099 "mptsas%d: pm-component property creation failed.",
12100 mpt->m_instance);
12101 return (DDI_FAILURE);
12102 }
12103
12104 /*
12105 * Power on device.
12106 */
12107 (void) pm_busy_component(mpt->m_dip, 0);
12108 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
12109 mpt->m_pmcsr_offset);
12110 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
12111 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
12112 mpt->m_instance);
12113 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
12114 PCI_PMCSR_D0);
12115 }
12116 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
12117 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
12118 return (DDI_FAILURE);
12119 }
12120 mpt->m_power_level = PM_LEVEL_D0;
12121 /*
12122 * Set pm idle delay.
12123 */
12124 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
12125 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
12126
12127 return (DDI_SUCCESS);
12128 }
12129
12130 static int
12131 mptsas_register_intrs(mptsas_t *mpt)
12132 {
12133 dev_info_t *dip;
12134 int intr_types;
12135
12136 dip = mpt->m_dip;
12137
12138 /* Get supported interrupt types */
12139 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
12140 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
12141 "failed\n");
12142 return (FALSE);
12143 }
12144
12145 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
12146
12147 /*
12148 * Try MSI, but fall back to FIXED
12149 */
12150 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
12151 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
12152 NDBG0(("Using MSI interrupt type"));
12153 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
12154 return (TRUE);
12155 }
12156 }
12157 if (intr_types & DDI_INTR_TYPE_FIXED) {
12158 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
12159 NDBG0(("Using FIXED interrupt type"));
12160 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
12161 return (TRUE);
12162 } else {
12163 NDBG0(("FIXED interrupt registration failed"));
12164 return (FALSE);
12165 }
12166 }
12167
12168 return (FALSE);
12169 }
12170
12171 static void
12172 mptsas_unregister_intrs(mptsas_t *mpt)
12173 {
12174 mptsas_rem_intrs(mpt);
12175 }
12176
12177 /*
12178 * mptsas_add_intrs:
12179 *
12180 * Register FIXED or MSI interrupts.
12181 */
12182 static int
12183 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
12184 {
12185 dev_info_t *dip = mpt->m_dip;
12186 int avail, actual, count = 0;
12187 int i, flag, ret;
12188
12189 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
12190
12191 /* Get number of interrupts */
12192 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
12193 if ((ret != DDI_SUCCESS) || (count <= 0)) {
12194 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
12195 "ret %d count %d\n", ret, count);
12196
12197 return (DDI_FAILURE);
12198 }
12199
12200 /* Get number of available interrupts */
12201 ret = ddi_intr_get_navail(dip, intr_type, &avail);
12202 if ((ret != DDI_SUCCESS) || (avail == 0)) {
12203 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
12204 "ret %d avail %d\n", ret, avail);
12205
12206 return (DDI_FAILURE);
12207 }
12208
12209 if (avail < count) {
12210 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
12211 "navail() returned %d", count, avail);
12212 }
12213
12214 /* Mpt only have one interrupt routine */
12215 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
12216 count = 1;
12217 }
12218
12219 /* Allocate an array of interrupt handles */
12220 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
12221 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
12222
12223 flag = DDI_INTR_ALLOC_NORMAL;
12224
12225 /* call ddi_intr_alloc() */
12226 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
12227 count, &actual, flag);
12228
12229 if ((ret != DDI_SUCCESS) || (actual == 0)) {
12230 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
12231 ret);
12232 kmem_free(mpt->m_htable, mpt->m_intr_size);
12233 return (DDI_FAILURE);
12234 }
12235
12236 /* use interrupt count returned or abort? */
12237 if (actual < count) {
12238 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
12239 count, actual);
12240 }
12241
12242 mpt->m_intr_cnt = actual;
12243
12244 /*
12245 * Get priority for first msi, assume remaining are all the same
12246 */
12247 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
12248 &mpt->m_intr_pri)) != DDI_SUCCESS) {
12249 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
12250
12251 /* Free already allocated intr */
12252 for (i = 0; i < actual; i++) {
12253 (void) ddi_intr_free(mpt->m_htable[i]);
12254 }
12255
12256 kmem_free(mpt->m_htable, mpt->m_intr_size);
12257 return (DDI_FAILURE);
12258 }
12259
12260 /* Test for high level mutex */
12261 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
12262 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
12263 "Hi level interrupt not supported\n");
12264
12265 /* Free already allocated intr */
12266 for (i = 0; i < actual; i++) {
12267 (void) ddi_intr_free(mpt->m_htable[i]);
12268 }
12269
12270 kmem_free(mpt->m_htable, mpt->m_intr_size);
12271 return (DDI_FAILURE);
12272 }
12273
12274 /* Call ddi_intr_add_handler() */
12275 for (i = 0; i < actual; i++) {
12276 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
12277 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
12278 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
12279 "failed %d\n", ret);
12280
12281 /* Free already allocated intr */
12282 for (i = 0; i < actual; i++) {
12283 (void) ddi_intr_free(mpt->m_htable[i]);
12284 }
12285
12286 kmem_free(mpt->m_htable, mpt->m_intr_size);
12287 return (DDI_FAILURE);
12288 }
12289 }
12290
12291 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
12292 != DDI_SUCCESS) {
12293 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
12294
12295 /* Free already allocated intr */
12296 for (i = 0; i < actual; i++) {
12297 (void) ddi_intr_free(mpt->m_htable[i]);
12298 }
12299
12300 kmem_free(mpt->m_htable, mpt->m_intr_size);
12301 return (DDI_FAILURE);
12302 }
12303
12304 /*
12305 * Enable interrupts
12306 */
12307 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12308 /* Call ddi_intr_block_enable() for MSI interrupts */
12309 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
12310 } else {
12311 /* Call ddi_intr_enable for MSI or FIXED interrupts */
12312 for (i = 0; i < mpt->m_intr_cnt; i++) {
12313 (void) ddi_intr_enable(mpt->m_htable[i]);
12314 }
12315 }
12316 return (DDI_SUCCESS);
12317 }
12318
12319 /*
12320 * mptsas_rem_intrs:
12321 *
12322 * Unregister FIXED or MSI interrupts
12323 */
12324 static void
12325 mptsas_rem_intrs(mptsas_t *mpt)
12326 {
12327 int i;
12328
12329 NDBG6(("mptsas_rem_intrs"));
12330
12331 /* Disable all interrupts */
12332 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
12333 /* Call ddi_intr_block_disable() */
12334 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
12335 } else {
12336 for (i = 0; i < mpt->m_intr_cnt; i++) {
12337 (void) ddi_intr_disable(mpt->m_htable[i]);
12338 }
12339 }
12340
12341 /* Call ddi_intr_remove_handler() */
12342 for (i = 0; i < mpt->m_intr_cnt; i++) {
12343 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
12344 (void) ddi_intr_free(mpt->m_htable[i]);
12345 }
12346
12347 kmem_free(mpt->m_htable, mpt->m_intr_size);
12348 }
12349
12350 /*
12351 * The IO fault service error handling callback function
12352 */
12353 /*ARGSUSED*/
12354 static int
12355 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
12356 {
12357 /*
12358 * as the driver can always deal with an error in any dma or
12359 * access handle, we can just return the fme_status value.
12360 */
12361 pci_ereport_post(dip, err, NULL);
12362 return (err->fme_status);
12363 }
12364
12365 /*
12366 * mptsas_fm_init - initialize fma capabilities and register with IO
12367 * fault services.
12368 */
12369 static void
12370 mptsas_fm_init(mptsas_t *mpt)
12371 {
12372 /*
12373 * Need to change iblock to priority for new MSI intr
12374 */
12375 ddi_iblock_cookie_t fm_ibc;
12376
12377 /* Only register with IO Fault Services if we have some capability */
12378 if (mpt->m_fm_capabilities) {
12379 /* Adjust access and dma attributes for FMA */
12380 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
12381 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12382 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
12383
12384 /*
12385 * Register capabilities with IO Fault Services.
12386 * mpt->m_fm_capabilities will be updated to indicate
12387 * capabilities actually supported (not requested.)
12388 */
12389 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
12390
12391 /*
12392 * Initialize pci ereport capabilities if ereport
12393 * capable (should always be.)
12394 */
12395 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12396 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12397 pci_ereport_setup(mpt->m_dip);
12398 }
12399
12400 /*
12401 * Register error callback if error callback capable.
12402 */
12403 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12404 ddi_fm_handler_register(mpt->m_dip,
12405 mptsas_fm_error_cb, (void *) mpt);
12406 }
12407 }
12408 }
12409
12410 /*
12411 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
12412 * fault services.
12413 *
12414 */
12415 static void
12416 mptsas_fm_fini(mptsas_t *mpt)
12417 {
12418 /* Only unregister FMA capabilities if registered */
12419 if (mpt->m_fm_capabilities) {
12420
12421 /*
12422 * Un-register error callback if error callback capable.
12423 */
12424
12425 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12426 ddi_fm_handler_unregister(mpt->m_dip);
12427 }
12428
12429 /*
12430 * Release any resources allocated by pci_ereport_setup()
12431 */
12432
12433 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
12434 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
12435 pci_ereport_teardown(mpt->m_dip);
12436 }
12437
12438 /* Unregister from IO Fault Services */
12439 ddi_fm_fini(mpt->m_dip);
12440
12441 /* Adjust access and dma attributes for FMA */
12442 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
12443 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12444 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
12445
12446 }
12447 }
12448
12449 int
12450 mptsas_check_acc_handle(ddi_acc_handle_t handle)
12451 {
12452 ddi_fm_error_t de;
12453
12454 if (handle == NULL)
12455 return (DDI_FAILURE);
12456 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
12457 return (de.fme_status);
12458 }
12459
12460 int
12461 mptsas_check_dma_handle(ddi_dma_handle_t handle)
12462 {
12463 ddi_fm_error_t de;
12464
12465 if (handle == NULL)
12466 return (DDI_FAILURE);
12467 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
12468 return (de.fme_status);
12469 }
12470
12471 void
12472 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
12473 {
12474 uint64_t ena;
12475 char buf[FM_MAX_CLASS];
12476
12477 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
12478 ena = fm_ena_generate(0, FM_ENA_FMT1);
12479 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
12480 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
12481 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
12482 }
12483 }
12484
12485 static int
12486 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
12487 uint16_t *dev_handle, mptsas_target_t **pptgt)
12488 {
12489 int rval;
12490 uint32_t dev_info;
12491 uint64_t sas_wwn;
12492 mptsas_phymask_t phymask;
12493 uint8_t physport, phynum, config, disk;
12494 mptsas_slots_t *slots = mpt->m_active;
12495 uint64_t devicename;
12496 uint16_t pdev_hdl;
12497 mptsas_target_t *tmp_tgt = NULL;
12498 uint16_t bay_num, enclosure;
12499
12500 ASSERT(*pptgt == NULL);
12501
12502 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
12503 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
12504 &bay_num, &enclosure);
12505 if (rval != DDI_SUCCESS) {
12506 rval = DEV_INFO_FAIL_PAGE0;
12507 return (rval);
12508 }
12509
12510 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
12511 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12512 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
12513 rval = DEV_INFO_WRONG_DEVICE_TYPE;
12514 return (rval);
12515 }
12516
12517 /*
12518 * Check if the dev handle is for a Phys Disk. If so, set return value
12519 * and exit. Don't add Phys Disks to hash.
12520 */
12521 for (config = 0; config < slots->m_num_raid_configs; config++) {
12522 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
12523 if (*dev_handle == slots->m_raidconfig[config].
12524 m_physdisk_devhdl[disk]) {
12525 rval = DEV_INFO_PHYS_DISK;
12526 return (rval);
12527 }
12528 }
12529 }
12530
12531 /*
12532 * Get SATA Device Name from SAS device page0 for
12533 * sata device, if device name doesn't exist, set m_sas_wwn to
12534 * 0 for direct attached SATA. For the device behind the expander
12535 * we still can use STP address assigned by expander.
12536 */
12537 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
12538 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
12539 mutex_exit(&mpt->m_mutex);
12540 /* alloc a tmp_tgt to send the cmd */
12541 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target),
12542 KM_SLEEP);
12543 tmp_tgt->m_devhdl = *dev_handle;
12544 tmp_tgt->m_deviceinfo = dev_info;
12545 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
12546 tmp_tgt->m_qfull_retry_interval =
12547 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
12548 tmp_tgt->m_t_throttle = MAX_THROTTLE;
12549 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
12550 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
12551 mutex_enter(&mpt->m_mutex);
12552 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
12553 sas_wwn = devicename;
12554 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
12555 sas_wwn = 0;
12556 }
12557 }
12558
12559 phymask = mptsas_physport_to_phymask(mpt, physport);
12560 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn,
12561 dev_info, phymask, phynum);
12562 if (*pptgt == NULL) {
12563 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
12564 "structure!");
12565 rval = DEV_INFO_FAIL_ALLOC;
12566 return (rval);
12567 }
12568 (*pptgt)->m_enclosure = enclosure;
12569 (*pptgt)->m_slot_num = bay_num;
12570 return (DEV_INFO_SUCCESS);
12571 }
12572
12573 uint64_t
12574 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
12575 {
12576 uint64_t sata_guid = 0, *pwwn = NULL;
12577 int target = ptgt->m_devhdl;
12578 uchar_t *inq83 = NULL;
12579 int inq83_len = 0xFF;
12580 uchar_t *dblk = NULL;
12581 int inq83_retry = 3;
12582 int rval = DDI_FAILURE;
12583
12584 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
12585
12586 inq83_retry:
12587 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
12588 inq83_len, NULL, 1);
12589 if (rval != DDI_SUCCESS) {
12590 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
12591 "0x83 for target:%x, lun:%x failed!", target, lun);
12592 goto out;
12593 }
12594 /* According to SAT2, the first descriptor is logic unit name */
12595 dblk = &inq83[4];
12596 if ((dblk[1] & 0x30) != 0) {
12597 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
12598 goto out;
12599 }
12600 pwwn = (uint64_t *)(void *)(&dblk[4]);
12601 if ((dblk[4] & 0xf0) == 0x50) {
12602 sata_guid = BE_64(*pwwn);
12603 goto out;
12604 } else if (dblk[4] == 'A') {
12605 NDBG20(("SATA drive has no NAA format GUID."));
12606 goto out;
12607 } else {
12608 /* The data is not ready, wait and retry */
12609 inq83_retry--;
12610 if (inq83_retry <= 0) {
12611 goto out;
12612 }
12613 NDBG20(("The GUID is not ready, retry..."));
12614 delay(1 * drv_usectohz(1000000));
12615 goto inq83_retry;
12616 }
12617 out:
12618 kmem_free(inq83, inq83_len);
12619 return (sata_guid);
12620 }
12621
12622 static int
12623 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
12624 unsigned char *buf, int len, int *reallen, uchar_t evpd)
12625 {
12626 uchar_t cdb[CDB_GROUP0];
12627 struct scsi_address ap;
12628 struct buf *data_bp = NULL;
12629 int resid = 0;
12630 int ret = DDI_FAILURE;
12631
12632 ASSERT(len <= 0xffff);
12633
12634 ap.a_target = MPTSAS_INVALID_DEVHDL;
12635 ap.a_lun = (uchar_t)(lun);
12636 ap.a_hba_tran = mpt->m_tran;
12637
12638 data_bp = scsi_alloc_consistent_buf(&ap,
12639 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
12640 if (data_bp == NULL) {
12641 return (ret);
12642 }
12643 bzero(cdb, CDB_GROUP0);
12644 cdb[0] = SCMD_INQUIRY;
12645 cdb[1] = evpd;
12646 cdb[2] = page;
12647 cdb[3] = (len & 0xff00) >> 8;
12648 cdb[4] = (len & 0x00ff);
12649 cdb[5] = 0;
12650
12651 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
12652 &resid);
12653 if (ret == DDI_SUCCESS) {
12654 if (reallen) {
12655 *reallen = len - resid;
12656 }
12657 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
12658 }
12659 if (data_bp) {
12660 scsi_free_consistent_buf(data_bp);
12661 }
12662 return (ret);
12663 }
12664
12665 static int
12666 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
12667 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
12668 int *resid)
12669 {
12670 struct scsi_pkt *pktp = NULL;
12671 scsi_hba_tran_t *tran_clone = NULL;
12672 mptsas_tgt_private_t *tgt_private = NULL;
12673 int ret = DDI_FAILURE;
12674
12675 /*
12676 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
12677 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
12678 * to simulate the cmds from sd
12679 */
12680 tran_clone = kmem_alloc(
12681 sizeof (scsi_hba_tran_t), KM_SLEEP);
12682 if (tran_clone == NULL) {
12683 goto out;
12684 }
12685 bcopy((caddr_t)mpt->m_tran,
12686 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
12687 tgt_private = kmem_alloc(
12688 sizeof (mptsas_tgt_private_t), KM_SLEEP);
12689 if (tgt_private == NULL) {
12690 goto out;
12691 }
12692 tgt_private->t_lun = ap->a_lun;
12693 tgt_private->t_private = ptgt;
12694 tran_clone->tran_tgt_private = tgt_private;
12695 ap->a_hba_tran = tran_clone;
12696
12697 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
12698 data_bp, cdblen, sizeof (struct scsi_arq_status),
12699 0, PKT_CONSISTENT, NULL, NULL);
12700 if (pktp == NULL) {
12701 goto out;
12702 }
12703 bcopy(cdb, pktp->pkt_cdbp, cdblen);
12704 pktp->pkt_flags = FLAG_NOPARITY;
12705 if (scsi_poll(pktp) < 0) {
12706 goto out;
12707 }
12708 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
12709 goto out;
12710 }
12711 if (resid != NULL) {
12712 *resid = pktp->pkt_resid;
12713 }
12714
12715 ret = DDI_SUCCESS;
12716 out:
12717 if (pktp) {
12718 scsi_destroy_pkt(pktp);
12719 }
12720 if (tran_clone) {
12721 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
12722 }
12723 if (tgt_private) {
12724 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
12725 }
12726 return (ret);
12727 }
12728 static int
12729 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
12730 {
12731 char *cp = NULL;
12732 char *ptr = NULL;
12733 size_t s = 0;
12734 char *wwid_str = NULL;
12735 char *lun_str = NULL;
12736 long lunnum;
12737 long phyid = -1;
12738 int rc = DDI_FAILURE;
12739
12740 ptr = name;
12741 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
12742 ptr++;
12743 if ((cp = strchr(ptr, ',')) == NULL) {
12744 return (DDI_FAILURE);
12745 }
12746
12747 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12748 s = (uintptr_t)cp - (uintptr_t)ptr;
12749
12750 bcopy(ptr, wwid_str, s);
12751 wwid_str[s] = '\0';
12752
12753 ptr = ++cp;
12754
12755 if ((cp = strchr(ptr, '\0')) == NULL) {
12756 goto out;
12757 }
12758 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12759 s = (uintptr_t)cp - (uintptr_t)ptr;
12760
12761 bcopy(ptr, lun_str, s);
12762 lun_str[s] = '\0';
12763
12764 if (name[0] == 'p') {
12765 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
12766 } else {
12767 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
12768 }
12769 if (rc != DDI_SUCCESS)
12770 goto out;
12771
12772 if (phyid != -1) {
12773 ASSERT(phyid < MPTSAS_MAX_PHYS);
12774 *phy = (uint8_t)phyid;
12775 }
12776 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
12777 if (rc != 0)
12778 goto out;
12779
12780 *lun = (int)lunnum;
12781 rc = DDI_SUCCESS;
12782 out:
12783 if (wwid_str)
12784 kmem_free(wwid_str, SCSI_MAXNAMELEN);
12785 if (lun_str)
12786 kmem_free(lun_str, SCSI_MAXNAMELEN);
12787
12788 return (rc);
12789 }
12790
12791 /*
12792 * mptsas_parse_smp_name() is to parse sas wwn string
12793 * which format is "wWWN"
12794 */
12795 static int
12796 mptsas_parse_smp_name(char *name, uint64_t *wwn)
12797 {
12798 char *ptr = name;
12799
12800 if (*ptr != 'w') {
12801 return (DDI_FAILURE);
12802 }
12803
12804 ptr++;
12805 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
12806 return (DDI_FAILURE);
12807 }
12808 return (DDI_SUCCESS);
12809 }
12810
12811 static int
12812 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
12813 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
12814 {
12815 int ret = NDI_FAILURE;
12816 int circ = 0;
12817 int circ1 = 0;
12818 mptsas_t *mpt;
12819 char *ptr = NULL;
12820 char *devnm = NULL;
12821 uint64_t wwid = 0;
12822 uint8_t phy = 0xFF;
12823 int lun = 0;
12824 uint_t mflags = flag;
12825 int bconfig = TRUE;
12826
12827 if (scsi_hba_iport_unit_address(pdip) == 0) {
12828 return (DDI_FAILURE);
12829 }
12830
12831 mpt = DIP2MPT(pdip);
12832 if (!mpt) {
12833 return (DDI_FAILURE);
12834 }
12835 /*
12836 * Hold the nexus across the bus_config
12837 */
12838 ndi_devi_enter(scsi_vhci_dip, &circ);
12839 ndi_devi_enter(pdip, &circ1);
12840 switch (op) {
12841 case BUS_CONFIG_ONE:
12842 /* parse wwid/target name out of name given */
12843 if ((ptr = strchr((char *)arg, '@')) == NULL) {
12844 ret = NDI_FAILURE;
12845 break;
12846 }
12847 ptr++;
12848 if (strncmp((char *)arg, "smp", 3) == 0) {
12849 /*
12850 * This is a SMP target device
12851 */
12852 ret = mptsas_parse_smp_name(ptr, &wwid);
12853 if (ret != DDI_SUCCESS) {
12854 ret = NDI_FAILURE;
12855 break;
12856 }
12857 ret = mptsas_config_smp(pdip, wwid, childp);
12858 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
12859 /*
12860 * OBP could pass down a non-canonical form
12861 * bootpath without LUN part when LUN is 0.
12862 * So driver need adjust the string.
12863 */
12864 if (strchr(ptr, ',') == NULL) {
12865 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
12866 (void) sprintf(devnm, "%s,0", (char *)arg);
12867 ptr = strchr(devnm, '@');
12868 ptr++;
12869 }
12870
12871 /*
12872 * The device path is wWWID format and the device
12873 * is not SMP target device.
12874 */
12875 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
12876 if (ret != DDI_SUCCESS) {
12877 ret = NDI_FAILURE;
12878 break;
12879 }
12880 *childp = NULL;
12881 if (ptr[0] == 'w') {
12882 ret = mptsas_config_one_addr(pdip, wwid,
12883 lun, childp);
12884 } else if (ptr[0] == 'p') {
12885 ret = mptsas_config_one_phy(pdip, phy, lun,
12886 childp);
12887 }
12888
12889 /*
12890 * If this is CD/DVD device in OBP path, the
12891 * ndi_busop_bus_config can be skipped as config one
12892 * operation is done above.
12893 */
12894 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
12895 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
12896 (strncmp((char *)arg, "disk", 4) == 0)) {
12897 bconfig = FALSE;
12898 ndi_hold_devi(*childp);
12899 }
12900 } else {
12901 ret = NDI_FAILURE;
12902 break;
12903 }
12904
12905 /*
12906 * DDI group instructed us to use this flag.
12907 */
12908 mflags |= NDI_MDI_FALLBACK;
12909 break;
12910 case BUS_CONFIG_DRIVER:
12911 case BUS_CONFIG_ALL:
12912 mptsas_config_all(pdip);
12913 ret = NDI_SUCCESS;
12914 break;
12915 }
12916
12917 if ((ret == NDI_SUCCESS) && bconfig) {
12918 ret = ndi_busop_bus_config(pdip, mflags, op,
12919 (devnm == NULL) ? arg : devnm, childp, 0);
12920 }
12921
12922 ndi_devi_exit(pdip, circ1);
12923 ndi_devi_exit(scsi_vhci_dip, circ);
12924 if (devnm != NULL)
12925 kmem_free(devnm, SCSI_MAXNAMELEN);
12926 return (ret);
12927 }
12928
12929 static int
12930 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
12931 mptsas_target_t *ptgt)
12932 {
12933 int rval = DDI_FAILURE;
12934 struct scsi_inquiry *sd_inq = NULL;
12935 mptsas_t *mpt = DIP2MPT(pdip);
12936
12937 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
12938
12939 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
12940 SUN_INQSIZE, 0, (uchar_t)0);
12941
12942 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
12943 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
12944 } else {
12945 rval = DDI_FAILURE;
12946 }
12947
12948 kmem_free(sd_inq, SUN_INQSIZE);
12949 return (rval);
12950 }
12951
12952 static int
12953 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
12954 dev_info_t **lundip)
12955 {
12956 int rval;
12957 mptsas_t *mpt = DIP2MPT(pdip);
12958 int phymask;
12959 mptsas_target_t *ptgt = NULL;
12960
12961 /*
12962 * Get the physical port associated to the iport
12963 */
12964 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
12965 "phymask", 0);
12966
12967 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
12968 if (ptgt == NULL) {
12969 /*
12970 * didn't match any device by searching
12971 */
12972 return (DDI_FAILURE);
12973 }
12974 /*
12975 * If the LUN already exists and the status is online,
12976 * we just return the pointer to dev_info_t directly.
12977 * For the mdi_pathinfo node, we'll handle it in
12978 * mptsas_create_virt_lun()
12979 * TODO should be also in mptsas_handle_dr
12980 */
12981
12982 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
12983 if (*lundip != NULL) {
12984 /*
12985 * TODO Another senario is, we hotplug the same disk
12986 * on the same slot, the devhdl changed, is this
12987 * possible?
12988 * tgt_private->t_private != ptgt
12989 */
12990 if (sasaddr != ptgt->m_sas_wwn) {
12991 /*
12992 * The device has changed although the devhdl is the
12993 * same (Enclosure mapping mode, change drive on the
12994 * same slot)
12995 */
12996 return (DDI_FAILURE);
12997 }
12998 return (DDI_SUCCESS);
12999 }
13000
13001 if (phymask == 0) {
13002 /*
13003 * Configure IR volume
13004 */
13005 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
13006 return (rval);
13007 }
13008 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13009
13010 return (rval);
13011 }
13012
13013 static int
13014 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
13015 dev_info_t **lundip)
13016 {
13017 int rval;
13018 mptsas_t *mpt = DIP2MPT(pdip);
13019 int phymask;
13020 mptsas_target_t *ptgt = NULL;
13021
13022 /*
13023 * Get the physical port associated to the iport
13024 */
13025 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13026 "phymask", 0);
13027
13028 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
13029 if (ptgt == NULL) {
13030 /*
13031 * didn't match any device by searching
13032 */
13033 return (DDI_FAILURE);
13034 }
13035
13036 /*
13037 * If the LUN already exists and the status is online,
13038 * we just return the pointer to dev_info_t directly.
13039 * For the mdi_pathinfo node, we'll handle it in
13040 * mptsas_create_virt_lun().
13041 */
13042
13043 *lundip = mptsas_find_child_phy(pdip, phy);
13044 if (*lundip != NULL) {
13045 return (DDI_SUCCESS);
13046 }
13047
13048 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
13049
13050 return (rval);
13051 }
13052
13053 static int
13054 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
13055 uint8_t *lun_addr_type)
13056 {
13057 uint32_t lun_idx = 0;
13058
13059 ASSERT(lun_num != NULL);
13060 ASSERT(lun_addr_type != NULL);
13061
13062 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13063 /* determine report luns addressing type */
13064 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
13065 /*
13066 * Vendors in the field have been found to be concatenating
13067 * bus/target/lun to equal the complete lun value instead
13068 * of switching to flat space addressing
13069 */
13070 /* 00b - peripheral device addressing method */
13071 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
13072 /* FALLTHRU */
13073 /* 10b - logical unit addressing method */
13074 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
13075 /* FALLTHRU */
13076 /* 01b - flat space addressing method */
13077 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
13078 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
13079 *lun_addr_type = (buf[lun_idx] &
13080 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
13081 *lun_num = (buf[lun_idx] & 0x3F) << 8;
13082 *lun_num |= buf[lun_idx + 1];
13083 return (DDI_SUCCESS);
13084 default:
13085 return (DDI_FAILURE);
13086 }
13087 }
13088
13089 static int
13090 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
13091 {
13092 struct buf *repluns_bp = NULL;
13093 struct scsi_address ap;
13094 uchar_t cdb[CDB_GROUP5];
13095 int ret = DDI_FAILURE;
13096 int retry = 0;
13097 int lun_list_len = 0;
13098 uint16_t lun_num = 0;
13099 uint8_t lun_addr_type = 0;
13100 uint32_t lun_cnt = 0;
13101 uint32_t lun_total = 0;
13102 dev_info_t *cdip = NULL;
13103 uint16_t *saved_repluns = NULL;
13104 char *buffer = NULL;
13105 int buf_len = 128;
13106 mptsas_t *mpt = DIP2MPT(pdip);
13107 uint64_t sas_wwn = 0;
13108 uint8_t phy = 0xFF;
13109 uint32_t dev_info = 0;
13110
13111 mutex_enter(&mpt->m_mutex);
13112 sas_wwn = ptgt->m_sas_wwn;
13113 phy = ptgt->m_phynum;
13114 dev_info = ptgt->m_deviceinfo;
13115 mutex_exit(&mpt->m_mutex);
13116
13117 if (sas_wwn == 0) {
13118 /*
13119 * It's a SATA without Device Name
13120 * So don't try multi-LUNs
13121 */
13122 if (mptsas_find_child_phy(pdip, phy)) {
13123 return (DDI_SUCCESS);
13124 } else {
13125 /*
13126 * need configure and create node
13127 */
13128 return (DDI_FAILURE);
13129 }
13130 }
13131
13132 /*
13133 * WWN (SAS address or Device Name exist)
13134 */
13135 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13136 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13137 /*
13138 * SATA device with Device Name
13139 * So don't try multi-LUNs
13140 */
13141 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
13142 return (DDI_SUCCESS);
13143 } else {
13144 return (DDI_FAILURE);
13145 }
13146 }
13147
13148 do {
13149 ap.a_target = MPTSAS_INVALID_DEVHDL;
13150 ap.a_lun = 0;
13151 ap.a_hba_tran = mpt->m_tran;
13152 repluns_bp = scsi_alloc_consistent_buf(&ap,
13153 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
13154 if (repluns_bp == NULL) {
13155 retry++;
13156 continue;
13157 }
13158 bzero(cdb, CDB_GROUP5);
13159 cdb[0] = SCMD_REPORT_LUNS;
13160 cdb[6] = (buf_len & 0xff000000) >> 24;
13161 cdb[7] = (buf_len & 0x00ff0000) >> 16;
13162 cdb[8] = (buf_len & 0x0000ff00) >> 8;
13163 cdb[9] = (buf_len & 0x000000ff);
13164
13165 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
13166 repluns_bp, NULL);
13167 if (ret != DDI_SUCCESS) {
13168 scsi_free_consistent_buf(repluns_bp);
13169 retry++;
13170 continue;
13171 }
13172 lun_list_len = BE_32(*(int *)((void *)(
13173 repluns_bp->b_un.b_addr)));
13174 if (buf_len >= lun_list_len + 8) {
13175 ret = DDI_SUCCESS;
13176 break;
13177 }
13178 scsi_free_consistent_buf(repluns_bp);
13179 buf_len = lun_list_len + 8;
13180
13181 } while (retry < 3);
13182
13183 if (ret != DDI_SUCCESS)
13184 return (ret);
13185 buffer = (char *)repluns_bp->b_un.b_addr;
13186 /*
13187 * find out the number of luns returned by the SCSI ReportLun call
13188 * and allocate buffer space
13189 */
13190 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
13191 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
13192 if (saved_repluns == NULL) {
13193 scsi_free_consistent_buf(repluns_bp);
13194 return (DDI_FAILURE);
13195 }
13196 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
13197 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
13198 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
13199 continue;
13200 }
13201 saved_repluns[lun_cnt] = lun_num;
13202 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
13203 ret = DDI_SUCCESS;
13204 else
13205 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
13206 ptgt);
13207 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
13208 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
13209 MPTSAS_DEV_GONE);
13210 }
13211 }
13212 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
13213 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
13214 scsi_free_consistent_buf(repluns_bp);
13215 return (DDI_SUCCESS);
13216 }
13217
13218 static int
13219 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
13220 {
13221 int rval = DDI_FAILURE;
13222 struct scsi_inquiry *sd_inq = NULL;
13223 mptsas_t *mpt = DIP2MPT(pdip);
13224 mptsas_target_t *ptgt = NULL;
13225
13226 mutex_enter(&mpt->m_mutex);
13227 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target);
13228 mutex_exit(&mpt->m_mutex);
13229 if (ptgt == NULL) {
13230 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
13231 "not found.", target);
13232 return (rval);
13233 }
13234
13235 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
13236 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
13237 SUN_INQSIZE, 0, (uchar_t)0);
13238
13239 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
13240 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
13241 0);
13242 } else {
13243 rval = DDI_FAILURE;
13244 }
13245
13246 kmem_free(sd_inq, SUN_INQSIZE);
13247 return (rval);
13248 }
13249
13250 /*
13251 * configure all RAID volumes for virtual iport
13252 */
13253 static void
13254 mptsas_config_all_viport(dev_info_t *pdip)
13255 {
13256 mptsas_t *mpt = DIP2MPT(pdip);
13257 int config, vol;
13258 int target;
13259 dev_info_t *lundip = NULL;
13260 mptsas_slots_t *slots = mpt->m_active;
13261
13262 /*
13263 * Get latest RAID info and search for any Volume DevHandles. If any
13264 * are found, configure the volume.
13265 */
13266 mutex_enter(&mpt->m_mutex);
13267 for (config = 0; config < slots->m_num_raid_configs; config++) {
13268 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
13269 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid
13270 == 1) {
13271 target = slots->m_raidconfig[config].
13272 m_raidvol[vol].m_raidhandle;
13273 mutex_exit(&mpt->m_mutex);
13274 (void) mptsas_config_raid(pdip, target,
13275 &lundip);
13276 mutex_enter(&mpt->m_mutex);
13277 }
13278 }
13279 }
13280 mutex_exit(&mpt->m_mutex);
13281 }
13282
13283 static void
13284 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
13285 int lun_cnt, mptsas_target_t *ptgt)
13286 {
13287 dev_info_t *child = NULL, *savechild = NULL;
13288 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13289 uint64_t sas_wwn, wwid;
13290 uint8_t phy;
13291 int lun;
13292 int i;
13293 int find;
13294 char *addr;
13295 char *nodename;
13296 mptsas_t *mpt = DIP2MPT(pdip);
13297
13298 mutex_enter(&mpt->m_mutex);
13299 wwid = ptgt->m_sas_wwn;
13300 mutex_exit(&mpt->m_mutex);
13301
13302 child = ddi_get_child(pdip);
13303 while (child) {
13304 find = 0;
13305 savechild = child;
13306 child = ddi_get_next_sibling(child);
13307
13308 nodename = ddi_node_name(savechild);
13309 if (strcmp(nodename, "smp") == 0) {
13310 continue;
13311 }
13312
13313 addr = ddi_get_name_addr(savechild);
13314 if (addr == NULL) {
13315 continue;
13316 }
13317
13318 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
13319 DDI_SUCCESS) {
13320 continue;
13321 }
13322
13323 if (wwid == sas_wwn) {
13324 for (i = 0; i < lun_cnt; i++) {
13325 if (repluns[i] == lun) {
13326 find = 1;
13327 break;
13328 }
13329 }
13330 } else {
13331 continue;
13332 }
13333 if (find == 0) {
13334 /*
13335 * The lun has not been there already
13336 */
13337 (void) mptsas_offline_lun(pdip, savechild, NULL,
13338 NDI_DEVI_REMOVE);
13339 }
13340 }
13341
13342 pip = mdi_get_next_client_path(pdip, NULL);
13343 while (pip) {
13344 find = 0;
13345 savepip = pip;
13346 addr = MDI_PI(pip)->pi_addr;
13347
13348 pip = mdi_get_next_client_path(pdip, pip);
13349
13350 if (addr == NULL) {
13351 continue;
13352 }
13353
13354 if (mptsas_parse_address(addr, &sas_wwn, &phy,
13355 &lun) != DDI_SUCCESS) {
13356 continue;
13357 }
13358
13359 if (sas_wwn == wwid) {
13360 for (i = 0; i < lun_cnt; i++) {
13361 if (repluns[i] == lun) {
13362 find = 1;
13363 break;
13364 }
13365 }
13366 } else {
13367 continue;
13368 }
13369
13370 if (find == 0) {
13371 /*
13372 * The lun has not been there already
13373 */
13374 (void) mptsas_offline_lun(pdip, NULL, savepip,
13375 NDI_DEVI_REMOVE);
13376 }
13377 }
13378 }
13379
13380 void
13381 mptsas_update_hashtab(struct mptsas *mpt)
13382 {
13383 uint32_t page_address;
13384 int rval = 0;
13385 uint16_t dev_handle;
13386 mptsas_target_t *ptgt = NULL;
13387 mptsas_smp_t smp_node;
13388
13389 /*
13390 * Get latest RAID info.
13391 */
13392 (void) mptsas_get_raid_info(mpt);
13393
13394 dev_handle = mpt->m_smp_devhdl;
13395 for (; mpt->m_done_traverse_smp == 0; ) {
13396 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
13397 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
13398 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
13399 != DDI_SUCCESS) {
13400 break;
13401 }
13402 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
13403 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
13404 }
13405
13406 /*
13407 * Config target devices
13408 */
13409 dev_handle = mpt->m_dev_handle;
13410
13411 /*
13412 * Do loop to get sas device page 0 by GetNextHandle till the
13413 * the last handle. If the sas device is a SATA/SSP target,
13414 * we try to config it.
13415 */
13416 for (; mpt->m_done_traverse_dev == 0; ) {
13417 ptgt = NULL;
13418 page_address =
13419 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
13420 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
13421 (uint32_t)dev_handle;
13422 rval = mptsas_get_target_device_info(mpt, page_address,
13423 &dev_handle, &ptgt);
13424 if ((rval == DEV_INFO_FAIL_PAGE0) ||
13425 (rval == DEV_INFO_FAIL_ALLOC)) {
13426 break;
13427 }
13428
13429 mpt->m_dev_handle = dev_handle;
13430 }
13431
13432 }
13433
13434 void
13435 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab)
13436 {
13437 mptsas_hash_data_t *data;
13438 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
13439 while (data != NULL) {
13440 data->devhdl = MPTSAS_INVALID_DEVHDL;
13441 data->device_info = 0;
13442 /*
13443 * For tgttbl, clear dr_flag.
13444 */
13445 data->dr_flag = MPTSAS_DR_INACTIVE;
13446 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
13447 }
13448 }
13449
13450 void
13451 mptsas_update_driver_data(struct mptsas *mpt)
13452 {
13453 /*
13454 * TODO after hard reset, update the driver data structures
13455 * 1. update port/phymask mapping table mpt->m_phy_info
13456 * 2. invalid all the entries in hash table
13457 * m_devhdl = 0xffff and m_deviceinfo = 0
13458 * 3. call sas_device_page/expander_page to update hash table
13459 */
13460 mptsas_update_phymask(mpt);
13461 /*
13462 * Invalid the existing entries
13463 */
13464 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl);
13465 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl);
13466 mpt->m_done_traverse_dev = 0;
13467 mpt->m_done_traverse_smp = 0;
13468 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
13469 mptsas_update_hashtab(mpt);
13470 }
13471
13472 static void
13473 mptsas_config_all(dev_info_t *pdip)
13474 {
13475 dev_info_t *smpdip = NULL;
13476 mptsas_t *mpt = DIP2MPT(pdip);
13477 int phymask = 0;
13478 mptsas_phymask_t phy_mask;
13479 mptsas_target_t *ptgt = NULL;
13480 mptsas_smp_t *psmp;
13481
13482 /*
13483 * Get the phymask associated to the iport
13484 */
13485 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
13486 "phymask", 0);
13487
13488 /*
13489 * Enumerate RAID volumes here (phymask == 0).
13490 */
13491 if (phymask == 0) {
13492 mptsas_config_all_viport(pdip);
13493 return;
13494 }
13495
13496 mutex_enter(&mpt->m_mutex);
13497
13498 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
13499 mptsas_update_hashtab(mpt);
13500 }
13501
13502 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl,
13503 MPTSAS_HASH_FIRST);
13504 while (psmp != NULL) {
13505 phy_mask = psmp->m_phymask;
13506 if (phy_mask == phymask) {
13507 smpdip = NULL;
13508 mutex_exit(&mpt->m_mutex);
13509 (void) mptsas_online_smp(pdip, psmp, &smpdip);
13510 mutex_enter(&mpt->m_mutex);
13511 }
13512 psmp = (mptsas_smp_t *)mptsas_hash_traverse(
13513 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT);
13514 }
13515
13516 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
13517 MPTSAS_HASH_FIRST);
13518 while (ptgt != NULL) {
13519 phy_mask = ptgt->m_phymask;
13520 if (phy_mask == phymask) {
13521 mutex_exit(&mpt->m_mutex);
13522 (void) mptsas_config_target(pdip, ptgt);
13523 mutex_enter(&mpt->m_mutex);
13524 }
13525
13526 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
13527 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
13528 }
13529 mutex_exit(&mpt->m_mutex);
13530 }
13531
13532 static int
13533 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
13534 {
13535 int rval = DDI_FAILURE;
13536 dev_info_t *tdip;
13537
13538 rval = mptsas_config_luns(pdip, ptgt);
13539 if (rval != DDI_SUCCESS) {
13540 /*
13541 * The return value means the SCMD_REPORT_LUNS
13542 * did not execute successfully. The target maybe
13543 * doesn't support such command.
13544 */
13545 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
13546 }
13547 return (rval);
13548 }
13549
13550 /*
13551 * Return fail if not all the childs/paths are freed.
13552 * if there is any path under the HBA, the return value will be always fail
13553 * because we didn't call mdi_pi_free for path
13554 */
13555 static int
13556 mptsas_offline_target(dev_info_t *pdip, char *name)
13557 {
13558 dev_info_t *child = NULL, *prechild = NULL;
13559 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
13560 int tmp_rval, rval = DDI_SUCCESS;
13561 char *addr, *cp;
13562 size_t s;
13563 mptsas_t *mpt = DIP2MPT(pdip);
13564
13565 child = ddi_get_child(pdip);
13566 while (child) {
13567 addr = ddi_get_name_addr(child);
13568 prechild = child;
13569 child = ddi_get_next_sibling(child);
13570
13571 if (addr == NULL) {
13572 continue;
13573 }
13574 if ((cp = strchr(addr, ',')) == NULL) {
13575 continue;
13576 }
13577
13578 s = (uintptr_t)cp - (uintptr_t)addr;
13579
13580 if (strncmp(addr, name, s) != 0) {
13581 continue;
13582 }
13583
13584 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
13585 NDI_DEVI_REMOVE);
13586 if (tmp_rval != DDI_SUCCESS) {
13587 rval = DDI_FAILURE;
13588 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
13589 prechild, MPTSAS_DEV_GONE) !=
13590 DDI_PROP_SUCCESS) {
13591 mptsas_log(mpt, CE_WARN, "mptsas driver "
13592 "unable to create property for "
13593 "SAS %s (MPTSAS_DEV_GONE)", addr);
13594 }
13595 }
13596 }
13597
13598 pip = mdi_get_next_client_path(pdip, NULL);
13599 while (pip) {
13600 addr = MDI_PI(pip)->pi_addr;
13601 savepip = pip;
13602 pip = mdi_get_next_client_path(pdip, pip);
13603 if (addr == NULL) {
13604 continue;
13605 }
13606
13607 if ((cp = strchr(addr, ',')) == NULL) {
13608 continue;
13609 }
13610
13611 s = (uintptr_t)cp - (uintptr_t)addr;
13612
13613 if (strncmp(addr, name, s) != 0) {
13614 continue;
13615 }
13616
13617 (void) mptsas_offline_lun(pdip, NULL, savepip,
13618 NDI_DEVI_REMOVE);
13619 /*
13620 * driver will not invoke mdi_pi_free, so path will not
13621 * be freed forever, return DDI_FAILURE.
13622 */
13623 rval = DDI_FAILURE;
13624 }
13625 return (rval);
13626 }
13627
13628 static int
13629 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
13630 mdi_pathinfo_t *rpip, uint_t flags)
13631 {
13632 int rval = DDI_FAILURE;
13633 char *devname;
13634 dev_info_t *cdip, *parent;
13635
13636 if (rpip != NULL) {
13637 parent = scsi_vhci_dip;
13638 cdip = mdi_pi_get_client(rpip);
13639 } else if (rdip != NULL) {
13640 parent = pdip;
13641 cdip = rdip;
13642 } else {
13643 return (DDI_FAILURE);
13644 }
13645
13646 /*
13647 * Make sure node is attached otherwise
13648 * it won't have related cache nodes to
13649 * clean up. i_ddi_devi_attached is
13650 * similiar to i_ddi_node_state(cdip) >=
13651 * DS_ATTACHED.
13652 */
13653 if (i_ddi_devi_attached(cdip)) {
13654
13655 /* Get full devname */
13656 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13657 (void) ddi_deviname(cdip, devname);
13658 /* Clean cache */
13659 (void) devfs_clean(parent, devname + 1,
13660 DV_CLEAN_FORCE);
13661 kmem_free(devname, MAXNAMELEN + 1);
13662 }
13663 if (rpip != NULL) {
13664 if (MDI_PI_IS_OFFLINE(rpip)) {
13665 rval = DDI_SUCCESS;
13666 } else {
13667 rval = mdi_pi_offline(rpip, 0);
13668 }
13669 } else {
13670 rval = ndi_devi_offline(cdip, flags);
13671 }
13672
13673 return (rval);
13674 }
13675
13676 static dev_info_t *
13677 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
13678 {
13679 dev_info_t *child = NULL;
13680 char *smp_wwn = NULL;
13681
13682 child = ddi_get_child(parent);
13683 while (child) {
13684 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
13685 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
13686 != DDI_SUCCESS) {
13687 child = ddi_get_next_sibling(child);
13688 continue;
13689 }
13690
13691 if (strcmp(smp_wwn, str_wwn) == 0) {
13692 ddi_prop_free(smp_wwn);
13693 break;
13694 }
13695 child = ddi_get_next_sibling(child);
13696 ddi_prop_free(smp_wwn);
13697 }
13698 return (child);
13699 }
13700
13701 static int
13702 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
13703 {
13704 int rval = DDI_FAILURE;
13705 char *devname;
13706 char wwn_str[MPTSAS_WWN_STRLEN];
13707 dev_info_t *cdip;
13708
13709 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
13710
13711 cdip = mptsas_find_smp_child(pdip, wwn_str);
13712
13713 if (cdip == NULL)
13714 return (DDI_SUCCESS);
13715
13716 /*
13717 * Make sure node is attached otherwise
13718 * it won't have related cache nodes to
13719 * clean up. i_ddi_devi_attached is
13720 * similiar to i_ddi_node_state(cdip) >=
13721 * DS_ATTACHED.
13722 */
13723 if (i_ddi_devi_attached(cdip)) {
13724
13725 /* Get full devname */
13726 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
13727 (void) ddi_deviname(cdip, devname);
13728 /* Clean cache */
13729 (void) devfs_clean(pdip, devname + 1,
13730 DV_CLEAN_FORCE);
13731 kmem_free(devname, MAXNAMELEN + 1);
13732 }
13733
13734 rval = ndi_devi_offline(cdip, flags);
13735
13736 return (rval);
13737 }
13738
13739 static dev_info_t *
13740 mptsas_find_child(dev_info_t *pdip, char *name)
13741 {
13742 dev_info_t *child = NULL;
13743 char *rname = NULL;
13744 int rval = DDI_FAILURE;
13745
13746 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13747
13748 child = ddi_get_child(pdip);
13749 while (child) {
13750 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
13751 if (rval != DDI_SUCCESS) {
13752 child = ddi_get_next_sibling(child);
13753 bzero(rname, SCSI_MAXNAMELEN);
13754 continue;
13755 }
13756
13757 if (strcmp(rname, name) == 0) {
13758 break;
13759 }
13760 child = ddi_get_next_sibling(child);
13761 bzero(rname, SCSI_MAXNAMELEN);
13762 }
13763
13764 kmem_free(rname, SCSI_MAXNAMELEN);
13765
13766 return (child);
13767 }
13768
13769
13770 static dev_info_t *
13771 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
13772 {
13773 dev_info_t *child = NULL;
13774 char *name = NULL;
13775 char *addr = NULL;
13776
13777 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13778 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13779 (void) sprintf(name, "%016"PRIx64, sasaddr);
13780 (void) sprintf(addr, "w%s,%x", name, lun);
13781 child = mptsas_find_child(pdip, addr);
13782 kmem_free(name, SCSI_MAXNAMELEN);
13783 kmem_free(addr, SCSI_MAXNAMELEN);
13784 return (child);
13785 }
13786
13787 static dev_info_t *
13788 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
13789 {
13790 dev_info_t *child;
13791 char *addr;
13792
13793 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13794 (void) sprintf(addr, "p%x,0", phy);
13795 child = mptsas_find_child(pdip, addr);
13796 kmem_free(addr, SCSI_MAXNAMELEN);
13797 return (child);
13798 }
13799
13800 static mdi_pathinfo_t *
13801 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
13802 {
13803 mdi_pathinfo_t *path;
13804 char *addr = NULL;
13805
13806 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13807 (void) sprintf(addr, "p%x,0", phy);
13808 path = mdi_pi_find(pdip, NULL, addr);
13809 kmem_free(addr, SCSI_MAXNAMELEN);
13810 return (path);
13811 }
13812
13813 static mdi_pathinfo_t *
13814 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
13815 {
13816 mdi_pathinfo_t *path;
13817 char *name = NULL;
13818 char *addr = NULL;
13819
13820 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13821 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13822 (void) sprintf(name, "%016"PRIx64, sasaddr);
13823 (void) sprintf(addr, "w%s,%x", name, lun);
13824 path = mdi_pi_find(parent, NULL, addr);
13825 kmem_free(name, SCSI_MAXNAMELEN);
13826 kmem_free(addr, SCSI_MAXNAMELEN);
13827
13828 return (path);
13829 }
13830
13831 static int
13832 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
13833 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
13834 {
13835 int i = 0;
13836 uchar_t *inq83 = NULL;
13837 int inq83_len1 = 0xFF;
13838 int inq83_len = 0;
13839 int rval = DDI_FAILURE;
13840 ddi_devid_t devid;
13841 char *guid = NULL;
13842 int target = ptgt->m_devhdl;
13843 mdi_pathinfo_t *pip = NULL;
13844 mptsas_t *mpt = DIP2MPT(pdip);
13845
13846 /*
13847 * For DVD/CD ROM and tape devices and optical
13848 * devices, we won't try to enumerate them under
13849 * scsi_vhci, so no need to try page83
13850 */
13851 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
13852 sd_inq->inq_dtype == DTYPE_OPTICAL ||
13853 sd_inq->inq_dtype == DTYPE_ESI))
13854 goto create_lun;
13855
13856 /*
13857 * The LCA returns good SCSI status, but corrupt page 83 data the first
13858 * time it is queried. The solution is to keep trying to request page83
13859 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
13860 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
13861 * give up to get VPD page at this stage and fail the enumeration.
13862 */
13863
13864 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
13865
13866 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
13867 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13868 inq83_len1, &inq83_len, 1);
13869 if (rval != 0) {
13870 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13871 "0x83 for target:%x, lun:%x failed!", target, lun);
13872 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
13873 goto create_lun;
13874 goto out;
13875 }
13876 /*
13877 * create DEVID from inquiry data
13878 */
13879 if ((rval = ddi_devid_scsi_encode(
13880 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
13881 sizeof (struct scsi_inquiry), NULL, 0, inq83,
13882 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
13883 /*
13884 * extract GUID from DEVID
13885 */
13886 guid = ddi_devid_to_guid(devid);
13887
13888 /*
13889 * Do not enable MPXIO if the strlen(guid) is greater
13890 * than MPTSAS_MAX_GUID_LEN, this constrain would be
13891 * handled by framework later.
13892 */
13893 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
13894 ddi_devid_free_guid(guid);
13895 guid = NULL;
13896 if (mpt->m_mpxio_enable == TRUE) {
13897 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
13898 "lun:%x doesn't have a valid GUID, "
13899 "multipathing for this drive is "
13900 "not enabled", target, lun);
13901 }
13902 }
13903
13904 /*
13905 * devid no longer needed
13906 */
13907 ddi_devid_free(devid);
13908 break;
13909 } else if (rval == DDI_NOT_WELL_FORMED) {
13910 /*
13911 * return value of ddi_devid_scsi_encode equal to
13912 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
13913 * to retry inquiry page 0x83 and get GUID.
13914 */
13915 NDBG20(("Not well formed devid, retry..."));
13916 delay(1 * drv_usectohz(1000000));
13917 continue;
13918 } else {
13919 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
13920 "path target:%x, lun:%x", target, lun);
13921 rval = DDI_FAILURE;
13922 goto create_lun;
13923 }
13924 }
13925
13926 if (i == mptsas_inq83_retry_timeout) {
13927 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
13928 "for path target:%x, lun:%x", target, lun);
13929 }
13930
13931 rval = DDI_FAILURE;
13932
13933 create_lun:
13934 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
13935 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
13936 ptgt, lun);
13937 }
13938 if (rval != DDI_SUCCESS) {
13939 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
13940 ptgt, lun);
13941
13942 }
13943 out:
13944 if (guid != NULL) {
13945 /*
13946 * guid no longer needed
13947 */
13948 ddi_devid_free_guid(guid);
13949 }
13950 if (inq83 != NULL)
13951 kmem_free(inq83, inq83_len1);
13952 return (rval);
13953 }
13954
13955 static int
13956 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
13957 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
13958 {
13959 int target;
13960 char *nodename = NULL;
13961 char **compatible = NULL;
13962 int ncompatible = 0;
13963 int mdi_rtn = MDI_FAILURE;
13964 int rval = DDI_FAILURE;
13965 char *old_guid = NULL;
13966 mptsas_t *mpt = DIP2MPT(pdip);
13967 char *lun_addr = NULL;
13968 char *wwn_str = NULL;
13969 char *attached_wwn_str = NULL;
13970 char *component = NULL;
13971 uint8_t phy = 0xFF;
13972 uint64_t sas_wwn;
13973 int64_t lun64 = 0;
13974 uint32_t devinfo;
13975 uint16_t dev_hdl;
13976 uint16_t pdev_hdl;
13977 uint64_t dev_sas_wwn;
13978 uint64_t pdev_sas_wwn;
13979 uint32_t pdev_info;
13980 uint8_t physport;
13981 uint8_t phy_id;
13982 uint32_t page_address;
13983 uint16_t bay_num, enclosure;
13984 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
13985 uint32_t dev_info;
13986
13987 mutex_enter(&mpt->m_mutex);
13988 target = ptgt->m_devhdl;
13989 sas_wwn = ptgt->m_sas_wwn;
13990 devinfo = ptgt->m_deviceinfo;
13991 phy = ptgt->m_phynum;
13992 mutex_exit(&mpt->m_mutex);
13993
13994 if (sas_wwn) {
13995 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
13996 } else {
13997 *pip = mptsas_find_path_phy(pdip, phy);
13998 }
13999
14000 if (*pip != NULL) {
14001 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14002 ASSERT(*lun_dip != NULL);
14003 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
14004 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
14005 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
14006 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
14007 /*
14008 * Same path back online again.
14009 */
14010 (void) ddi_prop_free(old_guid);
14011 if ((!MDI_PI_IS_ONLINE(*pip)) &&
14012 (!MDI_PI_IS_STANDBY(*pip)) &&
14013 (ptgt->m_tgt_unconfigured == 0)) {
14014 rval = mdi_pi_online(*pip, 0);
14015 mutex_enter(&mpt->m_mutex);
14016 ptgt->m_led_status = 0;
14017 (void) mptsas_flush_led_status(mpt,
14018 ptgt);
14019 mutex_exit(&mpt->m_mutex);
14020 } else {
14021 rval = DDI_SUCCESS;
14022 }
14023 if (rval != DDI_SUCCESS) {
14024 mptsas_log(mpt, CE_WARN, "path:target: "
14025 "%x, lun:%x online failed!", target,
14026 lun);
14027 *pip = NULL;
14028 *lun_dip = NULL;
14029 }
14030 return (rval);
14031 } else {
14032 /*
14033 * The GUID of the LUN has changed which maybe
14034 * because customer mapped another volume to the
14035 * same LUN.
14036 */
14037 mptsas_log(mpt, CE_WARN, "The GUID of the "
14038 "target:%x, lun:%x was changed, maybe "
14039 "because someone mapped another volume "
14040 "to the same LUN", target, lun);
14041 (void) ddi_prop_free(old_guid);
14042 if (!MDI_PI_IS_OFFLINE(*pip)) {
14043 rval = mdi_pi_offline(*pip, 0);
14044 if (rval != MDI_SUCCESS) {
14045 mptsas_log(mpt, CE_WARN, "path:"
14046 "target:%x, lun:%x offline "
14047 "failed!", target, lun);
14048 *pip = NULL;
14049 *lun_dip = NULL;
14050 return (DDI_FAILURE);
14051 }
14052 }
14053 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
14054 mptsas_log(mpt, CE_WARN, "path:target:"
14055 "%x, lun:%x free failed!", target,
14056 lun);
14057 *pip = NULL;
14058 *lun_dip = NULL;
14059 return (DDI_FAILURE);
14060 }
14061 }
14062 } else {
14063 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
14064 "property for path:target:%x, lun:%x", target, lun);
14065 *pip = NULL;
14066 *lun_dip = NULL;
14067 return (DDI_FAILURE);
14068 }
14069 }
14070 scsi_hba_nodename_compatible_get(inq, NULL,
14071 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
14072
14073 /*
14074 * if nodename can't be determined then print a message and skip it
14075 */
14076 if (nodename == NULL) {
14077 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
14078 "driver for target%d lun %d dtype:0x%02x", target, lun,
14079 inq->inq_dtype);
14080 return (DDI_FAILURE);
14081 }
14082
14083 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14084 /* The property is needed by MPAPI */
14085 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14086
14087 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14088 if (guid) {
14089 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
14090 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14091 } else {
14092 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
14093 (void) sprintf(wwn_str, "p%x", phy);
14094 }
14095
14096 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
14097 guid, lun_addr, compatible, ncompatible,
14098 0, pip);
14099 if (mdi_rtn == MDI_SUCCESS) {
14100
14101 if (mdi_prop_update_string(*pip, MDI_GUID,
14102 guid) != DDI_SUCCESS) {
14103 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14104 "create prop for target %d lun %d (MDI_GUID)",
14105 target, lun);
14106 mdi_rtn = MDI_FAILURE;
14107 goto virt_create_done;
14108 }
14109
14110 if (mdi_prop_update_int(*pip, LUN_PROP,
14111 lun) != DDI_SUCCESS) {
14112 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14113 "create prop for target %d lun %d (LUN_PROP)",
14114 target, lun);
14115 mdi_rtn = MDI_FAILURE;
14116 goto virt_create_done;
14117 }
14118 lun64 = (int64_t)lun;
14119 if (mdi_prop_update_int64(*pip, LUN64_PROP,
14120 lun64) != DDI_SUCCESS) {
14121 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14122 "create prop for target %d (LUN64_PROP)",
14123 target);
14124 mdi_rtn = MDI_FAILURE;
14125 goto virt_create_done;
14126 }
14127 if (mdi_prop_update_string_array(*pip, "compatible",
14128 compatible, ncompatible) !=
14129 DDI_PROP_SUCCESS) {
14130 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14131 "create prop for target %d lun %d (COMPATIBLE)",
14132 target, lun);
14133 mdi_rtn = MDI_FAILURE;
14134 goto virt_create_done;
14135 }
14136 if (sas_wwn && (mdi_prop_update_string(*pip,
14137 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
14138 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14139 "create prop for target %d lun %d "
14140 "(target-port)", target, lun);
14141 mdi_rtn = MDI_FAILURE;
14142 goto virt_create_done;
14143 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
14144 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
14145 /*
14146 * Direct attached SATA device without DeviceName
14147 */
14148 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14149 "create prop for SAS target %d lun %d "
14150 "(sata-phy)", target, lun);
14151 mdi_rtn = MDI_FAILURE;
14152 goto virt_create_done;
14153 }
14154 mutex_enter(&mpt->m_mutex);
14155
14156 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14157 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14158 (uint32_t)ptgt->m_devhdl;
14159 rval = mptsas_get_sas_device_page0(mpt, page_address,
14160 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
14161 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14162 if (rval != DDI_SUCCESS) {
14163 mutex_exit(&mpt->m_mutex);
14164 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14165 "parent device for handle %d", page_address);
14166 mdi_rtn = MDI_FAILURE;
14167 goto virt_create_done;
14168 }
14169
14170 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14171 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14172 rval = mptsas_get_sas_device_page0(mpt, page_address,
14173 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
14174 &phy_id, &pdev_hdl, &bay_num, &enclosure);
14175 if (rval != DDI_SUCCESS) {
14176 mutex_exit(&mpt->m_mutex);
14177 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14178 "device info for handle %d", page_address);
14179 mdi_rtn = MDI_FAILURE;
14180 goto virt_create_done;
14181 }
14182
14183 mutex_exit(&mpt->m_mutex);
14184
14185 /*
14186 * If this device direct attached to the controller
14187 * set the attached-port to the base wwid
14188 */
14189 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14190 != DEVINFO_DIRECT_ATTACHED) {
14191 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14192 pdev_sas_wwn);
14193 } else {
14194 /*
14195 * Update the iport's attached-port to guid
14196 */
14197 if (sas_wwn == 0) {
14198 (void) sprintf(wwn_str, "p%x", phy);
14199 } else {
14200 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14201 }
14202 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14203 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14204 DDI_PROP_SUCCESS) {
14205 mptsas_log(mpt, CE_WARN,
14206 "mptsas unable to create "
14207 "property for iport target-port"
14208 " %s (sas_wwn)",
14209 wwn_str);
14210 mdi_rtn = MDI_FAILURE;
14211 goto virt_create_done;
14212 }
14213
14214 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14215 mpt->un.m_base_wwid);
14216 }
14217
14218 if (mdi_prop_update_string(*pip,
14219 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14220 DDI_PROP_SUCCESS) {
14221 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14222 "property for iport attached-port %s (sas_wwn)",
14223 attached_wwn_str);
14224 mdi_rtn = MDI_FAILURE;
14225 goto virt_create_done;
14226 }
14227
14228
14229 if (inq->inq_dtype == 0) {
14230 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14231 /*
14232 * set obp path for pathinfo
14233 */
14234 (void) snprintf(component, MAXPATHLEN,
14235 "disk@%s", lun_addr);
14236
14237 if (mdi_pi_pathname_obp_set(*pip, component) !=
14238 DDI_SUCCESS) {
14239 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14240 "unable to set obp-path for object %s",
14241 component);
14242 mdi_rtn = MDI_FAILURE;
14243 goto virt_create_done;
14244 }
14245 }
14246
14247 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
14248 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14249 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14250 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
14251 "pm-capable", 1)) !=
14252 DDI_PROP_SUCCESS) {
14253 mptsas_log(mpt, CE_WARN, "mptsas driver"
14254 "failed to create pm-capable "
14255 "property, target %d", target);
14256 mdi_rtn = MDI_FAILURE;
14257 goto virt_create_done;
14258 }
14259 }
14260 /*
14261 * Create the phy-num property
14262 */
14263 if (mdi_prop_update_int(*pip, "phy-num",
14264 ptgt->m_phynum) != DDI_SUCCESS) {
14265 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
14266 "create phy-num property for target %d lun %d",
14267 target, lun);
14268 mdi_rtn = MDI_FAILURE;
14269 goto virt_create_done;
14270 }
14271 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
14272 mdi_rtn = mdi_pi_online(*pip, 0);
14273 if (mdi_rtn == MDI_SUCCESS) {
14274 mutex_enter(&mpt->m_mutex);
14275 ptgt->m_led_status = 0;
14276 (void) mptsas_flush_led_status(mpt, ptgt);
14277 mutex_exit(&mpt->m_mutex);
14278 }
14279 if (mdi_rtn == MDI_NOT_SUPPORTED) {
14280 mdi_rtn = MDI_FAILURE;
14281 }
14282 virt_create_done:
14283 if (*pip && mdi_rtn != MDI_SUCCESS) {
14284 (void) mdi_pi_free(*pip, 0);
14285 *pip = NULL;
14286 *lun_dip = NULL;
14287 }
14288 }
14289
14290 scsi_hba_nodename_compatible_free(nodename, compatible);
14291 if (lun_addr != NULL) {
14292 kmem_free(lun_addr, SCSI_MAXNAMELEN);
14293 }
14294 if (wwn_str != NULL) {
14295 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14296 }
14297 if (component != NULL) {
14298 kmem_free(component, MAXPATHLEN);
14299 }
14300
14301 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14302 }
14303
14304 static int
14305 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
14306 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14307 {
14308 int target;
14309 int rval;
14310 int ndi_rtn = NDI_FAILURE;
14311 uint64_t be_sas_wwn;
14312 char *nodename = NULL;
14313 char **compatible = NULL;
14314 int ncompatible = 0;
14315 int instance = 0;
14316 mptsas_t *mpt = DIP2MPT(pdip);
14317 char *wwn_str = NULL;
14318 char *component = NULL;
14319 char *attached_wwn_str = NULL;
14320 uint8_t phy = 0xFF;
14321 uint64_t sas_wwn;
14322 uint32_t devinfo;
14323 uint16_t dev_hdl;
14324 uint16_t pdev_hdl;
14325 uint64_t pdev_sas_wwn;
14326 uint64_t dev_sas_wwn;
14327 uint32_t pdev_info;
14328 uint8_t physport;
14329 uint8_t phy_id;
14330 uint32_t page_address;
14331 uint16_t bay_num, enclosure;
14332 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
14333 uint32_t dev_info;
14334 int64_t lun64 = 0;
14335
14336 mutex_enter(&mpt->m_mutex);
14337 target = ptgt->m_devhdl;
14338 sas_wwn = ptgt->m_sas_wwn;
14339 devinfo = ptgt->m_deviceinfo;
14340 phy = ptgt->m_phynum;
14341 mutex_exit(&mpt->m_mutex);
14342
14343 /*
14344 * generate compatible property with binding-set "mpt"
14345 */
14346 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
14347 &nodename, &compatible, &ncompatible);
14348
14349 /*
14350 * if nodename can't be determined then print a message and skip it
14351 */
14352 if (nodename == NULL) {
14353 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
14354 "for target %d lun %d", target, lun);
14355 return (DDI_FAILURE);
14356 }
14357
14358 ndi_rtn = ndi_devi_alloc(pdip, nodename,
14359 DEVI_SID_NODEID, lun_dip);
14360
14361 /*
14362 * if lun alloc success, set props
14363 */
14364 if (ndi_rtn == NDI_SUCCESS) {
14365
14366 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14367 *lun_dip, LUN_PROP, lun) !=
14368 DDI_PROP_SUCCESS) {
14369 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14370 "property for target %d lun %d (LUN_PROP)",
14371 target, lun);
14372 ndi_rtn = NDI_FAILURE;
14373 goto phys_create_done;
14374 }
14375
14376 lun64 = (int64_t)lun;
14377 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
14378 *lun_dip, LUN64_PROP, lun64) !=
14379 DDI_PROP_SUCCESS) {
14380 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14381 "property for target %d lun64 %d (LUN64_PROP)",
14382 target, lun);
14383 ndi_rtn = NDI_FAILURE;
14384 goto phys_create_done;
14385 }
14386 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
14387 *lun_dip, "compatible", compatible, ncompatible)
14388 != DDI_PROP_SUCCESS) {
14389 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14390 "property for target %d lun %d (COMPATIBLE)",
14391 target, lun);
14392 ndi_rtn = NDI_FAILURE;
14393 goto phys_create_done;
14394 }
14395
14396 /*
14397 * We need the SAS WWN for non-multipath devices, so
14398 * we'll use the same property as that multipathing
14399 * devices need to present for MPAPI. If we don't have
14400 * a WWN (e.g. parallel SCSI), don't create the prop.
14401 */
14402 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
14403 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14404 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
14405 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
14406 != DDI_PROP_SUCCESS) {
14407 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14408 "create property for SAS target %d lun %d "
14409 "(target-port)", target, lun);
14410 ndi_rtn = NDI_FAILURE;
14411 goto phys_create_done;
14412 }
14413
14414 be_sas_wwn = BE_64(sas_wwn);
14415 if (sas_wwn && ndi_prop_update_byte_array(
14416 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
14417 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
14418 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14419 "create property for SAS target %d lun %d "
14420 "(port-wwn)", target, lun);
14421 ndi_rtn = NDI_FAILURE;
14422 goto phys_create_done;
14423 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
14424 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
14425 DDI_PROP_SUCCESS)) {
14426 /*
14427 * Direct attached SATA device without DeviceName
14428 */
14429 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14430 "create property for SAS target %d lun %d "
14431 "(sata-phy)", target, lun);
14432 ndi_rtn = NDI_FAILURE;
14433 goto phys_create_done;
14434 }
14435
14436 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14437 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
14438 mptsas_log(mpt, CE_WARN, "mptsas unable to"
14439 "create property for SAS target %d lun %d"
14440 " (SAS_PROP)", target, lun);
14441 ndi_rtn = NDI_FAILURE;
14442 goto phys_create_done;
14443 }
14444 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
14445 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
14446 mptsas_log(mpt, CE_WARN, "mptsas unable "
14447 "to create guid property for target %d "
14448 "lun %d", target, lun);
14449 ndi_rtn = NDI_FAILURE;
14450 goto phys_create_done;
14451 }
14452
14453 /*
14454 * The following code is to set properties for SM-HBA support,
14455 * it doesn't apply to RAID volumes
14456 */
14457 if (ptgt->m_phymask == 0)
14458 goto phys_raid_lun;
14459
14460 mutex_enter(&mpt->m_mutex);
14461
14462 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14463 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14464 (uint32_t)ptgt->m_devhdl;
14465 rval = mptsas_get_sas_device_page0(mpt, page_address,
14466 &dev_hdl, &dev_sas_wwn, &dev_info,
14467 &physport, &phy_id, &pdev_hdl,
14468 &bay_num, &enclosure);
14469 if (rval != DDI_SUCCESS) {
14470 mutex_exit(&mpt->m_mutex);
14471 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
14472 "parent device for handle %d.", page_address);
14473 ndi_rtn = NDI_FAILURE;
14474 goto phys_create_done;
14475 }
14476
14477 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14478 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
14479 rval = mptsas_get_sas_device_page0(mpt, page_address,
14480 &dev_hdl, &pdev_sas_wwn, &pdev_info,
14481 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14482 if (rval != DDI_SUCCESS) {
14483 mutex_exit(&mpt->m_mutex);
14484 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14485 "device for handle %d.", page_address);
14486 ndi_rtn = NDI_FAILURE;
14487 goto phys_create_done;
14488 }
14489
14490 mutex_exit(&mpt->m_mutex);
14491
14492 /*
14493 * If this device direct attached to the controller
14494 * set the attached-port to the base wwid
14495 */
14496 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14497 != DEVINFO_DIRECT_ATTACHED) {
14498 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14499 pdev_sas_wwn);
14500 } else {
14501 /*
14502 * Update the iport's attached-port to guid
14503 */
14504 if (sas_wwn == 0) {
14505 (void) sprintf(wwn_str, "p%x", phy);
14506 } else {
14507 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
14508 }
14509 if (ddi_prop_update_string(DDI_DEV_T_NONE,
14510 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14511 DDI_PROP_SUCCESS) {
14512 mptsas_log(mpt, CE_WARN,
14513 "mptsas unable to create "
14514 "property for iport target-port"
14515 " %s (sas_wwn)",
14516 wwn_str);
14517 ndi_rtn = NDI_FAILURE;
14518 goto phys_create_done;
14519 }
14520
14521 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
14522 mpt->un.m_base_wwid);
14523 }
14524
14525 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14526 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
14527 DDI_PROP_SUCCESS) {
14528 mptsas_log(mpt, CE_WARN,
14529 "mptsas unable to create "
14530 "property for iport attached-port %s (sas_wwn)",
14531 attached_wwn_str);
14532 ndi_rtn = NDI_FAILURE;
14533 goto phys_create_done;
14534 }
14535
14536 if (IS_SATA_DEVICE(dev_info)) {
14537 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14538 *lun_dip, MPTSAS_VARIANT, "sata") !=
14539 DDI_PROP_SUCCESS) {
14540 mptsas_log(mpt, CE_WARN,
14541 "mptsas unable to create "
14542 "property for device variant ");
14543 ndi_rtn = NDI_FAILURE;
14544 goto phys_create_done;
14545 }
14546 }
14547
14548 if (IS_ATAPI_DEVICE(dev_info)) {
14549 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14550 *lun_dip, MPTSAS_VARIANT, "atapi") !=
14551 DDI_PROP_SUCCESS) {
14552 mptsas_log(mpt, CE_WARN,
14553 "mptsas unable to create "
14554 "property for device variant ");
14555 ndi_rtn = NDI_FAILURE;
14556 goto phys_create_done;
14557 }
14558 }
14559
14560 phys_raid_lun:
14561 /*
14562 * if this is a SAS controller, and the target is a SATA
14563 * drive, set the 'pm-capable' property for sd and if on
14564 * an OPL platform, also check if this is an ATAPI
14565 * device.
14566 */
14567 instance = ddi_get_instance(mpt->m_dip);
14568 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14569 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14570 NDBG2(("mptsas%d: creating pm-capable property, "
14571 "target %d", instance, target));
14572
14573 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
14574 *lun_dip, "pm-capable", 1)) !=
14575 DDI_PROP_SUCCESS) {
14576 mptsas_log(mpt, CE_WARN, "mptsas "
14577 "failed to create pm-capable "
14578 "property, target %d", target);
14579 ndi_rtn = NDI_FAILURE;
14580 goto phys_create_done;
14581 }
14582
14583 }
14584
14585 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
14586 /*
14587 * add 'obp-path' properties for devinfo
14588 */
14589 bzero(wwn_str, sizeof (wwn_str));
14590 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
14591 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
14592 if (guid) {
14593 (void) snprintf(component, MAXPATHLEN,
14594 "disk@w%s,%x", wwn_str, lun);
14595 } else {
14596 (void) snprintf(component, MAXPATHLEN,
14597 "disk@p%x,%x", phy, lun);
14598 }
14599 if (ddi_pathname_obp_set(*lun_dip, component)
14600 != DDI_SUCCESS) {
14601 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
14602 "unable to set obp-path for SAS "
14603 "object %s", component);
14604 ndi_rtn = NDI_FAILURE;
14605 goto phys_create_done;
14606 }
14607 }
14608 /*
14609 * Create the phy-num property for non-raid disk
14610 */
14611 if (ptgt->m_phymask != 0) {
14612 if (ndi_prop_update_int(DDI_DEV_T_NONE,
14613 *lun_dip, "phy-num", ptgt->m_phynum) !=
14614 DDI_PROP_SUCCESS) {
14615 mptsas_log(mpt, CE_WARN, "mptsas driver "
14616 "failed to create phy-num property for "
14617 "target %d", target);
14618 ndi_rtn = NDI_FAILURE;
14619 goto phys_create_done;
14620 }
14621 }
14622 phys_create_done:
14623 /*
14624 * If props were setup ok, online the lun
14625 */
14626 if (ndi_rtn == NDI_SUCCESS) {
14627 /*
14628 * Try to online the new node
14629 */
14630 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
14631 }
14632 if (ndi_rtn == NDI_SUCCESS) {
14633 mutex_enter(&mpt->m_mutex);
14634 ptgt->m_led_status = 0;
14635 (void) mptsas_flush_led_status(mpt, ptgt);
14636 mutex_exit(&mpt->m_mutex);
14637 }
14638
14639 /*
14640 * If success set rtn flag, else unwire alloc'd lun
14641 */
14642 if (ndi_rtn != NDI_SUCCESS) {
14643 NDBG12(("mptsas driver unable to online "
14644 "target %d lun %d", target, lun));
14645 ndi_prop_remove_all(*lun_dip);
14646 (void) ndi_devi_free(*lun_dip);
14647 *lun_dip = NULL;
14648 }
14649 }
14650
14651 scsi_hba_nodename_compatible_free(nodename, compatible);
14652
14653 if (wwn_str != NULL) {
14654 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
14655 }
14656 if (component != NULL) {
14657 kmem_free(component, MAXPATHLEN);
14658 }
14659
14660
14661 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14662 }
14663
14664 static int
14665 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
14666 {
14667 mptsas_t *mpt = DIP2MPT(pdip);
14668 struct smp_device smp_sd;
14669
14670 /* XXX An HBA driver should not be allocating an smp_device. */
14671 bzero(&smp_sd, sizeof (struct smp_device));
14672 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
14673 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
14674
14675 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
14676 return (NDI_FAILURE);
14677 return (NDI_SUCCESS);
14678 }
14679
14680 static int
14681 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
14682 {
14683 mptsas_t *mpt = DIP2MPT(pdip);
14684 mptsas_smp_t *psmp = NULL;
14685 int rval;
14686 int phymask;
14687
14688 /*
14689 * Get the physical port associated to the iport
14690 * PHYMASK TODO
14691 */
14692 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14693 "phymask", 0);
14694 /*
14695 * Find the smp node in hash table with specified sas address and
14696 * physical port
14697 */
14698 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
14699 if (psmp == NULL) {
14700 return (DDI_FAILURE);
14701 }
14702
14703 rval = mptsas_online_smp(pdip, psmp, smp_dip);
14704
14705 return (rval);
14706 }
14707
14708 static int
14709 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
14710 dev_info_t **smp_dip)
14711 {
14712 char wwn_str[MPTSAS_WWN_STRLEN];
14713 char attached_wwn_str[MPTSAS_WWN_STRLEN];
14714 int ndi_rtn = NDI_FAILURE;
14715 int rval = 0;
14716 mptsas_smp_t dev_info;
14717 uint32_t page_address;
14718 mptsas_t *mpt = DIP2MPT(pdip);
14719 uint16_t dev_hdl;
14720 uint64_t sas_wwn;
14721 uint64_t smp_sas_wwn;
14722 uint8_t physport;
14723 uint8_t phy_id;
14724 uint16_t pdev_hdl;
14725 uint8_t numphys = 0;
14726 uint16_t i = 0;
14727 char phymask[MPTSAS_MAX_PHYS];
14728 char *iport = NULL;
14729 mptsas_phymask_t phy_mask = 0;
14730 uint16_t attached_devhdl;
14731 uint16_t bay_num, enclosure;
14732
14733 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr);
14734
14735 /*
14736 * Probe smp device, prevent the node of removed device from being
14737 * configured succesfully
14738 */
14739 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) {
14740 return (DDI_FAILURE);
14741 }
14742
14743 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
14744 return (DDI_SUCCESS);
14745 }
14746
14747 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
14748
14749 /*
14750 * if lun alloc success, set props
14751 */
14752 if (ndi_rtn == NDI_SUCCESS) {
14753 /*
14754 * Set the flavor of the child to be SMP flavored
14755 */
14756 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
14757
14758 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14759 *smp_dip, SMP_WWN, wwn_str) !=
14760 DDI_PROP_SUCCESS) {
14761 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14762 "property for smp device %s (sas_wwn)",
14763 wwn_str);
14764 ndi_rtn = NDI_FAILURE;
14765 goto smp_create_done;
14766 }
14767 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr);
14768 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14769 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
14770 DDI_PROP_SUCCESS) {
14771 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14772 "property for iport target-port %s (sas_wwn)",
14773 wwn_str);
14774 ndi_rtn = NDI_FAILURE;
14775 goto smp_create_done;
14776 }
14777
14778 mutex_enter(&mpt->m_mutex);
14779
14780 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
14781 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
14782 rval = mptsas_get_sas_expander_page0(mpt, page_address,
14783 &dev_info);
14784 if (rval != DDI_SUCCESS) {
14785 mutex_exit(&mpt->m_mutex);
14786 mptsas_log(mpt, CE_WARN,
14787 "mptsas unable to get expander "
14788 "parent device info for %x", page_address);
14789 ndi_rtn = NDI_FAILURE;
14790 goto smp_create_done;
14791 }
14792
14793 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
14794 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14795 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14796 (uint32_t)dev_info.m_pdevhdl;
14797 rval = mptsas_get_sas_device_page0(mpt, page_address,
14798 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo,
14799 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14800 if (rval != DDI_SUCCESS) {
14801 mutex_exit(&mpt->m_mutex);
14802 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14803 "device info for %x", page_address);
14804 ndi_rtn = NDI_FAILURE;
14805 goto smp_create_done;
14806 }
14807
14808 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
14809 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14810 (uint32_t)dev_info.m_devhdl;
14811 rval = mptsas_get_sas_device_page0(mpt, page_address,
14812 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
14813 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure);
14814 if (rval != DDI_SUCCESS) {
14815 mutex_exit(&mpt->m_mutex);
14816 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
14817 "device info for %x", page_address);
14818 ndi_rtn = NDI_FAILURE;
14819 goto smp_create_done;
14820 }
14821 mutex_exit(&mpt->m_mutex);
14822
14823 /*
14824 * If this smp direct attached to the controller
14825 * set the attached-port to the base wwid
14826 */
14827 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14828 != DEVINFO_DIRECT_ATTACHED) {
14829 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14830 sas_wwn);
14831 } else {
14832 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
14833 mpt->un.m_base_wwid);
14834 }
14835
14836 if (ndi_prop_update_string(DDI_DEV_T_NONE,
14837 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
14838 DDI_PROP_SUCCESS) {
14839 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
14840 "property for smp attached-port %s (sas_wwn)",
14841 attached_wwn_str);
14842 ndi_rtn = NDI_FAILURE;
14843 goto smp_create_done;
14844 }
14845
14846 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14847 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
14848 mptsas_log(mpt, CE_WARN, "mptsas unable to "
14849 "create property for SMP %s (SMP_PROP) ",
14850 wwn_str);
14851 ndi_rtn = NDI_FAILURE;
14852 goto smp_create_done;
14853 }
14854
14855 /*
14856 * check the smp to see whether it direct
14857 * attached to the controller
14858 */
14859 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
14860 != DEVINFO_DIRECT_ATTACHED) {
14861 goto smp_create_done;
14862 }
14863 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
14864 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
14865 if (numphys > 0) {
14866 goto smp_create_done;
14867 }
14868 /*
14869 * this iport is an old iport, we need to
14870 * reconfig the props for it.
14871 */
14872 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14873 MPTSAS_VIRTUAL_PORT, 0) !=
14874 DDI_PROP_SUCCESS) {
14875 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14876 MPTSAS_VIRTUAL_PORT);
14877 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
14878 "prop update failed");
14879 goto smp_create_done;
14880 }
14881
14882 mutex_enter(&mpt->m_mutex);
14883 numphys = 0;
14884 iport = ddi_get_name_addr(pdip);
14885 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14886 bzero(phymask, sizeof (phymask));
14887 (void) sprintf(phymask,
14888 "%x", mpt->m_phy_info[i].phy_mask);
14889 if (strcmp(phymask, iport) == 0) {
14890 phy_mask = mpt->m_phy_info[i].phy_mask;
14891 break;
14892 }
14893 }
14894
14895 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
14896 if ((phy_mask >> i) & 0x01) {
14897 numphys++;
14898 }
14899 }
14900 /*
14901 * Update PHY info for smhba
14902 */
14903 if (mptsas_smhba_phy_init(mpt)) {
14904 mutex_exit(&mpt->m_mutex);
14905 mptsas_log(mpt, CE_WARN, "mptsas phy update "
14906 "failed");
14907 goto smp_create_done;
14908 }
14909 mutex_exit(&mpt->m_mutex);
14910
14911 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
14912 &attached_devhdl);
14913
14914 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
14915 MPTSAS_NUM_PHYS, numphys) !=
14916 DDI_PROP_SUCCESS) {
14917 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14918 MPTSAS_NUM_PHYS);
14919 mptsas_log(mpt, CE_WARN, "mptsas update "
14920 "num phys props failed");
14921 goto smp_create_done;
14922 }
14923 /*
14924 * Add parent's props for SMHBA support
14925 */
14926 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
14927 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
14928 DDI_PROP_SUCCESS) {
14929 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
14930 SCSI_ADDR_PROP_ATTACHED_PORT);
14931 mptsas_log(mpt, CE_WARN, "mptsas update iport"
14932 "attached-port failed");
14933 goto smp_create_done;
14934 }
14935
14936 smp_create_done:
14937 /*
14938 * If props were setup ok, online the lun
14939 */
14940 if (ndi_rtn == NDI_SUCCESS) {
14941 /*
14942 * Try to online the new node
14943 */
14944 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
14945 }
14946
14947 /*
14948 * If success set rtn flag, else unwire alloc'd lun
14949 */
14950 if (ndi_rtn != NDI_SUCCESS) {
14951 NDBG12(("mptsas unable to online "
14952 "SMP target %s", wwn_str));
14953 ndi_prop_remove_all(*smp_dip);
14954 (void) ndi_devi_free(*smp_dip);
14955 }
14956 }
14957
14958 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
14959 }
14960
14961 /* smp transport routine */
14962 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
14963 {
14964 uint64_t wwn;
14965 Mpi2SmpPassthroughRequest_t req;
14966 Mpi2SmpPassthroughReply_t rep;
14967 uint32_t direction = 0;
14968 mptsas_t *mpt;
14969 int ret;
14970 uint64_t tmp64;
14971
14972 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
14973 smp_a_hba_tran->smp_tran_hba_private;
14974
14975 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
14976 /*
14977 * Need to compose a SMP request message
14978 * and call mptsas_do_passthru() function
14979 */
14980 bzero(&req, sizeof (req));
14981 bzero(&rep, sizeof (rep));
14982 req.PassthroughFlags = 0;
14983 req.PhysicalPort = 0xff;
14984 req.ChainOffset = 0;
14985 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
14986
14987 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
14988 smp_pkt->smp_pkt_reason = ERANGE;
14989 return (DDI_FAILURE);
14990 }
14991 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
14992
14993 req.MsgFlags = 0;
14994 tmp64 = LE_64(wwn);
14995 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
14996 if (smp_pkt->smp_pkt_rspsize > 0) {
14997 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
14998 }
14999 if (smp_pkt->smp_pkt_reqsize > 0) {
15000 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
15001 }
15002
15003 mutex_enter(&mpt->m_mutex);
15004 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
15005 (uint8_t *)smp_pkt->smp_pkt_rsp,
15006 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
15007 smp_pkt->smp_pkt_rspsize - 4, direction,
15008 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
15009 smp_pkt->smp_pkt_timeout, FKIOCTL);
15010 mutex_exit(&mpt->m_mutex);
15011 if (ret != 0) {
15012 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
15013 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
15014 return (DDI_FAILURE);
15015 }
15016 /* do passthrough success, check the smp status */
15017 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15018 switch (LE_16(rep.IOCStatus)) {
15019 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
15020 smp_pkt->smp_pkt_reason = ENODEV;
15021 break;
15022 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
15023 smp_pkt->smp_pkt_reason = EOVERFLOW;
15024 break;
15025 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
15026 smp_pkt->smp_pkt_reason = EIO;
15027 break;
15028 default:
15029 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
15030 "status:%x", LE_16(rep.IOCStatus));
15031 smp_pkt->smp_pkt_reason = EIO;
15032 break;
15033 }
15034 return (DDI_FAILURE);
15035 }
15036 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
15037 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
15038 rep.SASStatus);
15039 smp_pkt->smp_pkt_reason = EIO;
15040 return (DDI_FAILURE);
15041 }
15042
15043 return (DDI_SUCCESS);
15044 }
15045
15046 /*
15047 * If we didn't get a match, we need to get sas page0 for each device, and
15048 * untill we get a match. If failed, return NULL
15049 */
15050 static mptsas_target_t *
15051 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy)
15052 {
15053 int i, j = 0;
15054 int rval = 0;
15055 uint16_t cur_handle;
15056 uint32_t page_address;
15057 mptsas_target_t *ptgt = NULL;
15058
15059 /*
15060 * PHY named device must be direct attached and attaches to
15061 * narrow port, if the iport is not parent of the device which
15062 * we are looking for.
15063 */
15064 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
15065 if ((1 << i) & phymask)
15066 j++;
15067 }
15068
15069 if (j > 1)
15070 return (NULL);
15071
15072 /*
15073 * Must be a narrow port and single device attached to the narrow port
15074 * So the physical port num of device which is equal to the iport's
15075 * port num is the device what we are looking for.
15076 */
15077
15078 if (mpt->m_phy_info[phy].phy_mask != phymask)
15079 return (NULL);
15080
15081 mutex_enter(&mpt->m_mutex);
15082
15083 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl,
15084 MPTSAS_HASH_FIRST);
15085 while (ptgt != NULL) {
15086 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15087 mutex_exit(&mpt->m_mutex);
15088 return (ptgt);
15089 }
15090
15091 ptgt = (mptsas_target_t *)mptsas_hash_traverse(
15092 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT);
15093 }
15094
15095 if (mpt->m_done_traverse_dev) {
15096 mutex_exit(&mpt->m_mutex);
15097 return (NULL);
15098 }
15099
15100 /* If didn't get a match, come here */
15101 cur_handle = mpt->m_dev_handle;
15102 for (; ; ) {
15103 ptgt = NULL;
15104 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15105 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15106 rval = mptsas_get_target_device_info(mpt, page_address,
15107 &cur_handle, &ptgt);
15108 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15109 (rval == DEV_INFO_FAIL_ALLOC)) {
15110 break;
15111 }
15112 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15113 (rval == DEV_INFO_PHYS_DISK)) {
15114 continue;
15115 }
15116 mpt->m_dev_handle = cur_handle;
15117
15118 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) {
15119 break;
15120 }
15121 }
15122
15123 mutex_exit(&mpt->m_mutex);
15124 return (ptgt);
15125 }
15126
15127 /*
15128 * The ptgt->m_sas_wwn contains the wwid for each disk.
15129 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
15130 * If we didn't get a match, we need to get sas page0 for each device, and
15131 * untill we get a match
15132 * If failed, return NULL
15133 */
15134 static mptsas_target_t *
15135 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid)
15136 {
15137 int rval = 0;
15138 uint16_t cur_handle;
15139 uint32_t page_address;
15140 mptsas_target_t *tmp_tgt = NULL;
15141
15142 mutex_enter(&mpt->m_mutex);
15143 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15144 &mpt->m_active->m_tgttbl, wwid, phymask);
15145 if (tmp_tgt != NULL) {
15146 mutex_exit(&mpt->m_mutex);
15147 return (tmp_tgt);
15148 }
15149
15150 if (phymask == 0) {
15151 /*
15152 * It's IR volume
15153 */
15154 rval = mptsas_get_raid_info(mpt);
15155 if (rval) {
15156 tmp_tgt = (struct mptsas_target *)mptsas_hash_search(
15157 &mpt->m_active->m_tgttbl, wwid, phymask);
15158 }
15159 mutex_exit(&mpt->m_mutex);
15160 return (tmp_tgt);
15161 }
15162
15163 if (mpt->m_done_traverse_dev) {
15164 mutex_exit(&mpt->m_mutex);
15165 return (NULL);
15166 }
15167
15168 /* If didn't get a match, come here */
15169 cur_handle = mpt->m_dev_handle;
15170 for (; ; ) {
15171 tmp_tgt = NULL;
15172 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
15173 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
15174 rval = mptsas_get_target_device_info(mpt, page_address,
15175 &cur_handle, &tmp_tgt);
15176 if ((rval == DEV_INFO_FAIL_PAGE0) ||
15177 (rval == DEV_INFO_FAIL_ALLOC)) {
15178 tmp_tgt = NULL;
15179 break;
15180 }
15181 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
15182 (rval == DEV_INFO_PHYS_DISK)) {
15183 continue;
15184 }
15185 mpt->m_dev_handle = cur_handle;
15186 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) &&
15187 (tmp_tgt->m_phymask == phymask)) {
15188 break;
15189 }
15190 }
15191
15192 mutex_exit(&mpt->m_mutex);
15193 return (tmp_tgt);
15194 }
15195
15196 static mptsas_smp_t *
15197 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid)
15198 {
15199 int rval = 0;
15200 uint16_t cur_handle;
15201 uint32_t page_address;
15202 mptsas_smp_t smp_node, *psmp = NULL;
15203
15204 mutex_enter(&mpt->m_mutex);
15205 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl,
15206 wwid, phymask);
15207 if (psmp != NULL) {
15208 mutex_exit(&mpt->m_mutex);
15209 return (psmp);
15210 }
15211
15212 if (mpt->m_done_traverse_smp) {
15213 mutex_exit(&mpt->m_mutex);
15214 return (NULL);
15215 }
15216
15217 /* If didn't get a match, come here */
15218 cur_handle = mpt->m_smp_devhdl;
15219 for (; ; ) {
15220 psmp = NULL;
15221 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
15222 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
15223 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15224 &smp_node);
15225 if (rval != DDI_SUCCESS) {
15226 break;
15227 }
15228 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
15229 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node);
15230 ASSERT(psmp);
15231 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) &&
15232 (psmp->m_phymask == phymask)) {
15233 break;
15234 }
15235 }
15236
15237 mutex_exit(&mpt->m_mutex);
15238 return (psmp);
15239 }
15240
15241 /* helper functions using hash */
15242
15243 /*
15244 * Can't have duplicate entries for same devhdl,
15245 * if there are invalid entries, the devhdl should be set to 0xffff
15246 */
15247 static void *
15248 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl)
15249 {
15250 mptsas_hash_data_t *data;
15251
15252 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST);
15253 while (data != NULL) {
15254 if (data->devhdl == devhdl) {
15255 break;
15256 }
15257 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT);
15258 }
15259 return (data);
15260 }
15261
15262 mptsas_target_t *
15263 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid,
15264 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
15265 {
15266 mptsas_target_t *tmp_tgt = NULL;
15267
15268 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask);
15269 if (tmp_tgt != NULL) {
15270 NDBG20(("Hash item already exist"));
15271 tmp_tgt->m_deviceinfo = devinfo;
15272 tmp_tgt->m_devhdl = devhdl;
15273 return (tmp_tgt);
15274 }
15275 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
15276 if (tmp_tgt == NULL) {
15277 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
15278 return (NULL);
15279 }
15280 tmp_tgt->m_devhdl = devhdl;
15281 tmp_tgt->m_sas_wwn = wwid;
15282 tmp_tgt->m_deviceinfo = devinfo;
15283 tmp_tgt->m_phymask = phymask;
15284 tmp_tgt->m_phynum = phynum;
15285 /* Initialized the tgt structure */
15286 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
15287 tmp_tgt->m_qfull_retry_interval =
15288 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
15289 tmp_tgt->m_t_throttle = MAX_THROTTLE;
15290
15291 mptsas_hash_add(hashtab, tmp_tgt);
15292
15293 return (tmp_tgt);
15294 }
15295
15296 static void
15297 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15298 mptsas_phymask_t phymask)
15299 {
15300 mptsas_target_t *tmp_tgt;
15301 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask);
15302 if (tmp_tgt == NULL) {
15303 cmn_err(CE_WARN, "Tgt not found, nothing to free");
15304 } else {
15305 kmem_free(tmp_tgt, sizeof (struct mptsas_target));
15306 }
15307 }
15308
15309 /*
15310 * Return the entry in the hash table
15311 */
15312 static mptsas_smp_t *
15313 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data)
15314 {
15315 uint64_t key1 = data->m_sasaddr;
15316 mptsas_phymask_t key2 = data->m_phymask;
15317 mptsas_smp_t *ret_data;
15318
15319 ret_data = mptsas_hash_search(hashtab, key1, key2);
15320 if (ret_data != NULL) {
15321 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15322 return (ret_data);
15323 }
15324
15325 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
15326 bcopy(data, ret_data, sizeof (mptsas_smp_t));
15327 mptsas_hash_add(hashtab, ret_data);
15328 return (ret_data);
15329 }
15330
15331 static void
15332 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid,
15333 mptsas_phymask_t phymask)
15334 {
15335 mptsas_smp_t *tmp_smp;
15336 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask);
15337 if (tmp_smp == NULL) {
15338 cmn_err(CE_WARN, "Smp element not found, nothing to free");
15339 } else {
15340 kmem_free(tmp_smp, sizeof (struct mptsas_smp));
15341 }
15342 }
15343
15344 /*
15345 * Hash operation functions
15346 * key1 is the sas_wwn, key2 is the phymask
15347 */
15348 static void
15349 mptsas_hash_init(mptsas_hash_table_t *hashtab)
15350 {
15351 if (hashtab == NULL) {
15352 return;
15353 }
15354 bzero(hashtab->head, sizeof (mptsas_hash_node_t) *
15355 MPTSAS_HASH_ARRAY_SIZE);
15356 hashtab->cur = NULL;
15357 hashtab->line = 0;
15358 }
15359
15360 static void
15361 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen)
15362 {
15363 uint16_t line = 0;
15364 mptsas_hash_node_t *cur = NULL, *last = NULL;
15365
15366 if (hashtab == NULL) {
15367 return;
15368 }
15369 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) {
15370 cur = hashtab->head[line];
15371 while (cur != NULL) {
15372 last = cur;
15373 cur = cur->next;
15374 kmem_free(last->data, datalen);
15375 kmem_free(last, sizeof (mptsas_hash_node_t));
15376 }
15377 }
15378 }
15379
15380 /*
15381 * You must guarantee the element doesn't exist in the hash table
15382 * before you call mptsas_hash_add()
15383 */
15384 static void
15385 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data)
15386 {
15387 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1;
15388 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2;
15389 mptsas_hash_node_t **head = NULL;
15390 mptsas_hash_node_t *node = NULL;
15391
15392 if (hashtab == NULL) {
15393 return;
15394 }
15395 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL);
15396 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP);
15397 node->data = data;
15398
15399 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15400 if (*head == NULL) {
15401 *head = node;
15402 } else {
15403 node->next = *head;
15404 *head = node;
15405 }
15406 }
15407
15408 static void *
15409 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1,
15410 mptsas_phymask_t key2)
15411 {
15412 mptsas_hash_node_t **head = NULL;
15413 mptsas_hash_node_t *last = NULL, *cur = NULL;
15414 mptsas_hash_data_t *data;
15415 if (hashtab == NULL) {
15416 return (NULL);
15417 }
15418 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]);
15419 cur = *head;
15420 while (cur != NULL) {
15421 data = cur->data;
15422 if ((data->key1 == key1) && (data->key2 == key2)) {
15423 if (last == NULL) {
15424 (*head) = cur->next;
15425 } else {
15426 last->next = cur->next;
15427 }
15428 kmem_free(cur, sizeof (mptsas_hash_node_t));
15429 return (data);
15430 } else {
15431 last = cur;
15432 cur = cur->next;
15433 }
15434 }
15435 return (NULL);
15436 }
15437
15438 static void *
15439 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1,
15440 mptsas_phymask_t key2)
15441 {
15442 mptsas_hash_node_t *cur = NULL;
15443 mptsas_hash_data_t *data;
15444 if (hashtab == NULL) {
15445 return (NULL);
15446 }
15447 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE];
15448 while (cur != NULL) {
15449 data = cur->data;
15450 if ((data->key1 == key1) && (data->key2 == key2)) {
15451 return (data);
15452 } else {
15453 cur = cur->next;
15454 }
15455 }
15456 return (NULL);
15457 }
15458
15459 static void *
15460 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos)
15461 {
15462 mptsas_hash_node_t *this = NULL;
15463
15464 if (hashtab == NULL) {
15465 return (NULL);
15466 }
15467
15468 if (pos == MPTSAS_HASH_FIRST) {
15469 hashtab->line = 0;
15470 hashtab->cur = NULL;
15471 this = hashtab->head[0];
15472 } else {
15473 if (hashtab->cur == NULL) {
15474 return (NULL);
15475 } else {
15476 this = hashtab->cur->next;
15477 }
15478 }
15479
15480 while (this == NULL) {
15481 hashtab->line++;
15482 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) {
15483 /* the traverse reaches the end */
15484 hashtab->cur = NULL;
15485 return (NULL);
15486 } else {
15487 this = hashtab->head[hashtab->line];
15488 }
15489 }
15490 hashtab->cur = this;
15491 return (this->data);
15492 }
15493
15494 /*
15495 * Functions for SGPIO LED support
15496 */
15497 static dev_info_t *
15498 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
15499 {
15500 dev_info_t *dip;
15501 int prop;
15502 dip = e_ddi_hold_devi_by_dev(dev, 0);
15503 if (dip == NULL)
15504 return (dip);
15505 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
15506 "phymask", 0);
15507 *phymask = (mptsas_phymask_t)prop;
15508 ddi_release_devi(dip);
15509 return (dip);
15510 }
15511 static mptsas_target_t *
15512 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
15513 {
15514 uint8_t phynum;
15515 uint64_t wwn;
15516 int lun;
15517 mptsas_target_t *ptgt = NULL;
15518
15519 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
15520 return (NULL);
15521 }
15522 if (addr[0] == 'w') {
15523 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
15524 } else {
15525 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
15526 }
15527 return (ptgt);
15528 }
15529
15530 static int
15531 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
15532 {
15533 uint32_t slotstatus = 0;
15534
15535 /* Build an MPI2 Slot Status based on our view of the world */
15536 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
15537 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
15538 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
15539 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
15540 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
15541 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
15542
15543 /* Write it to the controller */
15544 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
15545 slotstatus, ptgt->m_slot_num));
15546 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
15547 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
15548 }
15549
15550 /*
15551 * send sep request, use enclosure/slot addressing
15552 */
15553 static int
15554 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
15555 uint32_t *status, uint8_t act)
15556 {
15557 Mpi2SepRequest_t req;
15558 Mpi2SepReply_t rep;
15559 int ret;
15560
15561 ASSERT(mutex_owned(&mpt->m_mutex));
15562
15563 /*
15564 * We only support SEP control of directly-attached targets, in which
15565 * case the "SEP" we're talking to is a virtual one contained within
15566 * the HBA itself. This is necessary because DA targets typically have
15567 * no other mechanism for LED control. Targets for which a separate
15568 * enclosure service processor exists should be controlled via ses(7d)
15569 * or sgen(7d). Furthermore, since such requests can time out, they
15570 * should be made in user context rather than in response to
15571 * asynchronous fabric changes.
15572 *
15573 * In addition, we do not support this operation for RAID volumes,
15574 * since there is no slot associated with them.
15575 */
15576 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
15577 ptgt->m_phymask == 0) {
15578 return (ENOTTY);
15579 }
15580
15581 bzero(&req, sizeof (req));
15582 bzero(&rep, sizeof (rep));
15583
15584 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
15585 req.Action = act;
15586 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
15587 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
15588 req.Slot = LE_16(ptgt->m_slot_num);
15589 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15590 req.SlotStatus = LE_32(*status);
15591 }
15592 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
15593 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
15594 if (ret != 0) {
15595 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
15596 "Processor Request message error %d", ret);
15597 return (ret);
15598 }
15599 /* do passthrough success, check the ioc status */
15600 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
15601 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
15602 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
15603 LE_32(rep.IOCLogInfo));
15604 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
15605 case MPI2_IOCSTATUS_INVALID_FUNCTION:
15606 case MPI2_IOCSTATUS_INVALID_VPID:
15607 case MPI2_IOCSTATUS_INVALID_FIELD:
15608 case MPI2_IOCSTATUS_INVALID_STATE:
15609 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
15610 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
15611 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
15612 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
15613 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
15614 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
15615 return (EINVAL);
15616 case MPI2_IOCSTATUS_BUSY:
15617 return (EBUSY);
15618 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
15619 return (EAGAIN);
15620 case MPI2_IOCSTATUS_INVALID_SGL:
15621 case MPI2_IOCSTATUS_INTERNAL_ERROR:
15622 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
15623 default:
15624 return (EIO);
15625 }
15626 }
15627 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
15628 *status = LE_32(rep.SlotStatus);
15629 }
15630
15631 return (0);
15632 }
15633
15634 int
15635 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
15636 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
15637 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
15638 {
15639 ddi_dma_cookie_t new_cookie;
15640 size_t alloc_len;
15641 uint_t ncookie;
15642
15643 if (cookiep == NULL)
15644 cookiep = &new_cookie;
15645
15646 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
15647 NULL, dma_hdp) != DDI_SUCCESS) {
15648 return (FALSE);
15649 }
15650
15651 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
15652 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
15653 acc_hdp) != DDI_SUCCESS) {
15654 ddi_dma_free_handle(dma_hdp);
15655 return (FALSE);
15656 }
15657
15658 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
15659 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
15660 cookiep, &ncookie) != DDI_DMA_MAPPED) {
15661 (void) ddi_dma_mem_free(acc_hdp);
15662 ddi_dma_free_handle(dma_hdp);
15663 return (FALSE);
15664 }
15665
15666 return (TRUE);
15667 }
15668
15669 void
15670 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
15671 {
15672 if (*dma_hdp == NULL)
15673 return;
15674
15675 (void) ddi_dma_unbind_handle(*dma_hdp);
15676 (void) ddi_dma_mem_free(acc_hdp);
15677 ddi_dma_free_handle(dma_hdp);
15678 }