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--- old/usr/src/uts/intel/os/archdep.c
+++ new/usr/src/uts/intel/os/archdep.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 26 /* All Rights Reserved */
27 27 /*
28 28 * Copyright (c) 2018, Joyent, Inc.
29 29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 30 * Copyright 2023 Oxide Computer Company
31 31 */
32 32
33 33 #include <sys/param.h>
34 34 #include <sys/types.h>
35 35 #include <sys/vmparam.h>
36 36 #include <sys/systm.h>
37 37 #include <sys/signal.h>
38 38 #include <sys/stack.h>
39 39 #include <sys/regset.h>
40 40 #include <sys/privregs.h>
41 41 #include <sys/frame.h>
42 42 #include <sys/proc.h>
43 43 #include <sys/psw.h>
44 44 #include <sys/siginfo.h>
45 45 #include <sys/cpuvar.h>
46 46 #include <sys/asm_linkage.h>
47 47 #include <sys/kmem.h>
48 48 #include <sys/errno.h>
49 49 #include <sys/bootconf.h>
50 50 #include <sys/archsystm.h>
51 51 #include <sys/debug.h>
52 52 #include <sys/elf.h>
53 53 #include <sys/spl.h>
54 54 #include <sys/time.h>
55 55 #include <sys/atomic.h>
56 56 #include <sys/sysmacros.h>
57 57 #include <sys/cmn_err.h>
58 58 #include <sys/modctl.h>
59 59 #include <sys/kobj.h>
60 60 #include <sys/panic.h>
61 61 #include <sys/reboot.h>
62 62 #include <sys/time.h>
63 63 #include <sys/fp.h>
64 64 #include <sys/x86_archext.h>
65 65 #include <sys/auxv.h>
66 66 #include <sys/auxv_386.h>
67 67 #include <sys/dtrace.h>
68 68 #include <sys/brand.h>
69 69 #include <sys/machbrand.h>
70 70 #include <sys/cmn_err.h>
71 71
72 72 /*
73 73 * Map an fnsave-formatted save area into an fxsave-formatted save area.
74 74 *
75 75 * Most fields are the same width, content and semantics. However
76 76 * the tag word is compressed.
77 77 */
78 78 static void
79 79 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
80 80 {
81 81 uint_t i, tagbits;
82 82
83 83 fx->fx_fcw = fn->f_fcw;
84 84 fx->fx_fsw = fn->f_fsw;
85 85
86 86 /*
87 87 * copy element by element (because of holes)
88 88 */
89 89 for (i = 0; i < 8; i++)
90 90 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
91 91 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
92 92
93 93 /*
94 94 * synthesize compressed tag bits
95 95 */
96 96 fx->fx_fctw = 0;
97 97 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
98 98 if ((tagbits & 3) != 3)
99 99 fx->fx_fctw |= (1 << i);
100 100
101 101 fx->fx_fop = fn->f_fop;
102 102
103 103 fx->fx_rip = (uint64_t)fn->f_eip;
104 104 fx->fx_rdp = (uint64_t)fn->f_dp;
105 105 }
106 106
107 107 /*
108 108 * Map from an fxsave-format save area to an fnsave-format save area.
109 109 */
110 110 static void
111 111 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
112 112 {
113 113 uint_t i, top, tagbits;
114 114
115 115 fn->f_fcw = fx->fx_fcw;
116 116 fn->__f_ign0 = 0;
117 117 fn->f_fsw = fx->fx_fsw;
118 118 fn->__f_ign1 = 0;
119 119
120 120 top = (fx->fx_fsw & FPS_TOP) >> 11;
121 121
122 122 /*
123 123 * copy element by element (because of holes)
124 124 */
125 125 for (i = 0; i < 8; i++)
126 126 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
127 127 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
128 128
129 129 /*
130 130 * synthesize uncompressed tag bits
131 131 */
132 132 fn->f_ftw = 0;
133 133 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
134 134 uint_t ibit, expo;
135 135 const uint16_t *fpp;
136 136 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
137 137
138 138 if ((tagbits & 1) == 0) {
139 139 fn->f_ftw |= 3 << (i << 1); /* empty */
140 140 continue;
141 141 }
142 142
143 143 /*
144 144 * (tags refer to *physical* registers)
145 145 */
146 146 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
147 147 ibit = fpp[3] >> 15;
148 148 expo = fpp[4] & 0x7fff;
149 149
150 150 if (ibit && expo != 0 && expo != 0x7fff)
151 151 continue; /* valid fp number */
152 152
153 153 if (bcmp(fpp, &zero, sizeof (zero)))
154 154 fn->f_ftw |= 2 << (i << 1); /* NaN */
155 155 else
156 156 fn->f_ftw |= 1 << (i << 1); /* fp zero */
157 157 }
158 158
159 159 fn->f_fop = fx->fx_fop;
160 160
161 161 fn->__f_ign2 = 0;
162 162 fn->f_eip = (uint32_t)fx->fx_rip;
163 163 fn->f_cs = U32CS_SEL;
164 164 fn->f_dp = (uint32_t)fx->fx_rdp;
165 165 fn->f_ds = UDS_SEL;
166 166 fn->__f_ign3 = 0;
167 167 }
168 168
169 169 /*
170 170 * Map from an fpregset_t into an fxsave-format save area
171 171 */
172 172 static void
173 173 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
174 174 {
175 175 bcopy(fp, fx, sizeof (*fx));
176 176 /*
177 177 * avoid useless #gp exceptions - mask reserved bits
178 178 */
179 179 fx->fx_mxcsr &= sse_mxcsr_mask;
180 180 }
181 181
182 182 /*
183 183 * Map from an fxsave-format save area into a fpregset_t
184 184 */
185 185 static void
186 186 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
187 187 {
188 188 bcopy(fx, fp, sizeof (*fx));
189 189 }
190 190
191 191 #if defined(_SYSCALL32_IMPL)
192 192 static void
193 193 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
194 194 {
195 195 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
196 196
197 197 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
198 198 /*
199 199 * avoid useless #gp exceptions - mask reserved bits
200 200 */
201 201 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
202 202 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
203 203 }
204 204
205 205 static void
206 206 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
207 207 {
208 208 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
209 209
210 210 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
211 211 fc->mxcsr = fx->fx_mxcsr;
212 212 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
213 213 }
214 214
215 215 static void
216 216 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
217 217 {
218 218 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
219 219 dst->fp_reg_set.fpchip_state.status =
220 220 src->fp_reg_set.fpchip_state.status;
221 221 dst->fp_reg_set.fpchip_state.xstatus =
222 222 src->fp_reg_set.fpchip_state.xstatus;
223 223 }
224 224
225 225 static void
226 226 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
227 227 {
228 228 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
229 229 dst->fp_reg_set.fpchip_state.status =
230 230 src->fp_reg_set.fpchip_state.status;
231 231 dst->fp_reg_set.fpchip_state.xstatus =
232 232 src->fp_reg_set.fpchip_state.xstatus;
233 233 }
234 234 #endif
235 235
236 236 /*
237 237 * Set floating-point registers from a native fpregset_t.
238 238 */
239 239 void
240 240 setfpregs(klwp_t *lwp, fpregset_t *fp)
241 241 {
242 242 fpu_set_fpregset(lwp, fp);
243 243 }
244 244
245 245 /*
246 246 * Get floating-point registers into a native fpregset_t.
247 247 */
248 248 void
249 249 getfpregs(klwp_t *lwp, fpregset_t *fp)
250 250 {
251 251 bzero(fp, sizeof (*fp));
252 252 fpu_get_fpregset(lwp, fp);
253 253 }
254 254
255 255 #if defined(_SYSCALL32_IMPL)
256 256
257 257 /*
258 258 * Set floating-point registers from an fpregset32_t.
259 259 */
260 260 void
261 261 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
262 262 {
263 263 fpregset_t fpregs;
264 264
265 265 fpregset_32ton(fp, &fpregs);
266 266 setfpregs(lwp, &fpregs);
267 267 }
268 268
269 269 /*
270 270 * Get floating-point registers into an fpregset32_t.
271 271 */
272 272 void
273 273 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
274 274 {
275 275 fpregset_t fpregs;
276 276
277 277 getfpregs(lwp, &fpregs);
278 278 fpregset_nto32(&fpregs, fp);
279 279 }
280 280
281 281 #endif /* _SYSCALL32_IMPL */
282 282
283 283 /*
284 284 * Return the general registers
285 285 */
286 286 void
287 287 getgregs(klwp_t *lwp, gregset_t grp)
288 288 {
289 289 struct regs *rp = lwptoregs(lwp);
290 290 struct pcb *pcb = &lwp->lwp_pcb;
291 291 int thisthread = lwptot(lwp) == curthread;
292 292
293 293 grp[REG_RDI] = rp->r_rdi;
294 294 grp[REG_RSI] = rp->r_rsi;
295 295 grp[REG_RDX] = rp->r_rdx;
296 296 grp[REG_RCX] = rp->r_rcx;
297 297 grp[REG_R8] = rp->r_r8;
298 298 grp[REG_R9] = rp->r_r9;
299 299 grp[REG_RAX] = rp->r_rax;
300 300 grp[REG_RBX] = rp->r_rbx;
301 301 grp[REG_RBP] = rp->r_rbp;
302 302 grp[REG_R10] = rp->r_r10;
303 303 grp[REG_R11] = rp->r_r11;
304 304 grp[REG_R12] = rp->r_r12;
305 305 grp[REG_R13] = rp->r_r13;
306 306 grp[REG_R14] = rp->r_r14;
307 307 grp[REG_R15] = rp->r_r15;
308 308 grp[REG_FSBASE] = pcb->pcb_fsbase;
309 309 grp[REG_GSBASE] = pcb->pcb_gsbase;
310 310 if (thisthread)
311 311 kpreempt_disable();
312 312 if (PCB_NEED_UPDATE_SEGS(pcb)) {
313 313 grp[REG_DS] = pcb->pcb_ds;
314 314 grp[REG_ES] = pcb->pcb_es;
315 315 grp[REG_FS] = pcb->pcb_fs;
316 316 grp[REG_GS] = pcb->pcb_gs;
317 317 } else {
318 318 grp[REG_DS] = rp->r_ds;
319 319 grp[REG_ES] = rp->r_es;
320 320 grp[REG_FS] = rp->r_fs;
321 321 grp[REG_GS] = rp->r_gs;
322 322 }
323 323 if (thisthread)
324 324 kpreempt_enable();
325 325 grp[REG_TRAPNO] = rp->r_trapno;
326 326 grp[REG_ERR] = rp->r_err;
327 327 grp[REG_RIP] = rp->r_rip;
328 328 grp[REG_CS] = rp->r_cs;
329 329 grp[REG_SS] = rp->r_ss;
330 330 grp[REG_RFL] = rp->r_rfl;
331 331 grp[REG_RSP] = rp->r_rsp;
332 332 }
333 333
334 334 #if defined(_SYSCALL32_IMPL)
335 335
336 336 void
337 337 getgregs32(klwp_t *lwp, gregset32_t grp)
338 338 {
339 339 struct regs *rp = lwptoregs(lwp);
340 340 struct pcb *pcb = &lwp->lwp_pcb;
341 341 int thisthread = lwptot(lwp) == curthread;
342 342
343 343 if (thisthread)
344 344 kpreempt_disable();
345 345 if (PCB_NEED_UPDATE_SEGS(pcb)) {
346 346 grp[GS] = (uint16_t)pcb->pcb_gs;
347 347 grp[FS] = (uint16_t)pcb->pcb_fs;
348 348 grp[DS] = (uint16_t)pcb->pcb_ds;
349 349 grp[ES] = (uint16_t)pcb->pcb_es;
350 350 } else {
351 351 grp[GS] = (uint16_t)rp->r_gs;
352 352 grp[FS] = (uint16_t)rp->r_fs;
353 353 grp[DS] = (uint16_t)rp->r_ds;
354 354 grp[ES] = (uint16_t)rp->r_es;
355 355 }
356 356 if (thisthread)
357 357 kpreempt_enable();
358 358 grp[EDI] = (greg32_t)rp->r_rdi;
359 359 grp[ESI] = (greg32_t)rp->r_rsi;
360 360 grp[EBP] = (greg32_t)rp->r_rbp;
361 361 grp[ESP] = 0;
362 362 grp[EBX] = (greg32_t)rp->r_rbx;
363 363 grp[EDX] = (greg32_t)rp->r_rdx;
364 364 grp[ECX] = (greg32_t)rp->r_rcx;
365 365 grp[EAX] = (greg32_t)rp->r_rax;
366 366 grp[TRAPNO] = (greg32_t)rp->r_trapno;
367 367 grp[ERR] = (greg32_t)rp->r_err;
368 368 grp[EIP] = (greg32_t)rp->r_rip;
369 369 grp[CS] = (uint16_t)rp->r_cs;
370 370 grp[EFL] = (greg32_t)rp->r_rfl;
371 371 grp[UESP] = (greg32_t)rp->r_rsp;
372 372 grp[SS] = (uint16_t)rp->r_ss;
373 373 }
374 374
375 375 void
376 376 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
377 377 {
378 378 mcontext_t *dmc = &dst->uc_mcontext;
379 379 const mcontext32_t *smc = &src->uc_mcontext;
380 380
381 381 bzero(dst, sizeof (*dst));
382 382 dst->uc_flags = src->uc_flags;
383 383 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
384 384
385 385 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
386 386
387 387 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
388 388 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
389 389 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
390 390
391 391 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
392 392 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
393 393 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
394 394 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
395 395 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
396 396 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
397 397 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
398 398 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
399 399 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
400 400 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
401 401 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
402 402 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
403 403 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
404 404 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
405 405 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
406 406 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
407 407 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
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408 408 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
409 409
410 410 /*
411 411 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
412 412 * otherwise there is no guarantee that anything in fpregs is valid.
413 413 */
414 414 if (src->uc_flags & UC_FPU)
415 415 fpregset_32ton(&src->uc_mcontext.fpregs,
416 416 &dst->uc_mcontext.fpregs);
417 417
418 + /*
419 + * Copy the brand-private data:
420 + */
421 + dst->uc_brand_data[0] = (void *)(uintptr_t)src->uc_brand_data[0];
422 + dst->uc_brand_data[1] = (void *)(uintptr_t)src->uc_brand_data[1];
423 + dst->uc_brand_data[2] = (void *)(uintptr_t)src->uc_brand_data[2];
424 +
418 425 if (src->uc_flags & UC_XSAVE) {
419 426 dst->uc_xsave = (long)(uint32_t)src->uc_xsave;
420 427 } else {
421 428 dst->uc_xsave = 0;
422 429 }
423 430 }
424 431
425 432 #endif /* _SYSCALL32_IMPL */
426 433
427 434 /*
428 435 * Return the user-level PC.
429 436 * If in a system call, return the address of the syscall trap.
430 437 */
431 438 greg_t
432 439 getuserpc(void)
433 440 {
434 441 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
435 442 uint32_t insn;
436 443
437 444 if (curthread->t_sysnum == 0)
438 445 return (upc);
439 446
440 447 /*
441 448 * We might've gotten here from sysenter (0xf 0x34),
442 449 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
443 450 *
444 451 * Go peek at the binary to figure it out..
445 452 */
446 453 if (fuword32((void *)(upc - 2), &insn) != -1 &&
447 454 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
448 455 return (upc - 2);
449 456 return (upc - 7);
450 457 }
451 458
452 459 /*
453 460 * Protect segment registers from non-user privilege levels and GDT selectors
454 461 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
455 462 * selector is non-null and not USER_CS/USER_DS, we make sure that the
456 463 * TI bit is set to point into the LDT and that the RPL is set to 3.
457 464 *
458 465 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
459 466 * also explicitly zero the top 16 bits since they may be coming from the
460 467 * user's address space via setcontext(2) or /proc.
461 468 *
462 469 * Note about null selector. When running on the hypervisor if we allow a
463 470 * process to set its %cs to null selector with RPL of 0 the hypervisor will
464 471 * crash the domain. If running on bare metal we would get a #gp fault and
465 472 * be able to kill the process and continue on. Therefore we make sure to
466 473 * force RPL to SEL_UPL even for null selector when setting %cs.
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467 474 */
468 475
469 476 #if defined(IS_CS) || defined(IS_NOT_CS)
470 477 #error "IS_CS and IS_NOT_CS already defined"
471 478 #endif
472 479
473 480 #define IS_CS 1
474 481 #define IS_NOT_CS 0
475 482
476 483 /*ARGSUSED*/
477 -static greg_t
484 +greg_t
478 485 fix_segreg(greg_t sr, int iscs, model_t datamodel)
479 486 {
487 + kthread_t *t = curthread;
488 +
480 489 switch (sr &= 0xffff) {
481 490
482 491 case 0:
483 492 if (iscs == IS_CS)
484 493 return (0 | SEL_UPL);
485 494 else
486 495 return (0);
487 496
488 497 /*
489 498 * If lwp attempts to switch data model then force their
490 499 * code selector to be null selector.
491 500 */
492 501 case U32CS_SEL:
493 502 if (datamodel == DATAMODEL_NATIVE)
494 503 return (0 | SEL_UPL);
495 504 else
496 505 return (sr);
497 506
498 507 case UCS_SEL:
499 508 if (datamodel == DATAMODEL_ILP32)
500 509 return (0 | SEL_UPL);
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501 510 /*FALLTHROUGH*/
502 511 case UDS_SEL:
503 512 case LWPFS_SEL:
504 513 case LWPGS_SEL:
505 514 case SEL_UPL:
506 515 return (sr);
507 516 default:
508 517 break;
509 518 }
510 519
520 + /*
521 + * Allow this process's brand to do any necessary segment register
522 + * manipulation.
523 + */
524 + if (PROC_IS_BRANDED(t->t_procp) && BRMOP(t->t_procp)->b_fixsegreg) {
525 + greg_t bsr = BRMOP(t->t_procp)->b_fixsegreg(sr, datamodel);
526 +
527 + if (bsr == 0 && iscs == IS_CS)
528 + return (0 | SEL_UPL);
529 + else
530 + return (bsr);
531 + }
532 +
511 533 /*
512 534 * Force it into the LDT in ring 3 for 32-bit processes, which by
513 535 * default do not have an LDT, so that any attempt to use an invalid
514 536 * selector will reference the (non-existant) LDT, and cause a #gp
515 537 * fault for the process.
516 538 *
517 539 * 64-bit processes get the null gdt selector since they
518 540 * are not allowed to have a private LDT.
519 541 */
520 542 if (datamodel == DATAMODEL_ILP32) {
521 543 return (sr | SEL_TI_LDT | SEL_UPL);
522 544 } else {
523 545 if (iscs == IS_CS)
524 546 return (0 | SEL_UPL);
525 547 else
526 548 return (0);
527 549 }
528 550
529 551 }
530 552
531 553 /*
532 554 * Set general registers.
533 555 */
534 556 void
535 557 setgregs(klwp_t *lwp, gregset_t grp)
536 558 {
537 559 struct regs *rp = lwptoregs(lwp);
538 560 model_t datamodel = lwp_getdatamodel(lwp);
539 561
540 562 struct pcb *pcb = &lwp->lwp_pcb;
541 563 int thisthread = lwptot(lwp) == curthread;
542 564
543 565 if (datamodel == DATAMODEL_NATIVE) {
544 566 if (thisthread)
545 567 (void) save_syscall_args(); /* copy the args */
546 568
547 569 rp->r_rdi = grp[REG_RDI];
548 570 rp->r_rsi = grp[REG_RSI];
549 571 rp->r_rdx = grp[REG_RDX];
550 572 rp->r_rcx = grp[REG_RCX];
551 573 rp->r_r8 = grp[REG_R8];
552 574 rp->r_r9 = grp[REG_R9];
553 575 rp->r_rax = grp[REG_RAX];
554 576 rp->r_rbx = grp[REG_RBX];
555 577 rp->r_rbp = grp[REG_RBP];
556 578 rp->r_r10 = grp[REG_R10];
557 579 rp->r_r11 = grp[REG_R11];
558 580 rp->r_r12 = grp[REG_R12];
559 581 rp->r_r13 = grp[REG_R13];
560 582 rp->r_r14 = grp[REG_R14];
561 583 rp->r_r15 = grp[REG_R15];
562 584 rp->r_trapno = grp[REG_TRAPNO];
563 585 rp->r_err = grp[REG_ERR];
564 586 rp->r_rip = grp[REG_RIP];
565 587 /*
566 588 * Setting %cs or %ss to anything else is quietly but
567 589 * quite definitely forbidden!
568 590 */
569 591 rp->r_cs = UCS_SEL;
570 592 rp->r_ss = UDS_SEL;
571 593 rp->r_rsp = grp[REG_RSP];
572 594
573 595 if (thisthread)
574 596 kpreempt_disable();
575 597
576 598 pcb->pcb_ds = UDS_SEL;
577 599 pcb->pcb_es = UDS_SEL;
578 600
579 601 /*
580 602 * 64-bit processes -are- allowed to set their fsbase/gsbase
581 603 * values directly, but only if they're using the segment
582 604 * selectors that allow that semantic.
583 605 *
584 606 * (32-bit processes must use lwp_set_private().)
585 607 */
586 608 pcb->pcb_fsbase = grp[REG_FSBASE];
587 609 pcb->pcb_gsbase = grp[REG_GSBASE];
588 610 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
589 611 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
590 612
591 613 /*
592 614 * Ensure that we go out via update_sregs
593 615 */
594 616 PCB_SET_UPDATE_SEGS(pcb);
595 617 lwptot(lwp)->t_post_sys = 1;
596 618 if (thisthread)
597 619 kpreempt_enable();
598 620 #if defined(_SYSCALL32_IMPL)
599 621 } else {
600 622 rp->r_rdi = (uint32_t)grp[REG_RDI];
601 623 rp->r_rsi = (uint32_t)grp[REG_RSI];
602 624 rp->r_rdx = (uint32_t)grp[REG_RDX];
603 625 rp->r_rcx = (uint32_t)grp[REG_RCX];
604 626 rp->r_rax = (uint32_t)grp[REG_RAX];
605 627 rp->r_rbx = (uint32_t)grp[REG_RBX];
606 628 rp->r_rbp = (uint32_t)grp[REG_RBP];
607 629 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
608 630 rp->r_err = (uint32_t)grp[REG_ERR];
609 631 rp->r_rip = (uint32_t)grp[REG_RIP];
610 632
611 633 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
612 634 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
613 635
614 636 rp->r_rsp = (uint32_t)grp[REG_RSP];
615 637
616 638 if (thisthread)
617 639 kpreempt_disable();
618 640
619 641 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
620 642 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
621 643
622 644 /*
623 645 * (See fsbase/gsbase commentary above)
624 646 */
625 647 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
626 648 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
627 649
628 650 /*
629 651 * Ensure that we go out via update_sregs
630 652 */
631 653 PCB_SET_UPDATE_SEGS(pcb);
632 654 lwptot(lwp)->t_post_sys = 1;
633 655 if (thisthread)
634 656 kpreempt_enable();
635 657 #endif
636 658 }
637 659
638 660 /*
639 661 * Only certain bits of the flags register can be modified.
640 662 */
641 663 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
642 664 (grp[REG_RFL] & PSL_USERMASK);
643 665 }
644 666
645 667 /*
646 668 * Determine whether eip is likely to have an interrupt frame
647 669 * on the stack. We do this by comparing the address to the
648 670 * range of addresses spanned by several well-known routines.
649 671 */
650 672 extern void _interrupt();
651 673 extern void _allsyscalls();
652 674 extern void _cmntrap();
653 675 extern void fakesoftint();
654 676
655 677 extern size_t _interrupt_size;
656 678 extern size_t _allsyscalls_size;
657 679 extern size_t _cmntrap_size;
658 680 extern size_t _fakesoftint_size;
659 681
660 682 /*
661 683 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
662 684 * Returns MIN(current stack depth, pcstack_limit).
663 685 */
664 686 int
665 687 getpcstack(pc_t *pcstack, int pcstack_limit)
666 688 {
667 689 struct frame *fp = (struct frame *)getfp();
668 690 struct frame *nextfp, *minfp, *stacktop;
669 691 int depth = 0;
670 692 int on_intr;
671 693 uintptr_t pc;
672 694
673 695 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
674 696 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
675 697 else
676 698 stacktop = (struct frame *)curthread->t_stk;
677 699 minfp = fp;
678 700
679 701 pc = ((struct regs *)fp)->r_pc;
680 702
681 703 while (depth < pcstack_limit) {
682 704 nextfp = (struct frame *)fp->fr_savfp;
683 705 pc = fp->fr_savpc;
684 706 if (nextfp <= minfp || nextfp >= stacktop) {
685 707 if (on_intr) {
686 708 /*
687 709 * Hop from interrupt stack to thread stack.
688 710 */
689 711 stacktop = (struct frame *)curthread->t_stk;
690 712 minfp = (struct frame *)curthread->t_stkbase;
691 713 on_intr = 0;
692 714 continue;
693 715 }
694 716 break;
695 717 }
696 718 pcstack[depth++] = (pc_t)pc;
697 719 fp = nextfp;
698 720 minfp = fp;
699 721 }
700 722 return (depth);
701 723 }
702 724
703 725 /*
704 726 * The following ELF header fields are defined as processor-specific
705 727 * in the V8 ABI:
706 728 *
707 729 * e_ident[EI_DATA] encoding of the processor-specific
708 730 * data in the object file
709 731 * e_machine processor identification
710 732 * e_flags processor-specific flags associated
711 733 * with the file
712 734 */
713 735
714 736 /*
715 737 * The value of at_flags reflects a platform's cpu module support.
716 738 * at_flags is used to check for allowing a binary to execute and
717 739 * is passed as the value of the AT_FLAGS auxiliary vector.
718 740 */
719 741 int at_flags = 0;
720 742
721 743 /*
722 744 * Check the processor-specific fields of an ELF header.
723 745 *
724 746 * returns 1 if the fields are valid, 0 otherwise
725 747 */
726 748 /*ARGSUSED2*/
727 749 int
728 750 elfheadcheck(
729 751 unsigned char e_data,
730 752 Elf32_Half e_machine,
731 753 Elf32_Word e_flags)
732 754 {
733 755 if (e_data != ELFDATA2LSB)
734 756 return (0);
735 757 if (e_machine == EM_AMD64)
736 758 return (1);
737 759 return (e_machine == EM_386);
738 760 }
739 761
740 762 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
741 763 uint_t auxv_hwcap_include_2 = 0; /* second word */
742 764 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
743 765 uint_t auxv_hwcap_exclude_2 = 0; /* second word */
744 766 #if defined(_SYSCALL32_IMPL)
745 767 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
746 768 uint_t auxv_hwcap32_include_2 = 0; /* ditto for 32-bit apps */
747 769 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
748 770 uint_t auxv_hwcap32_exclude_2 = 0; /* ditto for 32-bit apps */
749 771 #endif
750 772
751 773 /*
752 774 * Gather information about the processor and place it into auxv_hwcap
753 775 * so that it can be exported to the linker via the aux vector.
754 776 *
755 777 * We use this seemingly complicated mechanism so that we can ensure
756 778 * that /etc/system can be used to override what the system can or
757 779 * cannot discover for itself. Due to a lack of use, this has not
758 780 * been extended to the 3rd word.
759 781 */
760 782 void
761 783 bind_hwcap(void)
762 784 {
763 785 uint_t cpu_hwcap_flags[3];
764 786 cpuid_execpass(NULL, CPUID_PASS_RESOLVE, cpu_hwcap_flags);
765 787
766 788 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags[0]) &
767 789 ~auxv_hwcap_exclude;
768 790 auxv_hwcap_2 = (auxv_hwcap_include_2 | cpu_hwcap_flags[1]) &
769 791 ~auxv_hwcap_exclude_2;
770 792 auxv_hwcap_3 = cpu_hwcap_flags[2];
771 793
772 794 /*
773 795 * On AMD processors, sysenter just doesn't work at all
774 796 * when the kernel is in long mode. On IA-32e processors
775 797 * it does, but there's no real point in all the alternate
776 798 * mechanism when syscall works on both.
777 799 *
778 800 * Besides, the kernel's sysenter handler is expecting a
779 801 * 32-bit lwp ...
780 802 */
781 803 auxv_hwcap &= ~AV_386_SEP;
782 804
783 805 if (auxv_hwcap_include || auxv_hwcap_exclude || auxv_hwcap_include_2 ||
784 806 auxv_hwcap_exclude_2) {
785 807 /*
786 808 * The below assignment is regrettably required to get lint
787 809 * to accept the validity of our format string. The format
788 810 * string is in fact valid, but whatever intelligence in lint
789 811 * understands the cmn_err()-specific %b appears to have an
790 812 * off-by-one error: it (mistakenly) complains about bit
791 813 * number 32 (even though this is explicitly permitted).
792 814 * Normally, one would will away such warnings with a "LINTED"
793 815 * directive, but for reasons unclear and unknown, lint
794 816 * refuses to be assuaged in this case. Fortunately, lint
795 817 * doesn't pretend to have solved the Halting Problem --
796 818 * and as soon as the format string is programmatic, it
797 819 * knows enough to shut up.
798 820 */
799 821 char *fmt = "?user ABI extensions: %b\n";
800 822 cmn_err(CE_CONT, fmt, auxv_hwcap, FMT_AV_386);
801 823 fmt = "?user ABI extensions (word 2): %b\n";
802 824 cmn_err(CE_CONT, fmt, auxv_hwcap_2, FMT_AV_386_2);
803 825 fmt = "?user ABI extensions (word 2): %b\n";
804 826 cmn_err(CE_CONT, fmt, auxv_hwcap_3, FMT_AV_386_3);
805 827 }
806 828
807 829 #if defined(_SYSCALL32_IMPL)
808 830 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags[0]) &
809 831 ~auxv_hwcap32_exclude;
810 832 auxv_hwcap32_2 = (auxv_hwcap32_include_2 | cpu_hwcap_flags[1]) &
811 833 ~auxv_hwcap32_exclude_2;
812 834 auxv_hwcap32_3 = auxv_hwcap_3;
813 835
814 836 /*
815 837 * If this is an amd64 architecture machine from Intel, then
816 838 * syscall -doesn't- work in compatibility mode, only sysenter does.
817 839 *
818 840 * Sigh.
819 841 */
820 842 if (!cpuid_syscall32_insn(NULL))
821 843 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
822 844
823 845 /*
824 846 * 32-bit processes can -always- use the lahf/sahf instructions
825 847 */
826 848 auxv_hwcap32 |= AV_386_AHF;
827 849
828 850 /*
829 851 * 32-bit processes can -never- use fsgsbase instructions.
830 852 */
831 853 auxv_hwcap32_2 &= ~AV_386_2_FSGSBASE;
832 854
833 855 if (auxv_hwcap32_include || auxv_hwcap32_exclude ||
834 856 auxv_hwcap32_include_2 || auxv_hwcap32_exclude_2) {
835 857 /*
836 858 * See the block comment in the cmn_err() of auxv_hwcap, above.
837 859 */
838 860 char *fmt = "?32-bit user ABI extensions: %b\n";
839 861 cmn_err(CE_CONT, fmt, auxv_hwcap32, FMT_AV_386);
840 862 fmt = "?32-bit user ABI extensions (word 2): %b\n";
841 863 cmn_err(CE_CONT, fmt, auxv_hwcap32_2, FMT_AV_386_2);
842 864 fmt = "?32-bit user ABI extensions (word 3): %b\n";
843 865 cmn_err(CE_CONT, fmt, auxv_hwcap32_3, FMT_AV_386_3);
844 866 }
845 867 #endif
846 868 }
847 869
848 870 /*
849 871 * sync_icache() - this is called
850 872 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
851 873 * this is a nop.
852 874 */
853 875 /* ARGSUSED */
854 876 void
855 877 sync_icache(caddr_t addr, uint_t len)
856 878 {
857 879 /* Do nothing for now */
858 880 }
859 881
860 882 /*ARGSUSED*/
861 883 void
862 884 sync_data_memory(caddr_t va, size_t len)
863 885 {
864 886 /* Not implemented for this platform */
865 887 }
866 888
867 889 int
868 890 __ipltospl(int ipl)
869 891 {
870 892 return (ipltospl(ipl));
871 893 }
872 894
873 895 /*
874 896 * The panic code invokes panic_saveregs() to record the contents of a
875 897 * regs structure into the specified panic_data structure for debuggers.
876 898 */
877 899 void
878 900 panic_saveregs(panic_data_t *pdp, struct regs *rp)
879 901 {
880 902 panic_nv_t *pnv = PANICNVGET(pdp);
881 903
882 904 struct cregs creg;
883 905
884 906 getcregs(&creg);
885 907
886 908 PANICNVADD(pnv, "rdi", rp->r_rdi);
887 909 PANICNVADD(pnv, "rsi", rp->r_rsi);
888 910 PANICNVADD(pnv, "rdx", rp->r_rdx);
889 911 PANICNVADD(pnv, "rcx", rp->r_rcx);
890 912 PANICNVADD(pnv, "r8", rp->r_r8);
891 913 PANICNVADD(pnv, "r9", rp->r_r9);
892 914 PANICNVADD(pnv, "rax", rp->r_rax);
893 915 PANICNVADD(pnv, "rbx", rp->r_rbx);
894 916 PANICNVADD(pnv, "rbp", rp->r_rbp);
895 917 PANICNVADD(pnv, "r10", rp->r_r10);
896 918 PANICNVADD(pnv, "r11", rp->r_r11);
897 919 PANICNVADD(pnv, "r12", rp->r_r12);
898 920 PANICNVADD(pnv, "r13", rp->r_r13);
899 921 PANICNVADD(pnv, "r14", rp->r_r14);
900 922 PANICNVADD(pnv, "r15", rp->r_r15);
901 923 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
902 924 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
903 925 PANICNVADD(pnv, "ds", rp->r_ds);
904 926 PANICNVADD(pnv, "es", rp->r_es);
905 927 PANICNVADD(pnv, "fs", rp->r_fs);
906 928 PANICNVADD(pnv, "gs", rp->r_gs);
907 929 PANICNVADD(pnv, "trapno", rp->r_trapno);
908 930 PANICNVADD(pnv, "err", rp->r_err);
909 931 PANICNVADD(pnv, "rip", rp->r_rip);
910 932 PANICNVADD(pnv, "cs", rp->r_cs);
911 933 PANICNVADD(pnv, "rflags", rp->r_rfl);
912 934 PANICNVADD(pnv, "rsp", rp->r_rsp);
913 935 PANICNVADD(pnv, "ss", rp->r_ss);
914 936 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
915 937 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
916 938 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
917 939 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
918 940
919 941 PANICNVADD(pnv, "ldt", creg.cr_ldt);
920 942 PANICNVADD(pnv, "task", creg.cr_task);
921 943 PANICNVADD(pnv, "cr0", creg.cr_cr0);
922 944 PANICNVADD(pnv, "cr2", creg.cr_cr2);
923 945 PANICNVADD(pnv, "cr3", creg.cr_cr3);
924 946 if (creg.cr_cr4)
925 947 PANICNVADD(pnv, "cr4", creg.cr_cr4);
926 948
927 949 PANICNVSET(pdp, pnv);
928 950 }
929 951
930 952 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
931 953
932 954
933 955 /*
934 956 * Print a stack backtrace using the specified frame pointer. We delay two
935 957 * seconds before continuing, unless this is the panic traceback.
936 958 * If we are in the process of panicking, we also attempt to write the
937 959 * stack backtrace to a staticly assigned buffer, to allow the panic
938 960 * code to find it and write it in to uncompressed pages within the
939 961 * system crash dump.
940 962 * Note that the frame for the starting stack pointer value is omitted because
941 963 * the corresponding %eip is not known.
942 964 */
943 965
944 966 extern char *dump_stack_scratch;
945 967
946 968
947 969 void
948 970 traceback(caddr_t fpreg)
949 971 {
950 972 struct frame *fp = (struct frame *)fpreg;
951 973 struct frame *nextfp;
952 974 uintptr_t pc, nextpc;
953 975 ulong_t off;
954 976 char args[TR_ARG_MAX * 2 + 16], *sym;
955 977 uint_t offset = 0;
956 978 uint_t next_offset = 0;
957 979 char stack_buffer[1024];
958 980
959 981 if (!panicstr)
960 982 printf("traceback: %%fp = %p\n", (void *)fp);
961 983
962 984 if (panicstr && !dump_stack_scratch) {
963 985 printf("Warning - stack not written to the dump buffer\n");
964 986 }
965 987
966 988 fp = (struct frame *)plat_traceback(fpreg);
967 989 if ((uintptr_t)fp < KERNELBASE)
968 990 goto out;
969 991
970 992 pc = fp->fr_savpc;
971 993 fp = (struct frame *)fp->fr_savfp;
972 994
973 995 while ((uintptr_t)fp >= KERNELBASE) {
974 996 /*
975 997 * XX64 Until port is complete tolerate 8-byte aligned
976 998 * frame pointers but flag with a warning so they can
977 999 * be fixed.
978 1000 */
979 1001 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
980 1002 if (((uintptr_t)fp & (8 - 1)) == 0) {
981 1003 printf(" >> warning! 8-byte"
982 1004 " aligned %%fp = %p\n", (void *)fp);
983 1005 } else {
984 1006 printf(
985 1007 " >> mis-aligned %%fp = %p\n", (void *)fp);
986 1008 break;
987 1009 }
988 1010 }
989 1011
990 1012 args[0] = '\0';
991 1013 nextpc = (uintptr_t)fp->fr_savpc;
992 1014 nextfp = (struct frame *)fp->fr_savfp;
993 1015 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
994 1016 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
995 1017 mod_containing_pc((caddr_t)pc), sym, off, args);
996 1018 (void) snprintf(stack_buffer, sizeof (stack_buffer),
997 1019 "%s:%s+%lx (%s) | ",
998 1020 mod_containing_pc((caddr_t)pc), sym, off, args);
999 1021 } else {
1000 1022 printf("%016lx %lx (%s)\n",
1001 1023 (uintptr_t)fp, pc, args);
1002 1024 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1003 1025 "%lx (%s) | ", pc, args);
1004 1026 }
1005 1027
1006 1028 if (panicstr && dump_stack_scratch) {
1007 1029 next_offset = offset + strlen(stack_buffer);
1008 1030 if (next_offset < STACK_BUF_SIZE) {
1009 1031 bcopy(stack_buffer, dump_stack_scratch + offset,
1010 1032 strlen(stack_buffer));
1011 1033 offset = next_offset;
1012 1034 } else {
1013 1035 /*
1014 1036 * In attempting to save the panic stack
1015 1037 * to the dumpbuf we have overflowed that area.
1016 1038 * Print a warning and continue to printf the
1017 1039 * stack to the msgbuf
1018 1040 */
1019 1041 printf("Warning: stack in the dump buffer"
1020 1042 " may be incomplete\n");
1021 1043 offset = next_offset;
1022 1044 }
1023 1045 }
1024 1046
1025 1047 pc = nextpc;
1026 1048 fp = nextfp;
1027 1049 }
1028 1050 out:
1029 1051 if (!panicstr) {
1030 1052 printf("end of traceback\n");
1031 1053 DELAY(2 * MICROSEC);
1032 1054 } else if (dump_stack_scratch) {
1033 1055 dump_stack_scratch[offset] = '\0';
1034 1056 }
1035 1057 }
1036 1058
1037 1059
1038 1060 /*
1039 1061 * Generate a stack backtrace from a saved register set.
1040 1062 */
1041 1063 void
1042 1064 traceregs(struct regs *rp)
1043 1065 {
1044 1066 traceback((caddr_t)rp->r_fp);
1045 1067 }
1046 1068
1047 1069 void
1048 1070 exec_set_sp(size_t stksize)
1049 1071 {
1050 1072 klwp_t *lwp = ttolwp(curthread);
1051 1073
1052 1074 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1053 1075 }
1054 1076
1055 1077 hrtime_t
1056 1078 gethrtime_waitfree(void)
1057 1079 {
1058 1080 return (dtrace_gethrtime());
1059 1081 }
1060 1082
1061 1083 hrtime_t
1062 1084 gethrtime(void)
1063 1085 {
1064 1086 return (gethrtimef());
1065 1087 }
1066 1088
1067 1089 hrtime_t
1068 1090 gethrtime_unscaled(void)
1069 1091 {
1070 1092 return (gethrtimeunscaledf());
1071 1093 }
1072 1094
1073 1095 void
1074 1096 scalehrtime(hrtime_t *hrt)
1075 1097 {
1076 1098 scalehrtimef(hrt);
1077 1099 }
1078 1100
1079 1101 uint64_t
1080 1102 unscalehrtime(hrtime_t nsecs)
1081 1103 {
1082 1104 return (unscalehrtimef(nsecs));
1083 1105 }
1084 1106
1085 1107 void
1086 1108 gethrestime(timespec_t *tp)
1087 1109 {
1088 1110 gethrestimef(tp);
1089 1111 }
1090 1112
1091 1113 /*
1092 1114 * Part of the implementation of hres_tick(); this routine is
1093 1115 * easier in C than assembler .. called with the hres_lock held.
1094 1116 *
1095 1117 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1096 1118 */
1097 1119
1098 1120 #include <sys/time.h>
1099 1121 #include <sys/machlock.h>
1100 1122
1101 1123 extern int one_sec;
1102 1124 extern int max_hres_adj;
1103 1125
1104 1126 void
1105 1127 __adj_hrestime(void)
1106 1128 {
1107 1129 long long adj;
1108 1130
1109 1131 if (hrestime_adj == 0)
1110 1132 adj = 0;
1111 1133 else if (hrestime_adj > 0) {
1112 1134 if (hrestime_adj < max_hres_adj)
1113 1135 adj = hrestime_adj;
1114 1136 else
1115 1137 adj = max_hres_adj;
1116 1138 } else {
1117 1139 if (hrestime_adj < -max_hres_adj)
1118 1140 adj = -max_hres_adj;
1119 1141 else
1120 1142 adj = hrestime_adj;
1121 1143 }
1122 1144
1123 1145 timedelta -= adj;
1124 1146 hrestime_adj = timedelta;
1125 1147 hrestime.tv_nsec += adj;
1126 1148
1127 1149 while (hrestime.tv_nsec >= NANOSEC) {
1128 1150 one_sec++;
1129 1151 hrestime.tv_sec++;
1130 1152 hrestime.tv_nsec -= NANOSEC;
1131 1153 }
1132 1154 }
1133 1155
1134 1156 /*
1135 1157 * Wrapper functions to maintain backwards compability
1136 1158 */
1137 1159 int
1138 1160 xcopyin(const void *uaddr, void *kaddr, size_t count)
1139 1161 {
1140 1162 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1141 1163 }
1142 1164
1143 1165 int
1144 1166 xcopyout(const void *kaddr, void *uaddr, size_t count)
1145 1167 {
1146 1168 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1147 1169 }
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