1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */
26 /* All Rights Reserved */
27 /*
28 * Copyright (c) 2018, Joyent, Inc.
29 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
30 * Copyright 2023 Oxide Computer Company
31 */
32
33 #include <sys/param.h>
34 #include <sys/types.h>
35 #include <sys/vmparam.h>
36 #include <sys/systm.h>
37 #include <sys/signal.h>
38 #include <sys/stack.h>
39 #include <sys/regset.h>
40 #include <sys/privregs.h>
41 #include <sys/frame.h>
42 #include <sys/proc.h>
43 #include <sys/psw.h>
44 #include <sys/siginfo.h>
45 #include <sys/cpuvar.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/kmem.h>
48 #include <sys/errno.h>
49 #include <sys/bootconf.h>
50 #include <sys/archsystm.h>
51 #include <sys/debug.h>
52 #include <sys/elf.h>
53 #include <sys/spl.h>
54 #include <sys/time.h>
55 #include <sys/atomic.h>
56 #include <sys/sysmacros.h>
57 #include <sys/cmn_err.h>
58 #include <sys/modctl.h>
59 #include <sys/kobj.h>
60 #include <sys/panic.h>
61 #include <sys/reboot.h>
62 #include <sys/time.h>
63 #include <sys/fp.h>
64 #include <sys/x86_archext.h>
65 #include <sys/auxv.h>
66 #include <sys/auxv_386.h>
67 #include <sys/dtrace.h>
68 #include <sys/brand.h>
69 #include <sys/machbrand.h>
70 #include <sys/cmn_err.h>
71
72 /*
73 * Map an fnsave-formatted save area into an fxsave-formatted save area.
74 *
75 * Most fields are the same width, content and semantics. However
76 * the tag word is compressed.
77 */
78 static void
79 fnsave_to_fxsave(const struct fnsave_state *fn, struct fxsave_state *fx)
80 {
81 uint_t i, tagbits;
82
83 fx->fx_fcw = fn->f_fcw;
84 fx->fx_fsw = fn->f_fsw;
85
86 /*
87 * copy element by element (because of holes)
88 */
89 for (i = 0; i < 8; i++)
90 bcopy(&fn->f_st[i].fpr_16[0], &fx->fx_st[i].fpr_16[0],
91 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
92
93 /*
94 * synthesize compressed tag bits
95 */
96 fx->fx_fctw = 0;
97 for (tagbits = fn->f_ftw, i = 0; i < 8; i++, tagbits >>= 2)
98 if ((tagbits & 3) != 3)
99 fx->fx_fctw |= (1 << i);
100
101 fx->fx_fop = fn->f_fop;
102
103 fx->fx_rip = (uint64_t)fn->f_eip;
104 fx->fx_rdp = (uint64_t)fn->f_dp;
105 }
106
107 /*
108 * Map from an fxsave-format save area to an fnsave-format save area.
109 */
110 static void
111 fxsave_to_fnsave(const struct fxsave_state *fx, struct fnsave_state *fn)
112 {
113 uint_t i, top, tagbits;
114
115 fn->f_fcw = fx->fx_fcw;
116 fn->__f_ign0 = 0;
117 fn->f_fsw = fx->fx_fsw;
118 fn->__f_ign1 = 0;
119
120 top = (fx->fx_fsw & FPS_TOP) >> 11;
121
122 /*
123 * copy element by element (because of holes)
124 */
125 for (i = 0; i < 8; i++)
126 bcopy(&fx->fx_st[i].fpr_16[0], &fn->f_st[i].fpr_16[0],
127 sizeof (fn->f_st[0].fpr_16)); /* 80-bit x87-style floats */
128
129 /*
130 * synthesize uncompressed tag bits
131 */
132 fn->f_ftw = 0;
133 for (tagbits = fx->fx_fctw, i = 0; i < 8; i++, tagbits >>= 1) {
134 uint_t ibit, expo;
135 const uint16_t *fpp;
136 static const uint16_t zero[5] = { 0, 0, 0, 0, 0 };
137
138 if ((tagbits & 1) == 0) {
139 fn->f_ftw |= 3 << (i << 1); /* empty */
140 continue;
141 }
142
143 /*
144 * (tags refer to *physical* registers)
145 */
146 fpp = &fx->fx_st[(i - top + 8) & 7].fpr_16[0];
147 ibit = fpp[3] >> 15;
148 expo = fpp[4] & 0x7fff;
149
150 if (ibit && expo != 0 && expo != 0x7fff)
151 continue; /* valid fp number */
152
153 if (bcmp(fpp, &zero, sizeof (zero)))
154 fn->f_ftw |= 2 << (i << 1); /* NaN */
155 else
156 fn->f_ftw |= 1 << (i << 1); /* fp zero */
157 }
158
159 fn->f_fop = fx->fx_fop;
160
161 fn->__f_ign2 = 0;
162 fn->f_eip = (uint32_t)fx->fx_rip;
163 fn->f_cs = U32CS_SEL;
164 fn->f_dp = (uint32_t)fx->fx_rdp;
165 fn->f_ds = UDS_SEL;
166 fn->__f_ign3 = 0;
167 }
168
169 /*
170 * Map from an fpregset_t into an fxsave-format save area
171 */
172 static void
173 fpregset_to_fxsave(const fpregset_t *fp, struct fxsave_state *fx)
174 {
175 bcopy(fp, fx, sizeof (*fx));
176 /*
177 * avoid useless #gp exceptions - mask reserved bits
178 */
179 fx->fx_mxcsr &= sse_mxcsr_mask;
180 }
181
182 /*
183 * Map from an fxsave-format save area into a fpregset_t
184 */
185 static void
186 fxsave_to_fpregset(const struct fxsave_state *fx, fpregset_t *fp)
187 {
188 bcopy(fx, fp, sizeof (*fx));
189 }
190
191 #if defined(_SYSCALL32_IMPL)
192 static void
193 fpregset32_to_fxsave(const fpregset32_t *fp, struct fxsave_state *fx)
194 {
195 const struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
196
197 fnsave_to_fxsave((const struct fnsave_state *)fc, fx);
198 /*
199 * avoid useless #gp exceptions - mask reserved bits
200 */
201 fx->fx_mxcsr = sse_mxcsr_mask & fc->mxcsr;
202 bcopy(&fc->xmm[0], &fx->fx_xmm[0], sizeof (fc->xmm));
203 }
204
205 static void
206 fxsave_to_fpregset32(const struct fxsave_state *fx, fpregset32_t *fp)
207 {
208 struct fpchip32_state *fc = &fp->fp_reg_set.fpchip_state;
209
210 fxsave_to_fnsave(fx, (struct fnsave_state *)fc);
211 fc->mxcsr = fx->fx_mxcsr;
212 bcopy(&fx->fx_xmm[0], &fc->xmm[0], sizeof (fc->xmm));
213 }
214
215 static void
216 fpregset_nto32(const fpregset_t *src, fpregset32_t *dst)
217 {
218 fxsave_to_fpregset32((struct fxsave_state *)src, dst);
219 dst->fp_reg_set.fpchip_state.status =
220 src->fp_reg_set.fpchip_state.status;
221 dst->fp_reg_set.fpchip_state.xstatus =
222 src->fp_reg_set.fpchip_state.xstatus;
223 }
224
225 static void
226 fpregset_32ton(const fpregset32_t *src, fpregset_t *dst)
227 {
228 fpregset32_to_fxsave(src, (struct fxsave_state *)dst);
229 dst->fp_reg_set.fpchip_state.status =
230 src->fp_reg_set.fpchip_state.status;
231 dst->fp_reg_set.fpchip_state.xstatus =
232 src->fp_reg_set.fpchip_state.xstatus;
233 }
234 #endif
235
236 /*
237 * Set floating-point registers from a native fpregset_t.
238 */
239 void
240 setfpregs(klwp_t *lwp, fpregset_t *fp)
241 {
242 fpu_set_fpregset(lwp, fp);
243 }
244
245 /*
246 * Get floating-point registers into a native fpregset_t.
247 */
248 void
249 getfpregs(klwp_t *lwp, fpregset_t *fp)
250 {
251 bzero(fp, sizeof (*fp));
252 fpu_get_fpregset(lwp, fp);
253 }
254
255 #if defined(_SYSCALL32_IMPL)
256
257 /*
258 * Set floating-point registers from an fpregset32_t.
259 */
260 void
261 setfpregs32(klwp_t *lwp, fpregset32_t *fp)
262 {
263 fpregset_t fpregs;
264
265 fpregset_32ton(fp, &fpregs);
266 setfpregs(lwp, &fpregs);
267 }
268
269 /*
270 * Get floating-point registers into an fpregset32_t.
271 */
272 void
273 getfpregs32(klwp_t *lwp, fpregset32_t *fp)
274 {
275 fpregset_t fpregs;
276
277 getfpregs(lwp, &fpregs);
278 fpregset_nto32(&fpregs, fp);
279 }
280
281 #endif /* _SYSCALL32_IMPL */
282
283 /*
284 * Return the general registers
285 */
286 void
287 getgregs(klwp_t *lwp, gregset_t grp)
288 {
289 struct regs *rp = lwptoregs(lwp);
290 struct pcb *pcb = &lwp->lwp_pcb;
291 int thisthread = lwptot(lwp) == curthread;
292
293 grp[REG_RDI] = rp->r_rdi;
294 grp[REG_RSI] = rp->r_rsi;
295 grp[REG_RDX] = rp->r_rdx;
296 grp[REG_RCX] = rp->r_rcx;
297 grp[REG_R8] = rp->r_r8;
298 grp[REG_R9] = rp->r_r9;
299 grp[REG_RAX] = rp->r_rax;
300 grp[REG_RBX] = rp->r_rbx;
301 grp[REG_RBP] = rp->r_rbp;
302 grp[REG_R10] = rp->r_r10;
303 grp[REG_R11] = rp->r_r11;
304 grp[REG_R12] = rp->r_r12;
305 grp[REG_R13] = rp->r_r13;
306 grp[REG_R14] = rp->r_r14;
307 grp[REG_R15] = rp->r_r15;
308 grp[REG_FSBASE] = pcb->pcb_fsbase;
309 grp[REG_GSBASE] = pcb->pcb_gsbase;
310 if (thisthread)
311 kpreempt_disable();
312 if (PCB_NEED_UPDATE_SEGS(pcb)) {
313 grp[REG_DS] = pcb->pcb_ds;
314 grp[REG_ES] = pcb->pcb_es;
315 grp[REG_FS] = pcb->pcb_fs;
316 grp[REG_GS] = pcb->pcb_gs;
317 } else {
318 grp[REG_DS] = rp->r_ds;
319 grp[REG_ES] = rp->r_es;
320 grp[REG_FS] = rp->r_fs;
321 grp[REG_GS] = rp->r_gs;
322 }
323 if (thisthread)
324 kpreempt_enable();
325 grp[REG_TRAPNO] = rp->r_trapno;
326 grp[REG_ERR] = rp->r_err;
327 grp[REG_RIP] = rp->r_rip;
328 grp[REG_CS] = rp->r_cs;
329 grp[REG_SS] = rp->r_ss;
330 grp[REG_RFL] = rp->r_rfl;
331 grp[REG_RSP] = rp->r_rsp;
332 }
333
334 #if defined(_SYSCALL32_IMPL)
335
336 void
337 getgregs32(klwp_t *lwp, gregset32_t grp)
338 {
339 struct regs *rp = lwptoregs(lwp);
340 struct pcb *pcb = &lwp->lwp_pcb;
341 int thisthread = lwptot(lwp) == curthread;
342
343 if (thisthread)
344 kpreempt_disable();
345 if (PCB_NEED_UPDATE_SEGS(pcb)) {
346 grp[GS] = (uint16_t)pcb->pcb_gs;
347 grp[FS] = (uint16_t)pcb->pcb_fs;
348 grp[DS] = (uint16_t)pcb->pcb_ds;
349 grp[ES] = (uint16_t)pcb->pcb_es;
350 } else {
351 grp[GS] = (uint16_t)rp->r_gs;
352 grp[FS] = (uint16_t)rp->r_fs;
353 grp[DS] = (uint16_t)rp->r_ds;
354 grp[ES] = (uint16_t)rp->r_es;
355 }
356 if (thisthread)
357 kpreempt_enable();
358 grp[EDI] = (greg32_t)rp->r_rdi;
359 grp[ESI] = (greg32_t)rp->r_rsi;
360 grp[EBP] = (greg32_t)rp->r_rbp;
361 grp[ESP] = 0;
362 grp[EBX] = (greg32_t)rp->r_rbx;
363 grp[EDX] = (greg32_t)rp->r_rdx;
364 grp[ECX] = (greg32_t)rp->r_rcx;
365 grp[EAX] = (greg32_t)rp->r_rax;
366 grp[TRAPNO] = (greg32_t)rp->r_trapno;
367 grp[ERR] = (greg32_t)rp->r_err;
368 grp[EIP] = (greg32_t)rp->r_rip;
369 grp[CS] = (uint16_t)rp->r_cs;
370 grp[EFL] = (greg32_t)rp->r_rfl;
371 grp[UESP] = (greg32_t)rp->r_rsp;
372 grp[SS] = (uint16_t)rp->r_ss;
373 }
374
375 void
376 ucontext_32ton(const ucontext32_t *src, ucontext_t *dst)
377 {
378 mcontext_t *dmc = &dst->uc_mcontext;
379 const mcontext32_t *smc = &src->uc_mcontext;
380
381 bzero(dst, sizeof (*dst));
382 dst->uc_flags = src->uc_flags;
383 dst->uc_link = (ucontext_t *)(uintptr_t)src->uc_link;
384
385 bcopy(&src->uc_sigmask, &dst->uc_sigmask, sizeof (dst->uc_sigmask));
386
387 dst->uc_stack.ss_sp = (void *)(uintptr_t)src->uc_stack.ss_sp;
388 dst->uc_stack.ss_size = (size_t)src->uc_stack.ss_size;
389 dst->uc_stack.ss_flags = src->uc_stack.ss_flags;
390
391 dmc->gregs[REG_GS] = (greg_t)(uint32_t)smc->gregs[GS];
392 dmc->gregs[REG_FS] = (greg_t)(uint32_t)smc->gregs[FS];
393 dmc->gregs[REG_ES] = (greg_t)(uint32_t)smc->gregs[ES];
394 dmc->gregs[REG_DS] = (greg_t)(uint32_t)smc->gregs[DS];
395 dmc->gregs[REG_RDI] = (greg_t)(uint32_t)smc->gregs[EDI];
396 dmc->gregs[REG_RSI] = (greg_t)(uint32_t)smc->gregs[ESI];
397 dmc->gregs[REG_RBP] = (greg_t)(uint32_t)smc->gregs[EBP];
398 dmc->gregs[REG_RBX] = (greg_t)(uint32_t)smc->gregs[EBX];
399 dmc->gregs[REG_RDX] = (greg_t)(uint32_t)smc->gregs[EDX];
400 dmc->gregs[REG_RCX] = (greg_t)(uint32_t)smc->gregs[ECX];
401 dmc->gregs[REG_RAX] = (greg_t)(uint32_t)smc->gregs[EAX];
402 dmc->gregs[REG_TRAPNO] = (greg_t)(uint32_t)smc->gregs[TRAPNO];
403 dmc->gregs[REG_ERR] = (greg_t)(uint32_t)smc->gregs[ERR];
404 dmc->gregs[REG_RIP] = (greg_t)(uint32_t)smc->gregs[EIP];
405 dmc->gregs[REG_CS] = (greg_t)(uint32_t)smc->gregs[CS];
406 dmc->gregs[REG_RFL] = (greg_t)(uint32_t)smc->gregs[EFL];
407 dmc->gregs[REG_RSP] = (greg_t)(uint32_t)smc->gregs[UESP];
408 dmc->gregs[REG_SS] = (greg_t)(uint32_t)smc->gregs[SS];
409
410 /*
411 * A valid fpregs is only copied in if uc.uc_flags has UC_FPU set
412 * otherwise there is no guarantee that anything in fpregs is valid.
413 */
414 if (src->uc_flags & UC_FPU)
415 fpregset_32ton(&src->uc_mcontext.fpregs,
416 &dst->uc_mcontext.fpregs);
417
418 if (src->uc_flags & UC_XSAVE) {
419 dst->uc_xsave = (long)(uint32_t)src->uc_xsave;
420 } else {
421 dst->uc_xsave = 0;
422 }
423 }
424
425 #endif /* _SYSCALL32_IMPL */
426
427 /*
428 * Return the user-level PC.
429 * If in a system call, return the address of the syscall trap.
430 */
431 greg_t
432 getuserpc(void)
433 {
434 greg_t upc = lwptoregs(ttolwp(curthread))->r_pc;
435 uint32_t insn;
436
437 if (curthread->t_sysnum == 0)
438 return (upc);
439
440 /*
441 * We might've gotten here from sysenter (0xf 0x34),
442 * syscall (0xf 0x5) or lcall (0x9a 0 0 0 0 0x27 0).
443 *
444 * Go peek at the binary to figure it out..
445 */
446 if (fuword32((void *)(upc - 2), &insn) != -1 &&
447 (insn & 0xffff) == 0x340f || (insn & 0xffff) == 0x050f)
448 return (upc - 2);
449 return (upc - 7);
450 }
451
452 /*
453 * Protect segment registers from non-user privilege levels and GDT selectors
454 * other than USER_CS, USER_DS and lwp FS and GS values. If the segment
455 * selector is non-null and not USER_CS/USER_DS, we make sure that the
456 * TI bit is set to point into the LDT and that the RPL is set to 3.
457 *
458 * Since struct regs stores each 16-bit segment register as a 32-bit greg_t, we
459 * also explicitly zero the top 16 bits since they may be coming from the
460 * user's address space via setcontext(2) or /proc.
461 *
462 * Note about null selector. When running on the hypervisor if we allow a
463 * process to set its %cs to null selector with RPL of 0 the hypervisor will
464 * crash the domain. If running on bare metal we would get a #gp fault and
465 * be able to kill the process and continue on. Therefore we make sure to
466 * force RPL to SEL_UPL even for null selector when setting %cs.
467 */
468
469 #if defined(IS_CS) || defined(IS_NOT_CS)
470 #error "IS_CS and IS_NOT_CS already defined"
471 #endif
472
473 #define IS_CS 1
474 #define IS_NOT_CS 0
475
476 /*ARGSUSED*/
477 static greg_t
478 fix_segreg(greg_t sr, int iscs, model_t datamodel)
479 {
480 switch (sr &= 0xffff) {
481
482 case 0:
483 if (iscs == IS_CS)
484 return (0 | SEL_UPL);
485 else
486 return (0);
487
488 /*
489 * If lwp attempts to switch data model then force their
490 * code selector to be null selector.
491 */
492 case U32CS_SEL:
493 if (datamodel == DATAMODEL_NATIVE)
494 return (0 | SEL_UPL);
495 else
496 return (sr);
497
498 case UCS_SEL:
499 if (datamodel == DATAMODEL_ILP32)
500 return (0 | SEL_UPL);
501 /*FALLTHROUGH*/
502 case UDS_SEL:
503 case LWPFS_SEL:
504 case LWPGS_SEL:
505 case SEL_UPL:
506 return (sr);
507 default:
508 break;
509 }
510
511 /*
512 * Force it into the LDT in ring 3 for 32-bit processes, which by
513 * default do not have an LDT, so that any attempt to use an invalid
514 * selector will reference the (non-existant) LDT, and cause a #gp
515 * fault for the process.
516 *
517 * 64-bit processes get the null gdt selector since they
518 * are not allowed to have a private LDT.
519 */
520 if (datamodel == DATAMODEL_ILP32) {
521 return (sr | SEL_TI_LDT | SEL_UPL);
522 } else {
523 if (iscs == IS_CS)
524 return (0 | SEL_UPL);
525 else
526 return (0);
527 }
528
529 }
530
531 /*
532 * Set general registers.
533 */
534 void
535 setgregs(klwp_t *lwp, gregset_t grp)
536 {
537 struct regs *rp = lwptoregs(lwp);
538 model_t datamodel = lwp_getdatamodel(lwp);
539
540 struct pcb *pcb = &lwp->lwp_pcb;
541 int thisthread = lwptot(lwp) == curthread;
542
543 if (datamodel == DATAMODEL_NATIVE) {
544 if (thisthread)
545 (void) save_syscall_args(); /* copy the args */
546
547 rp->r_rdi = grp[REG_RDI];
548 rp->r_rsi = grp[REG_RSI];
549 rp->r_rdx = grp[REG_RDX];
550 rp->r_rcx = grp[REG_RCX];
551 rp->r_r8 = grp[REG_R8];
552 rp->r_r9 = grp[REG_R9];
553 rp->r_rax = grp[REG_RAX];
554 rp->r_rbx = grp[REG_RBX];
555 rp->r_rbp = grp[REG_RBP];
556 rp->r_r10 = grp[REG_R10];
557 rp->r_r11 = grp[REG_R11];
558 rp->r_r12 = grp[REG_R12];
559 rp->r_r13 = grp[REG_R13];
560 rp->r_r14 = grp[REG_R14];
561 rp->r_r15 = grp[REG_R15];
562 rp->r_trapno = grp[REG_TRAPNO];
563 rp->r_err = grp[REG_ERR];
564 rp->r_rip = grp[REG_RIP];
565 /*
566 * Setting %cs or %ss to anything else is quietly but
567 * quite definitely forbidden!
568 */
569 rp->r_cs = UCS_SEL;
570 rp->r_ss = UDS_SEL;
571 rp->r_rsp = grp[REG_RSP];
572
573 if (thisthread)
574 kpreempt_disable();
575
576 pcb->pcb_ds = UDS_SEL;
577 pcb->pcb_es = UDS_SEL;
578
579 /*
580 * 64-bit processes -are- allowed to set their fsbase/gsbase
581 * values directly, but only if they're using the segment
582 * selectors that allow that semantic.
583 *
584 * (32-bit processes must use lwp_set_private().)
585 */
586 pcb->pcb_fsbase = grp[REG_FSBASE];
587 pcb->pcb_gsbase = grp[REG_GSBASE];
588 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
589 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
590
591 /*
592 * Ensure that we go out via update_sregs
593 */
594 PCB_SET_UPDATE_SEGS(pcb);
595 lwptot(lwp)->t_post_sys = 1;
596 if (thisthread)
597 kpreempt_enable();
598 #if defined(_SYSCALL32_IMPL)
599 } else {
600 rp->r_rdi = (uint32_t)grp[REG_RDI];
601 rp->r_rsi = (uint32_t)grp[REG_RSI];
602 rp->r_rdx = (uint32_t)grp[REG_RDX];
603 rp->r_rcx = (uint32_t)grp[REG_RCX];
604 rp->r_rax = (uint32_t)grp[REG_RAX];
605 rp->r_rbx = (uint32_t)grp[REG_RBX];
606 rp->r_rbp = (uint32_t)grp[REG_RBP];
607 rp->r_trapno = (uint32_t)grp[REG_TRAPNO];
608 rp->r_err = (uint32_t)grp[REG_ERR];
609 rp->r_rip = (uint32_t)grp[REG_RIP];
610
611 rp->r_cs = fix_segreg(grp[REG_CS], IS_CS, datamodel);
612 rp->r_ss = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
613
614 rp->r_rsp = (uint32_t)grp[REG_RSP];
615
616 if (thisthread)
617 kpreempt_disable();
618
619 pcb->pcb_ds = fix_segreg(grp[REG_DS], IS_NOT_CS, datamodel);
620 pcb->pcb_es = fix_segreg(grp[REG_ES], IS_NOT_CS, datamodel);
621
622 /*
623 * (See fsbase/gsbase commentary above)
624 */
625 pcb->pcb_fs = fix_segreg(grp[REG_FS], IS_NOT_CS, datamodel);
626 pcb->pcb_gs = fix_segreg(grp[REG_GS], IS_NOT_CS, datamodel);
627
628 /*
629 * Ensure that we go out via update_sregs
630 */
631 PCB_SET_UPDATE_SEGS(pcb);
632 lwptot(lwp)->t_post_sys = 1;
633 if (thisthread)
634 kpreempt_enable();
635 #endif
636 }
637
638 /*
639 * Only certain bits of the flags register can be modified.
640 */
641 rp->r_rfl = (rp->r_rfl & ~PSL_USERMASK) |
642 (grp[REG_RFL] & PSL_USERMASK);
643 }
644
645 /*
646 * Determine whether eip is likely to have an interrupt frame
647 * on the stack. We do this by comparing the address to the
648 * range of addresses spanned by several well-known routines.
649 */
650 extern void _interrupt();
651 extern void _allsyscalls();
652 extern void _cmntrap();
653 extern void fakesoftint();
654
655 extern size_t _interrupt_size;
656 extern size_t _allsyscalls_size;
657 extern size_t _cmntrap_size;
658 extern size_t _fakesoftint_size;
659
660 /*
661 * Get a pc-only stacktrace. Used for kmem_alloc() buffer ownership tracking.
662 * Returns MIN(current stack depth, pcstack_limit).
663 */
664 int
665 getpcstack(pc_t *pcstack, int pcstack_limit)
666 {
667 struct frame *fp = (struct frame *)getfp();
668 struct frame *nextfp, *minfp, *stacktop;
669 int depth = 0;
670 int on_intr;
671 uintptr_t pc;
672
673 if ((on_intr = CPU_ON_INTR(CPU)) != 0)
674 stacktop = (struct frame *)(CPU->cpu_intr_stack + SA(MINFRAME));
675 else
676 stacktop = (struct frame *)curthread->t_stk;
677 minfp = fp;
678
679 pc = ((struct regs *)fp)->r_pc;
680
681 while (depth < pcstack_limit) {
682 nextfp = (struct frame *)fp->fr_savfp;
683 pc = fp->fr_savpc;
684 if (nextfp <= minfp || nextfp >= stacktop) {
685 if (on_intr) {
686 /*
687 * Hop from interrupt stack to thread stack.
688 */
689 stacktop = (struct frame *)curthread->t_stk;
690 minfp = (struct frame *)curthread->t_stkbase;
691 on_intr = 0;
692 continue;
693 }
694 break;
695 }
696 pcstack[depth++] = (pc_t)pc;
697 fp = nextfp;
698 minfp = fp;
699 }
700 return (depth);
701 }
702
703 /*
704 * The following ELF header fields are defined as processor-specific
705 * in the V8 ABI:
706 *
707 * e_ident[EI_DATA] encoding of the processor-specific
708 * data in the object file
709 * e_machine processor identification
710 * e_flags processor-specific flags associated
711 * with the file
712 */
713
714 /*
715 * The value of at_flags reflects a platform's cpu module support.
716 * at_flags is used to check for allowing a binary to execute and
717 * is passed as the value of the AT_FLAGS auxiliary vector.
718 */
719 int at_flags = 0;
720
721 /*
722 * Check the processor-specific fields of an ELF header.
723 *
724 * returns 1 if the fields are valid, 0 otherwise
725 */
726 /*ARGSUSED2*/
727 int
728 elfheadcheck(
729 unsigned char e_data,
730 Elf32_Half e_machine,
731 Elf32_Word e_flags)
732 {
733 if (e_data != ELFDATA2LSB)
734 return (0);
735 if (e_machine == EM_AMD64)
736 return (1);
737 return (e_machine == EM_386);
738 }
739
740 uint_t auxv_hwcap_include = 0; /* patch to enable unrecognized features */
741 uint_t auxv_hwcap_include_2 = 0; /* second word */
742 uint_t auxv_hwcap_exclude = 0; /* patch for broken cpus, debugging */
743 uint_t auxv_hwcap_exclude_2 = 0; /* second word */
744 #if defined(_SYSCALL32_IMPL)
745 uint_t auxv_hwcap32_include = 0; /* ditto for 32-bit apps */
746 uint_t auxv_hwcap32_include_2 = 0; /* ditto for 32-bit apps */
747 uint_t auxv_hwcap32_exclude = 0; /* ditto for 32-bit apps */
748 uint_t auxv_hwcap32_exclude_2 = 0; /* ditto for 32-bit apps */
749 #endif
750
751 /*
752 * Gather information about the processor and place it into auxv_hwcap
753 * so that it can be exported to the linker via the aux vector.
754 *
755 * We use this seemingly complicated mechanism so that we can ensure
756 * that /etc/system can be used to override what the system can or
757 * cannot discover for itself. Due to a lack of use, this has not
758 * been extended to the 3rd word.
759 */
760 void
761 bind_hwcap(void)
762 {
763 uint_t cpu_hwcap_flags[3];
764 cpuid_execpass(NULL, CPUID_PASS_RESOLVE, cpu_hwcap_flags);
765
766 auxv_hwcap = (auxv_hwcap_include | cpu_hwcap_flags[0]) &
767 ~auxv_hwcap_exclude;
768 auxv_hwcap_2 = (auxv_hwcap_include_2 | cpu_hwcap_flags[1]) &
769 ~auxv_hwcap_exclude_2;
770 auxv_hwcap_3 = cpu_hwcap_flags[2];
771
772 /*
773 * On AMD processors, sysenter just doesn't work at all
774 * when the kernel is in long mode. On IA-32e processors
775 * it does, but there's no real point in all the alternate
776 * mechanism when syscall works on both.
777 *
778 * Besides, the kernel's sysenter handler is expecting a
779 * 32-bit lwp ...
780 */
781 auxv_hwcap &= ~AV_386_SEP;
782
783 if (auxv_hwcap_include || auxv_hwcap_exclude || auxv_hwcap_include_2 ||
784 auxv_hwcap_exclude_2) {
785 /*
786 * The below assignment is regrettably required to get lint
787 * to accept the validity of our format string. The format
788 * string is in fact valid, but whatever intelligence in lint
789 * understands the cmn_err()-specific %b appears to have an
790 * off-by-one error: it (mistakenly) complains about bit
791 * number 32 (even though this is explicitly permitted).
792 * Normally, one would will away such warnings with a "LINTED"
793 * directive, but for reasons unclear and unknown, lint
794 * refuses to be assuaged in this case. Fortunately, lint
795 * doesn't pretend to have solved the Halting Problem --
796 * and as soon as the format string is programmatic, it
797 * knows enough to shut up.
798 */
799 char *fmt = "?user ABI extensions: %b\n";
800 cmn_err(CE_CONT, fmt, auxv_hwcap, FMT_AV_386);
801 fmt = "?user ABI extensions (word 2): %b\n";
802 cmn_err(CE_CONT, fmt, auxv_hwcap_2, FMT_AV_386_2);
803 fmt = "?user ABI extensions (word 2): %b\n";
804 cmn_err(CE_CONT, fmt, auxv_hwcap_3, FMT_AV_386_3);
805 }
806
807 #if defined(_SYSCALL32_IMPL)
808 auxv_hwcap32 = (auxv_hwcap32_include | cpu_hwcap_flags[0]) &
809 ~auxv_hwcap32_exclude;
810 auxv_hwcap32_2 = (auxv_hwcap32_include_2 | cpu_hwcap_flags[1]) &
811 ~auxv_hwcap32_exclude_2;
812 auxv_hwcap32_3 = auxv_hwcap_3;
813
814 /*
815 * If this is an amd64 architecture machine from Intel, then
816 * syscall -doesn't- work in compatibility mode, only sysenter does.
817 *
818 * Sigh.
819 */
820 if (!cpuid_syscall32_insn(NULL))
821 auxv_hwcap32 &= ~AV_386_AMD_SYSC;
822
823 /*
824 * 32-bit processes can -always- use the lahf/sahf instructions
825 */
826 auxv_hwcap32 |= AV_386_AHF;
827
828 /*
829 * 32-bit processes can -never- use fsgsbase instructions.
830 */
831 auxv_hwcap32_2 &= ~AV_386_2_FSGSBASE;
832
833 if (auxv_hwcap32_include || auxv_hwcap32_exclude ||
834 auxv_hwcap32_include_2 || auxv_hwcap32_exclude_2) {
835 /*
836 * See the block comment in the cmn_err() of auxv_hwcap, above.
837 */
838 char *fmt = "?32-bit user ABI extensions: %b\n";
839 cmn_err(CE_CONT, fmt, auxv_hwcap32, FMT_AV_386);
840 fmt = "?32-bit user ABI extensions (word 2): %b\n";
841 cmn_err(CE_CONT, fmt, auxv_hwcap32_2, FMT_AV_386_2);
842 fmt = "?32-bit user ABI extensions (word 3): %b\n";
843 cmn_err(CE_CONT, fmt, auxv_hwcap32_3, FMT_AV_386_3);
844 }
845 #endif
846 }
847
848 /*
849 * sync_icache() - this is called
850 * in proc/fs/prusrio.c. x86 has an unified cache and therefore
851 * this is a nop.
852 */
853 /* ARGSUSED */
854 void
855 sync_icache(caddr_t addr, uint_t len)
856 {
857 /* Do nothing for now */
858 }
859
860 /*ARGSUSED*/
861 void
862 sync_data_memory(caddr_t va, size_t len)
863 {
864 /* Not implemented for this platform */
865 }
866
867 int
868 __ipltospl(int ipl)
869 {
870 return (ipltospl(ipl));
871 }
872
873 /*
874 * The panic code invokes panic_saveregs() to record the contents of a
875 * regs structure into the specified panic_data structure for debuggers.
876 */
877 void
878 panic_saveregs(panic_data_t *pdp, struct regs *rp)
879 {
880 panic_nv_t *pnv = PANICNVGET(pdp);
881
882 struct cregs creg;
883
884 getcregs(&creg);
885
886 PANICNVADD(pnv, "rdi", rp->r_rdi);
887 PANICNVADD(pnv, "rsi", rp->r_rsi);
888 PANICNVADD(pnv, "rdx", rp->r_rdx);
889 PANICNVADD(pnv, "rcx", rp->r_rcx);
890 PANICNVADD(pnv, "r8", rp->r_r8);
891 PANICNVADD(pnv, "r9", rp->r_r9);
892 PANICNVADD(pnv, "rax", rp->r_rax);
893 PANICNVADD(pnv, "rbx", rp->r_rbx);
894 PANICNVADD(pnv, "rbp", rp->r_rbp);
895 PANICNVADD(pnv, "r10", rp->r_r10);
896 PANICNVADD(pnv, "r11", rp->r_r11);
897 PANICNVADD(pnv, "r12", rp->r_r12);
898 PANICNVADD(pnv, "r13", rp->r_r13);
899 PANICNVADD(pnv, "r14", rp->r_r14);
900 PANICNVADD(pnv, "r15", rp->r_r15);
901 PANICNVADD(pnv, "fsbase", rdmsr(MSR_AMD_FSBASE));
902 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE));
903 PANICNVADD(pnv, "ds", rp->r_ds);
904 PANICNVADD(pnv, "es", rp->r_es);
905 PANICNVADD(pnv, "fs", rp->r_fs);
906 PANICNVADD(pnv, "gs", rp->r_gs);
907 PANICNVADD(pnv, "trapno", rp->r_trapno);
908 PANICNVADD(pnv, "err", rp->r_err);
909 PANICNVADD(pnv, "rip", rp->r_rip);
910 PANICNVADD(pnv, "cs", rp->r_cs);
911 PANICNVADD(pnv, "rflags", rp->r_rfl);
912 PANICNVADD(pnv, "rsp", rp->r_rsp);
913 PANICNVADD(pnv, "ss", rp->r_ss);
914 PANICNVADD(pnv, "gdt_hi", (uint64_t)(creg.cr_gdt._l[3]));
915 PANICNVADD(pnv, "gdt_lo", (uint64_t)(creg.cr_gdt._l[0]));
916 PANICNVADD(pnv, "idt_hi", (uint64_t)(creg.cr_idt._l[3]));
917 PANICNVADD(pnv, "idt_lo", (uint64_t)(creg.cr_idt._l[0]));
918
919 PANICNVADD(pnv, "ldt", creg.cr_ldt);
920 PANICNVADD(pnv, "task", creg.cr_task);
921 PANICNVADD(pnv, "cr0", creg.cr_cr0);
922 PANICNVADD(pnv, "cr2", creg.cr_cr2);
923 PANICNVADD(pnv, "cr3", creg.cr_cr3);
924 if (creg.cr_cr4)
925 PANICNVADD(pnv, "cr4", creg.cr_cr4);
926
927 PANICNVSET(pdp, pnv);
928 }
929
930 #define TR_ARG_MAX 6 /* Max args to print, same as SPARC */
931
932
933 /*
934 * Print a stack backtrace using the specified frame pointer. We delay two
935 * seconds before continuing, unless this is the panic traceback.
936 * If we are in the process of panicking, we also attempt to write the
937 * stack backtrace to a staticly assigned buffer, to allow the panic
938 * code to find it and write it in to uncompressed pages within the
939 * system crash dump.
940 * Note that the frame for the starting stack pointer value is omitted because
941 * the corresponding %eip is not known.
942 */
943
944 extern char *dump_stack_scratch;
945
946
947 void
948 traceback(caddr_t fpreg)
949 {
950 struct frame *fp = (struct frame *)fpreg;
951 struct frame *nextfp;
952 uintptr_t pc, nextpc;
953 ulong_t off;
954 char args[TR_ARG_MAX * 2 + 16], *sym;
955 uint_t offset = 0;
956 uint_t next_offset = 0;
957 char stack_buffer[1024];
958
959 if (!panicstr)
960 printf("traceback: %%fp = %p\n", (void *)fp);
961
962 if (panicstr && !dump_stack_scratch) {
963 printf("Warning - stack not written to the dump buffer\n");
964 }
965
966 fp = (struct frame *)plat_traceback(fpreg);
967 if ((uintptr_t)fp < KERNELBASE)
968 goto out;
969
970 pc = fp->fr_savpc;
971 fp = (struct frame *)fp->fr_savfp;
972
973 while ((uintptr_t)fp >= KERNELBASE) {
974 /*
975 * XX64 Until port is complete tolerate 8-byte aligned
976 * frame pointers but flag with a warning so they can
977 * be fixed.
978 */
979 if (((uintptr_t)fp & (STACK_ALIGN - 1)) != 0) {
980 if (((uintptr_t)fp & (8 - 1)) == 0) {
981 printf(" >> warning! 8-byte"
982 " aligned %%fp = %p\n", (void *)fp);
983 } else {
984 printf(
985 " >> mis-aligned %%fp = %p\n", (void *)fp);
986 break;
987 }
988 }
989
990 args[0] = '\0';
991 nextpc = (uintptr_t)fp->fr_savpc;
992 nextfp = (struct frame *)fp->fr_savfp;
993 if ((sym = kobj_getsymname(pc, &off)) != NULL) {
994 printf("%016lx %s:%s+%lx (%s)\n", (uintptr_t)fp,
995 mod_containing_pc((caddr_t)pc), sym, off, args);
996 (void) snprintf(stack_buffer, sizeof (stack_buffer),
997 "%s:%s+%lx (%s) | ",
998 mod_containing_pc((caddr_t)pc), sym, off, args);
999 } else {
1000 printf("%016lx %lx (%s)\n",
1001 (uintptr_t)fp, pc, args);
1002 (void) snprintf(stack_buffer, sizeof (stack_buffer),
1003 "%lx (%s) | ", pc, args);
1004 }
1005
1006 if (panicstr && dump_stack_scratch) {
1007 next_offset = offset + strlen(stack_buffer);
1008 if (next_offset < STACK_BUF_SIZE) {
1009 bcopy(stack_buffer, dump_stack_scratch + offset,
1010 strlen(stack_buffer));
1011 offset = next_offset;
1012 } else {
1013 /*
1014 * In attempting to save the panic stack
1015 * to the dumpbuf we have overflowed that area.
1016 * Print a warning and continue to printf the
1017 * stack to the msgbuf
1018 */
1019 printf("Warning: stack in the dump buffer"
1020 " may be incomplete\n");
1021 offset = next_offset;
1022 }
1023 }
1024
1025 pc = nextpc;
1026 fp = nextfp;
1027 }
1028 out:
1029 if (!panicstr) {
1030 printf("end of traceback\n");
1031 DELAY(2 * MICROSEC);
1032 } else if (dump_stack_scratch) {
1033 dump_stack_scratch[offset] = '\0';
1034 }
1035 }
1036
1037
1038 /*
1039 * Generate a stack backtrace from a saved register set.
1040 */
1041 void
1042 traceregs(struct regs *rp)
1043 {
1044 traceback((caddr_t)rp->r_fp);
1045 }
1046
1047 void
1048 exec_set_sp(size_t stksize)
1049 {
1050 klwp_t *lwp = ttolwp(curthread);
1051
1052 lwptoregs(lwp)->r_sp = (uintptr_t)curproc->p_usrstack - stksize;
1053 }
1054
1055 hrtime_t
1056 gethrtime_waitfree(void)
1057 {
1058 return (dtrace_gethrtime());
1059 }
1060
1061 hrtime_t
1062 gethrtime(void)
1063 {
1064 return (gethrtimef());
1065 }
1066
1067 hrtime_t
1068 gethrtime_unscaled(void)
1069 {
1070 return (gethrtimeunscaledf());
1071 }
1072
1073 void
1074 scalehrtime(hrtime_t *hrt)
1075 {
1076 scalehrtimef(hrt);
1077 }
1078
1079 uint64_t
1080 unscalehrtime(hrtime_t nsecs)
1081 {
1082 return (unscalehrtimef(nsecs));
1083 }
1084
1085 void
1086 gethrestime(timespec_t *tp)
1087 {
1088 gethrestimef(tp);
1089 }
1090
1091 /*
1092 * Part of the implementation of hres_tick(); this routine is
1093 * easier in C than assembler .. called with the hres_lock held.
1094 *
1095 * XX64 Many of these timekeeping variables need to be extern'ed in a header
1096 */
1097
1098 #include <sys/time.h>
1099 #include <sys/machlock.h>
1100
1101 extern int one_sec;
1102 extern int max_hres_adj;
1103
1104 void
1105 __adj_hrestime(void)
1106 {
1107 long long adj;
1108
1109 if (hrestime_adj == 0)
1110 adj = 0;
1111 else if (hrestime_adj > 0) {
1112 if (hrestime_adj < max_hres_adj)
1113 adj = hrestime_adj;
1114 else
1115 adj = max_hres_adj;
1116 } else {
1117 if (hrestime_adj < -max_hres_adj)
1118 adj = -max_hres_adj;
1119 else
1120 adj = hrestime_adj;
1121 }
1122
1123 timedelta -= adj;
1124 hrestime_adj = timedelta;
1125 hrestime.tv_nsec += adj;
1126
1127 while (hrestime.tv_nsec >= NANOSEC) {
1128 one_sec++;
1129 hrestime.tv_sec++;
1130 hrestime.tv_nsec -= NANOSEC;
1131 }
1132 }
1133
1134 /*
1135 * Wrapper functions to maintain backwards compability
1136 */
1137 int
1138 xcopyin(const void *uaddr, void *kaddr, size_t count)
1139 {
1140 return (xcopyin_nta(uaddr, kaddr, count, UIO_COPY_CACHED));
1141 }
1142
1143 int
1144 xcopyout(const void *kaddr, void *uaddr, size_t count)
1145 {
1146 return (xcopyout_nta(kaddr, uaddr, count, UIO_COPY_CACHED));
1147 }