--- old/usr/src/test/os-tests/tests/xsave/data/mdb_xregs.ymm.32
          +++ new/usr/src/test/os-tests/tests/xsave/data/mdb_xregs.ymm.32

   1    1  x86 FPU with 256-bit %ymm registers
   2    2  xcr0            0x7
   3    3  xfd             0x0
   4    4  xstate_bv       0x7
   5    5  xcomp_bv        0x0
   6    6  
   7    7  %ymm0  [255:128] 0x12900929 12900928 12900927 12900926
   8    8  %xmm0  [127:0]   0x12900925 12900924 12900923 12900922
   9    9  
  10   10  %ymm1  [255:128] 0x12900931 12900930 1290092f 1290092e
  11   11  %xmm1  [127:0]   0x1290092d 1290092c 1290092b 1290092a
  12   12  
  13   13  %ymm2  [255:128] 0x12900939 12900938 12900937 12900936
  14   14  %xmm2  [127:0]   0x12900935 12900934 12900933 12900932
  15   15  
  16   16  %ymm3  [255:128] 0x12900941 12900940 1290093f 1290093e
  17   17  %xmm3  [127:0]   0x1290093d 1290093c 1290093b 1290093a
  18   18  
  19   19  %ymm4  [255:128] 0x12900949 12900948 12900947 12900946
  20   20  %xmm4  [127:0]   0x12900945 12900944 12900943 12900942
  21   21  
  22   22  %ymm5  [255:128] 0x12900951 12900950 1290094f 1290094e
  23   23  %xmm5  [127:0]   0x1290094d 1290094c 1290094b 1290094a
  24   24  
  25   25  %ymm6  [255:128] 0x12900959 12900958 12900957 12900956
  26   26  %xmm6  [127:0]   0x12900955 12900954 12900953 12900952
  27   27  
  28   28  %ymm7  [255:128] 0x12900961 12900960 1290095f 1290095e
  29   29  %xmm7  [127:0]   0x1290095d 1290095c 1290095b 1290095a
  30   30  
  31   31  387 and FP Control State
  32   32  cw     0x137f (IM|DM|ZM|OM|UM|PM|SIG64|RTN|A)
  33   33  sw     0x0000 (TOP=0t0) (0)
  34   34  xcp sw 0x0000 (0)
  35   35  
  36   36  ipoff  0
  37   37  cssel  0x43
  38   38  dtoff  0
  39   39  dtsel  0x4b
  40   40  
  41   41  %st0   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  42   42  %st1   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  43   43  %st2   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  44   44  %st3   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  45   45  %st4   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  46   46  %st5   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  47   47  %st6   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  48   48  %st7   0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  49   49  
  50   50  SSE Control State
  51   51  mxcsr  0x1f80 (IM|DM|ZM|OM|UM|PM|RTN)
  52   52  xcp    0x0000 (RTN)

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX