--- old/usr/src/test/os-tests/tests/xsave/data/mdb_xregs.ymm.32.man.txt
          +++ new/usr/src/test/os-tests/tests/xsave/data/mdb_xregs.ymm.32.man.txt

   1    1  ()                                                                          ()
   2    2  
   3    3  x86 FPU with 256-bit %ymm registers xcr0            0x7 xfd             0x0
   4    4  xstate_bv       0x7 xcomp_bv        0x0
   5    5  
   6    6  %ymm0  [255:128] 0x12900929 12900928 12900927 12900926 %xmm0  [127:0]
   7    7  0x12900925 12900924 12900923 12900922
   8    8  
   9    9  %ymm1  [255:128] 0x12900931 12900930 1290092f 1290092e %xmm1  [127:0]
  10   10  0x1290092d 1290092c 1290092b 1290092a
  11   11  
  12   12  %ymm2  [255:128] 0x12900939 12900938 12900937 12900936 %xmm2  [127:0]
  13   13  0x12900935 12900934 12900933 12900932
  14   14  
  15   15  %ymm3  [255:128] 0x12900941 12900940 1290093f 1290093e %xmm3  [127:0]
  16   16  0x1290093d 1290093c 1290093b 1290093a
  17   17  
  18   18  %ymm4  [255:128] 0x12900949 12900948 12900947 12900946 %xmm4  [127:0]
  19   19  0x12900945 12900944 12900943 12900942
  20   20  
  21   21  %ymm5  [255:128] 0x12900951 12900950 1290094f 1290094e %xmm5  [127:0]
  22   22  0x1290094d 1290094c 1290094b 1290094a
  23   23  
  24   24  %ymm6  [255:128] 0x12900959 12900958 12900957 12900956 %xmm6  [127:0]
  25   25  0x12900955 12900954 12900953 12900952
  26   26  
  27   27  %ymm7  [255:128] 0x12900961 12900960 1290095f 1290095e %xmm7  [127:0]
  28   28  0x1290095d 1290095c 1290095b 1290095a
  29   29  
  30   30  387 and FP Control State cw     0x137f (IM|DM|ZM|OM|UM|PM|SIG64|RTN|A) sw
  31   31  0x0000 (TOP=0t0) (0) xcp sw 0x0000 (0)
  32   32  
  33   33  ipoff  0 cssel  0x43 dtoff  0 dtsel  0x4b
  34   34  
  35   35  %st0   0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st1
  36   36  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st2
  37   37  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st3
  38   38  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st4
  39   39  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st5
  40   40  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st6
  41   41  0x0000.0000000000000000 = +0.0000000000000000e+00 empty %st7
  42   42  0x0000.0000000000000000 = +0.0000000000000000e+00 empty
  43   43  
  44   44  SSE Control State mxcsr  0x1f80 (IM|DM|ZM|OM|UM|PM|RTN) xcp    0x0000 (RTN)
  45   45  
  46   46                                                                              ()

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX